sys/dev/drm/mga_drv.h

   1 /* mga_drv.h -- Private header for the Matrox G200/G400 driver -*- linux-c -*-
   2  * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
   3  *
   4  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
   5  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
   6  * All rights reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  25  * OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Gareth Hughes <gareth@valinux.com>
  29  *
  30  * $DragonFly: src/sys/dev/drm/mga_drv.h,v 1.1 2008/04/05 18:12:29 hasso Exp $
  31  */
  32
  33 #ifndef __MGA_DRV_H__
  34 #define __MGA_DRV_H__
  35
  36 /* General customization:
  37  */
  38
  39 #define DRIVER_AUTHOR           "Gareth Hughes, VA Linux Systems Inc."
  40
  41 #define DRIVER_NAME             "mga"
  42 #define DRIVER_DESC             "Matrox G200/G400"
  43 #define DRIVER_DATE             "20060319"
  44
  45 #define DRIVER_MAJOR            3
  46 #define DRIVER_MINOR            2
  47 #define DRIVER_PATCHLEVEL       2
  48
  49 typedef struct drm_mga_primary_buffer {
  50         u8 *start;
  51         u8 *end;
  52         int size;
  53
  54         u32 tail;
  55         int space;
  56         volatile long wrapped;
  57
  58         volatile u32 *status;
  59
  60         u32 last_flush;
  61         u32 last_wrap;
  62
  63         u32 high_mark;
  64 } drm_mga_primary_buffer_t;
  65
  66 typedef struct drm_mga_freelist {
  67         struct drm_mga_freelist *next;
  68         struct drm_mga_freelist *prev;
  69         drm_mga_age_t age;
  70         struct drm_buf *buf;
  71 } drm_mga_freelist_t;
  72
  73 typedef struct {
  74         drm_mga_freelist_t *list_entry;
  75         int discard;
  76         int dispatched;
  77 } drm_mga_buf_priv_t;
  78
  79 typedef struct drm_mga_private {
  80         drm_mga_primary_buffer_t prim;
  81         drm_mga_sarea_t *sarea_priv;
  82
  83         drm_mga_freelist_t *head;
  84         drm_mga_freelist_t *tail;
  85
  86         unsigned int warp_pipe;
  87         unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES];
  88
  89         int chipset;
  90         int usec_timeout;
  91
  92         /**
  93          * If set, the new DMA initialization sequence was used.  This is
  94          * primarilly used to select how the driver should uninitialized its
  95          * internal DMA structures.
  96          */
  97         int used_new_dma_init;
  98
  99         /**
 100          * If AGP memory is used for DMA buffers, this will be the value
 101          * \c MGA_PAGPXFER.  Otherwise, it will be zero (for a PCI transfer).
 102          */
 103         u32 dma_access;
 104
 105         /**
 106          * If AGP memory is used for DMA buffers, this will be the value
 107          * \c MGA_WAGP_ENABLE.  Otherwise, it will be zero (for a PCI
 108          * transfer).
 109          */
 110         u32 wagp_enable;
 111
 112         /**
 113          * \name MMIO region parameters.
 114          *
 115          * \sa drm_mga_private_t::mmio
 116          */
 117         /*@{*/
 118         u32 mmio_base;             /**< Bus address of base of MMIO. */
 119         u32 mmio_size;             /**< Size of the MMIO region. */
 120         /*@}*/
 121
 122         u32 clear_cmd;
 123         u32 maccess;
 124
 125         wait_queue_head_t fence_queue;
 126         atomic_t last_fence_retired;
 127         u32 next_fence_to_post;
 128
 129         unsigned int fb_cpp;
 130         unsigned int front_offset;
 131         unsigned int front_pitch;
 132         unsigned int back_offset;
 133         unsigned int back_pitch;
 134
 135         unsigned int depth_cpp;
 136         unsigned int depth_offset;
 137         unsigned int depth_pitch;
 138
 139         unsigned int texture_offset;
 140         unsigned int texture_size;
 141
 142         drm_local_map_t *sarea;
 143         drm_local_map_t *mmio;
 144         drm_local_map_t *status;
 145         drm_local_map_t *warp;
 146         drm_local_map_t *primary;
 147         drm_local_map_t *agp_textures;
 148
 149         unsigned long agp_handle;
 150         unsigned int agp_size;
 151 } drm_mga_private_t;
 152
 153 extern struct drm_ioctl_desc mga_ioctls[];
 154 extern int mga_max_ioctl;
 155
 156                                 /* mga_dma.c */
 157 extern int mga_dma_bootstrap(struct drm_device *dev, void *data,
 158                              struct drm_file *file_priv);
 159 extern int mga_dma_init(struct drm_device *dev, void *data,
 160                         struct drm_file *file_priv);
 161 extern int mga_dma_flush(struct drm_device *dev, void *data,
 162                          struct drm_file *file_priv);
 163 extern int mga_dma_reset(struct drm_device *dev, void *data,
 164                          struct drm_file *file_priv);
 165 extern int mga_dma_buffers(struct drm_device *dev, void *data,
 166                            struct drm_file *file_priv);
 167 extern int mga_driver_load(struct drm_device *dev, unsigned long flags);
 168 extern int mga_driver_unload(struct drm_device * dev);
 169 extern void mga_driver_lastclose(struct drm_device * dev);
 170 extern int mga_driver_dma_quiescent(struct drm_device * dev);
 171
 172 extern int mga_do_wait_for_idle(drm_mga_private_t * dev_priv);
 173
 174 extern void mga_do_dma_flush(drm_mga_private_t * dev_priv);
 175 extern void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv);
 176 extern void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv);
 177
 178 extern int mga_freelist_put(struct drm_device * dev, struct drm_buf * buf);
 179
 180                                 /* mga_warp.c */
 181 extern unsigned int mga_warp_microcode_size(const drm_mga_private_t * dev_priv);
 182 extern int mga_warp_install_microcode(drm_mga_private_t * dev_priv);
 183 extern int mga_warp_init(drm_mga_private_t * dev_priv);
 184
 185                                 /* mga_irq.c */
 186 extern int mga_driver_fence_wait(struct drm_device * dev, unsigned int *sequence);
 187 extern int mga_driver_vblank_wait(struct drm_device * dev, unsigned int *sequence);
 188 extern irqreturn_t mga_driver_irq_handler(DRM_IRQ_ARGS);
 189 extern void mga_driver_irq_preinstall(struct drm_device * dev);
 190 extern void mga_driver_irq_postinstall(struct drm_device * dev);
 191 extern void mga_driver_irq_uninstall(struct drm_device * dev);
 192 extern long mga_compat_ioctl(struct file *filp, unsigned int cmd,
 193                              unsigned long arg);
 194
 195 #define mga_flush_write_combine()       DRM_WRITEMEMORYBARRIER()
 196
 197 #if defined(__linux__) && defined(__alpha__)
 198 #define MGA_BASE( reg )         ((unsigned long)(dev_priv->mmio->handle))
 199 #define MGA_ADDR( reg )         (MGA_BASE(reg) + reg)
 200
 201 #define MGA_DEREF( reg )        *(volatile u32 *)MGA_ADDR( reg )
 202 #define MGA_DEREF8( reg )       *(volatile u8 *)MGA_ADDR( reg )
 203
 204 #define MGA_READ( reg )         (_MGA_READ((u32 *)MGA_ADDR(reg)))
 205 #define MGA_READ8( reg )        (_MGA_READ((u8 *)MGA_ADDR(reg)))
 206 #define MGA_WRITE( reg, val )   do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0)
 207 #define MGA_WRITE8( reg, val )  do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8( reg ) = val; } while (0)
 208
 209 static inline u32 _MGA_READ(u32 * addr)
 210 {
 211         DRM_MEMORYBARRIER();
 212         return *(volatile u32 *)addr;
 213 }
 214 #else
 215 #define MGA_READ8( reg )        DRM_READ8(dev_priv->mmio, (reg))
 216 #define MGA_READ( reg )         DRM_READ32(dev_priv->mmio, (reg))
 217 #define MGA_WRITE8( reg, val )  DRM_WRITE8(dev_priv->mmio, (reg), (val))
 218 #define MGA_WRITE( reg, val )   DRM_WRITE32(dev_priv->mmio, (reg), (val))
 219 #endif
 220
 221 #define DWGREG0         0x1c00
 222 #define DWGREG0_END     0x1dff
 223 #define DWGREG1         0x2c00
 224 #define DWGREG1_END     0x2dff
 225
 226 #define ISREG0(r)       (r >= DWGREG0 && r <= DWGREG0_END)
 227 #define DMAREG0(r)      (u8)((r - DWGREG0) >> 2)
 228 #define DMAREG1(r)      (u8)(((r - DWGREG1) >> 2) | 0x80)
 229 #define DMAREG(r)       (ISREG0(r) ? DMAREG0(r) : DMAREG1(r))
 230
 231 /* ================================================================
 232  * Helper macross...
 233  */
 234
 235 #define MGA_EMIT_STATE( dev_priv, dirty )                               \
 236 do {                                                                    \
 237         if ( (dirty) & ~MGA_UPLOAD_CLIPRECTS ) {                        \
 238                 if ( dev_priv->chipset >= MGA_CARD_TYPE_G400 ) {        \
 239                         mga_g400_emit_state( dev_priv );                \
 240                 } else {                                                \
 241                         mga_g200_emit_state( dev_priv );                \
 242                 }                                                       \
 243         }                                                               \
 244 } while (0)
 245
 246 #define WRAP_TEST_WITH_RETURN( dev_priv )                               \
 247 do {                                                                    \
 248         if ( test_bit( 0, &dev_priv->prim.wrapped ) ) {                 \
 249                 if ( mga_is_idle( dev_priv ) ) {                        \
 250                         mga_do_dma_wrap_end( dev_priv );                \
 251                 } else if ( dev_priv->prim.space <                      \
 252                             dev_priv->prim.high_mark ) {                \
 253                         if ( MGA_DMA_DEBUG )                            \
 254                                 DRM_INFO( "wrap...\n");         \
 255                         return -EBUSY;                  \
 256                 }                                                       \
 257         }                                                               \
 258 } while (0)
 259
 260 #define WRAP_WAIT_WITH_RETURN( dev_priv )                               \
 261 do {                                                                    \
 262         if ( test_bit( 0, &dev_priv->prim.wrapped ) ) {                 \
 263                 if ( mga_do_wait_for_idle( dev_priv ) < 0 ) {           \
 264                         if ( MGA_DMA_DEBUG )                            \
 265                                 DRM_INFO( "wrap...\n");         \
 266                         return -EBUSY;                  \
 267                 }                                                       \
 268                 mga_do_dma_wrap_end( dev_priv );                        \
 269         }                                                               \
 270 } while (0)
 271
 272 /* ================================================================
 273  * Primary DMA command stream
 274  */
 275
 276 #define MGA_VERBOSE     0
 277
 278 #define DMA_LOCALS      unsigned int write; volatile u8 *prim;
 279
 280 #define DMA_BLOCK_SIZE  (5 * sizeof(u32))
 281
 282 #define BEGIN_DMA( n )                                                  \
 283 do {                                                                    \
 284         if ( MGA_VERBOSE ) {                                            \
 285                 DRM_INFO( "BEGIN_DMA( %d )\n", (n) );           \
 286                 DRM_INFO( "   space=0x%x req=0x%Zx\n",                  \
 287                           dev_priv->prim.space, (n) * DMA_BLOCK_SIZE ); \
 288         }                                                               \
 289         prim = dev_priv->prim.start;                                    \
 290         write = dev_priv->prim.tail;                                    \
 291 } while (0)
 292
 293 #define BEGIN_DMA_WRAP()                                                \
 294 do {                                                                    \
 295         if ( MGA_VERBOSE ) {                                            \
 296                 DRM_INFO( "BEGIN_DMA()\n" );                            \
 297                 DRM_INFO( "   space=0x%x\n", dev_priv->prim.space );    \
 298         }                                                               \
 299         prim = dev_priv->prim.start;                                    \
 300         write = dev_priv->prim.tail;                                    \
 301 } while (0)
 302
 303 #define ADVANCE_DMA()                                                   \
 304 do {                                                                    \
 305         dev_priv->prim.tail = write;                                    \
 306         if ( MGA_VERBOSE ) {                                            \
 307                 DRM_INFO( "ADVANCE_DMA() tail=0x%05x sp=0x%x\n",        \
 308                           write, dev_priv->prim.space );                \
 309         }                                                               \
 310 } while (0)
 311
 312 #define FLUSH_DMA()                                                     \
 313 do {                                                                    \
 314         if ( 0 ) {                                                      \
 315                 DRM_INFO( "\n" );                                       \
 316                 DRM_INFO( "   tail=0x%06x head=0x%06lx\n",              \
 317                           dev_priv->prim.tail,                          \
 318                           MGA_READ( MGA_PRIMADDRESS ) -                 \
 319                           dev_priv->primary->offset );                  \
 320         }                                                               \
 321         if ( !test_bit( 0, &dev_priv->prim.wrapped ) ) {                \
 322                 if ( dev_priv->prim.space <                             \
 323                      dev_priv->prim.high_mark ) {                       \
 324                         mga_do_dma_wrap_start( dev_priv );              \
 325                 } else {                                                \
 326                         mga_do_dma_flush( dev_priv );                   \
 327                 }                                                       \
 328         }                                                               \
 329 } while (0)
 330
 331 /* Never use this, always use DMA_BLOCK(...) for primary DMA output.
 332  */
 333 #define DMA_WRITE( offset, val )                                        \
 334 do {                                                                    \
 335         if ( MGA_VERBOSE ) {                                            \
 336                 DRM_INFO( "   DMA_WRITE( 0x%08x ) at 0x%04Zx\n",        \
 337                           (u32)(val), write + (offset) * sizeof(u32) ); \
 338         }                                                               \
 339         *(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \
 340 } while (0)
 341
 342 #define DMA_BLOCK( reg0, val0, reg1, val1, reg2, val2, reg3, val3 )     \
 343 do {                                                                    \
 344         DMA_WRITE( 0, ((DMAREG( reg0 ) << 0) |                          \
 345                        (DMAREG( reg1 ) << 8) |                          \
 346                        (DMAREG( reg2 ) << 16) |                         \
 347                        (DMAREG( reg3 ) << 24)) );                       \
 348         DMA_WRITE( 1, val0 );                                           \
 349         DMA_WRITE( 2, val1 );                                           \
 350         DMA_WRITE( 3, val2 );                                           \
 351         DMA_WRITE( 4, val3 );                                           \
 352         write += DMA_BLOCK_SIZE;                                        \
 353 } while (0)
 354
 355 /* Buffer aging via primary DMA stream head pointer.
 356  */
 357
 358 #define SET_AGE( age, h, w )                                            \
 359 do {                                                                    \
 360         (age)->head = h;                                                \
 361         (age)->wrap = w;                                                \
 362 } while (0)
 363
 364 #define TEST_AGE( age, h, w )           ( (age)->wrap < w ||            \
 365                                           ( (age)->wrap == w &&         \
 366                                             (age)->head < h ) )
 367
 368 #define AGE_BUFFER( buf_priv )                                          \
 369 do {                                                                    \
 370         drm_mga_freelist_t *entry = (buf_priv)->list_entry;             \
 371         if ( (buf_priv)->dispatched ) {                                 \
 372                 entry->age.head = (dev_priv->prim.tail +                \
 373                                    dev_priv->primary->offset);          \
 374                 entry->age.wrap = dev_priv->sarea_priv->last_wrap;      \
 375         } else {                                                        \
 376                 entry->age.head = 0;                                    \
 377                 entry->age.wrap = 0;                                    \
 378         }                                                               \
 379 } while (0)
 380
 381 #define MGA_ENGINE_IDLE_MASK            (MGA_SOFTRAPEN |                \
 382                                          MGA_DWGENGSTS |                \
 383                                          MGA_ENDPRDMASTS)
 384 #define MGA_DMA_IDLE_MASK               (MGA_SOFTRAPEN |                \
 385                                          MGA_ENDPRDMASTS)
 386
 387 #define MGA_DMA_DEBUG                   0
 388
 389 /* A reduced set of the mga registers.
 390  */
 391 #define MGA_CRTC_INDEX                  0x1fd4
 392 #define MGA_CRTC_DATA                   0x1fd5
 393
 394 /* CRTC11 */
 395 #define MGA_VINTCLR                     (1 << 4)
 396 #define MGA_VINTEN                      (1 << 5)
 397
 398 #define MGA_ALPHACTRL                   0x2c7c
 399 #define MGA_AR0                         0x1c60
 400 #define MGA_AR1                         0x1c64
 401 #define MGA_AR2                         0x1c68
 402 #define MGA_AR3                         0x1c6c
 403 #define MGA_AR4                         0x1c70
 404 #define MGA_AR5                         0x1c74
 405 #define MGA_AR6                         0x1c78
 406
 407 #define MGA_CXBNDRY                     0x1c80
 408 #define MGA_CXLEFT                      0x1ca0
 409 #define MGA_CXRIGHT                     0x1ca4
 410
 411 #define MGA_DMAPAD                      0x1c54
 412 #define MGA_DSTORG                      0x2cb8
 413 #define MGA_DWGCTL                      0x1c00
 414 #       define MGA_OPCOD_MASK                   (15 << 0)
 415 #       define MGA_OPCOD_TRAP                   (4 << 0)
 416 #       define MGA_OPCOD_TEXTURE_TRAP           (6 << 0)
 417 #       define MGA_OPCOD_BITBLT                 (8 << 0)
 418 #       define MGA_OPCOD_ILOAD                  (9 << 0)
 419 #       define MGA_ATYPE_MASK                   (7 << 4)
 420 #       define MGA_ATYPE_RPL                    (0 << 4)
 421 #       define MGA_ATYPE_RSTR                   (1 << 4)
 422 #       define MGA_ATYPE_ZI                     (3 << 4)
 423 #       define MGA_ATYPE_BLK                    (4 << 4)
 424 #       define MGA_ATYPE_I                      (7 << 4)
 425 #       define MGA_LINEAR                       (1 << 7)
 426 #       define MGA_ZMODE_MASK                   (7 << 8)
 427 #       define MGA_ZMODE_NOZCMP                 (0 << 8)
 428 #       define MGA_ZMODE_ZE                     (2 << 8)
 429 #       define MGA_ZMODE_ZNE                    (3 << 8)
 430 #       define MGA_ZMODE_ZLT                    (4 << 8)
 431 #       define MGA_ZMODE_ZLTE                   (5 << 8)
 432 #       define MGA_ZMODE_ZGT                    (6 << 8)
 433 #       define MGA_ZMODE_ZGTE                   (7 << 8)
 434 #       define MGA_SOLID                        (1 << 11)
 435 #       define MGA_ARZERO                       (1 << 12)
 436 #       define MGA_SGNZERO                      (1 << 13)
 437 #       define MGA_SHIFTZERO                    (1 << 14)
 438 #       define MGA_BOP_MASK                     (15 << 16)
 439 #       define MGA_BOP_ZERO                     (0 << 16)
 440 #       define MGA_BOP_DST                      (10 << 16)
 441 #       define MGA_BOP_SRC                      (12 << 16)
 442 #       define MGA_BOP_ONE                      (15 << 16)
 443 #       define MGA_TRANS_SHIFT                  20
 444 #       define MGA_TRANS_MASK                   (15 << 20)
 445 #       define MGA_BLTMOD_MASK                  (15 << 25)
 446 #       define MGA_BLTMOD_BMONOLEF              (0 << 25)
 447 #       define MGA_BLTMOD_BMONOWF               (4 << 25)
 448 #       define MGA_BLTMOD_PLAN                  (1 << 25)
 449 #       define MGA_BLTMOD_BFCOL                 (2 << 25)
 450 #       define MGA_BLTMOD_BU32BGR               (3 << 25)
 451 #       define MGA_BLTMOD_BU32RGB               (7 << 25)
 452 #       define MGA_BLTMOD_BU24BGR               (11 << 25)
 453 #       define MGA_BLTMOD_BU24RGB               (15 << 25)
 454 #       define MGA_PATTERN                      (1 << 29)
 455 #       define MGA_TRANSC                       (1 << 30)
 456 #       define MGA_CLIPDIS                      (1 << 31)
 457 #define MGA_DWGSYNC                     0x2c4c
 458
 459 #define MGA_FCOL                        0x1c24
 460 #define MGA_FIFOSTATUS                  0x1e10
 461 #define MGA_FOGCOL                      0x1cf4
 462 #define MGA_FXBNDRY                     0x1c84
 463 #define MGA_FXLEFT                      0x1ca8
 464 #define MGA_FXRIGHT                     0x1cac
 465
 466 #define MGA_ICLEAR                      0x1e18
 467 #       define MGA_SOFTRAPICLR                  (1 << 0)
 468 #       define MGA_VLINEICLR                    (1 << 5)
 469 #define MGA_IEN                         0x1e1c
 470 #       define MGA_SOFTRAPIEN                   (1 << 0)
 471 #       define MGA_VLINEIEN                     (1 << 5)
 472
 473 #define MGA_LEN                         0x1c5c
 474
 475 #define MGA_MACCESS                     0x1c04
 476
 477 #define MGA_PITCH                       0x1c8c
 478 #define MGA_PLNWT                       0x1c1c
 479 #define MGA_PRIMADDRESS                 0x1e58
 480 #       define MGA_DMA_GENERAL                  (0 << 0)
 481 #       define MGA_DMA_BLIT                     (1 << 0)
 482 #       define MGA_DMA_VECTOR                   (2 << 0)
 483 #       define MGA_DMA_VERTEX                   (3 << 0)
 484 #define MGA_PRIMEND                     0x1e5c
 485 #       define MGA_PRIMNOSTART                  (1 << 0)
 486 #       define MGA_PAGPXFER                     (1 << 1)
 487 #define MGA_PRIMPTR                     0x1e50
 488 #       define MGA_PRIMPTREN0                   (1 << 0)
 489 #       define MGA_PRIMPTREN1                   (1 << 1)
 490
 491 #define MGA_RST                         0x1e40
 492 #       define MGA_SOFTRESET                    (1 << 0)
 493 #       define MGA_SOFTEXTRST                   (1 << 1)
 494
 495 #define MGA_SECADDRESS                  0x2c40
 496 #define MGA_SECEND                      0x2c44
 497 #define MGA_SETUPADDRESS                0x2cd0
 498 #define MGA_SETUPEND                    0x2cd4
 499 #define MGA_SGN                         0x1c58
 500 #define MGA_SOFTRAP                     0x2c48
 501 #define MGA_SRCORG                      0x2cb4
 502 #       define MGA_SRMMAP_MASK                  (1 << 0)
 503 #       define MGA_SRCMAP_FB                    (0 << 0)
 504 #       define MGA_SRCMAP_SYSMEM                (1 << 0)
 505 #       define MGA_SRCACC_MASK                  (1 << 1)
 506 #       define MGA_SRCACC_PCI                   (0 << 1)
 507 #       define MGA_SRCACC_AGP                   (1 << 1)
 508 #define MGA_STATUS                      0x1e14
 509 #       define MGA_SOFTRAPEN                    (1 << 0)
 510 #       define MGA_VSYNCPEN                     (1 << 4)
 511 #       define MGA_VLINEPEN                     (1 << 5)
 512 #       define MGA_DWGENGSTS                    (1 << 16)
 513 #       define MGA_ENDPRDMASTS                  (1 << 17)
 514 #define MGA_STENCIL                     0x2cc8
 515 #define MGA_STENCILCTL                  0x2ccc
 516
 517 #define MGA_TDUALSTAGE0                 0x2cf8
 518 #define MGA_TDUALSTAGE1                 0x2cfc
 519 #define MGA_TEXBORDERCOL                0x2c5c
 520 #define MGA_TEXCTL                      0x2c30
 521 #define MGA_TEXCTL2                     0x2c3c
 522 #       define MGA_DUALTEX                      (1 << 7)
 523 #       define MGA_G400_TC2_MAGIC               (1 << 15)
 524 #       define MGA_MAP1_ENABLE                  (1 << 31)
 525 #define MGA_TEXFILTER                   0x2c58
 526 #define MGA_TEXHEIGHT                   0x2c2c
 527 #define MGA_TEXORG                      0x2c24
 528 #       define MGA_TEXORGMAP_MASK               (1 << 0)
 529 #       define MGA_TEXORGMAP_FB                 (0 << 0)
 530 #       define MGA_TEXORGMAP_SYSMEM             (1 << 0)
 531 #       define MGA_TEXORGACC_MASK               (1 << 1)
 532 #       define MGA_TEXORGACC_PCI                (0 << 1)
 533 #       define MGA_TEXORGACC_AGP                (1 << 1)
 534 #define MGA_TEXORG1                     0x2ca4
 535 #define MGA_TEXORG2                     0x2ca8
 536 #define MGA_TEXORG3                     0x2cac
 537 #define MGA_TEXORG4                     0x2cb0
 538 #define MGA_TEXTRANS                    0x2c34
 539 #define MGA_TEXTRANSHIGH                0x2c38
 540 #define MGA_TEXWIDTH                    0x2c28
 541
 542 #define MGA_WACCEPTSEQ                  0x1dd4
 543 #define MGA_WCODEADDR                   0x1e6c
 544 #define MGA_WFLAG                       0x1dc4
 545 #define MGA_WFLAG1                      0x1de0
 546 #define MGA_WFLAGNB                     0x1e64
 547 #define MGA_WFLAGNB1                    0x1e08
 548 #define MGA_WGETMSB                     0x1dc8
 549 #define MGA_WIADDR                      0x1dc0
 550 #define MGA_WIADDR2                     0x1dd8
 551 #       define MGA_WMODE_SUSPEND                (0 << 0)
 552 #       define MGA_WMODE_RESUME                 (1 << 0)
 553 #       define MGA_WMODE_JUMP                   (2 << 0)
 554 #       define MGA_WMODE_START                  (3 << 0)
 555 #       define MGA_WAGP_ENABLE                  (1 << 2)
 556 #define MGA_WMISC                       0x1e70
 557 #       define MGA_WUCODECACHE_ENABLE           (1 << 0)
 558 #       define MGA_WMASTER_ENABLE               (1 << 1)
 559 #       define MGA_WCACHEFLUSH_ENABLE           (1 << 3)
 560 #define MGA_WVRTXSZ                     0x1dcc
 561
 562 #define MGA_YBOT                        0x1c9c
 563 #define MGA_YDST                        0x1c90
 564 #define MGA_YDSTLEN                     0x1c88
 565 #define MGA_YDSTORG                     0x1c94
 566 #define MGA_YTOP                        0x1c98
 567
 568 #define MGA_ZORG                        0x1c0c
 569
 570 /* This finishes the current batch of commands
 571  */
 572 #define MGA_EXEC                        0x0100
 573
 574 /* AGP PLL encoding (for G200 only).
 575  */
 576 #define MGA_AGP_PLL                     0x1e4c
 577 #       define MGA_AGP2XPLL_DISABLE             (0 << 0)
 578 #       define MGA_AGP2XPLL_ENABLE              (1 << 0)
 579
 580 /* Warp registers
 581  */
 582 #define MGA_WR0                         0x2d00
 583 #define MGA_WR1                         0x2d04
 584 #define MGA_WR2                         0x2d08
 585 #define MGA_WR3                         0x2d0c
 586 #define MGA_WR4                         0x2d10
 587 #define MGA_WR5                         0x2d14
 588 #define MGA_WR6                         0x2d18
 589 #define MGA_WR7                         0x2d1c
 590 #define MGA_WR8                         0x2d20
 591 #define MGA_WR9                         0x2d24
 592 #define MGA_WR10                        0x2d28
 593 #define MGA_WR11                        0x2d2c
 594 #define MGA_WR12                        0x2d30
 595 #define MGA_WR13                        0x2d34
 596 #define MGA_WR14                        0x2d38
 597 #define MGA_WR15                        0x2d3c
 598 #define MGA_WR16                        0x2d40
 599 #define MGA_WR17                        0x2d44
 600 #define MGA_WR18                        0x2d48
 601 #define MGA_WR19                        0x2d4c
 602 #define MGA_WR20                        0x2d50
 603 #define MGA_WR21                        0x2d54
 604 #define MGA_WR22                        0x2d58
 605 #define MGA_WR23                        0x2d5c
 606 #define MGA_WR24                        0x2d60
 607 #define MGA_WR25                        0x2d64
 608 #define MGA_WR26                        0x2d68
 609 #define MGA_WR27                        0x2d6c
 610 #define MGA_WR28                        0x2d70
 611 #define MGA_WR29                        0x2d74
 612 #define MGA_WR30                        0x2d78
 613 #define MGA_WR31                        0x2d7c
 614 #define MGA_WR32                        0x2d80
 615 #define MGA_WR33                        0x2d84
 616 #define MGA_WR34                        0x2d88
 617 #define MGA_WR35                        0x2d8c
 618 #define MGA_WR36                        0x2d90
 619 #define MGA_WR37                        0x2d94
 620 #define MGA_WR38                        0x2d98
 621 #define MGA_WR39                        0x2d9c
 622 #define MGA_WR40                        0x2da0
 623 #define MGA_WR41                        0x2da4
 624 #define MGA_WR42                        0x2da8
 625 #define MGA_WR43                        0x2dac
 626 #define MGA_WR44                        0x2db0
 627 #define MGA_WR45                        0x2db4
 628 #define MGA_WR46                        0x2db8
 629 #define MGA_WR47                        0x2dbc
 630 #define MGA_WR48                        0x2dc0
 631 #define MGA_WR49                        0x2dc4
 632 #define MGA_WR50                        0x2dc8
 633 #define MGA_WR51                        0x2dcc
 634 #define MGA_WR52                        0x2dd0
 635 #define MGA_WR53                        0x2dd4
 636 #define MGA_WR54                        0x2dd8
 637 #define MGA_WR55                        0x2ddc
 638 #define MGA_WR56                        0x2de0
 639 #define MGA_WR57                        0x2de4
 640 #define MGA_WR58                        0x2de8
 641 #define MGA_WR59                        0x2dec
 642 #define MGA_WR60                        0x2df0
 643 #define MGA_WR61                        0x2df4
 644 #define MGA_WR62                        0x2df8
 645 #define MGA_WR63                        0x2dfc
 646 #       define MGA_G400_WR_MAGIC                (1 << 6)
 647 #       define MGA_G400_WR56_MAGIC              0x46480000      /* 12800.0f */
 648
 649 #define MGA_ILOAD_ALIGN         64
 650 #define MGA_ILOAD_MASK          (MGA_ILOAD_ALIGN - 1)
 651
 652 #define MGA_DWGCTL_FLUSH        (MGA_OPCOD_TEXTURE_TRAP |               \
 653                                  MGA_ATYPE_I |                          \
 654                                  MGA_ZMODE_NOZCMP |                     \
 655                                  MGA_ARZERO |                           \
 656                                  MGA_SGNZERO |                          \
 657                                  MGA_BOP_SRC |                          \
 658                                  (15 << MGA_TRANS_SHIFT))
 659
 660 #define MGA_DWGCTL_CLEAR        (MGA_OPCOD_TRAP |                       \
 661                                  MGA_ZMODE_NOZCMP |                     \
 662                                  MGA_SOLID |                            \
 663                                  MGA_ARZERO |                           \
 664                                  MGA_SGNZERO |                          \
 665                                  MGA_SHIFTZERO |                        \
 666                                  MGA_BOP_SRC |                          \
 667                                  (0 << MGA_TRANS_SHIFT) |               \
 668                                  MGA_BLTMOD_BMONOLEF |                  \
 669                                  MGA_TRANSC |                           \
 670                                  MGA_CLIPDIS)
 671
 672 #define MGA_DWGCTL_COPY         (MGA_OPCOD_BITBLT |                     \
 673                                  MGA_ATYPE_RPL |                        \
 674                                  MGA_SGNZERO |                          \
 675                                  MGA_SHIFTZERO |                        \
 676                                  MGA_BOP_SRC |                          \
 677                                  (0 << MGA_TRANS_SHIFT) |               \
 678                                  MGA_BLTMOD_BFCOL |                     \
 679                                  MGA_CLIPDIS)
 680
 681 /* Simple idle test.
 682  */
 683 static __inline__ int mga_is_idle(drm_mga_private_t * dev_priv)
 684 {
 685         u32 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
 686         return (status == MGA_ENDPRDMASTS);
 687 }
 688
 689 #endif