2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/kernel.h>
33 #include <sys/sysctl.h>
34 #include <sys/malloc.h>
35 #include <sys/memrange.h>
36 #include <sys/cons.h> /* cngetc() */
37 #include <sys/machintr.h>
39 #include <sys/mplock2.h>
42 #include <vm/vm_param.h>
44 #include <vm/vm_kern.h>
45 #include <vm/vm_extern.h>
47 #include <vm/vm_map.h>
53 #include <machine/smp.h>
54 #include <machine_base/apic/apicreg.h>
55 #include <machine/atomic.h>
56 #include <machine/cpufunc.h>
57 #include <machine_base/apic/lapic.h>
58 #include <machine_base/apic/ioapic.h>
59 #include <machine/psl.h>
60 #include <machine/segments.h>
61 #include <machine/tss.h>
62 #include <machine/specialreg.h>
63 #include <machine/globaldata.h>
64 #include <machine/pmap_inval.h>
66 #include <machine/md_var.h> /* setidt() */
67 #include <machine_base/icu/icu.h> /* IPIs */
68 #include <machine_base/icu/icu_var.h>
69 #include <machine_base/apic/ioapic_abi.h>
70 #include <machine/intr_machdep.h> /* IPIs */
72 #define WARMBOOT_TARGET 0
73 #define WARMBOOT_OFF (KERNBASE + 0x0467)
74 #define WARMBOOT_SEG (KERNBASE + 0x0469)
76 #define CMOS_REG (0x70)
77 #define CMOS_DATA (0x71)
78 #define BIOS_RESET (0x0f)
79 #define BIOS_WARM (0x0a)
82 * this code MUST be enabled here and in mpboot.s.
83 * it follows the very early stages of AP boot by placing values in CMOS ram.
84 * it NORMALLY will never be needed and thus the primitive method for enabling.
87 #if defined(CHECK_POINTS)
88 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
89 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
91 #define CHECK_INIT(D); \
92 CHECK_WRITE(0x34, (D)); \
93 CHECK_WRITE(0x35, (D)); \
94 CHECK_WRITE(0x36, (D)); \
95 CHECK_WRITE(0x37, (D)); \
96 CHECK_WRITE(0x38, (D)); \
97 CHECK_WRITE(0x39, (D));
99 #define CHECK_PRINT(S); \
100 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
109 #else /* CHECK_POINTS */
111 #define CHECK_INIT(D)
112 #define CHECK_PRINT(S)
114 #endif /* CHECK_POINTS */
117 * Values to send to the POST hardware.
119 #define MP_BOOTADDRESS_POST 0x10
120 #define MP_PROBE_POST 0x11
121 #define MPTABLE_PASS1_POST 0x12
123 #define MP_START_POST 0x13
124 #define MP_ENABLE_POST 0x14
125 #define MPTABLE_PASS2_POST 0x15
127 #define START_ALL_APS_POST 0x16
128 #define INSTALL_AP_TRAMP_POST 0x17
129 #define START_AP_POST 0x18
131 #define MP_ANNOUNCE_POST 0x19
133 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
134 int current_postcode;
136 /** XXX FIXME: what system files declare these??? */
137 extern struct region_descriptor r_gdt, r_idt;
139 int mp_naps; /* # of Applications processors */
143 extern int64_t tsc_offsets[];
145 #ifdef SMP /* APIC-IO */
146 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
149 /* AP uses this during bootstrap. Do not staticize. */
153 struct pcb stoppcbs[MAXCPU];
155 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
158 * Local data and functions.
161 static u_int boot_address;
162 static int mp_finish;
163 static int mp_finish_lapic;
165 static void mp_enable(u_int boot_addr);
167 static int start_all_aps(u_int boot_addr);
169 static void install_ap_tramp(u_int boot_addr);
171 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
172 static int smitest(void);
173 static void cpu_simple_setup(void);
175 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
176 static cpumask_t smp_lapic_mask = 1; /* which cpus have lapic been inited */
177 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
178 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
179 static u_int bootMP_size;
184 * Calculate usable address in base memory for AP trampoline code.
187 mp_bootaddress(u_int basemem)
189 POSTCODE(MP_BOOTADDRESS_POST);
191 base_memory = basemem;
193 bootMP_size = mptramp_end - mptramp_start;
194 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
195 if (((basemem * 1024) - boot_address) < bootMP_size)
196 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
197 /* 3 levels of page table pages */
198 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
200 return mptramp_pagetables;
204 * Startup the SMP processors.
209 POSTCODE(MP_START_POST);
210 mp_enable(boot_address);
215 * Print various information about the SMP system hardware and setup.
222 POSTCODE(MP_ANNOUNCE_POST);
224 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
225 kprintf(" cpu0 (BSP): apic id: %2d\n", CPUID_TO_APICID(0));
226 for (x = 1; x <= mp_naps; ++x)
227 kprintf(" cpu%d (AP): apic id: %2d\n", x, CPUID_TO_APICID(x));
230 kprintf(" Warning: APIC I/O disabled\n");
234 * AP cpu's call this to sync up protected mode.
236 * WARNING! %gs is not set up on entry. This routine sets up %gs.
242 int x, myid = bootAP;
244 struct mdglobaldata *md;
245 struct privatespace *ps;
247 ps = &CPU_prvspace[myid];
249 gdt_segs[GPROC0_SEL].ssd_base =
250 (long) &ps->mdglobaldata.gd_common_tss;
251 ps->mdglobaldata.mi.gd_prvspace = ps;
253 /* We fill the 32-bit segment descriptors */
254 for (x = 0; x < NGDT; x++) {
255 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
256 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
258 /* And now a 64-bit one */
259 ssdtosyssd(&gdt_segs[GPROC0_SEL],
260 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
262 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
263 r_gdt.rd_base = (long) &gdt[myid * NGDT];
264 lgdt(&r_gdt); /* does magic intra-segment return */
266 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
267 wrmsr(MSR_FSBASE, 0); /* User value */
268 wrmsr(MSR_GSBASE, (u_int64_t)ps);
269 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
275 mdcpu->gd_currentldt = _default_ldt;
278 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
279 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
281 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
283 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
285 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
287 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
288 md->gd_common_tssd = *md->gd_tss_gdt;
290 /* double fault stack */
291 md->gd_common_tss.tss_ist1 =
292 (long)&md->mi.gd_prvspace->idlestack[
293 sizeof(md->mi.gd_prvspace->idlestack)];
298 * Set to a known state:
299 * Set by mpboot.s: CR0_PG, CR0_PE
300 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
303 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
306 /* Set up the fast syscall stuff */
307 msr = rdmsr(MSR_EFER) | EFER_SCE;
308 wrmsr(MSR_EFER, msr);
309 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
310 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
311 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
312 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
313 wrmsr(MSR_STAR, msr);
314 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
316 pmap_set_opt(); /* PSE/4MB pages, etc */
318 /* Initialize the PAT MSR. */
322 /* set up CPU registers and state */
325 /* set up SSE/NX registers */
328 /* set up FPU state on the AP */
329 npxinit(__INITIAL_NPXCW__);
331 /* disable the APIC, just to be SURE */
332 lapic->svr &= ~APIC_SVR_ENABLE;
335 /*******************************************************************
336 * local functions and data
340 * start the SMP system
343 mp_enable(u_int boot_addr)
347 POSTCODE(MP_ENABLE_POST);
349 error = lapic_config();
353 icu_reinit_noioapic();
359 /* Initialize BSP's local APIC */
362 /* start each Application Processor */
363 start_all_aps(boot_addr);
366 error = ioapic_config();
369 icu_reinit_noioapic();
370 lapic_fixup_noioapic();
376 * start each AP in our list
379 start_all_aps(u_int boot_addr)
381 vm_offset_t va = boot_address + KERNBASE;
382 u_int64_t *pt4, *pt3, *pt2;
389 u_long mpbioswarmvec;
390 struct mdglobaldata *gd;
391 struct privatespace *ps;
393 POSTCODE(START_ALL_APS_POST);
395 /* install the AP 1st level boot code */
396 pmap_kenter(va, boot_address);
397 cpu_invlpg((void *)va); /* JG XXX */
398 bcopy(mptramp_start, (void *)va, bootMP_size);
400 /* Locate the page tables, they'll be below the trampoline */
401 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
402 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
403 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
405 /* Create the initial 1GB replicated page tables */
406 for (i = 0; i < 512; i++) {
407 /* Each slot of the level 4 pages points to the same level 3 page */
408 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
409 pt4[i] |= PG_V | PG_RW | PG_U;
411 /* Each slot of the level 3 pages points to the same level 2 page */
412 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
413 pt3[i] |= PG_V | PG_RW | PG_U;
415 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
416 pt2[i] = i * (2 * 1024 * 1024);
417 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
420 /* save the current value of the warm-start vector */
421 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
422 outb(CMOS_REG, BIOS_RESET);
423 mpbiosreason = inb(CMOS_DATA);
425 /* setup a vector to our boot code */
426 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
427 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
428 outb(CMOS_REG, BIOS_RESET);
429 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
432 * If we have a TSC we can figure out the SMI interrupt rate.
433 * The SMI does not necessarily use a constant rate. Spend
434 * up to 250ms trying to figure it out.
437 if (cpu_feature & CPUID_TSC) {
438 set_apic_timer(275000);
439 smilast = read_apic_timer();
440 for (x = 0; x < 20 && read_apic_timer(); ++x) {
441 smicount = smitest();
442 if (smibest == 0 || smilast - smicount < smibest)
443 smibest = smilast - smicount;
446 if (smibest > 250000)
449 smibest = smibest * (int64_t)1000000 /
450 get_apic_timer_frequency();
454 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
455 1000000 / smibest, smibest);
458 for (x = 1; x <= mp_naps; ++x) {
460 /* This is a bit verbose, it will go away soon. */
462 /* first page of AP's private space */
463 pg = x * x86_64_btop(sizeof(struct privatespace));
465 /* allocate new private data page(s) */
466 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
467 MDGLOBALDATA_BASEALLOC_SIZE);
469 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
470 bzero(gd, sizeof(*gd));
471 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
473 /* prime data page for it to use */
474 mi_gdinit(&gd->mi, x);
476 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
477 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
479 /* setup a vector to our boot code */
480 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
481 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
482 outb(CMOS_REG, BIOS_RESET);
483 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
486 * Setup the AP boot stack
488 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
491 /* attempt to start the Application Processor */
492 CHECK_INIT(99); /* setup checkpoints */
493 if (!start_ap(gd, boot_addr, smibest)) {
494 kprintf("\nAP #%d (PHY# %d) failed!\n",
495 x, CPUID_TO_APICID(x));
496 CHECK_PRINT("trace"); /* show checkpoints */
497 /* better panic as the AP may be running loose */
498 kprintf("panic y/n? [y] ");
502 CHECK_PRINT("trace"); /* show checkpoints */
505 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
508 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
509 for (shift = 0; (1 << shift) <= ncpus; ++shift)
512 ncpus2_shift = shift;
514 ncpus2_mask = ncpus2 - 1;
516 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
517 if ((1 << shift) < ncpus)
519 ncpus_fit = 1 << shift;
520 ncpus_fit_mask = ncpus_fit - 1;
522 /* build our map of 'other' CPUs */
523 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
524 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
525 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
527 /* restore the warmstart vector */
528 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
529 outb(CMOS_REG, BIOS_RESET);
530 outb(CMOS_DATA, mpbiosreason);
533 * NOTE! The idlestack for the BSP was setup by locore. Finish
534 * up, clean out the P==V mapping we did earlier.
539 * Wait all APs to finish initializing LAPIC
543 kprintf("SMP: Waiting APs LAPIC initialization\n");
544 if (cpu_feature & CPUID_TSC)
545 tsc0_offset = rdtsc();
548 while (smp_lapic_mask != smp_startup_mask) {
550 if (cpu_feature & CPUID_TSC)
551 tsc0_offset = rdtsc();
553 while (try_mplock() == 0)
556 /* number of APs actually started */
562 * load the 1st level AP boot code into base memory.
565 /* targets for relocation */
566 extern void bigJump(void);
567 extern void bootCodeSeg(void);
568 extern void bootDataSeg(void);
569 extern void MPentry(void);
571 extern u_int mp_gdtbase;
576 install_ap_tramp(u_int boot_addr)
579 int size = *(int *) ((u_long) & bootMP_size);
580 u_char *src = (u_char *) ((u_long) bootMP);
581 u_char *dst = (u_char *) boot_addr + KERNBASE;
582 u_int boot_base = (u_int) bootMP;
587 POSTCODE(INSTALL_AP_TRAMP_POST);
589 for (x = 0; x < size; ++x)
593 * modify addresses in code we just moved to basemem. unfortunately we
594 * need fairly detailed info about mpboot.s for this to work. changes
595 * to mpboot.s might require changes here.
598 /* boot code is located in KERNEL space */
599 dst = (u_char *) boot_addr + KERNBASE;
601 /* modify the lgdt arg */
602 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
603 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
605 /* modify the ljmp target for MPentry() */
606 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
607 *dst32 = ((u_int) MPentry - KERNBASE);
609 /* modify the target for boot code segment */
610 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
611 dst8 = (u_int8_t *) (dst16 + 1);
612 *dst16 = (u_int) boot_addr & 0xffff;
613 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
615 /* modify the target for boot data segment */
616 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
617 dst8 = (u_int8_t *) (dst16 + 1);
618 *dst16 = (u_int) boot_addr & 0xffff;
619 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
625 * This function starts the AP (application processor) identified
626 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
627 * to accomplish this. This is necessary because of the nuances
628 * of the different hardware we might encounter. It ain't pretty,
629 * but it seems to work.
631 * NOTE: eventually an AP gets to ap_init(), which is called just
632 * before the AP goes into the LWKT scheduler's idle loop.
635 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
639 u_long icr_lo, icr_hi;
641 POSTCODE(START_AP_POST);
643 /* get the PHYSICAL APIC ID# */
644 physical_cpu = CPUID_TO_APICID(gd->mi.gd_cpuid);
646 /* calculate the vector */
647 vector = (boot_addr >> 12) & 0xff;
649 /* We don't want anything interfering */
652 /* Make sure the target cpu sees everything */
656 * Try to detect when a SMI has occurred, wait up to 200ms.
658 * If a SMI occurs during an AP reset but before we issue
659 * the STARTUP command, the AP may brick. To work around
660 * this problem we hold off doing the AP startup until
661 * after we have detected the SMI. Hopefully another SMI
662 * will not occur before we finish the AP startup.
664 * Retries don't seem to help. SMIs have a window of opportunity
665 * and if USB->legacy keyboard emulation is enabled in the BIOS
666 * the interrupt rate can be quite high.
668 * NOTE: Don't worry about the L1 cache load, it might bloat
669 * ldelta a little but ndelta will be so huge when the SMI
670 * occurs the detection logic will still work fine.
673 set_apic_timer(200000);
678 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
679 * and running the target CPU. OR this INIT IPI might be latched (P5
680 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
683 * see apic/apicreg.h for icr bit definitions.
685 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
689 * Setup the address for the target AP. We can setup
690 * icr_hi once and then just trigger operations with
693 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
694 icr_hi |= (physical_cpu << 24);
695 icr_lo = lapic->icr_lo & 0xfff00000;
696 lapic->icr_hi = icr_hi;
699 * Do an INIT IPI: assert RESET
701 * Use edge triggered mode to assert INIT
703 lapic->icr_lo = icr_lo | 0x00004500;
704 while (lapic->icr_lo & APIC_DELSTAT_MASK)
708 * The spec calls for a 10ms delay but we may have to use a
709 * MUCH lower delay to avoid bricking an AP due to a fast SMI
710 * interrupt. We have other loops here too and dividing by 2
711 * doesn't seem to be enough even after subtracting 350us,
714 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
715 * interrupt was detected we use the full 10ms.
719 else if (smibest < 150 * 4 + 350)
721 else if ((smibest - 350) / 4 < 10000)
722 u_sleep((smibest - 350) / 4);
727 * Do an INIT IPI: deassert RESET
729 * Use level triggered mode to deassert. It is unclear
730 * why we need to do this.
732 lapic->icr_lo = icr_lo | 0x00008500;
733 while (lapic->icr_lo & APIC_DELSTAT_MASK)
735 u_sleep(150); /* wait 150us */
738 * Next we do a STARTUP IPI: the previous INIT IPI might still be
739 * latched, (P5 bug) this 1st STARTUP would then terminate
740 * immediately, and the previously started INIT IPI would continue. OR
741 * the previous INIT IPI has already run. and this STARTUP IPI will
742 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
745 lapic->icr_lo = icr_lo | 0x00000600 | vector;
746 while (lapic->icr_lo & APIC_DELSTAT_MASK)
748 u_sleep(200); /* wait ~200uS */
751 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
752 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
753 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
754 * recognized after hardware RESET or INIT IPI.
756 lapic->icr_lo = icr_lo | 0x00000600 | vector;
757 while (lapic->icr_lo & APIC_DELSTAT_MASK)
760 /* Resume normal operation */
763 /* wait for it to start, see ap_init() */
764 set_apic_timer(5000000);/* == 5 seconds */
765 while (read_apic_timer()) {
766 if (smp_startup_mask & CPUMASK(gd->mi.gd_cpuid))
767 return 1; /* return SUCCESS */
770 return 0; /* return FAILURE */
785 while (read_apic_timer()) {
787 for (count = 0; count < 100; ++count)
788 ntsc = rdtsc(); /* force loop to occur */
790 ndelta = ntsc - ltsc;
793 if (ndelta > ldelta * 2)
796 ldelta = ntsc - ltsc;
799 return(read_apic_timer());
803 * Synchronously flush the TLB on all other CPU's. The current cpu's
804 * TLB is not flushed. If the caller wishes to flush the current cpu's
805 * TLB the caller must call cpu_invltlb() in addition to smp_invltlb().
807 * NOTE: If for some reason we were unable to start all cpus we cannot
808 * safely use broadcast IPIs.
811 static cpumask_t smp_invltlb_req;
813 #define SMP_INVLTLB_DEBUG
819 struct mdglobaldata *md = mdcpu;
820 #ifdef SMP_INVLTLB_DEBUG
825 crit_enter_gd(&md->mi);
826 md->gd_invltlb_ret = 0;
827 ++md->mi.gd_cnt.v_smpinvltlb;
828 atomic_set_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
829 #ifdef SMP_INVLTLB_DEBUG
832 if (smp_startup_mask == smp_active_mask) {
833 all_but_self_ipi(XINVLTLB_OFFSET);
835 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
836 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
839 #ifdef SMP_INVLTLB_DEBUG
841 kprintf("smp_invltlb: ipi sent\n");
843 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
844 (smp_active_mask & ~md->mi.gd_cpumask)) {
847 #ifdef SMP_INVLTLB_DEBUG
849 if (++count == 400000000) {
851 kprintf("smp_invltlb: endless loop %08lx %08lx, "
852 "rflags %016jx retry",
853 (long)md->gd_invltlb_ret,
854 (long)smp_invltlb_req,
855 (intmax_t)read_rflags());
856 __asm __volatile ("sti");
861 int bcpu = BSFCPUMASK(~md->gd_invltlb_ret &
866 kprintf("bcpu %d\n", bcpu);
867 xgd = globaldata_find(bcpu);
868 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
871 Debugger("giving up");
877 atomic_clear_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
878 crit_exit_gd(&md->mi);
885 * Called from Xinvltlb assembly with interrupts disabled. We didn't
886 * bother to bump the critical section count or nested interrupt count
887 * so only do very low level operations here.
890 smp_invltlb_intr(void)
892 struct mdglobaldata *md = mdcpu;
893 struct mdglobaldata *omd;
898 mask = smp_invltlb_req;
901 cpu = BSFCPUMASK(mask);
902 mask &= ~CPUMASK(cpu);
903 omd = (struct mdglobaldata *)globaldata_find(cpu);
904 atomic_set_cpumask(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
911 * When called the executing CPU will send an IPI to all other CPUs
912 * requesting that they halt execution.
914 * Usually (but not necessarily) called with 'other_cpus' as its arg.
916 * - Signals all CPUs in map to stop.
917 * - Waits for each to stop.
924 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
925 * from executing at same time.
928 stop_cpus(cpumask_t map)
930 map &= smp_active_mask;
932 /* send the Xcpustop IPI to all CPUs in map */
933 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
935 while ((stopped_cpus & map) != map)
943 * Called by a CPU to restart stopped CPUs.
945 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
947 * - Signals all CPUs in map to restart.
948 * - Waits for each to restart.
956 restart_cpus(cpumask_t map)
958 /* signal other cpus to restart */
959 started_cpus = map & smp_active_mask;
961 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
968 * This is called once the mpboot code has gotten us properly relocated
969 * and the MMU turned on, etc. ap_init() is actually the idle thread,
970 * and when it returns the scheduler will call the real cpu_idle() main
971 * loop for the idlethread. Interrupts are disabled on entry and should
972 * remain disabled at return.
980 * Adjust smp_startup_mask to signal the BSP that we have started
981 * up successfully. Note that we do not yet hold the BGL. The BSP
982 * is waiting for our signal.
984 * We can't set our bit in smp_active_mask yet because we are holding
985 * interrupts physically disabled and remote cpus could deadlock
986 * trying to send us an IPI.
988 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid);
992 * Interlock for LAPIC initialization. Wait until mp_finish_lapic is
993 * non-zero, then get the MP lock.
995 * Note: We are in a critical section.
997 * Note: we are the idle thread, we can only spin.
999 * Note: The load fence is memory volatile and prevents the compiler
1000 * from improperly caching mp_finish_lapic, and the cpu from improperly
1003 while (mp_finish_lapic == 0)
1005 while (try_mplock() == 0)
1008 if (cpu_feature & CPUID_TSC) {
1010 * The BSP is constantly updating tsc0_offset, figure out
1011 * the relative difference to synchronize ktrdump.
1013 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
1016 /* BSP may have changed PTD while we're waiting for the lock */
1019 /* Build our map of 'other' CPUs. */
1020 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
1022 /* A quick check from sanity claus */
1023 cpu_id = APICID_TO_CPUID((lapic->id & 0xff000000) >> 24);
1024 if (mycpu->gd_cpuid != cpu_id) {
1025 kprintf("SMP: assigned cpuid = %d\n", mycpu->gd_cpuid);
1026 kprintf("SMP: actual cpuid = %d lapicid %d\n",
1027 cpu_id, (lapic->id & 0xff000000) >> 24);
1029 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
1031 panic("cpuid mismatch! boom!!");
1034 /* Initialize AP's local APIC for irq's */
1037 /* LAPIC initialization is done */
1038 smp_lapic_mask |= CPUMASK(mycpu->gd_cpuid);
1041 /* Let BSP move onto the next initialization stage */
1045 * Interlock for finalization. Wait until mp_finish is non-zero,
1046 * then get the MP lock.
1048 * Note: We are in a critical section.
1050 * Note: we are the idle thread, we can only spin.
1052 * Note: The load fence is memory volatile and prevents the compiler
1053 * from improperly caching mp_finish, and the cpu from improperly
1056 while (mp_finish == 0)
1058 while (try_mplock() == 0)
1061 /* BSP may have changed PTD while we're waiting for the lock */
1064 /* Set memory range attributes for this CPU to match the BSP */
1065 mem_range_AP_init();
1068 * Once we go active we must process any IPIQ messages that may
1069 * have been queued, because no actual IPI will occur until we
1070 * set our bit in the smp_active_mask. If we don't the IPI
1071 * message interlock could be left set which would also prevent
1074 * The idle loop doesn't expect the BGL to be held and while
1075 * lwkt_switch() normally cleans things up this is a special case
1076 * because we returning almost directly into the idle loop.
1078 * The idle thread is never placed on the runq, make sure
1079 * nothing we've done put it there.
1081 KKASSERT(get_mplock_count(curthread) == 1);
1082 smp_active_mask |= CPUMASK(mycpu->gd_cpuid);
1085 * Enable interrupts here. idle_restore will also do it, but
1086 * doing it here lets us clean up any strays that got posted to
1087 * the CPU during the AP boot while we are still in a critical
1090 __asm __volatile("sti; pause; pause"::);
1091 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
1093 initclocks_pcpu(); /* clock interrupts (via IPIs) */
1094 lwkt_process_ipiq();
1097 * Releasing the mp lock lets the BSP finish up the SMP init
1100 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
1104 * Get SMP fully working before we start initializing devices.
1112 kprintf("Finish MP startup\n");
1114 while (smp_active_mask != smp_startup_mask)
1116 while (try_mplock() == 0)
1119 kprintf("Active CPU Mask: %016jx\n",
1120 (uintmax_t)smp_active_mask);
1124 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
1127 cpu_send_ipiq(int dcpu)
1129 if (CPUMASK(dcpu) & smp_active_mask)
1130 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
1133 #if 0 /* single_apic_ipi_passive() not working yet */
1135 * Returns 0 on failure, 1 on success
1138 cpu_send_ipiq_passive(int dcpu)
1141 if (CPUMASK(dcpu) & smp_active_mask) {
1142 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
1143 APIC_DELMODE_FIXED);
1150 cpu_simple_setup(void)
1152 /* build our map of 'other' CPUs */
1153 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
1154 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
1155 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
1159 if (cpu_feature & CPUID_TSC)
1160 tsc0_offset = rdtsc();