2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
30 #include <sys/param.h>
31 #include <sys/systm.h>
32 #include <sys/kernel.h>
33 #include <sys/sysctl.h>
34 #include <sys/malloc.h>
35 #include <sys/memrange.h>
36 #include <sys/cons.h> /* cngetc() */
37 #include <sys/machintr.h>
39 #include <sys/mplock2.h>
42 #include <vm/vm_param.h>
44 #include <vm/vm_kern.h>
45 #include <vm/vm_extern.h>
47 #include <vm/vm_map.h>
53 #include <machine/smp.h>
54 #include <machine_base/apic/apicreg.h>
55 #include <machine/atomic.h>
56 #include <machine/cpufunc.h>
57 #include <machine_base/apic/lapic.h>
58 #include <machine_base/apic/ioapic.h>
59 #include <machine/psl.h>
60 #include <machine/segments.h>
61 #include <machine/tss.h>
62 #include <machine/specialreg.h>
63 #include <machine/globaldata.h>
64 #include <machine/pmap_inval.h>
66 #include <machine/md_var.h> /* setidt() */
67 #include <machine_base/icu/icu.h> /* IPIs */
68 #include <machine_base/icu/icu_var.h>
69 #include <machine_base/apic/ioapic_abi.h>
70 #include <machine/intr_machdep.h> /* IPIs */
72 #define WARMBOOT_TARGET 0
73 #define WARMBOOT_OFF (KERNBASE + 0x0467)
74 #define WARMBOOT_SEG (KERNBASE + 0x0469)
76 #define CMOS_REG (0x70)
77 #define CMOS_DATA (0x71)
78 #define BIOS_RESET (0x0f)
79 #define BIOS_WARM (0x0a)
82 * this code MUST be enabled here and in mpboot.s.
83 * it follows the very early stages of AP boot by placing values in CMOS ram.
84 * it NORMALLY will never be needed and thus the primitive method for enabling.
87 #if defined(CHECK_POINTS)
88 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
89 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
91 #define CHECK_INIT(D); \
92 CHECK_WRITE(0x34, (D)); \
93 CHECK_WRITE(0x35, (D)); \
94 CHECK_WRITE(0x36, (D)); \
95 CHECK_WRITE(0x37, (D)); \
96 CHECK_WRITE(0x38, (D)); \
97 CHECK_WRITE(0x39, (D));
99 #define CHECK_PRINT(S); \
100 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
109 #else /* CHECK_POINTS */
111 #define CHECK_INIT(D)
112 #define CHECK_PRINT(S)
114 #endif /* CHECK_POINTS */
117 * Values to send to the POST hardware.
119 #define MP_BOOTADDRESS_POST 0x10
120 #define MP_PROBE_POST 0x11
121 #define MPTABLE_PASS1_POST 0x12
123 #define MP_START_POST 0x13
124 #define MP_ENABLE_POST 0x14
125 #define MPTABLE_PASS2_POST 0x15
127 #define START_ALL_APS_POST 0x16
128 #define INSTALL_AP_TRAMP_POST 0x17
129 #define START_AP_POST 0x18
131 #define MP_ANNOUNCE_POST 0x19
133 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
134 int current_postcode;
136 /** XXX FIXME: what system files declare these??? */
137 extern struct region_descriptor r_gdt, r_idt;
143 extern int64_t tsc_offsets[];
145 /* AP uses this during bootstrap. Do not staticize. */
149 struct pcb stoppcbs[MAXCPU];
151 extern inthand_t IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
154 * Local data and functions.
157 static u_int boot_address;
158 static int mp_finish;
159 static int mp_finish_lapic;
161 static void mp_enable(u_int boot_addr);
163 static int start_all_aps(u_int boot_addr);
165 static void install_ap_tramp(u_int boot_addr);
167 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
168 static int smitest(void);
169 static void cpu_simple_setup(void);
171 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
172 static cpumask_t smp_lapic_mask = 1; /* which cpus have lapic been inited */
173 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
174 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
175 static u_int bootMP_size;
178 * Calculate usable address in base memory for AP trampoline code.
181 mp_bootaddress(u_int basemem)
183 POSTCODE(MP_BOOTADDRESS_POST);
185 bootMP_size = mptramp_end - mptramp_start;
186 boot_address = trunc_page(basemem * 1024); /* round down to 4k boundary */
187 if (((basemem * 1024) - boot_address) < bootMP_size)
188 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
189 /* 3 levels of page table pages */
190 mptramp_pagetables = boot_address - (PAGE_SIZE * 3);
192 return mptramp_pagetables;
196 * Startup the SMP processors.
201 POSTCODE(MP_START_POST);
202 mp_enable(boot_address);
207 * Print various information about the SMP system hardware and setup.
214 POSTCODE(MP_ANNOUNCE_POST);
216 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
217 kprintf(" cpu0 (BSP): apic id: %2d\n", CPUID_TO_APICID(0));
218 for (x = 1; x <= naps; ++x)
219 kprintf(" cpu%d (AP): apic id: %2d\n", x, CPUID_TO_APICID(x));
222 kprintf(" Warning: APIC I/O disabled\n");
226 * AP cpu's call this to sync up protected mode.
228 * WARNING! %gs is not set up on entry. This routine sets up %gs.
234 int x, myid = bootAP;
236 struct mdglobaldata *md;
237 struct privatespace *ps;
239 ps = &CPU_prvspace[myid];
241 gdt_segs[GPROC0_SEL].ssd_base =
242 (long) &ps->mdglobaldata.gd_common_tss;
243 ps->mdglobaldata.mi.gd_prvspace = ps;
245 /* We fill the 32-bit segment descriptors */
246 for (x = 0; x < NGDT; x++) {
247 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
248 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x]);
250 /* And now a 64-bit one */
251 ssdtosyssd(&gdt_segs[GPROC0_SEL],
252 (struct system_segment_descriptor *)&gdt[myid * NGDT + GPROC0_SEL]);
254 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
255 r_gdt.rd_base = (long) &gdt[myid * NGDT];
256 lgdt(&r_gdt); /* does magic intra-segment return */
258 /* lgdt() destroys the GSBASE value, so we load GSBASE after lgdt() */
259 wrmsr(MSR_FSBASE, 0); /* User value */
260 wrmsr(MSR_GSBASE, (u_int64_t)ps);
261 wrmsr(MSR_KGSBASE, 0); /* XXX User value while we're in the kernel */
267 mdcpu->gd_currentldt = _default_ldt;
270 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
271 gdt[myid * NGDT + GPROC0_SEL].sd_type = SDT_SYSTSS;
273 md = mdcpu; /* loaded through %gs:0 (mdglobaldata.mi.gd_prvspace)*/
275 md->gd_common_tss.tss_rsp0 = 0; /* not used until after switch */
277 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
279 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL];
280 md->gd_common_tssd = *md->gd_tss_gdt;
282 /* double fault stack */
283 md->gd_common_tss.tss_ist1 =
284 (long)&md->mi.gd_prvspace->idlestack[
285 sizeof(md->mi.gd_prvspace->idlestack)];
290 * Set to a known state:
291 * Set by mpboot.s: CR0_PG, CR0_PE
292 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
295 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
298 /* Set up the fast syscall stuff */
299 msr = rdmsr(MSR_EFER) | EFER_SCE;
300 wrmsr(MSR_EFER, msr);
301 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
302 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
303 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
304 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
305 wrmsr(MSR_STAR, msr);
306 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D);
308 pmap_set_opt(); /* PSE/4MB pages, etc */
310 /* Initialize the PAT MSR. */
314 /* set up CPU registers and state */
317 /* set up SSE/NX registers */
320 /* set up FPU state on the AP */
321 npxinit(__INITIAL_NPXCW__);
323 /* disable the APIC, just to be SURE */
324 lapic->svr &= ~APIC_SVR_ENABLE;
327 /*******************************************************************
328 * local functions and data
332 * start the SMP system
335 mp_enable(u_int boot_addr)
339 POSTCODE(MP_ENABLE_POST);
341 error = lapic_config();
345 icu_reinit_noioapic();
351 /* Initialize BSP's local APIC */
354 /* start each Application Processor */
355 start_all_aps(boot_addr);
358 error = ioapic_config();
361 icu_reinit_noioapic();
362 lapic_fixup_noioapic();
368 * start each AP in our list
371 start_all_aps(u_int boot_addr)
373 vm_offset_t va = boot_address + KERNBASE;
374 u_int64_t *pt4, *pt3, *pt2;
381 u_long mpbioswarmvec;
382 struct mdglobaldata *gd;
383 struct privatespace *ps;
385 POSTCODE(START_ALL_APS_POST);
387 /* install the AP 1st level boot code */
388 pmap_kenter(va, boot_address);
389 cpu_invlpg((void *)va); /* JG XXX */
390 bcopy(mptramp_start, (void *)va, bootMP_size);
392 /* Locate the page tables, they'll be below the trampoline */
393 pt4 = (u_int64_t *)(uintptr_t)(mptramp_pagetables + KERNBASE);
394 pt3 = pt4 + (PAGE_SIZE) / sizeof(u_int64_t);
395 pt2 = pt3 + (PAGE_SIZE) / sizeof(u_int64_t);
397 /* Create the initial 1GB replicated page tables */
398 for (i = 0; i < 512; i++) {
399 /* Each slot of the level 4 pages points to the same level 3 page */
400 pt4[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + PAGE_SIZE);
401 pt4[i] |= PG_V | PG_RW | PG_U;
403 /* Each slot of the level 3 pages points to the same level 2 page */
404 pt3[i] = (u_int64_t)(uintptr_t)(mptramp_pagetables + (2 * PAGE_SIZE));
405 pt3[i] |= PG_V | PG_RW | PG_U;
407 /* The level 2 page slots are mapped with 2MB pages for 1GB. */
408 pt2[i] = i * (2 * 1024 * 1024);
409 pt2[i] |= PG_V | PG_RW | PG_PS | PG_U;
412 /* save the current value of the warm-start vector */
413 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
414 outb(CMOS_REG, BIOS_RESET);
415 mpbiosreason = inb(CMOS_DATA);
417 /* setup a vector to our boot code */
418 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
419 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
420 outb(CMOS_REG, BIOS_RESET);
421 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
424 * If we have a TSC we can figure out the SMI interrupt rate.
425 * The SMI does not necessarily use a constant rate. Spend
426 * up to 250ms trying to figure it out.
429 if (cpu_feature & CPUID_TSC) {
430 set_apic_timer(275000);
431 smilast = read_apic_timer();
432 for (x = 0; x < 20 && read_apic_timer(); ++x) {
433 smicount = smitest();
434 if (smibest == 0 || smilast - smicount < smibest)
435 smibest = smilast - smicount;
438 if (smibest > 250000)
441 smibest = smibest * (int64_t)1000000 /
442 get_apic_timer_frequency();
446 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
447 1000000 / smibest, smibest);
450 for (x = 1; x <= naps; ++x) {
452 /* This is a bit verbose, it will go away soon. */
454 /* first page of AP's private space */
455 pg = x * x86_64_btop(sizeof(struct privatespace));
457 /* allocate new private data page(s) */
458 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
459 MDGLOBALDATA_BASEALLOC_SIZE);
461 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
462 bzero(gd, sizeof(*gd));
463 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
465 /* prime data page for it to use */
466 mi_gdinit(&gd->mi, x);
468 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (naps + 1));
469 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (naps + 1));
471 /* setup a vector to our boot code */
472 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
473 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
474 outb(CMOS_REG, BIOS_RESET);
475 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
478 * Setup the AP boot stack
480 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
483 /* attempt to start the Application Processor */
484 CHECK_INIT(99); /* setup checkpoints */
485 if (!start_ap(gd, boot_addr, smibest)) {
486 kprintf("\nAP #%d (PHY# %d) failed!\n",
487 x, CPUID_TO_APICID(x));
488 CHECK_PRINT("trace"); /* show checkpoints */
489 /* better panic as the AP may be running loose */
490 kprintf("panic y/n? [y] ");
494 CHECK_PRINT("trace"); /* show checkpoints */
497 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
500 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
501 for (shift = 0; (1 << shift) <= ncpus; ++shift)
504 ncpus2_shift = shift;
506 ncpus2_mask = ncpus2 - 1;
508 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
509 if ((1 << shift) < ncpus)
511 ncpus_fit = 1 << shift;
512 ncpus_fit_mask = ncpus_fit - 1;
514 /* build our map of 'other' CPUs */
515 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
516 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
517 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
519 /* restore the warmstart vector */
520 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
521 outb(CMOS_REG, BIOS_RESET);
522 outb(CMOS_DATA, mpbiosreason);
525 * NOTE! The idlestack for the BSP was setup by locore. Finish
526 * up, clean out the P==V mapping we did earlier.
531 * Wait all APs to finish initializing LAPIC
535 kprintf("SMP: Waiting APs LAPIC initialization\n");
536 if (cpu_feature & CPUID_TSC)
537 tsc0_offset = rdtsc();
540 while (smp_lapic_mask != smp_startup_mask) {
542 if (cpu_feature & CPUID_TSC)
543 tsc0_offset = rdtsc();
545 while (try_mplock() == 0)
548 /* number of APs actually started */
554 * load the 1st level AP boot code into base memory.
557 /* targets for relocation */
558 extern void bigJump(void);
559 extern void bootCodeSeg(void);
560 extern void bootDataSeg(void);
561 extern void MPentry(void);
563 extern u_int mp_gdtbase;
568 install_ap_tramp(u_int boot_addr)
571 int size = *(int *) ((u_long) & bootMP_size);
572 u_char *src = (u_char *) ((u_long) bootMP);
573 u_char *dst = (u_char *) boot_addr + KERNBASE;
574 u_int boot_base = (u_int) bootMP;
579 POSTCODE(INSTALL_AP_TRAMP_POST);
581 for (x = 0; x < size; ++x)
585 * modify addresses in code we just moved to basemem. unfortunately we
586 * need fairly detailed info about mpboot.s for this to work. changes
587 * to mpboot.s might require changes here.
590 /* boot code is located in KERNEL space */
591 dst = (u_char *) boot_addr + KERNBASE;
593 /* modify the lgdt arg */
594 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
595 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
597 /* modify the ljmp target for MPentry() */
598 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
599 *dst32 = ((u_int) MPentry - KERNBASE);
601 /* modify the target for boot code segment */
602 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
603 dst8 = (u_int8_t *) (dst16 + 1);
604 *dst16 = (u_int) boot_addr & 0xffff;
605 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
607 /* modify the target for boot data segment */
608 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
609 dst8 = (u_int8_t *) (dst16 + 1);
610 *dst16 = (u_int) boot_addr & 0xffff;
611 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
617 * This function starts the AP (application processor) identified
618 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
619 * to accomplish this. This is necessary because of the nuances
620 * of the different hardware we might encounter. It ain't pretty,
621 * but it seems to work.
623 * NOTE: eventually an AP gets to ap_init(), which is called just
624 * before the AP goes into the LWKT scheduler's idle loop.
627 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
631 u_long icr_lo, icr_hi;
633 POSTCODE(START_AP_POST);
635 /* get the PHYSICAL APIC ID# */
636 physical_cpu = CPUID_TO_APICID(gd->mi.gd_cpuid);
638 /* calculate the vector */
639 vector = (boot_addr >> 12) & 0xff;
641 /* We don't want anything interfering */
644 /* Make sure the target cpu sees everything */
648 * Try to detect when a SMI has occurred, wait up to 200ms.
650 * If a SMI occurs during an AP reset but before we issue
651 * the STARTUP command, the AP may brick. To work around
652 * this problem we hold off doing the AP startup until
653 * after we have detected the SMI. Hopefully another SMI
654 * will not occur before we finish the AP startup.
656 * Retries don't seem to help. SMIs have a window of opportunity
657 * and if USB->legacy keyboard emulation is enabled in the BIOS
658 * the interrupt rate can be quite high.
660 * NOTE: Don't worry about the L1 cache load, it might bloat
661 * ldelta a little but ndelta will be so huge when the SMI
662 * occurs the detection logic will still work fine.
665 set_apic_timer(200000);
670 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
671 * and running the target CPU. OR this INIT IPI might be latched (P5
672 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
675 * see apic/apicreg.h for icr bit definitions.
677 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
681 * Setup the address for the target AP. We can setup
682 * icr_hi once and then just trigger operations with
685 icr_hi = lapic->icr_hi & ~APIC_ID_MASK;
686 icr_hi |= (physical_cpu << 24);
687 icr_lo = lapic->icr_lo & 0xfff00000;
688 lapic->icr_hi = icr_hi;
691 * Do an INIT IPI: assert RESET
693 * Use edge triggered mode to assert INIT
695 lapic->icr_lo = icr_lo | 0x00004500;
696 while (lapic->icr_lo & APIC_DELSTAT_MASK)
700 * The spec calls for a 10ms delay but we may have to use a
701 * MUCH lower delay to avoid bricking an AP due to a fast SMI
702 * interrupt. We have other loops here too and dividing by 2
703 * doesn't seem to be enough even after subtracting 350us,
706 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
707 * interrupt was detected we use the full 10ms.
711 else if (smibest < 150 * 4 + 350)
713 else if ((smibest - 350) / 4 < 10000)
714 u_sleep((smibest - 350) / 4);
719 * Do an INIT IPI: deassert RESET
721 * Use level triggered mode to deassert. It is unclear
722 * why we need to do this.
724 lapic->icr_lo = icr_lo | 0x00008500;
725 while (lapic->icr_lo & APIC_DELSTAT_MASK)
727 u_sleep(150); /* wait 150us */
730 * Next we do a STARTUP IPI: the previous INIT IPI might still be
731 * latched, (P5 bug) this 1st STARTUP would then terminate
732 * immediately, and the previously started INIT IPI would continue. OR
733 * the previous INIT IPI has already run. and this STARTUP IPI will
734 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
737 lapic->icr_lo = icr_lo | 0x00000600 | vector;
738 while (lapic->icr_lo & APIC_DELSTAT_MASK)
740 u_sleep(200); /* wait ~200uS */
743 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
744 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
745 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
746 * recognized after hardware RESET or INIT IPI.
748 lapic->icr_lo = icr_lo | 0x00000600 | vector;
749 while (lapic->icr_lo & APIC_DELSTAT_MASK)
752 /* Resume normal operation */
755 /* wait for it to start, see ap_init() */
756 set_apic_timer(5000000);/* == 5 seconds */
757 while (read_apic_timer()) {
758 if (smp_startup_mask & CPUMASK(gd->mi.gd_cpuid))
759 return 1; /* return SUCCESS */
762 return 0; /* return FAILURE */
777 while (read_apic_timer()) {
779 for (count = 0; count < 100; ++count)
780 ntsc = rdtsc(); /* force loop to occur */
782 ndelta = ntsc - ltsc;
785 if (ndelta > ldelta * 2)
788 ldelta = ntsc - ltsc;
791 return(read_apic_timer());
795 * Synchronously flush the TLB on all other CPU's. The current cpu's
796 * TLB is not flushed. If the caller wishes to flush the current cpu's
797 * TLB the caller must call cpu_invltlb() in addition to smp_invltlb().
799 * NOTE: If for some reason we were unable to start all cpus we cannot
800 * safely use broadcast IPIs.
803 static cpumask_t smp_invltlb_req;
805 #define SMP_INVLTLB_DEBUG
811 struct mdglobaldata *md = mdcpu;
812 #ifdef SMP_INVLTLB_DEBUG
817 crit_enter_gd(&md->mi);
818 md->gd_invltlb_ret = 0;
819 ++md->mi.gd_cnt.v_smpinvltlb;
820 atomic_set_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
821 #ifdef SMP_INVLTLB_DEBUG
824 if (smp_startup_mask == smp_active_mask) {
825 all_but_self_ipi(XINVLTLB_OFFSET);
827 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
828 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
831 #ifdef SMP_INVLTLB_DEBUG
833 kprintf("smp_invltlb: ipi sent\n");
835 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
836 (smp_active_mask & ~md->mi.gd_cpumask)) {
839 #ifdef SMP_INVLTLB_DEBUG
841 if (++count == 400000000) {
843 kprintf("smp_invltlb: endless loop %08lx %08lx, "
844 "rflags %016jx retry",
845 (long)md->gd_invltlb_ret,
846 (long)smp_invltlb_req,
847 (intmax_t)read_rflags());
848 __asm __volatile ("sti");
853 int bcpu = BSFCPUMASK(~md->gd_invltlb_ret &
858 kprintf("bcpu %d\n", bcpu);
859 xgd = globaldata_find(bcpu);
860 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
863 Debugger("giving up");
869 atomic_clear_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
870 crit_exit_gd(&md->mi);
877 * Called from Xinvltlb assembly with interrupts disabled. We didn't
878 * bother to bump the critical section count or nested interrupt count
879 * so only do very low level operations here.
882 smp_invltlb_intr(void)
884 struct mdglobaldata *md = mdcpu;
885 struct mdglobaldata *omd;
890 mask = smp_invltlb_req;
893 cpu = BSFCPUMASK(mask);
894 mask &= ~CPUMASK(cpu);
895 omd = (struct mdglobaldata *)globaldata_find(cpu);
896 atomic_set_cpumask(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
903 * When called the executing CPU will send an IPI to all other CPUs
904 * requesting that they halt execution.
906 * Usually (but not necessarily) called with 'other_cpus' as its arg.
908 * - Signals all CPUs in map to stop.
909 * - Waits for each to stop.
916 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
917 * from executing at same time.
920 stop_cpus(cpumask_t map)
922 map &= smp_active_mask;
924 /* send the Xcpustop IPI to all CPUs in map */
925 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
927 while ((stopped_cpus & map) != map)
935 * Called by a CPU to restart stopped CPUs.
937 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
939 * - Signals all CPUs in map to restart.
940 * - Waits for each to restart.
948 restart_cpus(cpumask_t map)
950 /* signal other cpus to restart */
951 started_cpus = map & smp_active_mask;
953 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
960 * This is called once the mpboot code has gotten us properly relocated
961 * and the MMU turned on, etc. ap_init() is actually the idle thread,
962 * and when it returns the scheduler will call the real cpu_idle() main
963 * loop for the idlethread. Interrupts are disabled on entry and should
964 * remain disabled at return.
972 * Adjust smp_startup_mask to signal the BSP that we have started
973 * up successfully. Note that we do not yet hold the BGL. The BSP
974 * is waiting for our signal.
976 * We can't set our bit in smp_active_mask yet because we are holding
977 * interrupts physically disabled and remote cpus could deadlock
978 * trying to send us an IPI.
980 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid);
984 * Interlock for LAPIC initialization. Wait until mp_finish_lapic is
985 * non-zero, then get the MP lock.
987 * Note: We are in a critical section.
989 * Note: we are the idle thread, we can only spin.
991 * Note: The load fence is memory volatile and prevents the compiler
992 * from improperly caching mp_finish_lapic, and the cpu from improperly
995 while (mp_finish_lapic == 0)
997 while (try_mplock() == 0)
1000 if (cpu_feature & CPUID_TSC) {
1002 * The BSP is constantly updating tsc0_offset, figure out
1003 * the relative difference to synchronize ktrdump.
1005 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
1008 /* BSP may have changed PTD while we're waiting for the lock */
1011 /* Build our map of 'other' CPUs. */
1012 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
1014 /* A quick check from sanity claus */
1015 cpu_id = APICID_TO_CPUID((lapic->id & 0xff000000) >> 24);
1016 if (mycpu->gd_cpuid != cpu_id) {
1017 kprintf("SMP: assigned cpuid = %d\n", mycpu->gd_cpuid);
1018 kprintf("SMP: actual cpuid = %d lapicid %d\n",
1019 cpu_id, (lapic->id & 0xff000000) >> 24);
1021 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
1023 panic("cpuid mismatch! boom!!");
1026 /* Initialize AP's local APIC for irq's */
1029 /* LAPIC initialization is done */
1030 smp_lapic_mask |= CPUMASK(mycpu->gd_cpuid);
1033 /* Let BSP move onto the next initialization stage */
1037 * Interlock for finalization. Wait until mp_finish is non-zero,
1038 * then get the MP lock.
1040 * Note: We are in a critical section.
1042 * Note: we are the idle thread, we can only spin.
1044 * Note: The load fence is memory volatile and prevents the compiler
1045 * from improperly caching mp_finish, and the cpu from improperly
1048 while (mp_finish == 0)
1050 while (try_mplock() == 0)
1053 /* BSP may have changed PTD while we're waiting for the lock */
1056 /* Set memory range attributes for this CPU to match the BSP */
1057 mem_range_AP_init();
1060 * Once we go active we must process any IPIQ messages that may
1061 * have been queued, because no actual IPI will occur until we
1062 * set our bit in the smp_active_mask. If we don't the IPI
1063 * message interlock could be left set which would also prevent
1066 * The idle loop doesn't expect the BGL to be held and while
1067 * lwkt_switch() normally cleans things up this is a special case
1068 * because we returning almost directly into the idle loop.
1070 * The idle thread is never placed on the runq, make sure
1071 * nothing we've done put it there.
1073 KKASSERT(get_mplock_count(curthread) == 1);
1074 smp_active_mask |= CPUMASK(mycpu->gd_cpuid);
1077 * Enable interrupts here. idle_restore will also do it, but
1078 * doing it here lets us clean up any strays that got posted to
1079 * the CPU during the AP boot while we are still in a critical
1082 __asm __volatile("sti; pause; pause"::);
1083 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
1085 initclocks_pcpu(); /* clock interrupts (via IPIs) */
1086 lwkt_process_ipiq();
1089 * Releasing the mp lock lets the BSP finish up the SMP init
1092 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
1096 * Get SMP fully working before we start initializing devices.
1104 kprintf("Finish MP startup\n");
1106 while (smp_active_mask != smp_startup_mask)
1108 while (try_mplock() == 0)
1111 kprintf("Active CPU Mask: %016jx\n",
1112 (uintmax_t)smp_active_mask);
1116 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
1119 cpu_send_ipiq(int dcpu)
1121 if (CPUMASK(dcpu) & smp_active_mask)
1122 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
1125 #if 0 /* single_apic_ipi_passive() not working yet */
1127 * Returns 0 on failure, 1 on success
1130 cpu_send_ipiq_passive(int dcpu)
1133 if (CPUMASK(dcpu) & smp_active_mask) {
1134 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
1135 APIC_DELMODE_FIXED);
1142 cpu_simple_setup(void)
1144 /* build our map of 'other' CPUs */
1145 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
1146 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
1147 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
1151 if (cpu_feature & CPUID_TSC)
1152 tsc0_offset = rdtsc();