2 * Copyright 2009 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Alex Deucher <alexander.deucher@amd.com>
26 * $FreeBSD: head/sys/dev/drm2/radeon/r600_blit.c 254885 2013-08-25 19:37:15Z dumbbell $
30 #include <uapi_drm/radeon_drm.h>
31 #include "radeon_drv.h"
33 #include "r600_blit_shaders.h"
35 #define DI_PT_RECTLIST 0x11
36 #define DI_INDEX_SIZE_16_BIT 0x0
37 #define DI_SRC_SEL_AUTO_INDEX 0x2
41 #define FMT_8_8_8_8 0x1a
43 #define COLOR_5_6_5 0x8
44 #define COLOR_8_8_8_8 0x1a
47 set_render_target(drm_radeon_private_t *dev_priv, int format, int w, int h, u64 gpu_addr)
58 cb_color_info = ((format << 2) | (1 << 27));
60 slice = ((w * h) / 64) - 1;
62 if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600) &&
63 ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770)) {
65 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
66 OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
67 OUT_RING(gpu_addr >> 8);
68 OUT_RING(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
72 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
73 OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
74 OUT_RING(gpu_addr >> 8);
77 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
78 OUT_RING((R600_CB_COLOR0_SIZE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
79 OUT_RING((pitch << 0) | (slice << 10));
81 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
82 OUT_RING((R600_CB_COLOR0_VIEW - R600_SET_CONTEXT_REG_OFFSET) >> 2);
85 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
86 OUT_RING((R600_CB_COLOR0_INFO - R600_SET_CONTEXT_REG_OFFSET) >> 2);
87 OUT_RING(cb_color_info);
89 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
90 OUT_RING((R600_CB_COLOR0_TILE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
93 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
94 OUT_RING((R600_CB_COLOR0_FRAG - R600_SET_CONTEXT_REG_OFFSET) >> 2);
97 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
98 OUT_RING((R600_CB_COLOR0_MASK - R600_SET_CONTEXT_REG_OFFSET) >> 2);
105 cp_set_surface_sync(drm_radeon_private_t *dev_priv,
106 u32 sync_type, u32 size, u64 mc_addr)
112 if (size == 0xffffffff)
113 cp_coher_size = 0xffffffff;
115 cp_coher_size = ((size + 255) >> 8);
118 OUT_RING(CP_PACKET3(R600_IT_SURFACE_SYNC, 3));
120 OUT_RING(cp_coher_size);
121 OUT_RING((mc_addr >> 8));
122 OUT_RING(10); /* poll interval */
127 set_shaders(struct drm_device *dev)
129 drm_radeon_private_t *dev_priv = dev->dev_private;
133 uint32_t sq_pgm_resources;
138 vs = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset);
139 ps = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset + 256);
141 for (i = 0; i < r6xx_vs_size; i++)
142 vs[i] = cpu_to_le32(r6xx_vs[i]);
143 for (i = 0; i < r6xx_ps_size; i++)
144 ps[i] = cpu_to_le32(r6xx_ps[i]);
146 dev_priv->blit_vb->used = 512;
148 gpu_addr = dev_priv->gart_buffers_offset + dev_priv->blit_vb->offset;
150 /* setup shader regs */
151 sq_pgm_resources = (1 << 0);
155 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
156 OUT_RING((R600_SQ_PGM_START_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
157 OUT_RING(gpu_addr >> 8);
159 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
160 OUT_RING((R600_SQ_PGM_RESOURCES_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
161 OUT_RING(sq_pgm_resources);
163 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
164 OUT_RING((R600_SQ_PGM_CF_OFFSET_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
168 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
169 OUT_RING((R600_SQ_PGM_START_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
170 OUT_RING((gpu_addr + 256) >> 8);
172 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
173 OUT_RING((R600_SQ_PGM_RESOURCES_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
174 OUT_RING(sq_pgm_resources | (1 << 28));
176 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
177 OUT_RING((R600_SQ_PGM_EXPORTS_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
180 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
181 OUT_RING((R600_SQ_PGM_CF_OFFSET_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
185 cp_set_surface_sync(dev_priv,
186 R600_SH_ACTION_ENA, 512, gpu_addr);
190 set_vtx_resource(drm_radeon_private_t *dev_priv, u64 gpu_addr)
192 uint32_t sq_vtx_constant_word2;
196 sq_vtx_constant_word2 = (((gpu_addr >> 32) & 0xff) | (16 << 8));
198 sq_vtx_constant_word2 |= (2 << 30);
202 OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
204 OUT_RING(gpu_addr & 0xffffffff);
206 OUT_RING(sq_vtx_constant_word2);
210 OUT_RING(R600_SQ_TEX_VTX_VALID_BUFFER << 30);
213 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
214 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
215 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
216 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880) ||
217 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710))
218 cp_set_surface_sync(dev_priv,
219 R600_TC_ACTION_ENA, 48, gpu_addr);
221 cp_set_surface_sync(dev_priv,
222 R600_VC_ACTION_ENA, 48, gpu_addr);
226 set_tex_resource(drm_radeon_private_t *dev_priv,
227 int format, int w, int h, int pitch, u64 gpu_addr)
229 uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
236 sq_tex_resource_word0 = (1 << 0);
237 sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) |
240 sq_tex_resource_word1 = (format << 26);
241 sq_tex_resource_word1 |= ((h - 1) << 0);
243 sq_tex_resource_word4 = ((1 << 14) |
250 OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
252 OUT_RING(sq_tex_resource_word0);
253 OUT_RING(sq_tex_resource_word1);
254 OUT_RING(gpu_addr >> 8);
255 OUT_RING(gpu_addr >> 8);
256 OUT_RING(sq_tex_resource_word4);
258 OUT_RING(R600_SQ_TEX_VTX_VALID_TEXTURE << 30);
264 set_scissors(drm_radeon_private_t *dev_priv, int x1, int y1, int x2, int y2)
270 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
271 OUT_RING((R600_PA_SC_SCREEN_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
272 OUT_RING((x1 << 0) | (y1 << 16));
273 OUT_RING((x2 << 0) | (y2 << 16));
275 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
276 OUT_RING((R600_PA_SC_GENERIC_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
277 OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31));
278 OUT_RING((x2 << 0) | (y2 << 16));
280 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
281 OUT_RING((R600_PA_SC_WINDOW_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
282 OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31));
283 OUT_RING((x2 << 0) | (y2 << 16));
288 draw_auto(drm_radeon_private_t *dev_priv)
294 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
295 OUT_RING((R600_VGT_PRIMITIVE_TYPE - R600_SET_CONFIG_REG_OFFSET) >> 2);
296 OUT_RING(DI_PT_RECTLIST);
298 OUT_RING(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
300 OUT_RING((2 << 2) | DI_INDEX_SIZE_16_BIT);
302 OUT_RING(DI_INDEX_SIZE_16_BIT);
305 OUT_RING(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
308 OUT_RING(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1));
310 OUT_RING(DI_SRC_SEL_AUTO_INDEX);
317 set_default_state(drm_radeon_private_t *dev_priv)
320 u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
321 u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
322 int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
323 int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
324 int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
327 switch ((dev_priv->flags & RADEON_FAMILY_MASK)) {
334 num_ps_threads = 136;
338 num_ps_stack_entries = 128;
339 num_vs_stack_entries = 128;
340 num_gs_stack_entries = 0;
341 num_es_stack_entries = 0;
350 num_ps_threads = 144;
354 num_ps_stack_entries = 40;
355 num_vs_stack_entries = 40;
356 num_gs_stack_entries = 32;
357 num_es_stack_entries = 16;
369 num_ps_threads = 136;
373 num_ps_stack_entries = 40;
374 num_vs_stack_entries = 40;
375 num_gs_stack_entries = 32;
376 num_es_stack_entries = 16;
384 num_ps_threads = 136;
388 num_ps_stack_entries = 40;
389 num_vs_stack_entries = 40;
390 num_gs_stack_entries = 32;
391 num_es_stack_entries = 16;
399 num_ps_threads = 188;
403 num_ps_stack_entries = 256;
404 num_vs_stack_entries = 256;
405 num_gs_stack_entries = 0;
406 num_es_stack_entries = 0;
415 num_ps_threads = 188;
419 num_ps_stack_entries = 128;
420 num_vs_stack_entries = 128;
421 num_gs_stack_entries = 0;
422 num_es_stack_entries = 0;
430 num_ps_threads = 144;
434 num_ps_stack_entries = 128;
435 num_vs_stack_entries = 128;
436 num_gs_stack_entries = 0;
437 num_es_stack_entries = 0;
441 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
442 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
443 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
444 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880) ||
445 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710))
448 sq_config = R600_VC_ENABLE;
450 sq_config |= (R600_DX9_CONSTS |
451 R600_ALU_INST_PREFER_VECTOR |
457 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(num_ps_gprs) |
458 R600_NUM_VS_GPRS(num_vs_gprs) |
459 R600_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
460 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(num_gs_gprs) |
461 R600_NUM_ES_GPRS(num_es_gprs));
462 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(num_ps_threads) |
463 R600_NUM_VS_THREADS(num_vs_threads) |
464 R600_NUM_GS_THREADS(num_gs_threads) |
465 R600_NUM_ES_THREADS(num_es_threads));
466 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
467 R600_NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
468 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
469 R600_NUM_ES_STACK_ENTRIES(num_es_stack_entries));
471 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
472 BEGIN_RING(r7xx_default_size + 10);
473 for (i = 0; i < r7xx_default_size; i++)
474 OUT_RING(r7xx_default_state[i]);
476 BEGIN_RING(r6xx_default_size + 10);
477 for (i = 0; i < r6xx_default_size; i++)
478 OUT_RING(r6xx_default_state[i]);
480 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
481 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
483 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 6));
484 OUT_RING((R600_SQ_CONFIG - R600_SET_CONFIG_REG_OFFSET) >> 2);
486 OUT_RING(sq_gpr_resource_mgmt_1);
487 OUT_RING(sq_gpr_resource_mgmt_2);
488 OUT_RING(sq_thread_resource_mgmt);
489 OUT_RING(sq_stack_resource_mgmt_1);
490 OUT_RING(sq_stack_resource_mgmt_2);
494 /* 23 bits of float fractional data */
495 #define I2F_FRAC_BITS 23
496 #define I2F_MASK ((1 << I2F_FRAC_BITS) - 1)
499 * Converts unsigned integer into 32-bit IEEE floating point representation.
500 * Will be exact from 0 to 2^24. Above that, we round towards zero
501 * as the fractional bits will not fit in a float. (It would be better to
502 * round towards even as the fpu does, but that is slower.)
504 __pure uint32_t int2float(uint32_t x)
506 uint32_t msb, exponent, fraction;
508 /* Zero is special */
511 /* Get location of the most significant bit */
515 * Use a rotate instead of a shift because that works both leftwards
516 * and rightwards due to the mod(32) behaviour. This means we don't
517 * need to check to see if we are above 2^24 or not.
519 fraction = ror32(x, (msb - I2F_FRAC_BITS) & 0x1f) & I2F_MASK;
520 exponent = (127 + msb) << I2F_FRAC_BITS;
522 return fraction + exponent;
525 static int r600_nomm_get_vb(struct drm_device *dev)
527 drm_radeon_private_t *dev_priv = dev->dev_private;
528 dev_priv->blit_vb = radeon_freelist_get(dev);
529 if (!dev_priv->blit_vb) {
530 DRM_ERROR("Unable to allocate vertex buffer for blit\n");
536 static void r600_nomm_put_vb(struct drm_device *dev)
538 drm_radeon_private_t *dev_priv = dev->dev_private;
540 dev_priv->blit_vb->used = 0;
541 radeon_cp_discard_buffer(dev, dev_priv->blit_vb->file_priv->master, dev_priv->blit_vb);
544 static void *r600_nomm_get_vb_ptr(struct drm_device *dev)
546 drm_radeon_private_t *dev_priv = dev->dev_private;
547 return (((char *)dev->agp_buffer_map->handle +
548 dev_priv->blit_vb->offset + dev_priv->blit_vb->used));
552 r600_prepare_blit_copy(struct drm_device *dev, struct drm_file *file_priv)
554 drm_radeon_private_t *dev_priv = dev->dev_private;
558 ret = r600_nomm_get_vb(dev);
562 dev_priv->blit_vb->file_priv = file_priv;
564 set_default_state(dev_priv);
572 r600_done_blit_copy(struct drm_device *dev)
574 drm_radeon_private_t *dev_priv = dev->dev_private;
579 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
580 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
581 /* wait for 3D idle clean */
582 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
583 OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2);
584 OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN);
589 r600_nomm_put_vb(dev);
593 r600_blit_copy(struct drm_device *dev,
594 uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
597 drm_radeon_private_t *dev_priv = dev->dev_private;
602 vb = r600_nomm_get_vb_ptr(dev);
604 if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) {
608 int cur_size = size_bytes;
609 int src_x = src_gpu_addr & 255;
610 int dst_x = dst_gpu_addr & 255;
612 src_gpu_addr = src_gpu_addr & ~255;
613 dst_gpu_addr = dst_gpu_addr & ~255;
615 if (!src_x && !dst_x) {
616 h = (cur_size / max_bytes);
622 cur_size = max_bytes;
624 if (cur_size > max_bytes)
625 cur_size = max_bytes;
626 if (cur_size > (max_bytes - dst_x))
627 cur_size = (max_bytes - dst_x);
628 if (cur_size > (max_bytes - src_x))
629 cur_size = (max_bytes - src_x);
632 if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) {
634 r600_nomm_put_vb(dev);
635 r600_nomm_get_vb(dev);
636 if (!dev_priv->blit_vb)
639 vb = r600_nomm_get_vb_ptr(dev);
642 vb[0] = int2float(dst_x);
644 vb[2] = int2float(src_x);
647 vb[4] = int2float(dst_x);
648 vb[5] = int2float(h);
649 vb[6] = int2float(src_x);
650 vb[7] = int2float(h);
652 vb[8] = int2float(dst_x + cur_size);
653 vb[9] = int2float(h);
654 vb[10] = int2float(src_x + cur_size);
655 vb[11] = int2float(h);
658 set_tex_resource(dev_priv, FMT_8,
659 src_x + cur_size, h, src_x + cur_size,
662 cp_set_surface_sync(dev_priv,
663 R600_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
666 set_render_target(dev_priv, COLOR_8,
671 set_scissors(dev_priv, dst_x, 0, dst_x + cur_size, h);
673 /* Vertex buffer setup */
674 vb_addr = dev_priv->gart_buffers_offset +
675 dev_priv->blit_vb->offset +
676 dev_priv->blit_vb->used;
677 set_vtx_resource(dev_priv, vb_addr);
682 cp_set_surface_sync(dev_priv,
683 R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA,
684 cur_size * h, dst_gpu_addr);
687 dev_priv->blit_vb->used += 12 * 4;
689 src_gpu_addr += cur_size * h;
690 dst_gpu_addr += cur_size * h;
691 size_bytes -= cur_size * h;
694 max_bytes = 8192 * 4;
697 int cur_size = size_bytes;
698 int src_x = (src_gpu_addr & 255);
699 int dst_x = (dst_gpu_addr & 255);
701 src_gpu_addr = src_gpu_addr & ~255;
702 dst_gpu_addr = dst_gpu_addr & ~255;
704 if (!src_x && !dst_x) {
705 h = (cur_size / max_bytes);
711 cur_size = max_bytes;
713 if (cur_size > max_bytes)
714 cur_size = max_bytes;
715 if (cur_size > (max_bytes - dst_x))
716 cur_size = (max_bytes - dst_x);
717 if (cur_size > (max_bytes - src_x))
718 cur_size = (max_bytes - src_x);
721 if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) {
722 r600_nomm_put_vb(dev);
723 r600_nomm_get_vb(dev);
724 if (!dev_priv->blit_vb)
728 vb = r600_nomm_get_vb_ptr(dev);
731 vb[0] = int2float(dst_x / 4);
733 vb[2] = int2float(src_x / 4);
736 vb[4] = int2float(dst_x / 4);
737 vb[5] = int2float(h);
738 vb[6] = int2float(src_x / 4);
739 vb[7] = int2float(h);
741 vb[8] = int2float((dst_x + cur_size) / 4);
742 vb[9] = int2float(h);
743 vb[10] = int2float((src_x + cur_size) / 4);
744 vb[11] = int2float(h);
747 set_tex_resource(dev_priv, FMT_8_8_8_8,
748 (src_x + cur_size) / 4,
749 h, (src_x + cur_size) / 4,
752 cp_set_surface_sync(dev_priv,
753 R600_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
756 set_render_target(dev_priv, COLOR_8_8_8_8,
757 (dst_x + cur_size) / 4, h,
761 set_scissors(dev_priv, (dst_x / 4), 0, (dst_x + cur_size / 4), h);
763 /* Vertex buffer setup */
764 vb_addr = dev_priv->gart_buffers_offset +
765 dev_priv->blit_vb->offset +
766 dev_priv->blit_vb->used;
767 set_vtx_resource(dev_priv, vb_addr);
772 cp_set_surface_sync(dev_priv,
773 R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA,
774 cur_size * h, dst_gpu_addr);
777 dev_priv->blit_vb->used += 12 * 4;
779 src_gpu_addr += cur_size * h;
780 dst_gpu_addr += cur_size * h;
781 size_bytes -= cur_size * h;
787 r600_blit_swap(struct drm_device *dev,
788 uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
789 int sx, int sy, int dx, int dy,
790 int w, int h, int src_pitch, int dst_pitch, int cpp)
792 drm_radeon_private_t *dev_priv = dev->dev_private;
793 int cb_format, tex_format;
794 int sx2, sy2, dx2, dy2;
798 if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) {
800 r600_nomm_put_vb(dev);
801 r600_nomm_get_vb(dev);
802 if (!dev_priv->blit_vb)
807 vb = r600_nomm_get_vb_ptr(dev);
814 vb[0] = int2float(dx);
815 vb[1] = int2float(dy);
816 vb[2] = int2float(sx);
817 vb[3] = int2float(sy);
819 vb[4] = int2float(dx);
820 vb[5] = int2float(dy2);
821 vb[6] = int2float(sx);
822 vb[7] = int2float(sy2);
824 vb[8] = int2float(dx2);
825 vb[9] = int2float(dy2);
826 vb[10] = int2float(sx2);
827 vb[11] = int2float(sy2);
831 cb_format = COLOR_8_8_8_8;
832 tex_format = FMT_8_8_8_8;
835 cb_format = COLOR_5_6_5;
836 tex_format = FMT_5_6_5;
845 set_tex_resource(dev_priv, tex_format,
847 sy2, src_pitch / cpp,
850 cp_set_surface_sync(dev_priv,
851 R600_TC_ACTION_ENA, src_pitch * sy2, src_gpu_addr);
854 set_render_target(dev_priv, cb_format,
855 dst_pitch / cpp, dy2,
859 set_scissors(dev_priv, dx, dy, dx2, dy2);
861 /* Vertex buffer setup */
862 vb_addr = dev_priv->gart_buffers_offset +
863 dev_priv->blit_vb->offset +
864 dev_priv->blit_vb->used;
865 set_vtx_resource(dev_priv, vb_addr);
870 cp_set_surface_sync(dev_priv,
871 R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA,
872 dst_pitch * dy2, dst_gpu_addr);
874 dev_priv->blit_vb->used += 12 * 4;