1 @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2002, 2008,
3 @c Free Software Foundation, Inc.
4 @c This is part of the GAS manual.
5 @c For copying conditions, see the file as.texinfo.
9 @chapter SPARC Dependent Features
12 @node Machine Dependencies
13 @chapter SPARC Dependent Features
18 * Sparc-Opts:: Options
19 * Sparc-Aligned-Data:: Option to enforce aligned data
20 * Sparc-Syntax:: Syntax
21 * Sparc-Float:: Floating Point
22 * Sparc-Directives:: Sparc Machine Directives
28 @cindex options for SPARC
30 @cindex architectures, SPARC
31 @cindex SPARC architectures
32 The SPARC chip family includes several successive versions, using the same
33 core instruction set, but including a few additional instructions at
34 each version. There are exceptions to this however. For details on what
35 instructions each variant supports, please see the chip's architecture
38 By default, @code{@value{AS}} assumes the core instruction set (SPARC
39 v6), but ``bumps'' the architecture level as needed: it switches to
40 successively higher architectures as it encounters instructions that
41 only exist in the higher levels.
43 If not configured for SPARC v9 (@code{sparc64-*-*}) GAS will not bump
44 past sparclite by default, an option must be passed to enable the
47 GAS treats sparclite as being compatible with v8, unless an architecture
48 is explicitly requested. SPARC v9 is always incompatible with sparclite.
50 @c The order here is the same as the order of enum sparc_opcode_arch_val
51 @c to give the user a sense of the order of the "bumping".
73 @item -Av6 | -Av7 | -Av8 | -Aleon | -Asparclet | -Asparclite
74 @itemx -Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd | -Av8plusv
75 @itemx -Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9v
76 @itemx -Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima
77 @itemx -Asparcvis3 | -Asparcvis3r
78 Use one of the @samp{-A} options to select one of the SPARC
79 architectures explicitly. If you select an architecture explicitly,
80 @code{@value{AS}} reports a fatal error if it encounters an instruction
81 or feature requiring an incompatible or higher level.
83 @samp{-Av8plus}, @samp{-Av8plusa}, @samp{-Av8plusb}, @samp{-Av8plusc},
84 @samp{-Av8plusd}, and @samp{-Av8plusv} select a 32 bit environment.
86 @samp{-Av9}, @samp{-Av9a}, @samp{-Av9b}, @samp{-Av9c}, @samp{-Av9d}, and
87 @samp{-Av9v} select a 64 bit environment and are not available unless GAS
88 is explicitly configured with 64 bit environment support.
90 @samp{-Av8plusa} and @samp{-Av9a} enable the SPARC V9 instruction set with
91 UltraSPARC VIS 1.0 extensions.
93 @samp{-Av8plusb} and @samp{-Av9b} enable the UltraSPARC VIS 2.0 instructions,
94 as well as the instructions enabled by @samp{-Av8plusa} and @samp{-Av9a}.
96 @samp{-Av8plusc} and @samp{-Av9c} enable the UltraSPARC Niagara instructions,
97 as well as the instructions enabled by @samp{-Av8plusb} and @samp{-Av9b}.
99 @samp{-Av8plusd} and @samp{-Av9d} enable the floating point fused
100 multiply-add, VIS 3.0, and HPC extension instructions, as well as the
101 instructions enabled by @samp{-Av8plusc} and @samp{-Av9c}.
103 @samp{-Av8plusv} and @samp{-Av9v} enable the 'random', transactional
104 memory, floating point unfused multiply-add, integer multiply-add, and
105 cache sparing store instructions, as well as the instructions enabled
106 by @samp{-Av8plusd} and @samp{-Av9d}.
108 @samp{-Asparc} specifies a v9 environment. It is equivalent to
109 @samp{-Av9} if the word size is 64-bit, and @samp{-Av8plus} otherwise.
111 @samp{-Asparcvis} specifies a v9a environment. It is equivalent to
112 @samp{-Av9a} if the word size is 64-bit, and @samp{-Av8plusa} otherwise.
114 @samp{-Asparcvis2} specifies a v9b environment. It is equivalent to
115 @samp{-Av9b} if the word size is 64-bit, and @samp{-Av8plusb} otherwise.
117 @samp{-Asparcfmaf} specifies a v9b environment with the floating point
118 fused multiply-add instructions enabled.
120 @samp{-Asparcima} specifies a v9b environment with the integer
121 multiply-add instructions enabled.
123 @samp{-Asparcvis3} specifies a v9b environment with the VIS 3.0,
124 HPC , and floating point fused multiply-add instructions enabled.
126 @samp{-Asparcvis3r} specifies a v9b environment with the VIS 3.0,
127 HPC, transactional memory, random, and floating point unfused multiply-add
128 instructions enabled.
130 @item -xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc
131 @itemx -xarch=v8plusd | -xarch=v8plusv | -xarch=v9 | -xarch=v9a
132 @itemx -xarch=v9b | -xarch=v9c | -xarch=v9d | -xarch=v9v
133 @itemx -xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2
134 @itemx -xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3
135 @itemx -xarch=sparcvis3r
136 For compatibility with the SunOS v9 assembler. These options are
137 equivalent to -Av8plus, -Av8plusa, -Av8plusb, -Av8plusc, -Av8plusd,
138 -Av8plusv, -Av9, -Av9a, -Av9b, -Av9c, -Av9d, -Av9v, -Asparc, -Asparcvis,
139 -Asparcvis2, -Asparcfmaf, -Asparcima, -Asparcvis3, and -Asparcvis3r,
143 Warn whenever it is necessary to switch to another level.
144 If an architecture level is explicitly requested, GAS will not issue
145 warnings until that level is reached, and will then bump the level
146 as required (except between incompatible levels).
149 Select the word size, either 32 bits or 64 bits.
150 These options are only available with the ELF object file format,
151 and require that the necessary BFD support has been included.
154 @node Sparc-Aligned-Data
155 @section Enforcing aligned data
157 @cindex data alignment on SPARC
158 @cindex SPARC data alignment
159 SPARC GAS normally permits data to be misaligned. For example, it
160 permits the @code{.long} pseudo-op to be used on a byte boundary.
161 However, the native SunOS assemblers issue an error when they see
164 @kindex --enforce-aligned-data
165 You can use the @code{--enforce-aligned-data} option to make SPARC GAS
166 also issue an error about misaligned data, just as the SunOS
169 The @code{--enforce-aligned-data} option is not the default because gcc
170 issues misaligned data pseudo-ops when it initializes certain packed
171 data structures (structures defined using the @code{packed} attribute).
172 You may have to assemble with GAS in order to initialize packed data
173 structures in your own code.
176 @cindex syntax, SPARC
178 @section Sparc Syntax
179 The assembler syntax closely follows The Sparc Architecture Manual,
180 versions 8 and 9, as well as most extensions defined by Sun
181 for their UltraSPARC and Niagara line of processors.
184 * Sparc-Chars:: Special Characters
185 * Sparc-Regs:: Register Names
186 * Sparc-Constants:: Constant Names
187 * Sparc-Relocs:: Relocations
188 * Sparc-Size-Translations:: Size Translations
192 @subsection Special Characters
194 @cindex line comment character, Sparc
195 @cindex Sparc line comment character
196 A @samp{!} character appearing anywhere on a line indicates the start
197 of a comment that extends to the end of that line.
199 If a @samp{#} appears as the first character of a line then the whole
200 line is treated as a comment, but in this case the line could also be
201 a logical line number directive (@pxref{Comments}) or a preprocessor
202 control command (@pxref{Preprocessing}).
204 @cindex line separator, Sparc
205 @cindex statement separator, Sparc
206 @cindex Sparc line separator
207 @samp{;} can be used instead of a newline to separate statements.
210 @subsection Register Names
211 @cindex Sparc registers
212 @cindex register names, Sparc
214 The Sparc integer register file is broken down into global,
215 outgoing, local, and incoming.
219 The 8 global registers are referred to as @samp{%g@var{n}}.
222 The 8 outgoing registers are referred to as @samp{%o@var{n}}.
225 The 8 local registers are referred to as @samp{%l@var{n}}.
228 The 8 incoming registers are referred to as @samp{%i@var{n}}.
231 The frame pointer register @samp{%i6} can be referenced using
232 the alias @samp{%fp}.
235 The stack pointer register @samp{%o6} can be referenced using
236 the alias @samp{%sp}.
239 Floating point registers are simply referred to as @samp{%f@var{n}}.
240 When assembling for pre-V9, only 32 floating point registers
241 are available. For V9 and later there are 64, but there are
242 restrictions when referencing the upper 32 registers. They
243 can only be accessed as double or quad, and thus only even
244 or quad numbered accesses are allowed. For example, @samp{%f34}
245 is a legal floating point register, but @samp{%f35} is not.
247 Certain V9 instructions allow access to ancillary state registers.
248 Most simply they can be referred to as @samp{%asr@var{n}} where
249 @var{n} can be from 16 to 31. However, there are some aliases
250 defined to reference ASR registers defined for various UltraSPARC
255 The tick compare register is referred to as @samp{%tick_cmpr}.
258 The system tick register is referred to as @samp{%stick}. An alias,
259 @samp{%sys_tick}, exists but is deprecated and should not be used
263 The system tick compare register is referred to as @samp{%stick_cmpr}.
264 An alias, @samp{%sys_tick_cmpr}, exists but is deprecated and should
265 not be used by new software.
268 The software interrupt register is referred to as @samp{%softint}.
271 The set software interrupt register is referred to as @samp{%set_softint}.
272 The mnemonic @samp{%softint_set} is provided as an alias.
275 The clear software interrupt register is referred to as
276 @samp{%clear_softint}. The mnemonic @samp{%softint_clear} is provided
280 The performance instrumentation counters register is referred to as
284 The performance control register is referred to as @samp{%pcr}.
287 The graphics status register is referred to as @samp{%gsr}.
290 The V9 dispatch control register is referred to as @samp{%dcr}.
293 Various V9 branch and conditional move instructions allow
294 specification of which set of integer condition codes to
295 test. These are referred to as @samp{%xcc} and @samp{%icc}.
297 In V9, there are 4 sets of floating point condition codes
298 which are referred to as @samp{%fcc@var{n}}.
300 Several special privileged and non-privileged registers
305 The V9 address space identifier register is referred to as @samp{%asi}.
308 The V9 restorable windows register is referred to as @samp{%canrestore}.
311 The V9 savable windows register is referred to as @samp{%cansave}.
314 The V9 clean windows register is referred to as @samp{%cleanwin}.
317 The V9 current window pointer register is referred to as @samp{%cwp}.
320 The floating-point queue register is referred to as @samp{%fq}.
323 The V8 co-processor queue register is referred to as @samp{%cq}.
326 The floating point status register is referred to as @samp{%fsr}.
329 The other windows register is referred to as @samp{%otherwin}.
332 The V9 program counter register is referred to as @samp{%pc}.
335 The V9 next program counter register is referred to as @samp{%npc}.
338 The V9 processor interrupt level register is referred to as @samp{%pil}.
341 The V9 processor state register is referred to as @samp{%pstate}.
344 The trap base address register is referred to as @samp{%tba}.
347 The V9 tick register is referred to as @samp{%tick}.
350 The V9 trap level is referred to as @samp{%tl}.
353 The V9 trap program counter is referred to as @samp{%tpc}.
356 The V9 trap next program counter is referred to as @samp{%tnpc}.
359 The V9 trap state is referred to as @samp{%tstate}.
362 The V9 trap type is referred to as @samp{%tt}.
365 The V9 condition codes is referred to as @samp{%ccr}.
368 The V9 floating-point registers state is referred to as @samp{%fprs}.
371 The V9 version register is referred to as @samp{%ver}.
374 The V9 window state register is referred to as @samp{%wstate}.
377 The Y register is referred to as @samp{%y}.
380 The V8 window invalid mask register is referred to as @samp{%wim}.
383 The V8 processor state register is referred to as @samp{%psr}.
386 The V9 global register level register is referred to as @samp{%gl}.
389 Several special register names exist for hypervisor mode code:
393 The hyperprivileged processor state register is referred to as
397 The hyperprivileged trap state register is referred to as @samp{%htstate}.
400 The hyperprivileged interrupt pending register is referred to as
404 The hyperprivileged trap base address register is referred to as
408 The hyperprivileged implementation version register is referred
412 The hyperprivileged system tick compare register is referred
413 to as @samp{%hstick_cmpr}. Note that there is no @samp{%hstick}
414 register, the normal @samp{%stick} is used.
417 @node Sparc-Constants
418 @subsection Constants
419 @cindex Sparc constants
420 @cindex constants, Sparc
422 Several Sparc instructions take an immediate operand field for
423 which mnemonic names exist. Two such examples are @samp{membar}
424 and @samp{prefetch}. Another example are the set of V9
425 memory access instruction that allow specification of an
426 address space identifier.
428 The @samp{membar} instruction specifies a memory barrier that is
429 the defined by the operand which is a bitmask. The supported
434 @samp{#Sync} requests that all operations (including nonmemory
435 reference operations) appearing prior to the @code{membar} must have
436 been performed and the effects of any exceptions become visible before
437 any instructions after the @code{membar} may be initiated. This
438 corresponds to @code{membar} cmask field bit 2.
441 @samp{#MemIssue} requests that all memory reference operations
442 appearing prior to the @code{membar} must have been performed before
443 any memory operation after the @code{membar} may be initiated. This
444 corresponds to @code{membar} cmask field bit 1.
447 @samp{#Lookaside} requests that a store appearing prior to the
448 @code{membar} must complete before any load following the
449 @code{membar} referencing the same address can be initiated. This
450 corresponds to @code{membar} cmask field bit 0.
453 @samp{#StoreStore} defines that the effects of all stores appearing
454 prior to the @code{membar} instruction must be visible to all
455 processors before the effect of any stores following the
456 @code{membar}. Equivalent to the deprecated @code{stbar} instruction.
457 This corresponds to @code{membar} mmask field bit 3.
460 @samp{#LoadStore} defines all loads appearing prior to the
461 @code{membar} instruction must have been performed before the effect
462 of any stores following the @code{membar} is visible to any other
463 processor. This corresponds to @code{membar} mmask field bit 2.
466 @samp{#StoreLoad} defines that the effects of all stores appearing
467 prior to the @code{membar} instruction must be visible to all
468 processors before loads following the @code{membar} may be performed.
469 This corresponds to @code{membar} mmask field bit 1.
472 @samp{#LoadLoad} defines that all loads appearing prior to the
473 @code{membar} instruction must have been performed before any loads
474 following the @code{membar} may be performed. This corresponds to
475 @code{membar} mmask field bit 0.
479 These values can be ored together, for example:
483 membar #StoreLoad | #LoadLoad
484 membar #StoreLoad | #StoreStore
487 The @code{prefetch} and @code{prefetcha} instructions take a prefetch
488 function code. The following prefetch function code constant
489 mnemonics are available:
493 @samp{#n_reads} requests a prefetch for several reads, and corresponds
494 to a prefetch function code of 0.
496 @samp{#one_read} requests a prefetch for one read, and corresponds
497 to a prefetch function code of 1.
499 @samp{#n_writes} requests a prefetch for several writes (and possibly
500 reads), and corresponds to a prefetch function code of 2.
502 @samp{#one_write} requests a prefetch for one write, and corresponds
503 to a prefetch function code of 3.
505 @samp{#page} requests a prefetch page, and corresponds to a prefetch
508 @samp{#invalidate} requests a prefetch invalidate, and corresponds to
509 a prefetch function code of 16.
511 @samp{#unified} requests a prefetch to the nearest unified cache, and
512 corresponds to a prefetch function code of 17.
514 @samp{#n_reads_strong} requests a strong prefetch for several reads,
515 and corresponds to a prefetch function code of 20.
517 @samp{#one_read_strong} requests a strong prefetch for one read,
518 and corresponds to a prefetch function code of 21.
520 @samp{#n_writes_strong} requests a strong prefetch for several writes,
521 and corresponds to a prefetch function code of 22.
523 @samp{#one_write_strong} requests a strong prefetch for one write,
524 and corresponds to a prefetch function code of 23.
526 Onle one prefetch code may be specified. Here are some examples:
529 prefetch [%l0 + %l2], #one_read
530 prefetch [%g2 + 8], #n_writes
531 prefetcha [%g1] 0x8, #unified
532 prefetcha [%o0 + 0x10] %asi, #n_reads
535 The actual behavior of a given prefetch function code is processor
536 specific. If a processor does not implement a given prefetch
537 function code, it will treat the prefetch instruction as a nop.
539 For instructions that accept an immediate address space identifier,
540 @code{@value{AS}} provides many mnemonics corresponding to
541 V9 defined as well as UltraSPARC and Niagara extended values.
542 For example, @samp{#ASI_P} and @samp{#ASI_BLK_INIT_QUAD_LDD_AIUS}.
543 See the V9 and processor specific manuals for details.
548 @subsection Relocations
549 @cindex Sparc relocations
550 @cindex relocations, Sparc
552 ELF relocations are available as defined in the 32-bit and 64-bit
553 Sparc ELF specifications.
555 @code{R_SPARC_HI22} is obtained using @samp{%hi} and @code{R_SPARC_LO10}
556 is obtained using @samp{%lo}. Likewise @code{R_SPARC_HIX22} is
557 obtained from @samp{%hix} and @code{R_SPARC_LOX10} is obtained
558 using @samp{%lox}. For example:
561 sethi %hi(symbol), %g1
562 or %g1, %lo(symbol), %g1
564 sethi %hix(symbol), %g1
565 xor %g1, %lox(symbol), %g1
568 These ``high'' mnemonics extract bits 31:10 of their operand,
569 and the ``low'' mnemonics extract bits 9:0 of their operand.
571 V9 code model relocations can be requested as follows:
575 @code{R_SPARC_HH22} is requested using @samp{%hh}. It can
576 also be generated using @samp{%uhi}.
578 @code{R_SPARC_HM10} is requested using @samp{%hm}. It can
579 also be generated using @samp{%ulo}.
581 @code{R_SPARC_LM22} is requested using @samp{%lm}.
584 @code{R_SPARC_H44} is requested using @samp{%h44}.
586 @code{R_SPARC_M44} is requested using @samp{%m44}.
588 @code{R_SPARC_L44} is requested using @samp{%l44} or @samp{%l34}.
590 @code{R_SPARC_H34} is requested using @samp{%h34}.
593 The @samp{%l34} generates a @code{R_SPARC_L44} relocation because it
594 calculates the necessary value, and therefore no explicit
595 @code{R_SPARC_L34} relocation needed to be created for this purpose.
597 The @samp{%h34} and @samp{%l34} relocations are used for the abs34 code
598 model. Here is an example abs34 address generation sequence:
601 sethi %h34(symbol), %g1
603 or %g1, %l34(symbol), %g1
606 The PC relative relocation @code{R_SPARC_PC22} can be obtained by
607 enclosing an operand inside of @samp{%pc22}. Likewise, the
608 @code{R_SPARC_PC10} relocation can be obtained using @samp{%pc10}.
609 These are mostly used when assembling PIC code. For example, the
610 standard PIC sequence on Sparc to get the base of the global offset
611 table, PC relative, into a register, can be performed as:
614 sethi %pc22(_GLOBAL_OFFSET_TABLE_-4), %l7
615 add %l7, %pc10(_GLOBAL_OFFSET_TABLE_+4), %l7
618 Several relocations exist to allow the link editor to potentially
619 optimize GOT data references. The @code{R_SPARC_GOTDATA_OP_HIX22}
620 relocation can obtained by enclosing an operand inside of
621 @samp{%gdop_hix22}. The @code{R_SPARC_GOTDATA_OP_LOX10}
622 relocation can obtained by enclosing an operand inside of
623 @samp{%gdop_lox10}. Likewise, @code{R_SPARC_GOTDATA_OP} can be
624 obtained by enclosing an operand inside of @samp{%gdop}.
625 For example, assuming the GOT base is in register @code{%l7}:
628 sethi %gdop_hix22(symbol), %l1
629 xor %l1, %gdop_lox10(symbol), %l1
630 ld [%l7 + %l1], %l2, %gdop(symbol)
633 There are many relocations that can be requested for access to
634 thread local storage variables. All of the Sparc TLS mnemonics
639 @code{R_SPARC_TLS_GD_HI22} is requested using @samp{%tgd_hi22}.
641 @code{R_SPARC_TLS_GD_LO10} is requested using @samp{%tgd_lo10}.
643 @code{R_SPARC_TLS_GD_ADD} is requested using @samp{%tgd_add}.
645 @code{R_SPARC_TLS_GD_CALL} is requested using @samp{%tgd_call}.
648 @code{R_SPARC_TLS_LDM_HI22} is requested using @samp{%tldm_hi22}.
650 @code{R_SPARC_TLS_LDM_LO10} is requested using @samp{%tldm_lo10}.
652 @code{R_SPARC_TLS_LDM_ADD} is requested using @samp{%tldm_add}.
654 @code{R_SPARC_TLS_LDM_CALL} is requested using @samp{%tldm_call}.
657 @code{R_SPARC_TLS_LDO_HIX22} is requested using @samp{%tldo_hix22}.
659 @code{R_SPARC_TLS_LDO_LOX10} is requested using @samp{%tldo_lox10}.
661 @code{R_SPARC_TLS_LDO_ADD} is requested using @samp{%tldo_add}.
664 @code{R_SPARC_TLS_IE_HI22} is requested using @samp{%tie_hi22}.
666 @code{R_SPARC_TLS_IE_LO10} is requested using @samp{%tie_lo10}.
668 @code{R_SPARC_TLS_IE_LD} is requested using @samp{%tie_ld}.
670 @code{R_SPARC_TLS_IE_LDX} is requested using @samp{%tie_ldx}.
672 @code{R_SPARC_TLS_IE_ADD} is requested using @samp{%tie_add}.
675 @code{R_SPARC_TLS_LE_HIX22} is requested using @samp{%tle_hix22}.
677 @code{R_SPARC_TLS_LE_LOX10} is requested using @samp{%tle_lox10}.
680 Here are some example TLS model sequences.
682 First, General Dynamic:
685 sethi %tgd_hi22(symbol), %l1
686 add %l1, %tgd_lo10(symbol), %l1
687 add %l7, %l1, %o0, %tgd_add(symbol)
688 call __tls_get_addr, %tgd_call(symbol)
695 sethi %tldm_hi22(symbol), %l1
696 add %l1, %tldm_lo10(symbol), %l1
697 add %l7, %l1, %o0, %tldm_add(symbol)
698 call __tls_get_addr, %tldm_call(symbol)
701 sethi %tldo_hix22(symbol), %l1
702 xor %l1, %tldo_lox10(symbol), %l1
703 add %o0, %l1, %l1, %tldo_add(symbol)
709 sethi %tie_hi22(symbol), %l1
710 add %l1, %tie_lo10(symbol), %l1
711 ld [%l7 + %l1], %o0, %tie_ld(symbol)
712 add %g7, %o0, %o0, %tie_add(symbol)
714 sethi %tie_hi22(symbol), %l1
715 add %l1, %tie_lo10(symbol), %l1
716 ldx [%l7 + %l1], %o0, %tie_ldx(symbol)
717 add %g7, %o0, %o0, %tie_add(symbol)
720 And finally, Local Exec:
723 sethi %tle_hix22(symbol), %l1
724 add %l1, %tle_lox10(symbol), %l1
728 When assembling for 64-bit, and a secondary constant addend is
729 specified in an address expression that would normally generate
730 an @code{R_SPARC_LO10} relocation, the assembler will emit an
731 @code{R_SPARC_OLO10} instead.
733 @node Sparc-Size-Translations
734 @subsection Size Translations
735 @cindex Sparc size translations
736 @cindex size, translations, Sparc
738 Often it is desirable to write code in an operand size agnostic
739 manner. @code{@value{AS}} provides support for this via
740 operand size opcode translations. Translations are supported
741 for loads, stores, shifts, compare-and-swap atomics, and the
742 @samp{clr} synthetic instruction.
744 If generating 32-bit code, @code{@value{AS}} will generate the
745 32-bit opcode. Whereas if 64-bit code is being generated,
746 the 64-bit opcode will be emitted. For example @code{ldn}
747 will be transformed into @code{ld} for 32-bit code and
748 @code{ldx} for 64-bit code.
750 Here is an example meant to demonstrate all the supported
762 casna [%o0] %asi, %o1, %o2
766 In 32-bit mode @code{@value{AS}} will emit:
777 casa [%o0] %asi, %o1, %o2
781 And in 64-bit mode @code{@value{AS}} will emit:
792 casxa [%o0] %asi, %o1, %o2
796 Finally, the @samp{.nword} translating directive is supported
797 as well. It is documented in the section on Sparc machine
801 @section Floating Point
803 @cindex floating point, SPARC (@sc{ieee})
804 @cindex SPARC floating point (@sc{ieee})
805 The Sparc uses @sc{ieee} floating-point numbers.
807 @node Sparc-Directives
808 @section Sparc Machine Directives
810 @cindex SPARC machine directives
811 @cindex machine directives, SPARC
812 The Sparc version of @code{@value{AS}} supports the following additional
816 @cindex @code{align} directive, SPARC
818 This must be followed by the desired alignment in bytes.
820 @cindex @code{common} directive, SPARC
822 This must be followed by a symbol name, a positive number, and
823 @code{"bss"}. This behaves somewhat like @code{.comm}, but the
826 @cindex @code{half} directive, SPARC
828 This is functionally identical to @code{.short}.
830 @cindex @code{nword} directive, SPARC
832 On the Sparc, the @code{.nword} directive produces native word sized value,
833 ie. if assembling with -32 it is equivalent to @code{.word}, if assembling
834 with -64 it is equivalent to @code{.xword}.
836 @cindex @code{proc} directive, SPARC
838 This directive is ignored. Any text following it on the same
839 line is also ignored.
841 @cindex @code{register} directive, SPARC
843 This directive declares use of a global application or system register.
844 It must be followed by a register name %g2, %g3, %g6 or %g7, comma and
845 the symbol name for that register. If symbol name is @code{#scratch},
846 it is a scratch register, if it is @code{#ignore}, it just suppresses any
847 errors about using undeclared global register, but does not emit any
848 information about it into the object file. This can be useful e.g. if you
849 save the register before use and restore it after.
851 @cindex @code{reserve} directive, SPARC
853 This must be followed by a symbol name, a positive number, and
854 @code{"bss"}. This behaves somewhat like @code{.lcomm}, but the
857 @cindex @code{seg} directive, SPARC
859 This must be followed by @code{"text"}, @code{"data"}, or
860 @code{"data1"}. It behaves like @code{.text}, @code{.data}, or
863 @cindex @code{skip} directive, SPARC
865 This is functionally identical to the @code{.space} directive.
867 @cindex @code{word} directive, SPARC
869 On the Sparc, the @code{.word} directive produces 32 bit values,
870 instead of the 16 bit values it produces on many other machines.
872 @cindex @code{xword} directive, SPARC
874 On the Sparc V9 processor, the @code{.xword} directive produces