1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2014 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma, disassemble_info *);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma get64 (void);
58 static bfd_signed_vma get32 (void);
59 static bfd_signed_vma get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VEXI4_Fixup (int, int);
99 static void VZERO_Fixup (int, int);
100 static void VCMP_Fixup (int, int);
101 static void VPCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void BND_Fixup (int, int);
112 static void HLE_Fixup1 (int, int);
113 static void HLE_Fixup2 (int, int);
114 static void HLE_Fixup3 (int, int);
115 static void CMPXCHG8B_Fixup (int, int);
116 static void XMM_Fixup (int, int);
117 static void CRC32_Fixup (int, int);
118 static void FXSAVE_Fixup (int, int);
119 static void OP_LWPCB_E (int, int);
120 static void OP_LWP_E (int, int);
121 static void OP_Vex_2src_1 (int, int);
122 static void OP_Vex_2src_2 (int, int);
124 static void MOVBE_Fixup (int, int);
126 static void OP_Mask (int, int);
129 /* Points to first byte not fetched. */
130 bfd_byte *max_fetched;
131 bfd_byte the_buffer[MAX_MNEM_SIZE];
134 OPCODES_SIGJMP_BUF bailout;
144 enum address_mode address_mode;
146 /* Flags for the prefixes for the current instruction. See below. */
149 /* REX prefix the current instruction. See below. */
151 /* Bits of REX we've already used. */
153 /* REX bits in original REX prefix ignored. */
154 static int rex_ignored;
155 /* Mark parts used in the REX prefix. When we are testing for
156 empty prefix (for 8bit register REX extension), just mask it
157 out. Otherwise test for REX bit is excuse for existence of REX
158 only in case value is nonzero. */
159 #define USED_REX(value) \
164 rex_used |= (value) | REX_OPCODE; \
167 rex_used |= REX_OPCODE; \
170 /* Flags for prefixes which we somehow handled when printing the
171 current instruction. */
172 static int used_prefixes;
174 /* Flags stored in PREFIXES. */
175 #define PREFIX_REPZ 1
176 #define PREFIX_REPNZ 2
177 #define PREFIX_LOCK 4
179 #define PREFIX_SS 0x10
180 #define PREFIX_DS 0x20
181 #define PREFIX_ES 0x40
182 #define PREFIX_FS 0x80
183 #define PREFIX_GS 0x100
184 #define PREFIX_DATA 0x200
185 #define PREFIX_ADDR 0x400
186 #define PREFIX_FWAIT 0x800
188 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
189 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
191 #define FETCH_DATA(info, addr) \
192 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
193 ? 1 : fetch_data ((info), (addr)))
196 fetch_data (struct disassemble_info *info, bfd_byte *addr)
199 struct dis_private *priv = (struct dis_private *) info->private_data;
200 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
202 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
203 status = (*info->read_memory_func) (start,
205 addr - priv->max_fetched,
211 /* If we did manage to read at least one byte, then
212 print_insn_i386 will do something sensible. Otherwise, print
213 an error. We do that here because this is where we know
215 if (priv->max_fetched == priv->the_buffer)
216 (*info->memory_error_func) (status, start, info);
217 OPCODES_SIGLONGJMP (priv->bailout, 1);
220 priv->max_fetched = addr;
224 #define XX { NULL, 0 }
225 #define Bad_Opcode NULL, { { NULL, 0 } }
227 #define Eb { OP_E, b_mode }
228 #define Ebnd { OP_E, bnd_mode }
229 #define EbS { OP_E, b_swap_mode }
230 #define Ev { OP_E, v_mode }
231 #define Ev_bnd { OP_E, v_bnd_mode }
232 #define EvS { OP_E, v_swap_mode }
233 #define Ed { OP_E, d_mode }
234 #define Edq { OP_E, dq_mode }
235 #define Edqw { OP_E, dqw_mode }
236 #define EdqwS { OP_E, dqw_swap_mode }
237 #define Edqb { OP_E, dqb_mode }
238 #define Edb { OP_E, db_mode }
239 #define Edw { OP_E, dw_mode }
240 #define Edqd { OP_E, dqd_mode }
241 #define Eq { OP_E, q_mode }
242 #define indirEv { OP_indirE, stack_v_mode }
243 #define indirEp { OP_indirE, f_mode }
244 #define stackEv { OP_E, stack_v_mode }
245 #define Em { OP_E, m_mode }
246 #define Ew { OP_E, w_mode }
247 #define M { OP_M, 0 } /* lea, lgdt, etc. */
248 #define Ma { OP_M, a_mode }
249 #define Mb { OP_M, b_mode }
250 #define Md { OP_M, d_mode }
251 #define Mo { OP_M, o_mode }
252 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
253 #define Mq { OP_M, q_mode }
254 #define Mx { OP_M, x_mode }
255 #define Mxmm { OP_M, xmm_mode }
256 #define Gb { OP_G, b_mode }
257 #define Gbnd { OP_G, bnd_mode }
258 #define Gv { OP_G, v_mode }
259 #define Gd { OP_G, d_mode }
260 #define Gdq { OP_G, dq_mode }
261 #define Gm { OP_G, m_mode }
262 #define Gw { OP_G, w_mode }
263 #define Rd { OP_R, d_mode }
264 #define Rdq { OP_R, dq_mode }
265 #define Rm { OP_R, m_mode }
266 #define Ib { OP_I, b_mode }
267 #define sIb { OP_sI, b_mode } /* sign extened byte */
268 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
269 #define Iv { OP_I, v_mode }
270 #define sIv { OP_sI, v_mode }
271 #define Iq { OP_I, q_mode }
272 #define Iv64 { OP_I64, v_mode }
273 #define Iw { OP_I, w_mode }
274 #define I1 { OP_I, const_1_mode }
275 #define Jb { OP_J, b_mode }
276 #define Jv { OP_J, v_mode }
277 #define Cm { OP_C, m_mode }
278 #define Dm { OP_D, m_mode }
279 #define Td { OP_T, d_mode }
280 #define Skip_MODRM { OP_Skip_MODRM, 0 }
282 #define RMeAX { OP_REG, eAX_reg }
283 #define RMeBX { OP_REG, eBX_reg }
284 #define RMeCX { OP_REG, eCX_reg }
285 #define RMeDX { OP_REG, eDX_reg }
286 #define RMeSP { OP_REG, eSP_reg }
287 #define RMeBP { OP_REG, eBP_reg }
288 #define RMeSI { OP_REG, eSI_reg }
289 #define RMeDI { OP_REG, eDI_reg }
290 #define RMrAX { OP_REG, rAX_reg }
291 #define RMrBX { OP_REG, rBX_reg }
292 #define RMrCX { OP_REG, rCX_reg }
293 #define RMrDX { OP_REG, rDX_reg }
294 #define RMrSP { OP_REG, rSP_reg }
295 #define RMrBP { OP_REG, rBP_reg }
296 #define RMrSI { OP_REG, rSI_reg }
297 #define RMrDI { OP_REG, rDI_reg }
298 #define RMAL { OP_REG, al_reg }
299 #define RMCL { OP_REG, cl_reg }
300 #define RMDL { OP_REG, dl_reg }
301 #define RMBL { OP_REG, bl_reg }
302 #define RMAH { OP_REG, ah_reg }
303 #define RMCH { OP_REG, ch_reg }
304 #define RMDH { OP_REG, dh_reg }
305 #define RMBH { OP_REG, bh_reg }
306 #define RMAX { OP_REG, ax_reg }
307 #define RMDX { OP_REG, dx_reg }
309 #define eAX { OP_IMREG, eAX_reg }
310 #define eBX { OP_IMREG, eBX_reg }
311 #define eCX { OP_IMREG, eCX_reg }
312 #define eDX { OP_IMREG, eDX_reg }
313 #define eSP { OP_IMREG, eSP_reg }
314 #define eBP { OP_IMREG, eBP_reg }
315 #define eSI { OP_IMREG, eSI_reg }
316 #define eDI { OP_IMREG, eDI_reg }
317 #define AL { OP_IMREG, al_reg }
318 #define CL { OP_IMREG, cl_reg }
319 #define DL { OP_IMREG, dl_reg }
320 #define BL { OP_IMREG, bl_reg }
321 #define AH { OP_IMREG, ah_reg }
322 #define CH { OP_IMREG, ch_reg }
323 #define DH { OP_IMREG, dh_reg }
324 #define BH { OP_IMREG, bh_reg }
325 #define AX { OP_IMREG, ax_reg }
326 #define DX { OP_IMREG, dx_reg }
327 #define zAX { OP_IMREG, z_mode_ax_reg }
328 #define indirDX { OP_IMREG, indir_dx_reg }
330 #define Sw { OP_SEG, w_mode }
331 #define Sv { OP_SEG, v_mode }
332 #define Ap { OP_DIR, 0 }
333 #define Ob { OP_OFF64, b_mode }
334 #define Ov { OP_OFF64, v_mode }
335 #define Xb { OP_DSreg, eSI_reg }
336 #define Xv { OP_DSreg, eSI_reg }
337 #define Xz { OP_DSreg, eSI_reg }
338 #define Yb { OP_ESreg, eDI_reg }
339 #define Yv { OP_ESreg, eDI_reg }
340 #define DSBX { OP_DSreg, eBX_reg }
342 #define es { OP_REG, es_reg }
343 #define ss { OP_REG, ss_reg }
344 #define cs { OP_REG, cs_reg }
345 #define ds { OP_REG, ds_reg }
346 #define fs { OP_REG, fs_reg }
347 #define gs { OP_REG, gs_reg }
349 #define MX { OP_MMX, 0 }
350 #define XM { OP_XMM, 0 }
351 #define XMScalar { OP_XMM, scalar_mode }
352 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
353 #define XMM { OP_XMM, xmm_mode }
354 #define XMxmmq { OP_XMM, xmmq_mode }
355 #define EM { OP_EM, v_mode }
356 #define EMS { OP_EM, v_swap_mode }
357 #define EMd { OP_EM, d_mode }
358 #define EMx { OP_EM, x_mode }
359 #define EXw { OP_EX, w_mode }
360 #define EXd { OP_EX, d_mode }
361 #define EXdScalar { OP_EX, d_scalar_mode }
362 #define EXdS { OP_EX, d_swap_mode }
363 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
364 #define EXq { OP_EX, q_mode }
365 #define EXqScalar { OP_EX, q_scalar_mode }
366 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
367 #define EXqS { OP_EX, q_swap_mode }
368 #define EXx { OP_EX, x_mode }
369 #define EXxS { OP_EX, x_swap_mode }
370 #define EXxmm { OP_EX, xmm_mode }
371 #define EXymm { OP_EX, ymm_mode }
372 #define EXxmmq { OP_EX, xmmq_mode }
373 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
374 #define EXxmm_mb { OP_EX, xmm_mb_mode }
375 #define EXxmm_mw { OP_EX, xmm_mw_mode }
376 #define EXxmm_md { OP_EX, xmm_md_mode }
377 #define EXxmm_mq { OP_EX, xmm_mq_mode }
378 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
379 #define EXxmmdw { OP_EX, xmmdw_mode }
380 #define EXxmmqd { OP_EX, xmmqd_mode }
381 #define EXymmq { OP_EX, ymmq_mode }
382 #define EXVexWdq { OP_EX, vex_w_dq_mode }
383 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
384 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
385 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
386 #define MS { OP_MS, v_mode }
387 #define XS { OP_XS, v_mode }
388 #define EMCq { OP_EMC, q_mode }
389 #define MXC { OP_MXC, 0 }
390 #define OPSUF { OP_3DNowSuffix, 0 }
391 #define CMP { CMP_Fixup, 0 }
392 #define XMM0 { XMM_Fixup, 0 }
393 #define FXSAVE { FXSAVE_Fixup, 0 }
394 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
395 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
397 #define Vex { OP_VEX, vex_mode }
398 #define VexScalar { OP_VEX, vex_scalar_mode }
399 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
400 #define Vex128 { OP_VEX, vex128_mode }
401 #define Vex256 { OP_VEX, vex256_mode }
402 #define VexGdq { OP_VEX, dq_mode }
403 #define VexI4 { VEXI4_Fixup, 0}
404 #define EXdVex { OP_EX_Vex, d_mode }
405 #define EXdVexS { OP_EX_Vex, d_swap_mode }
406 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
407 #define EXqVex { OP_EX_Vex, q_mode }
408 #define EXqVexS { OP_EX_Vex, q_swap_mode }
409 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
410 #define EXVexW { OP_EX_VexW, x_mode }
411 #define EXdVexW { OP_EX_VexW, d_mode }
412 #define EXqVexW { OP_EX_VexW, q_mode }
413 #define EXVexImmW { OP_EX_VexImmW, x_mode }
414 #define XMVex { OP_XMM_Vex, 0 }
415 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
416 #define XMVexW { OP_XMM_VexW, 0 }
417 #define XMVexI4 { OP_REG_VexI4, x_mode }
418 #define PCLMUL { PCLMUL_Fixup, 0 }
419 #define VZERO { VZERO_Fixup, 0 }
420 #define VCMP { VCMP_Fixup, 0 }
421 #define VPCMP { VPCMP_Fixup, 0 }
423 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
424 #define EXxEVexS { OP_Rounding, evex_sae_mode }
426 #define XMask { OP_Mask, mask_mode }
427 #define MaskG { OP_G, mask_mode }
428 #define MaskE { OP_E, mask_mode }
429 #define MaskBDE { OP_E, mask_bd_mode }
430 #define MaskR { OP_R, mask_mode }
431 #define MaskVex { OP_VEX, mask_mode }
433 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
434 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
435 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
436 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
438 /* Used handle "rep" prefix for string instructions. */
439 #define Xbr { REP_Fixup, eSI_reg }
440 #define Xvr { REP_Fixup, eSI_reg }
441 #define Ybr { REP_Fixup, eDI_reg }
442 #define Yvr { REP_Fixup, eDI_reg }
443 #define Yzr { REP_Fixup, eDI_reg }
444 #define indirDXr { REP_Fixup, indir_dx_reg }
445 #define ALr { REP_Fixup, al_reg }
446 #define eAXr { REP_Fixup, eAX_reg }
448 /* Used handle HLE prefix for lockable instructions. */
449 #define Ebh1 { HLE_Fixup1, b_mode }
450 #define Evh1 { HLE_Fixup1, v_mode }
451 #define Ebh2 { HLE_Fixup2, b_mode }
452 #define Evh2 { HLE_Fixup2, v_mode }
453 #define Ebh3 { HLE_Fixup3, b_mode }
454 #define Evh3 { HLE_Fixup3, v_mode }
456 #define BND { BND_Fixup, 0 }
458 #define cond_jump_flag { NULL, cond_jump_mode }
459 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
461 /* bits in sizeflag */
462 #define SUFFIX_ALWAYS 4
470 /* byte operand with operand swapped */
472 /* byte operand, sign extend like 'T' suffix */
474 /* operand size depends on prefixes */
476 /* operand size depends on prefixes with operand swapped */
480 /* double word operand */
482 /* double word operand with operand swapped */
484 /* quad word operand */
486 /* quad word operand with operand swapped */
488 /* ten-byte operand */
490 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
491 broadcast enabled. */
493 /* Similar to x_mode, but with different EVEX mem shifts. */
495 /* Similar to x_mode, but with disabled broadcast. */
497 /* Similar to x_mode, but with operands swapped and disabled broadcast
500 /* 16-byte XMM operand */
502 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
503 memory operand (depending on vector length). Broadcast isn't
506 /* Same as xmmq_mode, but broadcast is allowed. */
507 evex_half_bcst_xmmq_mode,
508 /* XMM register or byte memory operand */
510 /* XMM register or word memory operand */
512 /* XMM register or double word memory operand */
514 /* XMM register or quad word memory operand */
516 /* XMM register or double/quad word memory operand, depending on
519 /* 16-byte XMM, word, double word or quad word operand. */
521 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
523 /* 32-byte YMM operand */
525 /* quad word, ymmword or zmmword memory operand. */
527 /* 32-byte YMM or 16-byte word operand */
529 /* d_mode in 32bit, q_mode in 64bit mode. */
531 /* pair of v_mode operands */
536 /* operand size depends on REX prefixes. */
538 /* registers like dq_mode, memory like w_mode. */
542 /* 4- or 6-byte pointer operand */
545 /* v_mode for stack-related opcodes. */
547 /* non-quad operand size depends on prefixes */
549 /* 16-byte operand */
551 /* registers like dq_mode, memory like b_mode. */
553 /* registers like d_mode, memory like b_mode. */
555 /* registers like d_mode, memory like w_mode. */
557 /* registers like dq_mode, memory like d_mode. */
559 /* normal vex mode */
561 /* 128bit vex mode */
563 /* 256bit vex mode */
565 /* operand size depends on the VEX.W bit. */
568 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
569 vex_vsib_d_w_dq_mode,
570 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
572 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
573 vex_vsib_q_w_dq_mode,
574 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
577 /* scalar, ignore vector length. */
579 /* like d_mode, ignore vector length. */
581 /* like d_swap_mode, ignore vector length. */
583 /* like q_mode, ignore vector length. */
585 /* like q_swap_mode, ignore vector length. */
587 /* like vex_mode, ignore vector length. */
589 /* like vex_w_dq_mode, ignore vector length. */
590 vex_scalar_w_dq_mode,
592 /* Static rounding. */
594 /* Supress all exceptions. */
597 /* Mask register operand. */
599 /* Mask register operand. */
666 #define FLOAT NULL, { { NULL, FLOATCODE } }
668 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
669 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
670 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
671 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
672 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
673 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
674 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
675 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
676 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
677 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
678 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
679 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
680 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
796 MOD_VEX_0F12_PREFIX_0,
798 MOD_VEX_0F16_PREFIX_0,
814 MOD_VEX_0FD7_PREFIX_2,
815 MOD_VEX_0FE7_PREFIX_2,
816 MOD_VEX_0FF0_PREFIX_3,
817 MOD_VEX_0F381A_PREFIX_2,
818 MOD_VEX_0F382A_PREFIX_2,
819 MOD_VEX_0F382C_PREFIX_2,
820 MOD_VEX_0F382D_PREFIX_2,
821 MOD_VEX_0F382E_PREFIX_2,
822 MOD_VEX_0F382F_PREFIX_2,
823 MOD_VEX_0F385A_PREFIX_2,
824 MOD_VEX_0F388C_PREFIX_2,
825 MOD_VEX_0F388E_PREFIX_2,
827 MOD_EVEX_0F10_PREFIX_1,
828 MOD_EVEX_0F10_PREFIX_3,
829 MOD_EVEX_0F11_PREFIX_1,
830 MOD_EVEX_0F11_PREFIX_3,
831 MOD_EVEX_0F12_PREFIX_0,
832 MOD_EVEX_0F16_PREFIX_0,
833 MOD_EVEX_0F38C6_REG_1,
834 MOD_EVEX_0F38C6_REG_2,
835 MOD_EVEX_0F38C6_REG_5,
836 MOD_EVEX_0F38C6_REG_6,
837 MOD_EVEX_0F38C7_REG_1,
838 MOD_EVEX_0F38C7_REG_2,
839 MOD_EVEX_0F38C7_REG_5,
840 MOD_EVEX_0F38C7_REG_6
904 PREFIX_RM_0_0FAE_REG_7,
1034 PREFIX_VEX_0F71_REG_2,
1035 PREFIX_VEX_0F71_REG_4,
1036 PREFIX_VEX_0F71_REG_6,
1037 PREFIX_VEX_0F72_REG_2,
1038 PREFIX_VEX_0F72_REG_4,
1039 PREFIX_VEX_0F72_REG_6,
1040 PREFIX_VEX_0F73_REG_2,
1041 PREFIX_VEX_0F73_REG_3,
1042 PREFIX_VEX_0F73_REG_6,
1043 PREFIX_VEX_0F73_REG_7,
1215 PREFIX_VEX_0F38F3_REG_1,
1216 PREFIX_VEX_0F38F3_REG_2,
1217 PREFIX_VEX_0F38F3_REG_3,
1334 PREFIX_EVEX_0F71_REG_2,
1335 PREFIX_EVEX_0F71_REG_4,
1336 PREFIX_EVEX_0F71_REG_6,
1337 PREFIX_EVEX_0F72_REG_0,
1338 PREFIX_EVEX_0F72_REG_1,
1339 PREFIX_EVEX_0F72_REG_2,
1340 PREFIX_EVEX_0F72_REG_4,
1341 PREFIX_EVEX_0F72_REG_6,
1342 PREFIX_EVEX_0F73_REG_2,
1343 PREFIX_EVEX_0F73_REG_3,
1344 PREFIX_EVEX_0F73_REG_6,
1345 PREFIX_EVEX_0F73_REG_7,
1528 PREFIX_EVEX_0F38C6_REG_1,
1529 PREFIX_EVEX_0F38C6_REG_2,
1530 PREFIX_EVEX_0F38C6_REG_5,
1531 PREFIX_EVEX_0F38C6_REG_6,
1532 PREFIX_EVEX_0F38C7_REG_1,
1533 PREFIX_EVEX_0F38C7_REG_2,
1534 PREFIX_EVEX_0F38C7_REG_5,
1535 PREFIX_EVEX_0F38C7_REG_6,
1622 THREE_BYTE_0F38 = 0,
1650 VEX_LEN_0F10_P_1 = 0,
1654 VEX_LEN_0F12_P_0_M_0,
1655 VEX_LEN_0F12_P_0_M_1,
1658 VEX_LEN_0F16_P_0_M_0,
1659 VEX_LEN_0F16_P_0_M_1,
1723 VEX_LEN_0FAE_R_2_M_0,
1724 VEX_LEN_0FAE_R_3_M_0,
1733 VEX_LEN_0F381A_P_2_M_0,
1736 VEX_LEN_0F385A_P_2_M_0,
1743 VEX_LEN_0F38F3_R_1_P_0,
1744 VEX_LEN_0F38F3_R_2_P_0,
1745 VEX_LEN_0F38F3_R_3_P_0,
1791 VEX_LEN_0FXOP_08_CC,
1792 VEX_LEN_0FXOP_08_CD,
1793 VEX_LEN_0FXOP_08_CE,
1794 VEX_LEN_0FXOP_08_CF,
1795 VEX_LEN_0FXOP_08_EC,
1796 VEX_LEN_0FXOP_08_ED,
1797 VEX_LEN_0FXOP_08_EE,
1798 VEX_LEN_0FXOP_08_EF,
1799 VEX_LEN_0FXOP_09_80,
1833 VEX_W_0F41_P_0_LEN_1,
1834 VEX_W_0F41_P_2_LEN_1,
1835 VEX_W_0F42_P_0_LEN_1,
1836 VEX_W_0F42_P_2_LEN_1,
1837 VEX_W_0F44_P_0_LEN_0,
1838 VEX_W_0F44_P_2_LEN_0,
1839 VEX_W_0F45_P_0_LEN_1,
1840 VEX_W_0F45_P_2_LEN_1,
1841 VEX_W_0F46_P_0_LEN_1,
1842 VEX_W_0F46_P_2_LEN_1,
1843 VEX_W_0F47_P_0_LEN_1,
1844 VEX_W_0F47_P_2_LEN_1,
1845 VEX_W_0F4A_P_0_LEN_1,
1846 VEX_W_0F4A_P_2_LEN_1,
1847 VEX_W_0F4B_P_0_LEN_1,
1848 VEX_W_0F4B_P_2_LEN_1,
1928 VEX_W_0F90_P_0_LEN_0,
1929 VEX_W_0F90_P_2_LEN_0,
1930 VEX_W_0F91_P_0_LEN_0,
1931 VEX_W_0F91_P_2_LEN_0,
1932 VEX_W_0F92_P_0_LEN_0,
1933 VEX_W_0F92_P_2_LEN_0,
1934 VEX_W_0F92_P_3_LEN_0,
1935 VEX_W_0F93_P_0_LEN_0,
1936 VEX_W_0F93_P_2_LEN_0,
1937 VEX_W_0F93_P_3_LEN_0,
1938 VEX_W_0F98_P_0_LEN_0,
1939 VEX_W_0F98_P_2_LEN_0,
1940 VEX_W_0F99_P_0_LEN_0,
1941 VEX_W_0F99_P_2_LEN_0,
2020 VEX_W_0F381A_P_2_M_0,
2032 VEX_W_0F382A_P_2_M_0,
2034 VEX_W_0F382C_P_2_M_0,
2035 VEX_W_0F382D_P_2_M_0,
2036 VEX_W_0F382E_P_2_M_0,
2037 VEX_W_0F382F_P_2_M_0,
2059 VEX_W_0F385A_P_2_M_0,
2087 VEX_W_0F3A30_P_2_LEN_0,
2088 VEX_W_0F3A31_P_2_LEN_0,
2089 VEX_W_0F3A32_P_2_LEN_0,
2090 VEX_W_0F3A33_P_2_LEN_0,
2110 EVEX_W_0F10_P_1_M_0,
2111 EVEX_W_0F10_P_1_M_1,
2113 EVEX_W_0F10_P_3_M_0,
2114 EVEX_W_0F10_P_3_M_1,
2116 EVEX_W_0F11_P_1_M_0,
2117 EVEX_W_0F11_P_1_M_1,
2119 EVEX_W_0F11_P_3_M_0,
2120 EVEX_W_0F11_P_3_M_1,
2121 EVEX_W_0F12_P_0_M_0,
2122 EVEX_W_0F12_P_0_M_1,
2132 EVEX_W_0F16_P_0_M_0,
2133 EVEX_W_0F16_P_0_M_1,
2204 EVEX_W_0F72_R_2_P_2,
2205 EVEX_W_0F72_R_6_P_2,
2206 EVEX_W_0F73_R_2_P_2,
2207 EVEX_W_0F73_R_6_P_2,
2307 EVEX_W_0F38C7_R_1_P_2,
2308 EVEX_W_0F38C7_R_2_P_2,
2309 EVEX_W_0F38C7_R_5_P_2,
2310 EVEX_W_0F38C7_R_6_P_2,
2345 typedef void (*op_rtn) (int bytemode, int sizeflag);
2356 /* Upper case letters in the instruction names here are macros.
2357 'A' => print 'b' if no register operands or suffix_always is true
2358 'B' => print 'b' if suffix_always is true
2359 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2361 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2362 suffix_always is true
2363 'E' => print 'e' if 32-bit form of jcxz
2364 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2365 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2366 'H' => print ",pt" or ",pn" branch hint
2367 'I' => honor following macro letter even in Intel mode (implemented only
2368 for some of the macro letters)
2370 'K' => print 'd' or 'q' if rex prefix is present.
2371 'L' => print 'l' if suffix_always is true
2372 'M' => print 'r' if intel_mnemonic is false.
2373 'N' => print 'n' if instruction has no wait "prefix"
2374 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2375 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2376 or suffix_always is true. print 'q' if rex prefix is present.
2377 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2379 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2380 'S' => print 'w', 'l' or 'q' if suffix_always is true
2381 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2382 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2383 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2384 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2385 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2386 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2387 suffix_always is true.
2388 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2389 '!' => change condition from true to false or from false to true.
2390 '%' => add 1 upper case letter to the macro.
2392 2 upper case letter macros:
2393 "XY" => print 'x' or 'y' if no register operands or suffix_always
2395 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2396 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2397 or suffix_always is true
2398 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2399 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2400 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2401 "LW" => print 'd', 'q' depending on the VEX.W bit
2402 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2403 an operand size prefix, or suffix_always is true. print
2404 'q' if rex prefix is present.
2406 Many of the above letters print nothing in Intel mode. See "putop"
2409 Braces '{' and '}', and vertical bars '|', indicate alternative
2410 mnemonic strings for AT&T and Intel. */
2412 static const struct dis386 dis386[] = {
2414 { "addB", { Ebh1, Gb } },
2415 { "addS", { Evh1, Gv } },
2416 { "addB", { Gb, EbS } },
2417 { "addS", { Gv, EvS } },
2418 { "addB", { AL, Ib } },
2419 { "addS", { eAX, Iv } },
2420 { X86_64_TABLE (X86_64_06) },
2421 { X86_64_TABLE (X86_64_07) },
2423 { "orB", { Ebh1, Gb } },
2424 { "orS", { Evh1, Gv } },
2425 { "orB", { Gb, EbS } },
2426 { "orS", { Gv, EvS } },
2427 { "orB", { AL, Ib } },
2428 { "orS", { eAX, Iv } },
2429 { X86_64_TABLE (X86_64_0D) },
2430 { Bad_Opcode }, /* 0x0f extended opcode escape */
2432 { "adcB", { Ebh1, Gb } },
2433 { "adcS", { Evh1, Gv } },
2434 { "adcB", { Gb, EbS } },
2435 { "adcS", { Gv, EvS } },
2436 { "adcB", { AL, Ib } },
2437 { "adcS", { eAX, Iv } },
2438 { X86_64_TABLE (X86_64_16) },
2439 { X86_64_TABLE (X86_64_17) },
2441 { "sbbB", { Ebh1, Gb } },
2442 { "sbbS", { Evh1, Gv } },
2443 { "sbbB", { Gb, EbS } },
2444 { "sbbS", { Gv, EvS } },
2445 { "sbbB", { AL, Ib } },
2446 { "sbbS", { eAX, Iv } },
2447 { X86_64_TABLE (X86_64_1E) },
2448 { X86_64_TABLE (X86_64_1F) },
2450 { "andB", { Ebh1, Gb } },
2451 { "andS", { Evh1, Gv } },
2452 { "andB", { Gb, EbS } },
2453 { "andS", { Gv, EvS } },
2454 { "andB", { AL, Ib } },
2455 { "andS", { eAX, Iv } },
2456 { Bad_Opcode }, /* SEG ES prefix */
2457 { X86_64_TABLE (X86_64_27) },
2459 { "subB", { Ebh1, Gb } },
2460 { "subS", { Evh1, Gv } },
2461 { "subB", { Gb, EbS } },
2462 { "subS", { Gv, EvS } },
2463 { "subB", { AL, Ib } },
2464 { "subS", { eAX, Iv } },
2465 { Bad_Opcode }, /* SEG CS prefix */
2466 { X86_64_TABLE (X86_64_2F) },
2468 { "xorB", { Ebh1, Gb } },
2469 { "xorS", { Evh1, Gv } },
2470 { "xorB", { Gb, EbS } },
2471 { "xorS", { Gv, EvS } },
2472 { "xorB", { AL, Ib } },
2473 { "xorS", { eAX, Iv } },
2474 { Bad_Opcode }, /* SEG SS prefix */
2475 { X86_64_TABLE (X86_64_37) },
2477 { "cmpB", { Eb, Gb } },
2478 { "cmpS", { Ev, Gv } },
2479 { "cmpB", { Gb, EbS } },
2480 { "cmpS", { Gv, EvS } },
2481 { "cmpB", { AL, Ib } },
2482 { "cmpS", { eAX, Iv } },
2483 { Bad_Opcode }, /* SEG DS prefix */
2484 { X86_64_TABLE (X86_64_3F) },
2486 { "inc{S|}", { RMeAX } },
2487 { "inc{S|}", { RMeCX } },
2488 { "inc{S|}", { RMeDX } },
2489 { "inc{S|}", { RMeBX } },
2490 { "inc{S|}", { RMeSP } },
2491 { "inc{S|}", { RMeBP } },
2492 { "inc{S|}", { RMeSI } },
2493 { "inc{S|}", { RMeDI } },
2495 { "dec{S|}", { RMeAX } },
2496 { "dec{S|}", { RMeCX } },
2497 { "dec{S|}", { RMeDX } },
2498 { "dec{S|}", { RMeBX } },
2499 { "dec{S|}", { RMeSP } },
2500 { "dec{S|}", { RMeBP } },
2501 { "dec{S|}", { RMeSI } },
2502 { "dec{S|}", { RMeDI } },
2504 { "pushV", { RMrAX } },
2505 { "pushV", { RMrCX } },
2506 { "pushV", { RMrDX } },
2507 { "pushV", { RMrBX } },
2508 { "pushV", { RMrSP } },
2509 { "pushV", { RMrBP } },
2510 { "pushV", { RMrSI } },
2511 { "pushV", { RMrDI } },
2513 { "popV", { RMrAX } },
2514 { "popV", { RMrCX } },
2515 { "popV", { RMrDX } },
2516 { "popV", { RMrBX } },
2517 { "popV", { RMrSP } },
2518 { "popV", { RMrBP } },
2519 { "popV", { RMrSI } },
2520 { "popV", { RMrDI } },
2522 { X86_64_TABLE (X86_64_60) },
2523 { X86_64_TABLE (X86_64_61) },
2524 { X86_64_TABLE (X86_64_62) },
2525 { X86_64_TABLE (X86_64_63) },
2526 { Bad_Opcode }, /* seg fs */
2527 { Bad_Opcode }, /* seg gs */
2528 { Bad_Opcode }, /* op size prefix */
2529 { Bad_Opcode }, /* adr size prefix */
2531 { "pushT", { sIv } },
2532 { "imulS", { Gv, Ev, Iv } },
2533 { "pushT", { sIbT } },
2534 { "imulS", { Gv, Ev, sIb } },
2535 { "ins{b|}", { Ybr, indirDX } },
2536 { X86_64_TABLE (X86_64_6D) },
2537 { "outs{b|}", { indirDXr, Xb } },
2538 { X86_64_TABLE (X86_64_6F) },
2540 { "joH", { Jb, BND, cond_jump_flag } },
2541 { "jnoH", { Jb, BND, cond_jump_flag } },
2542 { "jbH", { Jb, BND, cond_jump_flag } },
2543 { "jaeH", { Jb, BND, cond_jump_flag } },
2544 { "jeH", { Jb, BND, cond_jump_flag } },
2545 { "jneH", { Jb, BND, cond_jump_flag } },
2546 { "jbeH", { Jb, BND, cond_jump_flag } },
2547 { "jaH", { Jb, BND, cond_jump_flag } },
2549 { "jsH", { Jb, BND, cond_jump_flag } },
2550 { "jnsH", { Jb, BND, cond_jump_flag } },
2551 { "jpH", { Jb, BND, cond_jump_flag } },
2552 { "jnpH", { Jb, BND, cond_jump_flag } },
2553 { "jlH", { Jb, BND, cond_jump_flag } },
2554 { "jgeH", { Jb, BND, cond_jump_flag } },
2555 { "jleH", { Jb, BND, cond_jump_flag } },
2556 { "jgH", { Jb, BND, cond_jump_flag } },
2558 { REG_TABLE (REG_80) },
2559 { REG_TABLE (REG_81) },
2561 { REG_TABLE (REG_82) },
2562 { "testB", { Eb, Gb } },
2563 { "testS", { Ev, Gv } },
2564 { "xchgB", { Ebh2, Gb } },
2565 { "xchgS", { Evh2, Gv } },
2567 { "movB", { Ebh3, Gb } },
2568 { "movS", { Evh3, Gv } },
2569 { "movB", { Gb, EbS } },
2570 { "movS", { Gv, EvS } },
2571 { "movD", { Sv, Sw } },
2572 { MOD_TABLE (MOD_8D) },
2573 { "movD", { Sw, Sv } },
2574 { REG_TABLE (REG_8F) },
2576 { PREFIX_TABLE (PREFIX_90) },
2577 { "xchgS", { RMeCX, eAX } },
2578 { "xchgS", { RMeDX, eAX } },
2579 { "xchgS", { RMeBX, eAX } },
2580 { "xchgS", { RMeSP, eAX } },
2581 { "xchgS", { RMeBP, eAX } },
2582 { "xchgS", { RMeSI, eAX } },
2583 { "xchgS", { RMeDI, eAX } },
2585 { "cW{t|}R", { XX } },
2586 { "cR{t|}O", { XX } },
2587 { X86_64_TABLE (X86_64_9A) },
2588 { Bad_Opcode }, /* fwait */
2589 { "pushfT", { XX } },
2590 { "popfT", { XX } },
2594 { "mov%LB", { AL, Ob } },
2595 { "mov%LS", { eAX, Ov } },
2596 { "mov%LB", { Ob, AL } },
2597 { "mov%LS", { Ov, eAX } },
2598 { "movs{b|}", { Ybr, Xb } },
2599 { "movs{R|}", { Yvr, Xv } },
2600 { "cmps{b|}", { Xb, Yb } },
2601 { "cmps{R|}", { Xv, Yv } },
2603 { "testB", { AL, Ib } },
2604 { "testS", { eAX, Iv } },
2605 { "stosB", { Ybr, AL } },
2606 { "stosS", { Yvr, eAX } },
2607 { "lodsB", { ALr, Xb } },
2608 { "lodsS", { eAXr, Xv } },
2609 { "scasB", { AL, Yb } },
2610 { "scasS", { eAX, Yv } },
2612 { "movB", { RMAL, Ib } },
2613 { "movB", { RMCL, Ib } },
2614 { "movB", { RMDL, Ib } },
2615 { "movB", { RMBL, Ib } },
2616 { "movB", { RMAH, Ib } },
2617 { "movB", { RMCH, Ib } },
2618 { "movB", { RMDH, Ib } },
2619 { "movB", { RMBH, Ib } },
2621 { "mov%LV", { RMeAX, Iv64 } },
2622 { "mov%LV", { RMeCX, Iv64 } },
2623 { "mov%LV", { RMeDX, Iv64 } },
2624 { "mov%LV", { RMeBX, Iv64 } },
2625 { "mov%LV", { RMeSP, Iv64 } },
2626 { "mov%LV", { RMeBP, Iv64 } },
2627 { "mov%LV", { RMeSI, Iv64 } },
2628 { "mov%LV", { RMeDI, Iv64 } },
2630 { REG_TABLE (REG_C0) },
2631 { REG_TABLE (REG_C1) },
2632 { "retT", { Iw, BND } },
2633 { "retT", { BND } },
2634 { X86_64_TABLE (X86_64_C4) },
2635 { X86_64_TABLE (X86_64_C5) },
2636 { REG_TABLE (REG_C6) },
2637 { REG_TABLE (REG_C7) },
2639 { "enterT", { Iw, Ib } },
2640 { "leaveT", { XX } },
2641 { "Jret{|f}P", { Iw } },
2642 { "Jret{|f}P", { XX } },
2645 { X86_64_TABLE (X86_64_CE) },
2646 { "iret%LP", { XX } },
2648 { REG_TABLE (REG_D0) },
2649 { REG_TABLE (REG_D1) },
2650 { REG_TABLE (REG_D2) },
2651 { REG_TABLE (REG_D3) },
2652 { X86_64_TABLE (X86_64_D4) },
2653 { X86_64_TABLE (X86_64_D5) },
2655 { "xlat", { DSBX } },
2666 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
2667 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
2668 { "loopFH", { Jb, XX, loop_jcxz_flag } },
2669 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
2670 { "inB", { AL, Ib } },
2671 { "inG", { zAX, Ib } },
2672 { "outB", { Ib, AL } },
2673 { "outG", { Ib, zAX } },
2675 { "callT", { Jv, BND } },
2676 { "jmpT", { Jv, BND } },
2677 { X86_64_TABLE (X86_64_EA) },
2678 { "jmp", { Jb, BND } },
2679 { "inB", { AL, indirDX } },
2680 { "inG", { zAX, indirDX } },
2681 { "outB", { indirDX, AL } },
2682 { "outG", { indirDX, zAX } },
2684 { Bad_Opcode }, /* lock prefix */
2685 { "icebp", { XX } },
2686 { Bad_Opcode }, /* repne */
2687 { Bad_Opcode }, /* repz */
2690 { REG_TABLE (REG_F6) },
2691 { REG_TABLE (REG_F7) },
2699 { REG_TABLE (REG_FE) },
2700 { REG_TABLE (REG_FF) },
2703 static const struct dis386 dis386_twobyte[] = {
2705 { REG_TABLE (REG_0F00 ) },
2706 { REG_TABLE (REG_0F01 ) },
2707 { "larS", { Gv, Ew } },
2708 { "lslS", { Gv, Ew } },
2710 { "syscall", { XX } },
2712 { "sysret%LP", { XX } },
2715 { "wbinvd", { XX } },
2719 { REG_TABLE (REG_0F0D) },
2720 { "femms", { XX } },
2721 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
2723 { PREFIX_TABLE (PREFIX_0F10) },
2724 { PREFIX_TABLE (PREFIX_0F11) },
2725 { PREFIX_TABLE (PREFIX_0F12) },
2726 { MOD_TABLE (MOD_0F13) },
2727 { "unpcklpX", { XM, EXx } },
2728 { "unpckhpX", { XM, EXx } },
2729 { PREFIX_TABLE (PREFIX_0F16) },
2730 { MOD_TABLE (MOD_0F17) },
2732 { REG_TABLE (REG_0F18) },
2734 { PREFIX_TABLE (PREFIX_0F1A) },
2735 { PREFIX_TABLE (PREFIX_0F1B) },
2741 { "movZ", { Rm, Cm } },
2742 { "movZ", { Rm, Dm } },
2743 { "movZ", { Cm, Rm } },
2744 { "movZ", { Dm, Rm } },
2745 { MOD_TABLE (MOD_0F24) },
2747 { MOD_TABLE (MOD_0F26) },
2750 { "movapX", { XM, EXx } },
2751 { "movapX", { EXxS, XM } },
2752 { PREFIX_TABLE (PREFIX_0F2A) },
2753 { PREFIX_TABLE (PREFIX_0F2B) },
2754 { PREFIX_TABLE (PREFIX_0F2C) },
2755 { PREFIX_TABLE (PREFIX_0F2D) },
2756 { PREFIX_TABLE (PREFIX_0F2E) },
2757 { PREFIX_TABLE (PREFIX_0F2F) },
2759 { "wrmsr", { XX } },
2760 { "rdtsc", { XX } },
2761 { "rdmsr", { XX } },
2762 { "rdpmc", { XX } },
2763 { "sysenter", { XX } },
2764 { "sysexit", { XX } },
2766 { "getsec", { XX } },
2768 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2770 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2777 { "cmovoS", { Gv, Ev } },
2778 { "cmovnoS", { Gv, Ev } },
2779 { "cmovbS", { Gv, Ev } },
2780 { "cmovaeS", { Gv, Ev } },
2781 { "cmoveS", { Gv, Ev } },
2782 { "cmovneS", { Gv, Ev } },
2783 { "cmovbeS", { Gv, Ev } },
2784 { "cmovaS", { Gv, Ev } },
2786 { "cmovsS", { Gv, Ev } },
2787 { "cmovnsS", { Gv, Ev } },
2788 { "cmovpS", { Gv, Ev } },
2789 { "cmovnpS", { Gv, Ev } },
2790 { "cmovlS", { Gv, Ev } },
2791 { "cmovgeS", { Gv, Ev } },
2792 { "cmovleS", { Gv, Ev } },
2793 { "cmovgS", { Gv, Ev } },
2795 { MOD_TABLE (MOD_0F51) },
2796 { PREFIX_TABLE (PREFIX_0F51) },
2797 { PREFIX_TABLE (PREFIX_0F52) },
2798 { PREFIX_TABLE (PREFIX_0F53) },
2799 { "andpX", { XM, EXx } },
2800 { "andnpX", { XM, EXx } },
2801 { "orpX", { XM, EXx } },
2802 { "xorpX", { XM, EXx } },
2804 { PREFIX_TABLE (PREFIX_0F58) },
2805 { PREFIX_TABLE (PREFIX_0F59) },
2806 { PREFIX_TABLE (PREFIX_0F5A) },
2807 { PREFIX_TABLE (PREFIX_0F5B) },
2808 { PREFIX_TABLE (PREFIX_0F5C) },
2809 { PREFIX_TABLE (PREFIX_0F5D) },
2810 { PREFIX_TABLE (PREFIX_0F5E) },
2811 { PREFIX_TABLE (PREFIX_0F5F) },
2813 { PREFIX_TABLE (PREFIX_0F60) },
2814 { PREFIX_TABLE (PREFIX_0F61) },
2815 { PREFIX_TABLE (PREFIX_0F62) },
2816 { "packsswb", { MX, EM } },
2817 { "pcmpgtb", { MX, EM } },
2818 { "pcmpgtw", { MX, EM } },
2819 { "pcmpgtd", { MX, EM } },
2820 { "packuswb", { MX, EM } },
2822 { "punpckhbw", { MX, EM } },
2823 { "punpckhwd", { MX, EM } },
2824 { "punpckhdq", { MX, EM } },
2825 { "packssdw", { MX, EM } },
2826 { PREFIX_TABLE (PREFIX_0F6C) },
2827 { PREFIX_TABLE (PREFIX_0F6D) },
2828 { "movK", { MX, Edq } },
2829 { PREFIX_TABLE (PREFIX_0F6F) },
2831 { PREFIX_TABLE (PREFIX_0F70) },
2832 { REG_TABLE (REG_0F71) },
2833 { REG_TABLE (REG_0F72) },
2834 { REG_TABLE (REG_0F73) },
2835 { "pcmpeqb", { MX, EM } },
2836 { "pcmpeqw", { MX, EM } },
2837 { "pcmpeqd", { MX, EM } },
2840 { PREFIX_TABLE (PREFIX_0F78) },
2841 { PREFIX_TABLE (PREFIX_0F79) },
2842 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2844 { PREFIX_TABLE (PREFIX_0F7C) },
2845 { PREFIX_TABLE (PREFIX_0F7D) },
2846 { PREFIX_TABLE (PREFIX_0F7E) },
2847 { PREFIX_TABLE (PREFIX_0F7F) },
2849 { "joH", { Jv, BND, cond_jump_flag } },
2850 { "jnoH", { Jv, BND, cond_jump_flag } },
2851 { "jbH", { Jv, BND, cond_jump_flag } },
2852 { "jaeH", { Jv, BND, cond_jump_flag } },
2853 { "jeH", { Jv, BND, cond_jump_flag } },
2854 { "jneH", { Jv, BND, cond_jump_flag } },
2855 { "jbeH", { Jv, BND, cond_jump_flag } },
2856 { "jaH", { Jv, BND, cond_jump_flag } },
2858 { "jsH", { Jv, BND, cond_jump_flag } },
2859 { "jnsH", { Jv, BND, cond_jump_flag } },
2860 { "jpH", { Jv, BND, cond_jump_flag } },
2861 { "jnpH", { Jv, BND, cond_jump_flag } },
2862 { "jlH", { Jv, BND, cond_jump_flag } },
2863 { "jgeH", { Jv, BND, cond_jump_flag } },
2864 { "jleH", { Jv, BND, cond_jump_flag } },
2865 { "jgH", { Jv, BND, cond_jump_flag } },
2868 { "setno", { Eb } },
2870 { "setae", { Eb } },
2872 { "setne", { Eb } },
2873 { "setbe", { Eb } },
2877 { "setns", { Eb } },
2879 { "setnp", { Eb } },
2881 { "setge", { Eb } },
2882 { "setle", { Eb } },
2885 { "pushT", { fs } },
2887 { "cpuid", { XX } },
2888 { "btS", { Ev, Gv } },
2889 { "shldS", { Ev, Gv, Ib } },
2890 { "shldS", { Ev, Gv, CL } },
2891 { REG_TABLE (REG_0FA6) },
2892 { REG_TABLE (REG_0FA7) },
2894 { "pushT", { gs } },
2897 { "btsS", { Evh1, Gv } },
2898 { "shrdS", { Ev, Gv, Ib } },
2899 { "shrdS", { Ev, Gv, CL } },
2900 { REG_TABLE (REG_0FAE) },
2901 { "imulS", { Gv, Ev } },
2903 { "cmpxchgB", { Ebh1, Gb } },
2904 { "cmpxchgS", { Evh1, Gv } },
2905 { MOD_TABLE (MOD_0FB2) },
2906 { "btrS", { Evh1, Gv } },
2907 { MOD_TABLE (MOD_0FB4) },
2908 { MOD_TABLE (MOD_0FB5) },
2909 { "movz{bR|x}", { Gv, Eb } },
2910 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
2912 { PREFIX_TABLE (PREFIX_0FB8) },
2914 { REG_TABLE (REG_0FBA) },
2915 { "btcS", { Evh1, Gv } },
2916 { PREFIX_TABLE (PREFIX_0FBC) },
2917 { PREFIX_TABLE (PREFIX_0FBD) },
2918 { "movs{bR|x}", { Gv, Eb } },
2919 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
2921 { "xaddB", { Ebh1, Gb } },
2922 { "xaddS", { Evh1, Gv } },
2923 { PREFIX_TABLE (PREFIX_0FC2) },
2924 { PREFIX_TABLE (PREFIX_0FC3) },
2925 { "pinsrw", { MX, Edqw, Ib } },
2926 { "pextrw", { Gdq, MS, Ib } },
2927 { "shufpX", { XM, EXx, Ib } },
2928 { REG_TABLE (REG_0FC7) },
2930 { "bswap", { RMeAX } },
2931 { "bswap", { RMeCX } },
2932 { "bswap", { RMeDX } },
2933 { "bswap", { RMeBX } },
2934 { "bswap", { RMeSP } },
2935 { "bswap", { RMeBP } },
2936 { "bswap", { RMeSI } },
2937 { "bswap", { RMeDI } },
2939 { PREFIX_TABLE (PREFIX_0FD0) },
2940 { "psrlw", { MX, EM } },
2941 { "psrld", { MX, EM } },
2942 { "psrlq", { MX, EM } },
2943 { "paddq", { MX, EM } },
2944 { "pmullw", { MX, EM } },
2945 { PREFIX_TABLE (PREFIX_0FD6) },
2946 { MOD_TABLE (MOD_0FD7) },
2948 { "psubusb", { MX, EM } },
2949 { "psubusw", { MX, EM } },
2950 { "pminub", { MX, EM } },
2951 { "pand", { MX, EM } },
2952 { "paddusb", { MX, EM } },
2953 { "paddusw", { MX, EM } },
2954 { "pmaxub", { MX, EM } },
2955 { "pandn", { MX, EM } },
2957 { "pavgb", { MX, EM } },
2958 { "psraw", { MX, EM } },
2959 { "psrad", { MX, EM } },
2960 { "pavgw", { MX, EM } },
2961 { "pmulhuw", { MX, EM } },
2962 { "pmulhw", { MX, EM } },
2963 { PREFIX_TABLE (PREFIX_0FE6) },
2964 { PREFIX_TABLE (PREFIX_0FE7) },
2966 { "psubsb", { MX, EM } },
2967 { "psubsw", { MX, EM } },
2968 { "pminsw", { MX, EM } },
2969 { "por", { MX, EM } },
2970 { "paddsb", { MX, EM } },
2971 { "paddsw", { MX, EM } },
2972 { "pmaxsw", { MX, EM } },
2973 { "pxor", { MX, EM } },
2975 { PREFIX_TABLE (PREFIX_0FF0) },
2976 { "psllw", { MX, EM } },
2977 { "pslld", { MX, EM } },
2978 { "psllq", { MX, EM } },
2979 { "pmuludq", { MX, EM } },
2980 { "pmaddwd", { MX, EM } },
2981 { "psadbw", { MX, EM } },
2982 { PREFIX_TABLE (PREFIX_0FF7) },
2984 { "psubb", { MX, EM } },
2985 { "psubw", { MX, EM } },
2986 { "psubd", { MX, EM } },
2987 { "psubq", { MX, EM } },
2988 { "paddb", { MX, EM } },
2989 { "paddw", { MX, EM } },
2990 { "paddd", { MX, EM } },
2994 static const unsigned char onebyte_has_modrm[256] = {
2995 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2996 /* ------------------------------- */
2997 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2998 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2999 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3000 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3001 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3002 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3003 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3004 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3005 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3006 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3007 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3008 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3009 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3010 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3011 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3012 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3013 /* ------------------------------- */
3014 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3017 static const unsigned char twobyte_has_modrm[256] = {
3018 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3019 /* ------------------------------- */
3020 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3021 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3022 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3023 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3024 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3025 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3026 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3027 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3028 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3029 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3030 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3031 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3032 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3033 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3034 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3035 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
3036 /* ------------------------------- */
3037 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3040 static const unsigned char twobyte_has_mandatory_prefix[256] = {
3041 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3042 /* ------------------------------- */
3043 /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */
3044 /* 10 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* 1f */
3045 /* 20 */ 0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0, /* 2f */
3046 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3047 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
3048 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3049 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3050 /* 70 */ 1,0,0,0,1,1,1,1,0,0,1,1,1,1,1,1, /* 7f */
3051 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3052 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */
3053 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
3054 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */
3055 /* c0 */ 0,0,1,1,1,1,1,0,0,0,0,0,0,0,0,0, /* cf */
3056 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3057 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3058 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
3059 /* ------------------------------- */
3060 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3063 static char obuf[100];
3065 static char *mnemonicendp;
3066 static char scratchbuf[100];
3067 static unsigned char *start_codep;
3068 static unsigned char *insn_codep;
3069 static unsigned char *codep;
3070 static unsigned char *end_codep;
3071 static int last_lock_prefix;
3072 static int last_repz_prefix;
3073 static int last_repnz_prefix;
3074 static int last_data_prefix;
3075 static int last_addr_prefix;
3076 static int last_rex_prefix;
3077 static int last_seg_prefix;
3078 static int fwait_prefix;
3079 /* The PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is mandatory. */
3080 static int mandatory_prefix;
3081 /* The active segment register prefix. */
3082 static int active_seg_prefix;
3083 #define MAX_CODE_LENGTH 15
3084 /* We can up to 14 prefixes since the maximum instruction length is
3086 static int all_prefixes[MAX_CODE_LENGTH - 1];
3087 static disassemble_info *the_info;
3095 static unsigned char need_modrm;
3105 int register_specifier;
3112 int mask_register_specifier;
3118 static unsigned char need_vex;
3119 static unsigned char need_vex_reg;
3120 static unsigned char vex_w_done;
3128 /* If we are accessing mod/rm/reg without need_modrm set, then the
3129 values are stale. Hitting this abort likely indicates that you
3130 need to update onebyte_has_modrm or twobyte_has_modrm. */
3131 #define MODRM_CHECK if (!need_modrm) abort ()
3133 static const char **names64;
3134 static const char **names32;
3135 static const char **names16;
3136 static const char **names8;
3137 static const char **names8rex;
3138 static const char **names_seg;
3139 static const char *index64;
3140 static const char *index32;
3141 static const char **index16;
3142 static const char **names_bnd;
3144 static const char *intel_names64[] = {
3145 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3146 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3148 static const char *intel_names32[] = {
3149 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3150 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3152 static const char *intel_names16[] = {
3153 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3154 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3156 static const char *intel_names8[] = {
3157 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3159 static const char *intel_names8rex[] = {
3160 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3161 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3163 static const char *intel_names_seg[] = {
3164 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3166 static const char *intel_index64 = "riz";
3167 static const char *intel_index32 = "eiz";
3168 static const char *intel_index16[] = {
3169 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3172 static const char *att_names64[] = {
3173 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3174 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3176 static const char *att_names32[] = {
3177 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3178 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3180 static const char *att_names16[] = {
3181 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3182 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3184 static const char *att_names8[] = {
3185 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3187 static const char *att_names8rex[] = {
3188 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3189 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3191 static const char *att_names_seg[] = {
3192 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3194 static const char *att_index64 = "%riz";
3195 static const char *att_index32 = "%eiz";
3196 static const char *att_index16[] = {
3197 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3200 static const char **names_mm;
3201 static const char *intel_names_mm[] = {
3202 "mm0", "mm1", "mm2", "mm3",
3203 "mm4", "mm5", "mm6", "mm7"
3205 static const char *att_names_mm[] = {
3206 "%mm0", "%mm1", "%mm2", "%mm3",
3207 "%mm4", "%mm5", "%mm6", "%mm7"
3210 static const char *intel_names_bnd[] = {
3211 "bnd0", "bnd1", "bnd2", "bnd3"
3214 static const char *att_names_bnd[] = {
3215 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3218 static const char **names_xmm;
3219 static const char *intel_names_xmm[] = {
3220 "xmm0", "xmm1", "xmm2", "xmm3",
3221 "xmm4", "xmm5", "xmm6", "xmm7",
3222 "xmm8", "xmm9", "xmm10", "xmm11",
3223 "xmm12", "xmm13", "xmm14", "xmm15",
3224 "xmm16", "xmm17", "xmm18", "xmm19",
3225 "xmm20", "xmm21", "xmm22", "xmm23",
3226 "xmm24", "xmm25", "xmm26", "xmm27",
3227 "xmm28", "xmm29", "xmm30", "xmm31"
3229 static const char *att_names_xmm[] = {
3230 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3231 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3232 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3233 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3234 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3235 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3236 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3237 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3240 static const char **names_ymm;
3241 static const char *intel_names_ymm[] = {
3242 "ymm0", "ymm1", "ymm2", "ymm3",
3243 "ymm4", "ymm5", "ymm6", "ymm7",
3244 "ymm8", "ymm9", "ymm10", "ymm11",
3245 "ymm12", "ymm13", "ymm14", "ymm15",
3246 "ymm16", "ymm17", "ymm18", "ymm19",
3247 "ymm20", "ymm21", "ymm22", "ymm23",
3248 "ymm24", "ymm25", "ymm26", "ymm27",
3249 "ymm28", "ymm29", "ymm30", "ymm31"
3251 static const char *att_names_ymm[] = {
3252 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3253 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3254 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3255 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3256 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3257 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3258 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3259 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3262 static const char **names_zmm;
3263 static const char *intel_names_zmm[] = {
3264 "zmm0", "zmm1", "zmm2", "zmm3",
3265 "zmm4", "zmm5", "zmm6", "zmm7",
3266 "zmm8", "zmm9", "zmm10", "zmm11",
3267 "zmm12", "zmm13", "zmm14", "zmm15",
3268 "zmm16", "zmm17", "zmm18", "zmm19",
3269 "zmm20", "zmm21", "zmm22", "zmm23",
3270 "zmm24", "zmm25", "zmm26", "zmm27",
3271 "zmm28", "zmm29", "zmm30", "zmm31"
3273 static const char *att_names_zmm[] = {
3274 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3275 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3276 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3277 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3278 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3279 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3280 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3281 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3284 static const char **names_mask;
3285 static const char *intel_names_mask[] = {
3286 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3288 static const char *att_names_mask[] = {
3289 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3292 static const char *names_rounding[] =
3300 static const struct dis386 reg_table[][8] = {
3303 { "addA", { Ebh1, Ib } },
3304 { "orA", { Ebh1, Ib } },
3305 { "adcA", { Ebh1, Ib } },
3306 { "sbbA", { Ebh1, Ib } },
3307 { "andA", { Ebh1, Ib } },
3308 { "subA", { Ebh1, Ib } },
3309 { "xorA", { Ebh1, Ib } },
3310 { "cmpA", { Eb, Ib } },
3314 { "addQ", { Evh1, Iv } },
3315 { "orQ", { Evh1, Iv } },
3316 { "adcQ", { Evh1, Iv } },
3317 { "sbbQ", { Evh1, Iv } },
3318 { "andQ", { Evh1, Iv } },
3319 { "subQ", { Evh1, Iv } },
3320 { "xorQ", { Evh1, Iv } },
3321 { "cmpQ", { Ev, Iv } },
3325 { "addQ", { Evh1, sIb } },
3326 { "orQ", { Evh1, sIb } },
3327 { "adcQ", { Evh1, sIb } },
3328 { "sbbQ", { Evh1, sIb } },
3329 { "andQ", { Evh1, sIb } },
3330 { "subQ", { Evh1, sIb } },
3331 { "xorQ", { Evh1, sIb } },
3332 { "cmpQ", { Ev, sIb } },
3336 { "popU", { stackEv } },
3337 { XOP_8F_TABLE (XOP_09) },
3341 { XOP_8F_TABLE (XOP_09) },
3345 { "rolA", { Eb, Ib } },
3346 { "rorA", { Eb, Ib } },
3347 { "rclA", { Eb, Ib } },
3348 { "rcrA", { Eb, Ib } },
3349 { "shlA", { Eb, Ib } },
3350 { "shrA", { Eb, Ib } },
3352 { "sarA", { Eb, Ib } },
3356 { "rolQ", { Ev, Ib } },
3357 { "rorQ", { Ev, Ib } },
3358 { "rclQ", { Ev, Ib } },
3359 { "rcrQ", { Ev, Ib } },
3360 { "shlQ", { Ev, Ib } },
3361 { "shrQ", { Ev, Ib } },
3363 { "sarQ", { Ev, Ib } },
3367 { "movA", { Ebh3, Ib } },
3374 { MOD_TABLE (MOD_C6_REG_7) },
3378 { "movQ", { Evh3, Iv } },
3385 { MOD_TABLE (MOD_C7_REG_7) },
3389 { "rolA", { Eb, I1 } },
3390 { "rorA", { Eb, I1 } },
3391 { "rclA", { Eb, I1 } },
3392 { "rcrA", { Eb, I1 } },
3393 { "shlA", { Eb, I1 } },
3394 { "shrA", { Eb, I1 } },
3396 { "sarA", { Eb, I1 } },
3400 { "rolQ", { Ev, I1 } },
3401 { "rorQ", { Ev, I1 } },
3402 { "rclQ", { Ev, I1 } },
3403 { "rcrQ", { Ev, I1 } },
3404 { "shlQ", { Ev, I1 } },
3405 { "shrQ", { Ev, I1 } },
3407 { "sarQ", { Ev, I1 } },
3411 { "rolA", { Eb, CL } },
3412 { "rorA", { Eb, CL } },
3413 { "rclA", { Eb, CL } },
3414 { "rcrA", { Eb, CL } },
3415 { "shlA", { Eb, CL } },
3416 { "shrA", { Eb, CL } },
3418 { "sarA", { Eb, CL } },
3422 { "rolQ", { Ev, CL } },
3423 { "rorQ", { Ev, CL } },
3424 { "rclQ", { Ev, CL } },
3425 { "rcrQ", { Ev, CL } },
3426 { "shlQ", { Ev, CL } },
3427 { "shrQ", { Ev, CL } },
3429 { "sarQ", { Ev, CL } },
3433 { "testA", { Eb, Ib } },
3435 { "notA", { Ebh1 } },
3436 { "negA", { Ebh1 } },
3437 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
3438 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
3439 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
3440 { "idivA", { Eb } }, /* and idiv for consistency. */
3444 { "testQ", { Ev, Iv } },
3446 { "notQ", { Evh1 } },
3447 { "negQ", { Evh1 } },
3448 { "mulQ", { Ev } }, /* Don't print the implicit register. */
3449 { "imulQ", { Ev } },
3451 { "idivQ", { Ev } },
3455 { "incA", { Ebh1 } },
3456 { "decA", { Ebh1 } },
3460 { "incQ", { Evh1 } },
3461 { "decQ", { Evh1 } },
3462 { "call{T|}", { indirEv, BND } },
3463 { MOD_TABLE (MOD_FF_REG_3) },
3464 { "jmp{T|}", { indirEv, BND } },
3465 { MOD_TABLE (MOD_FF_REG_5) },
3466 { "pushU", { stackEv } },
3471 { "sldtD", { Sv } },
3482 { MOD_TABLE (MOD_0F01_REG_0) },
3483 { MOD_TABLE (MOD_0F01_REG_1) },
3484 { MOD_TABLE (MOD_0F01_REG_2) },
3485 { MOD_TABLE (MOD_0F01_REG_3) },
3486 { "smswD", { Sv } },
3489 { MOD_TABLE (MOD_0F01_REG_7) },
3493 { "prefetch", { Mb } },
3494 { "prefetchw", { Mb } },
3495 { "prefetchwt1", { Mb } },
3496 { "prefetch", { Mb } },
3497 { "prefetch", { Mb } },
3498 { "prefetch", { Mb } },
3499 { "prefetch", { Mb } },
3500 { "prefetch", { Mb } },
3504 { MOD_TABLE (MOD_0F18_REG_0) },
3505 { MOD_TABLE (MOD_0F18_REG_1) },
3506 { MOD_TABLE (MOD_0F18_REG_2) },
3507 { MOD_TABLE (MOD_0F18_REG_3) },
3508 { MOD_TABLE (MOD_0F18_REG_4) },
3509 { MOD_TABLE (MOD_0F18_REG_5) },
3510 { MOD_TABLE (MOD_0F18_REG_6) },
3511 { MOD_TABLE (MOD_0F18_REG_7) },
3517 { MOD_TABLE (MOD_0F71_REG_2) },
3519 { MOD_TABLE (MOD_0F71_REG_4) },
3521 { MOD_TABLE (MOD_0F71_REG_6) },
3527 { MOD_TABLE (MOD_0F72_REG_2) },
3529 { MOD_TABLE (MOD_0F72_REG_4) },
3531 { MOD_TABLE (MOD_0F72_REG_6) },
3537 { MOD_TABLE (MOD_0F73_REG_2) },
3538 { MOD_TABLE (MOD_0F73_REG_3) },
3541 { MOD_TABLE (MOD_0F73_REG_6) },
3542 { MOD_TABLE (MOD_0F73_REG_7) },
3546 { "montmul", { { OP_0f07, 0 } } },
3547 { "xsha1", { { OP_0f07, 0 } } },
3548 { "xsha256", { { OP_0f07, 0 } } },
3552 { "xstore-rng", { { OP_0f07, 0 } } },
3553 { "xcrypt-ecb", { { OP_0f07, 0 } } },
3554 { "xcrypt-cbc", { { OP_0f07, 0 } } },
3555 { "xcrypt-ctr", { { OP_0f07, 0 } } },
3556 { "xcrypt-cfb", { { OP_0f07, 0 } } },
3557 { "xcrypt-ofb", { { OP_0f07, 0 } } },
3561 { MOD_TABLE (MOD_0FAE_REG_0) },
3562 { MOD_TABLE (MOD_0FAE_REG_1) },
3563 { MOD_TABLE (MOD_0FAE_REG_2) },
3564 { MOD_TABLE (MOD_0FAE_REG_3) },
3565 { MOD_TABLE (MOD_0FAE_REG_4) },
3566 { MOD_TABLE (MOD_0FAE_REG_5) },
3567 { MOD_TABLE (MOD_0FAE_REG_6) },
3568 { MOD_TABLE (MOD_0FAE_REG_7) },
3576 { "btQ", { Ev, Ib } },
3577 { "btsQ", { Evh1, Ib } },
3578 { "btrQ", { Evh1, Ib } },
3579 { "btcQ", { Evh1, Ib } },
3584 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
3586 { MOD_TABLE (MOD_0FC7_REG_3) },
3587 { MOD_TABLE (MOD_0FC7_REG_4) },
3588 { MOD_TABLE (MOD_0FC7_REG_5) },
3589 { MOD_TABLE (MOD_0FC7_REG_6) },
3590 { MOD_TABLE (MOD_0FC7_REG_7) },
3596 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3598 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3600 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3606 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3608 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3610 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3616 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3617 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3620 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3621 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3627 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3628 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3630 /* REG_VEX_0F38F3 */
3633 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3634 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3635 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3639 { "llwpcb", { { OP_LWPCB_E, 0 } } },
3640 { "slwpcb", { { OP_LWPCB_E, 0 } } },
3644 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
3645 { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
3647 /* REG_XOP_TBM_01 */
3650 { "blcfill", { { OP_LWP_E, 0 }, Ev } },
3651 { "blsfill", { { OP_LWP_E, 0 }, Ev } },
3652 { "blcs", { { OP_LWP_E, 0 }, Ev } },
3653 { "tzmsk", { { OP_LWP_E, 0 }, Ev } },
3654 { "blcic", { { OP_LWP_E, 0 }, Ev } },
3655 { "blsic", { { OP_LWP_E, 0 }, Ev } },
3656 { "t1mskc", { { OP_LWP_E, 0 }, Ev } },
3658 /* REG_XOP_TBM_02 */
3661 { "blcmsk", { { OP_LWP_E, 0 }, Ev } },
3666 { "blci", { { OP_LWP_E, 0 }, Ev } },
3668 #define NEED_REG_TABLE
3669 #include "i386-dis-evex.h"
3670 #undef NEED_REG_TABLE
3673 static const struct dis386 prefix_table[][4] = {
3676 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3677 { "pause", { XX } },
3678 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3683 { "movups", { XM, EXx } },
3684 { "movss", { XM, EXd } },
3685 { "movupd", { XM, EXx } },
3686 { "movsd", { XM, EXq } },
3691 { "movups", { EXxS, XM } },
3692 { "movss", { EXdS, XM } },
3693 { "movupd", { EXxS, XM } },
3694 { "movsd", { EXqS, XM } },
3699 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3700 { "movsldup", { XM, EXx } },
3701 { "movlpd", { XM, EXq } },
3702 { "movddup", { XM, EXq } },
3707 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3708 { "movshdup", { XM, EXx } },
3709 { "movhpd", { XM, EXq } },
3714 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3715 { "bndcl", { Gbnd, Ev_bnd } },
3716 { "bndmov", { Gbnd, Ebnd } },
3717 { "bndcu", { Gbnd, Ev_bnd } },
3722 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3723 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3724 { "bndmov", { Ebnd, Gbnd } },
3725 { "bndcn", { Gbnd, Ev_bnd } },
3730 { "cvtpi2ps", { XM, EMCq } },
3731 { "cvtsi2ss%LQ", { XM, Ev } },
3732 { "cvtpi2pd", { XM, EMCq } },
3733 { "cvtsi2sd%LQ", { XM, Ev } },
3738 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3739 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3740 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3741 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3746 { "cvttps2pi", { MXC, EXq } },
3747 { "cvttss2siY", { Gv, EXd } },
3748 { "cvttpd2pi", { MXC, EXx } },
3749 { "cvttsd2siY", { Gv, EXq } },
3754 { "cvtps2pi", { MXC, EXq } },
3755 { "cvtss2siY", { Gv, EXd } },
3756 { "cvtpd2pi", { MXC, EXx } },
3757 { "cvtsd2siY", { Gv, EXq } },
3762 { "ucomiss",{ XM, EXd } },
3764 { "ucomisd",{ XM, EXq } },
3769 { "comiss", { XM, EXd } },
3771 { "comisd", { XM, EXq } },
3776 { "sqrtps", { XM, EXx } },
3777 { "sqrtss", { XM, EXd } },
3778 { "sqrtpd", { XM, EXx } },
3779 { "sqrtsd", { XM, EXq } },
3784 { "rsqrtps",{ XM, EXx } },
3785 { "rsqrtss",{ XM, EXd } },
3790 { "rcpps", { XM, EXx } },
3791 { "rcpss", { XM, EXd } },
3796 { "addps", { XM, EXx } },
3797 { "addss", { XM, EXd } },
3798 { "addpd", { XM, EXx } },
3799 { "addsd", { XM, EXq } },
3804 { "mulps", { XM, EXx } },
3805 { "mulss", { XM, EXd } },
3806 { "mulpd", { XM, EXx } },
3807 { "mulsd", { XM, EXq } },
3812 { "cvtps2pd", { XM, EXq } },
3813 { "cvtss2sd", { XM, EXd } },
3814 { "cvtpd2ps", { XM, EXx } },
3815 { "cvtsd2ss", { XM, EXq } },
3820 { "cvtdq2ps", { XM, EXx } },
3821 { "cvttps2dq", { XM, EXx } },
3822 { "cvtps2dq", { XM, EXx } },
3827 { "subps", { XM, EXx } },
3828 { "subss", { XM, EXd } },
3829 { "subpd", { XM, EXx } },
3830 { "subsd", { XM, EXq } },
3835 { "minps", { XM, EXx } },
3836 { "minss", { XM, EXd } },
3837 { "minpd", { XM, EXx } },
3838 { "minsd", { XM, EXq } },
3843 { "divps", { XM, EXx } },
3844 { "divss", { XM, EXd } },
3845 { "divpd", { XM, EXx } },
3846 { "divsd", { XM, EXq } },
3851 { "maxps", { XM, EXx } },
3852 { "maxss", { XM, EXd } },
3853 { "maxpd", { XM, EXx } },
3854 { "maxsd", { XM, EXq } },
3859 { "punpcklbw",{ MX, EMd } },
3861 { "punpcklbw",{ MX, EMx } },
3866 { "punpcklwd",{ MX, EMd } },
3868 { "punpcklwd",{ MX, EMx } },
3873 { "punpckldq",{ MX, EMd } },
3875 { "punpckldq",{ MX, EMx } },
3882 { "punpcklqdq", { XM, EXx } },
3889 { "punpckhqdq", { XM, EXx } },
3894 { "movq", { MX, EM } },
3895 { "movdqu", { XM, EXx } },
3896 { "movdqa", { XM, EXx } },
3901 { "pshufw", { MX, EM, Ib } },
3902 { "pshufhw",{ XM, EXx, Ib } },
3903 { "pshufd", { XM, EXx, Ib } },
3904 { "pshuflw",{ XM, EXx, Ib } },
3907 /* PREFIX_0F73_REG_3 */
3911 { "psrldq", { XS, Ib } },
3914 /* PREFIX_0F73_REG_7 */
3918 { "pslldq", { XS, Ib } },
3923 {"vmread", { Em, Gm } },
3925 {"extrq", { XS, Ib, Ib } },
3926 {"insertq", { XM, XS, Ib, Ib } },
3931 {"vmwrite", { Gm, Em } },
3933 {"extrq", { XM, XS } },
3934 {"insertq", { XM, XS } },
3941 { "haddpd", { XM, EXx } },
3942 { "haddps", { XM, EXx } },
3949 { "hsubpd", { XM, EXx } },
3950 { "hsubps", { XM, EXx } },
3955 { "movK", { Edq, MX } },
3956 { "movq", { XM, EXq } },
3957 { "movK", { Edq, XM } },
3962 { "movq", { EMS, MX } },
3963 { "movdqu", { EXxS, XM } },
3964 { "movdqa", { EXxS, XM } },
3967 /* PREFIX_0FAE_REG_0 */
3970 { "rdfsbase", { Ev } },
3973 /* PREFIX_0FAE_REG_1 */
3976 { "rdgsbase", { Ev } },
3979 /* PREFIX_0FAE_REG_2 */
3982 { "wrfsbase", { Ev } },
3985 /* PREFIX_0FAE_REG_3 */
3988 { "wrgsbase", { Ev } },
3991 /* PREFIX_0FAE_REG_6 */
3993 { "xsaveopt", { FXSAVE } },
3998 /* PREFIX_0FAE_REG_7 */
4000 { "clflush", { Mb } },
4002 { "clflushopt", { Mb } },
4005 /* PREFIX_RM_0_0FAE_REG_7 */
4007 { "sfence", { Skip_MODRM } },
4009 { "pcommit", { Skip_MODRM } },
4015 { "popcntS", { Gv, Ev } },
4020 { "bsfS", { Gv, Ev } },
4021 { "tzcntS", { Gv, Ev } },
4022 { "bsfS", { Gv, Ev } },
4027 { "bsrS", { Gv, Ev } },
4028 { "lzcntS", { Gv, Ev } },
4029 { "bsrS", { Gv, Ev } },
4034 { "cmpps", { XM, EXx, CMP } },
4035 { "cmpss", { XM, EXd, CMP } },
4036 { "cmppd", { XM, EXx, CMP } },
4037 { "cmpsd", { XM, EXq, CMP } },
4042 { "movntiS", { Ma, Gv } },
4045 /* PREFIX_0FC7_REG_6 */
4047 { "vmptrld",{ Mq } },
4048 { "vmxon", { Mq } },
4049 { "vmclear",{ Mq } },
4056 { "addsubpd", { XM, EXx } },
4057 { "addsubps", { XM, EXx } },
4063 { "movq2dq",{ XM, MS } },
4064 { "movq", { EXqS, XM } },
4065 { "movdq2q",{ MX, XS } },
4071 { "cvtdq2pd", { XM, EXq } },
4072 { "cvttpd2dq", { XM, EXx } },
4073 { "cvtpd2dq", { XM, EXx } },
4078 { "movntq", { Mq, MX } },
4080 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4088 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4093 { "maskmovq", { MX, MS } },
4095 { "maskmovdqu", { XM, XS } },
4102 { "pblendvb", { XM, EXx, XMM0 } },
4109 { "blendvps", { XM, EXx, XMM0 } },
4116 { "blendvpd", { XM, EXx, XMM0 } },
4123 { "ptest", { XM, EXx } },
4130 { "pmovsxbw", { XM, EXq } },
4137 { "pmovsxbd", { XM, EXd } },
4144 { "pmovsxbq", { XM, EXw } },
4151 { "pmovsxwd", { XM, EXq } },
4158 { "pmovsxwq", { XM, EXd } },
4165 { "pmovsxdq", { XM, EXq } },
4172 { "pmuldq", { XM, EXx } },
4179 { "pcmpeqq", { XM, EXx } },
4186 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4193 { "packusdw", { XM, EXx } },
4200 { "pmovzxbw", { XM, EXq } },
4207 { "pmovzxbd", { XM, EXd } },
4214 { "pmovzxbq", { XM, EXw } },
4221 { "pmovzxwd", { XM, EXq } },
4228 { "pmovzxwq", { XM, EXd } },
4235 { "pmovzxdq", { XM, EXq } },
4242 { "pcmpgtq", { XM, EXx } },
4249 { "pminsb", { XM, EXx } },
4256 { "pminsd", { XM, EXx } },
4263 { "pminuw", { XM, EXx } },
4270 { "pminud", { XM, EXx } },
4277 { "pmaxsb", { XM, EXx } },
4284 { "pmaxsd", { XM, EXx } },
4291 { "pmaxuw", { XM, EXx } },
4298 { "pmaxud", { XM, EXx } },
4305 { "pmulld", { XM, EXx } },
4312 { "phminposuw", { XM, EXx } },
4319 { "invept", { Gm, Mo } },
4326 { "invvpid", { Gm, Mo } },
4333 { "invpcid", { Gm, M } },
4338 { "sha1nexte", { XM, EXxmm } },
4343 { "sha1msg1", { XM, EXxmm } },
4348 { "sha1msg2", { XM, EXxmm } },
4353 { "sha256rnds2", { XM, EXxmm, XMM0 } },
4358 { "sha256msg1", { XM, EXxmm } },
4363 { "sha256msg2", { XM, EXxmm } },
4370 { "aesimc", { XM, EXx } },
4377 { "aesenc", { XM, EXx } },
4384 { "aesenclast", { XM, EXx } },
4391 { "aesdec", { XM, EXx } },
4398 { "aesdeclast", { XM, EXx } },
4403 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4405 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
4406 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
4411 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4413 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
4414 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
4420 { "adoxS", { Gdq, Edq} },
4421 { "adcxS", { Gdq, Edq} },
4429 { "roundps", { XM, EXx, Ib } },
4436 { "roundpd", { XM, EXx, Ib } },
4443 { "roundss", { XM, EXd, Ib } },
4450 { "roundsd", { XM, EXq, Ib } },
4457 { "blendps", { XM, EXx, Ib } },
4464 { "blendpd", { XM, EXx, Ib } },
4471 { "pblendw", { XM, EXx, Ib } },
4478 { "pextrb", { Edqb, XM, Ib } },
4485 { "pextrw", { Edqw, XM, Ib } },
4492 { "pextrK", { Edq, XM, Ib } },
4499 { "extractps", { Edqd, XM, Ib } },
4506 { "pinsrb", { XM, Edqb, Ib } },
4513 { "insertps", { XM, EXd, Ib } },
4520 { "pinsrK", { XM, Edq, Ib } },
4527 { "dpps", { XM, EXx, Ib } },
4534 { "dppd", { XM, EXx, Ib } },
4541 { "mpsadbw", { XM, EXx, Ib } },
4548 { "pclmulqdq", { XM, EXx, PCLMUL } },
4555 { "pcmpestrm", { XM, EXx, Ib } },
4562 { "pcmpestri", { XM, EXx, Ib } },
4569 { "pcmpistrm", { XM, EXx, Ib } },
4576 { "pcmpistri", { XM, EXx, Ib } },
4581 { "sha1rnds4", { XM, EXxmm, Ib } },
4588 { "aeskeygenassist", { XM, EXx, Ib } },
4591 /* PREFIX_VEX_0F10 */
4593 { VEX_W_TABLE (VEX_W_0F10_P_0) },
4594 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4595 { VEX_W_TABLE (VEX_W_0F10_P_2) },
4596 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4599 /* PREFIX_VEX_0F11 */
4601 { VEX_W_TABLE (VEX_W_0F11_P_0) },
4602 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4603 { VEX_W_TABLE (VEX_W_0F11_P_2) },
4604 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4607 /* PREFIX_VEX_0F12 */
4609 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4610 { VEX_W_TABLE (VEX_W_0F12_P_1) },
4611 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4612 { VEX_W_TABLE (VEX_W_0F12_P_3) },
4615 /* PREFIX_VEX_0F16 */
4617 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4618 { VEX_W_TABLE (VEX_W_0F16_P_1) },
4619 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4622 /* PREFIX_VEX_0F2A */
4625 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4627 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4630 /* PREFIX_VEX_0F2C */
4633 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4635 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4638 /* PREFIX_VEX_0F2D */
4641 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4643 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4646 /* PREFIX_VEX_0F2E */
4648 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4650 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4653 /* PREFIX_VEX_0F2F */
4655 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4657 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4660 /* PREFIX_VEX_0F41 */
4662 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4664 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4667 /* PREFIX_VEX_0F42 */
4669 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4671 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4674 /* PREFIX_VEX_0F44 */
4676 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4678 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4681 /* PREFIX_VEX_0F45 */
4683 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4685 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4688 /* PREFIX_VEX_0F46 */
4690 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4692 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4695 /* PREFIX_VEX_0F47 */
4697 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4699 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4702 /* PREFIX_VEX_0F4A */
4704 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4706 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4709 /* PREFIX_VEX_0F4B */
4711 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4713 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4716 /* PREFIX_VEX_0F51 */
4718 { VEX_W_TABLE (VEX_W_0F51_P_0) },
4719 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4720 { VEX_W_TABLE (VEX_W_0F51_P_2) },
4721 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4724 /* PREFIX_VEX_0F52 */
4726 { VEX_W_TABLE (VEX_W_0F52_P_0) },
4727 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4730 /* PREFIX_VEX_0F53 */
4732 { VEX_W_TABLE (VEX_W_0F53_P_0) },
4733 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4736 /* PREFIX_VEX_0F58 */
4738 { VEX_W_TABLE (VEX_W_0F58_P_0) },
4739 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4740 { VEX_W_TABLE (VEX_W_0F58_P_2) },
4741 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4744 /* PREFIX_VEX_0F59 */
4746 { VEX_W_TABLE (VEX_W_0F59_P_0) },
4747 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4748 { VEX_W_TABLE (VEX_W_0F59_P_2) },
4749 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4752 /* PREFIX_VEX_0F5A */
4754 { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4755 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4756 { "vcvtpd2ps%XY", { XMM, EXx } },
4757 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4760 /* PREFIX_VEX_0F5B */
4762 { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4763 { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4764 { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4767 /* PREFIX_VEX_0F5C */
4769 { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4770 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4771 { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4772 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4775 /* PREFIX_VEX_0F5D */
4777 { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4778 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4779 { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4780 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4783 /* PREFIX_VEX_0F5E */
4785 { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4786 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4787 { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4788 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4791 /* PREFIX_VEX_0F5F */
4793 { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4794 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4795 { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4796 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4799 /* PREFIX_VEX_0F60 */
4803 { VEX_W_TABLE (VEX_W_0F60_P_2) },
4806 /* PREFIX_VEX_0F61 */
4810 { VEX_W_TABLE (VEX_W_0F61_P_2) },
4813 /* PREFIX_VEX_0F62 */
4817 { VEX_W_TABLE (VEX_W_0F62_P_2) },
4820 /* PREFIX_VEX_0F63 */
4824 { VEX_W_TABLE (VEX_W_0F63_P_2) },
4827 /* PREFIX_VEX_0F64 */
4831 { VEX_W_TABLE (VEX_W_0F64_P_2) },
4834 /* PREFIX_VEX_0F65 */
4838 { VEX_W_TABLE (VEX_W_0F65_P_2) },
4841 /* PREFIX_VEX_0F66 */
4845 { VEX_W_TABLE (VEX_W_0F66_P_2) },
4848 /* PREFIX_VEX_0F67 */
4852 { VEX_W_TABLE (VEX_W_0F67_P_2) },
4855 /* PREFIX_VEX_0F68 */
4859 { VEX_W_TABLE (VEX_W_0F68_P_2) },
4862 /* PREFIX_VEX_0F69 */
4866 { VEX_W_TABLE (VEX_W_0F69_P_2) },
4869 /* PREFIX_VEX_0F6A */
4873 { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4876 /* PREFIX_VEX_0F6B */
4880 { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4883 /* PREFIX_VEX_0F6C */
4887 { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4890 /* PREFIX_VEX_0F6D */
4894 { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4897 /* PREFIX_VEX_0F6E */
4901 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4904 /* PREFIX_VEX_0F6F */
4907 { VEX_W_TABLE (VEX_W_0F6F_P_1) },
4908 { VEX_W_TABLE (VEX_W_0F6F_P_2) },
4911 /* PREFIX_VEX_0F70 */
4914 { VEX_W_TABLE (VEX_W_0F70_P_1) },
4915 { VEX_W_TABLE (VEX_W_0F70_P_2) },
4916 { VEX_W_TABLE (VEX_W_0F70_P_3) },
4919 /* PREFIX_VEX_0F71_REG_2 */
4923 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
4926 /* PREFIX_VEX_0F71_REG_4 */
4930 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
4933 /* PREFIX_VEX_0F71_REG_6 */
4937 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
4940 /* PREFIX_VEX_0F72_REG_2 */
4944 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
4947 /* PREFIX_VEX_0F72_REG_4 */
4951 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
4954 /* PREFIX_VEX_0F72_REG_6 */
4958 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
4961 /* PREFIX_VEX_0F73_REG_2 */
4965 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
4968 /* PREFIX_VEX_0F73_REG_3 */
4972 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
4975 /* PREFIX_VEX_0F73_REG_6 */
4979 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
4982 /* PREFIX_VEX_0F73_REG_7 */
4986 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
4989 /* PREFIX_VEX_0F74 */
4993 { VEX_W_TABLE (VEX_W_0F74_P_2) },
4996 /* PREFIX_VEX_0F75 */
5000 { VEX_W_TABLE (VEX_W_0F75_P_2) },
5003 /* PREFIX_VEX_0F76 */
5007 { VEX_W_TABLE (VEX_W_0F76_P_2) },
5010 /* PREFIX_VEX_0F77 */
5012 { VEX_W_TABLE (VEX_W_0F77_P_0) },
5015 /* PREFIX_VEX_0F7C */
5019 { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5020 { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5023 /* PREFIX_VEX_0F7D */
5027 { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5028 { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5031 /* PREFIX_VEX_0F7E */
5034 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5035 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5038 /* PREFIX_VEX_0F7F */
5041 { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5042 { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5045 /* PREFIX_VEX_0F90 */
5047 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5049 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5052 /* PREFIX_VEX_0F91 */
5054 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5056 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5059 /* PREFIX_VEX_0F92 */
5061 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5063 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5064 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5067 /* PREFIX_VEX_0F93 */
5069 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5071 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5072 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5075 /* PREFIX_VEX_0F98 */
5077 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5079 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5082 /* PREFIX_VEX_0F99 */
5084 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5086 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5089 /* PREFIX_VEX_0FC2 */
5091 { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5092 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5093 { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5094 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5097 /* PREFIX_VEX_0FC4 */
5101 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5104 /* PREFIX_VEX_0FC5 */
5108 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5111 /* PREFIX_VEX_0FD0 */
5115 { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5116 { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5119 /* PREFIX_VEX_0FD1 */
5123 { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5126 /* PREFIX_VEX_0FD2 */
5130 { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5133 /* PREFIX_VEX_0FD3 */
5137 { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5140 /* PREFIX_VEX_0FD4 */
5144 { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5147 /* PREFIX_VEX_0FD5 */
5151 { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5154 /* PREFIX_VEX_0FD6 */
5158 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5161 /* PREFIX_VEX_0FD7 */
5165 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5168 /* PREFIX_VEX_0FD8 */
5172 { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5175 /* PREFIX_VEX_0FD9 */
5179 { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5182 /* PREFIX_VEX_0FDA */
5186 { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5189 /* PREFIX_VEX_0FDB */
5193 { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5196 /* PREFIX_VEX_0FDC */
5200 { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5203 /* PREFIX_VEX_0FDD */
5207 { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5210 /* PREFIX_VEX_0FDE */
5214 { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5217 /* PREFIX_VEX_0FDF */
5221 { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5224 /* PREFIX_VEX_0FE0 */
5228 { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5231 /* PREFIX_VEX_0FE1 */
5235 { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5238 /* PREFIX_VEX_0FE2 */
5242 { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5245 /* PREFIX_VEX_0FE3 */
5249 { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5252 /* PREFIX_VEX_0FE4 */
5256 { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5259 /* PREFIX_VEX_0FE5 */
5263 { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5266 /* PREFIX_VEX_0FE6 */
5269 { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5270 { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5271 { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5274 /* PREFIX_VEX_0FE7 */
5278 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5281 /* PREFIX_VEX_0FE8 */
5285 { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5288 /* PREFIX_VEX_0FE9 */
5292 { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5295 /* PREFIX_VEX_0FEA */
5299 { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5302 /* PREFIX_VEX_0FEB */
5306 { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5309 /* PREFIX_VEX_0FEC */
5313 { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5316 /* PREFIX_VEX_0FED */
5320 { VEX_W_TABLE (VEX_W_0FED_P_2) },
5323 /* PREFIX_VEX_0FEE */
5327 { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5330 /* PREFIX_VEX_0FEF */
5334 { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5337 /* PREFIX_VEX_0FF0 */
5342 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5345 /* PREFIX_VEX_0FF1 */
5349 { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5352 /* PREFIX_VEX_0FF2 */
5356 { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5359 /* PREFIX_VEX_0FF3 */
5363 { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5366 /* PREFIX_VEX_0FF4 */
5370 { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5373 /* PREFIX_VEX_0FF5 */
5377 { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5380 /* PREFIX_VEX_0FF6 */
5384 { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5387 /* PREFIX_VEX_0FF7 */
5391 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5394 /* PREFIX_VEX_0FF8 */
5398 { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5401 /* PREFIX_VEX_0FF9 */
5405 { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5408 /* PREFIX_VEX_0FFA */
5412 { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5415 /* PREFIX_VEX_0FFB */
5419 { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5422 /* PREFIX_VEX_0FFC */
5426 { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5429 /* PREFIX_VEX_0FFD */
5433 { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5436 /* PREFIX_VEX_0FFE */
5440 { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5443 /* PREFIX_VEX_0F3800 */
5447 { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5450 /* PREFIX_VEX_0F3801 */
5454 { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5457 /* PREFIX_VEX_0F3802 */
5461 { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5464 /* PREFIX_VEX_0F3803 */
5468 { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5471 /* PREFIX_VEX_0F3804 */
5475 { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5478 /* PREFIX_VEX_0F3805 */
5482 { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5485 /* PREFIX_VEX_0F3806 */
5489 { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5492 /* PREFIX_VEX_0F3807 */
5496 { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5499 /* PREFIX_VEX_0F3808 */
5503 { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5506 /* PREFIX_VEX_0F3809 */
5510 { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5513 /* PREFIX_VEX_0F380A */
5517 { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5520 /* PREFIX_VEX_0F380B */
5524 { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5527 /* PREFIX_VEX_0F380C */
5531 { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5534 /* PREFIX_VEX_0F380D */
5538 { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5541 /* PREFIX_VEX_0F380E */
5545 { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5548 /* PREFIX_VEX_0F380F */
5552 { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5555 /* PREFIX_VEX_0F3813 */
5559 { "vcvtph2ps", { XM, EXxmmq } },
5562 /* PREFIX_VEX_0F3816 */
5566 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5569 /* PREFIX_VEX_0F3817 */
5573 { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5576 /* PREFIX_VEX_0F3818 */
5580 { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5583 /* PREFIX_VEX_0F3819 */
5587 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5590 /* PREFIX_VEX_0F381A */
5594 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5597 /* PREFIX_VEX_0F381C */
5601 { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5604 /* PREFIX_VEX_0F381D */
5608 { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5611 /* PREFIX_VEX_0F381E */
5615 { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5618 /* PREFIX_VEX_0F3820 */
5622 { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5625 /* PREFIX_VEX_0F3821 */
5629 { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5632 /* PREFIX_VEX_0F3822 */
5636 { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5639 /* PREFIX_VEX_0F3823 */
5643 { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5646 /* PREFIX_VEX_0F3824 */
5650 { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5653 /* PREFIX_VEX_0F3825 */
5657 { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5660 /* PREFIX_VEX_0F3828 */
5664 { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5667 /* PREFIX_VEX_0F3829 */
5671 { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5674 /* PREFIX_VEX_0F382A */
5678 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5681 /* PREFIX_VEX_0F382B */
5685 { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5688 /* PREFIX_VEX_0F382C */
5692 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5695 /* PREFIX_VEX_0F382D */
5699 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5702 /* PREFIX_VEX_0F382E */
5706 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5709 /* PREFIX_VEX_0F382F */
5713 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5716 /* PREFIX_VEX_0F3830 */
5720 { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5723 /* PREFIX_VEX_0F3831 */
5727 { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5730 /* PREFIX_VEX_0F3832 */
5734 { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5737 /* PREFIX_VEX_0F3833 */
5741 { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5744 /* PREFIX_VEX_0F3834 */
5748 { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5751 /* PREFIX_VEX_0F3835 */
5755 { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5758 /* PREFIX_VEX_0F3836 */
5762 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5765 /* PREFIX_VEX_0F3837 */
5769 { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5772 /* PREFIX_VEX_0F3838 */
5776 { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5779 /* PREFIX_VEX_0F3839 */
5783 { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5786 /* PREFIX_VEX_0F383A */
5790 { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5793 /* PREFIX_VEX_0F383B */
5797 { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5800 /* PREFIX_VEX_0F383C */
5804 { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5807 /* PREFIX_VEX_0F383D */
5811 { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5814 /* PREFIX_VEX_0F383E */
5818 { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5821 /* PREFIX_VEX_0F383F */
5825 { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5828 /* PREFIX_VEX_0F3840 */
5832 { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5835 /* PREFIX_VEX_0F3841 */
5839 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5842 /* PREFIX_VEX_0F3845 */
5846 { "vpsrlv%LW", { XM, Vex, EXx } },
5849 /* PREFIX_VEX_0F3846 */
5853 { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5856 /* PREFIX_VEX_0F3847 */
5860 { "vpsllv%LW", { XM, Vex, EXx } },
5863 /* PREFIX_VEX_0F3858 */
5867 { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5870 /* PREFIX_VEX_0F3859 */
5874 { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5877 /* PREFIX_VEX_0F385A */
5881 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5884 /* PREFIX_VEX_0F3878 */
5888 { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5891 /* PREFIX_VEX_0F3879 */
5895 { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5898 /* PREFIX_VEX_0F388C */
5902 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5905 /* PREFIX_VEX_0F388E */
5909 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5912 /* PREFIX_VEX_0F3890 */
5916 { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } },
5919 /* PREFIX_VEX_0F3891 */
5923 { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5926 /* PREFIX_VEX_0F3892 */
5930 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } },
5933 /* PREFIX_VEX_0F3893 */
5937 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5940 /* PREFIX_VEX_0F3896 */
5944 { "vfmaddsub132p%XW", { XM, Vex, EXx } },
5947 /* PREFIX_VEX_0F3897 */
5951 { "vfmsubadd132p%XW", { XM, Vex, EXx } },
5954 /* PREFIX_VEX_0F3898 */
5958 { "vfmadd132p%XW", { XM, Vex, EXx } },
5961 /* PREFIX_VEX_0F3899 */
5965 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5968 /* PREFIX_VEX_0F389A */
5972 { "vfmsub132p%XW", { XM, Vex, EXx } },
5975 /* PREFIX_VEX_0F389B */
5979 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5982 /* PREFIX_VEX_0F389C */
5986 { "vfnmadd132p%XW", { XM, Vex, EXx } },
5989 /* PREFIX_VEX_0F389D */
5993 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5996 /* PREFIX_VEX_0F389E */
6000 { "vfnmsub132p%XW", { XM, Vex, EXx } },
6003 /* PREFIX_VEX_0F389F */
6007 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6010 /* PREFIX_VEX_0F38A6 */
6014 { "vfmaddsub213p%XW", { XM, Vex, EXx } },
6018 /* PREFIX_VEX_0F38A7 */
6022 { "vfmsubadd213p%XW", { XM, Vex, EXx } },
6025 /* PREFIX_VEX_0F38A8 */
6029 { "vfmadd213p%XW", { XM, Vex, EXx } },
6032 /* PREFIX_VEX_0F38A9 */
6036 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6039 /* PREFIX_VEX_0F38AA */
6043 { "vfmsub213p%XW", { XM, Vex, EXx } },
6046 /* PREFIX_VEX_0F38AB */
6050 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6053 /* PREFIX_VEX_0F38AC */
6057 { "vfnmadd213p%XW", { XM, Vex, EXx } },
6060 /* PREFIX_VEX_0F38AD */
6064 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6067 /* PREFIX_VEX_0F38AE */
6071 { "vfnmsub213p%XW", { XM, Vex, EXx } },
6074 /* PREFIX_VEX_0F38AF */
6078 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6081 /* PREFIX_VEX_0F38B6 */
6085 { "vfmaddsub231p%XW", { XM, Vex, EXx } },
6088 /* PREFIX_VEX_0F38B7 */
6092 { "vfmsubadd231p%XW", { XM, Vex, EXx } },
6095 /* PREFIX_VEX_0F38B8 */
6099 { "vfmadd231p%XW", { XM, Vex, EXx } },
6102 /* PREFIX_VEX_0F38B9 */
6106 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6109 /* PREFIX_VEX_0F38BA */
6113 { "vfmsub231p%XW", { XM, Vex, EXx } },
6116 /* PREFIX_VEX_0F38BB */
6120 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6123 /* PREFIX_VEX_0F38BC */
6127 { "vfnmadd231p%XW", { XM, Vex, EXx } },
6130 /* PREFIX_VEX_0F38BD */
6134 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6137 /* PREFIX_VEX_0F38BE */
6141 { "vfnmsub231p%XW", { XM, Vex, EXx } },
6144 /* PREFIX_VEX_0F38BF */
6148 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6151 /* PREFIX_VEX_0F38DB */
6155 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6158 /* PREFIX_VEX_0F38DC */
6162 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6165 /* PREFIX_VEX_0F38DD */
6169 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6172 /* PREFIX_VEX_0F38DE */
6176 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6179 /* PREFIX_VEX_0F38DF */
6183 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6186 /* PREFIX_VEX_0F38F2 */
6188 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6191 /* PREFIX_VEX_0F38F3_REG_1 */
6193 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6196 /* PREFIX_VEX_0F38F3_REG_2 */
6198 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6201 /* PREFIX_VEX_0F38F3_REG_3 */
6203 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6206 /* PREFIX_VEX_0F38F5 */
6208 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6209 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6211 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6214 /* PREFIX_VEX_0F38F6 */
6219 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6222 /* PREFIX_VEX_0F38F7 */
6224 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6225 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6226 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6227 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6230 /* PREFIX_VEX_0F3A00 */
6234 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6237 /* PREFIX_VEX_0F3A01 */
6241 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6244 /* PREFIX_VEX_0F3A02 */
6248 { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6251 /* PREFIX_VEX_0F3A04 */
6255 { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6258 /* PREFIX_VEX_0F3A05 */
6262 { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6265 /* PREFIX_VEX_0F3A06 */
6269 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6272 /* PREFIX_VEX_0F3A08 */
6276 { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6279 /* PREFIX_VEX_0F3A09 */
6283 { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6286 /* PREFIX_VEX_0F3A0A */
6290 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6293 /* PREFIX_VEX_0F3A0B */
6297 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6300 /* PREFIX_VEX_0F3A0C */
6304 { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6307 /* PREFIX_VEX_0F3A0D */
6311 { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6314 /* PREFIX_VEX_0F3A0E */
6318 { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6321 /* PREFIX_VEX_0F3A0F */
6325 { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6328 /* PREFIX_VEX_0F3A14 */
6332 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6335 /* PREFIX_VEX_0F3A15 */
6339 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6342 /* PREFIX_VEX_0F3A16 */
6346 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6349 /* PREFIX_VEX_0F3A17 */
6353 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6356 /* PREFIX_VEX_0F3A18 */
6360 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6363 /* PREFIX_VEX_0F3A19 */
6367 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6370 /* PREFIX_VEX_0F3A1D */
6374 { "vcvtps2ph", { EXxmmq, XM, Ib } },
6377 /* PREFIX_VEX_0F3A20 */
6381 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6384 /* PREFIX_VEX_0F3A21 */
6388 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6391 /* PREFIX_VEX_0F3A22 */
6395 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6398 /* PREFIX_VEX_0F3A30 */
6402 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6405 /* PREFIX_VEX_0F3A31 */
6409 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6412 /* PREFIX_VEX_0F3A32 */
6416 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6419 /* PREFIX_VEX_0F3A33 */
6423 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6426 /* PREFIX_VEX_0F3A38 */
6430 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6433 /* PREFIX_VEX_0F3A39 */
6437 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6440 /* PREFIX_VEX_0F3A40 */
6444 { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6447 /* PREFIX_VEX_0F3A41 */
6451 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6454 /* PREFIX_VEX_0F3A42 */
6458 { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6461 /* PREFIX_VEX_0F3A44 */
6465 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6468 /* PREFIX_VEX_0F3A46 */
6472 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6475 /* PREFIX_VEX_0F3A48 */
6479 { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6482 /* PREFIX_VEX_0F3A49 */
6486 { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6489 /* PREFIX_VEX_0F3A4A */
6493 { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6496 /* PREFIX_VEX_0F3A4B */
6500 { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6503 /* PREFIX_VEX_0F3A4C */
6507 { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6510 /* PREFIX_VEX_0F3A5C */
6514 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6517 /* PREFIX_VEX_0F3A5D */
6521 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6524 /* PREFIX_VEX_0F3A5E */
6528 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6531 /* PREFIX_VEX_0F3A5F */
6535 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6538 /* PREFIX_VEX_0F3A60 */
6542 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6546 /* PREFIX_VEX_0F3A61 */
6550 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6553 /* PREFIX_VEX_0F3A62 */
6557 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6560 /* PREFIX_VEX_0F3A63 */
6564 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6567 /* PREFIX_VEX_0F3A68 */
6571 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6574 /* PREFIX_VEX_0F3A69 */
6578 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6581 /* PREFIX_VEX_0F3A6A */
6585 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6588 /* PREFIX_VEX_0F3A6B */
6592 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6595 /* PREFIX_VEX_0F3A6C */
6599 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6602 /* PREFIX_VEX_0F3A6D */
6606 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6609 /* PREFIX_VEX_0F3A6E */
6613 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6616 /* PREFIX_VEX_0F3A6F */
6620 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6623 /* PREFIX_VEX_0F3A78 */
6627 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6630 /* PREFIX_VEX_0F3A79 */
6634 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6637 /* PREFIX_VEX_0F3A7A */
6641 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6644 /* PREFIX_VEX_0F3A7B */
6648 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6651 /* PREFIX_VEX_0F3A7C */
6655 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6659 /* PREFIX_VEX_0F3A7D */
6663 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6666 /* PREFIX_VEX_0F3A7E */
6670 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6673 /* PREFIX_VEX_0F3A7F */
6677 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6680 /* PREFIX_VEX_0F3ADF */
6684 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6687 /* PREFIX_VEX_0F3AF0 */
6692 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6695 #define NEED_PREFIX_TABLE
6696 #include "i386-dis-evex.h"
6697 #undef NEED_PREFIX_TABLE
6700 static const struct dis386 x86_64_table[][2] = {
6703 { "pushP", { es } },
6713 { "pushP", { cs } },
6718 { "pushP", { ss } },
6728 { "pushP", { ds } },
6758 { "pushaP", { XX } },
6763 { "popaP", { XX } },
6768 { MOD_TABLE (MOD_62_32BIT) },
6769 { EVEX_TABLE (EVEX_0F) },
6774 { "arpl", { Ew, Gw } },
6775 { "movs{lq|xd}", { Gv, Ed } },
6780 { "ins{R|}", { Yzr, indirDX } },
6781 { "ins{G|}", { Yzr, indirDX } },
6786 { "outs{R|}", { indirDXr, Xz } },
6787 { "outs{G|}", { indirDXr, Xz } },
6792 { "Jcall{T|}", { Ap } },
6797 { MOD_TABLE (MOD_C4_32BIT) },
6798 { VEX_C4_TABLE (VEX_0F) },
6803 { MOD_TABLE (MOD_C5_32BIT) },
6804 { VEX_C5_TABLE (VEX_0F) },
6824 { "Jjmp{T|}", { Ap } },
6827 /* X86_64_0F01_REG_0 */
6829 { "sgdt{Q|IQ}", { M } },
6833 /* X86_64_0F01_REG_1 */
6835 { "sidt{Q|IQ}", { M } },
6839 /* X86_64_0F01_REG_2 */
6841 { "lgdt{Q|Q}", { M } },
6845 /* X86_64_0F01_REG_3 */
6847 { "lidt{Q|Q}", { M } },
6852 static const struct dis386 three_byte_table[][256] = {
6854 /* THREE_BYTE_0F38 */
6857 { "pshufb", { MX, EM } },
6858 { "phaddw", { MX, EM } },
6859 { "phaddd", { MX, EM } },
6860 { "phaddsw", { MX, EM } },
6861 { "pmaddubsw", { MX, EM } },
6862 { "phsubw", { MX, EM } },
6863 { "phsubd", { MX, EM } },
6864 { "phsubsw", { MX, EM } },
6866 { "psignb", { MX, EM } },
6867 { "psignw", { MX, EM } },
6868 { "psignd", { MX, EM } },
6869 { "pmulhrsw", { MX, EM } },
6875 { PREFIX_TABLE (PREFIX_0F3810) },
6879 { PREFIX_TABLE (PREFIX_0F3814) },
6880 { PREFIX_TABLE (PREFIX_0F3815) },
6882 { PREFIX_TABLE (PREFIX_0F3817) },
6888 { "pabsb", { MX, EM } },
6889 { "pabsw", { MX, EM } },
6890 { "pabsd", { MX, EM } },
6893 { PREFIX_TABLE (PREFIX_0F3820) },
6894 { PREFIX_TABLE (PREFIX_0F3821) },
6895 { PREFIX_TABLE (PREFIX_0F3822) },
6896 { PREFIX_TABLE (PREFIX_0F3823) },
6897 { PREFIX_TABLE (PREFIX_0F3824) },
6898 { PREFIX_TABLE (PREFIX_0F3825) },
6902 { PREFIX_TABLE (PREFIX_0F3828) },
6903 { PREFIX_TABLE (PREFIX_0F3829) },
6904 { PREFIX_TABLE (PREFIX_0F382A) },
6905 { PREFIX_TABLE (PREFIX_0F382B) },
6911 { PREFIX_TABLE (PREFIX_0F3830) },
6912 { PREFIX_TABLE (PREFIX_0F3831) },
6913 { PREFIX_TABLE (PREFIX_0F3832) },
6914 { PREFIX_TABLE (PREFIX_0F3833) },
6915 { PREFIX_TABLE (PREFIX_0F3834) },
6916 { PREFIX_TABLE (PREFIX_0F3835) },
6918 { PREFIX_TABLE (PREFIX_0F3837) },
6920 { PREFIX_TABLE (PREFIX_0F3838) },
6921 { PREFIX_TABLE (PREFIX_0F3839) },
6922 { PREFIX_TABLE (PREFIX_0F383A) },
6923 { PREFIX_TABLE (PREFIX_0F383B) },
6924 { PREFIX_TABLE (PREFIX_0F383C) },
6925 { PREFIX_TABLE (PREFIX_0F383D) },
6926 { PREFIX_TABLE (PREFIX_0F383E) },
6927 { PREFIX_TABLE (PREFIX_0F383F) },
6929 { PREFIX_TABLE (PREFIX_0F3840) },
6930 { PREFIX_TABLE (PREFIX_0F3841) },
7001 { PREFIX_TABLE (PREFIX_0F3880) },
7002 { PREFIX_TABLE (PREFIX_0F3881) },
7003 { PREFIX_TABLE (PREFIX_0F3882) },
7082 { PREFIX_TABLE (PREFIX_0F38C8) },
7083 { PREFIX_TABLE (PREFIX_0F38C9) },
7084 { PREFIX_TABLE (PREFIX_0F38CA) },
7085 { PREFIX_TABLE (PREFIX_0F38CB) },
7086 { PREFIX_TABLE (PREFIX_0F38CC) },
7087 { PREFIX_TABLE (PREFIX_0F38CD) },
7103 { PREFIX_TABLE (PREFIX_0F38DB) },
7104 { PREFIX_TABLE (PREFIX_0F38DC) },
7105 { PREFIX_TABLE (PREFIX_0F38DD) },
7106 { PREFIX_TABLE (PREFIX_0F38DE) },
7107 { PREFIX_TABLE (PREFIX_0F38DF) },
7127 { PREFIX_TABLE (PREFIX_0F38F0) },
7128 { PREFIX_TABLE (PREFIX_0F38F1) },
7133 { PREFIX_TABLE (PREFIX_0F38F6) },
7145 /* THREE_BYTE_0F3A */
7157 { PREFIX_TABLE (PREFIX_0F3A08) },
7158 { PREFIX_TABLE (PREFIX_0F3A09) },
7159 { PREFIX_TABLE (PREFIX_0F3A0A) },
7160 { PREFIX_TABLE (PREFIX_0F3A0B) },
7161 { PREFIX_TABLE (PREFIX_0F3A0C) },
7162 { PREFIX_TABLE (PREFIX_0F3A0D) },
7163 { PREFIX_TABLE (PREFIX_0F3A0E) },
7164 { "palignr", { MX, EM, Ib } },
7170 { PREFIX_TABLE (PREFIX_0F3A14) },
7171 { PREFIX_TABLE (PREFIX_0F3A15) },
7172 { PREFIX_TABLE (PREFIX_0F3A16) },
7173 { PREFIX_TABLE (PREFIX_0F3A17) },
7184 { PREFIX_TABLE (PREFIX_0F3A20) },
7185 { PREFIX_TABLE (PREFIX_0F3A21) },
7186 { PREFIX_TABLE (PREFIX_0F3A22) },
7220 { PREFIX_TABLE (PREFIX_0F3A40) },
7221 { PREFIX_TABLE (PREFIX_0F3A41) },
7222 { PREFIX_TABLE (PREFIX_0F3A42) },
7224 { PREFIX_TABLE (PREFIX_0F3A44) },
7256 { PREFIX_TABLE (PREFIX_0F3A60) },
7257 { PREFIX_TABLE (PREFIX_0F3A61) },
7258 { PREFIX_TABLE (PREFIX_0F3A62) },
7259 { PREFIX_TABLE (PREFIX_0F3A63) },
7377 { PREFIX_TABLE (PREFIX_0F3ACC) },
7398 { PREFIX_TABLE (PREFIX_0F3ADF) },
7437 /* THREE_BYTE_0F7A */
7476 { "ptest", { XX } },
7513 { "phaddbw", { XM, EXq } },
7514 { "phaddbd", { XM, EXq } },
7515 { "phaddbq", { XM, EXq } },
7518 { "phaddwd", { XM, EXq } },
7519 { "phaddwq", { XM, EXq } },
7524 { "phadddq", { XM, EXq } },
7531 { "phaddubw", { XM, EXq } },
7532 { "phaddubd", { XM, EXq } },
7533 { "phaddubq", { XM, EXq } },
7536 { "phadduwd", { XM, EXq } },
7537 { "phadduwq", { XM, EXq } },
7542 { "phaddudq", { XM, EXq } },
7549 { "phsubbw", { XM, EXq } },
7550 { "phsubbd", { XM, EXq } },
7551 { "phsubbq", { XM, EXq } },
7730 static const struct dis386 xop_table[][256] = {
7883 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7884 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7885 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7893 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7894 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7901 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7902 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7903 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7911 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7912 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7916 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7917 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7920 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7938 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7950 { "vprotb", { XM, Vex_2src_1, Ib } },
7951 { "vprotw", { XM, Vex_2src_1, Ib } },
7952 { "vprotd", { XM, Vex_2src_1, Ib } },
7953 { "vprotq", { XM, Vex_2src_1, Ib } },
7963 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7964 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7965 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7966 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7999 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
8000 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
8001 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
8002 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
8026 { REG_TABLE (REG_XOP_TBM_01) },
8027 { REG_TABLE (REG_XOP_TBM_02) },
8045 { REG_TABLE (REG_XOP_LWPCB) },
8169 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8170 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8171 { "vfrczss", { XM, EXd } },
8172 { "vfrczsd", { XM, EXq } },
8187 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 } },
8188 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 } },
8189 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 } },
8190 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 } },
8191 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 } },
8192 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 } },
8193 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 } },
8194 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 } },
8196 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 } },
8197 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 } },
8198 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 } },
8199 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 } },
8242 { "vphaddbw", { XM, EXxmm } },
8243 { "vphaddbd", { XM, EXxmm } },
8244 { "vphaddbq", { XM, EXxmm } },
8247 { "vphaddwd", { XM, EXxmm } },
8248 { "vphaddwq", { XM, EXxmm } },
8253 { "vphadddq", { XM, EXxmm } },
8260 { "vphaddubw", { XM, EXxmm } },
8261 { "vphaddubd", { XM, EXxmm } },
8262 { "vphaddubq", { XM, EXxmm } },
8265 { "vphadduwd", { XM, EXxmm } },
8266 { "vphadduwq", { XM, EXxmm } },
8271 { "vphaddudq", { XM, EXxmm } },
8278 { "vphsubbw", { XM, EXxmm } },
8279 { "vphsubwd", { XM, EXxmm } },
8280 { "vphsubdq", { XM, EXxmm } },
8334 { "bextr", { Gv, Ev, Iq } },
8336 { REG_TABLE (REG_XOP_LWP) },
8606 static const struct dis386 vex_table[][256] = {
8628 { PREFIX_TABLE (PREFIX_VEX_0F10) },
8629 { PREFIX_TABLE (PREFIX_VEX_0F11) },
8630 { PREFIX_TABLE (PREFIX_VEX_0F12) },
8631 { MOD_TABLE (MOD_VEX_0F13) },
8632 { VEX_W_TABLE (VEX_W_0F14) },
8633 { VEX_W_TABLE (VEX_W_0F15) },
8634 { PREFIX_TABLE (PREFIX_VEX_0F16) },
8635 { MOD_TABLE (MOD_VEX_0F17) },
8655 { VEX_W_TABLE (VEX_W_0F28) },
8656 { VEX_W_TABLE (VEX_W_0F29) },
8657 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8658 { MOD_TABLE (MOD_VEX_0F2B) },
8659 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8660 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8661 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8662 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8683 { PREFIX_TABLE (PREFIX_VEX_0F41) },
8684 { PREFIX_TABLE (PREFIX_VEX_0F42) },
8686 { PREFIX_TABLE (PREFIX_VEX_0F44) },
8687 { PREFIX_TABLE (PREFIX_VEX_0F45) },
8688 { PREFIX_TABLE (PREFIX_VEX_0F46) },
8689 { PREFIX_TABLE (PREFIX_VEX_0F47) },
8693 { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8694 { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8700 { MOD_TABLE (MOD_VEX_0F50) },
8701 { PREFIX_TABLE (PREFIX_VEX_0F51) },
8702 { PREFIX_TABLE (PREFIX_VEX_0F52) },
8703 { PREFIX_TABLE (PREFIX_VEX_0F53) },
8704 { "vandpX", { XM, Vex, EXx } },
8705 { "vandnpX", { XM, Vex, EXx } },
8706 { "vorpX", { XM, Vex, EXx } },
8707 { "vxorpX", { XM, Vex, EXx } },
8709 { PREFIX_TABLE (PREFIX_VEX_0F58) },
8710 { PREFIX_TABLE (PREFIX_VEX_0F59) },
8711 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8712 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8713 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8714 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8715 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8716 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8718 { PREFIX_TABLE (PREFIX_VEX_0F60) },
8719 { PREFIX_TABLE (PREFIX_VEX_0F61) },
8720 { PREFIX_TABLE (PREFIX_VEX_0F62) },
8721 { PREFIX_TABLE (PREFIX_VEX_0F63) },
8722 { PREFIX_TABLE (PREFIX_VEX_0F64) },
8723 { PREFIX_TABLE (PREFIX_VEX_0F65) },
8724 { PREFIX_TABLE (PREFIX_VEX_0F66) },
8725 { PREFIX_TABLE (PREFIX_VEX_0F67) },
8727 { PREFIX_TABLE (PREFIX_VEX_0F68) },
8728 { PREFIX_TABLE (PREFIX_VEX_0F69) },
8729 { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8730 { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8731 { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8732 { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8733 { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8734 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8736 { PREFIX_TABLE (PREFIX_VEX_0F70) },
8737 { REG_TABLE (REG_VEX_0F71) },
8738 { REG_TABLE (REG_VEX_0F72) },
8739 { REG_TABLE (REG_VEX_0F73) },
8740 { PREFIX_TABLE (PREFIX_VEX_0F74) },
8741 { PREFIX_TABLE (PREFIX_VEX_0F75) },
8742 { PREFIX_TABLE (PREFIX_VEX_0F76) },
8743 { PREFIX_TABLE (PREFIX_VEX_0F77) },
8749 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8750 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8751 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8752 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F90) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F91) },
8774 { PREFIX_TABLE (PREFIX_VEX_0F92) },
8775 { PREFIX_TABLE (PREFIX_VEX_0F93) },
8781 { PREFIX_TABLE (PREFIX_VEX_0F98) },
8782 { PREFIX_TABLE (PREFIX_VEX_0F99) },
8805 { REG_TABLE (REG_VEX_0FAE) },
8828 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8830 { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8831 { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8832 { "vshufpX", { XM, Vex, EXx, Ib } },
8844 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8845 { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8846 { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8847 { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8848 { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8849 { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8850 { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8851 { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8853 { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8854 { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8855 { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8856 { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8857 { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8858 { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8859 { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8860 { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8862 { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8863 { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8864 { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8865 { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8866 { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8867 { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8868 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8869 { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8871 { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8872 { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8873 { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8874 { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8875 { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8876 { PREFIX_TABLE (PREFIX_VEX_0FED) },
8877 { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8878 { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8880 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8881 { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8882 { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8883 { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8884 { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8885 { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8886 { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8887 { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8889 { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8890 { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8891 { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8892 { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8893 { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8894 { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8895 { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8901 { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8902 { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8903 { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8904 { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8905 { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8906 { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8907 { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8908 { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8910 { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8911 { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8912 { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8913 { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8914 { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8916 { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8917 { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8922 { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8925 { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8926 { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8928 { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8929 { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8930 { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8932 { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8934 { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8939 { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8940 { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8941 { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8942 { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8946 { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8947 { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8948 { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8949 { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8950 { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8951 { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8952 { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8953 { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8955 { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8956 { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8957 { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8958 { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8959 { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8960 { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8961 { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8962 { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8964 { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8965 { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8966 { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8967 { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8968 { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8969 { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8970 { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8971 { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8973 { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8974 { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8978 { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8979 { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8980 { PREFIX_TABLE (PREFIX_VEX_0F3847) },
9000 { PREFIX_TABLE (PREFIX_VEX_0F3858) },
9001 { PREFIX_TABLE (PREFIX_VEX_0F3859) },
9002 { PREFIX_TABLE (PREFIX_VEX_0F385A) },
9036 { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9037 { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9058 { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9060 { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9063 { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9064 { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9065 { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9066 { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9069 { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9070 { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9072 { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9073 { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9074 { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9075 { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9076 { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9077 { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9078 { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9079 { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9087 { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9088 { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9090 { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9091 { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9092 { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9093 { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9094 { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9095 { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9096 { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9097 { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9105 { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9106 { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9108 { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9109 { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9110 { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9111 { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9112 { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9113 { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9114 { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9115 { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9147 { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9148 { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9149 { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9150 { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9151 { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9173 { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9174 { REG_TABLE (REG_VEX_0F38F3) },
9176 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9177 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9178 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9192 { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9193 { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9194 { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9196 { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9197 { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9198 { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9201 { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9202 { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9203 { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9204 { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9205 { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9206 { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9207 { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9208 { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9214 { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9215 { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9216 { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9217 { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9219 { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9220 { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9224 { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9228 { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9229 { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9230 { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9246 { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9247 { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9248 { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9249 { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9255 { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9256 { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9264 { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9265 { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9266 { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9268 { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9270 { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9273 { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9274 { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9275 { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9276 { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9277 { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9295 { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9296 { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9297 { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9298 { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9300 { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9301 { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9302 { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9303 { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9309 { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9310 { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9311 { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9312 { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9313 { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9314 { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9315 { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9316 { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9327 { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9328 { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9329 { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9330 { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9331 { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9332 { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9333 { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9334 { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9442 { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9462 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9482 #define NEED_OPCODE_TABLE
9483 #include "i386-dis-evex.h"
9484 #undef NEED_OPCODE_TABLE
9485 static const struct dis386 vex_len_table[][2] = {
9486 /* VEX_LEN_0F10_P_1 */
9488 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9489 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9492 /* VEX_LEN_0F10_P_3 */
9494 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9495 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9498 /* VEX_LEN_0F11_P_1 */
9500 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9501 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9504 /* VEX_LEN_0F11_P_3 */
9506 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9507 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9510 /* VEX_LEN_0F12_P_0_M_0 */
9512 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9515 /* VEX_LEN_0F12_P_0_M_1 */
9517 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9520 /* VEX_LEN_0F12_P_2 */
9522 { VEX_W_TABLE (VEX_W_0F12_P_2) },
9525 /* VEX_LEN_0F13_M_0 */
9527 { VEX_W_TABLE (VEX_W_0F13_M_0) },
9530 /* VEX_LEN_0F16_P_0_M_0 */
9532 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9535 /* VEX_LEN_0F16_P_0_M_1 */
9537 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9540 /* VEX_LEN_0F16_P_2 */
9542 { VEX_W_TABLE (VEX_W_0F16_P_2) },
9545 /* VEX_LEN_0F17_M_0 */
9547 { VEX_W_TABLE (VEX_W_0F17_M_0) },
9550 /* VEX_LEN_0F2A_P_1 */
9552 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } },
9553 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } },
9556 /* VEX_LEN_0F2A_P_3 */
9558 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } },
9559 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } },
9562 /* VEX_LEN_0F2C_P_1 */
9564 { "vcvttss2siY", { Gv, EXdScalar } },
9565 { "vcvttss2siY", { Gv, EXdScalar } },
9568 /* VEX_LEN_0F2C_P_3 */
9570 { "vcvttsd2siY", { Gv, EXqScalar } },
9571 { "vcvttsd2siY", { Gv, EXqScalar } },
9574 /* VEX_LEN_0F2D_P_1 */
9576 { "vcvtss2siY", { Gv, EXdScalar } },
9577 { "vcvtss2siY", { Gv, EXdScalar } },
9580 /* VEX_LEN_0F2D_P_3 */
9582 { "vcvtsd2siY", { Gv, EXqScalar } },
9583 { "vcvtsd2siY", { Gv, EXqScalar } },
9586 /* VEX_LEN_0F2E_P_0 */
9588 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9589 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9592 /* VEX_LEN_0F2E_P_2 */
9594 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9595 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9598 /* VEX_LEN_0F2F_P_0 */
9600 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9601 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9604 /* VEX_LEN_0F2F_P_2 */
9606 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9607 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9610 /* VEX_LEN_0F41_P_0 */
9613 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9615 /* VEX_LEN_0F41_P_2 */
9618 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9620 /* VEX_LEN_0F42_P_0 */
9623 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9625 /* VEX_LEN_0F42_P_2 */
9628 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9630 /* VEX_LEN_0F44_P_0 */
9632 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9634 /* VEX_LEN_0F44_P_2 */
9636 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9638 /* VEX_LEN_0F45_P_0 */
9641 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9643 /* VEX_LEN_0F45_P_2 */
9646 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9648 /* VEX_LEN_0F46_P_0 */
9651 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9653 /* VEX_LEN_0F46_P_2 */
9656 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9658 /* VEX_LEN_0F47_P_0 */
9661 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9663 /* VEX_LEN_0F47_P_2 */
9666 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9668 /* VEX_LEN_0F4A_P_0 */
9671 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9673 /* VEX_LEN_0F4A_P_2 */
9676 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9678 /* VEX_LEN_0F4B_P_0 */
9681 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9683 /* VEX_LEN_0F4B_P_2 */
9686 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9689 /* VEX_LEN_0F51_P_1 */
9691 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9692 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9695 /* VEX_LEN_0F51_P_3 */
9697 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9698 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9701 /* VEX_LEN_0F52_P_1 */
9703 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9704 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9707 /* VEX_LEN_0F53_P_1 */
9709 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9710 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9713 /* VEX_LEN_0F58_P_1 */
9715 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9716 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9719 /* VEX_LEN_0F58_P_3 */
9721 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9722 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9725 /* VEX_LEN_0F59_P_1 */
9727 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9728 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9731 /* VEX_LEN_0F59_P_3 */
9733 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9734 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9737 /* VEX_LEN_0F5A_P_1 */
9739 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9740 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9743 /* VEX_LEN_0F5A_P_3 */
9745 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9746 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9749 /* VEX_LEN_0F5C_P_1 */
9751 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9752 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9755 /* VEX_LEN_0F5C_P_3 */
9757 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9758 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9761 /* VEX_LEN_0F5D_P_1 */
9763 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9764 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9767 /* VEX_LEN_0F5D_P_3 */
9769 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9770 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9773 /* VEX_LEN_0F5E_P_1 */
9775 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9776 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9779 /* VEX_LEN_0F5E_P_3 */
9781 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9782 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9785 /* VEX_LEN_0F5F_P_1 */
9787 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9788 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9791 /* VEX_LEN_0F5F_P_3 */
9793 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9794 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9797 /* VEX_LEN_0F6E_P_2 */
9799 { "vmovK", { XMScalar, Edq } },
9800 { "vmovK", { XMScalar, Edq } },
9803 /* VEX_LEN_0F7E_P_1 */
9805 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9806 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9809 /* VEX_LEN_0F7E_P_2 */
9811 { "vmovK", { Edq, XMScalar } },
9812 { "vmovK", { Edq, XMScalar } },
9815 /* VEX_LEN_0F90_P_0 */
9817 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9820 /* VEX_LEN_0F90_P_2 */
9822 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9825 /* VEX_LEN_0F91_P_0 */
9827 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9830 /* VEX_LEN_0F91_P_2 */
9832 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9835 /* VEX_LEN_0F92_P_0 */
9837 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9840 /* VEX_LEN_0F92_P_2 */
9842 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9845 /* VEX_LEN_0F92_P_3 */
9847 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9850 /* VEX_LEN_0F93_P_0 */
9852 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9855 /* VEX_LEN_0F93_P_2 */
9857 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9860 /* VEX_LEN_0F93_P_3 */
9862 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9865 /* VEX_LEN_0F98_P_0 */
9867 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9870 /* VEX_LEN_0F98_P_2 */
9872 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9875 /* VEX_LEN_0F99_P_0 */
9877 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9880 /* VEX_LEN_0F99_P_2 */
9882 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9885 /* VEX_LEN_0FAE_R_2_M_0 */
9887 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9890 /* VEX_LEN_0FAE_R_3_M_0 */
9892 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9895 /* VEX_LEN_0FC2_P_1 */
9897 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9898 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9901 /* VEX_LEN_0FC2_P_3 */
9903 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9904 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9907 /* VEX_LEN_0FC4_P_2 */
9909 { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9912 /* VEX_LEN_0FC5_P_2 */
9914 { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9917 /* VEX_LEN_0FD6_P_2 */
9919 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9920 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9923 /* VEX_LEN_0FF7_P_2 */
9925 { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9928 /* VEX_LEN_0F3816_P_2 */
9931 { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9934 /* VEX_LEN_0F3819_P_2 */
9937 { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9940 /* VEX_LEN_0F381A_P_2_M_0 */
9943 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9946 /* VEX_LEN_0F3836_P_2 */
9949 { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9952 /* VEX_LEN_0F3841_P_2 */
9954 { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9957 /* VEX_LEN_0F385A_P_2_M_0 */
9960 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9963 /* VEX_LEN_0F38DB_P_2 */
9965 { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9968 /* VEX_LEN_0F38DC_P_2 */
9970 { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9973 /* VEX_LEN_0F38DD_P_2 */
9975 { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9978 /* VEX_LEN_0F38DE_P_2 */
9980 { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9983 /* VEX_LEN_0F38DF_P_2 */
9985 { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9988 /* VEX_LEN_0F38F2_P_0 */
9990 { "andnS", { Gdq, VexGdq, Edq } },
9993 /* VEX_LEN_0F38F3_R_1_P_0 */
9995 { "blsrS", { VexGdq, Edq } },
9998 /* VEX_LEN_0F38F3_R_2_P_0 */
10000 { "blsmskS", { VexGdq, Edq } },
10003 /* VEX_LEN_0F38F3_R_3_P_0 */
10005 { "blsiS", { VexGdq, Edq } },
10008 /* VEX_LEN_0F38F5_P_0 */
10010 { "bzhiS", { Gdq, Edq, VexGdq } },
10013 /* VEX_LEN_0F38F5_P_1 */
10015 { "pextS", { Gdq, VexGdq, Edq } },
10018 /* VEX_LEN_0F38F5_P_3 */
10020 { "pdepS", { Gdq, VexGdq, Edq } },
10023 /* VEX_LEN_0F38F6_P_3 */
10025 { "mulxS", { Gdq, VexGdq, Edq } },
10028 /* VEX_LEN_0F38F7_P_0 */
10030 { "bextrS", { Gdq, Edq, VexGdq } },
10033 /* VEX_LEN_0F38F7_P_1 */
10035 { "sarxS", { Gdq, Edq, VexGdq } },
10038 /* VEX_LEN_0F38F7_P_2 */
10040 { "shlxS", { Gdq, Edq, VexGdq } },
10043 /* VEX_LEN_0F38F7_P_3 */
10045 { "shrxS", { Gdq, Edq, VexGdq } },
10048 /* VEX_LEN_0F3A00_P_2 */
10051 { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10054 /* VEX_LEN_0F3A01_P_2 */
10057 { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10060 /* VEX_LEN_0F3A06_P_2 */
10063 { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10066 /* VEX_LEN_0F3A0A_P_2 */
10068 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10069 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10072 /* VEX_LEN_0F3A0B_P_2 */
10074 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10075 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10078 /* VEX_LEN_0F3A14_P_2 */
10080 { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10083 /* VEX_LEN_0F3A15_P_2 */
10085 { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10088 /* VEX_LEN_0F3A16_P_2 */
10090 { "vpextrK", { Edq, XM, Ib } },
10093 /* VEX_LEN_0F3A17_P_2 */
10095 { "vextractps", { Edqd, XM, Ib } },
10098 /* VEX_LEN_0F3A18_P_2 */
10101 { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10104 /* VEX_LEN_0F3A19_P_2 */
10107 { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10110 /* VEX_LEN_0F3A20_P_2 */
10112 { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10115 /* VEX_LEN_0F3A21_P_2 */
10117 { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10120 /* VEX_LEN_0F3A22_P_2 */
10122 { "vpinsrK", { XM, Vex128, Edq, Ib } },
10125 /* VEX_LEN_0F3A30_P_2 */
10127 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10130 /* VEX_LEN_0F3A31_P_2 */
10132 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10135 /* VEX_LEN_0F3A32_P_2 */
10137 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10140 /* VEX_LEN_0F3A33_P_2 */
10142 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10145 /* VEX_LEN_0F3A38_P_2 */
10148 { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10151 /* VEX_LEN_0F3A39_P_2 */
10154 { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10157 /* VEX_LEN_0F3A41_P_2 */
10159 { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10162 /* VEX_LEN_0F3A44_P_2 */
10164 { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10167 /* VEX_LEN_0F3A46_P_2 */
10170 { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10173 /* VEX_LEN_0F3A60_P_2 */
10175 { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
10178 /* VEX_LEN_0F3A61_P_2 */
10180 { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
10183 /* VEX_LEN_0F3A62_P_2 */
10185 { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10188 /* VEX_LEN_0F3A63_P_2 */
10190 { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10193 /* VEX_LEN_0F3A6A_P_2 */
10195 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10198 /* VEX_LEN_0F3A6B_P_2 */
10200 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10203 /* VEX_LEN_0F3A6E_P_2 */
10205 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10208 /* VEX_LEN_0F3A6F_P_2 */
10210 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10213 /* VEX_LEN_0F3A7A_P_2 */
10215 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10218 /* VEX_LEN_0F3A7B_P_2 */
10220 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10223 /* VEX_LEN_0F3A7E_P_2 */
10225 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10228 /* VEX_LEN_0F3A7F_P_2 */
10230 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10233 /* VEX_LEN_0F3ADF_P_2 */
10235 { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10238 /* VEX_LEN_0F3AF0_P_3 */
10240 { "rorxS", { Gdq, Edq, Ib } },
10243 /* VEX_LEN_0FXOP_08_CC */
10245 { "vpcomb", { XM, Vex128, EXx, Ib } },
10248 /* VEX_LEN_0FXOP_08_CD */
10250 { "vpcomw", { XM, Vex128, EXx, Ib } },
10253 /* VEX_LEN_0FXOP_08_CE */
10255 { "vpcomd", { XM, Vex128, EXx, Ib } },
10258 /* VEX_LEN_0FXOP_08_CF */
10260 { "vpcomq", { XM, Vex128, EXx, Ib } },
10263 /* VEX_LEN_0FXOP_08_EC */
10265 { "vpcomub", { XM, Vex128, EXx, Ib } },
10268 /* VEX_LEN_0FXOP_08_ED */
10270 { "vpcomuw", { XM, Vex128, EXx, Ib } },
10273 /* VEX_LEN_0FXOP_08_EE */
10275 { "vpcomud", { XM, Vex128, EXx, Ib } },
10278 /* VEX_LEN_0FXOP_08_EF */
10280 { "vpcomuq", { XM, Vex128, EXx, Ib } },
10283 /* VEX_LEN_0FXOP_09_80 */
10285 { "vfrczps", { XM, EXxmm } },
10286 { "vfrczps", { XM, EXymmq } },
10289 /* VEX_LEN_0FXOP_09_81 */
10291 { "vfrczpd", { XM, EXxmm } },
10292 { "vfrczpd", { XM, EXymmq } },
10296 static const struct dis386 vex_w_table[][2] = {
10298 /* VEX_W_0F10_P_0 */
10299 { "vmovups", { XM, EXx } },
10302 /* VEX_W_0F10_P_1 */
10303 { "vmovss", { XMVexScalar, VexScalar, EXdScalar } },
10306 /* VEX_W_0F10_P_2 */
10307 { "vmovupd", { XM, EXx } },
10310 /* VEX_W_0F10_P_3 */
10311 { "vmovsd", { XMVexScalar, VexScalar, EXqScalar } },
10314 /* VEX_W_0F11_P_0 */
10315 { "vmovups", { EXxS, XM } },
10318 /* VEX_W_0F11_P_1 */
10319 { "vmovss", { EXdVexScalarS, VexScalar, XMScalar } },
10322 /* VEX_W_0F11_P_2 */
10323 { "vmovupd", { EXxS, XM } },
10326 /* VEX_W_0F11_P_3 */
10327 { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar } },
10330 /* VEX_W_0F12_P_0_M_0 */
10331 { "vmovlps", { XM, Vex128, EXq } },
10334 /* VEX_W_0F12_P_0_M_1 */
10335 { "vmovhlps", { XM, Vex128, EXq } },
10338 /* VEX_W_0F12_P_1 */
10339 { "vmovsldup", { XM, EXx } },
10342 /* VEX_W_0F12_P_2 */
10343 { "vmovlpd", { XM, Vex128, EXq } },
10346 /* VEX_W_0F12_P_3 */
10347 { "vmovddup", { XM, EXymmq } },
10350 /* VEX_W_0F13_M_0 */
10351 { "vmovlpX", { EXq, XM } },
10355 { "vunpcklpX", { XM, Vex, EXx } },
10359 { "vunpckhpX", { XM, Vex, EXx } },
10362 /* VEX_W_0F16_P_0_M_0 */
10363 { "vmovhps", { XM, Vex128, EXq } },
10366 /* VEX_W_0F16_P_0_M_1 */
10367 { "vmovlhps", { XM, Vex128, EXq } },
10370 /* VEX_W_0F16_P_1 */
10371 { "vmovshdup", { XM, EXx } },
10374 /* VEX_W_0F16_P_2 */
10375 { "vmovhpd", { XM, Vex128, EXq } },
10378 /* VEX_W_0F17_M_0 */
10379 { "vmovhpX", { EXq, XM } },
10383 { "vmovapX", { XM, EXx } },
10387 { "vmovapX", { EXxS, XM } },
10390 /* VEX_W_0F2B_M_0 */
10391 { "vmovntpX", { Mx, XM } },
10394 /* VEX_W_0F2E_P_0 */
10395 { "vucomiss", { XMScalar, EXdScalar } },
10398 /* VEX_W_0F2E_P_2 */
10399 { "vucomisd", { XMScalar, EXqScalar } },
10402 /* VEX_W_0F2F_P_0 */
10403 { "vcomiss", { XMScalar, EXdScalar } },
10406 /* VEX_W_0F2F_P_2 */
10407 { "vcomisd", { XMScalar, EXqScalar } },
10410 /* VEX_W_0F41_P_0_LEN_1 */
10411 { "kandw", { MaskG, MaskVex, MaskR } },
10412 { "kandq", { MaskG, MaskVex, MaskR } },
10415 /* VEX_W_0F41_P_2_LEN_1 */
10416 { "kandb", { MaskG, MaskVex, MaskR } },
10417 { "kandd", { MaskG, MaskVex, MaskR } },
10420 /* VEX_W_0F42_P_0_LEN_1 */
10421 { "kandnw", { MaskG, MaskVex, MaskR } },
10422 { "kandnq", { MaskG, MaskVex, MaskR } },
10425 /* VEX_W_0F42_P_2_LEN_1 */
10426 { "kandnb", { MaskG, MaskVex, MaskR } },
10427 { "kandnd", { MaskG, MaskVex, MaskR } },
10430 /* VEX_W_0F44_P_0_LEN_0 */
10431 { "knotw", { MaskG, MaskR } },
10432 { "knotq", { MaskG, MaskR } },
10435 /* VEX_W_0F44_P_2_LEN_0 */
10436 { "knotb", { MaskG, MaskR } },
10437 { "knotd", { MaskG, MaskR } },
10440 /* VEX_W_0F45_P_0_LEN_1 */
10441 { "korw", { MaskG, MaskVex, MaskR } },
10442 { "korq", { MaskG, MaskVex, MaskR } },
10445 /* VEX_W_0F45_P_2_LEN_1 */
10446 { "korb", { MaskG, MaskVex, MaskR } },
10447 { "kord", { MaskG, MaskVex, MaskR } },
10450 /* VEX_W_0F46_P_0_LEN_1 */
10451 { "kxnorw", { MaskG, MaskVex, MaskR } },
10452 { "kxnorq", { MaskG, MaskVex, MaskR } },
10455 /* VEX_W_0F46_P_2_LEN_1 */
10456 { "kxnorb", { MaskG, MaskVex, MaskR } },
10457 { "kxnord", { MaskG, MaskVex, MaskR } },
10460 /* VEX_W_0F47_P_0_LEN_1 */
10461 { "kxorw", { MaskG, MaskVex, MaskR } },
10462 { "kxorq", { MaskG, MaskVex, MaskR } },
10465 /* VEX_W_0F47_P_2_LEN_1 */
10466 { "kxorb", { MaskG, MaskVex, MaskR } },
10467 { "kxord", { MaskG, MaskVex, MaskR } },
10470 /* VEX_W_0F4A_P_0_LEN_1 */
10471 { "kaddw", { MaskG, MaskVex, MaskR } },
10472 { "kaddq", { MaskG, MaskVex, MaskR } },
10475 /* VEX_W_0F4A_P_2_LEN_1 */
10476 { "kaddb", { MaskG, MaskVex, MaskR } },
10477 { "kaddd", { MaskG, MaskVex, MaskR } },
10480 /* VEX_W_0F4B_P_0_LEN_1 */
10481 { "kunpckwd", { MaskG, MaskVex, MaskR } },
10482 { "kunpckdq", { MaskG, MaskVex, MaskR } },
10485 /* VEX_W_0F4B_P_2_LEN_1 */
10486 { "kunpckbw", { MaskG, MaskVex, MaskR } },
10489 /* VEX_W_0F50_M_0 */
10490 { "vmovmskpX", { Gdq, XS } },
10493 /* VEX_W_0F51_P_0 */
10494 { "vsqrtps", { XM, EXx } },
10497 /* VEX_W_0F51_P_1 */
10498 { "vsqrtss", { XMScalar, VexScalar, EXdScalar } },
10501 /* VEX_W_0F51_P_2 */
10502 { "vsqrtpd", { XM, EXx } },
10505 /* VEX_W_0F51_P_3 */
10506 { "vsqrtsd", { XMScalar, VexScalar, EXqScalar } },
10509 /* VEX_W_0F52_P_0 */
10510 { "vrsqrtps", { XM, EXx } },
10513 /* VEX_W_0F52_P_1 */
10514 { "vrsqrtss", { XMScalar, VexScalar, EXdScalar } },
10517 /* VEX_W_0F53_P_0 */
10518 { "vrcpps", { XM, EXx } },
10521 /* VEX_W_0F53_P_1 */
10522 { "vrcpss", { XMScalar, VexScalar, EXdScalar } },
10525 /* VEX_W_0F58_P_0 */
10526 { "vaddps", { XM, Vex, EXx } },
10529 /* VEX_W_0F58_P_1 */
10530 { "vaddss", { XMScalar, VexScalar, EXdScalar } },
10533 /* VEX_W_0F58_P_2 */
10534 { "vaddpd", { XM, Vex, EXx } },
10537 /* VEX_W_0F58_P_3 */
10538 { "vaddsd", { XMScalar, VexScalar, EXqScalar } },
10541 /* VEX_W_0F59_P_0 */
10542 { "vmulps", { XM, Vex, EXx } },
10545 /* VEX_W_0F59_P_1 */
10546 { "vmulss", { XMScalar, VexScalar, EXdScalar } },
10549 /* VEX_W_0F59_P_2 */
10550 { "vmulpd", { XM, Vex, EXx } },
10553 /* VEX_W_0F59_P_3 */
10554 { "vmulsd", { XMScalar, VexScalar, EXqScalar } },
10557 /* VEX_W_0F5A_P_0 */
10558 { "vcvtps2pd", { XM, EXxmmq } },
10561 /* VEX_W_0F5A_P_1 */
10562 { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar } },
10565 /* VEX_W_0F5A_P_3 */
10566 { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar } },
10569 /* VEX_W_0F5B_P_0 */
10570 { "vcvtdq2ps", { XM, EXx } },
10573 /* VEX_W_0F5B_P_1 */
10574 { "vcvttps2dq", { XM, EXx } },
10577 /* VEX_W_0F5B_P_2 */
10578 { "vcvtps2dq", { XM, EXx } },
10581 /* VEX_W_0F5C_P_0 */
10582 { "vsubps", { XM, Vex, EXx } },
10585 /* VEX_W_0F5C_P_1 */
10586 { "vsubss", { XMScalar, VexScalar, EXdScalar } },
10589 /* VEX_W_0F5C_P_2 */
10590 { "vsubpd", { XM, Vex, EXx } },
10593 /* VEX_W_0F5C_P_3 */
10594 { "vsubsd", { XMScalar, VexScalar, EXqScalar } },
10597 /* VEX_W_0F5D_P_0 */
10598 { "vminps", { XM, Vex, EXx } },
10601 /* VEX_W_0F5D_P_1 */
10602 { "vminss", { XMScalar, VexScalar, EXdScalar } },
10605 /* VEX_W_0F5D_P_2 */
10606 { "vminpd", { XM, Vex, EXx } },
10609 /* VEX_W_0F5D_P_3 */
10610 { "vminsd", { XMScalar, VexScalar, EXqScalar } },
10613 /* VEX_W_0F5E_P_0 */
10614 { "vdivps", { XM, Vex, EXx } },
10617 /* VEX_W_0F5E_P_1 */
10618 { "vdivss", { XMScalar, VexScalar, EXdScalar } },
10621 /* VEX_W_0F5E_P_2 */
10622 { "vdivpd", { XM, Vex, EXx } },
10625 /* VEX_W_0F5E_P_3 */
10626 { "vdivsd", { XMScalar, VexScalar, EXqScalar } },
10629 /* VEX_W_0F5F_P_0 */
10630 { "vmaxps", { XM, Vex, EXx } },
10633 /* VEX_W_0F5F_P_1 */
10634 { "vmaxss", { XMScalar, VexScalar, EXdScalar } },
10637 /* VEX_W_0F5F_P_2 */
10638 { "vmaxpd", { XM, Vex, EXx } },
10641 /* VEX_W_0F5F_P_3 */
10642 { "vmaxsd", { XMScalar, VexScalar, EXqScalar } },
10645 /* VEX_W_0F60_P_2 */
10646 { "vpunpcklbw", { XM, Vex, EXx } },
10649 /* VEX_W_0F61_P_2 */
10650 { "vpunpcklwd", { XM, Vex, EXx } },
10653 /* VEX_W_0F62_P_2 */
10654 { "vpunpckldq", { XM, Vex, EXx } },
10657 /* VEX_W_0F63_P_2 */
10658 { "vpacksswb", { XM, Vex, EXx } },
10661 /* VEX_W_0F64_P_2 */
10662 { "vpcmpgtb", { XM, Vex, EXx } },
10665 /* VEX_W_0F65_P_2 */
10666 { "vpcmpgtw", { XM, Vex, EXx } },
10669 /* VEX_W_0F66_P_2 */
10670 { "vpcmpgtd", { XM, Vex, EXx } },
10673 /* VEX_W_0F67_P_2 */
10674 { "vpackuswb", { XM, Vex, EXx } },
10677 /* VEX_W_0F68_P_2 */
10678 { "vpunpckhbw", { XM, Vex, EXx } },
10681 /* VEX_W_0F69_P_2 */
10682 { "vpunpckhwd", { XM, Vex, EXx } },
10685 /* VEX_W_0F6A_P_2 */
10686 { "vpunpckhdq", { XM, Vex, EXx } },
10689 /* VEX_W_0F6B_P_2 */
10690 { "vpackssdw", { XM, Vex, EXx } },
10693 /* VEX_W_0F6C_P_2 */
10694 { "vpunpcklqdq", { XM, Vex, EXx } },
10697 /* VEX_W_0F6D_P_2 */
10698 { "vpunpckhqdq", { XM, Vex, EXx } },
10701 /* VEX_W_0F6F_P_1 */
10702 { "vmovdqu", { XM, EXx } },
10705 /* VEX_W_0F6F_P_2 */
10706 { "vmovdqa", { XM, EXx } },
10709 /* VEX_W_0F70_P_1 */
10710 { "vpshufhw", { XM, EXx, Ib } },
10713 /* VEX_W_0F70_P_2 */
10714 { "vpshufd", { XM, EXx, Ib } },
10717 /* VEX_W_0F70_P_3 */
10718 { "vpshuflw", { XM, EXx, Ib } },
10721 /* VEX_W_0F71_R_2_P_2 */
10722 { "vpsrlw", { Vex, XS, Ib } },
10725 /* VEX_W_0F71_R_4_P_2 */
10726 { "vpsraw", { Vex, XS, Ib } },
10729 /* VEX_W_0F71_R_6_P_2 */
10730 { "vpsllw", { Vex, XS, Ib } },
10733 /* VEX_W_0F72_R_2_P_2 */
10734 { "vpsrld", { Vex, XS, Ib } },
10737 /* VEX_W_0F72_R_4_P_2 */
10738 { "vpsrad", { Vex, XS, Ib } },
10741 /* VEX_W_0F72_R_6_P_2 */
10742 { "vpslld", { Vex, XS, Ib } },
10745 /* VEX_W_0F73_R_2_P_2 */
10746 { "vpsrlq", { Vex, XS, Ib } },
10749 /* VEX_W_0F73_R_3_P_2 */
10750 { "vpsrldq", { Vex, XS, Ib } },
10753 /* VEX_W_0F73_R_6_P_2 */
10754 { "vpsllq", { Vex, XS, Ib } },
10757 /* VEX_W_0F73_R_7_P_2 */
10758 { "vpslldq", { Vex, XS, Ib } },
10761 /* VEX_W_0F74_P_2 */
10762 { "vpcmpeqb", { XM, Vex, EXx } },
10765 /* VEX_W_0F75_P_2 */
10766 { "vpcmpeqw", { XM, Vex, EXx } },
10769 /* VEX_W_0F76_P_2 */
10770 { "vpcmpeqd", { XM, Vex, EXx } },
10773 /* VEX_W_0F77_P_0 */
10777 /* VEX_W_0F7C_P_2 */
10778 { "vhaddpd", { XM, Vex, EXx } },
10781 /* VEX_W_0F7C_P_3 */
10782 { "vhaddps", { XM, Vex, EXx } },
10785 /* VEX_W_0F7D_P_2 */
10786 { "vhsubpd", { XM, Vex, EXx } },
10789 /* VEX_W_0F7D_P_3 */
10790 { "vhsubps", { XM, Vex, EXx } },
10793 /* VEX_W_0F7E_P_1 */
10794 { "vmovq", { XMScalar, EXqScalar } },
10797 /* VEX_W_0F7F_P_1 */
10798 { "vmovdqu", { EXxS, XM } },
10801 /* VEX_W_0F7F_P_2 */
10802 { "vmovdqa", { EXxS, XM } },
10805 /* VEX_W_0F90_P_0_LEN_0 */
10806 { "kmovw", { MaskG, MaskE } },
10807 { "kmovq", { MaskG, MaskE } },
10810 /* VEX_W_0F90_P_2_LEN_0 */
10811 { "kmovb", { MaskG, MaskBDE } },
10812 { "kmovd", { MaskG, MaskBDE } },
10815 /* VEX_W_0F91_P_0_LEN_0 */
10816 { "kmovw", { Ew, MaskG } },
10817 { "kmovq", { Eq, MaskG } },
10820 /* VEX_W_0F91_P_2_LEN_0 */
10821 { "kmovb", { Eb, MaskG } },
10822 { "kmovd", { Ed, MaskG } },
10825 /* VEX_W_0F92_P_0_LEN_0 */
10826 { "kmovw", { MaskG, Rdq } },
10829 /* VEX_W_0F92_P_2_LEN_0 */
10830 { "kmovb", { MaskG, Rdq } },
10833 /* VEX_W_0F92_P_3_LEN_0 */
10834 { "kmovd", { MaskG, Rdq } },
10835 { "kmovq", { MaskG, Rdq } },
10838 /* VEX_W_0F93_P_0_LEN_0 */
10839 { "kmovw", { Gdq, MaskR } },
10842 /* VEX_W_0F93_P_2_LEN_0 */
10843 { "kmovb", { Gdq, MaskR } },
10846 /* VEX_W_0F93_P_3_LEN_0 */
10847 { "kmovd", { Gdq, MaskR } },
10848 { "kmovq", { Gdq, MaskR } },
10851 /* VEX_W_0F98_P_0_LEN_0 */
10852 { "kortestw", { MaskG, MaskR } },
10853 { "kortestq", { MaskG, MaskR } },
10856 /* VEX_W_0F98_P_2_LEN_0 */
10857 { "kortestb", { MaskG, MaskR } },
10858 { "kortestd", { MaskG, MaskR } },
10861 /* VEX_W_0F99_P_0_LEN_0 */
10862 { "ktestw", { MaskG, MaskR } },
10863 { "ktestq", { MaskG, MaskR } },
10866 /* VEX_W_0F99_P_2_LEN_0 */
10867 { "ktestb", { MaskG, MaskR } },
10868 { "ktestd", { MaskG, MaskR } },
10871 /* VEX_W_0FAE_R_2_M_0 */
10872 { "vldmxcsr", { Md } },
10875 /* VEX_W_0FAE_R_3_M_0 */
10876 { "vstmxcsr", { Md } },
10879 /* VEX_W_0FC2_P_0 */
10880 { "vcmpps", { XM, Vex, EXx, VCMP } },
10883 /* VEX_W_0FC2_P_1 */
10884 { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP } },
10887 /* VEX_W_0FC2_P_2 */
10888 { "vcmppd", { XM, Vex, EXx, VCMP } },
10891 /* VEX_W_0FC2_P_3 */
10892 { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP } },
10895 /* VEX_W_0FC4_P_2 */
10896 { "vpinsrw", { XM, Vex128, Edqw, Ib } },
10899 /* VEX_W_0FC5_P_2 */
10900 { "vpextrw", { Gdq, XS, Ib } },
10903 /* VEX_W_0FD0_P_2 */
10904 { "vaddsubpd", { XM, Vex, EXx } },
10907 /* VEX_W_0FD0_P_3 */
10908 { "vaddsubps", { XM, Vex, EXx } },
10911 /* VEX_W_0FD1_P_2 */
10912 { "vpsrlw", { XM, Vex, EXxmm } },
10915 /* VEX_W_0FD2_P_2 */
10916 { "vpsrld", { XM, Vex, EXxmm } },
10919 /* VEX_W_0FD3_P_2 */
10920 { "vpsrlq", { XM, Vex, EXxmm } },
10923 /* VEX_W_0FD4_P_2 */
10924 { "vpaddq", { XM, Vex, EXx } },
10927 /* VEX_W_0FD5_P_2 */
10928 { "vpmullw", { XM, Vex, EXx } },
10931 /* VEX_W_0FD6_P_2 */
10932 { "vmovq", { EXqScalarS, XMScalar } },
10935 /* VEX_W_0FD7_P_2_M_1 */
10936 { "vpmovmskb", { Gdq, XS } },
10939 /* VEX_W_0FD8_P_2 */
10940 { "vpsubusb", { XM, Vex, EXx } },
10943 /* VEX_W_0FD9_P_2 */
10944 { "vpsubusw", { XM, Vex, EXx } },
10947 /* VEX_W_0FDA_P_2 */
10948 { "vpminub", { XM, Vex, EXx } },
10951 /* VEX_W_0FDB_P_2 */
10952 { "vpand", { XM, Vex, EXx } },
10955 /* VEX_W_0FDC_P_2 */
10956 { "vpaddusb", { XM, Vex, EXx } },
10959 /* VEX_W_0FDD_P_2 */
10960 { "vpaddusw", { XM, Vex, EXx } },
10963 /* VEX_W_0FDE_P_2 */
10964 { "vpmaxub", { XM, Vex, EXx } },
10967 /* VEX_W_0FDF_P_2 */
10968 { "vpandn", { XM, Vex, EXx } },
10971 /* VEX_W_0FE0_P_2 */
10972 { "vpavgb", { XM, Vex, EXx } },
10975 /* VEX_W_0FE1_P_2 */
10976 { "vpsraw", { XM, Vex, EXxmm } },
10979 /* VEX_W_0FE2_P_2 */
10980 { "vpsrad", { XM, Vex, EXxmm } },
10983 /* VEX_W_0FE3_P_2 */
10984 { "vpavgw", { XM, Vex, EXx } },
10987 /* VEX_W_0FE4_P_2 */
10988 { "vpmulhuw", { XM, Vex, EXx } },
10991 /* VEX_W_0FE5_P_2 */
10992 { "vpmulhw", { XM, Vex, EXx } },
10995 /* VEX_W_0FE6_P_1 */
10996 { "vcvtdq2pd", { XM, EXxmmq } },
10999 /* VEX_W_0FE6_P_2 */
11000 { "vcvttpd2dq%XY", { XMM, EXx } },
11003 /* VEX_W_0FE6_P_3 */
11004 { "vcvtpd2dq%XY", { XMM, EXx } },
11007 /* VEX_W_0FE7_P_2_M_0 */
11008 { "vmovntdq", { Mx, XM } },
11011 /* VEX_W_0FE8_P_2 */
11012 { "vpsubsb", { XM, Vex, EXx } },
11015 /* VEX_W_0FE9_P_2 */
11016 { "vpsubsw", { XM, Vex, EXx } },
11019 /* VEX_W_0FEA_P_2 */
11020 { "vpminsw", { XM, Vex, EXx } },
11023 /* VEX_W_0FEB_P_2 */
11024 { "vpor", { XM, Vex, EXx } },
11027 /* VEX_W_0FEC_P_2 */
11028 { "vpaddsb", { XM, Vex, EXx } },
11031 /* VEX_W_0FED_P_2 */
11032 { "vpaddsw", { XM, Vex, EXx } },
11035 /* VEX_W_0FEE_P_2 */
11036 { "vpmaxsw", { XM, Vex, EXx } },
11039 /* VEX_W_0FEF_P_2 */
11040 { "vpxor", { XM, Vex, EXx } },
11043 /* VEX_W_0FF0_P_3_M_0 */
11044 { "vlddqu", { XM, M } },
11047 /* VEX_W_0FF1_P_2 */
11048 { "vpsllw", { XM, Vex, EXxmm } },
11051 /* VEX_W_0FF2_P_2 */
11052 { "vpslld", { XM, Vex, EXxmm } },
11055 /* VEX_W_0FF3_P_2 */
11056 { "vpsllq", { XM, Vex, EXxmm } },
11059 /* VEX_W_0FF4_P_2 */
11060 { "vpmuludq", { XM, Vex, EXx } },
11063 /* VEX_W_0FF5_P_2 */
11064 { "vpmaddwd", { XM, Vex, EXx } },
11067 /* VEX_W_0FF6_P_2 */
11068 { "vpsadbw", { XM, Vex, EXx } },
11071 /* VEX_W_0FF7_P_2 */
11072 { "vmaskmovdqu", { XM, XS } },
11075 /* VEX_W_0FF8_P_2 */
11076 { "vpsubb", { XM, Vex, EXx } },
11079 /* VEX_W_0FF9_P_2 */
11080 { "vpsubw", { XM, Vex, EXx } },
11083 /* VEX_W_0FFA_P_2 */
11084 { "vpsubd", { XM, Vex, EXx } },
11087 /* VEX_W_0FFB_P_2 */
11088 { "vpsubq", { XM, Vex, EXx } },
11091 /* VEX_W_0FFC_P_2 */
11092 { "vpaddb", { XM, Vex, EXx } },
11095 /* VEX_W_0FFD_P_2 */
11096 { "vpaddw", { XM, Vex, EXx } },
11099 /* VEX_W_0FFE_P_2 */
11100 { "vpaddd", { XM, Vex, EXx } },
11103 /* VEX_W_0F3800_P_2 */
11104 { "vpshufb", { XM, Vex, EXx } },
11107 /* VEX_W_0F3801_P_2 */
11108 { "vphaddw", { XM, Vex, EXx } },
11111 /* VEX_W_0F3802_P_2 */
11112 { "vphaddd", { XM, Vex, EXx } },
11115 /* VEX_W_0F3803_P_2 */
11116 { "vphaddsw", { XM, Vex, EXx } },
11119 /* VEX_W_0F3804_P_2 */
11120 { "vpmaddubsw", { XM, Vex, EXx } },
11123 /* VEX_W_0F3805_P_2 */
11124 { "vphsubw", { XM, Vex, EXx } },
11127 /* VEX_W_0F3806_P_2 */
11128 { "vphsubd", { XM, Vex, EXx } },
11131 /* VEX_W_0F3807_P_2 */
11132 { "vphsubsw", { XM, Vex, EXx } },
11135 /* VEX_W_0F3808_P_2 */
11136 { "vpsignb", { XM, Vex, EXx } },
11139 /* VEX_W_0F3809_P_2 */
11140 { "vpsignw", { XM, Vex, EXx } },
11143 /* VEX_W_0F380A_P_2 */
11144 { "vpsignd", { XM, Vex, EXx } },
11147 /* VEX_W_0F380B_P_2 */
11148 { "vpmulhrsw", { XM, Vex, EXx } },
11151 /* VEX_W_0F380C_P_2 */
11152 { "vpermilps", { XM, Vex, EXx } },
11155 /* VEX_W_0F380D_P_2 */
11156 { "vpermilpd", { XM, Vex, EXx } },
11159 /* VEX_W_0F380E_P_2 */
11160 { "vtestps", { XM, EXx } },
11163 /* VEX_W_0F380F_P_2 */
11164 { "vtestpd", { XM, EXx } },
11167 /* VEX_W_0F3816_P_2 */
11168 { "vpermps", { XM, Vex, EXx } },
11171 /* VEX_W_0F3817_P_2 */
11172 { "vptest", { XM, EXx } },
11175 /* VEX_W_0F3818_P_2 */
11176 { "vbroadcastss", { XM, EXxmm_md } },
11179 /* VEX_W_0F3819_P_2 */
11180 { "vbroadcastsd", { XM, EXxmm_mq } },
11183 /* VEX_W_0F381A_P_2_M_0 */
11184 { "vbroadcastf128", { XM, Mxmm } },
11187 /* VEX_W_0F381C_P_2 */
11188 { "vpabsb", { XM, EXx } },
11191 /* VEX_W_0F381D_P_2 */
11192 { "vpabsw", { XM, EXx } },
11195 /* VEX_W_0F381E_P_2 */
11196 { "vpabsd", { XM, EXx } },
11199 /* VEX_W_0F3820_P_2 */
11200 { "vpmovsxbw", { XM, EXxmmq } },
11203 /* VEX_W_0F3821_P_2 */
11204 { "vpmovsxbd", { XM, EXxmmqd } },
11207 /* VEX_W_0F3822_P_2 */
11208 { "vpmovsxbq", { XM, EXxmmdw } },
11211 /* VEX_W_0F3823_P_2 */
11212 { "vpmovsxwd", { XM, EXxmmq } },
11215 /* VEX_W_0F3824_P_2 */
11216 { "vpmovsxwq", { XM, EXxmmqd } },
11219 /* VEX_W_0F3825_P_2 */
11220 { "vpmovsxdq", { XM, EXxmmq } },
11223 /* VEX_W_0F3828_P_2 */
11224 { "vpmuldq", { XM, Vex, EXx } },
11227 /* VEX_W_0F3829_P_2 */
11228 { "vpcmpeqq", { XM, Vex, EXx } },
11231 /* VEX_W_0F382A_P_2_M_0 */
11232 { "vmovntdqa", { XM, Mx } },
11235 /* VEX_W_0F382B_P_2 */
11236 { "vpackusdw", { XM, Vex, EXx } },
11239 /* VEX_W_0F382C_P_2_M_0 */
11240 { "vmaskmovps", { XM, Vex, Mx } },
11243 /* VEX_W_0F382D_P_2_M_0 */
11244 { "vmaskmovpd", { XM, Vex, Mx } },
11247 /* VEX_W_0F382E_P_2_M_0 */
11248 { "vmaskmovps", { Mx, Vex, XM } },
11251 /* VEX_W_0F382F_P_2_M_0 */
11252 { "vmaskmovpd", { Mx, Vex, XM } },
11255 /* VEX_W_0F3830_P_2 */
11256 { "vpmovzxbw", { XM, EXxmmq } },
11259 /* VEX_W_0F3831_P_2 */
11260 { "vpmovzxbd", { XM, EXxmmqd } },
11263 /* VEX_W_0F3832_P_2 */
11264 { "vpmovzxbq", { XM, EXxmmdw } },
11267 /* VEX_W_0F3833_P_2 */
11268 { "vpmovzxwd", { XM, EXxmmq } },
11271 /* VEX_W_0F3834_P_2 */
11272 { "vpmovzxwq", { XM, EXxmmqd } },
11275 /* VEX_W_0F3835_P_2 */
11276 { "vpmovzxdq", { XM, EXxmmq } },
11279 /* VEX_W_0F3836_P_2 */
11280 { "vpermd", { XM, Vex, EXx } },
11283 /* VEX_W_0F3837_P_2 */
11284 { "vpcmpgtq", { XM, Vex, EXx } },
11287 /* VEX_W_0F3838_P_2 */
11288 { "vpminsb", { XM, Vex, EXx } },
11291 /* VEX_W_0F3839_P_2 */
11292 { "vpminsd", { XM, Vex, EXx } },
11295 /* VEX_W_0F383A_P_2 */
11296 { "vpminuw", { XM, Vex, EXx } },
11299 /* VEX_W_0F383B_P_2 */
11300 { "vpminud", { XM, Vex, EXx } },
11303 /* VEX_W_0F383C_P_2 */
11304 { "vpmaxsb", { XM, Vex, EXx } },
11307 /* VEX_W_0F383D_P_2 */
11308 { "vpmaxsd", { XM, Vex, EXx } },
11311 /* VEX_W_0F383E_P_2 */
11312 { "vpmaxuw", { XM, Vex, EXx } },
11315 /* VEX_W_0F383F_P_2 */
11316 { "vpmaxud", { XM, Vex, EXx } },
11319 /* VEX_W_0F3840_P_2 */
11320 { "vpmulld", { XM, Vex, EXx } },
11323 /* VEX_W_0F3841_P_2 */
11324 { "vphminposuw", { XM, EXx } },
11327 /* VEX_W_0F3846_P_2 */
11328 { "vpsravd", { XM, Vex, EXx } },
11331 /* VEX_W_0F3858_P_2 */
11332 { "vpbroadcastd", { XM, EXxmm_md } },
11335 /* VEX_W_0F3859_P_2 */
11336 { "vpbroadcastq", { XM, EXxmm_mq } },
11339 /* VEX_W_0F385A_P_2_M_0 */
11340 { "vbroadcasti128", { XM, Mxmm } },
11343 /* VEX_W_0F3878_P_2 */
11344 { "vpbroadcastb", { XM, EXxmm_mb } },
11347 /* VEX_W_0F3879_P_2 */
11348 { "vpbroadcastw", { XM, EXxmm_mw } },
11351 /* VEX_W_0F38DB_P_2 */
11352 { "vaesimc", { XM, EXx } },
11355 /* VEX_W_0F38DC_P_2 */
11356 { "vaesenc", { XM, Vex128, EXx } },
11359 /* VEX_W_0F38DD_P_2 */
11360 { "vaesenclast", { XM, Vex128, EXx } },
11363 /* VEX_W_0F38DE_P_2 */
11364 { "vaesdec", { XM, Vex128, EXx } },
11367 /* VEX_W_0F38DF_P_2 */
11368 { "vaesdeclast", { XM, Vex128, EXx } },
11371 /* VEX_W_0F3A00_P_2 */
11373 { "vpermq", { XM, EXx, Ib } },
11376 /* VEX_W_0F3A01_P_2 */
11378 { "vpermpd", { XM, EXx, Ib } },
11381 /* VEX_W_0F3A02_P_2 */
11382 { "vpblendd", { XM, Vex, EXx, Ib } },
11385 /* VEX_W_0F3A04_P_2 */
11386 { "vpermilps", { XM, EXx, Ib } },
11389 /* VEX_W_0F3A05_P_2 */
11390 { "vpermilpd", { XM, EXx, Ib } },
11393 /* VEX_W_0F3A06_P_2 */
11394 { "vperm2f128", { XM, Vex256, EXx, Ib } },
11397 /* VEX_W_0F3A08_P_2 */
11398 { "vroundps", { XM, EXx, Ib } },
11401 /* VEX_W_0F3A09_P_2 */
11402 { "vroundpd", { XM, EXx, Ib } },
11405 /* VEX_W_0F3A0A_P_2 */
11406 { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib } },
11409 /* VEX_W_0F3A0B_P_2 */
11410 { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib } },
11413 /* VEX_W_0F3A0C_P_2 */
11414 { "vblendps", { XM, Vex, EXx, Ib } },
11417 /* VEX_W_0F3A0D_P_2 */
11418 { "vblendpd", { XM, Vex, EXx, Ib } },
11421 /* VEX_W_0F3A0E_P_2 */
11422 { "vpblendw", { XM, Vex, EXx, Ib } },
11425 /* VEX_W_0F3A0F_P_2 */
11426 { "vpalignr", { XM, Vex, EXx, Ib } },
11429 /* VEX_W_0F3A14_P_2 */
11430 { "vpextrb", { Edqb, XM, Ib } },
11433 /* VEX_W_0F3A15_P_2 */
11434 { "vpextrw", { Edqw, XM, Ib } },
11437 /* VEX_W_0F3A18_P_2 */
11438 { "vinsertf128", { XM, Vex256, EXxmm, Ib } },
11441 /* VEX_W_0F3A19_P_2 */
11442 { "vextractf128", { EXxmm, XM, Ib } },
11445 /* VEX_W_0F3A20_P_2 */
11446 { "vpinsrb", { XM, Vex128, Edqb, Ib } },
11449 /* VEX_W_0F3A21_P_2 */
11450 { "vinsertps", { XM, Vex128, EXd, Ib } },
11453 /* VEX_W_0F3A30_P_2_LEN_0 */
11454 { "kshiftrb", { MaskG, MaskR, Ib } },
11455 { "kshiftrw", { MaskG, MaskR, Ib } },
11458 /* VEX_W_0F3A31_P_2_LEN_0 */
11459 { "kshiftrd", { MaskG, MaskR, Ib } },
11460 { "kshiftrq", { MaskG, MaskR, Ib } },
11463 /* VEX_W_0F3A32_P_2_LEN_0 */
11464 { "kshiftlb", { MaskG, MaskR, Ib } },
11465 { "kshiftlw", { MaskG, MaskR, Ib } },
11468 /* VEX_W_0F3A33_P_2_LEN_0 */
11469 { "kshiftld", { MaskG, MaskR, Ib } },
11470 { "kshiftlq", { MaskG, MaskR, Ib } },
11473 /* VEX_W_0F3A38_P_2 */
11474 { "vinserti128", { XM, Vex256, EXxmm, Ib } },
11477 /* VEX_W_0F3A39_P_2 */
11478 { "vextracti128", { EXxmm, XM, Ib } },
11481 /* VEX_W_0F3A40_P_2 */
11482 { "vdpps", { XM, Vex, EXx, Ib } },
11485 /* VEX_W_0F3A41_P_2 */
11486 { "vdppd", { XM, Vex128, EXx, Ib } },
11489 /* VEX_W_0F3A42_P_2 */
11490 { "vmpsadbw", { XM, Vex, EXx, Ib } },
11493 /* VEX_W_0F3A44_P_2 */
11494 { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } },
11497 /* VEX_W_0F3A46_P_2 */
11498 { "vperm2i128", { XM, Vex256, EXx, Ib } },
11501 /* VEX_W_0F3A48_P_2 */
11502 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11503 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11506 /* VEX_W_0F3A49_P_2 */
11507 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11508 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11511 /* VEX_W_0F3A4A_P_2 */
11512 { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
11515 /* VEX_W_0F3A4B_P_2 */
11516 { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
11519 /* VEX_W_0F3A4C_P_2 */
11520 { "vpblendvb", { XM, Vex, EXx, XMVexI4 } },
11523 /* VEX_W_0F3A60_P_2 */
11524 { "vpcmpestrm", { XM, EXx, Ib } },
11527 /* VEX_W_0F3A61_P_2 */
11528 { "vpcmpestri", { XM, EXx, Ib } },
11531 /* VEX_W_0F3A62_P_2 */
11532 { "vpcmpistrm", { XM, EXx, Ib } },
11535 /* VEX_W_0F3A63_P_2 */
11536 { "vpcmpistri", { XM, EXx, Ib } },
11539 /* VEX_W_0F3ADF_P_2 */
11540 { "vaeskeygenassist", { XM, EXx, Ib } },
11542 #define NEED_VEX_W_TABLE
11543 #include "i386-dis-evex.h"
11544 #undef NEED_VEX_W_TABLE
11547 static const struct dis386 mod_table[][2] = {
11550 { "leaS", { Gv, M } },
11555 { RM_TABLE (RM_C6_REG_7) },
11560 { RM_TABLE (RM_C7_REG_7) },
11564 { "Jcall{T|}", { indirEp } },
11568 { "Jjmp{T|}", { indirEp } },
11571 /* MOD_0F01_REG_0 */
11572 { X86_64_TABLE (X86_64_0F01_REG_0) },
11573 { RM_TABLE (RM_0F01_REG_0) },
11576 /* MOD_0F01_REG_1 */
11577 { X86_64_TABLE (X86_64_0F01_REG_1) },
11578 { RM_TABLE (RM_0F01_REG_1) },
11581 /* MOD_0F01_REG_2 */
11582 { X86_64_TABLE (X86_64_0F01_REG_2) },
11583 { RM_TABLE (RM_0F01_REG_2) },
11586 /* MOD_0F01_REG_3 */
11587 { X86_64_TABLE (X86_64_0F01_REG_3) },
11588 { RM_TABLE (RM_0F01_REG_3) },
11591 /* MOD_0F01_REG_7 */
11592 { "invlpg", { Mb } },
11593 { RM_TABLE (RM_0F01_REG_7) },
11596 /* MOD_0F12_PREFIX_0 */
11597 { "movlps", { XM, EXq } },
11598 { "movhlps", { XM, EXq } },
11602 { "movlpX", { EXq, XM } },
11605 /* MOD_0F16_PREFIX_0 */
11606 { "movhps", { XM, EXq } },
11607 { "movlhps", { XM, EXq } },
11611 { "movhpX", { EXq, XM } },
11614 /* MOD_0F18_REG_0 */
11615 { "prefetchnta", { Mb } },
11618 /* MOD_0F18_REG_1 */
11619 { "prefetcht0", { Mb } },
11622 /* MOD_0F18_REG_2 */
11623 { "prefetcht1", { Mb } },
11626 /* MOD_0F18_REG_3 */
11627 { "prefetcht2", { Mb } },
11630 /* MOD_0F18_REG_4 */
11631 { "nop/reserved", { Mb } },
11634 /* MOD_0F18_REG_5 */
11635 { "nop/reserved", { Mb } },
11638 /* MOD_0F18_REG_6 */
11639 { "nop/reserved", { Mb } },
11642 /* MOD_0F18_REG_7 */
11643 { "nop/reserved", { Mb } },
11646 /* MOD_0F1A_PREFIX_0 */
11647 { "bndldx", { Gbnd, Ev_bnd } },
11648 { "nopQ", { Ev } },
11651 /* MOD_0F1B_PREFIX_0 */
11652 { "bndstx", { Ev_bnd, Gbnd } },
11653 { "nopQ", { Ev } },
11656 /* MOD_0F1B_PREFIX_1 */
11657 { "bndmk", { Gbnd, Ev_bnd } },
11658 { "nopQ", { Ev } },
11663 { "movL", { Rd, Td } },
11668 { "movL", { Td, Rd } },
11671 /* MOD_0F2B_PREFIX_0 */
11672 {"movntps", { Mx, XM } },
11675 /* MOD_0F2B_PREFIX_1 */
11676 {"movntss", { Md, XM } },
11679 /* MOD_0F2B_PREFIX_2 */
11680 {"movntpd", { Mx, XM } },
11683 /* MOD_0F2B_PREFIX_3 */
11684 {"movntsd", { Mq, XM } },
11689 { "movmskpX", { Gdq, XS } },
11692 /* MOD_0F71_REG_2 */
11694 { "psrlw", { MS, Ib } },
11697 /* MOD_0F71_REG_4 */
11699 { "psraw", { MS, Ib } },
11702 /* MOD_0F71_REG_6 */
11704 { "psllw", { MS, Ib } },
11707 /* MOD_0F72_REG_2 */
11709 { "psrld", { MS, Ib } },
11712 /* MOD_0F72_REG_4 */
11714 { "psrad", { MS, Ib } },
11717 /* MOD_0F72_REG_6 */
11719 { "pslld", { MS, Ib } },
11722 /* MOD_0F73_REG_2 */
11724 { "psrlq", { MS, Ib } },
11727 /* MOD_0F73_REG_3 */
11729 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11732 /* MOD_0F73_REG_6 */
11734 { "psllq", { MS, Ib } },
11737 /* MOD_0F73_REG_7 */
11739 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11742 /* MOD_0FAE_REG_0 */
11743 { "fxsave", { FXSAVE } },
11744 { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11747 /* MOD_0FAE_REG_1 */
11748 { "fxrstor", { FXSAVE } },
11749 { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11752 /* MOD_0FAE_REG_2 */
11753 { "ldmxcsr", { Md } },
11754 { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11757 /* MOD_0FAE_REG_3 */
11758 { "stmxcsr", { Md } },
11759 { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11762 /* MOD_0FAE_REG_4 */
11763 { "xsave", { FXSAVE } },
11766 /* MOD_0FAE_REG_5 */
11767 { "xrstor", { FXSAVE } },
11768 { RM_TABLE (RM_0FAE_REG_5) },
11771 /* MOD_0FAE_REG_6 */
11772 { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11773 { RM_TABLE (RM_0FAE_REG_6) },
11776 /* MOD_0FAE_REG_7 */
11777 { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11778 { RM_TABLE (RM_0FAE_REG_7) },
11782 { "lssS", { Gv, Mp } },
11786 { "lfsS", { Gv, Mp } },
11790 { "lgsS", { Gv, Mp } },
11793 /* MOD_0FC7_REG_3 */
11794 { "xrstors", { FXSAVE } },
11797 /* MOD_0FC7_REG_4 */
11798 { "xsavec", { FXSAVE } },
11801 /* MOD_0FC7_REG_5 */
11802 { "xsaves", { FXSAVE } },
11805 /* MOD_0FC7_REG_6 */
11806 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
11807 { "rdrand", { Ev } },
11810 /* MOD_0FC7_REG_7 */
11811 { "vmptrst", { Mq } },
11812 { "rdseed", { Ev } },
11817 { "pmovmskb", { Gdq, MS } },
11820 /* MOD_0FE7_PREFIX_2 */
11821 { "movntdq", { Mx, XM } },
11824 /* MOD_0FF0_PREFIX_3 */
11825 { "lddqu", { XM, M } },
11828 /* MOD_0F382A_PREFIX_2 */
11829 { "movntdqa", { XM, Mx } },
11833 { "bound{S|}", { Gv, Ma } },
11834 { EVEX_TABLE (EVEX_0F) },
11838 { "lesS", { Gv, Mp } },
11839 { VEX_C4_TABLE (VEX_0F) },
11843 { "ldsS", { Gv, Mp } },
11844 { VEX_C5_TABLE (VEX_0F) },
11847 /* MOD_VEX_0F12_PREFIX_0 */
11848 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11849 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11853 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11856 /* MOD_VEX_0F16_PREFIX_0 */
11857 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11858 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11862 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11866 { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11871 { VEX_W_TABLE (VEX_W_0F50_M_0) },
11874 /* MOD_VEX_0F71_REG_2 */
11876 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11879 /* MOD_VEX_0F71_REG_4 */
11881 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11884 /* MOD_VEX_0F71_REG_6 */
11886 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11889 /* MOD_VEX_0F72_REG_2 */
11891 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11894 /* MOD_VEX_0F72_REG_4 */
11896 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11899 /* MOD_VEX_0F72_REG_6 */
11901 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11904 /* MOD_VEX_0F73_REG_2 */
11906 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11909 /* MOD_VEX_0F73_REG_3 */
11911 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11914 /* MOD_VEX_0F73_REG_6 */
11916 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11919 /* MOD_VEX_0F73_REG_7 */
11921 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11924 /* MOD_VEX_0FAE_REG_2 */
11925 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11928 /* MOD_VEX_0FAE_REG_3 */
11929 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11932 /* MOD_VEX_0FD7_PREFIX_2 */
11934 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
11937 /* MOD_VEX_0FE7_PREFIX_2 */
11938 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
11941 /* MOD_VEX_0FF0_PREFIX_3 */
11942 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
11945 /* MOD_VEX_0F381A_PREFIX_2 */
11946 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11949 /* MOD_VEX_0F382A_PREFIX_2 */
11950 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
11953 /* MOD_VEX_0F382C_PREFIX_2 */
11954 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11957 /* MOD_VEX_0F382D_PREFIX_2 */
11958 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11961 /* MOD_VEX_0F382E_PREFIX_2 */
11962 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11965 /* MOD_VEX_0F382F_PREFIX_2 */
11966 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11969 /* MOD_VEX_0F385A_PREFIX_2 */
11970 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11973 /* MOD_VEX_0F388C_PREFIX_2 */
11974 { "vpmaskmov%LW", { XM, Vex, Mx } },
11977 /* MOD_VEX_0F388E_PREFIX_2 */
11978 { "vpmaskmov%LW", { Mx, Vex, XM } },
11980 #define NEED_MOD_TABLE
11981 #include "i386-dis-evex.h"
11982 #undef NEED_MOD_TABLE
11985 static const struct dis386 rm_table[][8] = {
11988 { "xabort", { Skip_MODRM, Ib } },
11992 { "xbeginT", { Skip_MODRM, Jv } },
11995 /* RM_0F01_REG_0 */
11997 { "vmcall", { Skip_MODRM } },
11998 { "vmlaunch", { Skip_MODRM } },
11999 { "vmresume", { Skip_MODRM } },
12000 { "vmxoff", { Skip_MODRM } },
12003 /* RM_0F01_REG_1 */
12004 { "monitor", { { OP_Monitor, 0 } } },
12005 { "mwait", { { OP_Mwait, 0 } } },
12006 { "clac", { Skip_MODRM } },
12007 { "stac", { Skip_MODRM } },
12011 { "encls", { Skip_MODRM } },
12014 /* RM_0F01_REG_2 */
12015 { "xgetbv", { Skip_MODRM } },
12016 { "xsetbv", { Skip_MODRM } },
12019 { "vmfunc", { Skip_MODRM } },
12020 { "xend", { Skip_MODRM } },
12021 { "xtest", { Skip_MODRM } },
12022 { "enclu", { Skip_MODRM } },
12025 /* RM_0F01_REG_3 */
12026 { "vmrun", { Skip_MODRM } },
12027 { "vmmcall", { Skip_MODRM } },
12028 { "vmload", { Skip_MODRM } },
12029 { "vmsave", { Skip_MODRM } },
12030 { "stgi", { Skip_MODRM } },
12031 { "clgi", { Skip_MODRM } },
12032 { "skinit", { Skip_MODRM } },
12033 { "invlpga", { Skip_MODRM } },
12036 /* RM_0F01_REG_7 */
12037 { "swapgs", { Skip_MODRM } },
12038 { "rdtscp", { Skip_MODRM } },
12041 /* RM_0FAE_REG_5 */
12042 { "lfence", { Skip_MODRM } },
12045 /* RM_0FAE_REG_6 */
12046 { "mfence", { Skip_MODRM } },
12049 /* RM_0FAE_REG_7 */
12050 { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7) },
12054 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12056 /* We use the high bit to indicate different name for the same
12058 #define REP_PREFIX (0xf3 | 0x100)
12059 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12060 #define XRELEASE_PREFIX (0xf3 | 0x400)
12061 #define BND_PREFIX (0xf2 | 0x400)
12066 int newrex, i, length;
12072 last_lock_prefix = -1;
12073 last_repz_prefix = -1;
12074 last_repnz_prefix = -1;
12075 last_data_prefix = -1;
12076 last_addr_prefix = -1;
12077 last_rex_prefix = -1;
12078 last_seg_prefix = -1;
12080 active_seg_prefix = 0;
12081 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12082 all_prefixes[i] = 0;
12085 /* The maximum instruction length is 15bytes. */
12086 while (length < MAX_CODE_LENGTH - 1)
12088 FETCH_DATA (the_info, codep + 1);
12092 /* REX prefixes family. */
12109 if (address_mode == mode_64bit)
12113 last_rex_prefix = i;
12116 prefixes |= PREFIX_REPZ;
12117 last_repz_prefix = i;
12120 prefixes |= PREFIX_REPNZ;
12121 last_repnz_prefix = i;
12124 prefixes |= PREFIX_LOCK;
12125 last_lock_prefix = i;
12128 prefixes |= PREFIX_CS;
12129 last_seg_prefix = i;
12130 active_seg_prefix = PREFIX_CS;
12133 prefixes |= PREFIX_SS;
12134 last_seg_prefix = i;
12135 active_seg_prefix = PREFIX_SS;
12138 prefixes |= PREFIX_DS;
12139 last_seg_prefix = i;
12140 active_seg_prefix = PREFIX_DS;
12143 prefixes |= PREFIX_ES;
12144 last_seg_prefix = i;
12145 active_seg_prefix = PREFIX_ES;
12148 prefixes |= PREFIX_FS;
12149 last_seg_prefix = i;
12150 active_seg_prefix = PREFIX_FS;
12153 prefixes |= PREFIX_GS;
12154 last_seg_prefix = i;
12155 active_seg_prefix = PREFIX_GS;
12158 prefixes |= PREFIX_DATA;
12159 last_data_prefix = i;
12162 prefixes |= PREFIX_ADDR;
12163 last_addr_prefix = i;
12166 /* fwait is really an instruction. If there are prefixes
12167 before the fwait, they belong to the fwait, *not* to the
12168 following instruction. */
12170 if (prefixes || rex)
12172 prefixes |= PREFIX_FWAIT;
12174 /* This ensures that the previous REX prefixes are noticed
12175 as unused prefixes, as in the return case below. */
12179 prefixes = PREFIX_FWAIT;
12184 /* Rex is ignored when followed by another prefix. */
12190 if (*codep != FWAIT_OPCODE)
12191 all_prefixes[i++] = *codep;
12199 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12202 static const char *
12203 prefix_name (int pref, int sizeflag)
12205 static const char *rexes [16] =
12208 "rex.B", /* 0x41 */
12209 "rex.X", /* 0x42 */
12210 "rex.XB", /* 0x43 */
12211 "rex.R", /* 0x44 */
12212 "rex.RB", /* 0x45 */
12213 "rex.RX", /* 0x46 */
12214 "rex.RXB", /* 0x47 */
12215 "rex.W", /* 0x48 */
12216 "rex.WB", /* 0x49 */
12217 "rex.WX", /* 0x4a */
12218 "rex.WXB", /* 0x4b */
12219 "rex.WR", /* 0x4c */
12220 "rex.WRB", /* 0x4d */
12221 "rex.WRX", /* 0x4e */
12222 "rex.WRXB", /* 0x4f */
12227 /* REX prefixes family. */
12244 return rexes [pref - 0x40];
12264 return (sizeflag & DFLAG) ? "data16" : "data32";
12266 if (address_mode == mode_64bit)
12267 return (sizeflag & AFLAG) ? "addr32" : "addr64";
12269 return (sizeflag & AFLAG) ? "addr16" : "addr32";
12274 case XACQUIRE_PREFIX:
12276 case XRELEASE_PREFIX:
12285 static char op_out[MAX_OPERANDS][100];
12286 static int op_ad, op_index[MAX_OPERANDS];
12287 static int two_source_ops;
12288 static bfd_vma op_address[MAX_OPERANDS];
12289 static bfd_vma op_riprel[MAX_OPERANDS];
12290 static bfd_vma start_pc;
12293 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12294 * (see topic "Redundant prefixes" in the "Differences from 8086"
12295 * section of the "Virtual 8086 Mode" chapter.)
12296 * 'pc' should be the address of this instruction, it will
12297 * be used to print the target address if this is a relative jump or call
12298 * The function returns the length of this instruction in bytes.
12301 static char intel_syntax;
12302 static char intel_mnemonic = !SYSV386_COMPAT;
12303 static char open_char;
12304 static char close_char;
12305 static char separator_char;
12306 static char scale_char;
12308 /* Here for backwards compatibility. When gdb stops using
12309 print_insn_i386_att and print_insn_i386_intel these functions can
12310 disappear, and print_insn_i386 be merged into print_insn. */
12312 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12316 return print_insn (pc, info);
12320 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12324 return print_insn (pc, info);
12328 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12332 return print_insn (pc, info);
12336 print_i386_disassembler_options (FILE *stream)
12338 fprintf (stream, _("\n\
12339 The following i386/x86-64 specific disassembler options are supported for use\n\
12340 with the -M switch (multiple options should be separated by commas):\n"));
12342 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
12343 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
12344 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
12345 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
12346 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
12347 fprintf (stream, _(" att-mnemonic\n"
12348 " Display instruction in AT&T mnemonic\n"));
12349 fprintf (stream, _(" intel-mnemonic\n"
12350 " Display instruction in Intel mnemonic\n"));
12351 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
12352 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
12353 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
12354 fprintf (stream, _(" data32 Assume 32bit data size\n"));
12355 fprintf (stream, _(" data16 Assume 16bit data size\n"));
12356 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12360 static const struct dis386 bad_opcode = { "(bad)", { XX } };
12362 /* Get a pointer to struct dis386 with a valid name. */
12364 static const struct dis386 *
12365 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12367 int vindex, vex_table_index;
12369 if (dp->name != NULL)
12372 switch (dp->op[0].bytemode)
12374 case USE_REG_TABLE:
12375 dp = ®_table[dp->op[1].bytemode][modrm.reg];
12378 case USE_MOD_TABLE:
12379 vindex = modrm.mod == 0x3 ? 1 : 0;
12380 dp = &mod_table[dp->op[1].bytemode][vindex];
12384 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12387 case USE_PREFIX_TABLE:
12390 /* The prefix in VEX is implicit. */
12391 switch (vex.prefix)
12396 case REPE_PREFIX_OPCODE:
12399 case DATA_PREFIX_OPCODE:
12402 case REPNE_PREFIX_OPCODE:
12412 int last_prefix = -1;
12415 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12416 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12418 if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12420 if (last_repz_prefix > last_repnz_prefix)
12423 prefix = PREFIX_REPZ;
12424 last_prefix = last_repz_prefix;
12429 prefix = PREFIX_REPNZ;
12430 last_prefix = last_repnz_prefix;
12433 /* Ignore the invalid index if it isn't mandatory. */
12434 if (!mandatory_prefix
12435 && (prefix_table[dp->op[1].bytemode][vindex].name
12437 && (prefix_table[dp->op[1].bytemode][vindex].op[0].bytemode
12442 if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12445 prefix = PREFIX_DATA;
12446 last_prefix = last_data_prefix;
12451 used_prefixes |= prefix;
12452 all_prefixes[last_prefix] = 0;
12455 dp = &prefix_table[dp->op[1].bytemode][vindex];
12458 case USE_X86_64_TABLE:
12459 vindex = address_mode == mode_64bit ? 1 : 0;
12460 dp = &x86_64_table[dp->op[1].bytemode][vindex];
12463 case USE_3BYTE_TABLE:
12464 FETCH_DATA (info, codep + 2);
12466 dp = &three_byte_table[dp->op[1].bytemode][vindex];
12468 modrm.mod = (*codep >> 6) & 3;
12469 modrm.reg = (*codep >> 3) & 7;
12470 modrm.rm = *codep & 7;
12473 case USE_VEX_LEN_TABLE:
12477 switch (vex.length)
12490 dp = &vex_len_table[dp->op[1].bytemode][vindex];
12493 case USE_XOP_8F_TABLE:
12494 FETCH_DATA (info, codep + 3);
12495 /* All bits in the REX prefix are ignored. */
12497 rex = ~(*codep >> 5) & 0x7;
12499 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12500 switch ((*codep & 0x1f))
12506 vex_table_index = XOP_08;
12509 vex_table_index = XOP_09;
12512 vex_table_index = XOP_0A;
12516 vex.w = *codep & 0x80;
12517 if (vex.w && address_mode == mode_64bit)
12520 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12521 if (address_mode != mode_64bit
12522 && vex.register_specifier > 0x7)
12528 vex.length = (*codep & 0x4) ? 256 : 128;
12529 switch ((*codep & 0x3))
12535 vex.prefix = DATA_PREFIX_OPCODE;
12538 vex.prefix = REPE_PREFIX_OPCODE;
12541 vex.prefix = REPNE_PREFIX_OPCODE;
12548 dp = &xop_table[vex_table_index][vindex];
12551 FETCH_DATA (info, codep + 1);
12552 modrm.mod = (*codep >> 6) & 3;
12553 modrm.reg = (*codep >> 3) & 7;
12554 modrm.rm = *codep & 7;
12557 case USE_VEX_C4_TABLE:
12559 FETCH_DATA (info, codep + 3);
12560 /* All bits in the REX prefix are ignored. */
12562 rex = ~(*codep >> 5) & 0x7;
12563 switch ((*codep & 0x1f))
12569 vex_table_index = VEX_0F;
12572 vex_table_index = VEX_0F38;
12575 vex_table_index = VEX_0F3A;
12579 vex.w = *codep & 0x80;
12580 if (vex.w && address_mode == mode_64bit)
12583 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12584 if (address_mode != mode_64bit
12585 && vex.register_specifier > 0x7)
12591 vex.length = (*codep & 0x4) ? 256 : 128;
12592 switch ((*codep & 0x3))
12598 vex.prefix = DATA_PREFIX_OPCODE;
12601 vex.prefix = REPE_PREFIX_OPCODE;
12604 vex.prefix = REPNE_PREFIX_OPCODE;
12611 dp = &vex_table[vex_table_index][vindex];
12613 /* There is no MODRM byte for VEX [82|77]. */
12614 if (vindex != 0x77 && vindex != 0x82)
12616 FETCH_DATA (info, codep + 1);
12617 modrm.mod = (*codep >> 6) & 3;
12618 modrm.reg = (*codep >> 3) & 7;
12619 modrm.rm = *codep & 7;
12623 case USE_VEX_C5_TABLE:
12625 FETCH_DATA (info, codep + 2);
12626 /* All bits in the REX prefix are ignored. */
12628 rex = (*codep & 0x80) ? 0 : REX_R;
12630 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12631 if (address_mode != mode_64bit
12632 && vex.register_specifier > 0x7)
12640 vex.length = (*codep & 0x4) ? 256 : 128;
12641 switch ((*codep & 0x3))
12647 vex.prefix = DATA_PREFIX_OPCODE;
12650 vex.prefix = REPE_PREFIX_OPCODE;
12653 vex.prefix = REPNE_PREFIX_OPCODE;
12660 dp = &vex_table[dp->op[1].bytemode][vindex];
12662 /* There is no MODRM byte for VEX [82|77]. */
12663 if (vindex != 0x77 && vindex != 0x82)
12665 FETCH_DATA (info, codep + 1);
12666 modrm.mod = (*codep >> 6) & 3;
12667 modrm.reg = (*codep >> 3) & 7;
12668 modrm.rm = *codep & 7;
12672 case USE_VEX_W_TABLE:
12676 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12679 case USE_EVEX_TABLE:
12680 two_source_ops = 0;
12683 FETCH_DATA (info, codep + 4);
12684 /* All bits in the REX prefix are ignored. */
12686 /* The first byte after 0x62. */
12687 rex = ~(*codep >> 5) & 0x7;
12688 vex.r = *codep & 0x10;
12689 switch ((*codep & 0xf))
12692 return &bad_opcode;
12694 vex_table_index = EVEX_0F;
12697 vex_table_index = EVEX_0F38;
12700 vex_table_index = EVEX_0F3A;
12704 /* The second byte after 0x62. */
12706 vex.w = *codep & 0x80;
12707 if (vex.w && address_mode == mode_64bit)
12710 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12711 if (address_mode != mode_64bit)
12713 /* In 16/32-bit mode silently ignore following bits. */
12717 vex.register_specifier &= 0x7;
12721 if (!(*codep & 0x4))
12722 return &bad_opcode;
12724 switch ((*codep & 0x3))
12730 vex.prefix = DATA_PREFIX_OPCODE;
12733 vex.prefix = REPE_PREFIX_OPCODE;
12736 vex.prefix = REPNE_PREFIX_OPCODE;
12740 /* The third byte after 0x62. */
12743 /* Remember the static rounding bits. */
12744 vex.ll = (*codep >> 5) & 3;
12745 vex.b = (*codep & 0x10) != 0;
12747 vex.v = *codep & 0x8;
12748 vex.mask_register_specifier = *codep & 0x7;
12749 vex.zeroing = *codep & 0x80;
12755 dp = &evex_table[vex_table_index][vindex];
12757 FETCH_DATA (info, codep + 1);
12758 modrm.mod = (*codep >> 6) & 3;
12759 modrm.reg = (*codep >> 3) & 7;
12760 modrm.rm = *codep & 7;
12762 /* Set vector length. */
12763 if (modrm.mod == 3 && vex.b)
12779 return &bad_opcode;
12792 if (dp->name != NULL)
12795 return get_valid_dis386 (dp, info);
12799 get_sib (disassemble_info *info, int sizeflag)
12801 /* If modrm.mod == 3, operand must be register. */
12803 && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12807 FETCH_DATA (info, codep + 2);
12808 sib.index = (codep [1] >> 3) & 7;
12809 sib.scale = (codep [1] >> 6) & 3;
12810 sib.base = codep [1] & 7;
12815 print_insn (bfd_vma pc, disassemble_info *info)
12817 const struct dis386 *dp;
12819 char *op_txt[MAX_OPERANDS];
12821 int sizeflag, orig_sizeflag;
12823 struct dis_private priv;
12826 priv.orig_sizeflag = AFLAG | DFLAG;
12827 if ((info->mach & bfd_mach_i386_i386) != 0)
12828 address_mode = mode_32bit;
12829 else if (info->mach == bfd_mach_i386_i8086)
12831 address_mode = mode_16bit;
12832 priv.orig_sizeflag = 0;
12835 address_mode = mode_64bit;
12837 if (intel_syntax == (char) -1)
12838 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12840 for (p = info->disassembler_options; p != NULL; )
12842 if (CONST_STRNEQ (p, "x86-64"))
12844 address_mode = mode_64bit;
12845 priv.orig_sizeflag = AFLAG | DFLAG;
12847 else if (CONST_STRNEQ (p, "i386"))
12849 address_mode = mode_32bit;
12850 priv.orig_sizeflag = AFLAG | DFLAG;
12852 else if (CONST_STRNEQ (p, "i8086"))
12854 address_mode = mode_16bit;
12855 priv.orig_sizeflag = 0;
12857 else if (CONST_STRNEQ (p, "intel"))
12860 if (CONST_STRNEQ (p + 5, "-mnemonic"))
12861 intel_mnemonic = 1;
12863 else if (CONST_STRNEQ (p, "att"))
12866 if (CONST_STRNEQ (p + 3, "-mnemonic"))
12867 intel_mnemonic = 0;
12869 else if (CONST_STRNEQ (p, "addr"))
12871 if (address_mode == mode_64bit)
12873 if (p[4] == '3' && p[5] == '2')
12874 priv.orig_sizeflag &= ~AFLAG;
12875 else if (p[4] == '6' && p[5] == '4')
12876 priv.orig_sizeflag |= AFLAG;
12880 if (p[4] == '1' && p[5] == '6')
12881 priv.orig_sizeflag &= ~AFLAG;
12882 else if (p[4] == '3' && p[5] == '2')
12883 priv.orig_sizeflag |= AFLAG;
12886 else if (CONST_STRNEQ (p, "data"))
12888 if (p[4] == '1' && p[5] == '6')
12889 priv.orig_sizeflag &= ~DFLAG;
12890 else if (p[4] == '3' && p[5] == '2')
12891 priv.orig_sizeflag |= DFLAG;
12893 else if (CONST_STRNEQ (p, "suffix"))
12894 priv.orig_sizeflag |= SUFFIX_ALWAYS;
12896 p = strchr (p, ',');
12903 names64 = intel_names64;
12904 names32 = intel_names32;
12905 names16 = intel_names16;
12906 names8 = intel_names8;
12907 names8rex = intel_names8rex;
12908 names_seg = intel_names_seg;
12909 names_mm = intel_names_mm;
12910 names_bnd = intel_names_bnd;
12911 names_xmm = intel_names_xmm;
12912 names_ymm = intel_names_ymm;
12913 names_zmm = intel_names_zmm;
12914 index64 = intel_index64;
12915 index32 = intel_index32;
12916 names_mask = intel_names_mask;
12917 index16 = intel_index16;
12920 separator_char = '+';
12925 names64 = att_names64;
12926 names32 = att_names32;
12927 names16 = att_names16;
12928 names8 = att_names8;
12929 names8rex = att_names8rex;
12930 names_seg = att_names_seg;
12931 names_mm = att_names_mm;
12932 names_bnd = att_names_bnd;
12933 names_xmm = att_names_xmm;
12934 names_ymm = att_names_ymm;
12935 names_zmm = att_names_zmm;
12936 index64 = att_index64;
12937 index32 = att_index32;
12938 names_mask = att_names_mask;
12939 index16 = att_index16;
12942 separator_char = ',';
12946 /* The output looks better if we put 7 bytes on a line, since that
12947 puts most long word instructions on a single line. Use 8 bytes
12949 if ((info->mach & bfd_mach_l1om) != 0)
12950 info->bytes_per_line = 8;
12952 info->bytes_per_line = 7;
12954 info->private_data = &priv;
12955 priv.max_fetched = priv.the_buffer;
12956 priv.insn_start = pc;
12959 for (i = 0; i < MAX_OPERANDS; ++i)
12967 start_codep = priv.the_buffer;
12968 codep = priv.the_buffer;
12970 if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12974 /* Getting here means we tried for data but didn't get it. That
12975 means we have an incomplete instruction of some sort. Just
12976 print the first byte as a prefix or a .byte pseudo-op. */
12977 if (codep > priv.the_buffer)
12979 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12981 (*info->fprintf_func) (info->stream, "%s", name);
12984 /* Just print the first byte as a .byte instruction. */
12985 (*info->fprintf_func) (info->stream, ".byte 0x%x",
12986 (unsigned int) priv.the_buffer[0]);
12996 sizeflag = priv.orig_sizeflag;
12998 if (!ckprefix () || rex_used)
13000 /* Too many prefixes or unused REX prefixes. */
13002 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13004 (*info->fprintf_func) (info->stream, "%s%s",
13006 prefix_name (all_prefixes[i], sizeflag));
13010 insn_codep = codep;
13012 FETCH_DATA (info, codep + 1);
13013 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13015 if (((prefixes & PREFIX_FWAIT)
13016 && ((*codep < 0xd8) || (*codep > 0xdf))))
13018 /* Handle prefixes before fwait. */
13019 for (i = 0; i < fwait_prefix && all_prefixes[i];
13021 (*info->fprintf_func) (info->stream, "%s ",
13022 prefix_name (all_prefixes[i], sizeflag));
13023 (*info->fprintf_func) (info->stream, "fwait");
13027 if (*codep == 0x0f)
13029 unsigned char threebyte;
13030 FETCH_DATA (info, codep + 2);
13031 threebyte = *++codep;
13032 dp = &dis386_twobyte[threebyte];
13033 need_modrm = twobyte_has_modrm[*codep];
13034 mandatory_prefix = twobyte_has_mandatory_prefix[*codep];
13039 dp = &dis386[*codep];
13040 need_modrm = onebyte_has_modrm[*codep];
13041 mandatory_prefix = 0;
13045 /* Save sizeflag for printing the extra prefixes later before updating
13046 it for mnemonic and operand processing. The prefix names depend
13047 only on the address mode. */
13048 orig_sizeflag = sizeflag;
13049 if (prefixes & PREFIX_ADDR)
13051 if ((prefixes & PREFIX_DATA))
13057 FETCH_DATA (info, codep + 1);
13058 modrm.mod = (*codep >> 6) & 3;
13059 modrm.reg = (*codep >> 3) & 7;
13060 modrm.rm = *codep & 7;
13068 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13070 get_sib (info, sizeflag);
13071 dofloat (sizeflag);
13075 dp = get_valid_dis386 (dp, info);
13076 if (dp != NULL && putop (dp->name, sizeflag) == 0)
13078 get_sib (info, sizeflag);
13079 for (i = 0; i < MAX_OPERANDS; ++i)
13082 op_ad = MAX_OPERANDS - 1 - i;
13084 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13085 /* For EVEX instruction after the last operand masking
13086 should be printed. */
13087 if (i == 0 && vex.evex)
13089 /* Don't print {%k0}. */
13090 if (vex.mask_register_specifier)
13093 oappend (names_mask[vex.mask_register_specifier]);
13103 /* Check if the REX prefix is used. */
13104 if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13105 all_prefixes[last_rex_prefix] = 0;
13107 /* Check if the SEG prefix is used. */
13108 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13109 | PREFIX_FS | PREFIX_GS)) != 0
13110 && (used_prefixes & active_seg_prefix) != 0)
13111 all_prefixes[last_seg_prefix] = 0;
13113 /* Check if the ADDR prefix is used. */
13114 if ((prefixes & PREFIX_ADDR) != 0
13115 && (used_prefixes & PREFIX_ADDR) != 0)
13116 all_prefixes[last_addr_prefix] = 0;
13118 /* Check if the DATA prefix is used. */
13119 if ((prefixes & PREFIX_DATA) != 0
13120 && (used_prefixes & PREFIX_DATA) != 0)
13121 all_prefixes[last_data_prefix] = 0;
13123 /* Print the extra prefixes. */
13125 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13126 if (all_prefixes[i])
13129 name = prefix_name (all_prefixes[i], orig_sizeflag);
13132 prefix_length += strlen (name) + 1;
13133 (*info->fprintf_func) (info->stream, "%s ", name);
13136 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13137 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13138 used by putop and MMX/SSE operand and may be overriden by the
13139 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13141 if (mandatory_prefix
13142 && dp != &bad_opcode
13144 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13146 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13148 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13150 && (used_prefixes & PREFIX_DATA) == 0))))
13152 (*info->fprintf_func) (info->stream, "(bad)");
13153 return end_codep - priv.the_buffer;
13156 /* Check maximum code length. */
13157 if ((codep - start_codep) > MAX_CODE_LENGTH)
13159 (*info->fprintf_func) (info->stream, "(bad)");
13160 return MAX_CODE_LENGTH;
13163 obufp = mnemonicendp;
13164 for (i = strlen (obuf) + prefix_length; i < 6; i++)
13167 (*info->fprintf_func) (info->stream, "%s", obuf);
13169 /* The enter and bound instructions are printed with operands in the same
13170 order as the intel book; everything else is printed in reverse order. */
13171 if (intel_syntax || two_source_ops)
13175 for (i = 0; i < MAX_OPERANDS; ++i)
13176 op_txt[i] = op_out[i];
13178 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13180 op_ad = op_index[i];
13181 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13182 op_index[MAX_OPERANDS - 1 - i] = op_ad;
13183 riprel = op_riprel[i];
13184 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13185 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13190 for (i = 0; i < MAX_OPERANDS; ++i)
13191 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13195 for (i = 0; i < MAX_OPERANDS; ++i)
13199 (*info->fprintf_func) (info->stream, ",");
13200 if (op_index[i] != -1 && !op_riprel[i])
13201 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13203 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13207 for (i = 0; i < MAX_OPERANDS; i++)
13208 if (op_index[i] != -1 && op_riprel[i])
13210 (*info->fprintf_func) (info->stream, " # ");
13211 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
13212 + op_address[op_index[i]]), info);
13215 return codep - priv.the_buffer;
13218 static const char *float_mem[] = {
13293 static const unsigned char float_mem_mode[] = {
13368 #define ST { OP_ST, 0 }
13369 #define STi { OP_STi, 0 }
13371 #define FGRPd9_2 NULL, { { NULL, 0 } }
13372 #define FGRPd9_4 NULL, { { NULL, 1 } }
13373 #define FGRPd9_5 NULL, { { NULL, 2 } }
13374 #define FGRPd9_6 NULL, { { NULL, 3 } }
13375 #define FGRPd9_7 NULL, { { NULL, 4 } }
13376 #define FGRPda_5 NULL, { { NULL, 5 } }
13377 #define FGRPdb_4 NULL, { { NULL, 6 } }
13378 #define FGRPde_3 NULL, { { NULL, 7 } }
13379 #define FGRPdf_4 NULL, { { NULL, 8 } }
13381 static const struct dis386 float_reg[][8] = {
13384 { "fadd", { ST, STi } },
13385 { "fmul", { ST, STi } },
13386 { "fcom", { STi } },
13387 { "fcomp", { STi } },
13388 { "fsub", { ST, STi } },
13389 { "fsubr", { ST, STi } },
13390 { "fdiv", { ST, STi } },
13391 { "fdivr", { ST, STi } },
13395 { "fld", { STi } },
13396 { "fxch", { STi } },
13406 { "fcmovb", { ST, STi } },
13407 { "fcmove", { ST, STi } },
13408 { "fcmovbe",{ ST, STi } },
13409 { "fcmovu", { ST, STi } },
13417 { "fcmovnb",{ ST, STi } },
13418 { "fcmovne",{ ST, STi } },
13419 { "fcmovnbe",{ ST, STi } },
13420 { "fcmovnu",{ ST, STi } },
13422 { "fucomi", { ST, STi } },
13423 { "fcomi", { ST, STi } },
13428 { "fadd", { STi, ST } },
13429 { "fmul", { STi, ST } },
13432 { "fsub!M", { STi, ST } },
13433 { "fsubM", { STi, ST } },
13434 { "fdiv!M", { STi, ST } },
13435 { "fdivM", { STi, ST } },
13439 { "ffree", { STi } },
13441 { "fst", { STi } },
13442 { "fstp", { STi } },
13443 { "fucom", { STi } },
13444 { "fucomp", { STi } },
13450 { "faddp", { STi, ST } },
13451 { "fmulp", { STi, ST } },
13454 { "fsub!Mp", { STi, ST } },
13455 { "fsubMp", { STi, ST } },
13456 { "fdiv!Mp", { STi, ST } },
13457 { "fdivMp", { STi, ST } },
13461 { "ffreep", { STi } },
13466 { "fucomip", { ST, STi } },
13467 { "fcomip", { ST, STi } },
13472 static char *fgrps[][8] = {
13475 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13480 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13485 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13490 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13495 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13500 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13505 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13506 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13511 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13516 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13521 swap_operand (void)
13523 mnemonicendp[0] = '.';
13524 mnemonicendp[1] = 's';
13529 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13530 int sizeflag ATTRIBUTE_UNUSED)
13532 /* Skip mod/rm byte. */
13538 dofloat (int sizeflag)
13540 const struct dis386 *dp;
13541 unsigned char floatop;
13543 floatop = codep[-1];
13545 if (modrm.mod != 3)
13547 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13549 putop (float_mem[fp_indx], sizeflag);
13552 OP_E (float_mem_mode[fp_indx], sizeflag);
13555 /* Skip mod/rm byte. */
13559 dp = &float_reg[floatop - 0xd8][modrm.reg];
13560 if (dp->name == NULL)
13562 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13564 /* Instruction fnstsw is only one with strange arg. */
13565 if (floatop == 0xdf && codep[-1] == 0xe0)
13566 strcpy (op_out[0], names16[0]);
13570 putop (dp->name, sizeflag);
13575 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13580 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13584 /* Like oappend (below), but S is a string starting with '%'.
13585 In Intel syntax, the '%' is elided. */
13587 oappend_maybe_intel (const char *s)
13589 oappend (s + intel_syntax);
13593 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13595 oappend_maybe_intel ("%st");
13599 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13601 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13602 oappend_maybe_intel (scratchbuf);
13605 /* Capital letters in template are macros. */
13607 putop (const char *in_template, int sizeflag)
13612 unsigned int l = 0, len = 1;
13615 #define SAVE_LAST(c) \
13616 if (l < len && l < sizeof (last)) \
13621 for (p = in_template; *p; p++)
13638 while (*++p != '|')
13639 if (*p == '}' || *p == '\0')
13642 /* Fall through. */
13647 while (*++p != '}')
13658 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13662 if (l == 0 && len == 1)
13667 if (sizeflag & SUFFIX_ALWAYS)
13680 if (address_mode == mode_64bit
13681 && !(prefixes & PREFIX_ADDR))
13692 if (intel_syntax && !alt)
13694 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13696 if (sizeflag & DFLAG)
13697 *obufp++ = intel_syntax ? 'd' : 'l';
13699 *obufp++ = intel_syntax ? 'w' : 's';
13700 used_prefixes |= (prefixes & PREFIX_DATA);
13704 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13707 if (modrm.mod == 3)
13713 if (sizeflag & DFLAG)
13714 *obufp++ = intel_syntax ? 'd' : 'l';
13717 used_prefixes |= (prefixes & PREFIX_DATA);
13723 case 'E': /* For jcxz/jecxz */
13724 if (address_mode == mode_64bit)
13726 if (sizeflag & AFLAG)
13732 if (sizeflag & AFLAG)
13734 used_prefixes |= (prefixes & PREFIX_ADDR);
13739 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13741 if (sizeflag & AFLAG)
13742 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13744 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13745 used_prefixes |= (prefixes & PREFIX_ADDR);
13749 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13751 if ((rex & REX_W) || (sizeflag & DFLAG))
13755 if (!(rex & REX_W))
13756 used_prefixes |= (prefixes & PREFIX_DATA);
13761 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13762 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13764 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13767 if (prefixes & PREFIX_DS)
13788 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13793 /* Fall through. */
13796 if (l != 0 || len != 1)
13804 if (sizeflag & SUFFIX_ALWAYS)
13808 if (intel_mnemonic != cond)
13812 if ((prefixes & PREFIX_FWAIT) == 0)
13815 used_prefixes |= PREFIX_FWAIT;
13821 else if (intel_syntax && (sizeflag & DFLAG))
13825 if (!(rex & REX_W))
13826 used_prefixes |= (prefixes & PREFIX_DATA);
13830 && address_mode == mode_64bit
13831 && ((sizeflag & DFLAG) || (rex & REX_W)))
13836 /* Fall through. */
13839 if (l == 0 && len == 1)
13844 if ((rex & REX_W) == 0
13845 && (prefixes & PREFIX_DATA))
13847 if ((sizeflag & DFLAG) == 0)
13849 used_prefixes |= (prefixes & PREFIX_DATA);
13853 if ((prefixes & PREFIX_DATA)
13855 || (sizeflag & SUFFIX_ALWAYS))
13862 if (sizeflag & DFLAG)
13866 used_prefixes |= (prefixes & PREFIX_DATA);
13872 if (l != 1 || len != 2 || last[0] != 'L')
13878 if ((prefixes & PREFIX_DATA)
13880 || (sizeflag & SUFFIX_ALWAYS))
13887 if (sizeflag & DFLAG)
13888 *obufp++ = intel_syntax ? 'd' : 'l';
13891 used_prefixes |= (prefixes & PREFIX_DATA);
13899 if (address_mode == mode_64bit
13900 && ((sizeflag & DFLAG) || (rex & REX_W)))
13902 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13906 /* Fall through. */
13909 if (l == 0 && len == 1)
13912 if (intel_syntax && !alt)
13915 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13921 if (sizeflag & DFLAG)
13922 *obufp++ = intel_syntax ? 'd' : 'l';
13925 used_prefixes |= (prefixes & PREFIX_DATA);
13931 if (l != 1 || len != 2 || last[0] != 'L')
13937 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13952 else if (sizeflag & DFLAG)
13961 if (intel_syntax && !p[1]
13962 && ((rex & REX_W) || (sizeflag & DFLAG)))
13964 if (!(rex & REX_W))
13965 used_prefixes |= (prefixes & PREFIX_DATA);
13968 if (l == 0 && len == 1)
13972 if (address_mode == mode_64bit
13973 && ((sizeflag & DFLAG) || (rex & REX_W)))
13975 if (sizeflag & SUFFIX_ALWAYS)
13997 /* Fall through. */
14000 if (l == 0 && len == 1)
14005 if (sizeflag & SUFFIX_ALWAYS)
14011 if (sizeflag & DFLAG)
14015 used_prefixes |= (prefixes & PREFIX_DATA);
14029 if (address_mode == mode_64bit
14030 && !(prefixes & PREFIX_ADDR))
14041 if (l != 0 || len != 1)
14046 if (need_vex && vex.prefix)
14048 if (vex.prefix == DATA_PREFIX_OPCODE)
14055 if (prefixes & PREFIX_DATA)
14059 used_prefixes |= (prefixes & PREFIX_DATA);
14063 if (l == 0 && len == 1)
14065 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14076 if (l != 1 || len != 2 || last[0] != 'X')
14084 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14086 switch (vex.length)
14100 if (l == 0 && len == 1)
14102 /* operand size flag for cwtl, cbtw */
14111 else if (sizeflag & DFLAG)
14115 if (!(rex & REX_W))
14116 used_prefixes |= (prefixes & PREFIX_DATA);
14123 && last[0] != 'L'))
14130 if (last[0] == 'X')
14131 *obufp++ = vex.w ? 'd': 's';
14133 *obufp++ = vex.w ? 'q': 'd';
14140 mnemonicendp = obufp;
14145 oappend (const char *s)
14147 obufp = stpcpy (obufp, s);
14153 /* Only print the active segment register. */
14154 if (!active_seg_prefix)
14157 used_prefixes |= active_seg_prefix;
14158 switch (active_seg_prefix)
14161 oappend_maybe_intel ("%cs:");
14164 oappend_maybe_intel ("%ds:");
14167 oappend_maybe_intel ("%ss:");
14170 oappend_maybe_intel ("%es:");
14173 oappend_maybe_intel ("%fs:");
14176 oappend_maybe_intel ("%gs:");
14184 OP_indirE (int bytemode, int sizeflag)
14188 OP_E (bytemode, sizeflag);
14192 print_operand_value (char *buf, int hex, bfd_vma disp)
14194 if (address_mode == mode_64bit)
14202 sprintf_vma (tmp, disp);
14203 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14204 strcpy (buf + 2, tmp + i);
14208 bfd_signed_vma v = disp;
14215 /* Check for possible overflow on 0x8000000000000000. */
14218 strcpy (buf, "9223372036854775808");
14232 tmp[28 - i] = (v % 10) + '0';
14236 strcpy (buf, tmp + 29 - i);
14242 sprintf (buf, "0x%x", (unsigned int) disp);
14244 sprintf (buf, "%d", (int) disp);
14248 /* Put DISP in BUF as signed hex number. */
14251 print_displacement (char *buf, bfd_vma disp)
14253 bfd_signed_vma val = disp;
14262 /* Check for possible overflow. */
14265 switch (address_mode)
14268 strcpy (buf + j, "0x8000000000000000");
14271 strcpy (buf + j, "0x80000000");
14274 strcpy (buf + j, "0x8000");
14284 sprintf_vma (tmp, (bfd_vma) val);
14285 for (i = 0; tmp[i] == '0'; i++)
14287 if (tmp[i] == '\0')
14289 strcpy (buf + j, tmp + i);
14293 intel_operand_size (int bytemode, int sizeflag)
14297 && (bytemode == x_mode
14298 || bytemode == evex_half_bcst_xmmq_mode))
14301 oappend ("QWORD PTR ");
14303 oappend ("DWORD PTR ");
14312 oappend ("BYTE PTR ");
14317 case dqw_swap_mode:
14318 oappend ("WORD PTR ");
14321 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14323 oappend ("QWORD PTR ");
14332 oappend ("QWORD PTR ");
14335 if ((sizeflag & DFLAG) || bytemode == dq_mode)
14336 oappend ("DWORD PTR ");
14338 oappend ("WORD PTR ");
14339 used_prefixes |= (prefixes & PREFIX_DATA);
14343 if ((rex & REX_W) || (sizeflag & DFLAG))
14345 oappend ("WORD PTR ");
14346 if (!(rex & REX_W))
14347 used_prefixes |= (prefixes & PREFIX_DATA);
14350 if (sizeflag & DFLAG)
14351 oappend ("QWORD PTR ");
14353 oappend ("DWORD PTR ");
14354 used_prefixes |= (prefixes & PREFIX_DATA);
14357 case d_scalar_mode:
14358 case d_scalar_swap_mode:
14361 oappend ("DWORD PTR ");
14364 case q_scalar_mode:
14365 case q_scalar_swap_mode:
14367 oappend ("QWORD PTR ");
14370 if (address_mode == mode_64bit)
14371 oappend ("QWORD PTR ");
14373 oappend ("DWORD PTR ");
14376 if (sizeflag & DFLAG)
14377 oappend ("FWORD PTR ");
14379 oappend ("DWORD PTR ");
14380 used_prefixes |= (prefixes & PREFIX_DATA);
14383 oappend ("TBYTE PTR ");
14387 case evex_x_gscat_mode:
14388 case evex_x_nobcst_mode:
14391 switch (vex.length)
14394 oappend ("XMMWORD PTR ");
14397 oappend ("YMMWORD PTR ");
14400 oappend ("ZMMWORD PTR ");
14407 oappend ("XMMWORD PTR ");
14410 oappend ("XMMWORD PTR ");
14413 oappend ("YMMWORD PTR ");
14416 case evex_half_bcst_xmmq_mode:
14420 switch (vex.length)
14423 oappend ("QWORD PTR ");
14426 oappend ("XMMWORD PTR ");
14429 oappend ("YMMWORD PTR ");
14439 switch (vex.length)
14444 oappend ("BYTE PTR ");
14454 switch (vex.length)
14459 oappend ("WORD PTR ");
14469 switch (vex.length)
14474 oappend ("DWORD PTR ");
14484 switch (vex.length)
14489 oappend ("QWORD PTR ");
14499 switch (vex.length)
14502 oappend ("WORD PTR ");
14505 oappend ("DWORD PTR ");
14508 oappend ("QWORD PTR ");
14518 switch (vex.length)
14521 oappend ("DWORD PTR ");
14524 oappend ("QWORD PTR ");
14527 oappend ("XMMWORD PTR ");
14537 switch (vex.length)
14540 oappend ("QWORD PTR ");
14543 oappend ("YMMWORD PTR ");
14546 oappend ("ZMMWORD PTR ");
14556 switch (vex.length)
14560 oappend ("XMMWORD PTR ");
14567 oappend ("OWORD PTR ");
14570 case vex_w_dq_mode:
14571 case vex_scalar_w_dq_mode:
14576 oappend ("QWORD PTR ");
14578 oappend ("DWORD PTR ");
14580 case vex_vsib_d_w_dq_mode:
14581 case vex_vsib_q_w_dq_mode:
14588 oappend ("QWORD PTR ");
14590 oappend ("DWORD PTR ");
14594 switch (vex.length)
14597 oappend ("XMMWORD PTR ");
14600 oappend ("YMMWORD PTR ");
14603 oappend ("ZMMWORD PTR ");
14610 case vex_vsib_q_w_d_mode:
14611 case vex_vsib_d_w_d_mode:
14612 if (!need_vex || !vex.evex)
14615 switch (vex.length)
14618 oappend ("QWORD PTR ");
14621 oappend ("XMMWORD PTR ");
14624 oappend ("YMMWORD PTR ");
14632 if (!need_vex || vex.length != 128)
14635 oappend ("DWORD PTR ");
14637 oappend ("BYTE PTR ");
14643 oappend ("QWORD PTR ");
14645 oappend ("WORD PTR ");
14654 OP_E_register (int bytemode, int sizeflag)
14656 int reg = modrm.rm;
14657 const char **names;
14663 if ((sizeflag & SUFFIX_ALWAYS)
14664 && (bytemode == b_swap_mode
14665 || bytemode == v_swap_mode
14666 || bytemode == dqw_swap_mode))
14692 names = address_mode == mode_64bit ? names64 : names32;
14698 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14711 case dqw_swap_mode:
14717 if ((sizeflag & DFLAG)
14718 || (bytemode != v_mode
14719 && bytemode != v_swap_mode))
14723 used_prefixes |= (prefixes & PREFIX_DATA);
14728 names = names_mask;
14733 oappend (INTERNAL_DISASSEMBLER_ERROR);
14736 oappend (names[reg]);
14740 OP_E_memory (int bytemode, int sizeflag)
14743 int add = (rex & REX_B) ? 8 : 0;
14749 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
14751 && bytemode != x_mode
14752 && bytemode != xmmq_mode
14753 && bytemode != evex_half_bcst_xmmq_mode)
14762 case dqw_swap_mode:
14769 case vex_vsib_d_w_dq_mode:
14770 case vex_vsib_d_w_d_mode:
14771 case vex_vsib_q_w_dq_mode:
14772 case vex_vsib_q_w_d_mode:
14773 case evex_x_gscat_mode:
14775 shift = vex.w ? 3 : 2;
14778 case evex_half_bcst_xmmq_mode:
14782 shift = vex.w ? 3 : 2;
14785 /* Fall through if vex.b == 0. */
14789 case evex_x_nobcst_mode:
14791 switch (vex.length)
14814 case q_scalar_mode:
14816 case q_scalar_swap_mode:
14822 case d_scalar_mode:
14824 case d_scalar_swap_mode:
14836 /* Make necessary corrections to shift for modes that need it.
14837 For these modes we currently have shift 4, 5 or 6 depending on
14838 vex.length (it corresponds to xmmword, ymmword or zmmword
14839 operand). We might want to make it 3, 4 or 5 (e.g. for
14840 xmmq_mode). In case of broadcast enabled the corrections
14841 aren't needed, as element size is always 32 or 64 bits. */
14843 && (bytemode == xmmq_mode
14844 || bytemode == evex_half_bcst_xmmq_mode))
14846 else if (bytemode == xmmqd_mode)
14848 else if (bytemode == xmmdw_mode)
14850 else if (bytemode == ymmq_mode && vex.length == 128)
14858 intel_operand_size (bytemode, sizeflag);
14861 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14863 /* 32/64 bit address mode */
14872 int addr32flag = !((sizeflag & AFLAG)
14873 || bytemode == v_bnd_mode
14874 || bytemode == bnd_mode);
14875 const char **indexes64 = names64;
14876 const char **indexes32 = names32;
14886 vindex = sib.index;
14892 case vex_vsib_d_w_dq_mode:
14893 case vex_vsib_d_w_d_mode:
14894 case vex_vsib_q_w_dq_mode:
14895 case vex_vsib_q_w_d_mode:
14905 switch (vex.length)
14908 indexes64 = indexes32 = names_xmm;
14912 || bytemode == vex_vsib_q_w_dq_mode
14913 || bytemode == vex_vsib_q_w_d_mode)
14914 indexes64 = indexes32 = names_ymm;
14916 indexes64 = indexes32 = names_xmm;
14920 || bytemode == vex_vsib_q_w_dq_mode
14921 || bytemode == vex_vsib_q_w_d_mode)
14922 indexes64 = indexes32 = names_zmm;
14924 indexes64 = indexes32 = names_ymm;
14931 haveindex = vindex != 4;
14938 rbase = base + add;
14946 if (address_mode == mode_64bit && !havesib)
14952 FETCH_DATA (the_info, codep + 1);
14954 if ((disp & 0x80) != 0)
14956 if (vex.evex && shift > 0)
14964 /* In 32bit mode, we need index register to tell [offset] from
14965 [eiz*1 + offset]. */
14966 needindex = (havesib
14969 && address_mode == mode_32bit);
14970 havedisp = (havebase
14972 || (havesib && (haveindex || scale != 0)));
14975 if (modrm.mod != 0 || base == 5)
14977 if (havedisp || riprel)
14978 print_displacement (scratchbuf, disp);
14980 print_operand_value (scratchbuf, 1, disp);
14981 oappend (scratchbuf);
14985 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
14989 if ((havebase || haveindex || riprel)
14990 && (bytemode != v_bnd_mode)
14991 && (bytemode != bnd_mode))
14992 used_prefixes |= PREFIX_ADDR;
14994 if (havedisp || (intel_syntax && riprel))
14996 *obufp++ = open_char;
14997 if (intel_syntax && riprel)
15000 oappend (sizeflag & AFLAG ? "rip" : "eip");
15004 oappend (address_mode == mode_64bit && !addr32flag
15005 ? names64[rbase] : names32[rbase]);
15008 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
15009 print index to tell base + index from base. */
15013 || (havebase && base != ESP_REG_NUM))
15015 if (!intel_syntax || havebase)
15017 *obufp++ = separator_char;
15021 oappend (address_mode == mode_64bit && !addr32flag
15022 ? indexes64[vindex] : indexes32[vindex]);
15024 oappend (address_mode == mode_64bit && !addr32flag
15025 ? index64 : index32);
15027 *obufp++ = scale_char;
15029 sprintf (scratchbuf, "%d", 1 << scale);
15030 oappend (scratchbuf);
15034 && (disp || modrm.mod != 0 || base == 5))
15036 if (!havedisp || (bfd_signed_vma) disp >= 0)
15041 else if (modrm.mod != 1 && disp != -disp)
15045 disp = - (bfd_signed_vma) disp;
15049 print_displacement (scratchbuf, disp);
15051 print_operand_value (scratchbuf, 1, disp);
15052 oappend (scratchbuf);
15055 *obufp++ = close_char;
15058 else if (intel_syntax)
15060 if (modrm.mod != 0 || base == 5)
15062 if (!active_seg_prefix)
15064 oappend (names_seg[ds_reg - es_reg]);
15067 print_operand_value (scratchbuf, 1, disp);
15068 oappend (scratchbuf);
15074 /* 16 bit address mode */
15075 used_prefixes |= prefixes & PREFIX_ADDR;
15082 if ((disp & 0x8000) != 0)
15087 FETCH_DATA (the_info, codep + 1);
15089 if ((disp & 0x80) != 0)
15094 if ((disp & 0x8000) != 0)
15100 if (modrm.mod != 0 || modrm.rm == 6)
15102 print_displacement (scratchbuf, disp);
15103 oappend (scratchbuf);
15106 if (modrm.mod != 0 || modrm.rm != 6)
15108 *obufp++ = open_char;
15110 oappend (index16[modrm.rm]);
15112 && (disp || modrm.mod != 0 || modrm.rm == 6))
15114 if ((bfd_signed_vma) disp >= 0)
15119 else if (modrm.mod != 1)
15123 disp = - (bfd_signed_vma) disp;
15126 print_displacement (scratchbuf, disp);
15127 oappend (scratchbuf);
15130 *obufp++ = close_char;
15133 else if (intel_syntax)
15135 if (!active_seg_prefix)
15137 oappend (names_seg[ds_reg - es_reg]);
15140 print_operand_value (scratchbuf, 1, disp & 0xffff);
15141 oappend (scratchbuf);
15144 if (vex.evex && vex.b
15145 && (bytemode == x_mode
15146 || bytemode == xmmq_mode
15147 || bytemode == evex_half_bcst_xmmq_mode))
15150 || bytemode == xmmq_mode
15151 || bytemode == evex_half_bcst_xmmq_mode)
15153 switch (vex.length)
15156 oappend ("{1to2}");
15159 oappend ("{1to4}");
15162 oappend ("{1to8}");
15170 switch (vex.length)
15173 oappend ("{1to4}");
15176 oappend ("{1to8}");
15179 oappend ("{1to16}");
15189 OP_E (int bytemode, int sizeflag)
15191 /* Skip mod/rm byte. */
15195 if (modrm.mod == 3)
15196 OP_E_register (bytemode, sizeflag);
15198 OP_E_memory (bytemode, sizeflag);
15202 OP_G (int bytemode, int sizeflag)
15213 oappend (names8rex[modrm.reg + add]);
15215 oappend (names8[modrm.reg + add]);
15218 oappend (names16[modrm.reg + add]);
15223 oappend (names32[modrm.reg + add]);
15226 oappend (names64[modrm.reg + add]);
15229 oappend (names_bnd[modrm.reg]);
15236 case dqw_swap_mode:
15239 oappend (names64[modrm.reg + add]);
15242 if ((sizeflag & DFLAG) || bytemode != v_mode)
15243 oappend (names32[modrm.reg + add]);
15245 oappend (names16[modrm.reg + add]);
15246 used_prefixes |= (prefixes & PREFIX_DATA);
15250 if (address_mode == mode_64bit)
15251 oappend (names64[modrm.reg + add]);
15253 oappend (names32[modrm.reg + add]);
15257 oappend (names_mask[modrm.reg + add]);
15260 oappend (INTERNAL_DISASSEMBLER_ERROR);
15273 FETCH_DATA (the_info, codep + 8);
15274 a = *codep++ & 0xff;
15275 a |= (*codep++ & 0xff) << 8;
15276 a |= (*codep++ & 0xff) << 16;
15277 a |= (*codep++ & 0xff) << 24;
15278 b = *codep++ & 0xff;
15279 b |= (*codep++ & 0xff) << 8;
15280 b |= (*codep++ & 0xff) << 16;
15281 b |= (*codep++ & 0xff) << 24;
15282 x = a + ((bfd_vma) b << 32);
15290 static bfd_signed_vma
15293 bfd_signed_vma x = 0;
15295 FETCH_DATA (the_info, codep + 4);
15296 x = *codep++ & (bfd_signed_vma) 0xff;
15297 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15298 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15299 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15303 static bfd_signed_vma
15306 bfd_signed_vma x = 0;
15308 FETCH_DATA (the_info, codep + 4);
15309 x = *codep++ & (bfd_signed_vma) 0xff;
15310 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15311 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15312 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15314 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15324 FETCH_DATA (the_info, codep + 2);
15325 x = *codep++ & 0xff;
15326 x |= (*codep++ & 0xff) << 8;
15331 set_op (bfd_vma op, int riprel)
15333 op_index[op_ad] = op_ad;
15334 if (address_mode == mode_64bit)
15336 op_address[op_ad] = op;
15337 op_riprel[op_ad] = riprel;
15341 /* Mask to get a 32-bit address. */
15342 op_address[op_ad] = op & 0xffffffff;
15343 op_riprel[op_ad] = riprel & 0xffffffff;
15348 OP_REG (int code, int sizeflag)
15355 case es_reg: case ss_reg: case cs_reg:
15356 case ds_reg: case fs_reg: case gs_reg:
15357 oappend (names_seg[code - es_reg]);
15369 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15370 case sp_reg: case bp_reg: case si_reg: case di_reg:
15371 s = names16[code - ax_reg + add];
15373 case al_reg: case ah_reg: case cl_reg: case ch_reg:
15374 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15377 s = names8rex[code - al_reg + add];
15379 s = names8[code - al_reg];
15381 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15382 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15383 if (address_mode == mode_64bit
15384 && ((sizeflag & DFLAG) || (rex & REX_W)))
15386 s = names64[code - rAX_reg + add];
15389 code += eAX_reg - rAX_reg;
15390 /* Fall through. */
15391 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15392 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15395 s = names64[code - eAX_reg + add];
15398 if (sizeflag & DFLAG)
15399 s = names32[code - eAX_reg + add];
15401 s = names16[code - eAX_reg + add];
15402 used_prefixes |= (prefixes & PREFIX_DATA);
15406 s = INTERNAL_DISASSEMBLER_ERROR;
15413 OP_IMREG (int code, int sizeflag)
15425 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15426 case sp_reg: case bp_reg: case si_reg: case di_reg:
15427 s = names16[code - ax_reg];
15429 case es_reg: case ss_reg: case cs_reg:
15430 case ds_reg: case fs_reg: case gs_reg:
15431 s = names_seg[code - es_reg];
15433 case al_reg: case ah_reg: case cl_reg: case ch_reg:
15434 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15437 s = names8rex[code - al_reg];
15439 s = names8[code - al_reg];
15441 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15442 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15445 s = names64[code - eAX_reg];
15448 if (sizeflag & DFLAG)
15449 s = names32[code - eAX_reg];
15451 s = names16[code - eAX_reg];
15452 used_prefixes |= (prefixes & PREFIX_DATA);
15455 case z_mode_ax_reg:
15456 if ((rex & REX_W) || (sizeflag & DFLAG))
15460 if (!(rex & REX_W))
15461 used_prefixes |= (prefixes & PREFIX_DATA);
15464 s = INTERNAL_DISASSEMBLER_ERROR;
15471 OP_I (int bytemode, int sizeflag)
15474 bfd_signed_vma mask = -1;
15479 FETCH_DATA (the_info, codep + 1);
15484 if (address_mode == mode_64bit)
15489 /* Fall through. */
15496 if (sizeflag & DFLAG)
15506 used_prefixes |= (prefixes & PREFIX_DATA);
15518 oappend (INTERNAL_DISASSEMBLER_ERROR);
15523 scratchbuf[0] = '$';
15524 print_operand_value (scratchbuf + 1, 1, op);
15525 oappend_maybe_intel (scratchbuf);
15526 scratchbuf[0] = '\0';
15530 OP_I64 (int bytemode, int sizeflag)
15533 bfd_signed_vma mask = -1;
15535 if (address_mode != mode_64bit)
15537 OP_I (bytemode, sizeflag);
15544 FETCH_DATA (the_info, codep + 1);
15554 if (sizeflag & DFLAG)
15564 used_prefixes |= (prefixes & PREFIX_DATA);
15572 oappend (INTERNAL_DISASSEMBLER_ERROR);
15577 scratchbuf[0] = '$';
15578 print_operand_value (scratchbuf + 1, 1, op);
15579 oappend_maybe_intel (scratchbuf);
15580 scratchbuf[0] = '\0';
15584 OP_sI (int bytemode, int sizeflag)
15592 FETCH_DATA (the_info, codep + 1);
15594 if ((op & 0x80) != 0)
15596 if (bytemode == b_T_mode)
15598 if (address_mode != mode_64bit
15599 || !((sizeflag & DFLAG) || (rex & REX_W)))
15601 /* The operand-size prefix is overridden by a REX prefix. */
15602 if ((sizeflag & DFLAG) || (rex & REX_W))
15610 if (!(rex & REX_W))
15612 if (sizeflag & DFLAG)
15620 /* The operand-size prefix is overridden by a REX prefix. */
15621 if ((sizeflag & DFLAG) || (rex & REX_W))
15627 oappend (INTERNAL_DISASSEMBLER_ERROR);
15631 scratchbuf[0] = '$';
15632 print_operand_value (scratchbuf + 1, 1, op);
15633 oappend_maybe_intel (scratchbuf);
15637 OP_J (int bytemode, int sizeflag)
15641 bfd_vma segment = 0;
15646 FETCH_DATA (the_info, codep + 1);
15648 if ((disp & 0x80) != 0)
15653 if ((sizeflag & DFLAG) || (rex & REX_W))
15658 if ((disp & 0x8000) != 0)
15660 /* In 16bit mode, address is wrapped around at 64k within
15661 the same segment. Otherwise, a data16 prefix on a jump
15662 instruction means that the pc is masked to 16 bits after
15663 the displacement is added! */
15665 if ((prefixes & PREFIX_DATA) == 0)
15666 segment = ((start_pc + codep - start_codep)
15667 & ~((bfd_vma) 0xffff));
15669 if (!(rex & REX_W))
15670 used_prefixes |= (prefixes & PREFIX_DATA);
15673 oappend (INTERNAL_DISASSEMBLER_ERROR);
15676 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15678 print_operand_value (scratchbuf, 1, disp);
15679 oappend (scratchbuf);
15683 OP_SEG (int bytemode, int sizeflag)
15685 if (bytemode == w_mode)
15686 oappend (names_seg[modrm.reg]);
15688 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15692 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15696 if (sizeflag & DFLAG)
15706 used_prefixes |= (prefixes & PREFIX_DATA);
15708 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15710 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15711 oappend (scratchbuf);
15715 OP_OFF (int bytemode, int sizeflag)
15719 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15720 intel_operand_size (bytemode, sizeflag);
15723 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15730 if (!active_seg_prefix)
15732 oappend (names_seg[ds_reg - es_reg]);
15736 print_operand_value (scratchbuf, 1, off);
15737 oappend (scratchbuf);
15741 OP_OFF64 (int bytemode, int sizeflag)
15745 if (address_mode != mode_64bit
15746 || (prefixes & PREFIX_ADDR))
15748 OP_OFF (bytemode, sizeflag);
15752 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15753 intel_operand_size (bytemode, sizeflag);
15760 if (!active_seg_prefix)
15762 oappend (names_seg[ds_reg - es_reg]);
15766 print_operand_value (scratchbuf, 1, off);
15767 oappend (scratchbuf);
15771 ptr_reg (int code, int sizeflag)
15775 *obufp++ = open_char;
15776 used_prefixes |= (prefixes & PREFIX_ADDR);
15777 if (address_mode == mode_64bit)
15779 if (!(sizeflag & AFLAG))
15780 s = names32[code - eAX_reg];
15782 s = names64[code - eAX_reg];
15784 else if (sizeflag & AFLAG)
15785 s = names32[code - eAX_reg];
15787 s = names16[code - eAX_reg];
15789 *obufp++ = close_char;
15794 OP_ESreg (int code, int sizeflag)
15800 case 0x6d: /* insw/insl */
15801 intel_operand_size (z_mode, sizeflag);
15803 case 0xa5: /* movsw/movsl/movsq */
15804 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15805 case 0xab: /* stosw/stosl */
15806 case 0xaf: /* scasw/scasl */
15807 intel_operand_size (v_mode, sizeflag);
15810 intel_operand_size (b_mode, sizeflag);
15813 oappend_maybe_intel ("%es:");
15814 ptr_reg (code, sizeflag);
15818 OP_DSreg (int code, int sizeflag)
15824 case 0x6f: /* outsw/outsl */
15825 intel_operand_size (z_mode, sizeflag);
15827 case 0xa5: /* movsw/movsl/movsq */
15828 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15829 case 0xad: /* lodsw/lodsl/lodsq */
15830 intel_operand_size (v_mode, sizeflag);
15833 intel_operand_size (b_mode, sizeflag);
15836 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15837 default segment register DS is printed. */
15838 if (!active_seg_prefix)
15839 active_seg_prefix = PREFIX_DS;
15841 ptr_reg (code, sizeflag);
15845 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15853 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15855 all_prefixes[last_lock_prefix] = 0;
15856 used_prefixes |= PREFIX_LOCK;
15861 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15862 oappend_maybe_intel (scratchbuf);
15866 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15875 sprintf (scratchbuf, "db%d", modrm.reg + add);
15877 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15878 oappend (scratchbuf);
15882 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15884 sprintf (scratchbuf, "%%tr%d", modrm.reg);
15885 oappend_maybe_intel (scratchbuf);
15889 OP_R (int bytemode, int sizeflag)
15891 /* Skip mod/rm byte. */
15894 OP_E_register (bytemode, sizeflag);
15898 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15900 int reg = modrm.reg;
15901 const char **names;
15903 used_prefixes |= (prefixes & PREFIX_DATA);
15904 if (prefixes & PREFIX_DATA)
15913 oappend (names[reg]);
15917 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15919 int reg = modrm.reg;
15920 const char **names;
15932 && bytemode != xmm_mode
15933 && bytemode != xmmq_mode
15934 && bytemode != evex_half_bcst_xmmq_mode
15935 && bytemode != ymm_mode
15936 && bytemode != scalar_mode)
15938 switch (vex.length)
15945 || (bytemode != vex_vsib_q_w_dq_mode
15946 && bytemode != vex_vsib_q_w_d_mode))
15958 else if (bytemode == xmmq_mode
15959 || bytemode == evex_half_bcst_xmmq_mode)
15961 switch (vex.length)
15974 else if (bytemode == ymm_mode)
15978 oappend (names[reg]);
15982 OP_EM (int bytemode, int sizeflag)
15985 const char **names;
15987 if (modrm.mod != 3)
15990 && (bytemode == v_mode || bytemode == v_swap_mode))
15992 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15993 used_prefixes |= (prefixes & PREFIX_DATA);
15995 OP_E (bytemode, sizeflag);
15999 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16002 /* Skip mod/rm byte. */
16005 used_prefixes |= (prefixes & PREFIX_DATA);
16007 if (prefixes & PREFIX_DATA)
16016 oappend (names[reg]);
16019 /* cvt* are the only instructions in sse2 which have
16020 both SSE and MMX operands and also have 0x66 prefix
16021 in their opcode. 0x66 was originally used to differentiate
16022 between SSE and MMX instruction(operands). So we have to handle the
16023 cvt* separately using OP_EMC and OP_MXC */
16025 OP_EMC (int bytemode, int sizeflag)
16027 if (modrm.mod != 3)
16029 if (intel_syntax && bytemode == v_mode)
16031 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16032 used_prefixes |= (prefixes & PREFIX_DATA);
16034 OP_E (bytemode, sizeflag);
16038 /* Skip mod/rm byte. */
16041 used_prefixes |= (prefixes & PREFIX_DATA);
16042 oappend (names_mm[modrm.rm]);
16046 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16048 used_prefixes |= (prefixes & PREFIX_DATA);
16049 oappend (names_mm[modrm.reg]);
16053 OP_EX (int bytemode, int sizeflag)
16056 const char **names;
16058 /* Skip mod/rm byte. */
16062 if (modrm.mod != 3)
16064 OP_E_memory (bytemode, sizeflag);
16079 if ((sizeflag & SUFFIX_ALWAYS)
16080 && (bytemode == x_swap_mode
16081 || bytemode == d_swap_mode
16082 || bytemode == dqw_swap_mode
16083 || bytemode == d_scalar_swap_mode
16084 || bytemode == q_swap_mode
16085 || bytemode == q_scalar_swap_mode))
16089 && bytemode != xmm_mode
16090 && bytemode != xmmdw_mode
16091 && bytemode != xmmqd_mode
16092 && bytemode != xmm_mb_mode
16093 && bytemode != xmm_mw_mode
16094 && bytemode != xmm_md_mode
16095 && bytemode != xmm_mq_mode
16096 && bytemode != xmm_mdq_mode
16097 && bytemode != xmmq_mode
16098 && bytemode != evex_half_bcst_xmmq_mode
16099 && bytemode != ymm_mode
16100 && bytemode != d_scalar_mode
16101 && bytemode != d_scalar_swap_mode
16102 && bytemode != q_scalar_mode
16103 && bytemode != q_scalar_swap_mode
16104 && bytemode != vex_scalar_w_dq_mode)
16106 switch (vex.length)
16121 else if (bytemode == xmmq_mode
16122 || bytemode == evex_half_bcst_xmmq_mode)
16124 switch (vex.length)
16137 else if (bytemode == ymm_mode)
16141 oappend (names[reg]);
16145 OP_MS (int bytemode, int sizeflag)
16147 if (modrm.mod == 3)
16148 OP_EM (bytemode, sizeflag);
16154 OP_XS (int bytemode, int sizeflag)
16156 if (modrm.mod == 3)
16157 OP_EX (bytemode, sizeflag);
16163 OP_M (int bytemode, int sizeflag)
16165 if (modrm.mod == 3)
16166 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16169 OP_E (bytemode, sizeflag);
16173 OP_0f07 (int bytemode, int sizeflag)
16175 if (modrm.mod != 3 || modrm.rm != 0)
16178 OP_E (bytemode, sizeflag);
16181 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16182 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16185 NOP_Fixup1 (int bytemode, int sizeflag)
16187 if ((prefixes & PREFIX_DATA) != 0
16190 && address_mode == mode_64bit))
16191 OP_REG (bytemode, sizeflag);
16193 strcpy (obuf, "nop");
16197 NOP_Fixup2 (int bytemode, int sizeflag)
16199 if ((prefixes & PREFIX_DATA) != 0
16202 && address_mode == mode_64bit))
16203 OP_IMREG (bytemode, sizeflag);
16206 static const char *const Suffix3DNow[] = {
16207 /* 00 */ NULL, NULL, NULL, NULL,
16208 /* 04 */ NULL, NULL, NULL, NULL,
16209 /* 08 */ NULL, NULL, NULL, NULL,
16210 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
16211 /* 10 */ NULL, NULL, NULL, NULL,
16212 /* 14 */ NULL, NULL, NULL, NULL,
16213 /* 18 */ NULL, NULL, NULL, NULL,
16214 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
16215 /* 20 */ NULL, NULL, NULL, NULL,
16216 /* 24 */ NULL, NULL, NULL, NULL,
16217 /* 28 */ NULL, NULL, NULL, NULL,
16218 /* 2C */ NULL, NULL, NULL, NULL,
16219 /* 30 */ NULL, NULL, NULL, NULL,
16220 /* 34 */ NULL, NULL, NULL, NULL,
16221 /* 38 */ NULL, NULL, NULL, NULL,
16222 /* 3C */ NULL, NULL, NULL, NULL,
16223 /* 40 */ NULL, NULL, NULL, NULL,
16224 /* 44 */ NULL, NULL, NULL, NULL,
16225 /* 48 */ NULL, NULL, NULL, NULL,
16226 /* 4C */ NULL, NULL, NULL, NULL,
16227 /* 50 */ NULL, NULL, NULL, NULL,
16228 /* 54 */ NULL, NULL, NULL, NULL,
16229 /* 58 */ NULL, NULL, NULL, NULL,
16230 /* 5C */ NULL, NULL, NULL, NULL,
16231 /* 60 */ NULL, NULL, NULL, NULL,
16232 /* 64 */ NULL, NULL, NULL, NULL,
16233 /* 68 */ NULL, NULL, NULL, NULL,
16234 /* 6C */ NULL, NULL, NULL, NULL,
16235 /* 70 */ NULL, NULL, NULL, NULL,
16236 /* 74 */ NULL, NULL, NULL, NULL,
16237 /* 78 */ NULL, NULL, NULL, NULL,
16238 /* 7C */ NULL, NULL, NULL, NULL,
16239 /* 80 */ NULL, NULL, NULL, NULL,
16240 /* 84 */ NULL, NULL, NULL, NULL,
16241 /* 88 */ NULL, NULL, "pfnacc", NULL,
16242 /* 8C */ NULL, NULL, "pfpnacc", NULL,
16243 /* 90 */ "pfcmpge", NULL, NULL, NULL,
16244 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
16245 /* 98 */ NULL, NULL, "pfsub", NULL,
16246 /* 9C */ NULL, NULL, "pfadd", NULL,
16247 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
16248 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
16249 /* A8 */ NULL, NULL, "pfsubr", NULL,
16250 /* AC */ NULL, NULL, "pfacc", NULL,
16251 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
16252 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
16253 /* B8 */ NULL, NULL, NULL, "pswapd",
16254 /* BC */ NULL, NULL, NULL, "pavgusb",
16255 /* C0 */ NULL, NULL, NULL, NULL,
16256 /* C4 */ NULL, NULL, NULL, NULL,
16257 /* C8 */ NULL, NULL, NULL, NULL,
16258 /* CC */ NULL, NULL, NULL, NULL,
16259 /* D0 */ NULL, NULL, NULL, NULL,
16260 /* D4 */ NULL, NULL, NULL, NULL,
16261 /* D8 */ NULL, NULL, NULL, NULL,
16262 /* DC */ NULL, NULL, NULL, NULL,
16263 /* E0 */ NULL, NULL, NULL, NULL,
16264 /* E4 */ NULL, NULL, NULL, NULL,
16265 /* E8 */ NULL, NULL, NULL, NULL,
16266 /* EC */ NULL, NULL, NULL, NULL,
16267 /* F0 */ NULL, NULL, NULL, NULL,
16268 /* F4 */ NULL, NULL, NULL, NULL,
16269 /* F8 */ NULL, NULL, NULL, NULL,
16270 /* FC */ NULL, NULL, NULL, NULL,
16274 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16276 const char *mnemonic;
16278 FETCH_DATA (the_info, codep + 1);
16279 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16280 place where an 8-bit immediate would normally go. ie. the last
16281 byte of the instruction. */
16282 obufp = mnemonicendp;
16283 mnemonic = Suffix3DNow[*codep++ & 0xff];
16285 oappend (mnemonic);
16288 /* Since a variable sized modrm/sib chunk is between the start
16289 of the opcode (0x0f0f) and the opcode suffix, we need to do
16290 all the modrm processing first, and don't know until now that
16291 we have a bad opcode. This necessitates some cleaning up. */
16292 op_out[0][0] = '\0';
16293 op_out[1][0] = '\0';
16296 mnemonicendp = obufp;
16299 static struct op simd_cmp_op[] =
16301 { STRING_COMMA_LEN ("eq") },
16302 { STRING_COMMA_LEN ("lt") },
16303 { STRING_COMMA_LEN ("le") },
16304 { STRING_COMMA_LEN ("unord") },
16305 { STRING_COMMA_LEN ("neq") },
16306 { STRING_COMMA_LEN ("nlt") },
16307 { STRING_COMMA_LEN ("nle") },
16308 { STRING_COMMA_LEN ("ord") }
16312 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16314 unsigned int cmp_type;
16316 FETCH_DATA (the_info, codep + 1);
16317 cmp_type = *codep++ & 0xff;
16318 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16321 char *p = mnemonicendp - 2;
16325 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16326 mnemonicendp += simd_cmp_op[cmp_type].len;
16330 /* We have a reserved extension byte. Output it directly. */
16331 scratchbuf[0] = '$';
16332 print_operand_value (scratchbuf + 1, 1, cmp_type);
16333 oappend_maybe_intel (scratchbuf);
16334 scratchbuf[0] = '\0';
16339 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16340 int sizeflag ATTRIBUTE_UNUSED)
16342 /* mwait %eax,%ecx */
16345 const char **names = (address_mode == mode_64bit
16346 ? names64 : names32);
16347 strcpy (op_out[0], names[0]);
16348 strcpy (op_out[1], names[1]);
16349 two_source_ops = 1;
16351 /* Skip mod/rm byte. */
16357 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16358 int sizeflag ATTRIBUTE_UNUSED)
16360 /* monitor %eax,%ecx,%edx" */
16363 const char **op1_names;
16364 const char **names = (address_mode == mode_64bit
16365 ? names64 : names32);
16367 if (!(prefixes & PREFIX_ADDR))
16368 op1_names = (address_mode == mode_16bit
16369 ? names16 : names);
16372 /* Remove "addr16/addr32". */
16373 all_prefixes[last_addr_prefix] = 0;
16374 op1_names = (address_mode != mode_32bit
16375 ? names32 : names16);
16376 used_prefixes |= PREFIX_ADDR;
16378 strcpy (op_out[0], op1_names[0]);
16379 strcpy (op_out[1], names[1]);
16380 strcpy (op_out[2], names[2]);
16381 two_source_ops = 1;
16383 /* Skip mod/rm byte. */
16391 /* Throw away prefixes and 1st. opcode byte. */
16392 codep = insn_codep + 1;
16397 REP_Fixup (int bytemode, int sizeflag)
16399 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16401 if (prefixes & PREFIX_REPZ)
16402 all_prefixes[last_repz_prefix] = REP_PREFIX;
16409 OP_IMREG (bytemode, sizeflag);
16412 OP_ESreg (bytemode, sizeflag);
16415 OP_DSreg (bytemode, sizeflag);
16423 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16427 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16429 if (prefixes & PREFIX_REPNZ)
16430 all_prefixes[last_repnz_prefix] = BND_PREFIX;
16433 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16434 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16438 HLE_Fixup1 (int bytemode, int sizeflag)
16441 && (prefixes & PREFIX_LOCK) != 0)
16443 if (prefixes & PREFIX_REPZ)
16444 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16445 if (prefixes & PREFIX_REPNZ)
16446 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16449 OP_E (bytemode, sizeflag);
16452 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16453 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
16457 HLE_Fixup2 (int bytemode, int sizeflag)
16459 if (modrm.mod != 3)
16461 if (prefixes & PREFIX_REPZ)
16462 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16463 if (prefixes & PREFIX_REPNZ)
16464 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16467 OP_E (bytemode, sizeflag);
16470 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
16471 "xrelease" for memory operand. No check for LOCK prefix. */
16474 HLE_Fixup3 (int bytemode, int sizeflag)
16477 && last_repz_prefix > last_repnz_prefix
16478 && (prefixes & PREFIX_REPZ) != 0)
16479 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16481 OP_E (bytemode, sizeflag);
16485 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16490 /* Change cmpxchg8b to cmpxchg16b. */
16491 char *p = mnemonicendp - 2;
16492 mnemonicendp = stpcpy (p, "16b");
16495 else if ((prefixes & PREFIX_LOCK) != 0)
16497 if (prefixes & PREFIX_REPZ)
16498 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16499 if (prefixes & PREFIX_REPNZ)
16500 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16503 OP_M (bytemode, sizeflag);
16507 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16509 const char **names;
16513 switch (vex.length)
16527 oappend (names[reg]);
16531 CRC32_Fixup (int bytemode, int sizeflag)
16533 /* Add proper suffix to "crc32". */
16534 char *p = mnemonicendp;
16553 if (sizeflag & DFLAG)
16557 used_prefixes |= (prefixes & PREFIX_DATA);
16561 oappend (INTERNAL_DISASSEMBLER_ERROR);
16568 if (modrm.mod == 3)
16572 /* Skip mod/rm byte. */
16577 add = (rex & REX_B) ? 8 : 0;
16578 if (bytemode == b_mode)
16582 oappend (names8rex[modrm.rm + add]);
16584 oappend (names8[modrm.rm + add]);
16590 oappend (names64[modrm.rm + add]);
16591 else if ((prefixes & PREFIX_DATA))
16592 oappend (names16[modrm.rm + add]);
16594 oappend (names32[modrm.rm + add]);
16598 OP_E (bytemode, sizeflag);
16602 FXSAVE_Fixup (int bytemode, int sizeflag)
16604 /* Add proper suffix to "fxsave" and "fxrstor". */
16608 char *p = mnemonicendp;
16614 OP_M (bytemode, sizeflag);
16617 /* Display the destination register operand for instructions with
16621 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16624 const char **names;
16632 reg = vex.register_specifier;
16639 if (bytemode == vex_scalar_mode)
16641 oappend (names_xmm[reg]);
16645 switch (vex.length)
16652 case vex_vsib_q_w_dq_mode:
16653 case vex_vsib_q_w_d_mode:
16664 names = names_mask;
16678 case vex_vsib_q_w_dq_mode:
16679 case vex_vsib_q_w_d_mode:
16680 names = vex.w ? names_ymm : names_xmm;
16684 names = names_mask;
16698 oappend (names[reg]);
16701 /* Get the VEX immediate byte without moving codep. */
16703 static unsigned char
16704 get_vex_imm8 (int sizeflag, int opnum)
16706 int bytes_before_imm = 0;
16708 if (modrm.mod != 3)
16710 /* There are SIB/displacement bytes. */
16711 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16713 /* 32/64 bit address mode */
16714 int base = modrm.rm;
16716 /* Check SIB byte. */
16719 FETCH_DATA (the_info, codep + 1);
16721 /* When decoding the third source, don't increase
16722 bytes_before_imm as this has already been incremented
16723 by one in OP_E_memory while decoding the second
16726 bytes_before_imm++;
16729 /* Don't increase bytes_before_imm when decoding the third source,
16730 it has already been incremented by OP_E_memory while decoding
16731 the second source operand. */
16737 /* When modrm.rm == 5 or modrm.rm == 4 and base in
16738 SIB == 5, there is a 4 byte displacement. */
16740 /* No displacement. */
16743 /* 4 byte displacement. */
16744 bytes_before_imm += 4;
16747 /* 1 byte displacement. */
16748 bytes_before_imm++;
16755 /* 16 bit address mode */
16756 /* Don't increase bytes_before_imm when decoding the third source,
16757 it has already been incremented by OP_E_memory while decoding
16758 the second source operand. */
16764 /* When modrm.rm == 6, there is a 2 byte displacement. */
16766 /* No displacement. */
16769 /* 2 byte displacement. */
16770 bytes_before_imm += 2;
16773 /* 1 byte displacement: when decoding the third source,
16774 don't increase bytes_before_imm as this has already
16775 been incremented by one in OP_E_memory while decoding
16776 the second source operand. */
16778 bytes_before_imm++;
16786 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16787 return codep [bytes_before_imm];
16791 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16793 const char **names;
16795 if (reg == -1 && modrm.mod != 3)
16797 OP_E_memory (bytemode, sizeflag);
16809 else if (reg > 7 && address_mode != mode_64bit)
16813 switch (vex.length)
16824 oappend (names[reg]);
16828 OP_EX_VexImmW (int bytemode, int sizeflag)
16831 static unsigned char vex_imm8;
16833 if (vex_w_done == 0)
16837 /* Skip mod/rm byte. */
16841 vex_imm8 = get_vex_imm8 (sizeflag, 0);
16844 reg = vex_imm8 >> 4;
16846 OP_EX_VexReg (bytemode, sizeflag, reg);
16848 else if (vex_w_done == 1)
16853 reg = vex_imm8 >> 4;
16855 OP_EX_VexReg (bytemode, sizeflag, reg);
16859 /* Output the imm8 directly. */
16860 scratchbuf[0] = '$';
16861 print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16862 oappend_maybe_intel (scratchbuf);
16863 scratchbuf[0] = '\0';
16869 OP_Vex_2src (int bytemode, int sizeflag)
16871 if (modrm.mod == 3)
16873 int reg = modrm.rm;
16877 oappend (names_xmm[reg]);
16882 && (bytemode == v_mode || bytemode == v_swap_mode))
16884 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16885 used_prefixes |= (prefixes & PREFIX_DATA);
16887 OP_E (bytemode, sizeflag);
16892 OP_Vex_2src_1 (int bytemode, int sizeflag)
16894 if (modrm.mod == 3)
16896 /* Skip mod/rm byte. */
16902 oappend (names_xmm[vex.register_specifier]);
16904 OP_Vex_2src (bytemode, sizeflag);
16908 OP_Vex_2src_2 (int bytemode, int sizeflag)
16911 OP_Vex_2src (bytemode, sizeflag);
16913 oappend (names_xmm[vex.register_specifier]);
16917 OP_EX_VexW (int bytemode, int sizeflag)
16925 /* Skip mod/rm byte. */
16930 reg = get_vex_imm8 (sizeflag, 0) >> 4;
16935 reg = get_vex_imm8 (sizeflag, 1) >> 4;
16938 OP_EX_VexReg (bytemode, sizeflag, reg);
16942 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
16943 int sizeflag ATTRIBUTE_UNUSED)
16945 /* Skip the immediate byte and check for invalid bits. */
16946 FETCH_DATA (the_info, codep + 1);
16947 if (*codep++ & 0xf)
16952 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16955 const char **names;
16957 FETCH_DATA (the_info, codep + 1);
16960 if (bytemode != x_mode)
16967 if (reg > 7 && address_mode != mode_64bit)
16970 switch (vex.length)
16981 oappend (names[reg]);
16985 OP_XMM_VexW (int bytemode, int sizeflag)
16987 /* Turn off the REX.W bit since it is used for swapping operands
16990 OP_XMM (bytemode, sizeflag);
16994 OP_EX_Vex (int bytemode, int sizeflag)
16996 if (modrm.mod != 3)
16998 if (vex.register_specifier != 0)
17002 OP_EX (bytemode, sizeflag);
17006 OP_XMM_Vex (int bytemode, int sizeflag)
17008 if (modrm.mod != 3)
17010 if (vex.register_specifier != 0)
17014 OP_XMM (bytemode, sizeflag);
17018 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17020 switch (vex.length)
17023 mnemonicendp = stpcpy (obuf, "vzeroupper");
17026 mnemonicendp = stpcpy (obuf, "vzeroall");
17033 static struct op vex_cmp_op[] =
17035 { STRING_COMMA_LEN ("eq") },
17036 { STRING_COMMA_LEN ("lt") },
17037 { STRING_COMMA_LEN ("le") },
17038 { STRING_COMMA_LEN ("unord") },
17039 { STRING_COMMA_LEN ("neq") },
17040 { STRING_COMMA_LEN ("nlt") },
17041 { STRING_COMMA_LEN ("nle") },
17042 { STRING_COMMA_LEN ("ord") },
17043 { STRING_COMMA_LEN ("eq_uq") },
17044 { STRING_COMMA_LEN ("nge") },
17045 { STRING_COMMA_LEN ("ngt") },
17046 { STRING_COMMA_LEN ("false") },
17047 { STRING_COMMA_LEN ("neq_oq") },
17048 { STRING_COMMA_LEN ("ge") },
17049 { STRING_COMMA_LEN ("gt") },
17050 { STRING_COMMA_LEN ("true") },
17051 { STRING_COMMA_LEN ("eq_os") },
17052 { STRING_COMMA_LEN ("lt_oq") },
17053 { STRING_COMMA_LEN ("le_oq") },
17054 { STRING_COMMA_LEN ("unord_s") },
17055 { STRING_COMMA_LEN ("neq_us") },
17056 { STRING_COMMA_LEN ("nlt_uq") },
17057 { STRING_COMMA_LEN ("nle_uq") },
17058 { STRING_COMMA_LEN ("ord_s") },
17059 { STRING_COMMA_LEN ("eq_us") },
17060 { STRING_COMMA_LEN ("nge_uq") },
17061 { STRING_COMMA_LEN ("ngt_uq") },
17062 { STRING_COMMA_LEN ("false_os") },
17063 { STRING_COMMA_LEN ("neq_os") },
17064 { STRING_COMMA_LEN ("ge_oq") },
17065 { STRING_COMMA_LEN ("gt_oq") },
17066 { STRING_COMMA_LEN ("true_us") },
17070 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17072 unsigned int cmp_type;
17074 FETCH_DATA (the_info, codep + 1);
17075 cmp_type = *codep++ & 0xff;
17076 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17079 char *p = mnemonicendp - 2;
17083 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17084 mnemonicendp += vex_cmp_op[cmp_type].len;
17088 /* We have a reserved extension byte. Output it directly. */
17089 scratchbuf[0] = '$';
17090 print_operand_value (scratchbuf + 1, 1, cmp_type);
17091 oappend_maybe_intel (scratchbuf);
17092 scratchbuf[0] = '\0';
17097 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17098 int sizeflag ATTRIBUTE_UNUSED)
17100 unsigned int cmp_type;
17105 FETCH_DATA (the_info, codep + 1);
17106 cmp_type = *codep++ & 0xff;
17107 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17108 If it's the case, print suffix, otherwise - print the immediate. */
17109 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17114 char *p = mnemonicendp - 2;
17116 /* vpcmp* can have both one- and two-lettered suffix. */
17130 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17131 mnemonicendp += simd_cmp_op[cmp_type].len;
17135 /* We have a reserved extension byte. Output it directly. */
17136 scratchbuf[0] = '$';
17137 print_operand_value (scratchbuf + 1, 1, cmp_type);
17138 oappend_maybe_intel (scratchbuf);
17139 scratchbuf[0] = '\0';
17143 static const struct op pclmul_op[] =
17145 { STRING_COMMA_LEN ("lql") },
17146 { STRING_COMMA_LEN ("hql") },
17147 { STRING_COMMA_LEN ("lqh") },
17148 { STRING_COMMA_LEN ("hqh") }
17152 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17153 int sizeflag ATTRIBUTE_UNUSED)
17155 unsigned int pclmul_type;
17157 FETCH_DATA (the_info, codep + 1);
17158 pclmul_type = *codep++ & 0xff;
17159 switch (pclmul_type)
17170 if (pclmul_type < ARRAY_SIZE (pclmul_op))
17173 char *p = mnemonicendp - 3;
17178 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17179 mnemonicendp += pclmul_op[pclmul_type].len;
17183 /* We have a reserved extension byte. Output it directly. */
17184 scratchbuf[0] = '$';
17185 print_operand_value (scratchbuf + 1, 1, pclmul_type);
17186 oappend_maybe_intel (scratchbuf);
17187 scratchbuf[0] = '\0';
17192 MOVBE_Fixup (int bytemode, int sizeflag)
17194 /* Add proper suffix to "movbe". */
17195 char *p = mnemonicendp;
17204 if (sizeflag & SUFFIX_ALWAYS)
17210 if (sizeflag & DFLAG)
17214 used_prefixes |= (prefixes & PREFIX_DATA);
17219 oappend (INTERNAL_DISASSEMBLER_ERROR);
17226 OP_M (bytemode, sizeflag);
17230 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17233 const char **names;
17235 /* Skip mod/rm byte. */
17249 oappend (names[reg]);
17253 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17255 const char **names;
17262 oappend (names[vex.register_specifier]);
17266 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17269 || (bytemode != mask_mode && bytemode != mask_bd_mode))
17273 if ((rex & REX_R) != 0 || !vex.r)
17279 oappend (names_mask [modrm.reg]);
17283 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17286 || (bytemode != evex_rounding_mode
17287 && bytemode != evex_sae_mode))
17289 if (modrm.mod == 3 && vex.b)
17292 case evex_rounding_mode:
17293 oappend (names_rounding[vex.ll]);
17295 case evex_sae_mode: