2 * Copyright (c) 1995, David Greenman
3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.110.2.30 2003/06/12 16:47:05 mux Exp $
29 * $DragonFly: src/sys/dev/netif/fxp/if_fxp.c,v 1.14 2004/07/23 07:16:26 joerg Exp $
33 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
36 #include <sys/param.h>
37 #include <sys/systm.h>
39 #include <sys/malloc.h>
40 /* #include <sys/mutex.h> */
41 #include <sys/kernel.h>
42 #include <sys/socket.h>
43 #include <sys/sysctl.h>
46 #include <net/if_dl.h>
47 #include <net/if_media.h>
51 #include <netns/ns_if.h>
55 #include <sys/sockio.h>
57 #include <machine/bus.h>
59 #include <machine/resource.h>
61 #include <net/ethernet.h>
62 #include <net/if_arp.h>
64 #include <vm/vm.h> /* for vtophys */
65 #include <vm/pmap.h> /* for vtophys */
66 #include <machine/clock.h> /* for DELAY */
68 #include <net/if_types.h>
69 #include <net/vlan/if_vlan_var.h>
71 #include <bus/pci/pcivar.h>
72 #include <bus/pci/pcireg.h> /* for PCIM_CMD_xxx */
74 #include "../mii_layer/mii.h"
75 #include "../mii_layer/miivar.h"
77 #include "if_fxpreg.h"
78 #include "if_fxpvar.h"
81 #include "miibus_if.h"
84 * NOTE! On the Alpha, we have an alignment constraint. The
85 * card DMAs the packet immediately following the RFA. However,
86 * the first thing in the packet is a 14-byte Ethernet header.
87 * This means that the packet is misaligned. To compensate,
88 * we actually offset the RFA 2 bytes into the cluster. This
89 * alignes the packet after the Ethernet header at a 32-bit
90 * boundary. HOWEVER! This means that the RFA is misaligned!
92 #define RFA_ALIGNMENT_FUDGE 2
95 * Set initial transmit threshold at 64 (512 bytes). This is
96 * increased by 64 (512 bytes) at a time, to maximum of 192
97 * (1536 bytes), if an underrun occurs.
99 static int tx_threshold = 64;
102 * The configuration byte map has several undefined fields which
103 * must be one or must be zero. Set up a template for these bits
104 * only, (assuming a 82557 chip) leaving the actual configuration
107 * See struct fxp_cb_config for the bit definitions.
109 static u_char fxp_cb_config_template[] = {
110 0x0, 0x0, /* cb_status */
111 0x0, 0x0, /* cb_command */
112 0x0, 0x0, 0x0, 0x0, /* link_addr */
139 int16_t revid; /* -1 matches anything */
144 * Claim various Intel PCI device identifiers for this driver. The
145 * sub-vendor and sub-device field are extensively used to identify
146 * particular variants, but we don't currently differentiate between
149 static struct fxp_ident fxp_ident_table[] = {
150 { 0x1029, -1, "Intel 82559 PCI/CardBus Pro/100" },
151 { 0x1030, -1, "Intel 82559 Pro/100 Ethernet" },
152 { 0x1031, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
153 { 0x1032, -1, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
154 { 0x1033, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
155 { 0x1034, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
156 { 0x1035, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
157 { 0x1036, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
158 { 0x1037, -1, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
159 { 0x1038, -1, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
160 { 0x1039, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
161 { 0x103A, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
162 { 0x103B, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
163 { 0x103C, -1, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
164 { 0x103D, -1, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
165 { 0x103E, -1, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
166 { 0x1050, -1, "Intel 82801BA (D865) Pro/100 VE Ethernet" },
167 { 0x1059, -1, "Intel 82551QM Pro/100 M Mobile Connection" },
168 { 0x1209, -1, "Intel 82559ER Embedded 10/100 Ethernet" },
169 { 0x1229, 0x01, "Intel 82557 Pro/100 Ethernet" },
170 { 0x1229, 0x02, "Intel 82557 Pro/100 Ethernet" },
171 { 0x1229, 0x03, "Intel 82557 Pro/100 Ethernet" },
172 { 0x1229, 0x04, "Intel 82558 Pro/100 Ethernet" },
173 { 0x1229, 0x05, "Intel 82558 Pro/100 Ethernet" },
174 { 0x1229, 0x06, "Intel 82559 Pro/100 Ethernet" },
175 { 0x1229, 0x07, "Intel 82559 Pro/100 Ethernet" },
176 { 0x1229, 0x08, "Intel 82559 Pro/100 Ethernet" },
177 { 0x1229, 0x09, "Intel 82559ER Pro/100 Ethernet" },
178 { 0x1229, 0x0c, "Intel 82550 Pro/100 Ethernet" },
179 { 0x1229, 0x0d, "Intel 82550 Pro/100 Ethernet" },
180 { 0x1229, 0x0e, "Intel 82550 Pro/100 Ethernet" },
181 { 0x1229, 0x0f, "Intel 82551 Pro/100 Ethernet" },
182 { 0x1229, 0x10, "Intel 82551 Pro/100 Ethernet" },
183 { 0x1229, -1, "Intel 82557/8/9 Pro/100 Ethernet" },
184 { 0x2449, -1, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" },
188 static int fxp_probe(device_t dev);
189 static int fxp_attach(device_t dev);
190 static int fxp_detach(device_t dev);
191 static int fxp_shutdown(device_t dev);
192 static int fxp_suspend(device_t dev);
193 static int fxp_resume(device_t dev);
195 static void fxp_intr(void *xsc);
196 static void fxp_intr_body(struct fxp_softc *sc,
197 u_int8_t statack, int count);
199 static void fxp_init(void *xsc);
200 static void fxp_tick(void *xsc);
201 static void fxp_powerstate_d0(device_t dev);
202 static void fxp_start(struct ifnet *ifp);
203 static void fxp_stop(struct fxp_softc *sc);
204 static void fxp_release(struct fxp_softc *sc);
205 static int fxp_ioctl(struct ifnet *ifp, u_long command,
206 caddr_t data, struct ucred *);
207 static void fxp_watchdog(struct ifnet *ifp);
208 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm);
209 static int fxp_mc_addrs(struct fxp_softc *sc);
210 static void fxp_mc_setup(struct fxp_softc *sc);
211 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset,
213 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset,
215 static void fxp_autosize_eeprom(struct fxp_softc *sc);
216 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data,
217 int offset, int words);
218 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data,
219 int offset, int words);
220 static int fxp_ifmedia_upd(struct ifnet *ifp);
221 static void fxp_ifmedia_sts(struct ifnet *ifp,
222 struct ifmediareq *ifmr);
223 static int fxp_serial_ifmedia_upd(struct ifnet *ifp);
224 static void fxp_serial_ifmedia_sts(struct ifnet *ifp,
225 struct ifmediareq *ifmr);
226 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg);
227 static void fxp_miibus_writereg(device_t dev, int phy, int reg,
229 static void fxp_load_ucode(struct fxp_softc *sc);
230 static int sysctl_int_range(SYSCTL_HANDLER_ARGS,
232 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS);
233 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS);
234 static __inline void fxp_lwcopy(volatile u_int32_t *src,
235 volatile u_int32_t *dst);
236 static __inline void fxp_scb_wait(struct fxp_softc *sc);
237 static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd);
238 static __inline void fxp_dma_wait(volatile u_int16_t *status,
239 struct fxp_softc *sc);
241 static device_method_t fxp_methods[] = {
242 /* Device interface */
243 DEVMETHOD(device_probe, fxp_probe),
244 DEVMETHOD(device_attach, fxp_attach),
245 DEVMETHOD(device_detach, fxp_detach),
246 DEVMETHOD(device_shutdown, fxp_shutdown),
247 DEVMETHOD(device_suspend, fxp_suspend),
248 DEVMETHOD(device_resume, fxp_resume),
251 DEVMETHOD(miibus_readreg, fxp_miibus_readreg),
252 DEVMETHOD(miibus_writereg, fxp_miibus_writereg),
257 static driver_t fxp_driver = {
260 sizeof(struct fxp_softc),
263 static devclass_t fxp_devclass;
265 DECLARE_DUMMY_MODULE(if_fxp);
266 MODULE_DEPEND(if_fxp, miibus, 1, 1, 1);
267 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0);
268 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0);
269 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0);
272 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events");
275 * Inline function to copy a 16-bit aligned 32-bit quantity.
278 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst)
283 volatile u_int16_t *a = (volatile u_int16_t *)src;
284 volatile u_int16_t *b = (volatile u_int16_t *)dst;
292 * Wait for the previous command to be accepted (but not necessarily
296 fxp_scb_wait(struct fxp_softc *sc)
300 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
303 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
304 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
305 CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
306 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS),
307 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL));
311 fxp_scb_cmd(struct fxp_softc *sc, int cmd)
314 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
315 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
318 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
322 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc)
326 while (!(*status & FXP_CB_STATUS_C) && --i)
329 device_printf(sc->dev, "DMA timeout\n");
333 * Return identification string if this is device is ours.
336 fxp_probe(device_t dev)
340 struct fxp_ident *ident;
342 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) {
343 devid = pci_get_device(dev);
344 revid = pci_get_revid(dev);
345 for (ident = fxp_ident_table; ident->name != NULL; ident++) {
346 if (ident->devid == devid &&
347 (ident->revid == revid || ident->revid == -1)) {
348 device_set_desc(dev, ident->name);
357 fxp_powerstate_d0(device_t dev)
359 #if defined(__DragonFly__) || __FreeBSD_version >= 430002
360 u_int32_t iobase, membase, irq;
362 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
363 /* Save important PCI config data. */
364 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4);
365 membase = pci_read_config(dev, FXP_PCI_MMBA, 4);
366 irq = pci_read_config(dev, PCIR_INTLINE, 4);
368 /* Reset the power state. */
369 device_printf(dev, "chip is in D%d power mode "
370 "-- setting to D0\n", pci_get_powerstate(dev));
372 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
374 /* Restore PCI config data. */
375 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4);
376 pci_write_config(dev, FXP_PCI_MMBA, membase, 4);
377 pci_write_config(dev, PCIR_INTLINE, irq, 4);
383 fxp_attach(device_t dev)
386 struct fxp_softc *sc = device_get_softc(dev);
390 int i, rid, m1, m2, prefer_iomap;
393 bzero(sc, sizeof(*sc));
395 callout_handle_init(&sc->stat_ch);
396 sysctl_ctx_init(&sc->sysctl_ctx);
397 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE);
402 * Enable bus mastering. Enable memory space too, in case
403 * BIOS/Prom forgot about it.
405 val = pci_read_config(dev, PCIR_COMMAND, 2);
406 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
407 pci_write_config(dev, PCIR_COMMAND, val, 2);
408 val = pci_read_config(dev, PCIR_COMMAND, 2);
410 fxp_powerstate_d0(dev);
413 * Figure out which we should try first - memory mapping or i/o mapping?
414 * We default to memory mapping. Then we accept an override from the
415 * command line. Then we check to see which one is enabled.
418 m2 = PCIM_CMD_PORTEN;
420 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
421 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) {
422 m1 = PCIM_CMD_PORTEN;
428 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
429 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
430 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd,
431 0, ~0, 1, RF_ACTIVE);
433 if (sc->mem == NULL && (val & m2)) {
435 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
436 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
437 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd,
438 0, ~0, 1, RF_ACTIVE);
442 device_printf(dev, "could not map device registers\n");
447 device_printf(dev, "using %s space register mapping\n",
448 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O");
451 sc->sc_st = rman_get_bustag(sc->mem);
452 sc->sc_sh = rman_get_bushandle(sc->mem);
455 * Allocate our interrupt.
458 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
459 RF_SHAREABLE | RF_ACTIVE);
460 if (sc->irq == NULL) {
461 device_printf(dev, "could not map interrupt\n");
466 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET,
467 fxp_intr, sc, &sc->ih);
469 device_printf(dev, "could not setup irq\n");
474 * Reset to a stable state.
476 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
479 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB,
480 M_DEVBUF, M_WAITOK | M_ZERO);
482 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF,
485 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_WAITOK);
488 * Pre-allocate our receive buffers.
490 for (i = 0; i < FXP_NRFABUFS; i++) {
491 if (fxp_add_rfabuf(sc, NULL) != 0) {
497 * Find out how large of an SEEPROM we have.
499 fxp_autosize_eeprom(sc);
502 * Determine whether we must use the 503 serial interface.
504 fxp_read_eeprom(sc, &data, 6, 1);
505 if ((data & FXP_PHY_DEVICE_MASK) != 0 &&
506 (data & FXP_PHY_SERIAL_ONLY))
507 sc->flags |= FXP_FLAG_SERIAL_MEDIA;
510 * Create the sysctl tree
512 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
513 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
514 device_get_nameunit(dev), CTLFLAG_RD, 0, "");
515 if (sc->sysctl_tree == NULL)
517 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
518 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON,
519 &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I",
520 "FXP driver receive interrupt microcode bundling delay");
521 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
522 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON,
523 &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I",
524 "FXP driver receive interrupt microcode bundle size limit");
527 * Pull in device tunables.
529 sc->tunable_int_delay = TUNABLE_INT_DELAY;
530 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX;
531 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
532 "int_delay", &sc->tunable_int_delay);
533 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
534 "bundle_max", &sc->tunable_bundle_max);
537 * Find out the chip revision; lump all 82557 revs together.
539 fxp_read_eeprom(sc, &data, 5, 1);
540 if ((data >> 8) == 1)
541 sc->revision = FXP_REV_82557;
543 sc->revision = pci_get_revid(dev);
546 * Enable workarounds for certain chip revision deficiencies.
548 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly
549 * some systems based a normal 82559 design, have a defect where
550 * the chip can cause a PCI protocol violation if it receives
551 * a CU_RESUME command when it is entering the IDLE state. The
552 * workaround is to disable Dynamic Standby Mode, so the chip never
553 * deasserts CLKRUN#, and always remains in an active state.
555 * See Intel 82801BA/82801BAM Specification Update, Errata #30.
557 i = pci_get_device(dev);
558 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) ||
559 sc->revision >= FXP_REV_82559_A0) {
560 fxp_read_eeprom(sc, &data, 10, 1);
561 if (data & 0x02) { /* STB enable */
566 "Disabling dynamic standby mode in EEPROM\n");
568 fxp_write_eeprom(sc, &data, 10, 1);
569 device_printf(dev, "New EEPROM ID: 0x%x\n", data);
571 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) {
572 fxp_read_eeprom(sc, &data, i, 1);
575 i = (1 << sc->eeprom_size) - 1;
576 cksum = 0xBABA - cksum;
577 fxp_read_eeprom(sc, &data, i, 1);
578 fxp_write_eeprom(sc, &cksum, i, 1);
580 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
584 * If the user elects to continue, try the software
585 * workaround, as it is better than nothing.
587 sc->flags |= FXP_FLAG_CU_RESUME_BUG;
593 * If we are not a 82557 chip, we can enable extended features.
595 if (sc->revision != FXP_REV_82557) {
597 * If MWI is enabled in the PCI configuration, and there
598 * is a valid cacheline size (8 or 16 dwords), then tell
599 * the board to turn on MWI.
601 if (val & PCIM_CMD_MWRICEN &&
602 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
603 sc->flags |= FXP_FLAG_MWI_ENABLE;
605 /* turn on the extended TxCB feature */
606 sc->flags |= FXP_FLAG_EXT_TXCB;
608 /* enable reception of long frames for VLAN */
609 sc->flags |= FXP_FLAG_LONG_PKT_EN;
615 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3);
616 if (sc->flags & FXP_FLAG_SERIAL_MEDIA)
617 device_printf(dev, "10Mbps");
619 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n",
620 pci_get_vendor(dev), pci_get_device(dev),
621 pci_get_subvendor(dev), pci_get_subdevice(dev),
623 fxp_read_eeprom(sc, &data, 10, 1);
624 device_printf(dev, "Dynamic Standby mode is %s\n",
625 data & 0x02 ? "enabled" : "disabled");
629 * If this is only a 10Mbps device, then there is no MII, and
630 * the PHY will use a serial interface instead.
632 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
633 * doesn't have a programming interface of any sort. The
634 * media is sensed automatically based on how the link partner
635 * is configured. This is, in essence, manual configuration.
637 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
638 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
639 fxp_serial_ifmedia_sts);
640 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
641 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
643 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd,
645 device_printf(dev, "MII without any PHY!\n");
651 ifp = &sc->arpcom.ac_if;
652 if_initname(ifp, "fxp", device_get_unit(dev));
653 ifp->if_baudrate = 100000000;
654 ifp->if_init = fxp_init;
656 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
657 ifp->if_ioctl = fxp_ioctl;
658 ifp->if_start = fxp_start;
659 ifp->if_watchdog = fxp_watchdog;
662 * Attach the interface.
664 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
667 * Tell the upper layer(s) we support long frames.
669 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
672 * Let the system queue as many packets as we have available
675 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1;
681 device_printf(dev, "Failed to malloc memory\n");
690 * release all resources
693 fxp_release(struct fxp_softc *sc)
696 bus_generic_detach(sc->dev);
698 device_delete_child(sc->dev, sc->miibus);
701 free(sc->cbl_base, M_DEVBUF);
703 free(sc->fxp_stats, M_DEVBUF);
705 free(sc->mcsp, M_DEVBUF);
707 m_freem(sc->rfa_headm);
710 bus_teardown_intr(sc->dev, sc->irq, sc->ih);
712 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq);
714 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem);
716 sysctl_ctx_free(&sc->sysctl_ctx);
718 mtx_destroy(&sc->sc_mtx);
725 fxp_detach(device_t dev)
727 struct fxp_softc *sc = device_get_softc(dev);
730 /* disable interrupts */
731 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
736 * Stop DMA and drop transmit queue.
741 * Close down routes etc.
743 ether_ifdetach(&sc->arpcom.ac_if);
746 * Free all media structures.
748 ifmedia_removeall(&sc->sc_media);
752 /* Release our allocated resources. */
759 * Device shutdown routine. Called at system shutdown after sync. The
760 * main purpose of this routine is to shut off receiver DMA so that
761 * kernel memory doesn't get clobbered during warmboot.
764 fxp_shutdown(device_t dev)
767 * Make sure that DMA is disabled prior to reboot. Not doing
768 * do could allow DMA to corrupt kernel memory during the
769 * reboot before the driver initializes.
771 fxp_stop((struct fxp_softc *) device_get_softc(dev));
776 * Device suspend routine. Stop the interface and save some PCI
777 * settings in case the BIOS doesn't restore them properly on
781 fxp_suspend(device_t dev)
783 struct fxp_softc *sc = device_get_softc(dev);
790 for (i = 0; i < 5; i++)
791 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
792 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
793 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
794 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
795 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
804 * Device resume routine. Restore some PCI settings in case the BIOS
805 * doesn't, re-enable busmastering, and restart the interface if
809 fxp_resume(device_t dev)
811 struct fxp_softc *sc = device_get_softc(dev);
812 struct ifnet *ifp = &sc->sc_if;
813 u_int16_t pci_command;
818 fxp_powerstate_d0(dev);
820 /* better way to do this? */
821 for (i = 0; i < 5; i++)
822 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
823 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
824 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
825 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
826 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
828 /* reenable busmastering */
829 pci_command = pci_read_config(dev, PCIR_COMMAND, 2);
830 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
831 pci_write_config(dev, PCIR_COMMAND, pci_command, 2);
833 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
836 /* reinitialize interface if necessary */
837 if (ifp->if_flags & IFF_UP)
847 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
855 for (x = 1 << (length - 1); x; x >>= 1) {
857 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
859 reg = FXP_EEPROM_EECS;
860 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
862 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
864 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
870 * Read from the serial EEPROM. Basically, you manually shift in
871 * the read opcode (one bit at a time) and then shift in the address,
872 * and then you shift out the data (all of this one bit at a time).
873 * The word size is 16 bits, so you have to provide the address for
874 * every 16 bits of data.
877 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
882 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
884 * Shift in read opcode.
886 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
891 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
893 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
895 reg = FXP_EEPROM_EECS;
896 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
898 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
900 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
902 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
904 if (autosize && reg == 0) {
905 sc->eeprom_size = data;
913 reg = FXP_EEPROM_EECS;
914 for (x = 1 << 15; x; x >>= 1) {
915 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
917 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
919 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
922 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
929 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data)
934 * Erase/write enable.
936 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
937 fxp_eeprom_shiftin(sc, 0x4, 3);
938 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
939 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
942 * Shift in write opcode, address, data.
944 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
945 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
946 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
947 fxp_eeprom_shiftin(sc, data, 16);
948 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
951 * Wait for EEPROM to finish up.
953 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
955 for (i = 0; i < 1000; i++) {
956 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
960 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
963 * Erase/write disable.
965 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
966 fxp_eeprom_shiftin(sc, 0x4, 3);
967 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
968 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
975 * Figure out EEPROM size.
977 * 559's can have either 64-word or 256-word EEPROMs, the 558
978 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
979 * talks about the existance of 16 to 256 word EEPROMs.
981 * The only known sizes are 64 and 256, where the 256 version is used
982 * by CardBus cards to store CIS information.
984 * The address is shifted in msb-to-lsb, and after the last
985 * address-bit the EEPROM is supposed to output a `dummy zero' bit,
986 * after which follows the actual data. We try to detect this zero, by
987 * probing the data-out bit in the EEPROM control register just after
988 * having shifted in a bit. If the bit is zero, we assume we've
989 * shifted enough address bits. The data-out should be tri-state,
990 * before this, which should translate to a logical one.
993 fxp_autosize_eeprom(struct fxp_softc *sc)
996 /* guess maximum size of 256 words */
1000 (void) fxp_eeprom_getword(sc, 0, 1);
1004 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1008 for (i = 0; i < words; i++)
1009 data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1013 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1017 for (i = 0; i < words; i++)
1018 fxp_eeprom_putword(sc, offset + i, data[i]);
1022 * Start packet transmission on the interface.
1025 fxp_start(struct ifnet *ifp)
1027 struct fxp_softc *sc = ifp->if_softc;
1028 struct fxp_cb_tx *txp;
1031 * See if we need to suspend xmit until the multicast filter
1032 * has been reprogrammed (which can only be done at the head
1033 * of the command chain).
1035 if (sc->need_mcsetup) {
1042 * We're finished if there is nothing more to add to the list or if
1043 * we're all filled up with buffers to transmit.
1044 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1045 * a NOP command when needed.
1047 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) {
1048 struct mbuf *m, *mb_head;
1052 * Grab a packet to transmit.
1054 IF_DEQUEUE(&ifp->if_snd, mb_head);
1057 * Get pointer to next available tx desc.
1059 txp = sc->cbl_last->next;
1062 * Go through each of the mbufs in the chain and initialize
1063 * the transmit buffer descriptors with the physical address
1064 * and size of the mbuf.
1067 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) {
1068 if (m->m_len != 0) {
1069 if (segment == FXP_NTXSEG)
1071 txp->tbd[segment].tb_addr =
1072 vtophys(mtod(m, vm_offset_t));
1073 txp->tbd[segment].tb_size = m->m_len;
1081 * We ran out of segments. We have to recopy this
1082 * mbuf chain first. Bail out if we can't get the
1085 MGETHDR(mn, MB_DONTWAIT, MT_DATA);
1090 if (mb_head->m_pkthdr.len > MHLEN) {
1091 MCLGET(mn, MB_DONTWAIT);
1092 if ((mn->m_flags & M_EXT) == 0) {
1098 m_copydata(mb_head, 0, mb_head->m_pkthdr.len,
1100 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len;
1106 txp->tbd_number = segment;
1107 txp->mb_head = mb_head;
1109 if (sc->tx_queued != FXP_CXINT_THRESH - 1) {
1111 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF |
1115 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF |
1116 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
1118 * Set a 5 second timer just in case we don't hear
1119 * from the card again.
1123 txp->tx_threshold = tx_threshold;
1126 * Advance the end of list forward.
1131 * On platforms which can't access memory in 16-bit
1132 * granularities, we must prevent the card from DMA'ing
1133 * up the status while we update the command field.
1134 * This could cause us to overwrite the completion status.
1136 atomic_clear_short(&sc->cbl_last->cb_command,
1139 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
1140 #endif /*__alpha__*/
1144 * Advance the beginning of the list forward if there are
1145 * no other packets queued (when nothing is queued, cbl_first
1146 * sits on the last TxCB that was sent out).
1148 if (sc->tx_queued == 0)
1149 sc->cbl_first = txp;
1154 * Pass packet to bpf if there is a listener.
1157 bpf_mtap(ifp, mb_head);
1161 * We're finished. If we added to the list, issue a RESUME to get DMA
1162 * going again if suspended.
1166 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1170 #ifdef DEVICE_POLLING
1171 static poll_handler_t fxp_poll;
1174 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1176 struct fxp_softc *sc = ifp->if_softc;
1179 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1180 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1183 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA |
1185 if (cmd == POLL_AND_CHECK_STATUS) {
1188 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1189 if (tmp == 0xff || tmp == 0)
1190 return; /* nothing to do */
1192 /* ack what we can */
1194 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
1197 fxp_intr_body(sc, statack, count);
1199 #endif /* DEVICE_POLLING */
1202 * Process interface interrupts.
1207 struct fxp_softc *sc = xsc;
1210 #ifdef DEVICE_POLLING
1211 struct ifnet *ifp = &sc->sc_if;
1213 if (ifp->if_flags & IFF_POLLING)
1215 if (ether_poll_register(fxp_poll, ifp)) {
1216 /* disable interrupts */
1217 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1218 fxp_poll(ifp, 0, 1);
1223 if (sc->suspended) {
1227 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1229 * It should not be possible to have all bits set; the
1230 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If
1231 * all bits are set, this may indicate that the card has
1232 * been physically ejected, so ignore it.
1234 if (statack == 0xff)
1238 * First ACK all the interrupts in this pass.
1240 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1241 fxp_intr_body(sc, statack, -1);
1246 fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count)
1248 struct ifnet *ifp = &sc->sc_if;
1250 struct fxp_rfa *rfa;
1251 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0;
1255 #ifdef DEVICE_POLLING
1256 /* Pick up a deferred RNR condition if `count' ran out last time. */
1257 if (sc->flags & FXP_FLAG_DEFERRED_RNR) {
1258 sc->flags &= ~FXP_FLAG_DEFERRED_RNR;
1264 * Free any finished transmit mbuf chains.
1266 * Handle the CNA event likt a CXTNO event. It used to
1267 * be that this event (control unit not ready) was not
1268 * encountered, but it is now with the SMPng modifications.
1269 * The exact sequence of events that occur when the interface
1270 * is brought up are different now, and if this event
1271 * goes unhandled, the configuration/rxfilter setup sequence
1272 * can stall for several seconds. The result is that no
1273 * packets go out onto the wire for about 5 to 10 seconds
1274 * after the interface is ifconfig'ed for the first time.
1276 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) {
1277 struct fxp_cb_tx *txp;
1279 for (txp = sc->cbl_first; sc->tx_queued &&
1280 (txp->cb_status & FXP_CB_STATUS_C) != 0;
1282 if (txp->mb_head != NULL) {
1283 m_freem(txp->mb_head);
1284 txp->mb_head = NULL;
1288 sc->cbl_first = txp;
1290 if (sc->tx_queued == 0) {
1291 if (sc->need_mcsetup)
1295 * Try to start more packets transmitting.
1297 if (ifp->if_snd.ifq_head != NULL)
1302 * Just return if nothing happened on the receive side.
1304 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0)
1308 * Process receiver interrupts. If a no-resource (RNR)
1309 * condition exists, get whatever packets we can and
1310 * re-start the receiver.
1312 * When using polling, we do not process the list to completion,
1313 * so when we get an RNR interrupt we must defer the restart
1314 * until we hit the last buffer with the C bit set.
1315 * If we run out of cycles and rfa_headm has the C bit set,
1316 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so
1317 * that the info will be used in the subsequent polling cycle.
1321 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1322 RFA_ALIGNMENT_FUDGE);
1324 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */
1325 if (count >= 0 && count-- == 0) {
1327 /* Defer RNR processing until the next time. */
1328 sc->flags |= FXP_FLAG_DEFERRED_RNR;
1333 #endif /* DEVICE_POLLING */
1335 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0)
1339 * Remove first packet from the chain.
1341 sc->rfa_headm = m->m_next;
1345 * Add a new buffer to the receive chain.
1346 * If this fails, the old buffer is recycled
1349 if (fxp_add_rfabuf(sc, m) == 0) {
1353 * Fetch packet length (the top 2 bits of
1354 * actual_size are flags set by the controller
1355 * upon completion), and drop the packet in case
1356 * of bogus length or CRC errors.
1358 total_len = rfa->actual_size & 0x3fff;
1359 if (total_len < sizeof(struct ether_header) ||
1360 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE -
1361 sizeof(struct fxp_rfa) ||
1362 rfa->rfa_status & FXP_RFA_STATUS_CRC) {
1366 m->m_pkthdr.len = m->m_len = total_len;
1367 (*ifp->if_input)(ifp, m);
1372 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1373 vtophys(sc->rfa_headm->m_ext.ext_buf) +
1374 RFA_ALIGNMENT_FUDGE);
1375 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1380 * Update packet in/out/collision statistics. The i82557 doesn't
1381 * allow you to access these counters without doing a fairly
1382 * expensive DMA to get _all_ of the statistics it maintains, so
1383 * we do this operation here only once per second. The statistics
1384 * counters in the kernel are updated from the previous dump-stats
1385 * DMA and then a new dump-stats DMA is started. The on-chip
1386 * counters are zeroed when the DMA completes. If we can't start
1387 * the DMA immediately, we don't wait - we just prepare to read
1388 * them again next time.
1393 struct fxp_softc *sc = xsc;
1394 struct ifnet *ifp = &sc->sc_if;
1395 struct fxp_stats *sp = sc->fxp_stats;
1396 struct fxp_cb_tx *txp;
1399 ifp->if_opackets += sp->tx_good;
1400 ifp->if_collisions += sp->tx_total_collisions;
1402 ifp->if_ipackets += sp->rx_good;
1403 sc->rx_idle_secs = 0;
1406 * Receiver's been idle for another second.
1412 sp->rx_alignment_errors +
1414 sp->rx_overrun_errors;
1416 * If any transmit underruns occured, bump up the transmit
1417 * threshold by another 512 bytes (64 * 8).
1419 if (sp->tx_underruns) {
1420 ifp->if_oerrors += sp->tx_underruns;
1421 if (tx_threshold < 192)
1426 * Release any xmit buffers that have completed DMA. This isn't
1427 * strictly necessary to do here, but it's advantagous for mbufs
1428 * with external storage to be released in a timely manner rather
1429 * than being defered for a potentially long time. This limits
1430 * the delay to a maximum of one second.
1432 for (txp = sc->cbl_first; sc->tx_queued &&
1433 (txp->cb_status & FXP_CB_STATUS_C) != 0;
1435 if (txp->mb_head != NULL) {
1436 m_freem(txp->mb_head);
1437 txp->mb_head = NULL;
1441 sc->cbl_first = txp;
1443 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
1444 * then assume the receiver has locked up and attempt to clear
1445 * the condition by reprogramming the multicast filter. This is
1446 * a work-around for a bug in the 82557 where the receiver locks
1447 * up if it gets certain types of garbage in the syncronization
1448 * bits prior to the packet header. This bug is supposed to only
1449 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
1450 * mode as well (perhaps due to a 10/100 speed transition).
1452 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
1453 sc->rx_idle_secs = 0;
1457 * If there is no pending command, start another stats
1458 * dump. Otherwise punt for now.
1460 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
1462 * Start another stats dump.
1464 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
1467 * A previous command is still waiting to be accepted.
1468 * Just zero our copy of the stats and wait for the
1469 * next timer event to update them.
1472 sp->tx_underruns = 0;
1473 sp->tx_total_collisions = 0;
1476 sp->rx_crc_errors = 0;
1477 sp->rx_alignment_errors = 0;
1478 sp->rx_rnr_errors = 0;
1479 sp->rx_overrun_errors = 0;
1481 if (sc->miibus != NULL)
1482 mii_tick(device_get_softc(sc->miibus));
1485 * Schedule another timeout one second from now.
1487 sc->stat_ch = timeout(fxp_tick, sc, hz);
1491 * Stop the interface. Cancels the statistics updater and resets
1495 fxp_stop(struct fxp_softc *sc)
1497 struct ifnet *ifp = &sc->sc_if;
1498 struct fxp_cb_tx *txp;
1501 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1504 #ifdef DEVICE_POLLING
1505 ether_poll_deregister(ifp);
1508 * Cancel stats updater.
1510 untimeout(fxp_tick, sc, sc->stat_ch);
1513 * Issue software reset, which also unloads the microcode.
1515 sc->flags &= ~FXP_FLAG_UCODE;
1516 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
1520 * Release any xmit buffers.
1524 for (i = 0; i < FXP_NTXCB; i++) {
1525 if (txp[i].mb_head != NULL) {
1526 m_freem(txp[i].mb_head);
1527 txp[i].mb_head = NULL;
1534 * Free all the receive buffers then reallocate/reinitialize
1536 if (sc->rfa_headm != NULL)
1537 m_freem(sc->rfa_headm);
1538 sc->rfa_headm = NULL;
1539 sc->rfa_tailm = NULL;
1540 for (i = 0; i < FXP_NRFABUFS; i++) {
1541 if (fxp_add_rfabuf(sc, NULL) != 0) {
1543 * This "can't happen" - we're at splimp()
1544 * and we just freed all the buffers we need
1547 panic("fxp_stop: no buffers!");
1553 * Watchdog/transmission transmit timeout handler. Called when a
1554 * transmission is started on the interface, but no interrupt is
1555 * received before the timeout. This usually indicates that the
1556 * card has wedged for some reason.
1559 fxp_watchdog(struct ifnet *ifp)
1561 struct fxp_softc *sc = ifp->if_softc;
1563 device_printf(sc->dev, "device timeout\n");
1572 struct fxp_softc *sc = xsc;
1573 struct ifnet *ifp = &sc->sc_if;
1574 struct fxp_cb_config *cbp;
1575 struct fxp_cb_ias *cb_ias;
1576 struct fxp_cb_tx *txp;
1577 struct fxp_cb_mcs *mcsp;
1582 * Cancel any pending I/O
1586 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
1589 * Initialize base of CBL and RFA memory. Loading with zero
1590 * sets it up for regular linear addressing.
1592 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
1593 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
1596 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
1599 * Initialize base of dump-stats buffer.
1602 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats));
1603 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
1606 * Attempt to load microcode if requested.
1608 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0)
1612 * Initialize the multicast address list.
1614 if (fxp_mc_addrs(sc)) {
1616 mcsp->cb_status = 0;
1617 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL;
1618 mcsp->link_addr = -1;
1620 * Start the multicast setup command.
1623 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
1624 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1625 /* ...and wait for it to complete. */
1626 fxp_dma_wait(&mcsp->cb_status, sc);
1630 * We temporarily use memory that contains the TxCB list to
1631 * construct the config CB. The TxCB list memory is rebuilt
1634 cbp = (struct fxp_cb_config *) sc->cbl_base;
1637 * This bcopy is kind of disgusting, but there are a bunch of must be
1638 * zero and must be one bits in this structure and this is the easiest
1639 * way to initialize them all to proper values.
1641 bcopy(fxp_cb_config_template,
1642 (void *)(uintptr_t)(volatile void *)&cbp->cb_status,
1643 sizeof(fxp_cb_config_template));
1646 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL;
1647 cbp->link_addr = -1; /* (no) next command */
1648 cbp->byte_count = 22; /* (22) bytes to config */
1649 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
1650 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
1651 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
1652 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
1653 cbp->type_enable = 0; /* actually reserved */
1654 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
1655 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
1656 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
1657 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
1658 cbp->dma_mbce = 0; /* (disable) dma max counters */
1659 cbp->late_scb = 0; /* (don't) defer SCB update */
1660 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */
1661 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */
1662 cbp->ci_int = 1; /* interrupt on CU idle */
1663 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
1664 cbp->ext_stats_dis = 1; /* disable extended counters */
1665 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */
1666 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm;
1667 cbp->disc_short_rx = !prm; /* discard short packets */
1668 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */
1669 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */
1670 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */
1671 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
1672 cbp->csma_dis = 0; /* (don't) disable link */
1673 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */
1674 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */
1675 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */
1676 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */
1677 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */
1678 cbp->nsai = 1; /* (don't) disable source addr insert */
1679 cbp->preamble_length = 2; /* (7 byte) preamble */
1680 cbp->loopback = 0; /* (don't) loopback */
1681 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
1682 cbp->linear_pri_mode = 0; /* (wait after xmit only) */
1683 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
1684 cbp->promiscuous = prm; /* promiscuous mode */
1685 cbp->bcast_disable = 0; /* (don't) disable broadcasts */
1686 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/
1687 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */
1688 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */
1689 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
1691 cbp->stripping = !prm; /* truncate rx packet to byte count */
1692 cbp->padding = 1; /* (do) pad short tx packets */
1693 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
1694 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
1695 cbp->ia_wake_en = 0; /* (don't) wake up on address match */
1696 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */
1697 /* must set wake_en in PMCSR also */
1698 cbp->force_fdx = 0; /* (don't) force full duplex */
1699 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
1700 cbp->multi_ia = 0; /* (don't) accept multiple IAs */
1701 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0;
1703 if (sc->revision == FXP_REV_82557) {
1705 * The 82557 has no hardware flow control, the values
1706 * below are the defaults for the chip.
1708 cbp->fc_delay_lsb = 0;
1709 cbp->fc_delay_msb = 0x40;
1710 cbp->pri_fc_thresh = 3;
1712 cbp->rx_fc_restop = 0;
1713 cbp->rx_fc_restart = 0;
1715 cbp->pri_fc_loc = 1;
1717 cbp->fc_delay_lsb = 0x1f;
1718 cbp->fc_delay_msb = 0x01;
1719 cbp->pri_fc_thresh = 3;
1720 cbp->tx_fc_dis = 0; /* enable transmit FC */
1721 cbp->rx_fc_restop = 1; /* enable FC restop frames */
1722 cbp->rx_fc_restart = 1; /* enable FC restart frames */
1723 cbp->fc_filter = !prm; /* drop FC frames to host */
1724 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */
1728 * Start the config command/DMA.
1731 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
1732 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1733 /* ...and wait for it to complete. */
1734 fxp_dma_wait(&cbp->cb_status, sc);
1737 * Now initialize the station address. Temporarily use the TxCB
1738 * memory area like we did above for the config CB.
1740 cb_ias = (struct fxp_cb_ias *) sc->cbl_base;
1741 cb_ias->cb_status = 0;
1742 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL;
1743 cb_ias->link_addr = -1;
1744 bcopy(sc->arpcom.ac_enaddr,
1745 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr,
1746 sizeof(sc->arpcom.ac_enaddr));
1749 * Start the IAS (Individual Address Setup) command/DMA.
1752 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1753 /* ...and wait for it to complete. */
1754 fxp_dma_wait(&cb_ias->cb_status, sc);
1757 * Initialize transmit control block (TxCB) list.
1761 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB);
1762 for (i = 0; i < FXP_NTXCB; i++) {
1763 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK;
1764 txp[i].cb_command = FXP_CB_COMMAND_NOP;
1766 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status);
1767 if (sc->flags & FXP_FLAG_EXT_TXCB)
1768 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]);
1770 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]);
1771 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK];
1774 * Set the suspend flag on the first TxCB and start the control
1775 * unit. It will execute the NOP and then suspend.
1777 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S;
1778 sc->cbl_first = sc->cbl_last = txp;
1782 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1785 * Initialize receiver buffer area - RFA.
1788 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1789 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE);
1790 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1793 * Set current media.
1795 if (sc->miibus != NULL)
1796 mii_mediachg(device_get_softc(sc->miibus));
1798 ifp->if_flags |= IFF_RUNNING;
1799 ifp->if_flags &= ~IFF_OACTIVE;
1802 * Enable interrupts.
1804 #ifdef DEVICE_POLLING
1806 * ... but only do that if we are not polling. And because (presumably)
1807 * the default is interrupts on, we need to disable them explicitly!
1809 if ( ifp->if_flags & IFF_POLLING )
1810 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1812 #endif /* DEVICE_POLLING */
1813 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1817 * Start stats updater.
1819 sc->stat_ch = timeout(fxp_tick, sc, hz);
1823 fxp_serial_ifmedia_upd(struct ifnet *ifp)
1830 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1833 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL;
1837 * Change media according to request.
1840 fxp_ifmedia_upd(struct ifnet *ifp)
1842 struct fxp_softc *sc = ifp->if_softc;
1843 struct mii_data *mii;
1845 mii = device_get_softc(sc->miibus);
1851 * Notify the world which media we're using.
1854 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1856 struct fxp_softc *sc = ifp->if_softc;
1857 struct mii_data *mii;
1859 mii = device_get_softc(sc->miibus);
1861 ifmr->ifm_active = mii->mii_media_active;
1862 ifmr->ifm_status = mii->mii_media_status;
1864 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG)
1865 sc->cu_resume_bug = 1;
1867 sc->cu_resume_bug = 0;
1871 * Add a buffer to the end of the RFA buffer list.
1872 * Return 0 if successful, 1 for failure. A failure results in
1873 * adding the 'oldm' (if non-NULL) on to the end of the list -
1874 * tossing out its old contents and recycling it.
1875 * The RFA struct is stuck at the beginning of mbuf cluster and the
1876 * data pointer is fixed up to point just past it.
1879 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm)
1883 struct fxp_rfa *rfa, *p_rfa;
1885 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1886 if (m == NULL) { /* try to recycle the old mbuf instead */
1890 m->m_data = m->m_ext.ext_buf;
1894 * Move the data pointer up so that the incoming data packet
1895 * will be 32-bit aligned.
1897 m->m_data += RFA_ALIGNMENT_FUDGE;
1900 * Get a pointer to the base of the mbuf cluster and move
1901 * data start past it.
1903 rfa = mtod(m, struct fxp_rfa *);
1904 m->m_data += sizeof(struct fxp_rfa);
1905 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE);
1908 * Initialize the rest of the RFA. Note that since the RFA
1909 * is misaligned, we cannot store values directly. Instead,
1910 * we use an optimized, inline copy.
1913 rfa->rfa_status = 0;
1914 rfa->rfa_control = FXP_RFA_CONTROL_EL;
1915 rfa->actual_size = 0;
1918 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr);
1919 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr);
1922 * If there are other buffers already on the list, attach this
1923 * one to the end by fixing up the tail to point to this one.
1925 if (sc->rfa_headm != NULL) {
1926 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf +
1927 RFA_ALIGNMENT_FUDGE);
1928 sc->rfa_tailm->m_next = m;
1930 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr);
1931 p_rfa->rfa_control = 0;
1941 fxp_miibus_readreg(device_t dev, int phy, int reg)
1943 struct fxp_softc *sc = device_get_softc(dev);
1947 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
1948 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
1950 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
1955 device_printf(dev, "fxp_miibus_readreg: timed out\n");
1957 return (value & 0xffff);
1961 fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
1963 struct fxp_softc *sc = device_get_softc(dev);
1966 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
1967 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
1970 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
1975 device_printf(dev, "fxp_miibus_writereg: timed out\n");
1979 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1981 struct fxp_softc *sc = ifp->if_softc;
1982 struct ifreq *ifr = (struct ifreq *)data;
1983 struct mii_data *mii;
1992 error = ether_ioctl(ifp, command, data);
1996 if (ifp->if_flags & IFF_ALLMULTI)
1997 sc->flags |= FXP_FLAG_ALL_MCAST;
1999 sc->flags &= ~FXP_FLAG_ALL_MCAST;
2002 * If interface is marked up and not running, then start it.
2003 * If it is marked down and running, stop it.
2004 * XXX If it's up then re-initialize it. This is so flags
2005 * such as IFF_PROMISC are handled.
2007 if (ifp->if_flags & IFF_UP) {
2010 if (ifp->if_flags & IFF_RUNNING)
2017 if (ifp->if_flags & IFF_ALLMULTI)
2018 sc->flags |= FXP_FLAG_ALL_MCAST;
2020 sc->flags &= ~FXP_FLAG_ALL_MCAST;
2022 * Multicast list has changed; set the hardware filter
2025 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0)
2028 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it
2029 * again rather than else {}.
2031 if (sc->flags & FXP_FLAG_ALL_MCAST)
2038 if (sc->miibus != NULL) {
2039 mii = device_get_softc(sc->miibus);
2040 error = ifmedia_ioctl(ifp, ifr,
2041 &mii->mii_media, command);
2043 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2055 * Fill in the multicast address list and return number of entries.
2058 fxp_mc_addrs(struct fxp_softc *sc)
2060 struct fxp_cb_mcs *mcsp = sc->mcsp;
2061 struct ifnet *ifp = &sc->sc_if;
2062 struct ifmultiaddr *ifma;
2066 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) {
2067 #if defined(__DragonFly__) || __FreeBSD_version < 500000
2068 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2070 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2072 if (ifma->ifma_addr->sa_family != AF_LINK)
2074 if (nmcasts >= MAXMCADDR) {
2075 sc->flags |= FXP_FLAG_ALL_MCAST;
2079 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
2080 (void *)(uintptr_t)(volatile void *)
2081 &sc->mcsp->mc_addr[nmcasts][0], 6);
2085 mcsp->mc_cnt = nmcasts * 6;
2090 * Program the multicast filter.
2092 * We have an artificial restriction that the multicast setup command
2093 * must be the first command in the chain, so we take steps to ensure
2094 * this. By requiring this, it allows us to keep up the performance of
2095 * the pre-initialized command ring (esp. link pointers) by not actually
2096 * inserting the mcsetup command in the ring - i.e. its link pointer
2097 * points to the TxCB ring, but the mcsetup descriptor itself is not part
2098 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
2099 * lead into the regular TxCB ring when it completes.
2101 * This function must be called at splimp.
2104 fxp_mc_setup(struct fxp_softc *sc)
2106 struct fxp_cb_mcs *mcsp = sc->mcsp;
2107 struct ifnet *ifp = &sc->sc_if;
2111 * If there are queued commands, we must wait until they are all
2112 * completed. If we are already waiting, then add a NOP command
2113 * with interrupt option so that we're notified when all commands
2114 * have been completed - fxp_start() ensures that no additional
2115 * TX commands will be added when need_mcsetup is true.
2117 if (sc->tx_queued) {
2118 struct fxp_cb_tx *txp;
2121 * need_mcsetup will be true if we are already waiting for the
2122 * NOP command to be completed (see below). In this case, bail.
2124 if (sc->need_mcsetup)
2126 sc->need_mcsetup = 1;
2129 * Add a NOP command with interrupt so that we are notified
2130 * when all TX commands have been processed.
2132 txp = sc->cbl_last->next;
2133 txp->mb_head = NULL;
2135 txp->cb_command = FXP_CB_COMMAND_NOP |
2136 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
2138 * Advance the end of list forward.
2140 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
2144 * Issue a resume in case the CU has just suspended.
2147 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
2149 * Set a 5 second timer just in case we don't hear from the
2156 sc->need_mcsetup = 0;
2159 * Initialize multicast setup descriptor.
2161 mcsp->next = sc->cbl_base;
2162 mcsp->mb_head = NULL;
2163 mcsp->cb_status = 0;
2164 mcsp->cb_command = FXP_CB_COMMAND_MCAS |
2165 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
2166 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status);
2167 (void) fxp_mc_addrs(sc);
2168 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp;
2172 * Wait until command unit is not active. This should never
2173 * be the case when nothing is queued, but make sure anyway.
2176 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) ==
2177 FXP_SCB_CUS_ACTIVE && --count)
2180 device_printf(sc->dev, "command queue timeout\n");
2185 * Start the multicast setup command.
2188 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
2189 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2195 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE;
2196 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE;
2197 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE;
2198 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE;
2199 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE;
2200 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE;
2202 #define UCODE(x) x, sizeof(x)
2208 u_short int_delay_offset;
2209 u_short bundle_max_offset;
2211 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 },
2212 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 },
2213 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma),
2214 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD },
2215 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s),
2216 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD },
2217 { FXP_REV_82550, UCODE(fxp_ucode_d102),
2218 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD },
2219 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c),
2220 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD },
2221 { 0, NULL, 0, 0, 0 }
2225 fxp_load_ucode(struct fxp_softc *sc)
2228 struct fxp_cb_ucode *cbp;
2230 for (uc = ucode_table; uc->ucode != NULL; uc++)
2231 if (sc->revision == uc->revision)
2233 if (uc->ucode == NULL)
2235 cbp = (struct fxp_cb_ucode *)sc->cbl_base;
2237 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL;
2238 cbp->link_addr = -1; /* (no) next command */
2239 memcpy(cbp->ucode, uc->ucode, uc->length);
2240 if (uc->int_delay_offset)
2241 *(u_short *)&cbp->ucode[uc->int_delay_offset] =
2242 sc->tunable_int_delay + sc->tunable_int_delay / 2;
2243 if (uc->bundle_max_offset)
2244 *(u_short *)&cbp->ucode[uc->bundle_max_offset] =
2245 sc->tunable_bundle_max;
2247 * Download the ucode to the chip.
2250 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
2251 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2252 /* ...and wait for it to complete. */
2253 fxp_dma_wait(&cbp->cb_status, sc);
2254 device_printf(sc->dev,
2255 "Microcode loaded, int_delay: %d usec bundle_max: %d\n",
2256 sc->tunable_int_delay,
2257 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
2258 sc->flags |= FXP_FLAG_UCODE;
2262 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
2266 value = *(int *)arg1;
2267 error = sysctl_handle_int(oidp, &value, 0, req);
2268 if (error || !req->newptr)
2270 if (value < low || value > high)
2272 *(int *)arg1 = value;
2277 * Interrupt delay is expressed in microseconds, a multiplier is used
2278 * to convert this to the appropriate clock ticks before using.
2281 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)
2283 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000));
2287 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)
2289 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff));