1 #ifndef _ECC_E31200_REG_H_
2 #define _ECC_E31200_REG_H_
5 #include <sys/bitops.h>
8 #define PCI_E31200_MCHBAR_LO 0x48
9 #define PCI_E31200_MCHBAR_LO_EN 0x1
10 #define PCI_E31200_MCHBAR_HI 0x4c
12 #define PCI_E31200_CAPID0_A 0xe4
13 #define PCI_E31200_CAPID0_A_DMFC __BITS(0, 2)
14 #define PCI_E31200_CAPID0_A_DMFC_ALL 0
15 #define PCI_E31200_CAPID0_A_DMFC_1333 0x6
16 #define PCI_E31200_CAPID0_A_DMFC_1067 0x7
17 #define PCI_E31200_CAPID0_A_ECCDIS __BIT(25)
19 #define PCI_E31200_MCHBAR_ADDRMASK __BITS64(15, 38)
21 #define MCH_E31200_SIZE (32 * 1024)
23 #define MCH_E31200_ERRLOG0_C0 0x40c8
24 #define MCH_E31200_ERRLOG1_C0 0x40cc
26 #define MCH_E31200_ERRLOG0_C1 0x44c8
27 #define MCH_E31200_ERRLOG1_C1 0x44cc
29 #define MCH_E31200_ERRLOG0_CERRSTS __BIT(0)
30 #define MCH_E31200_ERRLOG0_MERRSTS __BIT(1)
31 #define MCH_E31200_ERRLOG0_ERRSYND __BITS(16, 23)
32 #define MCH_E31200_ERRLOG0_ERRCHUNK __BITS(24, 26)
33 #define MCH_E31200_ERRLOG0_ERRRANK __BITS(27, 28)
34 #define MCH_E31200_ERRLOG0_ERRBANK __BITS(29, 31)
36 #define MCH_E31200_ERRLOG1_ERRROW __BITS(0, 15)
37 #define MCH_E31200_ERRLOG1_ERRCOL __BITS(16, 31)
39 #define MCH_E31200_DIMM_CH0 0x5004
40 #define MCH_E31200_DIMM_CH1 0x5008
42 #define MCH_E31200_DIMM_SIZE_UNIT 256 /* MB */
43 #define MCH_E31200_DIMM_A_SIZE __BITS(0, 7)
44 #define MCH_E31200_DIMM_B_SIZE __BITS(8, 15)
45 #define MCH_E31200_DIMM_A_DUAL_RANK __BIT(17)
46 #define MCH_E31200_DIMM_B_DUAL_RANK __BIT(18)
47 #define MCH_E31200_DIMM_A_X16 __BIT(19)
48 #define MCH_E31200_DIMM_B_X16 __BIT(20)
49 #define MCH_E31200_DIMM_RI __BIT(21) /* rank interleave */
50 #define MCH_E31200_DIMM_ENHI __BIT(22) /* enchanced interleave */
51 #define MCH_E31200_DIMM_ECC __BITS(24, 25)
52 #define MCH_E31200_DIMM_ECC_NONE 0x0
53 #define MCH_E31200_DIMM_ECC_IO 0x1
54 #define MCH_E31200_DIMM_ECC_LOGIC 0x2
55 #define MCH_E31200_DIMM_ECC_ALL 0x3
57 #endif /* !_ECC_E31200_REG_H_ */