1 /* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*-
3 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
5 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved.
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
29 * Keith Whitwell <keith@tungstengraphics.com>
30 * Michel Dänzer <michel@daenzer.net>
32 * $FreeBSD: src/sys/dev/drm/radeon_irq.c,v 1.2.2.1 2003/04/26 07:05:29 anholt Exp $
35 #include "dev/drm/radeon.h"
36 #include "dev/drm/drmP.h"
37 #include "dev/drm/drm.h"
38 #include "dev/drm/radeon_drm.h"
39 #include "dev/drm/radeon_drv.h"
41 /* Interrupts - Used for device synchronization and flushing in the
42 * following circumstances:
44 * - Exclusive FB access with hw idle:
45 * - Wait for GUI Idle (?) interrupt, then do normal flush.
47 * - Frame throttling, NV_fence:
48 * - Drop marker irq's into command stream ahead of time.
49 * - Wait on irq's with lock *not held*
50 * - Check each for termination condition
52 * - Internally in cp_getbuffer, etc:
53 * - as above, but wait with lock held???
55 * NOTE: These functions are misleadingly named -- the irq's aren't
56 * tied to dma at all, this is just a hangover from dri prehistory.
59 void DRM(dma_service)( DRM_IRQ_ARGS )
61 drm_device_t *dev = (drm_device_t *) arg;
62 drm_radeon_private_t *dev_priv =
63 (drm_radeon_private_t *)dev->dev_private;
66 /* Only consider the bits we're interested in - others could be used
69 stat = RADEON_READ(RADEON_GEN_INT_STATUS)
70 & (RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT);
75 if (stat & RADEON_SW_INT_TEST) {
76 DRM_WAKEUP( &dev_priv->swi_queue );
79 /* VBLANK interrupt */
80 if (stat & RADEON_CRTC_VBLANK_STAT) {
81 atomic_inc(&dev->vbl_received);
82 DRM_WAKEUP(&dev->vbl_queue);
83 DRM(vbl_send_signals)( dev );
86 /* Acknowledge interrupts we handle */
87 RADEON_WRITE(RADEON_GEN_INT_STATUS, stat);
90 static __inline__ void radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv)
92 u32 tmp = RADEON_READ( RADEON_GEN_INT_STATUS )
93 & (RADEON_SW_INT_TEST_ACK | RADEON_CRTC_VBLANK_STAT);
95 RADEON_WRITE( RADEON_GEN_INT_STATUS, tmp );
98 int radeon_emit_irq(drm_device_t *dev)
100 drm_radeon_private_t *dev_priv = dev->dev_private;
104 atomic_inc(&dev_priv->swi_emitted);
105 ret = atomic_read(&dev_priv->swi_emitted);
108 OUT_RING_REG( RADEON_LAST_SWI_REG, ret );
109 OUT_RING_REG( RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE );
117 int radeon_wait_irq(drm_device_t *dev, int swi_nr)
119 drm_radeon_private_t *dev_priv =
120 (drm_radeon_private_t *)dev->dev_private;
123 if (RADEON_READ( RADEON_LAST_SWI_REG ) >= swi_nr)
126 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
128 /* This is a hack to work around mysterious freezes on certain
131 radeon_acknowledge_irqs( dev_priv );
133 DRM_WAIT_ON( ret, dev_priv->swi_queue, 3 * DRM_HZ,
134 RADEON_READ( RADEON_LAST_SWI_REG ) >= swi_nr );
139 int radeon_emit_and_wait_irq(drm_device_t *dev)
141 return radeon_wait_irq( dev, radeon_emit_irq(dev) );
145 int DRM(vblank_wait)(drm_device_t *dev, unsigned int *sequence)
147 drm_radeon_private_t *dev_priv =
148 (drm_radeon_private_t *)dev->dev_private;
149 unsigned int cur_vblank;
153 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
154 return DRM_ERR(EINVAL);
157 radeon_acknowledge_irqs( dev_priv );
159 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
161 /* Assume that the user has missed the current sequence number
162 * by about a day rather than she wants to wait for years
163 * using vertical blanks...
165 DRM_WAIT_ON( ret, dev->vbl_queue, 3*DRM_HZ,
166 ( ( ( cur_vblank = atomic_read(&dev->vbl_received ) )
167 - *sequence ) <= (1<<23) ) );
169 *sequence = cur_vblank;
175 /* Needs the lock as it touches the ring.
177 int radeon_irq_emit( DRM_IOCTL_ARGS )
180 drm_radeon_private_t *dev_priv = dev->dev_private;
181 drm_radeon_irq_emit_t emit;
184 LOCK_TEST_WITH_RETURN( dev, filp );
187 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
188 return DRM_ERR(EINVAL);
191 DRM_COPY_FROM_USER_IOCTL( emit, (drm_radeon_irq_emit_t *)data,
194 result = radeon_emit_irq( dev );
196 if ( DRM_COPY_TO_USER( emit.irq_seq, &result, sizeof(int) ) ) {
197 DRM_ERROR( "copy_to_user\n" );
198 return DRM_ERR(EFAULT);
205 /* Doesn't need the hardware lock.
207 int radeon_irq_wait( DRM_IOCTL_ARGS )
210 drm_radeon_private_t *dev_priv = dev->dev_private;
211 drm_radeon_irq_wait_t irqwait;
214 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
215 return DRM_ERR(EINVAL);
218 DRM_COPY_FROM_USER_IOCTL( irqwait, (drm_radeon_irq_wait_t *)data,
221 return radeon_wait_irq( dev, irqwait.irq_seq );
227 void DRM(driver_irq_preinstall)( drm_device_t *dev ) {
228 drm_radeon_private_t *dev_priv =
229 (drm_radeon_private_t *)dev->dev_private;
231 /* Disable *all* interrupts */
232 RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
234 /* Clear bits if they're already high */
235 radeon_acknowledge_irqs( dev_priv );
238 void DRM(driver_irq_postinstall)( drm_device_t *dev ) {
239 drm_radeon_private_t *dev_priv =
240 (drm_radeon_private_t *)dev->dev_private;
242 atomic_set(&dev_priv->swi_emitted, 0);
243 DRM_INIT_WAITQUEUE( &dev_priv->swi_queue );
245 /* Turn on SW and VBL ints */
246 RADEON_WRITE( RADEON_GEN_INT_CNTL,
247 RADEON_CRTC_VBLANK_MASK |
248 RADEON_SW_INT_ENABLE );
251 void DRM(driver_irq_uninstall)( drm_device_t *dev ) {
252 drm_radeon_private_t *dev_priv =
253 (drm_radeon_private_t *)dev->dev_private;
255 /* Disable *all* interrupts */
256 RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );