2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/bge/if_bgereg.h,v 1.1.2.10 2003/05/11 18:00:55 ps Exp $
37 * BCM570x memory map. The internal memory layout varies somewhat
38 * depending on whether or not we have external SSRAM attached.
39 * The BCM5700 can have up to 16MB of external memory. The BCM5701
40 * is apparently not designed to use external SSRAM. The mappings
41 * up to the first 4 send rings are the same for both internal and
42 * external memory configurations. Note that mini RX ring space is
43 * only available with external SSRAM configurations, which means
44 * the mini RX ring is not supported on the BCM5701.
46 * The NIC's memory can be accessed by the host in one of 3 ways:
48 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA
49 * registers in PCI config space can be used to read any 32-bit
50 * address within the NIC's memory.
52 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config
53 * space can be used in conjunction with the memory window in the
54 * device register space at offset 0x8000 to read any 32K chunk
57 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is
58 * set, the device I/O mapping consumes 32MB of host address space,
59 * allowing all of the registers and internal NIC memory to be
60 * accessed directly. NIC memory addresses are offset by 0x01000000.
61 * Flat mode consumes so much host address space that it is not
64 #define BGE_PAGE_ZERO 0x00000000
65 #define BGE_PAGE_ZERO_END 0x000000FF
66 #define BGE_SEND_RING_RCB 0x00000100
67 #define BGE_SEND_RING_RCB_END 0x000001FF
68 #define BGE_RX_RETURN_RING_RCB 0x00000200
69 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF
70 #define BGE_STATS_BLOCK 0x00000300
71 #define BGE_STATS_BLOCK_END 0x00000AFF
72 #define BGE_STATUS_BLOCK 0x00000B00
73 #define BGE_STATUS_BLOCK_END 0x00000B4F
74 #define BGE_SOFTWARE_GENCOMM 0x00000B50
75 #define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54
76 #define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58
77 #define BGE_SOFTWARE_GENCOMM_END 0x00000FFF
78 #define BGE_UNMAPPED 0x00001000
79 #define BGE_UNMAPPED_END 0x00001FFF
80 #define BGE_DMA_DESCRIPTORS 0x00002000
81 #define BGE_DMA_DESCRIPTORS_END 0x00003FFF
82 #define BGE_SEND_RING_1_TO_4 0x00004000
83 #define BGE_SEND_RING_1_TO_4_END 0x00005FFF
85 /* Mappings for internal memory configuration */
86 #define BGE_STD_RX_RINGS 0x00006000
87 #define BGE_STD_RX_RINGS_END 0x00006FFF
88 #define BGE_JUMBO_RX_RINGS 0x00007000
89 #define BGE_JUMBO_RX_RINGS_END 0x00007FFF
90 #define BGE_BUFFPOOL_1 0x00008000
91 #define BGE_BUFFPOOL_1_END 0x0000FFFF
92 #define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */
93 #define BGE_BUFFPOOL_2_END 0x00017FFF
94 #define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */
95 #define BGE_BUFFPOOL_3_END 0x0001FFFF
97 /* Mappings for external SSRAM configurations */
98 #define BGE_SEND_RING_5_TO_6 0x00006000
99 #define BGE_SEND_RING_5_TO_6_END 0x00006FFF
100 #define BGE_SEND_RING_7_TO_8 0x00007000
101 #define BGE_SEND_RING_7_TO_8_END 0x00007FFF
102 #define BGE_SEND_RING_9_TO_16 0x00008000
103 #define BGE_SEND_RING_9_TO_16_END 0x0000BFFF
104 #define BGE_EXT_STD_RX_RINGS 0x0000C000
105 #define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF
106 #define BGE_EXT_JUMBO_RX_RINGS 0x0000D000
107 #define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF
108 #define BGE_MINI_RX_RINGS 0x0000E000
109 #define BGE_MINI_RX_RINGS_END 0x0000FFFF
110 #define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */
111 #define BGE_AVAIL_REGION1_END 0x00017FFF
112 #define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */
113 #define BGE_AVAIL_REGION2_END 0x0001FFFF
114 #define BGE_EXT_SSRAM 0x00020000
115 #define BGE_EXT_SSRAM_END 0x000FFFFF
119 * BCM570x register offsets. These are memory mapped registers
120 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros.
121 * Each register must be accessed using 32 bit operations.
123 * All registers are accessed through a 32K shared memory block.
124 * The first group of registers are actually copies of the PCI
125 * configuration space registers.
129 * PCI registers defined in the PCI 2.2 spec.
131 #define BGE_PCI_VID 0x00
132 #define BGE_PCI_DID 0x02
133 #define BGE_PCI_CMD 0x04
134 #define BGE_PCI_STS 0x06
135 #define BGE_PCI_REV 0x08
136 #define BGE_PCI_CLASS 0x09
137 #define BGE_PCI_CACHESZ 0x0C
138 #define BGE_PCI_LATTIMER 0x0D
139 #define BGE_PCI_HDRTYPE 0x0E
140 #define BGE_PCI_BIST 0x0F
141 #define BGE_PCI_BAR0 0x10
142 #define BGE_PCI_BAR1 0x14
143 #define BGE_PCI_SUBSYS 0x2C
144 #define BGE_PCI_SUBVID 0x2E
145 #define BGE_PCI_ROMBASE 0x30
146 #define BGE_PCI_CAPPTR 0x34
147 #define BGE_PCI_INTLINE 0x3C
148 #define BGE_PCI_INTPIN 0x3D
149 #define BGE_PCI_MINGNT 0x3E
150 #define BGE_PCI_MAXLAT 0x3F
151 #define BGE_PCI_PCIXCAP 0x40
152 #define BGE_PCI_NEXTPTR_PM 0x41
153 #define BGE_PCI_PCIX_CMD 0x42
154 #define BGE_PCI_PCIX_STS 0x44
155 #define BGE_PCI_PWRMGMT_CAPID 0x48
156 #define BGE_PCI_NEXTPTR_VPD 0x49
157 #define BGE_PCI_PWRMGMT_CAPS 0x4A
158 #define BGE_PCI_PWRMGMT_CMD 0x4C
159 #define BGE_PCI_PWRMGMT_STS 0x4D
160 #define BGE_PCI_PWRMGMT_DATA 0x4F
161 #define BGE_PCI_VPD_CAPID 0x50
162 #define BGE_PCI_NEXTPTR_MSI 0x51
163 #define BGE_PCI_VPD_ADDR 0x52
164 #define BGE_PCI_VPD_DATA 0x54
165 #define BGE_PCI_MSI_CAPID 0x58
166 #define BGE_PCI_NEXTPTR_NONE 0x59
167 #define BGE_PCI_MSI_CTL 0x5A
168 #define BGE_PCI_MSI_ADDR_HI 0x5C
169 #define BGE_PCI_MSI_ADDR_LO 0x60
170 #define BGE_PCI_MSI_DATA 0x64
173 * PCI registers specific to the BCM570x family.
175 #define BGE_PCI_MISC_CTL 0x68
176 #define BGE_PCI_DMA_RW_CTL 0x6C
177 #define BGE_PCI_PCISTATE 0x70
178 #define BGE_PCI_CLKCTL 0x74
179 #define BGE_PCI_REG_BASEADDR 0x78
180 #define BGE_PCI_MEMWIN_BASEADDR 0x7C
181 #define BGE_PCI_REG_DATA 0x80
182 #define BGE_PCI_MEMWIN_DATA 0x84
183 #define BGE_PCI_MODECTL 0x88
184 #define BGE_PCI_MISC_CFG 0x8C
185 #define BGE_PCI_MISC_LOCALCTL 0x90
186 #define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98
187 #define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C
188 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0
189 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4
190 #define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8
191 #define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC
192 #define BGE_PCI_ISR_MBX_HI 0xB0
193 #define BGE_PCI_ISR_MBX_LO 0xB4
195 /* PCI Misc. Host control register */
196 #define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001
197 #define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002
198 #define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004
199 #define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008
200 #define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010
201 #define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020
202 #define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040
203 #define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080
204 #define BGE_PCIMISCCTL_ASICREV 0xFFFF0000
206 #define BGE_BIGENDIAN_INIT \
207 (BGE_BGE_PCIMISCCTL_ENDIAN_BYTESWAP| \
208 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_CLEAR_INTA| \
209 BGE_PCIMISCCTL_INDIRECT_ACCESS|PCIMISCCTL_MASK_PCI_INTR)
211 #define BGE_LITTLEENDIAN_INIT \
212 (BGE_PCIMISCCTL_CLEAR_INTA|BGE_PCIMISCCTL_MASK_PCI_INTR| \
213 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_INDIRECT_ACCESS)
215 #define BGE_CHIPID_TIGON_I 0x40000000
216 #define BGE_CHIPID_TIGON_II 0x60000000
217 #define BGE_CHIPID_BCM5700_B0 0x71000000
218 #define BGE_CHIPID_BCM5700_B1 0x71020000
219 #define BGE_CHIPID_BCM5700_B2 0x71030000
220 #define BGE_CHIPID_BCM5700_ALTIMA 0x71040000
221 #define BGE_CHIPID_BCM5700_C0 0x72000000
222 #define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr */
223 #define BGE_CHIPID_BCM5701_B0 0x01000000
224 #define BGE_CHIPID_BCM5701_B2 0x01020000
225 #define BGE_CHIPID_BCM5701_B5 0x01050000
226 #define BGE_CHIPID_BCM5703_A0 0x10000000
227 #define BGE_CHIPID_BCM5703_A1 0x10010000
228 #define BGE_CHIPID_BCM5703_A2 0x10020000
229 #define BGE_CHIPID_BCM5704_A0 0x20000000
230 #define BGE_CHIPID_BCM5704_A1 0x20010000
231 #define BGE_CHIPID_BCM5704_A2 0x20020000
234 #define BGE_ASICREV(x) ((x) >> 28)
235 #define BGE_ASICREV_BCM5700 0x07
236 #define BGE_ASICREV_BCM5701 0x00
237 #define BGE_ASICREV_BCM5703 0x01
238 #define BGE_ASICREV_BCM5704 0x02
241 #define BGE_CHIPREV(x) ((x) >> 24)
242 #define BGE_CHIPREV_5700_AX 0x70
243 #define BGE_CHIPREV_5700_BX 0x71
244 #define BGE_CHIPREV_5700_CX 0x72
245 #define BGE_CHIPREV_5701_AX 0x00
247 /* PCI DMA Read/Write Control register */
248 #define BGE_PCIDMARWCTL_MINDMA 0x000000FF
249 #define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700
250 #define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800
251 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000
252 #define BGE_PCIDMARWCTL_RD_WAT 0x00070000
253 # define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16
254 #define BGE_PCIDMARWCTL_WR_WAT 0x00380000
255 # define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19
256 #define BGE_PCIDMARWCTL_USE_MRM 0x00400000
257 #define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000
258 #define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000
259 # define BGE_PCIDMA_RWCTL_PCI_RD_CMD_SHIFT 24
260 #define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000
261 # define BGE_PCIDMA_RWCTL_PCI_WR_CMD_SHIFT 28
263 #define BGE_PCI_READ_BNDRY_DISABLE 0x00000000
264 #define BGE_PCI_READ_BNDRY_16BYTES 0x00000100
265 #define BGE_PCI_READ_BNDRY_32BYTES 0x00000200
266 #define BGE_PCI_READ_BNDRY_64BYTES 0x00000300
267 #define BGE_PCI_READ_BNDRY_128BYTES 0x00000400
268 #define BGE_PCI_READ_BNDRY_256BYTES 0x00000500
269 #define BGE_PCI_READ_BNDRY_512BYTES 0x00000600
270 #define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700
272 #define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000
273 #define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800
274 #define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000
275 #define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800
276 #define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000
277 #define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800
278 #define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000
279 #define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800
282 * PCI state register -- note, this register is read only
283 * unless the PCISTATE_WR bit of the PCI Misc. Host Control
286 #define BGE_PCISTATE_FORCE_RESET 0x00000001
287 #define BGE_PCISTATE_INTR_STATE 0x00000002
288 #define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */
289 #define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */
290 #define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */
291 #define BGE_PCISTATE_WANT_EXPROM 0x00000020
292 #define BGE_PCISTATE_EXPROM_RETRY 0x00000040
293 #define BGE_PCISTATE_FLATVIEW_MODE 0x00000100
294 #define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00
297 * PCI Clock Control register -- note, this register is read only
298 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control
301 #define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F
302 #define BGE_PCICLOCKCTL_M66EN 0x00000080
303 #define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200
304 #define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400
305 #define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800
306 #define BGE_PCICLOCKCTL_ALTCLK 0x00001000
307 #define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000
308 #define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000
309 #define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000
310 #define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000
313 #ifndef PCIM_CMD_MWIEN
314 #define PCIM_CMD_MWIEN 0x0010
318 * High priority mailbox registers
319 * Each mailbox is 64-bits wide, though we only use the
320 * lower 32 bits. To write a 64-bit value, write the upper 32 bits
321 * first. The NIC will load the mailbox after the lower 32 bit word
324 #define BGE_MBX_IRQ0_HI 0x0200
325 #define BGE_MBX_IRQ0_LO 0x0204
326 #define BGE_MBX_IRQ1_HI 0x0208
327 #define BGE_MBX_IRQ1_LO 0x020C
328 #define BGE_MBX_IRQ2_HI 0x0210
329 #define BGE_MBX_IRQ2_LO 0x0214
330 #define BGE_MBX_IRQ3_HI 0x0218
331 #define BGE_MBX_IRQ3_LO 0x021C
332 #define BGE_MBX_GEN0_HI 0x0220
333 #define BGE_MBX_GEN0_LO 0x0224
334 #define BGE_MBX_GEN1_HI 0x0228
335 #define BGE_MBX_GEN1_LO 0x022C
336 #define BGE_MBX_GEN2_HI 0x0230
337 #define BGE_MBX_GEN2_LO 0x0234
338 #define BGE_MBX_GEN3_HI 0x0228
339 #define BGE_MBX_GEN3_LO 0x022C
340 #define BGE_MBX_GEN4_HI 0x0240
341 #define BGE_MBX_GEN4_LO 0x0244
342 #define BGE_MBX_GEN5_HI 0x0248
343 #define BGE_MBX_GEN5_LO 0x024C
344 #define BGE_MBX_GEN6_HI 0x0250
345 #define BGE_MBX_GEN6_LO 0x0254
346 #define BGE_MBX_GEN7_HI 0x0258
347 #define BGE_MBX_GEN7_LO 0x025C
348 #define BGE_MBX_RELOAD_STATS_HI 0x0260
349 #define BGE_MBX_RELOAD_STATS_LO 0x0264
350 #define BGE_MBX_RX_STD_PROD_HI 0x0268
351 #define BGE_MBX_RX_STD_PROD_LO 0x026C
352 #define BGE_MBX_RX_JUMBO_PROD_HI 0x0270
353 #define BGE_MBX_RX_JUMBO_PROD_LO 0x0274
354 #define BGE_MBX_RX_MINI_PROD_HI 0x0278
355 #define BGE_MBX_RX_MINI_PROD_LO 0x027C
356 #define BGE_MBX_RX_CONS0_HI 0x0280
357 #define BGE_MBX_RX_CONS0_LO 0x0284
358 #define BGE_MBX_RX_CONS1_HI 0x0288
359 #define BGE_MBX_RX_CONS1_LO 0x028C
360 #define BGE_MBX_RX_CONS2_HI 0x0290
361 #define BGE_MBX_RX_CONS2_LO 0x0294
362 #define BGE_MBX_RX_CONS3_HI 0x0298
363 #define BGE_MBX_RX_CONS3_LO 0x029C
364 #define BGE_MBX_RX_CONS4_HI 0x02A0
365 #define BGE_MBX_RX_CONS4_LO 0x02A4
366 #define BGE_MBX_RX_CONS5_HI 0x02A8
367 #define BGE_MBX_RX_CONS5_LO 0x02AC
368 #define BGE_MBX_RX_CONS6_HI 0x02B0
369 #define BGE_MBX_RX_CONS6_LO 0x02B4
370 #define BGE_MBX_RX_CONS7_HI 0x02B8
371 #define BGE_MBX_RX_CONS7_LO 0x02BC
372 #define BGE_MBX_RX_CONS8_HI 0x02C0
373 #define BGE_MBX_RX_CONS8_LO 0x02C4
374 #define BGE_MBX_RX_CONS9_HI 0x02C8
375 #define BGE_MBX_RX_CONS9_LO 0x02CC
376 #define BGE_MBX_RX_CONS10_HI 0x02D0
377 #define BGE_MBX_RX_CONS10_LO 0x02D4
378 #define BGE_MBX_RX_CONS11_HI 0x02D8
379 #define BGE_MBX_RX_CONS11_LO 0x02DC
380 #define BGE_MBX_RX_CONS12_HI 0x02E0
381 #define BGE_MBX_RX_CONS12_LO 0x02E4
382 #define BGE_MBX_RX_CONS13_HI 0x02E8
383 #define BGE_MBX_RX_CONS13_LO 0x02EC
384 #define BGE_MBX_RX_CONS14_HI 0x02F0
385 #define BGE_MBX_RX_CONS14_LO 0x02F4
386 #define BGE_MBX_RX_CONS15_HI 0x02F8
387 #define BGE_MBX_RX_CONS15_LO 0x02FC
388 #define BGE_MBX_TX_HOST_PROD0_HI 0x0300
389 #define BGE_MBX_TX_HOST_PROD0_LO 0x0304
390 #define BGE_MBX_TX_HOST_PROD1_HI 0x0308
391 #define BGE_MBX_TX_HOST_PROD1_LO 0x030C
392 #define BGE_MBX_TX_HOST_PROD2_HI 0x0310
393 #define BGE_MBX_TX_HOST_PROD2_LO 0x0314
394 #define BGE_MBX_TX_HOST_PROD3_HI 0x0318
395 #define BGE_MBX_TX_HOST_PROD3_LO 0x031C
396 #define BGE_MBX_TX_HOST_PROD4_HI 0x0320
397 #define BGE_MBX_TX_HOST_PROD4_LO 0x0324
398 #define BGE_MBX_TX_HOST_PROD5_HI 0x0328
399 #define BGE_MBX_TX_HOST_PROD5_LO 0x032C
400 #define BGE_MBX_TX_HOST_PROD6_HI 0x0330
401 #define BGE_MBX_TX_HOST_PROD6_LO 0x0334
402 #define BGE_MBX_TX_HOST_PROD7_HI 0x0338
403 #define BGE_MBX_TX_HOST_PROD7_LO 0x033C
404 #define BGE_MBX_TX_HOST_PROD8_HI 0x0340
405 #define BGE_MBX_TX_HOST_PROD8_LO 0x0344
406 #define BGE_MBX_TX_HOST_PROD9_HI 0x0348
407 #define BGE_MBX_TX_HOST_PROD9_LO 0x034C
408 #define BGE_MBX_TX_HOST_PROD10_HI 0x0350
409 #define BGE_MBX_TX_HOST_PROD10_LO 0x0354
410 #define BGE_MBX_TX_HOST_PROD11_HI 0x0358
411 #define BGE_MBX_TX_HOST_PROD11_LO 0x035C
412 #define BGE_MBX_TX_HOST_PROD12_HI 0x0360
413 #define BGE_MBX_TX_HOST_PROD12_LO 0x0364
414 #define BGE_MBX_TX_HOST_PROD13_HI 0x0368
415 #define BGE_MBX_TX_HOST_PROD13_LO 0x036C
416 #define BGE_MBX_TX_HOST_PROD14_HI 0x0370
417 #define BGE_MBX_TX_HOST_PROD14_LO 0x0374
418 #define BGE_MBX_TX_HOST_PROD15_HI 0x0378
419 #define BGE_MBX_TX_HOST_PROD15_LO 0x037C
420 #define BGE_MBX_TX_NIC_PROD0_HI 0x0380
421 #define BGE_MBX_TX_NIC_PROD0_LO 0x0384
422 #define BGE_MBX_TX_NIC_PROD1_HI 0x0388
423 #define BGE_MBX_TX_NIC_PROD1_LO 0x038C
424 #define BGE_MBX_TX_NIC_PROD2_HI 0x0390
425 #define BGE_MBX_TX_NIC_PROD2_LO 0x0394
426 #define BGE_MBX_TX_NIC_PROD3_HI 0x0398
427 #define BGE_MBX_TX_NIC_PROD3_LO 0x039C
428 #define BGE_MBX_TX_NIC_PROD4_HI 0x03A0
429 #define BGE_MBX_TX_NIC_PROD4_LO 0x03A4
430 #define BGE_MBX_TX_NIC_PROD5_HI 0x03A8
431 #define BGE_MBX_TX_NIC_PROD5_LO 0x03AC
432 #define BGE_MBX_TX_NIC_PROD6_HI 0x03B0
433 #define BGE_MBX_TX_NIC_PROD6_LO 0x03B4
434 #define BGE_MBX_TX_NIC_PROD7_HI 0x03B8
435 #define BGE_MBX_TX_NIC_PROD7_LO 0x03BC
436 #define BGE_MBX_TX_NIC_PROD8_HI 0x03C0
437 #define BGE_MBX_TX_NIC_PROD8_LO 0x03C4
438 #define BGE_MBX_TX_NIC_PROD9_HI 0x03C8
439 #define BGE_MBX_TX_NIC_PROD9_LO 0x03CC
440 #define BGE_MBX_TX_NIC_PROD10_HI 0x03D0
441 #define BGE_MBX_TX_NIC_PROD10_LO 0x03D4
442 #define BGE_MBX_TX_NIC_PROD11_HI 0x03D8
443 #define BGE_MBX_TX_NIC_PROD11_LO 0x03DC
444 #define BGE_MBX_TX_NIC_PROD12_HI 0x03E0
445 #define BGE_MBX_TX_NIC_PROD12_LO 0x03E4
446 #define BGE_MBX_TX_NIC_PROD13_HI 0x03E8
447 #define BGE_MBX_TX_NIC_PROD13_LO 0x03EC
448 #define BGE_MBX_TX_NIC_PROD14_HI 0x03F0
449 #define BGE_MBX_TX_NIC_PROD14_LO 0x03F4
450 #define BGE_MBX_TX_NIC_PROD15_HI 0x03F8
451 #define BGE_MBX_TX_NIC_PROD15_LO 0x03FC
453 #define BGE_TX_RINGS_MAX 4
454 #define BGE_TX_RINGS_EXTSSRAM_MAX 16
455 #define BGE_RX_RINGS_MAX 16
457 /* Ethernet MAC control registers */
458 #define BGE_MAC_MODE 0x0400
459 #define BGE_MAC_STS 0x0404
460 #define BGE_MAC_EVT_ENB 0x0408
461 #define BGE_MAC_LED_CTL 0x040C
462 #define BGE_MAC_ADDR1_LO 0x0410
463 #define BGE_MAC_ADDR1_HI 0x0414
464 #define BGE_MAC_ADDR2_LO 0x0418
465 #define BGE_MAC_ADDR2_HI 0x041C
466 #define BGE_MAC_ADDR3_LO 0x0420
467 #define BGE_MAC_ADDR3_HI 0x0424
468 #define BGE_MAC_ADDR4_LO 0x0428
469 #define BGE_MAC_ADDR4_HI 0x042C
470 #define BGE_WOL_PATPTR 0x0430
471 #define BGE_WOL_PATCFG 0x0434
472 #define BGE_TX_RANDOM_BACKOFF 0x0438
473 #define BGE_RX_MTU 0x043C
474 #define BGE_GBIT_PCS_TEST 0x0440
475 #define BGE_TX_TBI_AUTONEG 0x0444
476 #define BGE_RX_TBI_AUTONEG 0x0448
477 #define BGE_MI_COMM 0x044C
478 #define BGE_MI_STS 0x0450
479 #define BGE_MI_MODE 0x0454
480 #define BGE_AUTOPOLL_STS 0x0458
481 #define BGE_TX_MODE 0x045C
482 #define BGE_TX_STS 0x0460
483 #define BGE_TX_LENGTHS 0x0464
484 #define BGE_RX_MODE 0x0468
485 #define BGE_RX_STS 0x046C
486 #define BGE_MAR0 0x0470
487 #define BGE_MAR1 0x0474
488 #define BGE_MAR2 0x0478
489 #define BGE_MAR3 0x047C
490 #define BGE_RX_BD_RULES_CTL0 0x0480
491 #define BGE_RX_BD_RULES_MASKVAL0 0x0484
492 #define BGE_RX_BD_RULES_CTL1 0x0488
493 #define BGE_RX_BD_RULES_MASKVAL1 0x048C
494 #define BGE_RX_BD_RULES_CTL2 0x0490
495 #define BGE_RX_BD_RULES_MASKVAL2 0x0494
496 #define BGE_RX_BD_RULES_CTL3 0x0498
497 #define BGE_RX_BD_RULES_MASKVAL3 0x049C
498 #define BGE_RX_BD_RULES_CTL4 0x04A0
499 #define BGE_RX_BD_RULES_MASKVAL4 0x04A4
500 #define BGE_RX_BD_RULES_CTL5 0x04A8
501 #define BGE_RX_BD_RULES_MASKVAL5 0x04AC
502 #define BGE_RX_BD_RULES_CTL6 0x04B0
503 #define BGE_RX_BD_RULES_MASKVAL6 0x04B4
504 #define BGE_RX_BD_RULES_CTL7 0x04B8
505 #define BGE_RX_BD_RULES_MASKVAL7 0x04BC
506 #define BGE_RX_BD_RULES_CTL8 0x04C0
507 #define BGE_RX_BD_RULES_MASKVAL8 0x04C4
508 #define BGE_RX_BD_RULES_CTL9 0x04C8
509 #define BGE_RX_BD_RULES_MASKVAL9 0x04CC
510 #define BGE_RX_BD_RULES_CTL10 0x04D0
511 #define BGE_RX_BD_RULES_MASKVAL10 0x04D4
512 #define BGE_RX_BD_RULES_CTL11 0x04D8
513 #define BGE_RX_BD_RULES_MASKVAL11 0x04DC
514 #define BGE_RX_BD_RULES_CTL12 0x04E0
515 #define BGE_RX_BD_RULES_MASKVAL12 0x04E4
516 #define BGE_RX_BD_RULES_CTL13 0x04E8
517 #define BGE_RX_BD_RULES_MASKVAL13 0x04EC
518 #define BGE_RX_BD_RULES_CTL14 0x04F0
519 #define BGE_RX_BD_RULES_MASKVAL14 0x04F4
520 #define BGE_RX_BD_RULES_CTL15 0x04F8
521 #define BGE_RX_BD_RULES_MASKVAL15 0x04FC
522 #define BGE_RX_RULES_CFG 0x0500
523 #define BGE_RX_STATS 0x0800
524 #define BGE_TX_STATS 0x0880
526 /* Ethernet MAC Mode register */
527 #define BGE_MACMODE_RESET 0x00000001
528 #define BGE_MACMODE_HALF_DUPLEX 0x00000002
529 #define BGE_MACMODE_PORTMODE 0x0000000C
530 #define BGE_MACMODE_LOOPBACK 0x00000010
531 #define BGE_MACMODE_RX_TAGGEDPKT 0x00000080
532 #define BGE_MACMODE_TX_BURST_ENB 0x00000100
533 #define BGE_MACMODE_MAX_DEFER 0x00000200
534 #define BGE_MACMODE_LINK_POLARITY 0x00000400
535 #define BGE_MACMODE_RX_STATS_ENB 0x00000800
536 #define BGE_MACMODE_RX_STATS_CLEAR 0x00001000
537 #define BGE_MACMODE_RX_STATS_FLUSH 0x00002000
538 #define BGE_MACMODE_TX_STATS_ENB 0x00004000
539 #define BGE_MACMODE_TX_STATS_CLEAR 0x00008000
540 #define BGE_MACMODE_TX_STATS_FLUSH 0x00010000
541 #define BGE_MACMODE_TBI_SEND_CFGS 0x00020000
542 #define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000
543 #define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000
544 #define BGE_MACMODE_MIP_ENB 0x00100000
545 #define BGE_MACMODE_TXDMA_ENB 0x00200000
546 #define BGE_MACMODE_RXDMA_ENB 0x00400000
547 #define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000
549 #define BGE_PORTMODE_NONE 0x00000000
550 #define BGE_PORTMODE_MII 0x00000004
551 #define BGE_PORTMODE_GMII 0x00000008
552 #define BGE_PORTMODE_TBI 0x0000000C
554 /* MAC Status register */
555 #define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001
556 #define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002
557 #define BGE_MACSTAT_RX_CFG 0x00000004
558 #define BGE_MACSTAT_CFG_CHANGED 0x00000008
559 #define BGE_MACSTAT_SYNC_CHANGED 0x00000010
560 #define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400
561 #define BGE_MACSTAT_LINK_CHANGED 0x00001000
562 #define BGE_MACSTAT_MI_COMPLETE 0x00400000
563 #define BGE_MACSTAT_MI_INTERRUPT 0x00800000
564 #define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000
565 #define BGE_MACSTAT_ODI_ERROR 0x02000000
566 #define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000
567 #define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000
569 /* MAC Event Enable Register */
570 #define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400
571 #define BGE_EVTENB_LINK_CHANGED 0x00001000
572 #define BGE_EVTENB_MI_COMPLETE 0x00400000
573 #define BGE_EVTENB_MI_INTERRUPT 0x00800000
574 #define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000
575 #define BGE_EVTENB_ODI_ERROR 0x02000000
576 #define BGE_EVTENB_RXSTAT_OFLOW 0x04000000
577 #define BGE_EVTENB_TXSTAT_OFLOW 0x08000000
579 /* LED Control Register */
580 #define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001
581 #define BGE_LEDCTL_1000MBPS_LED 0x00000002
582 #define BGE_LEDCTL_100MBPS_LED 0x00000004
583 #define BGE_LEDCTL_10MBPS_LED 0x00000008
584 #define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010
585 #define BGE_LEDCTL_TRAFLED_BLINK 0x00000020
586 #define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040
587 #define BGE_LEDCTL_1000MBPS_STS 0x00000080
588 #define BGE_LEDCTL_100MBPS_STS 0x00000100
589 #define BGE_LEDCTL_10MBPS_STS 0x00000200
590 #define BGE_LEDCTL_TRADLED_STS 0x00000400
591 #define BGE_LEDCTL_BLINKPERIOD 0x7FF80000
592 #define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000
594 /* TX backoff seed register */
595 #define BGE_TX_BACKOFF_SEED_MASK 0x3F
597 /* Autopoll status register */
598 #define BGE_AUTOPOLLSTS_ERROR 0x00000001
600 /* Transmit MAC mode register */
601 #define BGE_TXMODE_RESET 0x00000001
602 #define BGE_TXMODE_ENABLE 0x00000002
603 #define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010
604 #define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020
605 #define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040
607 /* Transmit MAC status register */
608 #define BGE_TXSTAT_RX_XOFFED 0x00000001
609 #define BGE_TXSTAT_SENT_XOFF 0x00000002
610 #define BGE_TXSTAT_SENT_XON 0x00000004
611 #define BGE_TXSTAT_LINK_UP 0x00000008
612 #define BGE_TXSTAT_ODI_UFLOW 0x00000010
613 #define BGE_TXSTAT_ODI_OFLOW 0x00000020
615 /* Transmit MAC lengths register */
616 #define BGE_TXLEN_SLOTTIME 0x000000FF
617 #define BGE_TXLEN_IPG 0x00000F00
618 #define BGE_TXLEN_CRS 0x00003000
620 /* Receive MAC mode register */
621 #define BGE_RXMODE_RESET 0x00000001
622 #define BGE_RXMODE_ENABLE 0x00000002
623 #define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004
624 #define BGE_RXMODE_RX_GIANTS 0x00000020
625 #define BGE_RXMODE_RX_RUNTS 0x00000040
626 #define BGE_RXMODE_8022_LENCHECK 0x00000080
627 #define BGE_RXMODE_RX_PROMISC 0x00000100
628 #define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200
629 #define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400
631 /* Receive MAC status register */
632 #define BGE_RXSTAT_REMOTE_XOFFED 0x00000001
633 #define BGE_RXSTAT_RCVD_XOFF 0x00000002
634 #define BGE_RXSTAT_RCVD_XON 0x00000004
636 /* Receive Rules Control register */
637 #define BGE_RXRULECTL_OFFSET 0x000000FF
638 #define BGE_RXRULECTL_CLASS 0x00001F00
639 #define BGE_RXRULECTL_HDRTYPE 0x0000E000
640 #define BGE_RXRULECTL_COMPARE_OP 0x00030000
641 #define BGE_RXRULECTL_MAP 0x01000000
642 #define BGE_RXRULECTL_DISCARD 0x02000000
643 #define BGE_RXRULECTL_MASK 0x04000000
644 #define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000
645 #define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000
646 #define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000
647 #define BGE_RXRULECTL_ANDWITHNEXT 0x40000000
649 /* Receive Rules Mask register */
650 #define BGE_RXRULEMASK_VALUE 0x0000FFFF
651 #define BGE_RXRULEMASK_MASKVAL 0xFFFF0000
653 /* MI communication register */
654 #define BGE_MICOMM_DATA 0x0000FFFF
655 #define BGE_MICOMM_REG 0x001F0000
656 #define BGE_MICOMM_PHY 0x03E00000
657 #define BGE_MICOMM_CMD 0x0C000000
658 #define BGE_MICOMM_READFAIL 0x10000000
659 #define BGE_MICOMM_BUSY 0x20000000
661 #define BGE_MIREG(x) ((x & 0x1F) << 16)
662 #define BGE_MIPHY(x) ((x & 0x1F) << 21)
663 #define BGE_MICMD_WRITE 0x04000000
664 #define BGE_MICMD_READ 0x08000000
666 /* MI status register */
667 #define BGE_MISTS_LINK 0x00000001
668 #define BGE_MISTS_10MBPS 0x00000002
670 #define BGE_MIMODE_SHORTPREAMBLE 0x00000002
671 #define BGE_MIMODE_AUTOPOLL 0x00000010
672 #define BGE_MIMODE_CLKCNT 0x001F0000
676 * Send data initiator control registers.
678 #define BGE_SDI_MODE 0x0C00
679 #define BGE_SDI_STATUS 0x0C04
680 #define BGE_SDI_STATS_CTL 0x0C08
681 #define BGE_SDI_STATS_ENABLE_MASK 0x0C0C
682 #define BGE_SDI_STATS_INCREMENT_MASK 0x0C10
683 #define BGE_LOCSTATS_COS0 0x0C80
684 #define BGE_LOCSTATS_COS1 0x0C84
685 #define BGE_LOCSTATS_COS2 0x0C88
686 #define BGE_LOCSTATS_COS3 0x0C8C
687 #define BGE_LOCSTATS_COS4 0x0C90
688 #define BGE_LOCSTATS_COS5 0x0C84
689 #define BGE_LOCSTATS_COS6 0x0C98
690 #define BGE_LOCSTATS_COS7 0x0C9C
691 #define BGE_LOCSTATS_COS8 0x0CA0
692 #define BGE_LOCSTATS_COS9 0x0CA4
693 #define BGE_LOCSTATS_COS10 0x0CA8
694 #define BGE_LOCSTATS_COS11 0x0CAC
695 #define BGE_LOCSTATS_COS12 0x0CB0
696 #define BGE_LOCSTATS_COS13 0x0CB4
697 #define BGE_LOCSTATS_COS14 0x0CB8
698 #define BGE_LOCSTATS_COS15 0x0CBC
699 #define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0
700 #define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4
701 #define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8
702 #define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC
703 #define BGE_LOCSTATS_STATS_UPDATED 0x0CD0
704 #define BGE_LOCSTATS_IRQS 0x0CD4
705 #define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8
706 #define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC
708 /* Send Data Initiator mode register */
709 #define BGE_SDIMODE_RESET 0x00000001
710 #define BGE_SDIMODE_ENABLE 0x00000002
711 #define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004
713 /* Send Data Initiator stats register */
714 #define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004
716 /* Send Data Initiator stats control register */
717 #define BGE_SDISTATSCTL_ENABLE 0x00000001
718 #define BGE_SDISTATSCTL_FASTER 0x00000002
719 #define BGE_SDISTATSCTL_CLEAR 0x00000004
720 #define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008
721 #define BGE_SDISTATSCTL_FORCEZERO 0x00000010
724 * Send Data Completion Control registers
726 #define BGE_SDC_MODE 0x1000
727 #define BGE_SDC_STATUS 0x1004
729 /* Send Data completion mode register */
730 #define BGE_SDCMODE_RESET 0x00000001
731 #define BGE_SDCMODE_ENABLE 0x00000002
732 #define BGE_SDCMODE_ATTN 0x00000004
734 /* Send Data completion status register */
735 #define BGE_SDCSTAT_ATTN 0x00000004
738 * Send BD Ring Selector Control registers
740 #define BGE_SRS_MODE 0x1400
741 #define BGE_SRS_STATUS 0x1404
742 #define BGE_SRS_HWDIAG 0x1408
743 #define BGE_SRS_LOC_NIC_CONS0 0x1440
744 #define BGE_SRS_LOC_NIC_CONS1 0x1444
745 #define BGE_SRS_LOC_NIC_CONS2 0x1448
746 #define BGE_SRS_LOC_NIC_CONS3 0x144C
747 #define BGE_SRS_LOC_NIC_CONS4 0x1450
748 #define BGE_SRS_LOC_NIC_CONS5 0x1454
749 #define BGE_SRS_LOC_NIC_CONS6 0x1458
750 #define BGE_SRS_LOC_NIC_CONS7 0x145C
751 #define BGE_SRS_LOC_NIC_CONS8 0x1460
752 #define BGE_SRS_LOC_NIC_CONS9 0x1464
753 #define BGE_SRS_LOC_NIC_CONS10 0x1468
754 #define BGE_SRS_LOC_NIC_CONS11 0x146C
755 #define BGE_SRS_LOC_NIC_CONS12 0x1470
756 #define BGE_SRS_LOC_NIC_CONS13 0x1474
757 #define BGE_SRS_LOC_NIC_CONS14 0x1478
758 #define BGE_SRS_LOC_NIC_CONS15 0x147C
760 /* Send BD Ring Selector Mode register */
761 #define BGE_SRSMODE_RESET 0x00000001
762 #define BGE_SRSMODE_ENABLE 0x00000002
763 #define BGE_SRSMODE_ATTN 0x00000004
765 /* Send BD Ring Selector Status register */
766 #define BGE_SRSSTAT_ERROR 0x00000004
768 /* Send BD Ring Selector HW Diagnostics register */
769 #define BGE_SRSHWDIAG_STATE 0x0000000F
770 #define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0
771 #define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00
772 #define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000
775 * Send BD Initiator Selector Control registers
777 #define BGE_SBDI_MODE 0x1800
778 #define BGE_SBDI_STATUS 0x1804
779 #define BGE_SBDI_LOC_NIC_PROD0 0x1808
780 #define BGE_SBDI_LOC_NIC_PROD1 0x180C
781 #define BGE_SBDI_LOC_NIC_PROD2 0x1810
782 #define BGE_SBDI_LOC_NIC_PROD3 0x1814
783 #define BGE_SBDI_LOC_NIC_PROD4 0x1818
784 #define BGE_SBDI_LOC_NIC_PROD5 0x181C
785 #define BGE_SBDI_LOC_NIC_PROD6 0x1820
786 #define BGE_SBDI_LOC_NIC_PROD7 0x1824
787 #define BGE_SBDI_LOC_NIC_PROD8 0x1828
788 #define BGE_SBDI_LOC_NIC_PROD9 0x182C
789 #define BGE_SBDI_LOC_NIC_PROD10 0x1830
790 #define BGE_SBDI_LOC_NIC_PROD11 0x1834
791 #define BGE_SBDI_LOC_NIC_PROD12 0x1838
792 #define BGE_SBDI_LOC_NIC_PROD13 0x183C
793 #define BGE_SBDI_LOC_NIC_PROD14 0x1840
794 #define BGE_SBDI_LOC_NIC_PROD15 0x1844
796 /* Send BD Initiator Mode register */
797 #define BGE_SBDIMODE_RESET 0x00000001
798 #define BGE_SBDIMODE_ENABLE 0x00000002
799 #define BGE_SBDIMODE_ATTN 0x00000004
801 /* Send BD Initiator Status register */
802 #define BGE_SBDISTAT_ERROR 0x00000004
805 * Send BD Completion Control registers
807 #define BGE_SBDC_MODE 0x1C00
808 #define BGE_SBDC_STATUS 0x1C04
810 /* Send BD Completion Control Mode register */
811 #define BGE_SBDCMODE_RESET 0x00000001
812 #define BGE_SBDCMODE_ENABLE 0x00000002
813 #define BGE_SBDCMODE_ATTN 0x00000004
815 /* Send BD Completion Control Status register */
816 #define BGE_SBDCSTAT_ATTN 0x00000004
819 * Receive List Placement Control registers
821 #define BGE_RXLP_MODE 0x2000
822 #define BGE_RXLP_STATUS 0x2004
823 #define BGE_RXLP_SEL_LIST_LOCK 0x2008
824 #define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C
825 #define BGE_RXLP_CFG 0x2010
826 #define BGE_RXLP_STATS_CTL 0x2014
827 #define BGE_RXLP_STATS_ENABLE_MASK 0x2018
828 #define BGE_RXLP_STATS_INCREMENT_MASK 0x201C
829 #define BGE_RXLP_HEAD0 0x2100
830 #define BGE_RXLP_TAIL0 0x2104
831 #define BGE_RXLP_COUNT0 0x2108
832 #define BGE_RXLP_HEAD1 0x2110
833 #define BGE_RXLP_TAIL1 0x2114
834 #define BGE_RXLP_COUNT1 0x2118
835 #define BGE_RXLP_HEAD2 0x2120
836 #define BGE_RXLP_TAIL2 0x2124
837 #define BGE_RXLP_COUNT2 0x2128
838 #define BGE_RXLP_HEAD3 0x2130
839 #define BGE_RXLP_TAIL3 0x2134
840 #define BGE_RXLP_COUNT3 0x2138
841 #define BGE_RXLP_HEAD4 0x2140
842 #define BGE_RXLP_TAIL4 0x2144
843 #define BGE_RXLP_COUNT4 0x2148
844 #define BGE_RXLP_HEAD5 0x2150
845 #define BGE_RXLP_TAIL5 0x2154
846 #define BGE_RXLP_COUNT5 0x2158
847 #define BGE_RXLP_HEAD6 0x2160
848 #define BGE_RXLP_TAIL6 0x2164
849 #define BGE_RXLP_COUNT6 0x2168
850 #define BGE_RXLP_HEAD7 0x2170
851 #define BGE_RXLP_TAIL7 0x2174
852 #define BGE_RXLP_COUNT7 0x2178
853 #define BGE_RXLP_HEAD8 0x2180
854 #define BGE_RXLP_TAIL8 0x2184
855 #define BGE_RXLP_COUNT8 0x2188
856 #define BGE_RXLP_HEAD9 0x2190
857 #define BGE_RXLP_TAIL9 0x2194
858 #define BGE_RXLP_COUNT9 0x2198
859 #define BGE_RXLP_HEAD10 0x21A0
860 #define BGE_RXLP_TAIL10 0x21A4
861 #define BGE_RXLP_COUNT10 0x21A8
862 #define BGE_RXLP_HEAD11 0x21B0
863 #define BGE_RXLP_TAIL11 0x21B4
864 #define BGE_RXLP_COUNT11 0x21B8
865 #define BGE_RXLP_HEAD12 0x21C0
866 #define BGE_RXLP_TAIL12 0x21C4
867 #define BGE_RXLP_COUNT12 0x21C8
868 #define BGE_RXLP_HEAD13 0x21D0
869 #define BGE_RXLP_TAIL13 0x21D4
870 #define BGE_RXLP_COUNT13 0x21D8
871 #define BGE_RXLP_HEAD14 0x21E0
872 #define BGE_RXLP_TAIL14 0x21E4
873 #define BGE_RXLP_COUNT14 0x21E8
874 #define BGE_RXLP_HEAD15 0x21F0
875 #define BGE_RXLP_TAIL15 0x21F4
876 #define BGE_RXLP_COUNT15 0x21F8
877 #define BGE_RXLP_LOCSTAT_COS0 0x2200
878 #define BGE_RXLP_LOCSTAT_COS1 0x2204
879 #define BGE_RXLP_LOCSTAT_COS2 0x2208
880 #define BGE_RXLP_LOCSTAT_COS3 0x220C
881 #define BGE_RXLP_LOCSTAT_COS4 0x2210
882 #define BGE_RXLP_LOCSTAT_COS5 0x2214
883 #define BGE_RXLP_LOCSTAT_COS6 0x2218
884 #define BGE_RXLP_LOCSTAT_COS7 0x221C
885 #define BGE_RXLP_LOCSTAT_COS8 0x2220
886 #define BGE_RXLP_LOCSTAT_COS9 0x2224
887 #define BGE_RXLP_LOCSTAT_COS10 0x2228
888 #define BGE_RXLP_LOCSTAT_COS11 0x222C
889 #define BGE_RXLP_LOCSTAT_COS12 0x2230
890 #define BGE_RXLP_LOCSTAT_COS13 0x2234
891 #define BGE_RXLP_LOCSTAT_COS14 0x2238
892 #define BGE_RXLP_LOCSTAT_COS15 0x223C
893 #define BGE_RXLP_LOCSTAT_FILTDROP 0x2240
894 #define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244
895 #define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248
896 #define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C
897 #define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250
898 #define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254
899 #define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258
902 /* Receive List Placement mode register */
903 #define BGE_RXLPMODE_RESET 0x00000001
904 #define BGE_RXLPMODE_ENABLE 0x00000002
905 #define BGE_RXLPMODE_CLASS0_ATTN 0x00000004
906 #define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008
907 #define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010
909 /* Receive List Placement Status register */
910 #define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004
911 #define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008
912 #define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010
915 * Receive Data and Receive BD Initiator Control Registers
917 #define BGE_RDBDI_MODE 0x2400
918 #define BGE_RDBDI_STATUS 0x2404
919 #define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440
920 #define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444
921 #define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448
922 #define BGE_RX_JUMBO_RCB_NICADDR 0x244C
923 #define BGE_RX_STD_RCB_HADDR_HI 0x2450
924 #define BGE_RX_STD_RCB_HADDR_LO 0x2454
925 #define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458
926 #define BGE_RX_STD_RCB_NICADDR 0x245C
927 #define BGE_RX_MINI_RCB_HADDR_HI 0x2460
928 #define BGE_RX_MINI_RCB_HADDR_LO 0x2464
929 #define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468
930 #define BGE_RX_MINI_RCB_NICADDR 0x246C
931 #define BGE_RDBDI_JUMBO_RX_CONS 0x2470
932 #define BGE_RDBDI_STD_RX_CONS 0x2474
933 #define BGE_RDBDI_MINI_RX_CONS 0x2478
934 #define BGE_RDBDI_RETURN_PROD0 0x2480
935 #define BGE_RDBDI_RETURN_PROD1 0x2484
936 #define BGE_RDBDI_RETURN_PROD2 0x2488
937 #define BGE_RDBDI_RETURN_PROD3 0x248C
938 #define BGE_RDBDI_RETURN_PROD4 0x2490
939 #define BGE_RDBDI_RETURN_PROD5 0x2494
940 #define BGE_RDBDI_RETURN_PROD6 0x2498
941 #define BGE_RDBDI_RETURN_PROD7 0x249C
942 #define BGE_RDBDI_RETURN_PROD8 0x24A0
943 #define BGE_RDBDI_RETURN_PROD9 0x24A4
944 #define BGE_RDBDI_RETURN_PROD10 0x24A8
945 #define BGE_RDBDI_RETURN_PROD11 0x24AC
946 #define BGE_RDBDI_RETURN_PROD12 0x24B0
947 #define BGE_RDBDI_RETURN_PROD13 0x24B4
948 #define BGE_RDBDI_RETURN_PROD14 0x24B8
949 #define BGE_RDBDI_RETURN_PROD15 0x24BC
950 #define BGE_RDBDI_HWDIAG 0x24C0
953 /* Receive Data and Receive BD Initiator Mode register */
954 #define BGE_RDBDIMODE_RESET 0x00000001
955 #define BGE_RDBDIMODE_ENABLE 0x00000002
956 #define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004
957 #define BGE_RDBDIMODE_GIANT_ATTN 0x00000008
958 #define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010
960 /* Receive Data and Receive BD Initiator Status register */
961 #define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004
962 #define BGE_RDBDISTAT_GIANT_ATTN 0x00000008
963 #define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010
967 * Receive Data Completion Control registers
969 #define BGE_RDC_MODE 0x2800
971 /* Receive Data Completion Mode register */
972 #define BGE_RDCMODE_RESET 0x00000001
973 #define BGE_RDCMODE_ENABLE 0x00000002
974 #define BGE_RDCMODE_ATTN 0x00000004
977 * Receive BD Initiator Control registers
979 #define BGE_RBDI_MODE 0x2C00
980 #define BGE_RBDI_STATUS 0x2C04
981 #define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08
982 #define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C
983 #define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10
984 #define BGE_RBDI_MINI_REPL_THRESH 0x2C14
985 #define BGE_RBDI_STD_REPL_THRESH 0x2C18
986 #define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C
988 /* Receive BD Initiator Mode register */
989 #define BGE_RBDIMODE_RESET 0x00000001
990 #define BGE_RBDIMODE_ENABLE 0x00000002
991 #define BGE_RBDIMODE_ATTN 0x00000004
993 /* Receive BD Initiator Status register */
994 #define BGE_RBDISTAT_ATTN 0x00000004
997 * Receive BD Completion Control registers
999 #define BGE_RBDC_MODE 0x3000
1000 #define BGE_RBDC_STATUS 0x3004
1001 #define BGE_RBDC_JUMBO_BD_PROD 0x3008
1002 #define BGE_RBDC_STD_BD_PROD 0x300C
1003 #define BGE_RBDC_MINI_BD_PROD 0x3010
1005 /* Receive BD completion mode register */
1006 #define BGE_RBDCMODE_RESET 0x00000001
1007 #define BGE_RBDCMODE_ENABLE 0x00000002
1008 #define BGE_RBDCMODE_ATTN 0x00000004
1010 /* Receive BD completion status register */
1011 #define BGE_RBDCSTAT_ERROR 0x00000004
1014 * Receive List Selector Control registers
1016 #define BGE_RXLS_MODE 0x3400
1017 #define BGE_RXLS_STATUS 0x3404
1019 /* Receive List Selector Mode register */
1020 #define BGE_RXLSMODE_RESET 0x00000001
1021 #define BGE_RXLSMODE_ENABLE 0x00000002
1022 #define BGE_RXLSMODE_ATTN 0x00000004
1024 /* Receive List Selector Status register */
1025 #define BGE_RXLSSTAT_ERROR 0x00000004
1028 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs)
1030 #define BGE_MBCF_MODE 0x3800
1031 #define BGE_MBCF_STATUS 0x3804
1033 /* Mbuf Cluster Free mode register */
1034 #define BGE_MBCFMODE_RESET 0x00000001
1035 #define BGE_MBCFMODE_ENABLE 0x00000002
1036 #define BGE_MBCFMODE_ATTN 0x00000004
1038 /* Mbuf Cluster Free status register */
1039 #define BGE_MBCFSTAT_ERROR 0x00000004
1042 * Host Coalescing Control registers
1044 #define BGE_HCC_MODE 0x3C00
1045 #define BGE_HCC_STATUS 0x3C04
1046 #define BGE_HCC_RX_COAL_TICKS 0x3C08
1047 #define BGE_HCC_TX_COAL_TICKS 0x3C0C
1048 #define BGE_HCC_RX_MAX_COAL_BDS 0x3C10
1049 #define BGE_HCC_TX_MAX_COAL_BDS 0x3C14
1050 #define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */
1051 #define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */
1052 #define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */
1053 #define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C34 /* BDs during interrupt */
1054 #define BGE_HCC_STATS_TICKS 0x3C28
1055 #define BGE_HCC_STATS_ADDR_HI 0x3C30
1056 #define BGE_HCC_STATS_ADDR_LO 0x3C34
1057 #define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38
1058 #define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C
1059 #define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */
1060 #define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */
1061 #define BGE_FLOW_ATTN 0x3C48
1062 #define BGE_HCC_JUMBO_BD_CONS 0x3C50
1063 #define BGE_HCC_STD_BD_CONS 0x3C54
1064 #define BGE_HCC_MINI_BD_CONS 0x3C58
1065 #define BGE_HCC_RX_RETURN_PROD0 0x3C80
1066 #define BGE_HCC_RX_RETURN_PROD1 0x3C84
1067 #define BGE_HCC_RX_RETURN_PROD2 0x3C88
1068 #define BGE_HCC_RX_RETURN_PROD3 0x3C8C
1069 #define BGE_HCC_RX_RETURN_PROD4 0x3C90
1070 #define BGE_HCC_RX_RETURN_PROD5 0x3C94
1071 #define BGE_HCC_RX_RETURN_PROD6 0x3C98
1072 #define BGE_HCC_RX_RETURN_PROD7 0x3C9C
1073 #define BGE_HCC_RX_RETURN_PROD8 0x3CA0
1074 #define BGE_HCC_RX_RETURN_PROD9 0x3CA4
1075 #define BGE_HCC_RX_RETURN_PROD10 0x3CA8
1076 #define BGE_HCC_RX_RETURN_PROD11 0x3CAC
1077 #define BGE_HCC_RX_RETURN_PROD12 0x3CB0
1078 #define BGE_HCC_RX_RETURN_PROD13 0x3CB4
1079 #define BGE_HCC_RX_RETURN_PROD14 0x3CB8
1080 #define BGE_HCC_RX_RETURN_PROD15 0x3CBC
1081 #define BGE_HCC_TX_BD_CONS0 0x3CC0
1082 #define BGE_HCC_TX_BD_CONS1 0x3CC4
1083 #define BGE_HCC_TX_BD_CONS2 0x3CC8
1084 #define BGE_HCC_TX_BD_CONS3 0x3CCC
1085 #define BGE_HCC_TX_BD_CONS4 0x3CD0
1086 #define BGE_HCC_TX_BD_CONS5 0x3CD4
1087 #define BGE_HCC_TX_BD_CONS6 0x3CD8
1088 #define BGE_HCC_TX_BD_CONS7 0x3CDC
1089 #define BGE_HCC_TX_BD_CONS8 0x3CE0
1090 #define BGE_HCC_TX_BD_CONS9 0x3CE4
1091 #define BGE_HCC_TX_BD_CONS10 0x3CE8
1092 #define BGE_HCC_TX_BD_CONS11 0x3CEC
1093 #define BGE_HCC_TX_BD_CONS12 0x3CF0
1094 #define BGE_HCC_TX_BD_CONS13 0x3CF4
1095 #define BGE_HCC_TX_BD_CONS14 0x3CF8
1096 #define BGE_HCC_TX_BD_CONS15 0x3CFC
1099 /* Host coalescing mode register */
1100 #define BGE_HCCMODE_RESET 0x00000001
1101 #define BGE_HCCMODE_ENABLE 0x00000002
1102 #define BGE_HCCMODE_ATTN 0x00000004
1103 #define BGE_HCCMODE_COAL_NOW 0x00000008
1104 #define BGE_HCCMODE_MSI_BITS 0x0x000070
1105 #define BGE_HCCMODE_STATBLK_SIZE 0x00000180
1107 #define BGE_STATBLKSZ_FULL 0x00000000
1108 #define BGE_STATBLKSZ_64BYTE 0x00000080
1109 #define BGE_STATBLKSZ_32BYTE 0x00000100
1111 /* Host coalescing status register */
1112 #define BGE_HCCSTAT_ERROR 0x00000004
1114 /* Flow attention register */
1115 #define BGE_FLOWATTN_MB_LOWAT 0x00000040
1116 #define BGE_FLOWATTN_MEMARB 0x00000080
1117 #define BGE_FLOWATTN_HOSTCOAL 0x00008000
1118 #define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000
1119 #define BGE_FLOWATTN_RCB_INVAL 0x00020000
1120 #define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000
1121 #define BGE_FLOWATTN_RDBDI 0x00080000
1122 #define BGE_FLOWATTN_RXLS 0x00100000
1123 #define BGE_FLOWATTN_RXLP 0x00200000
1124 #define BGE_FLOWATTN_RBDC 0x00400000
1125 #define BGE_FLOWATTN_RBDI 0x00800000
1126 #define BGE_FLOWATTN_SDC 0x08000000
1127 #define BGE_FLOWATTN_SDI 0x10000000
1128 #define BGE_FLOWATTN_SRS 0x20000000
1129 #define BGE_FLOWATTN_SBDC 0x40000000
1130 #define BGE_FLOWATTN_SBDI 0x80000000
1133 * Memory arbiter registers
1135 #define BGE_MARB_MODE 0x4000
1136 #define BGE_MARB_STATUS 0x4004
1137 #define BGE_MARB_TRAPADDR_HI 0x4008
1138 #define BGE_MARB_TRAPADDR_LO 0x400C
1140 /* Memory arbiter mode register */
1141 #define BGE_MARBMODE_RESET 0x00000001
1142 #define BGE_MARBMODE_ENABLE 0x00000002
1143 #define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004
1144 #define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008
1145 #define BGE_MARBMODE_DMAW1_TRAP 0x00000010
1146 #define BGE_MARBMODE_DMAR1_TRAP 0x00000020
1147 #define BGE_MARBMODE_RXRISC_TRAP 0x00000040
1148 #define BGE_MARBMODE_TXRISC_TRAP 0x00000080
1149 #define BGE_MARBMODE_PCI_TRAP 0x00000100
1150 #define BGE_MARBMODE_DMAR2_TRAP 0x00000200
1151 #define BGE_MARBMODE_RXQ_TRAP 0x00000400
1152 #define BGE_MARBMODE_RXDI1_TRAP 0x00000800
1153 #define BGE_MARBMODE_RXDI2_TRAP 0x00001000
1154 #define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000
1155 #define BGE_MARBMODE_HCOAL_TRAP 0x00004000
1156 #define BGE_MARBMODE_MBUF_TRAP 0x00008000
1157 #define BGE_MARBMODE_TXDI_TRAP 0x00010000
1158 #define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000
1159 #define BGE_MARBMODE_TXBD_TRAP 0x00040000
1160 #define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000
1161 #define BGE_MARBMODE_DMAW2_TRAP 0x00100000
1162 #define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000
1163 #define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000
1164 #define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000
1165 #define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000
1166 #define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000
1168 /* Memory arbiter status register */
1169 #define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004
1170 #define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008
1171 #define BGE_MARBSTAT_DMAW1_TRAP 0x00000010
1172 #define BGE_MARBSTAT_DMAR1_TRAP 0x00000020
1173 #define BGE_MARBSTAT_RXRISC_TRAP 0x00000040
1174 #define BGE_MARBSTAT_TXRISC_TRAP 0x00000080
1175 #define BGE_MARBSTAT_PCI_TRAP 0x00000100
1176 #define BGE_MARBSTAT_DMAR2_TRAP 0x00000200
1177 #define BGE_MARBSTAT_RXQ_TRAP 0x00000400
1178 #define BGE_MARBSTAT_RXDI1_TRAP 0x00000800
1179 #define BGE_MARBSTAT_RXDI2_TRAP 0x00001000
1180 #define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000
1181 #define BGE_MARBSTAT_HCOAL_TRAP 0x00004000
1182 #define BGE_MARBSTAT_MBUF_TRAP 0x00008000
1183 #define BGE_MARBSTAT_TXDI_TRAP 0x00010000
1184 #define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000
1185 #define BGE_MARBSTAT_TXBD_TRAP 0x00040000
1186 #define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000
1187 #define BGE_MARBSTAT_DMAW2_TRAP 0x00100000
1188 #define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000
1189 #define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000
1190 #define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000
1191 #define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000
1192 #define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000
1195 * Buffer manager control registers
1197 #define BGE_BMAN_MODE 0x4400
1198 #define BGE_BMAN_STATUS 0x4404
1199 #define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408
1200 #define BGE_BMAN_MBUFPOOL_LEN 0x440C
1201 #define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410
1202 #define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414
1203 #define BGE_BMAN_MBUFPOOL_HIWAT 0x4418
1204 #define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C
1205 #define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420
1206 #define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424
1207 #define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428
1208 #define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C
1209 #define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430
1210 #define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434
1211 #define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438
1212 #define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C
1213 #define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440
1214 #define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444
1215 #define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448
1216 #define BGE_BMAN_HWDIAG_1 0x444C
1217 #define BGE_BMAN_HWDIAG_2 0x4450
1218 #define BGE_BMAN_HWDIAG_3 0x4454
1220 /* Buffer manager mode register */
1221 #define BGE_BMANMODE_RESET 0x00000001
1222 #define BGE_BMANMODE_ENABLE 0x00000002
1223 #define BGE_BMANMODE_ATTN 0x00000004
1224 #define BGE_BMANMODE_TESTMODE 0x00000008
1225 #define BGE_BMANMODE_LOMBUF_ATTN 0x00000010
1227 /* Buffer manager status register */
1228 #define BGE_BMANSTAT_ERRO 0x00000004
1229 #define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010
1233 * Read DMA Control registers
1235 #define BGE_RDMA_MODE 0x4800
1236 #define BGE_RDMA_STATUS 0x4804
1238 /* Read DMA mode register */
1239 #define BGE_RDMAMODE_RESET 0x00000001
1240 #define BGE_RDMAMODE_ENABLE 0x00000002
1241 #define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004
1242 #define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008
1243 #define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010
1244 #define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020
1245 #define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040
1246 #define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080
1247 #define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100
1248 #define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200
1249 #define BGE_RDMAMODE_ALL_ATTNS 0x000003FC
1251 /* Read DMA status register */
1252 #define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004
1253 #define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008
1254 #define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010
1255 #define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020
1256 #define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040
1257 #define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080
1258 #define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100
1259 #define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200
1262 * Write DMA control registers
1264 #define BGE_WDMA_MODE 0x4C00
1265 #define BGE_WDMA_STATUS 0x4C04
1267 /* Write DMA mode register */
1268 #define BGE_WDMAMODE_RESET 0x00000001
1269 #define BGE_WDMAMODE_ENABLE 0x00000002
1270 #define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004
1271 #define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008
1272 #define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010
1273 #define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020
1274 #define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040
1275 #define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080
1276 #define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100
1277 #define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200
1278 #define BGE_WDMAMODE_ALL_ATTNS 0x000003FC
1280 /* Write DMA status register */
1281 #define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004
1282 #define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008
1283 #define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010
1284 #define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020
1285 #define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040
1286 #define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080
1287 #define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100
1288 #define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200
1294 #define BGE_RXCPU_MODE 0x5000
1295 #define BGE_RXCPU_STATUS 0x5004
1296 #define BGE_RXCPU_PC 0x501C
1298 /* RX CPU mode register */
1299 #define BGE_RXCPUMODE_RESET 0x00000001
1300 #define BGE_RXCPUMODE_SINGLESTEP 0x00000002
1301 #define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004
1302 #define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008
1303 #define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010
1304 #define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020
1305 #define BGE_RXCPUMODE_ROMFAIL 0x00000040
1306 #define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080
1307 #define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100
1308 #define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200
1309 #define BGE_RXCPUMODE_HALTCPU 0x00000400
1310 #define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800
1311 #define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000
1312 #define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000
1314 /* RX CPU status register */
1315 #define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001
1316 #define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002
1317 #define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004
1318 #define BGE_RXCPUSTAT_P0_DATAREF 0x00000008
1319 #define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010
1320 #define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020
1321 #define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040
1322 #define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080
1323 #define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100
1324 #define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200
1325 #define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000
1326 #define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000
1327 #define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000
1328 #define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000
1329 #define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000
1330 #define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000
1331 #define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000
1337 #define BGE_TXCPU_MODE 0x5400
1338 #define BGE_TXCPU_STATUS 0x5404
1339 #define BGE_TXCPU_PC 0x541C
1341 /* TX CPU mode register */
1342 #define BGE_TXCPUMODE_RESET 0x00000001
1343 #define BGE_TXCPUMODE_SINGLESTEP 0x00000002
1344 #define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004
1345 #define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008
1346 #define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010
1347 #define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020
1348 #define BGE_TXCPUMODE_ROMFAIL 0x00000040
1349 #define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080
1350 #define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100
1351 #define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200
1352 #define BGE_TXCPUMODE_HALTCPU 0x00000400
1353 #define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800
1354 #define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000
1356 /* TX CPU status register */
1357 #define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001
1358 #define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002
1359 #define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004
1360 #define BGE_TXCPUSTAT_P0_DATAREF 0x00000008
1361 #define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010
1362 #define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020
1363 #define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040
1364 #define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080
1365 #define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100
1366 #define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200
1367 #define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000
1368 #define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000
1369 #define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000
1370 #define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000
1371 #define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000
1372 #define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000
1373 #define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000
1377 * Low priority mailbox registers
1379 #define BGE_LPMBX_IRQ0_HI 0x5800
1380 #define BGE_LPMBX_IRQ0_LO 0x5804
1381 #define BGE_LPMBX_IRQ1_HI 0x5808
1382 #define BGE_LPMBX_IRQ1_LO 0x580C
1383 #define BGE_LPMBX_IRQ2_HI 0x5810
1384 #define BGE_LPMBX_IRQ2_LO 0x5814
1385 #define BGE_LPMBX_IRQ3_HI 0x5818
1386 #define BGE_LPMBX_IRQ3_LO 0x581C
1387 #define BGE_LPMBX_GEN0_HI 0x5820
1388 #define BGE_LPMBX_GEN0_LO 0x5824
1389 #define BGE_LPMBX_GEN1_HI 0x5828
1390 #define BGE_LPMBX_GEN1_LO 0x582C
1391 #define BGE_LPMBX_GEN2_HI 0x5830
1392 #define BGE_LPMBX_GEN2_LO 0x5834
1393 #define BGE_LPMBX_GEN3_HI 0x5828
1394 #define BGE_LPMBX_GEN3_LO 0x582C
1395 #define BGE_LPMBX_GEN4_HI 0x5840
1396 #define BGE_LPMBX_GEN4_LO 0x5844
1397 #define BGE_LPMBX_GEN5_HI 0x5848
1398 #define BGE_LPMBX_GEN5_LO 0x584C
1399 #define BGE_LPMBX_GEN6_HI 0x5850
1400 #define BGE_LPMBX_GEN6_LO 0x5854
1401 #define BGE_LPMBX_GEN7_HI 0x5858
1402 #define BGE_LPMBX_GEN7_LO 0x585C
1403 #define BGE_LPMBX_RELOAD_STATS_HI 0x5860
1404 #define BGE_LPMBX_RELOAD_STATS_LO 0x5864
1405 #define BGE_LPMBX_RX_STD_PROD_HI 0x5868
1406 #define BGE_LPMBX_RX_STD_PROD_LO 0x586C
1407 #define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870
1408 #define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874
1409 #define BGE_LPMBX_RX_MINI_PROD_HI 0x5878
1410 #define BGE_LPMBX_RX_MINI_PROD_LO 0x587C
1411 #define BGE_LPMBX_RX_CONS0_HI 0x5880
1412 #define BGE_LPMBX_RX_CONS0_LO 0x5884
1413 #define BGE_LPMBX_RX_CONS1_HI 0x5888
1414 #define BGE_LPMBX_RX_CONS1_LO 0x588C
1415 #define BGE_LPMBX_RX_CONS2_HI 0x5890
1416 #define BGE_LPMBX_RX_CONS2_LO 0x5894
1417 #define BGE_LPMBX_RX_CONS3_HI 0x5898
1418 #define BGE_LPMBX_RX_CONS3_LO 0x589C
1419 #define BGE_LPMBX_RX_CONS4_HI 0x58A0
1420 #define BGE_LPMBX_RX_CONS4_LO 0x58A4
1421 #define BGE_LPMBX_RX_CONS5_HI 0x58A8
1422 #define BGE_LPMBX_RX_CONS5_LO 0x58AC
1423 #define BGE_LPMBX_RX_CONS6_HI 0x58B0
1424 #define BGE_LPMBX_RX_CONS6_LO 0x58B4
1425 #define BGE_LPMBX_RX_CONS7_HI 0x58B8
1426 #define BGE_LPMBX_RX_CONS7_LO 0x58BC
1427 #define BGE_LPMBX_RX_CONS8_HI 0x58C0
1428 #define BGE_LPMBX_RX_CONS8_LO 0x58C4
1429 #define BGE_LPMBX_RX_CONS9_HI 0x58C8
1430 #define BGE_LPMBX_RX_CONS9_LO 0x58CC
1431 #define BGE_LPMBX_RX_CONS10_HI 0x58D0
1432 #define BGE_LPMBX_RX_CONS10_LO 0x58D4
1433 #define BGE_LPMBX_RX_CONS11_HI 0x58D8
1434 #define BGE_LPMBX_RX_CONS11_LO 0x58DC
1435 #define BGE_LPMBX_RX_CONS12_HI 0x58E0
1436 #define BGE_LPMBX_RX_CONS12_LO 0x58E4
1437 #define BGE_LPMBX_RX_CONS13_HI 0x58E8
1438 #define BGE_LPMBX_RX_CONS13_LO 0x58EC
1439 #define BGE_LPMBX_RX_CONS14_HI 0x58F0
1440 #define BGE_LPMBX_RX_CONS14_LO 0x58F4
1441 #define BGE_LPMBX_RX_CONS15_HI 0x58F8
1442 #define BGE_LPMBX_RX_CONS15_LO 0x58FC
1443 #define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900
1444 #define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904
1445 #define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908
1446 #define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C
1447 #define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910
1448 #define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914
1449 #define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918
1450 #define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C
1451 #define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920
1452 #define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924
1453 #define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928
1454 #define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C
1455 #define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930
1456 #define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934
1457 #define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938
1458 #define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C
1459 #define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940
1460 #define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944
1461 #define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948
1462 #define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C
1463 #define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950
1464 #define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954
1465 #define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958
1466 #define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C
1467 #define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960
1468 #define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964
1469 #define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968
1470 #define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C
1471 #define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970
1472 #define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974
1473 #define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978
1474 #define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C
1475 #define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980
1476 #define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984
1477 #define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988
1478 #define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C
1479 #define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990
1480 #define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994
1481 #define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998
1482 #define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C
1483 #define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0
1484 #define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4
1485 #define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8
1486 #define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC
1487 #define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0
1488 #define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4
1489 #define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8
1490 #define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC
1491 #define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0
1492 #define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4
1493 #define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8
1494 #define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC
1495 #define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0
1496 #define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4
1497 #define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8
1498 #define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC
1499 #define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0
1500 #define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4
1501 #define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8
1502 #define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC
1503 #define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0
1504 #define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4
1505 #define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8
1506 #define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC
1509 * Flow throw Queue reset register
1511 #define BGE_FTQ_RESET 0x5C00
1513 #define BGE_FTQRESET_DMAREAD 0x00000002
1514 #define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004
1515 #define BGE_FTQRESET_DMADONE 0x00000010
1516 #define BGE_FTQRESET_SBDC 0x00000020
1517 #define BGE_FTQRESET_SDI 0x00000040
1518 #define BGE_FTQRESET_WDMA 0x00000080
1519 #define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100
1520 #define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200
1521 #define BGE_FTQRESET_SDC 0x00000400
1522 #define BGE_FTQRESET_HCC 0x00000800
1523 #define BGE_FTQRESET_TXFIFO 0x00001000
1524 #define BGE_FTQRESET_MBC 0x00002000
1525 #define BGE_FTQRESET_RBDC 0x00004000
1526 #define BGE_FTQRESET_RXLP 0x00008000
1527 #define BGE_FTQRESET_RDBDI 0x00010000
1528 #define BGE_FTQRESET_RDC 0x00020000
1529 #define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000
1532 * Message Signaled Interrupt registers
1534 #define BGE_MSI_MODE 0x6000
1535 #define BGE_MSI_STATUS 0x6004
1536 #define BGE_MSI_FIFOACCESS 0x6008
1538 /* MSI mode register */
1539 #define BGE_MSIMODE_RESET 0x00000001
1540 #define BGE_MSIMODE_ENABLE 0x00000002
1541 #define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004
1542 #define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008
1543 #define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010
1544 #define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020
1545 #define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040
1547 /* MSI status register */
1548 #define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004
1549 #define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008
1550 #define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010
1551 #define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020
1552 #define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040
1556 * DMA Completion registers
1558 #define BGE_DMAC_MODE 0x6400
1560 /* DMA Completion mode register */
1561 #define BGE_DMACMODE_RESET 0x00000001
1562 #define BGE_DMACMODE_ENABLE 0x00000002
1566 * General control registers.
1568 #define BGE_MODE_CTL 0x6800
1569 #define BGE_MISC_CFG 0x6804
1570 #define BGE_MISC_LOCAL_CTL 0x6808
1571 #define BGE_EE_ADDR 0x6838
1572 #define BGE_EE_DATA 0x683C
1573 #define BGE_EE_CTL 0x6840
1574 #define BGE_MDI_CTL 0x6844
1575 #define BGE_EE_DELAY 0x6848
1577 /* Mode control register */
1578 #define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001
1579 #define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002
1580 #define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004
1581 #define BGE_MODECTL_BYTESWAP_DATA 0x00000010
1582 #define BGE_MODECTL_WORDSWAP_DATA 0x00000020
1583 #define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200
1584 #define BGE_MODECTL_NO_RX_CRC 0x00000400
1585 #define BGE_MODECTL_RX_BADFRAMES 0x00000800
1586 #define BGE_MODECTL_NO_TX_INTR 0x00002000
1587 #define BGE_MODECTL_NO_RX_INTR 0x00004000
1588 #define BGE_MODECTL_FORCE_PCI32 0x00008000
1589 #define BGE_MODECTL_STACKUP 0x00010000
1590 #define BGE_MODECTL_HOST_SEND_BDS 0x00020000
1591 #define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000
1592 #define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000
1593 #define BGE_MODECTL_TX_ATTN_INTR 0x01000000
1594 #define BGE_MODECTL_RX_ATTN_INTR 0x02000000
1595 #define BGE_MODECTL_MAC_ATTN_INTR 0x04000000
1596 #define BGE_MODECTL_DMA_ATTN_INTR 0x08000000
1597 #define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000
1598 #define BGE_MODECTL_4X_SENDRING_SZ 0x20000000
1599 #define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000
1601 /* Misc. config register */
1602 #define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001
1603 #define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE
1605 #define BGE_32BITTIME_66MHZ (0x41 << 1)
1607 /* Misc. Local Control */
1608 #define BGE_MLC_INTR_STATE 0x00000001
1609 #define BGE_MLC_INTR_CLR 0x00000002
1610 #define BGE_MLC_INTR_SET 0x00000004
1611 #define BGE_MLC_INTR_ONATTN 0x00000008
1612 #define BGE_MLC_MISCIO_IN0 0x00000100
1613 #define BGE_MLC_MISCIO_IN1 0x00000200
1614 #define BGE_MLC_MISCIO_IN2 0x00000400
1615 #define BGE_MLC_MISCIO_OUTEN0 0x00000800
1616 #define BGE_MLC_MISCIO_OUTEN1 0x00001000
1617 #define BGE_MLC_MISCIO_OUTEN2 0x00002000
1618 #define BGE_MLC_MISCIO_OUT0 0x00004000
1619 #define BGE_MLC_MISCIO_OUT1 0x00008000
1620 #define BGE_MLC_MISCIO_OUT2 0x00010000
1621 #define BGE_MLC_EXTRAM_ENB 0x00020000
1622 #define BGE_MLC_SRAM_SIZE 0x001C0000
1623 #define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */
1624 #define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */
1625 #define BGE_MLC_SSRAM_CYC_DESEL 0x00800000
1626 #define BGE_MLC_AUTO_EEPROM 0x01000000
1628 #define BGE_SSRAMSIZE_256KB 0x00000000
1629 #define BGE_SSRAMSIZE_512KB 0x00040000
1630 #define BGE_SSRAMSIZE_1MB 0x00080000
1631 #define BGE_SSRAMSIZE_2MB 0x000C0000
1632 #define BGE_SSRAMSIZE_4MB 0x00100000
1633 #define BGE_SSRAMSIZE_8MB 0x00140000
1634 #define BGE_SSRAMSIZE_16M 0x00180000
1636 /* EEPROM address register */
1637 #define BGE_EEADDR_ADDRESS 0x0000FFFC
1638 #define BGE_EEADDR_HALFCLK 0x01FF0000
1639 #define BGE_EEADDR_START 0x02000000
1640 #define BGE_EEADDR_DEVID 0x1C000000
1641 #define BGE_EEADDR_RESET 0x20000000
1642 #define BGE_EEADDR_DONE 0x40000000
1643 #define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */
1645 #define BGE_EEDEVID(x) ((x & 7) << 26)
1646 #define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16)
1647 #define BGE_HALFCLK_384SCL 0x60
1648 #define BGE_EE_READCMD \
1649 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \
1650 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE)
1651 #define BGE_EE_WRCMD \
1652 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \
1653 BGE_EEADDR_START|BGE_EEADDR_DONE)
1655 /* EEPROM Control register */
1656 #define BGE_EECTL_CLKOUT_TRISTATE 0x00000001
1657 #define BGE_EECTL_CLKOUT 0x00000002
1658 #define BGE_EECTL_CLKIN 0x00000004
1659 #define BGE_EECTL_DATAOUT_TRISTATE 0x00000008
1660 #define BGE_EECTL_DATAOUT 0x00000010
1661 #define BGE_EECTL_DATAIN 0x00000020
1663 /* MDI (MII/GMII) access register */
1664 #define BGE_MDI_DATA 0x00000001
1665 #define BGE_MDI_DIR 0x00000002
1666 #define BGE_MDI_SEL 0x00000004
1667 #define BGE_MDI_CLK 0x00000008
1669 #define BGE_MEMWIN_START 0x00008000
1670 #define BGE_MEMWIN_END 0x0000FFFF
1673 #define BGE_MEMWIN_READ(sc, x, val) \
1675 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \
1676 (0xFFFF0000 & x), 4); \
1677 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \
1680 #define BGE_MEMWIN_WRITE(sc, x, val) \
1682 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \
1683 (0xFFFF0000 & x), 4); \
1684 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \
1688 * This magic number is used to prevent PXE restart when we
1689 * issue a software reset. We write this magic number to the
1690 * firmware mailbox at 0xB50 in order to prevent the PXE boot
1691 * code from running.
1693 #define BGE_MAGIC_NUMBER 0x4B657654
1696 u_int32_t bge_addr_hi;
1697 u_int32_t bge_addr_lo;
1699 #define BGE_HOSTADDR(x) ((x).bge_addr_lo)
1701 /* Ring control block structure */
1703 bge_hostaddr bge_hostaddr;
1704 u_int32_t bge_maxlen_flags;
1705 u_int32_t bge_nicaddr;
1707 #define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags))
1709 #define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001
1710 #define BGE_RCB_FLAG_RING_DISABLED 0x0002
1713 bge_hostaddr bge_addr;
1714 u_int16_t bge_flags;
1716 u_int16_t bge_vlan_tag;
1720 #define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001
1721 #define BGE_TXBDFLAG_IP_CSUM 0x0002
1722 #define BGE_TXBDFLAG_END 0x0004
1723 #define BGE_TXBDFLAG_IP_FRAG 0x0008
1724 #define BGE_TXBDFLAG_IP_FRAG_END 0x0010
1725 #define BGE_TXBDFLAG_VLAN_TAG 0x0040
1726 #define BGE_TXBDFLAG_COAL_NOW 0x0080
1727 #define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100
1728 #define BGE_TXBDFLAG_CPU_POST_DMA 0x0200
1729 #define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000
1730 #define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000
1731 #define BGE_TXBDFLAG_NO_CRC 0x8000
1733 #define BGE_NIC_TXRING_ADDR(ringno, size) \
1734 BGE_SEND_RING_1_TO_4 + \
1735 ((ringno * sizeof(struct bge_tx_bd) * size) / 4)
1738 bge_hostaddr bge_addr;
1741 u_int16_t bge_flags;
1743 u_int16_t bge_tcp_udp_csum;
1744 u_int16_t bge_ip_csum;
1745 u_int16_t bge_vlan_tag;
1746 u_int16_t bge_error_flag;
1748 u_int32_t bge_opaque;
1751 #define BGE_RXBDFLAG_END 0x0004
1752 #define BGE_RXBDFLAG_JUMBO_RING 0x0020
1753 #define BGE_RXBDFLAG_VLAN_TAG 0x0040
1754 #define BGE_RXBDFLAG_ERROR 0x0400
1755 #define BGE_RXBDFLAG_MINI_RING 0x0800
1756 #define BGE_RXBDFLAG_IP_CSUM 0x1000
1757 #define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000
1758 #define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000
1760 #define BGE_RXERRFLAG_BAD_CRC 0x0001
1761 #define BGE_RXERRFLAG_COLL_DETECT 0x0002
1762 #define BGE_RXERRFLAG_LINK_LOST 0x0004
1763 #define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008
1764 #define BGE_RXERRFLAG_MAC_ABORT 0x0010
1765 #define BGE_RXERRFLAG_RUNT 0x0020
1766 #define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040
1767 #define BGE_RXERRFLAG_GIANT 0x0080
1769 struct bge_sts_idx {
1770 u_int16_t bge_rx_prod_idx;
1771 u_int16_t bge_tx_cons_idx;
1774 struct bge_status_block {
1775 u_int32_t bge_status;
1776 u_int32_t bge_rsvd0;
1777 u_int16_t bge_rx_jumbo_cons_idx;
1778 u_int16_t bge_rx_std_cons_idx;
1779 u_int16_t bge_rx_mini_cons_idx;
1780 u_int16_t bge_rsvd1;
1781 struct bge_sts_idx bge_idx[16];
1784 #define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx
1785 #define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx
1787 #define BGE_STATFLAG_UPDATED 0x00000001
1788 #define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002
1789 #define BGE_STATFLAG_ERROR 0x00000004
1793 * Broadcom Vendor ID
1794 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID
1795 * even though they're now manufactured by Broadcom)
1797 #define BCOM_VENDORID 0x14E4
1798 #define BCOM_DEVICEID_BCM5700 0x1644
1799 #define BCOM_DEVICEID_BCM5701 0x1645
1800 #define BCOM_DEVICEID_BCM5702X 0x16A6
1801 #define BCOM_DEVICEID_BCM5703X 0x16A7
1802 #define BCOM_DEVICEID_BCM5704C 0x1648
1803 #define BCOM_DEVICEID_BCM5704S 0x16A8
1806 * Alteon AceNIC PCI vendor/device ID.
1808 #define ALT_VENDORID 0x12AE
1809 #define ALT_DEVICEID_ACENIC 0x0001
1810 #define ALT_DEVICEID_ACENIC_COPPER 0x0002
1811 #define ALT_DEVICEID_BCM5700 0x0003
1812 #define ALT_DEVICEID_BCM5701 0x0004
1815 * 3Com 3c985 PCI vendor/device ID.
1817 #define TC_VENDORID 0x10B7
1818 #define TC_DEVICEID_3C985 0x0001
1819 #define TC_DEVICEID_3C996 0x0003
1822 * SysKonnect PCI vendor ID
1824 #define SK_VENDORID 0x1148
1825 #define SK_DEVICEID_ALTIMA 0x4400
1826 #define SK_SUBSYSID_9D21 0x4421
1827 #define SK_SUBSYSID_9D41 0x4441
1830 * Altima PCI vendor/device ID.
1832 #define ALTIMA_VENDORID 0x173b
1833 #define ALTIMA_DEVICE_AC1000 0x03e8
1834 #define ALTIMA_DEVICE_AC9100 0x03ea
1837 * Offset of MAC address inside EEPROM.
1839 #define BGE_EE_MAC_OFFSET 0x7C
1840 #define BGE_EE_HWCFG_OFFSET 0xC8
1842 #define BGE_HWCFG_VOLTAGE 0x00000003
1843 #define BGE_HWCFG_PHYLED_MODE 0x0000000C
1844 #define BGE_HWCFG_MEDIA 0x00000030
1846 #define BGE_VOLTAGE_1POINT3 0x00000000
1847 #define BGE_VOLTAGE_1POINT8 0x00000001
1849 #define BGE_PHYLEDMODE_UNSPEC 0x00000000
1850 #define BGE_PHYLEDMODE_TRIPLELED 0x00000004
1851 #define BGE_PHYLEDMODE_SINGLELED 0x00000008
1853 #define BGE_MEDIA_UNSPEC 0x00000000
1854 #define BGE_MEDIA_COPPER 0x00000010
1855 #define BGE_MEDIA_FIBER 0x00000020
1857 #define BGE_PCI_READ_CMD 0x06000000
1858 #define BGE_PCI_WRITE_CMD 0x70000000
1860 #define BGE_TICKS_PER_SEC 1000000
1863 * Ring size constants.
1865 #define BGE_EVENT_RING_CNT 256
1866 #define BGE_CMD_RING_CNT 64
1867 #define BGE_STD_RX_RING_CNT 512
1868 #define BGE_JUMBO_RX_RING_CNT 256
1869 #define BGE_MINI_RX_RING_CNT 1024
1870 #define BGE_RETURN_RING_CNT 1024
1873 * Possible TX ring sizes.
1875 #define BGE_TX_RING_CNT_128 128
1876 #define BGE_TX_RING_BASE_128 0x3800
1878 #define BGE_TX_RING_CNT_256 256
1879 #define BGE_TX_RING_BASE_256 0x3000
1881 #define BGE_TX_RING_CNT_512 512
1882 #define BGE_TX_RING_BASE_512 0x2000
1884 #define BGE_TX_RING_CNT BGE_TX_RING_CNT_512
1885 #define BGE_TX_RING_BASE BGE_TX_RING_BASE_512
1888 * Tigon III statistics counters.
1891 u_int8_t Reserved0[256];
1893 /* Statistics maintained by Receive MAC. */
1894 bge_hostaddr ifHCInOctets;
1895 bge_hostaddr Reserved1;
1896 bge_hostaddr etherStatsFragments;
1897 bge_hostaddr ifHCInUcastPkts;
1898 bge_hostaddr ifHCInMulticastPkts;
1899 bge_hostaddr ifHCInBroadcastPkts;
1900 bge_hostaddr dot3StatsFCSErrors;
1901 bge_hostaddr dot3StatsAlignmentErrors;
1902 bge_hostaddr xonPauseFramesReceived;
1903 bge_hostaddr xoffPauseFramesReceived;
1904 bge_hostaddr macControlFramesReceived;
1905 bge_hostaddr xoffStateEntered;
1906 bge_hostaddr dot3StatsFramesTooLong;
1907 bge_hostaddr etherStatsJabbers;
1908 bge_hostaddr etherStatsUndersizePkts;
1909 bge_hostaddr inRangeLengthError;
1910 bge_hostaddr outRangeLengthError;
1911 bge_hostaddr etherStatsPkts64Octets;
1912 bge_hostaddr etherStatsPkts65Octetsto127Octets;
1913 bge_hostaddr etherStatsPkts128Octetsto255Octets;
1914 bge_hostaddr etherStatsPkts256Octetsto511Octets;
1915 bge_hostaddr etherStatsPkts512Octetsto1023Octets;
1916 bge_hostaddr etherStatsPkts1024Octetsto1522Octets;
1917 bge_hostaddr etherStatsPkts1523Octetsto2047Octets;
1918 bge_hostaddr etherStatsPkts2048Octetsto4095Octets;
1919 bge_hostaddr etherStatsPkts4096Octetsto8191Octets;
1920 bge_hostaddr etherStatsPkts8192Octetsto9022Octets;
1922 bge_hostaddr Unused1[37];
1924 /* Statistics maintained by Transmit MAC. */
1925 bge_hostaddr ifHCOutOctets;
1926 bge_hostaddr Reserved2;
1927 bge_hostaddr etherStatsCollisions;
1928 bge_hostaddr outXonSent;
1929 bge_hostaddr outXoffSent;
1930 bge_hostaddr flowControlDone;
1931 bge_hostaddr dot3StatsInternalMacTransmitErrors;
1932 bge_hostaddr dot3StatsSingleCollisionFrames;
1933 bge_hostaddr dot3StatsMultipleCollisionFrames;
1934 bge_hostaddr dot3StatsDeferredTransmissions;
1935 bge_hostaddr Reserved3;
1936 bge_hostaddr dot3StatsExcessiveCollisions;
1937 bge_hostaddr dot3StatsLateCollisions;
1938 bge_hostaddr dot3Collided2Times;
1939 bge_hostaddr dot3Collided3Times;
1940 bge_hostaddr dot3Collided4Times;
1941 bge_hostaddr dot3Collided5Times;
1942 bge_hostaddr dot3Collided6Times;
1943 bge_hostaddr dot3Collided7Times;
1944 bge_hostaddr dot3Collided8Times;
1945 bge_hostaddr dot3Collided9Times;
1946 bge_hostaddr dot3Collided10Times;
1947 bge_hostaddr dot3Collided11Times;
1948 bge_hostaddr dot3Collided12Times;
1949 bge_hostaddr dot3Collided13Times;
1950 bge_hostaddr dot3Collided14Times;
1951 bge_hostaddr dot3Collided15Times;
1952 bge_hostaddr ifHCOutUcastPkts;
1953 bge_hostaddr ifHCOutMulticastPkts;
1954 bge_hostaddr ifHCOutBroadcastPkts;
1955 bge_hostaddr dot3StatsCarrierSenseErrors;
1956 bge_hostaddr ifOutDiscards;
1957 bge_hostaddr ifOutErrors;
1959 bge_hostaddr Unused2[31];
1961 /* Statistics maintained by Receive List Placement. */
1962 bge_hostaddr COSIfHCInPkts[16];
1963 bge_hostaddr COSFramesDroppedDueToFilters;
1964 bge_hostaddr nicDmaWriteQueueFull;
1965 bge_hostaddr nicDmaWriteHighPriQueueFull;
1966 bge_hostaddr nicNoMoreRxBDs;
1967 bge_hostaddr ifInDiscards;
1968 bge_hostaddr ifInErrors;
1969 bge_hostaddr nicRecvThresholdHit;
1971 bge_hostaddr Unused3[9];
1973 /* Statistics maintained by Send Data Initiator. */
1974 bge_hostaddr COSIfHCOutPkts[16];
1975 bge_hostaddr nicDmaReadQueueFull;
1976 bge_hostaddr nicDmaReadHighPriQueueFull;
1977 bge_hostaddr nicSendDataCompQueueFull;
1979 /* Statistics maintained by Host Coalescing. */
1980 bge_hostaddr nicRingSetSendProdIndex;
1981 bge_hostaddr nicRingStatusUpdate;
1982 bge_hostaddr nicInterrupts;
1983 bge_hostaddr nicAvoidedInterrupts;
1984 bge_hostaddr nicSendThresholdHit;
1986 u_int8_t Reserved4[320];
1990 * Tigon general information block. This resides in host memory
1991 * and contains the status counters, ring control blocks and
1992 * producer pointers.
1996 struct bge_stats bge_stats;
1997 struct bge_rcb bge_tx_rcb[16];
1998 struct bge_rcb bge_std_rx_rcb;
1999 struct bge_rcb bge_jumbo_rx_rcb;
2000 struct bge_rcb bge_mini_rx_rcb;
2001 struct bge_rcb bge_return_rcb;
2005 * NOTE! On the Alpha, we have an alignment constraint.
2006 * The first thing in the packet is a 14-byte Ethernet header.
2007 * This means that the packet is misaligned. To compensate,
2008 * we actually offset the data 2 bytes into the cluster. This
2009 * alignes the packet after the Ethernet header at a 32-bit
2013 #define ETHER_ALIGN 2
2015 #define BGE_FRAMELEN 1518
2016 #define BGE_MAX_FRAMELEN 1536
2017 #define BGE_JUMBO_FRAMELEN 9018
2018 #define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
2019 #define BGE_PAGE_SIZE PAGE_SIZE
2020 #define BGE_MIN_FRAMELEN 60
2023 * Other utility macros.
2025 #define BGE_INC(x, y) (x) = (x + 1) % y
2028 * Vital product data and structures.
2030 #define BGE_VPD_FLAG 0x8000
2032 /* VPD structures */
2044 #define VPD_RES_ID 0x82 /* ID string */
2045 #define VPD_RES_READ 0x90 /* start of read only area */
2046 #define VPD_RES_WRITE 0x81 /* start of read/write area */
2047 #define VPD_RES_END 0x78 /* end tag */
2051 * Register access macros. The Tigon always uses memory mapped register
2052 * accesses and all registers must be accessed with 32 bit operations.
2055 #define CSR_WRITE_4(sc, reg, val) \
2056 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val)
2058 #define CSR_READ_4(sc, reg) \
2059 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg)
2061 #define BGE_SETBIT(sc, reg, x) \
2062 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x))
2063 #define BGE_CLRBIT(sc, reg, x) \
2064 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x))
2066 #define PCI_SETBIT(dev, reg, x, s) \
2067 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | x), s)
2068 #define PCI_CLRBIT(dev, reg, x, s) \
2069 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~x), s)
2072 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS
2073 * values are tuneable. They control the actual amount of buffers
2074 * allocated for the standard, mini and jumbo receive rings.
2077 #define BGE_SSLOTS 256
2078 #define BGE_MSLOTS 256
2079 #define BGE_JSLOTS 384
2081 #define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN + sizeof(u_int64_t))
2082 #define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \
2083 (BGE_JRAWLEN % sizeof(u_int64_t))))
2084 #define BGE_JPAGESZ PAGE_SIZE
2085 #define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ)
2086 #define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID)
2094 * Ring structures. Most of these reside in host memory and we tell
2095 * the NIC where they are via the ring control blocks. The exceptions
2096 * are the tx and command rings, which live in NIC memory and which
2097 * we access via the shared memory window.
2099 struct bge_ring_data {
2100 struct bge_rx_bd bge_rx_std_ring[BGE_STD_RX_RING_CNT];
2101 struct bge_rx_bd bge_rx_jumbo_ring[BGE_JUMBO_RX_RING_CNT];
2102 struct bge_rx_bd bge_rx_return_ring[BGE_RETURN_RING_CNT];
2103 struct bge_tx_bd bge_tx_ring[BGE_TX_RING_CNT];
2104 struct bge_status_block bge_status_block;
2105 struct bge_tx_desc *bge_tx_ring_nic;/* pointer to shared mem */
2106 struct bge_cmd_desc *bge_cmd_ring; /* pointer to shared mem */
2107 struct bge_gib bge_info;
2111 * Mbuf pointers. We need these to keep track of the virtual addresses
2112 * of our mbuf chains since we can only convert from physical to virtual,
2113 * not the other way around.
2115 struct bge_chain_data {
2116 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT];
2117 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT];
2118 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT];
2119 struct mbuf *bge_rx_mini_chain[BGE_MINI_RX_RING_CNT];
2120 /* Stick the jumbo mem management stuff here too. */
2121 struct bge_jslot bge_jslots[BGE_JSLOTS];
2122 void *bge_jumbo_buf;
2131 #define BGE_HWREV_TIGON 0x01
2132 #define BGE_HWREV_TIGON_II 0x02
2133 #define BGE_TIMEOUT 1000
2134 #define BGE_TXCONS_UNSET 0xFFFF /* impossible value */
2136 struct bge_jpool_entry {
2138 SLIST_ENTRY(bge_jpool_entry) jpool_entries;
2141 struct bge_bcom_hack {
2147 struct arpcom arpcom; /* interface info */
2149 device_t bge_miibus;
2150 bus_space_handle_t bge_bhandle;
2151 vm_offset_t bge_vhandle;
2152 bus_space_tag_t bge_btag;
2154 struct resource *bge_irq;
2155 struct resource *bge_res;
2156 struct ifmedia bge_ifmedia; /* TBI media info */
2157 u_int8_t bge_unit; /* interface number */
2158 u_int8_t bge_extram; /* has external SSRAM */
2160 u_int8_t bge_rx_alignment_bug;
2161 u_int32_t bge_chipid;
2162 u_int8_t bge_asicrev;
2163 u_int8_t bge_chiprev;
2164 struct bge_ring_data *bge_rdata; /* rings */
2165 struct bge_chain_data bge_cdata; /* mbufs */
2166 u_int16_t bge_tx_saved_considx;
2167 u_int16_t bge_rx_saved_considx;
2168 u_int16_t bge_ev_saved_considx;
2169 u_int16_t bge_std; /* current std ring head */
2170 u_int16_t bge_jumbo; /* current jumo ring head */
2171 SLIST_HEAD(__bge_jfreehead, bge_jpool_entry) bge_jfree_listhead;
2172 SLIST_HEAD(__bge_jinusehead, bge_jpool_entry) bge_jinuse_listhead;
2173 u_int32_t bge_stat_ticks;
2174 u_int32_t bge_rx_coal_ticks;
2175 u_int32_t bge_tx_coal_ticks;
2176 u_int32_t bge_rx_max_coal_bds;
2177 u_int32_t bge_tx_max_coal_bds;
2178 u_int32_t bge_tx_buf_ratio;
2182 struct callout_handle bge_stat_ch;
2183 char *bge_vpd_prodname;
2184 char *bge_vpd_readonly;
2189 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)