2 * Copyright (c) 1995, David Greenman
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/ed/if_ed.c,v 1.173.2.13 2001/11/03 00:36:07 luigi Exp $
31 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
32 * adapters. By David Greenman, 29-April-1993
34 * Currently supports the Western Digital/SMC 8003 and 8013 series,
35 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000,
36 * and a variety of similar clones.
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/sockio.h>
44 #include <sys/kernel.h>
45 #include <sys/socket.h>
46 #include <sys/syslog.h>
48 #include <sys/module.h>
51 #include <machine/bus.h>
53 #include <machine/resource.h>
55 #include <net/ethernet.h>
57 #include <net/if_arp.h>
58 #include <net/if_dl.h>
59 #include <net/if_mib.h>
60 #include <net/if_media.h>
62 #include <dev/mii/mii.h>
63 #include <dev/mii/miivar.h>
67 #include <net/bridge.h>
69 #include <machine/clock.h>
70 #include <machine/md_var.h>
72 #include <dev/ed/if_edreg.h>
73 #include <dev/ed/if_edvar.h>
75 static void ed_init __P((void *));
76 static int ed_ioctl __P((struct ifnet *, u_long, caddr_t));
77 static void ed_start __P((struct ifnet *));
78 static void ed_reset __P((struct ifnet *));
79 static void ed_watchdog __P((struct ifnet *));
80 static void ed_tick __P((void *));
82 static void ds_getmcaf __P((struct ed_softc *, u_int32_t *));
84 static void ed_get_packet __P((struct ed_softc *, char *, /* u_short */ int));
86 static __inline void ed_rint __P((struct ed_softc *));
87 static __inline void ed_xmit __P((struct ed_softc *));
88 static __inline char * ed_ring_copy __P((struct ed_softc *, char *, char *,
90 static void ed_hpp_set_physical_link __P((struct ed_softc *));
91 static void ed_hpp_readmem __P((struct ed_softc *, int, unsigned char *,
93 static void ed_hpp_writemem __P((struct ed_softc *, unsigned char *,
94 /* u_short */ int, /* u_short */ int));
95 static u_short ed_hpp_write_mbufs __P((struct ed_softc *, struct mbuf *,
98 static u_short ed_pio_write_mbufs __P((struct ed_softc *, struct mbuf *,
101 static void ed_setrcr __P((struct ed_softc *));
103 static u_int32_t ds_crc __P((u_char *ep));
106 * Interrupt conversion table for WD/SMC ASIC/83C584
108 static unsigned short ed_intr_val[] = {
120 * Interrupt conversion table for 83C790
122 static unsigned short ed_790_intr_val[] = {
134 * Interrupt conversion table for the HP PC LAN+
137 static unsigned short ed_hpp_intr_val[] = {
157 * Generic probe routine for testing for the existance of a DS8390.
158 * Must be called after the NIC has just been reset. This routine
159 * works by looking at certain register values that are guaranteed
160 * to be initialized a certain way after power-up or reset. Seems
161 * not to currently work on the 83C690.
165 * Register reset bits set bits
166 * Command Register (CR) TXP, STA RD2, STP
167 * Interrupt Status (ISR) RST
168 * Interrupt Mask (IMR) All bits
169 * Data Control (DCR) LAS
170 * Transmit Config. (TCR) LB1, LB0
172 * We only look at the CR and ISR registers, however, because looking at
173 * the others would require changing register pages (which would be
174 * intrusive if this isn't an 8390).
176 * Return 1 if 8390 was found, 0 if not.
180 ed_probe_generic8390(sc)
183 if ((ed_nic_inb(sc, ED_P0_CR) &
184 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) !=
185 (ED_CR_RD2 | ED_CR_STP))
187 if ((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
194 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards
197 ed_probe_WD80x3_generic(dev, flags, intr_vals)
200 unsigned short *intr_vals[];
202 struct ed_softc *sc = device_get_softc(dev);
205 u_int memsize, maddr;
206 u_char iptr, isa16bit, sum, totalsum;
207 u_long conf_maddr, conf_msize, irq, junk;
209 sc->chip_type = ED_CHIP_TYPE_DP8390;
211 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) {
212 totalsum = ED_WD_ROM_CHECKSUM_TOTAL_TOSH_ETHER;
213 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_POW);
217 totalsum = ED_WD_ROM_CHECKSUM_TOTAL;
220 * Attempt to do a checksum over the station address PROM. If it
221 * fails, it's probably not a SMC/WD board. There is a problem with
222 * this, though: some clone WD boards don't pass the checksum test.
223 * Danpex boards for one.
225 for (sum = 0, i = 0; i < 8; ++i)
226 sum += ed_asic_inb(sc, ED_WD_PROM + i);
228 if (sum != totalsum) {
231 * Checksum is invalid. This often happens with cheap WD8003E
232 * clones. In this case, the checksum byte (the eighth byte)
233 * seems to always be zero.
235 if (ed_asic_inb(sc, ED_WD_CARD_ID) != ED_TYPE_WD8003E ||
236 ed_asic_inb(sc, ED_WD_PROM + 7) != 0)
239 /* reset card to force it into a known state. */
240 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER)
241 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW);
243 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST);
246 ed_asic_outb(sc, ED_WD_MSR, ed_asic_inb(sc, ED_WD_MSR) & ~ED_WD_MSR_RST);
247 /* wait in the case this card is reading its EEROM */
250 sc->vendor = ED_VENDOR_WD_SMC;
251 sc->type = ed_asic_inb(sc, ED_WD_CARD_ID);
254 * Set initial values for width/size.
259 case ED_TYPE_WD8003S:
260 sc->type_str = "WD8003S";
262 case ED_TYPE_WD8003E:
263 sc->type_str = "WD8003E";
265 case ED_TYPE_WD8003EB:
266 sc->type_str = "WD8003EB";
268 case ED_TYPE_WD8003W:
269 sc->type_str = "WD8003W";
271 case ED_TYPE_WD8013EBT:
272 sc->type_str = "WD8013EBT";
276 case ED_TYPE_WD8013W:
277 sc->type_str = "WD8013W";
281 case ED_TYPE_WD8013EP: /* also WD8003EP */
282 if (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) {
285 sc->type_str = "WD8013EP";
287 sc->type_str = "WD8003EP";
290 case ED_TYPE_WD8013WC:
291 sc->type_str = "WD8013WC";
295 case ED_TYPE_WD8013EBP:
296 sc->type_str = "WD8013EBP";
300 case ED_TYPE_WD8013EPC:
301 sc->type_str = "WD8013EPC";
305 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */
306 case ED_TYPE_SMC8216T:
307 if (sc->type == ED_TYPE_SMC8216C) {
308 sc->type_str = "SMC8216/SMC8216C";
310 sc->type_str = "SMC8216T";
313 ed_asic_outb(sc, ED_WD790_HWR,
314 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH);
315 switch (ed_asic_inb(sc, ED_WD790_RAR) & ED_WD790_RAR_SZ64) {
316 case ED_WD790_RAR_SZ64:
319 case ED_WD790_RAR_SZ32:
322 case ED_WD790_RAR_SZ16:
325 case ED_WD790_RAR_SZ8:
326 /* 8216 has 16K shared mem -- 8416 has 8K */
327 if (sc->type == ED_TYPE_SMC8216C) {
328 sc->type_str = "SMC8416C/SMC8416BT";
330 sc->type_str = "SMC8416T";
335 ed_asic_outb(sc, ED_WD790_HWR,
336 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
339 sc->chip_type = ED_CHIP_TYPE_WD790;
341 case ED_TYPE_TOSHIBA1:
342 sc->type_str = "Toshiba1";
346 case ED_TYPE_TOSHIBA4:
347 sc->type_str = "Toshiba4";
357 * Make some adjustments to initial values depending on what is found
360 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT)
361 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4)
362 && ((ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) {
367 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
368 &conf_maddr, &conf_msize);
373 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n",
374 sc->type, sc->type_str, isa16bit, memsize, conf_msize);
375 for (i = 0; i < 8; i++)
376 printf("%x -> %x\n", i, ed_asic_inb(sc, i));
380 * Allow the user to override the autoconfiguration
383 memsize = conf_msize;
386 if (maddr < 0xa0000 || maddr + memsize > 0x1000000) {
387 device_printf(dev, "Invalid ISA memory address range configured: 0x%x - 0x%x\n",
388 maddr, maddr + memsize);
393 * (note that if the user specifies both of the following flags that
394 * '8bit' mode intentionally has precedence)
396 if (flags & ED_FLAGS_FORCE_16BIT_MODE)
398 if (flags & ED_FLAGS_FORCE_8BIT_MODE)
402 * If possible, get the assigned interrupt number from the card and
405 if ((sc->type & ED_WD_SOFTCONFIG) &&
406 (sc->chip_type != ED_CHIP_TYPE_WD790)) {
409 * Assemble together the encoded interrupt number.
411 iptr = (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_IR2) |
412 ((ed_asic_inb(sc, ED_WD_IRR) &
413 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
416 * If no interrupt specified (or "?"), use what the board tells us.
418 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
420 if (error && intr_vals[0] != NULL) {
421 error = bus_set_resource(dev, SYS_RES_IRQ, 0,
422 intr_vals[0][iptr], 1);
428 * Enable the interrupt.
430 ed_asic_outb(sc, ED_WD_IRR,
431 ed_asic_inb(sc, ED_WD_IRR) | ED_WD_IRR_IEN);
433 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
434 ed_asic_outb(sc, ED_WD790_HWR,
435 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH);
436 iptr = (((ed_asic_inb(sc, ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) |
437 (ed_asic_inb(sc, ED_WD790_GCR) &
438 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2);
439 ed_asic_outb(sc, ED_WD790_HWR,
440 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
443 * If no interrupt specified (or "?"), use what the board tells us.
445 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
447 if (error && intr_vals[1] != NULL) {
448 error = bus_set_resource(dev, SYS_RES_IRQ, 0,
449 intr_vals[1][iptr], 1);
457 ed_asic_outb(sc, ED_WD790_ICR,
458 ed_asic_inb(sc, ED_WD790_ICR) | ED_WD790_ICR_EIL);
460 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
463 device_printf(dev, "%s cards don't support auto-detected/assigned interrupts.\n",
467 sc->isa16bit = isa16bit;
470 error = ed_alloc_memory(dev, 0, memsize);
472 printf("*** ed_alloc_memory() failed! (%d)\n", error);
475 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
478 * allocate one xmit buffer if < 16k, two buffers otherwise
480 if ((memsize < 16384) ||
481 (flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
486 sc->tx_page_start = ED_WD_PAGE_OFFSET;
487 sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt;
488 sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE;
489 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start);
490 sc->mem_size = memsize;
491 sc->mem_end = sc->mem_start + memsize;
494 * Get station address from on-board ROM
496 for (i = 0; i < ETHER_ADDR_LEN; ++i)
497 sc->arpcom.ac_enaddr[i] = ed_asic_inb(sc, ED_WD_PROM + i);
500 * Set upper address bits and 8/16 bit access to shared memory.
503 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
504 sc->wd_laar_proto = ed_asic_inb(sc, ED_WD_LAAR);
506 sc->wd_laar_proto = ED_WD_LAAR_L16EN |
507 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI);
510 * Enable 16bit access
512 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto |
515 if (((sc->type & ED_WD_SOFTCONFIG) ||
516 (sc->type == ED_TYPE_TOSHIBA1) ||
517 (sc->type == ED_TYPE_TOSHIBA4) ||
518 (sc->type == ED_TYPE_WD8013EBT)) &&
519 (sc->chip_type != ED_CHIP_TYPE_WD790)) {
520 sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) &
522 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto);
527 * Set address and enable interface shared memory.
529 if (sc->chip_type != ED_CHIP_TYPE_WD790) {
530 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) {
531 ed_asic_outb(sc, ED_WD_MSR + 1,
532 ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4);
533 ed_asic_outb(sc, ED_WD_MSR + 2,
534 ((kvtop(sc->mem_start) >> 16) & 0x0f));
535 ed_asic_outb(sc, ED_WD_MSR,
536 ED_WD_MSR_MENB | ED_WD_MSR_POW);
538 ed_asic_outb(sc, ED_WD_MSR,
539 ((kvtop(sc->mem_start) >> 13) &
540 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB);
542 sc->cr_proto = ED_CR_RD2;
544 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
545 ed_asic_outb(sc, ED_WD790_HWR, (ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH));
546 ed_asic_outb(sc, ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) |
547 ((kvtop(sc->mem_start) >> 11) & 0x40) |
548 (ed_asic_inb(sc, ED_WD790_RAR) & 0xb0));
549 ed_asic_outb(sc, ED_WD790_HWR, (ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH));
554 printf("starting memory performance test at 0x%x, size %d...\n",
555 sc->mem_start, memsize*16384);
556 for (i = 0; i < 16384; i++)
557 bzero(sc->mem_start, memsize);
558 printf("***DONE***\n");
562 * Now zero memory and verify that it is clear
564 bzero(sc->mem_start, memsize);
566 for (i = 0; i < memsize; ++i) {
567 if (sc->mem_start[i]) {
568 device_printf(dev, "failed to clear shared memory at %lx - check configuration\n",
569 kvtop(sc->mem_start + i));
572 * Disable 16 bit access to shared memory
575 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
576 ed_asic_outb(sc, ED_WD_MSR, 0x00);
578 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto &
586 * Disable 16bit access to shared memory - we leave it
587 * disabled so that 1) machines reboot properly when the board
588 * is set 16 bit mode and there are conflicting 8bit
589 * devices/ROMS in the same 128k address space as this boards
590 * shared memory. and 2) so that other 8 bit devices with
591 * shared memory can be used in this 128k region, too.
594 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
595 ed_asic_outb(sc, ED_WD_MSR, 0x00);
597 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto &
604 ed_probe_WD80x3(dev, port_rid, flags)
609 struct ed_softc *sc = device_get_softc(dev);
611 static unsigned short *intr_vals[] = {ed_intr_val, ed_790_intr_val};
613 error = ed_alloc_port(dev, port_rid, ED_WD_IO_PORTS);
617 sc->asic_offset = ED_WD_ASIC_OFFSET;
618 sc->nic_offset = ED_WD_NIC_OFFSET;
620 return ed_probe_WD80x3_generic(dev, flags, intr_vals);
624 * Probe and vendor-specific initialization routine for 3Com 3c503 boards
627 ed_probe_3Com(dev, port_rid, flags)
632 struct ed_softc *sc = device_get_softc(dev);
637 u_long conf_maddr, conf_msize, irq, junk;
639 error = ed_alloc_port(dev, 0, ED_3COM_IO_PORTS);
643 sc->asic_offset = ED_3COM_ASIC_OFFSET;
644 sc->nic_offset = ED_3COM_NIC_OFFSET;
647 * Verify that the kernel configured I/O address matches the board
650 switch (ed_asic_inb(sc, ED_3COM_BCFR)) {
651 case ED_3COM_BCFR_300:
652 if (rman_get_start(sc->port_res) != 0x300)
655 case ED_3COM_BCFR_310:
656 if (rman_get_start(sc->port_res) != 0x310)
659 case ED_3COM_BCFR_330:
660 if (rman_get_start(sc->port_res) != 0x330)
663 case ED_3COM_BCFR_350:
664 if (rman_get_start(sc->port_res) != 0x350)
667 case ED_3COM_BCFR_250:
668 if (rman_get_start(sc->port_res) != 0x250)
671 case ED_3COM_BCFR_280:
672 if (rman_get_start(sc->port_res) != 0x280)
675 case ED_3COM_BCFR_2A0:
676 if (rman_get_start(sc->port_res) != 0x2a0)
679 case ED_3COM_BCFR_2E0:
680 if (rman_get_start(sc->port_res) != 0x2e0)
687 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
688 &conf_maddr, &conf_msize);
693 * Verify that the kernel shared memory address matches the board
694 * configured address.
696 switch (ed_asic_inb(sc, ED_3COM_PCFR)) {
697 case ED_3COM_PCFR_DC000:
698 if (conf_maddr != 0xdc000)
701 case ED_3COM_PCFR_D8000:
702 if (conf_maddr != 0xd8000)
705 case ED_3COM_PCFR_CC000:
706 if (conf_maddr != 0xcc000)
709 case ED_3COM_PCFR_C8000:
710 if (conf_maddr != 0xc8000)
719 * Reset NIC and ASIC. Enable on-board transceiver throughout reset
720 * sequence because it'll lock up if the cable isn't connected if we
723 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL);
726 * Wait for a while, then un-reset it
731 * The 3Com ASIC defaults to rather strange settings for the CR after
732 * a reset - it's important to set it again after the following outb
733 * (this is done when we map the PROM below).
735 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
738 * Wait a bit for the NIC to recover from the reset
742 sc->vendor = ED_VENDOR_3COM;
743 sc->type_str = "3c503";
745 sc->cr_proto = ED_CR_RD2;
748 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window
754 * Get station address from on-board ROM
758 * First, map ethernet address PROM over the top of where the NIC
759 * registers normally appear.
761 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
763 for (i = 0; i < ETHER_ADDR_LEN; ++i)
764 sc->arpcom.ac_enaddr[i] = ed_nic_inb(sc, i);
767 * Unmap PROM - select NIC registers. The proper setting of the
768 * tranceiver is set in ed_init so that the attach code is given a
769 * chance to set the default based on a compile-time config option
771 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
774 * Determine if this is an 8bit or 16bit board
778 * select page 0 registers
780 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
783 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit
786 ed_nic_outb(sc, ED_P0_DCR, 0);
789 * select page 2 registers
791 ed_nic_outb(sc, ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP);
794 * The 3c503 forces the WTS bit to a one if this is a 16bit board
796 if (ed_nic_inb(sc, ED_P2_DCR) & ED_DCR_WTS)
802 * select page 0 registers
804 ed_nic_outb(sc, ED_P2_CR, ED_CR_RD2 | ED_CR_STP);
806 error = ed_alloc_memory(dev, 0, memsize);
810 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
811 sc->mem_size = memsize;
812 sc->mem_end = sc->mem_start + memsize;
815 * We have an entire 8k window to put the transmit buffers on the
816 * 16bit boards. But since the 16bit 3c503's shared memory is only
817 * fast enough to overlap the loading of one full-size packet, trying
818 * to load more than 2 buffers can actually leave the transmitter idle
819 * during the load. So 2 seems the best value. (Although a mix of
820 * variable-sized packets might change this assumption. Nonetheless,
821 * we optimize for linear transfers of same-size packets.)
824 if (flags & ED_FLAGS_NO_MULTI_BUFFERING)
829 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT;
830 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT;
831 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
832 ED_3COM_RX_PAGE_OFFSET_16BIT;
833 sc->mem_ring = sc->mem_start;
836 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT;
837 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT;
838 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
839 ED_3COM_TX_PAGE_OFFSET_8BIT;
840 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
843 sc->isa16bit = isa16bit;
846 * Initialize GA page start/stop registers. Probably only needed if
847 * doing DMA, but what the hell.
849 ed_asic_outb(sc, ED_3COM_PSTR, sc->rec_page_start);
850 ed_asic_outb(sc, ED_3COM_PSPR, sc->rec_page_stop);
853 * Set IRQ. 3c503 only allows a choice of irq 2-5.
855 error = bus_get_resource(dev, SYS_RES_IRQ, 0, &irq, &junk);
862 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2);
865 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3);
868 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4);
871 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5);
874 device_printf(dev, "Invalid irq configuration (%ld) must be 3-5,9 for 3c503\n",
880 * Initialize GA configuration register. Set bank and enable shared
883 ed_asic_outb(sc, ED_3COM_GACFR, ED_3COM_GACFR_RSEL |
887 * Initialize "Vector Pointer" registers. These gawd-awful things are
888 * compared to 20 bits of the address on ISA, and if they match, the
889 * shared memory is disabled. We set them to 0xffff0...allegedly the
892 ed_asic_outb(sc, ED_3COM_VPTR2, 0xff);
893 ed_asic_outb(sc, ED_3COM_VPTR1, 0xff);
894 ed_asic_outb(sc, ED_3COM_VPTR0, 0x00);
897 * Zero memory and verify that it is clear
899 bzero(sc->mem_start, memsize);
901 for (i = 0; i < memsize; ++i)
902 if (sc->mem_start[i]) {
903 device_printf(dev, "failed to clear shared memory at %lx - check configuration\n",
904 kvtop(sc->mem_start + i));
911 * Probe and vendor-specific initialization routine for NE1000/2000 boards
914 ed_probe_Novell_generic(dev, flags)
918 struct ed_softc *sc = device_get_softc(dev);
920 u_char romdata[16], tmp;
921 static char test_pattern[32] = "THIS is A memory TEST pattern";
922 char test_buffer[32];
924 /* XXX - do Novell-specific probe here */
926 /* Reset the board */
927 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) {
928 ed_asic_outb(sc, ED_NOVELL_RESET, 0);
931 tmp = ed_asic_inb(sc, ED_NOVELL_RESET);
934 * I don't know if this is necessary; probably cruft leftover from
935 * Clarkson packet driver code. Doesn't do a thing on the boards I've
936 * tested. -DG [note that a outb(0x84, 0) seems to work here, and is
937 * non-invasive...but some boards don't seem to reset and I don't have
938 * complete documentation on what the 'right' thing to do is...so we
939 * do the invasive thing for now. Yuck.]
941 ed_asic_outb(sc, ED_NOVELL_RESET, tmp);
945 * This is needed because some NE clones apparently don't reset the
946 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX
947 * - this makes the probe invasive! ...Done against my better
950 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
954 /* Make sure that we really have an 8390 based board */
955 if (!ed_probe_generic8390(sc))
958 sc->vendor = ED_VENDOR_NOVELL;
960 sc->cr_proto = ED_CR_RD2;
963 * Test the ability to read and write to the NIC memory. This has the
964 * side affect of determining if this is an NE1000 or an NE2000.
968 * This prevents packets from being stored in the NIC memory when the
969 * readmem routine turns on the start bit in the CR.
971 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON);
973 /* Temporarily initialize DCR for byte operations */
974 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
976 ed_nic_outb(sc, ED_P0_PSTART, 8192 / ED_PAGE_SIZE);
977 ed_nic_outb(sc, ED_P0_PSTOP, 16384 / ED_PAGE_SIZE);
982 * Write a test pattern in byte mode. If this fails, then there
983 * probably isn't any memory at 8k - which likely means that the board
986 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern));
987 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern));
989 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) {
990 sc->type = ED_TYPE_NE1000;
991 sc->type_str = "NE1000";
994 /* neither an NE1000 nor a Linksys - try NE2000 */
995 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS);
996 ed_nic_outb(sc, ED_P0_PSTART, 16384 / ED_PAGE_SIZE);
997 ed_nic_outb(sc, ED_P0_PSTOP, 32768 / ED_PAGE_SIZE);
1002 * Write a test pattern in word mode. If this also fails, then
1003 * we don't know what this board is.
1005 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern));
1006 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern));
1007 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) {
1008 sc->type = ED_TYPE_NE2000;
1009 sc->type_str = "NE2000";
1016 /* 8k of memory plus an additional 8k if 16bit */
1017 memsize = 8192 + sc->isa16bit * 8192;
1019 #if 0 /* probably not useful - NE boards only come two ways */
1020 /* allow kernel config file overrides */
1021 if (isa_dev->id_msize)
1022 memsize = isa_dev->id_msize;
1025 sc->mem_size = memsize;
1027 /* NIC memory doesn't start at zero on an NE board */
1028 /* The start address is tied to the bus width */
1029 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192;
1030 sc->mem_end = sc->mem_start + memsize;
1031 sc->tx_page_start = memsize / ED_PAGE_SIZE;
1033 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) {
1034 int x, i, mstart = 0, msize = 0;
1035 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE];
1037 for (i = 0; i < ED_PAGE_SIZE; i++)
1040 /* Clear all the memory. */
1041 for (x = 1; x < 256; x++)
1042 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE);
1044 /* Search for the start of RAM. */
1045 for (x = 1; x < 256; x++) {
1046 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1047 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1048 for (i = 0; i < ED_PAGE_SIZE; i++)
1050 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1051 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1052 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) {
1053 mstart = x * ED_PAGE_SIZE;
1054 msize = ED_PAGE_SIZE;
1061 device_printf(dev, "Cannot find start of RAM.\n");
1064 /* Search for the start of RAM. */
1065 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) {
1066 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1067 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1068 for (i = 0; i < ED_PAGE_SIZE; i++)
1070 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1071 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1072 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0)
1073 msize += ED_PAGE_SIZE;
1083 device_printf(dev, "Cannot find any RAM, start : %d, x = %d.\n", mstart, x);
1086 device_printf(dev, "RAM start at %d, size : %d.\n", mstart, msize);
1088 sc->mem_size = msize;
1089 sc->mem_start = (caddr_t) mstart;
1090 sc->mem_end = (caddr_t) (msize + mstart);
1091 sc->tx_page_start = mstart / ED_PAGE_SIZE;
1095 * Use one xmit buffer if < 16k, two buffers otherwise (if not told
1098 if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING))
1103 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE;
1104 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE;
1106 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
1108 ed_pio_readmem(sc, 0, romdata, 16);
1109 for (n = 0; n < ETHER_ADDR_LEN; n++)
1110 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)];
1112 if ((ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) &&
1113 (sc->arpcom.ac_enaddr[2] == 0x86)) {
1114 sc->type_str = "Gateway AT";
1117 /* clear any pending interrupts that might have occurred above */
1118 ed_nic_outb(sc, ED_P0_ISR, 0xff);
1124 ed_probe_Novell(dev, port_rid, flags)
1129 struct ed_softc *sc = device_get_softc(dev);
1132 error = ed_alloc_port(dev, port_rid, ED_NOVELL_IO_PORTS);
1136 sc->asic_offset = ED_NOVELL_ASIC_OFFSET;
1137 sc->nic_offset = ED_NOVELL_NIC_OFFSET;
1139 return ed_probe_Novell_generic(dev, flags);
1142 #define ED_HPP_TEST_SIZE 16
1145 * Probe and vendor specific initialization for the HP PC Lan+ Cards.
1146 * (HP Part nos: 27247B and 27252A).
1148 * The card has an asic wrapper around a DS8390 core. The asic handles
1149 * host accesses and offers both standard register IO and memory mapped
1150 * IO. Memory mapped I/O allows better performance at the expense of greater
1151 * chance of an incompatibility with existing ISA cards.
1153 * The card has a few caveats: it isn't tolerant of byte wide accesses, only
1154 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions
1155 * don't allow 32 bit accesses; these are indicated by a bit in the software
1156 * ID register (see if_edreg.h).
1158 * Other caveats are: we should read the MAC address only when the card
1161 * For more information; please consult the CRYNWR packet driver.
1163 * The AUI port is turned on using the "link2" option on the ifconfig
1167 ed_probe_HP_pclanp(dev, port_rid, flags)
1172 struct ed_softc *sc = device_get_softc(dev);
1174 int n; /* temp var */
1175 int memsize; /* mem on board */
1176 u_char checksum; /* checksum of board address */
1177 u_char irq; /* board configured IRQ */
1178 char test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */
1179 char test_buffer[ED_HPP_TEST_SIZE]; /* probing card */
1180 u_long conf_maddr, conf_msize, conf_irq, junk;
1182 error = ed_alloc_port(dev, 0, ED_HPP_IO_PORTS);
1186 /* Fill in basic information */
1187 sc->asic_offset = ED_HPP_ASIC_OFFSET;
1188 sc->nic_offset = ED_HPP_NIC_OFFSET;
1190 sc->chip_type = ED_CHIP_TYPE_DP8390;
1191 sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */
1194 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53"
1197 if ((ed_asic_inb(sc, ED_HPP_ID) != 0x50) ||
1198 (ed_asic_inb(sc, ED_HPP_ID + 1) != 0x48) ||
1199 ((ed_asic_inb(sc, ED_HPP_ID + 2) & 0xF0) != 0) ||
1200 (ed_asic_inb(sc, ED_HPP_ID + 3) != 0x53))
1204 * Read the MAC address and verify checksum on the address.
1207 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_MAC);
1208 for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++)
1209 checksum += (sc->arpcom.ac_enaddr[n] =
1210 ed_asic_inb(sc, ED_HPP_MAC_ADDR + n));
1212 checksum += ed_asic_inb(sc, ED_HPP_MAC_ADDR + ETHER_ADDR_LEN);
1214 if (checksum != 0xFF)
1218 * Verify that the software model number is 0.
1221 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_ID);
1222 if (((sc->hpp_id = ed_asic_inw(sc, ED_HPP_PAGE_4)) &
1223 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000)
1227 * Read in and save the current options configured on card.
1230 sc->hpp_options = ed_asic_inw(sc, ED_HPP_OPTION);
1232 sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET |
1233 ED_HPP_OPTION_CHIP_RESET |
1234 ED_HPP_OPTION_ENABLE_IRQ);
1237 * Reset the chip. This requires writing to the option register
1238 * so take care to preserve the other bits.
1241 ed_asic_outw(sc, ED_HPP_OPTION,
1242 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET |
1243 ED_HPP_OPTION_CHIP_RESET)));
1245 DELAY(5000); /* wait for chip reset to complete */
1247 ed_asic_outw(sc, ED_HPP_OPTION,
1248 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET |
1249 ED_HPP_OPTION_CHIP_RESET |
1250 ED_HPP_OPTION_ENABLE_IRQ)));
1254 if (!(ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST))
1255 return ENXIO; /* reset did not complete */
1258 * Read out configuration information.
1261 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1263 irq = ed_asic_inb(sc, ED_HPP_HW_IRQ);
1266 * Check for impossible IRQ.
1269 if (irq >= (sizeof(ed_hpp_intr_val) / sizeof(ed_hpp_intr_val[0])))
1273 * If the kernel IRQ was specified with a '?' use the cards idea
1274 * of the IRQ. If the kernel IRQ was explicitly specified, it
1275 * should match that of the hardware.
1277 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
1280 bus_set_resource(dev, SYS_RES_IRQ, 0,
1281 ed_hpp_intr_val[irq], 1);
1283 if (conf_irq != ed_hpp_intr_val[irq])
1288 * Fill in softconfig info.
1291 sc->vendor = ED_VENDOR_HP;
1292 sc->type = ED_TYPE_HP_PCLANPLUS;
1293 sc->type_str = "HP-PCLAN+";
1295 sc->mem_shared = 0; /* we DON'T have dual ported RAM */
1296 sc->mem_start = 0; /* we use offsets inside the card RAM */
1298 sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */
1301 * The board has 32KB of memory. Is there a way to determine
1302 * this programmatically?
1308 * Check if memory mapping of the I/O registers possible.
1311 if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE)
1316 * determine the memory address from the board.
1319 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1320 mem_addr = (ed_asic_inw(sc, ED_HPP_HW_MEM_MAP) << 8);
1323 * Check that the kernel specified start of memory and
1324 * hardware's idea of it match.
1326 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
1327 &conf_maddr, &conf_msize);
1331 if (mem_addr != conf_maddr)
1334 error = ed_alloc_memory(dev, 0, memsize);
1338 sc->hpp_mem_start = rman_get_virtual(sc->mem_res);
1342 * Fill in the rest of the soft config structure.
1346 * The transmit page index.
1349 sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET;
1351 if (device_get_flags(dev) & ED_FLAGS_NO_MULTI_BUFFERING)
1357 * Memory description
1360 sc->mem_size = memsize;
1361 sc->mem_ring = sc->mem_start +
1362 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE);
1363 sc->mem_end = sc->mem_start + sc->mem_size;
1366 * Receive area starts after the transmit area and
1367 * continues till the end of memory.
1370 sc->rec_page_start = sc->tx_page_start +
1371 (sc->txb_cnt * ED_TXBUF_SIZE);
1372 sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE);
1375 sc->cr_proto = 0; /* value works */
1378 * Set the wrap registers for string I/O reads.
1381 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1382 ed_asic_outw(sc, ED_HPP_HW_WRAP,
1383 ((sc->rec_page_start / ED_PAGE_SIZE) |
1384 (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8)));
1387 * Reset the register page to normal operation.
1390 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1393 * Verify that we can read/write from adapter memory.
1394 * Create test pattern.
1397 for (n = 0; n < ED_HPP_TEST_SIZE; n++)
1399 test_pattern[n] = (n*n) ^ ~n;
1402 #undef ED_HPP_TEST_SIZE
1405 * Check that the memory is accessible thru the I/O ports.
1406 * Write out the contents of "test_pattern", read back
1407 * into "test_buffer" and compare the two for any
1411 for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) {
1413 ed_hpp_writemem(sc, test_pattern, (n * ED_PAGE_SIZE),
1414 sizeof(test_pattern));
1415 ed_hpp_readmem(sc, (n * ED_PAGE_SIZE),
1416 test_buffer, sizeof(test_pattern));
1418 if (bcmp(test_pattern, test_buffer,
1419 sizeof(test_pattern)))
1428 * HP PC Lan+ : Set the physical link to use AUI or TP/TL.
1432 ed_hpp_set_physical_link(struct ed_softc *sc)
1434 struct ifnet *ifp = &sc->arpcom.ac_if;
1437 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1438 lan_page = ed_asic_inw(sc, ED_HPP_PAGE_0);
1440 if (ifp->if_flags & IFF_ALTPHYS) {
1446 lan_page |= ED_HPP_LAN_AUI;
1448 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1449 ed_asic_outw(sc, ED_HPP_PAGE_0, lan_page);
1455 * Use the ThinLan interface
1458 lan_page &= ~ED_HPP_LAN_AUI;
1460 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1461 ed_asic_outw(sc, ED_HPP_PAGE_0, lan_page);
1466 * Wait for the lan card to re-initialize itself
1469 DELAY(150000); /* wait 150 ms */
1472 * Restore normal pages.
1475 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1480 * Allocate a port resource with the given resource id.
1483 ed_alloc_port(dev, rid, size)
1488 struct ed_softc *sc = device_get_softc(dev);
1489 struct resource *res;
1491 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1492 0ul, ~0ul, size, RF_ACTIVE);
1496 sc->port_used = size;
1504 * Allocate a memory resource with the given resource id.
1507 ed_alloc_memory(dev, rid, size)
1512 struct ed_softc *sc = device_get_softc(dev);
1513 struct resource *res;
1515 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1516 0ul, ~0ul, size, RF_ACTIVE);
1520 sc->mem_used = size;
1528 * Allocate an irq resource with the given resource id.
1531 ed_alloc_irq(dev, rid, flags)
1536 struct ed_softc *sc = device_get_softc(dev);
1537 struct resource *res;
1539 res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
1540 0ul, ~0ul, 1, (RF_ACTIVE | flags));
1551 * Release all resources
1554 ed_release_resources(dev)
1557 struct ed_softc *sc = device_get_softc(dev);
1560 bus_release_resource(dev, SYS_RES_IOPORT,
1561 sc->port_rid, sc->port_res);
1565 bus_release_resource(dev, SYS_RES_MEMORY,
1566 sc->mem_rid, sc->mem_res);
1570 bus_release_resource(dev, SYS_RES_IRQ,
1571 sc->irq_rid, sc->irq_res);
1577 * Install interface into kernel networking data structures
1580 ed_attach(sc, unit, flags)
1581 struct ed_softc *sc;
1585 struct ifnet *ifp = &sc->arpcom.ac_if;
1587 callout_handle_init(&sc->tick_ch);
1589 * Set interface to stopped condition (reset)
1593 if (!ifp->if_name) {
1595 * Initialize ifnet structure
1598 ifp->if_unit = unit;
1599 ifp->if_name = "ed";
1600 ifp->if_output = ether_output;
1601 ifp->if_start = ed_start;
1602 ifp->if_ioctl = ed_ioctl;
1603 ifp->if_watchdog = ed_watchdog;
1604 ifp->if_init = ed_init;
1605 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
1606 ifp->if_linkmib = &sc->mibdata;
1607 ifp->if_linkmiblen = sizeof sc->mibdata;
1609 * XXX - should do a better job.
1611 if (sc->chip_type == ED_CHIP_TYPE_WD790)
1612 sc->mibdata.dot3StatsEtherChipSet =
1613 DOT3CHIPSET(dot3VendorWesternDigital,
1614 dot3ChipSetWesternDigital83C790);
1616 sc->mibdata.dot3StatsEtherChipSet =
1617 DOT3CHIPSET(dot3VendorNational,
1618 dot3ChipSetNational8390);
1619 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS;
1622 * Set default state for ALTPHYS flag (used to disable the
1623 * tranceiver for AUI operation), based on compile-time
1626 if (flags & ED_FLAGS_DISABLE_TRANCEIVER)
1627 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX |
1628 IFF_MULTICAST | IFF_ALTPHYS);
1630 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX |
1634 * Attach the interface
1636 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1638 /* device attach does transition from UNCONFIGURED to IDLE state */
1641 * Print additional info when attached
1643 printf("%s%d: address %6D, ", ifp->if_name, ifp->if_unit,
1644 sc->arpcom.ac_enaddr, ":");
1646 if (sc->type_str && (*sc->type_str != 0))
1647 printf("type %s ", sc->type_str);
1649 printf("type unknown (0x%x) ", sc->type);
1651 if (sc->vendor == ED_VENDOR_HP)
1652 printf("(%s %s IO)", (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ?
1653 "16-bit" : "32-bit",
1654 sc->hpp_mem_start ? "memory mapped" : "regular");
1656 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)");
1658 printf("%s\n", (((sc->vendor == ED_VENDOR_3COM) ||
1659 (sc->vendor == ED_VENDOR_HP)) &&
1660 (ifp->if_flags & IFF_ALTPHYS)) ? " tranceiver disabled" : "");
1672 struct ed_softc *sc = ifp->if_softc;
1680 * Stop interface and re-initialize.
1689 * Take interface offline.
1693 struct ed_softc *sc;
1697 untimeout(ed_tick, sc, sc->tick_ch);
1698 callout_handle_init(&sc->tick_ch);
1702 * Stop everything on the interface, and select page 0 registers.
1704 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1707 * Wait for interface to enter stopped state, but limit # of checks to
1708 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but
1709 * just in case it's an old one.
1711 if (sc->chip_type != ED_CHIP_TYPE_AX88190)
1712 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) == 0) && --n);
1716 * Device timeout/watchdog routine. Entered if the device neglects to
1717 * generate an interrupt after a transmit has been started on it.
1723 struct ed_softc *sc = ifp->if_softc;
1727 log(LOG_ERR, "ed%d: device timeout\n", ifp->if_unit);
1737 struct ed_softc *sc = arg;
1738 struct mii_data *mii;
1742 callout_handle_init(&sc->tick_ch);
1746 if (sc->miibus != NULL) {
1747 mii = device_get_softc(sc->miibus);
1750 sc->tick_ch = timeout(ed_tick, sc, hz);
1755 * Initialize device.
1761 struct ed_softc *sc = xsc;
1762 struct ifnet *ifp = &sc->arpcom.ac_if;
1768 /* address not known */
1769 if (TAILQ_EMPTY(&ifp->if_addrhead)) /* unlikely? XXX */
1773 * Initialize the NIC in the exact order outlined in the NS manual.
1774 * This init procedure is "mandatory"...don't change what or when
1779 /* reset transmitter flags */
1785 sc->txb_next_tx = 0;
1787 /* This variable is used below - don't move this assignment */
1788 sc->next_packet = sc->rec_page_start + 1;
1791 * Set interface for page 0, Remote DMA complete, Stopped
1793 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1798 * Set FIFO threshold to 8, No auto-init Remote DMA, byte
1799 * order=80x86, word-wide DMA xfers,
1801 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS);
1805 * Same as above, but byte-wide DMA xfers
1807 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
1811 * Clear Remote Byte Count Registers
1813 ed_nic_outb(sc, ED_P0_RBCR0, 0);
1814 ed_nic_outb(sc, ED_P0_RBCR1, 0);
1817 * For the moment, don't store incoming packets in memory.
1819 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON);
1822 * Place NIC in internal loopback mode
1824 ed_nic_outb(sc, ED_P0_TCR, ED_TCR_LB0);
1827 * Initialize transmit/receive (ring-buffer) Page Start
1829 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start);
1830 ed_nic_outb(sc, ED_P0_PSTART, sc->rec_page_start);
1831 /* Set lower bits of byte addressable framing to 0 */
1832 if (sc->chip_type == ED_CHIP_TYPE_WD790)
1833 ed_nic_outb(sc, 0x09, 0);
1836 * Initialize Receiver (ring-buffer) Page Stop and Boundry
1838 ed_nic_outb(sc, ED_P0_PSTOP, sc->rec_page_stop);
1839 ed_nic_outb(sc, ED_P0_BNRY, sc->rec_page_start);
1842 * Clear all interrupts. A '1' in each bit position clears the
1843 * corresponding flag.
1845 ed_nic_outb(sc, ED_P0_ISR, 0xff);
1848 * Enable the following interrupts: receive/transmit complete,
1849 * receive/transmit error, and Receiver OverWrite.
1851 * Counter overflow and Remote DMA complete are *not* enabled.
1853 ed_nic_outb(sc, ED_P0_IMR,
1854 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE);
1857 * Program Command Register for page 1
1859 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
1862 * Copy out our station address
1864 for (i = 0; i < ETHER_ADDR_LEN; ++i)
1865 ed_nic_outb(sc, ED_P1_PAR(i), sc->arpcom.ac_enaddr[i]);
1868 * Set Current Page pointer to next_packet (initialized above)
1870 ed_nic_outb(sc, ED_P1_CURR, sc->next_packet);
1873 * Program Receiver Configuration Register and multicast filter. CR is
1874 * set to page 0 on return.
1879 * Take interface out of loopback
1881 ed_nic_outb(sc, ED_P0_TCR, 0);
1884 * If this is a 3Com board, the tranceiver must be software enabled
1885 * (there is no settable hardware default).
1887 if (sc->vendor == ED_VENDOR_3COM) {
1888 if (ifp->if_flags & IFF_ALTPHYS) {
1889 ed_asic_outb(sc, ED_3COM_CR, 0);
1891 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
1895 if (sc->miibus != NULL) {
1896 struct mii_data *mii;
1897 mii = device_get_softc(sc->miibus);
1901 * Set 'running' flag, and clear output active flag.
1903 ifp->if_flags |= IFF_RUNNING;
1904 ifp->if_flags &= ~IFF_OACTIVE;
1907 * ...and attempt to start output
1911 untimeout(ed_tick, sc, sc->tick_ch);
1912 sc->tick_ch = timeout(ed_tick, sc, hz);
1917 * This routine actually starts the transmission on the interface
1919 static __inline void
1921 struct ed_softc *sc;
1923 struct ifnet *ifp = (struct ifnet *)sc;
1928 len = sc->txb_len[sc->txb_next_tx];
1931 * Set NIC for page 0 register access
1933 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
1936 * Set TX buffer start page
1938 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start +
1939 sc->txb_next_tx * ED_TXBUF_SIZE);
1944 ed_nic_outb(sc, ED_P0_TBCR0, len);
1945 ed_nic_outb(sc, ED_P0_TBCR1, len >> 8);
1948 * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
1950 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA);
1954 * Point to next transmit buffer slot and wrap if necessary.
1957 if (sc->txb_next_tx == sc->txb_cnt)
1958 sc->txb_next_tx = 0;
1961 * Set a timer just in case we never hear from the board again
1967 * Start output on interface.
1968 * We make two assumptions here:
1969 * 1) that the current priority is set to splimp _before_ this code
1970 * is called *and* is returned to the appropriate priority after
1972 * 2) that the IFF_OACTIVE flag is checked before this code is called
1973 * (i.e. that the output part of the interface is idle)
1979 struct ed_softc *sc = ifp->if_softc;
1980 struct mbuf *m0, *m;
1985 printf("ed_start(%p) GONE\n",ifp);
1991 * First, see if there are buffered packets and an idle transmitter -
1992 * should never happen at this point.
1994 if (sc->txb_inuse && (sc->xmit_busy == 0)) {
1995 printf("ed: packets buffered, but transmitter idle\n");
2000 * See if there is room to put another packet in the buffer.
2002 if (sc->txb_inuse == sc->txb_cnt) {
2005 * No room. Indicate this to the outside world and exit.
2007 ifp->if_flags |= IFF_OACTIVE;
2010 IF_DEQUEUE(&ifp->if_snd, m);
2014 * We are using the !OACTIVE flag to indicate to the outside
2015 * world that we can accept an additional packet rather than
2016 * that the transmitter is _actually_ active. Indeed, the
2017 * transmitter may be active, but if we haven't filled all the
2018 * buffers with data then we still want to accept more.
2020 ifp->if_flags &= ~IFF_OACTIVE;
2025 * Copy the mbuf chain into the transmit buffer
2030 /* txb_new points to next open buffer slot */
2031 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE);
2033 if (sc->mem_shared) {
2036 * Special case setup for 16 bit boards...
2039 switch (sc->vendor) {
2042 * For 16bit 3Com boards (which have 16k of
2043 * memory), we have the xmit buffers in a
2044 * different page of memory ('page 0') - so
2047 case ED_VENDOR_3COM:
2048 ed_asic_outb(sc, ED_3COM_GACFR,
2049 ED_3COM_GACFR_RSEL);
2053 * Enable 16bit access to shared memory on
2056 case ED_VENDOR_WD_SMC:
2057 ed_asic_outb(sc, ED_WD_LAAR,
2058 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2059 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2060 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
2065 for (len = 0; m != 0; m = m->m_next) {
2066 bcopy(mtod(m, caddr_t), buffer, m->m_len);
2072 * Restore previous shared memory access
2075 switch (sc->vendor) {
2076 case ED_VENDOR_3COM:
2077 ed_asic_outb(sc, ED_3COM_GACFR,
2078 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
2080 case ED_VENDOR_WD_SMC:
2081 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2082 ed_asic_outb(sc, ED_WD_MSR, 0x00);
2084 ed_asic_outb(sc, ED_WD_LAAR,
2085 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2090 len = ed_pio_write_mbufs(sc, m, (int)buffer);
2095 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN));
2100 * Point to next buffer slot and wrap if necessary.
2103 if (sc->txb_new == sc->txb_cnt)
2106 if (sc->xmit_busy == 0)
2110 * Tap off here if there is a bpf listener.
2119 * Loop back to the top to possibly buffer more packets
2125 * Ethernet interface receiver interrupt.
2127 static __inline void
2129 struct ed_softc *sc;
2131 struct ifnet *ifp = &sc->arpcom.ac_if;
2134 struct ed_ring packet_hdr;
2141 * Set NIC to page 1 registers to get 'current' pointer
2143 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2146 * 'sc->next_packet' is the logical beginning of the ring-buffer -
2147 * i.e. it points to where new data has been buffered. The 'CURR'
2148 * (current) register points to the logical end of the ring-buffer -
2149 * i.e. it points to where additional new data will be added. We loop
2150 * here until the logical beginning equals the logical end (or in
2151 * other words, until the ring-buffer is empty).
2153 while (sc->next_packet != ed_nic_inb(sc, ED_P1_CURR)) {
2155 /* get pointer to this buffer's header structure */
2156 packet_ptr = sc->mem_ring +
2157 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE;
2160 * The byte count includes a 4 byte header that was added by
2164 packet_hdr = *(struct ed_ring *) packet_ptr;
2166 ed_pio_readmem(sc, (int)packet_ptr, (char *) &packet_hdr,
2167 sizeof(packet_hdr));
2168 len = packet_hdr.count;
2169 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) ||
2170 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) {
2172 * Length is a wild value. There's a good chance that
2173 * this was caused by the NIC being old and buggy.
2174 * The bug is that the length low byte is duplicated in
2175 * the high byte. Try to recalculate the length based on
2176 * the pointer to the next packet.
2179 * NOTE: sc->next_packet is pointing at the current packet.
2181 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */
2182 if (packet_hdr.next_packet >= sc->next_packet) {
2183 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE;
2185 len += ((packet_hdr.next_packet - sc->rec_page_start) +
2186 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE;
2189 * because buffers are aligned on 256-byte boundary,
2190 * the length computed above is off by 256 in almost
2191 * all cases. Fix it...
2195 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN
2196 + sizeof(struct ed_ring)))
2197 sc->mibdata.dot3StatsFrameTooLongs++;
2200 * Be fairly liberal about what we allow as a "reasonable" length
2201 * so that a [crufty] packet will make it to BPF (and can thus
2202 * be analyzed). Note that all that is really important is that
2203 * we have a length that will fit into one mbuf cluster or less;
2204 * the upper layer protocols can then figure out the length from
2205 * their own length field(s).
2206 * But make sure that we have at least a full ethernet header
2207 * or we would be unable to call ether_input() later.
2209 if ((len >= sizeof(struct ed_ring) + ETHER_HDR_LEN) &&
2210 (len <= MCLBYTES) &&
2211 (packet_hdr.next_packet >= sc->rec_page_start) &&
2212 (packet_hdr.next_packet < sc->rec_page_stop)) {
2216 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring),
2217 len - sizeof(struct ed_ring));
2221 * Really BAD. The ring pointers are corrupted.
2224 "ed%d: NIC memory corrupt - invalid packet length %d\n",
2232 * Update next packet pointer
2234 sc->next_packet = packet_hdr.next_packet;
2237 * Update NIC boundry pointer - being careful to keep it one
2238 * buffer behind. (as recommended by NS databook)
2240 boundry = sc->next_packet - 1;
2241 if (boundry < sc->rec_page_start)
2242 boundry = sc->rec_page_stop - 1;
2245 * Set NIC to page 0 registers to update boundry register
2247 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2249 ed_nic_outb(sc, ED_P0_BNRY, boundry);
2252 * Set NIC to page 1 registers before looping to top (prepare
2253 * to get 'CURR' current pointer)
2255 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2260 * Ethernet interface interrupt processor
2266 struct ed_softc *sc = (struct ed_softc*) arg;
2267 struct ifnet *ifp = (struct ifnet *)sc;
2273 * Set NIC to page 0 registers
2275 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2278 * loop until there are no more new interrupts
2280 while ((isr = ed_nic_inb(sc, ED_P0_ISR)) != 0) {
2283 * reset all the bits that we are 'acknowledging' by writing a
2284 * '1' to each bit position that was set (writing a '1'
2287 ed_nic_outb(sc, ED_P0_ISR, isr);
2289 /* XXX workaround for AX88190 */
2290 if (sc->chip_type == ED_CHIP_TYPE_AX88190) {
2291 while (ed_nic_inb(sc, ED_P0_ISR) & isr) {
2292 ed_nic_outb(sc, ED_P0_ISR,0);
2293 ed_nic_outb(sc, ED_P0_ISR,isr);
2298 * Handle transmitter interrupts. Handle these first because
2299 * the receiver will reset the board under some conditions.
2301 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) {
2302 u_char collisions = ed_nic_inb(sc, ED_P0_NCR) & 0x0f;
2305 * Check for transmit error. If a TX completed with an
2306 * error, we end up throwing the packet away. Really
2307 * the only error that is possible is excessive
2308 * collisions, and in this case it is best to allow
2309 * the automatic mechanisms of TCP to backoff the
2310 * flow. Of course, with UDP we're screwed, but this
2311 * is expected when a network is heavily loaded.
2313 (void) ed_nic_inb(sc, ED_P0_TSR);
2314 if (isr & ED_ISR_TXE) {
2318 * Excessive collisions (16)
2320 tsr = ed_nic_inb(sc, ED_P0_TSR);
2321 if ((tsr & ED_TSR_ABT)
2322 && (collisions == 0)) {
2325 * When collisions total 16, the
2326 * P0_NCR will indicate 0, and the
2330 sc->mibdata.dot3StatsExcessiveCollisions++;
2331 sc->mibdata.dot3StatsCollFrequencies[15]++;
2333 if (tsr & ED_TSR_OWC)
2334 sc->mibdata.dot3StatsLateCollisions++;
2335 if (tsr & ED_TSR_CDH)
2336 sc->mibdata.dot3StatsSQETestErrors++;
2337 if (tsr & ED_TSR_CRS)
2338 sc->mibdata.dot3StatsCarrierSenseErrors++;
2339 if (tsr & ED_TSR_FU)
2340 sc->mibdata.dot3StatsInternalMacTransmitErrors++;
2343 * update output errors counter
2349 * Update total number of successfully
2350 * transmitted packets.
2356 * reset tx busy and output active flags
2359 ifp->if_flags &= ~IFF_OACTIVE;
2362 * clear watchdog timer
2367 * Add in total number of collisions on last
2370 ifp->if_collisions += collisions;
2371 switch(collisions) {
2376 sc->mibdata.dot3StatsSingleCollisionFrames++;
2377 sc->mibdata.dot3StatsCollFrequencies[0]++;
2380 sc->mibdata.dot3StatsMultipleCollisionFrames++;
2382 dot3StatsCollFrequencies[collisions-1]
2388 * Decrement buffer in-use count if not zero (can only
2389 * be zero if a transmitter interrupt occured while
2390 * not actually transmitting). If data is ready to
2391 * transmit, start it transmitting, otherwise defer
2392 * until after handling receiver
2394 if (sc->txb_inuse && --sc->txb_inuse)
2399 * Handle receiver interrupts
2401 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) {
2404 * Overwrite warning. In order to make sure that a
2405 * lockup of the local DMA hasn't occurred, we reset
2406 * and re-init the NIC. The NSC manual suggests only a
2407 * partial reset/re-init is necessary - but some chips
2408 * seem to want more. The DMA lockup has been seen
2409 * only with early rev chips - Methinks this bug was
2410 * fixed in later revs. -DG
2412 if (isr & ED_ISR_OVW) {
2416 "ed%d: warning - receiver ring buffer overrun\n",
2421 * Stop/reset/re-init NIC
2427 * Receiver Error. One or more of: CRC error,
2428 * frame alignment error FIFO overrun, or
2431 if (isr & ED_ISR_RXE) {
2433 rsr = ed_nic_inb(sc, ED_P0_RSR);
2434 if (rsr & ED_RSR_CRC)
2435 sc->mibdata.dot3StatsFCSErrors++;
2436 if (rsr & ED_RSR_FAE)
2437 sc->mibdata.dot3StatsAlignmentErrors++;
2438 if (rsr & ED_RSR_FO)
2439 sc->mibdata.dot3StatsInternalMacReceiveErrors++;
2442 printf("ed%d: receive error %x\n", ifp->if_unit,
2443 ed_nic_inb(sc, ED_P0_RSR));
2448 * Go get the packet(s) XXX - Doing this on an
2449 * error is dubious because there shouldn't be
2450 * any data to get (we've configured the
2451 * interface to not accept packets with
2456 * Enable 16bit access to shared memory first
2460 (sc->vendor == ED_VENDOR_WD_SMC)) {
2462 ed_asic_outb(sc, ED_WD_LAAR,
2463 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2464 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2465 ed_asic_outb(sc, ED_WD_MSR,
2471 /* disable 16bit access */
2473 (sc->vendor == ED_VENDOR_WD_SMC)) {
2475 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2476 ed_asic_outb(sc, ED_WD_MSR, 0x00);
2478 ed_asic_outb(sc, ED_WD_LAAR,
2479 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2485 * If it looks like the transmitter can take more data,
2486 * attempt to start output on the interface. This is done
2487 * after handling the receiver to give the receiver priority.
2489 if ((ifp->if_flags & IFF_OACTIVE) == 0)
2493 * return NIC CR to standard state: page 0, remote DMA
2494 * complete, start (toggling the TXP bit off, even if was just
2495 * set in the transmit routine, is *okay* - it is 'edge'
2496 * triggered from low to high)
2498 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2501 * If the Network Talley Counters overflow, read them to reset
2502 * them. It appears that old 8390's won't clear the ISR flag
2503 * otherwise - resulting in an infinite loop.
2505 if (isr & ED_ISR_CNT) {
2506 (void) ed_nic_inb(sc, ED_P0_CNTR0);
2507 (void) ed_nic_inb(sc, ED_P0_CNTR1);
2508 (void) ed_nic_inb(sc, ED_P0_CNTR2);
2514 * Process an ioctl request. This code needs some work - it looks
2518 ed_ioctl(ifp, command, data)
2519 register struct ifnet *ifp;
2523 struct ed_softc *sc = ifp->if_softc;
2524 struct ifreq *ifr = (struct ifreq *)data;
2525 struct mii_data *mii;
2528 if (sc == NULL || sc->gone) {
2529 ifp->if_flags &= ~IFF_RUNNING;
2539 error = ether_ioctl(ifp, command, data);
2545 * If the interface is marked up and stopped, then start it.
2546 * If it is marked down and running, then stop it.
2548 if (ifp->if_flags & IFF_UP) {
2549 if ((ifp->if_flags & IFF_RUNNING) == 0)
2552 if (ifp->if_flags & IFF_RUNNING) {
2554 ifp->if_flags &= ~IFF_RUNNING;
2559 * Promiscuous flag may have changed, so reprogram the RCR.
2564 * An unfortunate hack to provide the (required) software
2565 * control of the tranceiver for 3Com boards. The ALTPHYS flag
2566 * disables the tranceiver if set.
2568 if (sc->vendor == ED_VENDOR_3COM) {
2569 if (ifp->if_flags & IFF_ALTPHYS) {
2570 ed_asic_outb(sc, ED_3COM_CR, 0);
2572 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
2574 } else if (sc->vendor == ED_VENDOR_HP)
2575 ed_hpp_set_physical_link(sc);
2581 * Multicast list has changed; set the hardware filter
2590 if (sc->miibus == NULL) {
2594 mii = device_get_softc(sc->miibus);
2595 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2606 * Given a source and destination address, copy 'amount' of a packet from
2607 * the ring buffer into a linear destination buffer. Takes into account
2610 static __inline char *
2611 ed_ring_copy(sc, src, dst, amount)
2612 struct ed_softc *sc;
2619 /* does copy wrap to lower addr in ring buffer? */
2620 if (src + amount > sc->mem_end) {
2621 tmp_amount = sc->mem_end - src;
2623 /* copy amount up to end of NIC memory */
2625 bcopy(src, dst, tmp_amount);
2627 ed_pio_readmem(sc, (int)src, dst, tmp_amount);
2629 amount -= tmp_amount;
2634 bcopy(src, dst, amount);
2636 ed_pio_readmem(sc, (int)src, dst, amount);
2638 return (src + amount);
2642 * Retreive packet from shared memory and send to the next level up via
2646 ed_get_packet(sc, buf, len)
2647 struct ed_softc *sc;
2651 struct ether_header *eh;
2654 /* Allocate a header mbuf */
2655 MGETHDR(m, M_DONTWAIT, MT_DATA);
2658 m->m_pkthdr.rcvif = &sc->arpcom.ac_if;
2659 m->m_pkthdr.len = m->m_len = len;
2662 * We always put the received packet in a single buffer -
2663 * either with just an mbuf header or in a cluster attached
2664 * to the header. The +2 is to compensate for the alignment
2667 if ((len + 2) > MHLEN) {
2668 /* Attach an mbuf cluster */
2669 MCLGET(m, M_DONTWAIT);
2671 /* Insist on getting a cluster */
2672 if ((m->m_flags & M_EXT) == 0) {
2679 * The +2 is to longword align the start of the real packet.
2680 * This is important for NFS.
2683 eh = mtod(m, struct ether_header *);
2686 * Don't read in the entire packet if we know we're going to drop it
2687 * and no bpf is active.
2689 if (!sc->arpcom.ac_if.if_bpf && BDG_ACTIVE( (&sc->arpcom.ac_if) ) ) {
2692 ed_ring_copy(sc, buf, (char *)eh, ETHER_HDR_LEN);
2693 bif = bridge_in_ptr(&sc->arpcom.ac_if, eh) ;
2694 if (bif == BDG_DROP) {
2698 if (len > ETHER_HDR_LEN)
2699 ed_ring_copy(sc, buf + ETHER_HDR_LEN,
2700 (char *)(eh + 1), len - ETHER_HDR_LEN);
2703 * Get packet, including link layer address, from interface.
2705 ed_ring_copy(sc, buf, (char *)eh, len);
2708 * Remove link layer address.
2710 m->m_pkthdr.len = m->m_len = len - sizeof(struct ether_header);
2711 m->m_data += sizeof(struct ether_header);
2713 ether_input(&sc->arpcom.ac_if, eh, m);
2717 * Supporting routines
2721 * Given a NIC memory source address and a host memory destination
2722 * address, copy 'amount' from NIC to host using Programmed I/O.
2723 * The 'amount' is rounded up to a word - okay as long as mbufs
2725 * This routine is currently Novell-specific.
2728 ed_pio_readmem(sc, src, dst, amount)
2729 struct ed_softc *sc;
2732 unsigned short amount;
2734 /* HP PC Lan+ cards need special handling */
2735 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
2736 ed_hpp_readmem(sc, src, dst, amount);
2740 /* Regular Novell cards */
2741 /* select page 0 registers */
2742 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2744 /* round up to a word */
2748 /* set up DMA byte count */
2749 ed_nic_outb(sc, ED_P0_RBCR0, amount);
2750 ed_nic_outb(sc, ED_P0_RBCR1, amount >> 8);
2752 /* set up source address in NIC mem */
2753 ed_nic_outb(sc, ED_P0_RSAR0, src);
2754 ed_nic_outb(sc, ED_P0_RSAR1, src >> 8);
2756 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD0 | ED_CR_STA);
2759 ed_asic_insw(sc, ED_NOVELL_DATA, dst, amount / 2);
2761 ed_asic_insb(sc, ED_NOVELL_DATA, dst, amount);
2766 * Stripped down routine for writing a linear buffer to NIC memory.
2767 * Only used in the probe routine to test the memory. 'len' must
2771 ed_pio_writemem(sc, src, dst, len)
2772 struct ed_softc *sc;
2777 int maxwait = 200; /* about 240us */
2779 /* select page 0 registers */
2780 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2782 /* reset remote DMA complete flag */
2783 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
2785 /* set up DMA byte count */
2786 ed_nic_outb(sc, ED_P0_RBCR0, len);
2787 ed_nic_outb(sc, ED_P0_RBCR1, len >> 8);
2789 /* set up destination address in NIC mem */
2790 ed_nic_outb(sc, ED_P0_RSAR0, dst);
2791 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
2793 /* set remote DMA write */
2794 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2797 ed_asic_outsw(sc, ED_NOVELL_DATA, src, len / 2);
2799 ed_asic_outsb(sc, ED_NOVELL_DATA, src, len);
2803 * Wait for remote DMA complete. This is necessary because on the
2804 * transmit side, data is handled internally by the NIC in bursts and
2805 * we can't start another remote DMA until this one completes. Not
2806 * waiting causes really bad things to happen - like the NIC
2807 * irrecoverably jamming the ISA bus.
2809 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2813 * Write an mbuf chain to the destination NIC memory address using
2817 ed_pio_write_mbufs(sc, m, dst)
2818 struct ed_softc *sc;
2822 struct ifnet *ifp = (struct ifnet *)sc;
2823 unsigned short total_len, dma_len;
2825 int maxwait = 200; /* about 240us */
2827 /* HP PC Lan+ cards need special handling */
2828 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
2829 return ed_hpp_write_mbufs(sc, m, dst);
2832 /* Regular Novell cards */
2833 /* First, count up the total number of bytes to copy */
2834 for (total_len = 0, mp = m; mp; mp = mp->m_next)
2835 total_len += mp->m_len;
2837 dma_len = total_len;
2838 if (sc->isa16bit && (dma_len & 1))
2841 /* select page 0 registers */
2842 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2844 /* reset remote DMA complete flag */
2845 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
2847 /* set up DMA byte count */
2848 ed_nic_outb(sc, ED_P0_RBCR0, dma_len);
2849 ed_nic_outb(sc, ED_P0_RBCR1, dma_len >> 8);
2851 /* set up destination address in NIC mem */
2852 ed_nic_outb(sc, ED_P0_RSAR0, dst);
2853 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
2855 /* set remote DMA write */
2856 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2859 * Transfer the mbuf chain to the NIC memory.
2860 * 16-bit cards require that data be transferred as words, and only words.
2861 * So that case requires some extra code to patch over odd-length mbufs.
2864 if (!sc->isa16bit) {
2865 /* NE1000s are easy */
2868 ed_asic_outsb(sc, ED_NOVELL_DATA,
2869 m->m_data, m->m_len);
2874 /* NE2000s are a pain */
2875 unsigned char *data;
2877 unsigned char savebyte[2];
2884 data = mtod(m, caddr_t);
2885 /* finish the last word */
2887 savebyte[1] = *data;
2888 ed_asic_outw(sc, ED_NOVELL_DATA,
2889 *(u_short *)savebyte);
2894 /* output contiguous words */
2896 ed_asic_outsw(sc, ED_NOVELL_DATA,
2901 /* save last byte, if necessary */
2903 savebyte[0] = *data;
2909 /* spit last byte */
2911 ed_asic_outw(sc, ED_NOVELL_DATA, *(u_short *)savebyte);
2916 * Wait for remote DMA complete. This is necessary because on the
2917 * transmit side, data is handled internally by the NIC in bursts and
2918 * we can't start another remote DMA until this one completes. Not
2919 * waiting causes really bad things to happen - like the NIC
2920 * irrecoverably jamming the ISA bus.
2922 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2925 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n",
2934 * Support routines to handle the HP PC Lan+ card.
2938 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped
2943 ed_hpp_readmem(sc, src, dst, amount)
2944 struct ed_softc *sc;
2947 unsigned short amount;
2950 int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
2953 /* Program the source address in RAM */
2954 ed_asic_outw(sc, ED_HPP_PAGE_2, src);
2957 * The HP PC Lan+ card supports word reads as well as
2958 * a memory mapped i/o port that is aliased to every
2959 * even address on the board.
2962 if (sc->hpp_mem_start) {
2964 /* Enable memory mapped access. */
2965 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
2966 ~(ED_HPP_OPTION_MEM_DISABLE |
2967 ED_HPP_OPTION_BOOT_ROM_ENB));
2969 if (use_32bit_access && (amount > 3)) {
2970 u_int32_t *dl = (u_int32_t *) dst;
2971 volatile u_int32_t *const sl =
2972 (u_int32_t *) sc->hpp_mem_start;
2973 u_int32_t *const fence = dl + (amount >> 2);
2975 /* Copy out NIC data. We could probably write this
2976 as a `movsl'. The currently generated code is lousy.
2982 dst += (amount & ~3);
2987 /* Finish off any words left, as a series of short reads */
2989 u_short *d = (u_short *) dst;
2990 volatile u_short *const s =
2991 (u_short *) sc->hpp_mem_start;
2992 u_short *const fence = d + (amount >> 1);
2994 /* Copy out NIC data. */
2999 dst += (amount & ~1);
3004 * read in a byte; however we need to always read 16 bits
3005 * at a time or the hardware gets into a funny state
3009 /* need to read in a short and copy LSB */
3010 volatile u_short *const s =
3011 (volatile u_short *) sc->hpp_mem_start;
3016 /* Restore Boot ROM access. */
3018 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3022 /* Read in data using the I/O port */
3023 if (use_32bit_access && (amount > 3)) {
3024 ed_asic_insl(sc, ED_HPP_PAGE_4, dst, amount >> 2);
3025 dst += (amount & ~3);
3029 ed_asic_insw(sc, ED_HPP_PAGE_4, dst, amount >> 1);
3030 dst += (amount & ~1);
3033 if (amount == 1) { /* read in a short and keep the LSB */
3034 *dst = ed_asic_inw(sc, ED_HPP_PAGE_4) & 0xFF;
3040 * HP PC Lan+: Write to NIC memory, using either PIO or memory mapped
3042 * Only used in the probe routine to test the memory. 'len' must
3046 ed_hpp_writemem(sc, src, dst, len)
3047 struct ed_softc *sc;
3052 /* reset remote DMA complete flag */
3053 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
3055 /* program the write address in RAM */
3056 ed_asic_outw(sc, ED_HPP_PAGE_0, dst);
3058 if (sc->hpp_mem_start) {
3059 u_short *s = (u_short *) src;
3060 volatile u_short *d = (u_short *) sc->hpp_mem_start;
3061 u_short *const fence = s + (len >> 1);
3064 * Enable memory mapped access.
3067 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3068 ~(ED_HPP_OPTION_MEM_DISABLE |
3069 ED_HPP_OPTION_BOOT_ROM_ENB));
3072 * Copy to NIC memory.
3079 * Restore Boot ROM access.
3082 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3085 /* write data using I/O writes */
3086 ed_asic_outsw(sc, ED_HPP_PAGE_4, src, len / 2);
3091 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using
3092 * outsw() or via the memory mapped interface to the same register.
3093 * Writes have to be in word units; byte accesses won't work and may cause
3094 * the NIC to behave wierdly. Long word accesses are permitted if the ASIC
3099 ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst)
3102 unsigned short total_len;
3103 unsigned char savebyte[2];
3104 volatile u_short * const d =
3105 (volatile u_short *) sc->hpp_mem_start;
3106 int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
3108 /* select page 0 registers */
3109 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
3111 /* reset remote DMA complete flag */
3112 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
3114 /* program the write address in RAM */
3115 ed_asic_outw(sc, ED_HPP_PAGE_0, dst);
3117 if (sc->hpp_mem_start) /* enable memory mapped I/O */
3118 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3119 ~(ED_HPP_OPTION_MEM_DISABLE |
3120 ED_HPP_OPTION_BOOT_ROM_ENB));
3125 if (sc->hpp_mem_start) { /* Memory mapped I/O port */
3127 total_len += (len = m->m_len);
3129 caddr_t data = mtod(m, caddr_t);
3130 /* finish the last word of the previous mbuf */
3132 savebyte[1] = *data;
3133 *d = *((ushort *) savebyte);
3134 data++; len--; wantbyte = 0;
3136 /* output contiguous words */
3137 if ((len > 3) && (use_32bit_accesses)) {
3138 volatile u_int32_t *const dl =
3139 (volatile u_int32_t *) d;
3140 u_int32_t *sl = (u_int32_t *) data;
3141 u_int32_t *fence = sl + (len >> 2);
3149 /* finish off remain 16 bit writes */
3151 u_short *s = (u_short *) data;
3152 u_short *fence = s + (len >> 1);
3160 /* save last byte if needed */
3161 if ((wantbyte = (len == 1)) != 0)
3162 savebyte[0] = *data;
3164 m = m->m_next; /* to next mbuf */
3166 if (wantbyte) /* write last byte */
3167 *d = *((u_short *) savebyte);
3169 /* use programmed I/O */
3171 total_len += (len = m->m_len);
3173 caddr_t data = mtod(m, caddr_t);
3174 /* finish the last word of the previous mbuf */
3176 savebyte[1] = *data;
3177 ed_asic_outw(sc, ED_HPP_PAGE_4,
3178 *((u_short *)savebyte));
3183 /* output contiguous words */
3184 if ((len > 3) && use_32bit_accesses) {
3185 ed_asic_outsl(sc, ED_HPP_PAGE_4,
3190 /* finish off remaining 16 bit accesses */
3192 ed_asic_outsw(sc, ED_HPP_PAGE_4,
3197 if ((wantbyte = (len == 1)) != 0)
3198 savebyte[0] = *data;
3203 if (wantbyte) /* spit last byte */
3204 ed_asic_outw(sc, ED_HPP_PAGE_4, *(u_short *)savebyte);
3208 if (sc->hpp_mem_start) /* turn off memory mapped i/o */
3209 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3215 * MII bus support routines.
3218 ed_miibus_readreg(dev, phy, reg)
3222 struct ed_softc *sc;
3226 sc = device_get_softc(dev);
3232 (*sc->mii_writebits)(sc, 0xffffffff, 32);
3233 (*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS);
3234 (*sc->mii_writebits)(sc, ED_MII_READOP, ED_MII_OP_BITS);
3235 (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS);
3236 (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS);
3238 failed = (*sc->mii_readbits)(sc, ED_MII_ACK_BITS);
3239 val = (*sc->mii_readbits)(sc, ED_MII_DATA_BITS);
3240 (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS);
3243 return (failed ? 0 : val);
3247 ed_miibus_writereg(dev, phy, reg, data)
3251 struct ed_softc *sc;
3255 sc = device_get_softc(dev);
3261 (*sc->mii_writebits)(sc, 0xffffffff, 32);
3262 (*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS);
3263 (*sc->mii_writebits)(sc, ED_MII_WRITEOP, ED_MII_OP_BITS);
3264 (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS);
3265 (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS);
3266 (*sc->mii_writebits)(sc, ED_MII_TURNAROUND, ED_MII_TURNAROUND_BITS);
3267 (*sc->mii_writebits)(sc, data, ED_MII_DATA_BITS);
3268 (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS);
3277 struct ed_softc *sc;
3278 struct mii_data *mii;
3281 if (sc->gone || sc->miibus == NULL)
3284 mii = device_get_softc(sc->miibus);
3285 return mii_mediachg(mii);
3289 ed_ifmedia_sts(ifp, ifmr)
3291 struct ifmediareq *ifmr;
3293 struct ed_softc *sc;
3294 struct mii_data *mii;
3297 if (sc->gone || sc->miibus == NULL)
3300 mii = device_get_softc(sc->miibus);
3302 ifmr->ifm_active = mii->mii_media_active;
3303 ifmr->ifm_status = mii->mii_media_status;
3307 ed_child_detached(dev, child)
3311 struct ed_softc *sc;
3313 sc = device_get_softc(dev);
3314 if (child == sc->miibus)
3320 struct ed_softc *sc;
3322 struct ifnet *ifp = (struct ifnet *)sc;
3326 /* Bit 6 in AX88190 RCR register must be set. */
3327 if (sc->chip_type == ED_CHIP_TYPE_AX88190)
3332 /* set page 1 registers */
3333 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
3335 if (ifp->if_flags & IFF_PROMISC) {
3338 * Reconfigure the multicast filter.
3340 for (i = 0; i < 8; i++)
3341 ed_nic_outb(sc, ED_P1_MAR(i), 0xff);
3344 * And turn on promiscuous mode. Also enable reception of
3345 * runts and packets with CRC & alignment errors.
3347 /* Set page 0 registers */
3348 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3350 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM |
3351 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP | reg1);
3353 /* set up multicast addresses and filter modes */
3354 if (ifp->if_flags & IFF_MULTICAST) {
3357 if (ifp->if_flags & IFF_ALLMULTI) {
3358 mcaf[0] = 0xffffffff;
3359 mcaf[1] = 0xffffffff;
3361 ds_getmcaf(sc, mcaf);
3364 * Set multicast filter on chip.
3366 for (i = 0; i < 8; i++)
3367 ed_nic_outb(sc, ED_P1_MAR(i), ((u_char *) mcaf)[i]);
3369 /* Set page 0 registers */
3370 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3372 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AM | ED_RCR_AB | reg1);
3376 * Initialize multicast address hashing registers to
3377 * not accept multicasts.
3379 for (i = 0; i < 8; ++i)
3380 ed_nic_outb(sc, ED_P1_MAR(i), 0x00);
3382 /* Set page 0 registers */
3383 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3385 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AB | reg1);
3392 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
3396 * Compute crc for ethernet address
3402 #define POLYNOMIAL 0x04c11db6
3403 register u_int32_t crc = 0xffffffff;
3404 register int carry, i, j;
3407 for (i = 6; --i >= 0;) {
3409 for (j = 8; --j >= 0;) {
3410 carry = ((crc & 0x80000000) ? 1 : 0) ^ (b & 0x01);
3414 crc = (crc ^ POLYNOMIAL) | carry;
3422 * Compute the multicast address filter from the
3423 * list of multicast addresses we need to listen to.
3426 ds_getmcaf(sc, mcaf)
3427 struct ed_softc *sc;
3430 register u_int32_t index;
3431 register u_char *af = (u_char *) mcaf;
3432 struct ifmultiaddr *ifma;
3437 for (ifma = sc->arpcom.ac_if.if_multiaddrs.lh_first; ifma;
3438 ifma = ifma->ifma_link.le_next) {
3439 if (ifma->ifma_addr->sa_family != AF_LINK)
3441 index = ds_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr))
3443 af[index >> 3] |= 1 << (index & 7);