2 * Copyright (c) 1995, David Greenman
3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * $FreeBSD: src/sys/dev/fxp/if_fxp.c,v 1.110.2.30 2003/06/12 16:47:05 mux Exp $
32 * Intel EtherExpress Pro/100B PCI Fast Ethernet driver
35 #include <sys/param.h>
36 #include <sys/systm.h>
38 #include <sys/malloc.h>
39 /* #include <sys/mutex.h> */
40 #include <sys/kernel.h>
41 #include <sys/socket.h>
42 #include <sys/sysctl.h>
45 #include <net/if_dl.h>
46 #include <net/if_media.h>
50 #include <netns/ns_if.h>
54 #include <sys/sockio.h>
56 #include <machine/bus.h>
58 #include <machine/resource.h>
60 #include <net/ethernet.h>
61 #include <net/if_arp.h>
63 #include <vm/vm.h> /* for vtophys */
64 #include <vm/pmap.h> /* for vtophys */
65 #include <machine/clock.h> /* for DELAY */
67 #include <net/if_types.h>
68 #include <net/if_vlan_var.h>
70 #include <pci/pcivar.h>
71 #include <pci/pcireg.h> /* for PCIM_CMD_xxx */
73 #include <dev/mii/mii.h>
74 #include <dev/mii/miivar.h>
76 #include <dev/fxp/if_fxpreg.h>
77 #include <dev/fxp/if_fxpvar.h>
78 #include <dev/fxp/rcvbundl.h>
80 MODULE_DEPEND(fxp, miibus, 1, 1, 1);
81 #include "miibus_if.h"
84 * NOTE! On the Alpha, we have an alignment constraint. The
85 * card DMAs the packet immediately following the RFA. However,
86 * the first thing in the packet is a 14-byte Ethernet header.
87 * This means that the packet is misaligned. To compensate,
88 * we actually offset the RFA 2 bytes into the cluster. This
89 * alignes the packet after the Ethernet header at a 32-bit
90 * boundary. HOWEVER! This means that the RFA is misaligned!
92 #define RFA_ALIGNMENT_FUDGE 2
95 * Set initial transmit threshold at 64 (512 bytes). This is
96 * increased by 64 (512 bytes) at a time, to maximum of 192
97 * (1536 bytes), if an underrun occurs.
99 static int tx_threshold = 64;
102 * The configuration byte map has several undefined fields which
103 * must be one or must be zero. Set up a template for these bits
104 * only, (assuming a 82557 chip) leaving the actual configuration
107 * See struct fxp_cb_config for the bit definitions.
109 static u_char fxp_cb_config_template[] = {
110 0x0, 0x0, /* cb_status */
111 0x0, 0x0, /* cb_command */
112 0x0, 0x0, 0x0, 0x0, /* link_addr */
143 * Claim various Intel PCI device identifiers for this driver. The
144 * sub-vendor and sub-device field are extensively used to identify
145 * particular variants, but we don't currently differentiate between
148 static struct fxp_ident fxp_ident_table[] = {
149 { 0x1029, "Intel 82559 PCI/CardBus Pro/100" },
150 { 0x1030, "Intel 82559 Pro/100 Ethernet" },
151 { 0x1031, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
152 { 0x1032, "Intel 82801CAM (ICH3) Pro/100 VE Ethernet" },
153 { 0x1033, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
154 { 0x1034, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
155 { 0x1035, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
156 { 0x1036, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
157 { 0x1037, "Intel 82801CAM (ICH3) Pro/100 Ethernet" },
158 { 0x1038, "Intel 82801CAM (ICH3) Pro/100 VM Ethernet" },
159 { 0x1039, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
160 { 0x103A, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
161 { 0x103B, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
162 { 0x103C, "Intel 82801DB (ICH4) Pro/100 Ethernet" },
163 { 0x103D, "Intel 82801DB (ICH4) Pro/100 VE Ethernet" },
164 { 0x103E, "Intel 82801DB (ICH4) Pro/100 VM Ethernet" },
165 { 0x1050, "Intel 82801BA (D865) Pro/100 VE Ethernet" },
166 { 0x1059, "Intel 82551QM Pro/100 M Mobile Connection" },
167 { 0x1209, "Intel 82559ER Embedded 10/100 Ethernet" },
168 { 0x1229, "Intel 82557/8/9 EtherExpress Pro/100(B) Ethernet" },
169 { 0x2449, "Intel 82801BA/CAM (ICH2/3) Pro/100 Ethernet" },
173 static int fxp_probe(device_t dev);
174 static int fxp_attach(device_t dev);
175 static int fxp_detach(device_t dev);
176 static int fxp_shutdown(device_t dev);
177 static int fxp_suspend(device_t dev);
178 static int fxp_resume(device_t dev);
180 static void fxp_intr(void *xsc);
181 static void fxp_intr_body(struct fxp_softc *sc,
182 u_int8_t statack, int count);
184 static void fxp_init(void *xsc);
185 static void fxp_tick(void *xsc);
186 static void fxp_powerstate_d0(device_t dev);
187 static void fxp_start(struct ifnet *ifp);
188 static void fxp_stop(struct fxp_softc *sc);
189 static void fxp_release(struct fxp_softc *sc);
190 static int fxp_ioctl(struct ifnet *ifp, u_long command,
192 static void fxp_watchdog(struct ifnet *ifp);
193 static int fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm);
194 static int fxp_mc_addrs(struct fxp_softc *sc);
195 static void fxp_mc_setup(struct fxp_softc *sc);
196 static u_int16_t fxp_eeprom_getword(struct fxp_softc *sc, int offset,
198 static void fxp_eeprom_putword(struct fxp_softc *sc, int offset,
200 static void fxp_autosize_eeprom(struct fxp_softc *sc);
201 static void fxp_read_eeprom(struct fxp_softc *sc, u_short *data,
202 int offset, int words);
203 static void fxp_write_eeprom(struct fxp_softc *sc, u_short *data,
204 int offset, int words);
205 static int fxp_ifmedia_upd(struct ifnet *ifp);
206 static void fxp_ifmedia_sts(struct ifnet *ifp,
207 struct ifmediareq *ifmr);
208 static int fxp_serial_ifmedia_upd(struct ifnet *ifp);
209 static void fxp_serial_ifmedia_sts(struct ifnet *ifp,
210 struct ifmediareq *ifmr);
211 static volatile int fxp_miibus_readreg(device_t dev, int phy, int reg);
212 static void fxp_miibus_writereg(device_t dev, int phy, int reg,
214 static void fxp_load_ucode(struct fxp_softc *sc);
215 static int sysctl_int_range(SYSCTL_HANDLER_ARGS,
217 static int sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS);
218 static int sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS);
219 static __inline void fxp_lwcopy(volatile u_int32_t *src,
220 volatile u_int32_t *dst);
221 static __inline void fxp_scb_wait(struct fxp_softc *sc);
222 static __inline void fxp_scb_cmd(struct fxp_softc *sc, int cmd);
223 static __inline void fxp_dma_wait(volatile u_int16_t *status,
224 struct fxp_softc *sc);
226 static device_method_t fxp_methods[] = {
227 /* Device interface */
228 DEVMETHOD(device_probe, fxp_probe),
229 DEVMETHOD(device_attach, fxp_attach),
230 DEVMETHOD(device_detach, fxp_detach),
231 DEVMETHOD(device_shutdown, fxp_shutdown),
232 DEVMETHOD(device_suspend, fxp_suspend),
233 DEVMETHOD(device_resume, fxp_resume),
236 DEVMETHOD(miibus_readreg, fxp_miibus_readreg),
237 DEVMETHOD(miibus_writereg, fxp_miibus_writereg),
242 static driver_t fxp_driver = {
245 sizeof(struct fxp_softc),
248 static devclass_t fxp_devclass;
250 DRIVER_MODULE(if_fxp, pci, fxp_driver, fxp_devclass, 0, 0);
251 DRIVER_MODULE(if_fxp, cardbus, fxp_driver, fxp_devclass, 0, 0);
252 DRIVER_MODULE(miibus, fxp, miibus_driver, miibus_devclass, 0, 0);
255 SYSCTL_INT(_hw, OID_AUTO, fxp_rnr, CTLFLAG_RW, &fxp_rnr, 0, "fxp rnr events");
258 * Inline function to copy a 16-bit aligned 32-bit quantity.
261 fxp_lwcopy(volatile u_int32_t *src, volatile u_int32_t *dst)
266 volatile u_int16_t *a = (volatile u_int16_t *)src;
267 volatile u_int16_t *b = (volatile u_int16_t *)dst;
275 * Wait for the previous command to be accepted (but not necessarily
279 fxp_scb_wait(struct fxp_softc *sc)
283 while (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) && --i)
286 device_printf(sc->dev, "SCB timeout: 0x%x 0x%x 0x%x 0x%x\n",
287 CSR_READ_1(sc, FXP_CSR_SCB_COMMAND),
288 CSR_READ_1(sc, FXP_CSR_SCB_STATACK),
289 CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS),
290 CSR_READ_2(sc, FXP_CSR_FLOWCONTROL));
294 fxp_scb_cmd(struct fxp_softc *sc, int cmd)
297 if (cmd == FXP_SCB_COMMAND_CU_RESUME && sc->cu_resume_bug) {
298 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP);
301 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd);
305 fxp_dma_wait(volatile u_int16_t *status, struct fxp_softc *sc)
309 while (!(*status & FXP_CB_STATUS_C) && --i)
312 device_printf(sc->dev, "DMA timeout\n");
316 * Return identification string if this is device is ours.
319 fxp_probe(device_t dev)
322 struct fxp_ident *ident;
324 if (pci_get_vendor(dev) == FXP_VENDORID_INTEL) {
325 devid = pci_get_device(dev);
326 for (ident = fxp_ident_table; ident->name != NULL; ident++) {
327 if (ident->devid == devid) {
328 device_set_desc(dev, ident->name);
337 fxp_powerstate_d0(device_t dev)
339 #if __FreeBSD_version >= 430002
340 u_int32_t iobase, membase, irq;
342 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
343 /* Save important PCI config data. */
344 iobase = pci_read_config(dev, FXP_PCI_IOBA, 4);
345 membase = pci_read_config(dev, FXP_PCI_MMBA, 4);
346 irq = pci_read_config(dev, PCIR_INTLINE, 4);
348 /* Reset the power state. */
349 device_printf(dev, "chip is in D%d power mode "
350 "-- setting to D0\n", pci_get_powerstate(dev));
352 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
354 /* Restore PCI config data. */
355 pci_write_config(dev, FXP_PCI_IOBA, iobase, 4);
356 pci_write_config(dev, FXP_PCI_MMBA, membase, 4);
357 pci_write_config(dev, PCIR_INTLINE, irq, 4);
363 fxp_attach(device_t dev)
366 struct fxp_softc *sc = device_get_softc(dev);
370 int i, rid, m1, m2, prefer_iomap;
373 bzero(sc, sizeof(*sc));
375 callout_handle_init(&sc->stat_ch);
376 sysctl_ctx_init(&sc->sysctl_ctx);
377 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE);
382 * Enable bus mastering. Enable memory space too, in case
383 * BIOS/Prom forgot about it.
385 val = pci_read_config(dev, PCIR_COMMAND, 2);
386 val |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
387 pci_write_config(dev, PCIR_COMMAND, val, 2);
388 val = pci_read_config(dev, PCIR_COMMAND, 2);
390 fxp_powerstate_d0(dev);
393 * Figure out which we should try first - memory mapping or i/o mapping?
394 * We default to memory mapping. Then we accept an override from the
395 * command line. Then we check to see which one is enabled.
398 m2 = PCIM_CMD_PORTEN;
400 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
401 "prefer_iomap", &prefer_iomap) == 0 && prefer_iomap != 0) {
402 m1 = PCIM_CMD_PORTEN;
408 (m1 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
409 sc->rgd = (m1 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
410 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd,
411 0, ~0, 1, RF_ACTIVE);
413 if (sc->mem == NULL && (val & m2)) {
415 (m2 == PCIM_CMD_MEMEN)? SYS_RES_MEMORY : SYS_RES_IOPORT;
416 sc->rgd = (m2 == PCIM_CMD_MEMEN)? FXP_PCI_MMBA : FXP_PCI_IOBA;
417 sc->mem = bus_alloc_resource(dev, sc->rtp, &sc->rgd,
418 0, ~0, 1, RF_ACTIVE);
422 device_printf(dev, "could not map device registers\n");
427 device_printf(dev, "using %s space register mapping\n",
428 sc->rtp == SYS_RES_MEMORY? "memory" : "I/O");
431 sc->sc_st = rman_get_bustag(sc->mem);
432 sc->sc_sh = rman_get_bushandle(sc->mem);
435 * Allocate our interrupt.
438 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
439 RF_SHAREABLE | RF_ACTIVE);
440 if (sc->irq == NULL) {
441 device_printf(dev, "could not map interrupt\n");
446 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET,
447 fxp_intr, sc, &sc->ih);
449 device_printf(dev, "could not setup irq\n");
454 * Reset to a stable state.
456 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
459 sc->cbl_base = malloc(sizeof(struct fxp_cb_tx) * FXP_NTXCB,
460 M_DEVBUF, M_NOWAIT | M_ZERO);
461 if (sc->cbl_base == NULL)
464 sc->fxp_stats = malloc(sizeof(struct fxp_stats), M_DEVBUF,
466 if (sc->fxp_stats == NULL)
469 sc->mcsp = malloc(sizeof(struct fxp_cb_mcs), M_DEVBUF, M_NOWAIT);
470 if (sc->mcsp == NULL)
474 * Pre-allocate our receive buffers.
476 for (i = 0; i < FXP_NRFABUFS; i++) {
477 if (fxp_add_rfabuf(sc, NULL) != 0) {
483 * Find out how large of an SEEPROM we have.
485 fxp_autosize_eeprom(sc);
488 * Determine whether we must use the 503 serial interface.
490 fxp_read_eeprom(sc, &data, 6, 1);
491 if ((data & FXP_PHY_DEVICE_MASK) != 0 &&
492 (data & FXP_PHY_SERIAL_ONLY))
493 sc->flags |= FXP_FLAG_SERIAL_MEDIA;
496 * Create the sysctl tree
498 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
499 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
500 device_get_nameunit(dev), CTLFLAG_RD, 0, "");
501 if (sc->sysctl_tree == NULL)
503 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
504 OID_AUTO, "int_delay", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON,
505 &sc->tunable_int_delay, 0, &sysctl_hw_fxp_int_delay, "I",
506 "FXP driver receive interrupt microcode bundling delay");
507 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
508 OID_AUTO, "bundle_max", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_PRISON,
509 &sc->tunable_bundle_max, 0, &sysctl_hw_fxp_bundle_max, "I",
510 "FXP driver receive interrupt microcode bundle size limit");
513 * Pull in device tunables.
515 sc->tunable_int_delay = TUNABLE_INT_DELAY;
516 sc->tunable_bundle_max = TUNABLE_BUNDLE_MAX;
517 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
518 "int_delay", &sc->tunable_int_delay);
519 (void) resource_int_value(device_get_name(dev), device_get_unit(dev),
520 "bundle_max", &sc->tunable_bundle_max);
523 * Find out the chip revision; lump all 82557 revs together.
525 fxp_read_eeprom(sc, &data, 5, 1);
526 if ((data >> 8) == 1)
527 sc->revision = FXP_REV_82557;
529 sc->revision = pci_get_revid(dev);
532 * Enable workarounds for certain chip revision deficiencies.
534 * Systems based on the ICH2/ICH2-M chip from Intel, and possibly
535 * some systems based a normal 82559 design, have a defect where
536 * the chip can cause a PCI protocol violation if it receives
537 * a CU_RESUME command when it is entering the IDLE state. The
538 * workaround is to disable Dynamic Standby Mode, so the chip never
539 * deasserts CLKRUN#, and always remains in an active state.
541 * See Intel 82801BA/82801BAM Specification Update, Errata #30.
543 i = pci_get_device(dev);
544 if (i == 0x2449 || (i > 0x1030 && i < 0x1039) ||
545 sc->revision >= FXP_REV_82559_A0) {
546 fxp_read_eeprom(sc, &data, 10, 1);
547 if (data & 0x02) { /* STB enable */
552 "Disabling dynamic standby mode in EEPROM\n");
554 fxp_write_eeprom(sc, &data, 10, 1);
555 device_printf(dev, "New EEPROM ID: 0x%x\n", data);
557 for (i = 0; i < (1 << sc->eeprom_size) - 1; i++) {
558 fxp_read_eeprom(sc, &data, i, 1);
561 i = (1 << sc->eeprom_size) - 1;
562 cksum = 0xBABA - cksum;
563 fxp_read_eeprom(sc, &data, i, 1);
564 fxp_write_eeprom(sc, &cksum, i, 1);
566 "EEPROM checksum @ 0x%x: 0x%x -> 0x%x\n",
570 * If the user elects to continue, try the software
571 * workaround, as it is better than nothing.
573 sc->flags |= FXP_FLAG_CU_RESUME_BUG;
579 * If we are not a 82557 chip, we can enable extended features.
581 if (sc->revision != FXP_REV_82557) {
583 * If MWI is enabled in the PCI configuration, and there
584 * is a valid cacheline size (8 or 16 dwords), then tell
585 * the board to turn on MWI.
587 if (val & PCIM_CMD_MWRICEN &&
588 pci_read_config(dev, PCIR_CACHELNSZ, 1) != 0)
589 sc->flags |= FXP_FLAG_MWI_ENABLE;
591 /* turn on the extended TxCB feature */
592 sc->flags |= FXP_FLAG_EXT_TXCB;
594 /* enable reception of long frames for VLAN */
595 sc->flags |= FXP_FLAG_LONG_PKT_EN;
601 fxp_read_eeprom(sc, (u_int16_t *)sc->arpcom.ac_enaddr, 0, 3);
602 device_printf(dev, "Ethernet address %6D%s\n",
603 sc->arpcom.ac_enaddr, ":",
604 sc->flags & FXP_FLAG_SERIAL_MEDIA ? ", 10Mbps" : "");
606 device_printf(dev, "PCI IDs: %04x %04x %04x %04x %04x\n",
607 pci_get_vendor(dev), pci_get_device(dev),
608 pci_get_subvendor(dev), pci_get_subdevice(dev),
610 fxp_read_eeprom(sc, &data, 10, 1);
611 device_printf(dev, "Dynamic Standby mode is %s\n",
612 data & 0x02 ? "enabled" : "disabled");
616 * If this is only a 10Mbps device, then there is no MII, and
617 * the PHY will use a serial interface instead.
619 * The Seeq 80c24 AutoDUPLEX(tm) Ethernet Interface Adapter
620 * doesn't have a programming interface of any sort. The
621 * media is sensed automatically based on how the link partner
622 * is configured. This is, in essence, manual configuration.
624 if (sc->flags & FXP_FLAG_SERIAL_MEDIA) {
625 ifmedia_init(&sc->sc_media, 0, fxp_serial_ifmedia_upd,
626 fxp_serial_ifmedia_sts);
627 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
628 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
630 if (mii_phy_probe(dev, &sc->miibus, fxp_ifmedia_upd,
632 device_printf(dev, "MII without any PHY!\n");
638 ifp = &sc->arpcom.ac_if;
639 ifp->if_unit = device_get_unit(dev);
640 ifp->if_name = "fxp";
641 ifp->if_output = ether_output;
642 ifp->if_baudrate = 100000000;
643 ifp->if_init = fxp_init;
645 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
646 ifp->if_ioctl = fxp_ioctl;
647 ifp->if_start = fxp_start;
648 ifp->if_watchdog = fxp_watchdog;
651 * Attach the interface.
653 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
656 * Tell the upper layer(s) we support long frames.
658 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
661 * Let the system queue as many packets as we have available
664 ifp->if_snd.ifq_maxlen = FXP_NTXCB - 1;
670 device_printf(dev, "Failed to malloc memory\n");
679 * release all resources
682 fxp_release(struct fxp_softc *sc)
685 bus_generic_detach(sc->dev);
687 device_delete_child(sc->dev, sc->miibus);
690 free(sc->cbl_base, M_DEVBUF);
692 free(sc->fxp_stats, M_DEVBUF);
694 free(sc->mcsp, M_DEVBUF);
696 m_freem(sc->rfa_headm);
699 bus_teardown_intr(sc->dev, sc->irq, sc->ih);
701 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq);
703 bus_release_resource(sc->dev, sc->rtp, sc->rgd, sc->mem);
705 sysctl_ctx_free(&sc->sysctl_ctx);
707 mtx_destroy(&sc->sc_mtx);
714 fxp_detach(device_t dev)
716 struct fxp_softc *sc = device_get_softc(dev);
719 /* disable interrupts */
720 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
725 * Stop DMA and drop transmit queue.
730 * Close down routes etc.
732 ether_ifdetach(&sc->arpcom.ac_if, ETHER_BPF_SUPPORTED);
735 * Free all media structures.
737 ifmedia_removeall(&sc->sc_media);
741 /* Release our allocated resources. */
748 * Device shutdown routine. Called at system shutdown after sync. The
749 * main purpose of this routine is to shut off receiver DMA so that
750 * kernel memory doesn't get clobbered during warmboot.
753 fxp_shutdown(device_t dev)
756 * Make sure that DMA is disabled prior to reboot. Not doing
757 * do could allow DMA to corrupt kernel memory during the
758 * reboot before the driver initializes.
760 fxp_stop((struct fxp_softc *) device_get_softc(dev));
765 * Device suspend routine. Stop the interface and save some PCI
766 * settings in case the BIOS doesn't restore them properly on
770 fxp_suspend(device_t dev)
772 struct fxp_softc *sc = device_get_softc(dev);
779 for (i = 0; i < 5; i++)
780 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
781 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
782 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
783 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
784 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
793 * Device resume routine. Restore some PCI settings in case the BIOS
794 * doesn't, re-enable busmastering, and restart the interface if
798 fxp_resume(device_t dev)
800 struct fxp_softc *sc = device_get_softc(dev);
801 struct ifnet *ifp = &sc->sc_if;
802 u_int16_t pci_command;
807 fxp_powerstate_d0(dev);
809 /* better way to do this? */
810 for (i = 0; i < 5; i++)
811 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
812 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
813 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
814 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
815 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
817 /* reenable busmastering */
818 pci_command = pci_read_config(dev, PCIR_COMMAND, 2);
819 pci_command |= (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
820 pci_write_config(dev, PCIR_COMMAND, pci_command, 2);
822 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
825 /* reinitialize interface if necessary */
826 if (ifp->if_flags & IFF_UP)
836 fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
844 for (x = 1 << (length - 1); x; x >>= 1) {
846 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
848 reg = FXP_EEPROM_EECS;
849 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
851 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
853 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
859 * Read from the serial EEPROM. Basically, you manually shift in
860 * the read opcode (one bit at a time) and then shift in the address,
861 * and then you shift out the data (all of this one bit at a time).
862 * The word size is 16 bits, so you have to provide the address for
863 * every 16 bits of data.
866 fxp_eeprom_getword(struct fxp_softc *sc, int offset, int autosize)
871 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
873 * Shift in read opcode.
875 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_READ, 3);
880 for (x = 1 << (sc->eeprom_size - 1); x; x >>= 1) {
882 reg = FXP_EEPROM_EECS | FXP_EEPROM_EEDI;
884 reg = FXP_EEPROM_EECS;
885 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
887 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
889 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
891 reg = CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO;
893 if (autosize && reg == 0) {
894 sc->eeprom_size = data;
902 reg = FXP_EEPROM_EECS;
903 for (x = 1 << 15; x; x >>= 1) {
904 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
906 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
908 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
911 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
918 fxp_eeprom_putword(struct fxp_softc *sc, int offset, u_int16_t data)
923 * Erase/write enable.
925 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
926 fxp_eeprom_shiftin(sc, 0x4, 3);
927 fxp_eeprom_shiftin(sc, 0x03 << (sc->eeprom_size - 2), sc->eeprom_size);
928 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
931 * Shift in write opcode, address, data.
933 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
934 fxp_eeprom_shiftin(sc, FXP_EEPROM_OPC_WRITE, 3);
935 fxp_eeprom_shiftin(sc, offset, sc->eeprom_size);
936 fxp_eeprom_shiftin(sc, data, 16);
937 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
940 * Wait for EEPROM to finish up.
942 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
944 for (i = 0; i < 1000; i++) {
945 if (CSR_READ_2(sc, FXP_CSR_EEPROMCONTROL) & FXP_EEPROM_EEDO)
949 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
952 * Erase/write disable.
954 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
955 fxp_eeprom_shiftin(sc, 0x4, 3);
956 fxp_eeprom_shiftin(sc, 0, sc->eeprom_size);
957 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
964 * Figure out EEPROM size.
966 * 559's can have either 64-word or 256-word EEPROMs, the 558
967 * datasheet only talks about 64-word EEPROMs, and the 557 datasheet
968 * talks about the existance of 16 to 256 word EEPROMs.
970 * The only known sizes are 64 and 256, where the 256 version is used
971 * by CardBus cards to store CIS information.
973 * The address is shifted in msb-to-lsb, and after the last
974 * address-bit the EEPROM is supposed to output a `dummy zero' bit,
975 * after which follows the actual data. We try to detect this zero, by
976 * probing the data-out bit in the EEPROM control register just after
977 * having shifted in a bit. If the bit is zero, we assume we've
978 * shifted enough address bits. The data-out should be tri-state,
979 * before this, which should translate to a logical one.
982 fxp_autosize_eeprom(struct fxp_softc *sc)
985 /* guess maximum size of 256 words */
989 (void) fxp_eeprom_getword(sc, 0, 1);
993 fxp_read_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
997 for (i = 0; i < words; i++)
998 data[i] = fxp_eeprom_getword(sc, offset + i, 0);
1002 fxp_write_eeprom(struct fxp_softc *sc, u_short *data, int offset, int words)
1006 for (i = 0; i < words; i++)
1007 fxp_eeprom_putword(sc, offset + i, data[i]);
1011 * Start packet transmission on the interface.
1014 fxp_start(struct ifnet *ifp)
1016 struct fxp_softc *sc = ifp->if_softc;
1017 struct fxp_cb_tx *txp;
1020 * See if we need to suspend xmit until the multicast filter
1021 * has been reprogrammed (which can only be done at the head
1022 * of the command chain).
1024 if (sc->need_mcsetup) {
1031 * We're finished if there is nothing more to add to the list or if
1032 * we're all filled up with buffers to transmit.
1033 * NOTE: One TxCB is reserved to guarantee that fxp_mc_setup() can add
1034 * a NOP command when needed.
1036 while (ifp->if_snd.ifq_head != NULL && sc->tx_queued < FXP_NTXCB - 1) {
1037 struct mbuf *m, *mb_head;
1041 * Grab a packet to transmit.
1043 IF_DEQUEUE(&ifp->if_snd, mb_head);
1046 * Get pointer to next available tx desc.
1048 txp = sc->cbl_last->next;
1051 * Go through each of the mbufs in the chain and initialize
1052 * the transmit buffer descriptors with the physical address
1053 * and size of the mbuf.
1056 for (m = mb_head, segment = 0; m != NULL; m = m->m_next) {
1057 if (m->m_len != 0) {
1058 if (segment == FXP_NTXSEG)
1060 txp->tbd[segment].tb_addr =
1061 vtophys(mtod(m, vm_offset_t));
1062 txp->tbd[segment].tb_size = m->m_len;
1070 * We ran out of segments. We have to recopy this
1071 * mbuf chain first. Bail out if we can't get the
1074 MGETHDR(mn, M_DONTWAIT, MT_DATA);
1079 if (mb_head->m_pkthdr.len > MHLEN) {
1080 MCLGET(mn, M_DONTWAIT);
1081 if ((mn->m_flags & M_EXT) == 0) {
1087 m_copydata(mb_head, 0, mb_head->m_pkthdr.len,
1089 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len;
1095 txp->tbd_number = segment;
1096 txp->mb_head = mb_head;
1098 if (sc->tx_queued != FXP_CXINT_THRESH - 1) {
1100 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF |
1104 FXP_CB_COMMAND_XMIT | FXP_CB_COMMAND_SF |
1105 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
1107 * Set a 5 second timer just in case we don't hear
1108 * from the card again.
1112 txp->tx_threshold = tx_threshold;
1115 * Advance the end of list forward.
1120 * On platforms which can't access memory in 16-bit
1121 * granularities, we must prevent the card from DMA'ing
1122 * up the status while we update the command field.
1123 * This could cause us to overwrite the completion status.
1125 atomic_clear_short(&sc->cbl_last->cb_command,
1128 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
1129 #endif /*__alpha__*/
1133 * Advance the beginning of the list forward if there are
1134 * no other packets queued (when nothing is queued, cbl_first
1135 * sits on the last TxCB that was sent out).
1137 if (sc->tx_queued == 0)
1138 sc->cbl_first = txp;
1143 * Pass packet to bpf if there is a listener.
1146 bpf_mtap(ifp, mb_head);
1150 * We're finished. If we added to the list, issue a RESUME to get DMA
1151 * going again if suspended.
1155 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
1159 #ifdef DEVICE_POLLING
1160 static poll_handler_t fxp_poll;
1163 fxp_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1165 struct fxp_softc *sc = ifp->if_softc;
1168 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1169 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1172 statack = FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA |
1174 if (cmd == POLL_AND_CHECK_STATUS) {
1177 tmp = CSR_READ_1(sc, FXP_CSR_SCB_STATACK);
1178 if (tmp == 0xff || tmp == 0)
1179 return; /* nothing to do */
1181 /* ack what we can */
1183 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp);
1186 fxp_intr_body(sc, statack, count);
1188 #endif /* DEVICE_POLLING */
1191 * Process interface interrupts.
1196 struct fxp_softc *sc = xsc;
1199 #ifdef DEVICE_POLLING
1200 struct ifnet *ifp = &sc->sc_if;
1202 if (ifp->if_ipending & IFF_POLLING)
1204 if (ether_poll_register(fxp_poll, ifp)) {
1205 /* disable interrupts */
1206 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1207 fxp_poll(ifp, 0, 1);
1212 if (sc->suspended) {
1216 while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
1218 * It should not be possible to have all bits set; the
1219 * FXP_SCB_INTR_SWI bit always returns 0 on a read. If
1220 * all bits are set, this may indicate that the card has
1221 * been physically ejected, so ignore it.
1223 if (statack == 0xff)
1227 * First ACK all the interrupts in this pass.
1229 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack);
1230 fxp_intr_body(sc, statack, -1);
1235 fxp_intr_body(struct fxp_softc *sc, u_int8_t statack, int count)
1237 struct ifnet *ifp = &sc->sc_if;
1239 struct fxp_rfa *rfa;
1240 int rnr = (statack & FXP_SCB_STATACK_RNR) ? 1 : 0;
1244 #ifdef DEVICE_POLLING
1245 /* Pick up a deferred RNR condition if `count' ran out last time. */
1246 if (sc->flags & FXP_FLAG_DEFERRED_RNR) {
1247 sc->flags &= ~FXP_FLAG_DEFERRED_RNR;
1253 * Free any finished transmit mbuf chains.
1255 * Handle the CNA event likt a CXTNO event. It used to
1256 * be that this event (control unit not ready) was not
1257 * encountered, but it is now with the SMPng modifications.
1258 * The exact sequence of events that occur when the interface
1259 * is brought up are different now, and if this event
1260 * goes unhandled, the configuration/rxfilter setup sequence
1261 * can stall for several seconds. The result is that no
1262 * packets go out onto the wire for about 5 to 10 seconds
1263 * after the interface is ifconfig'ed for the first time.
1265 if (statack & (FXP_SCB_STATACK_CXTNO | FXP_SCB_STATACK_CNA)) {
1266 struct fxp_cb_tx *txp;
1268 for (txp = sc->cbl_first; sc->tx_queued &&
1269 (txp->cb_status & FXP_CB_STATUS_C) != 0;
1271 if (txp->mb_head != NULL) {
1272 m_freem(txp->mb_head);
1273 txp->mb_head = NULL;
1277 sc->cbl_first = txp;
1279 if (sc->tx_queued == 0) {
1280 if (sc->need_mcsetup)
1284 * Try to start more packets transmitting.
1286 if (ifp->if_snd.ifq_head != NULL)
1291 * Just return if nothing happened on the receive side.
1293 if (!rnr && (statack & FXP_SCB_STATACK_FR) == 0)
1297 * Process receiver interrupts. If a no-resource (RNR)
1298 * condition exists, get whatever packets we can and
1299 * re-start the receiver.
1301 * When using polling, we do not process the list to completion,
1302 * so when we get an RNR interrupt we must defer the restart
1303 * until we hit the last buffer with the C bit set.
1304 * If we run out of cycles and rfa_headm has the C bit set,
1305 * record the pending RNR in the FXP_FLAG_DEFERRED_RNR flag so
1306 * that the info will be used in the subsequent polling cycle.
1310 rfa = (struct fxp_rfa *)(m->m_ext.ext_buf +
1311 RFA_ALIGNMENT_FUDGE);
1313 #ifdef DEVICE_POLLING /* loop at most count times if count >=0 */
1314 if (count >= 0 && count-- == 0) {
1316 /* Defer RNR processing until the next time. */
1317 sc->flags |= FXP_FLAG_DEFERRED_RNR;
1322 #endif /* DEVICE_POLLING */
1324 if ( (rfa->rfa_status & FXP_RFA_STATUS_C) == 0)
1328 * Remove first packet from the chain.
1330 sc->rfa_headm = m->m_next;
1334 * Add a new buffer to the receive chain.
1335 * If this fails, the old buffer is recycled
1338 if (fxp_add_rfabuf(sc, m) == 0) {
1342 * Fetch packet length (the top 2 bits of
1343 * actual_size are flags set by the controller
1344 * upon completion), and drop the packet in case
1345 * of bogus length or CRC errors.
1347 total_len = rfa->actual_size & 0x3fff;
1348 if (total_len < sizeof(struct ether_header) ||
1349 total_len > MCLBYTES - RFA_ALIGNMENT_FUDGE -
1350 sizeof(struct fxp_rfa) ||
1351 rfa->rfa_status & FXP_RFA_STATUS_CRC) {
1355 m->m_pkthdr.len = m->m_len = total_len;
1356 ether_input(ifp, NULL, m);
1361 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1362 vtophys(sc->rfa_headm->m_ext.ext_buf) +
1363 RFA_ALIGNMENT_FUDGE);
1364 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1369 * Update packet in/out/collision statistics. The i82557 doesn't
1370 * allow you to access these counters without doing a fairly
1371 * expensive DMA to get _all_ of the statistics it maintains, so
1372 * we do this operation here only once per second. The statistics
1373 * counters in the kernel are updated from the previous dump-stats
1374 * DMA and then a new dump-stats DMA is started. The on-chip
1375 * counters are zeroed when the DMA completes. If we can't start
1376 * the DMA immediately, we don't wait - we just prepare to read
1377 * them again next time.
1382 struct fxp_softc *sc = xsc;
1383 struct ifnet *ifp = &sc->sc_if;
1384 struct fxp_stats *sp = sc->fxp_stats;
1385 struct fxp_cb_tx *txp;
1388 ifp->if_opackets += sp->tx_good;
1389 ifp->if_collisions += sp->tx_total_collisions;
1391 ifp->if_ipackets += sp->rx_good;
1392 sc->rx_idle_secs = 0;
1395 * Receiver's been idle for another second.
1401 sp->rx_alignment_errors +
1403 sp->rx_overrun_errors;
1405 * If any transmit underruns occured, bump up the transmit
1406 * threshold by another 512 bytes (64 * 8).
1408 if (sp->tx_underruns) {
1409 ifp->if_oerrors += sp->tx_underruns;
1410 if (tx_threshold < 192)
1415 * Release any xmit buffers that have completed DMA. This isn't
1416 * strictly necessary to do here, but it's advantagous for mbufs
1417 * with external storage to be released in a timely manner rather
1418 * than being defered for a potentially long time. This limits
1419 * the delay to a maximum of one second.
1421 for (txp = sc->cbl_first; sc->tx_queued &&
1422 (txp->cb_status & FXP_CB_STATUS_C) != 0;
1424 if (txp->mb_head != NULL) {
1425 m_freem(txp->mb_head);
1426 txp->mb_head = NULL;
1430 sc->cbl_first = txp;
1432 * If we haven't received any packets in FXP_MAC_RX_IDLE seconds,
1433 * then assume the receiver has locked up and attempt to clear
1434 * the condition by reprogramming the multicast filter. This is
1435 * a work-around for a bug in the 82557 where the receiver locks
1436 * up if it gets certain types of garbage in the syncronization
1437 * bits prior to the packet header. This bug is supposed to only
1438 * occur in 10Mbps mode, but has been seen to occur in 100Mbps
1439 * mode as well (perhaps due to a 10/100 speed transition).
1441 if (sc->rx_idle_secs > FXP_MAX_RX_IDLE) {
1442 sc->rx_idle_secs = 0;
1446 * If there is no pending command, start another stats
1447 * dump. Otherwise punt for now.
1449 if (CSR_READ_1(sc, FXP_CSR_SCB_COMMAND) == 0) {
1451 * Start another stats dump.
1453 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMPRESET);
1456 * A previous command is still waiting to be accepted.
1457 * Just zero our copy of the stats and wait for the
1458 * next timer event to update them.
1461 sp->tx_underruns = 0;
1462 sp->tx_total_collisions = 0;
1465 sp->rx_crc_errors = 0;
1466 sp->rx_alignment_errors = 0;
1467 sp->rx_rnr_errors = 0;
1468 sp->rx_overrun_errors = 0;
1470 if (sc->miibus != NULL)
1471 mii_tick(device_get_softc(sc->miibus));
1474 * Schedule another timeout one second from now.
1476 sc->stat_ch = timeout(fxp_tick, sc, hz);
1480 * Stop the interface. Cancels the statistics updater and resets
1484 fxp_stop(struct fxp_softc *sc)
1486 struct ifnet *ifp = &sc->sc_if;
1487 struct fxp_cb_tx *txp;
1490 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1493 #ifdef DEVICE_POLLING
1494 ether_poll_deregister(ifp);
1497 * Cancel stats updater.
1499 untimeout(fxp_tick, sc, sc->stat_ch);
1502 * Issue software reset, which also unloads the microcode.
1504 sc->flags &= ~FXP_FLAG_UCODE;
1505 CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
1509 * Release any xmit buffers.
1513 for (i = 0; i < FXP_NTXCB; i++) {
1514 if (txp[i].mb_head != NULL) {
1515 m_freem(txp[i].mb_head);
1516 txp[i].mb_head = NULL;
1523 * Free all the receive buffers then reallocate/reinitialize
1525 if (sc->rfa_headm != NULL)
1526 m_freem(sc->rfa_headm);
1527 sc->rfa_headm = NULL;
1528 sc->rfa_tailm = NULL;
1529 for (i = 0; i < FXP_NRFABUFS; i++) {
1530 if (fxp_add_rfabuf(sc, NULL) != 0) {
1532 * This "can't happen" - we're at splimp()
1533 * and we just freed all the buffers we need
1536 panic("fxp_stop: no buffers!");
1542 * Watchdog/transmission transmit timeout handler. Called when a
1543 * transmission is started on the interface, but no interrupt is
1544 * received before the timeout. This usually indicates that the
1545 * card has wedged for some reason.
1548 fxp_watchdog(struct ifnet *ifp)
1550 struct fxp_softc *sc = ifp->if_softc;
1552 device_printf(sc->dev, "device timeout\n");
1561 struct fxp_softc *sc = xsc;
1562 struct ifnet *ifp = &sc->sc_if;
1563 struct fxp_cb_config *cbp;
1564 struct fxp_cb_ias *cb_ias;
1565 struct fxp_cb_tx *txp;
1566 struct fxp_cb_mcs *mcsp;
1571 * Cancel any pending I/O
1575 prm = (ifp->if_flags & IFF_PROMISC) ? 1 : 0;
1578 * Initialize base of CBL and RFA memory. Loading with zero
1579 * sets it up for regular linear addressing.
1581 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, 0);
1582 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_BASE);
1585 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_BASE);
1588 * Initialize base of dump-stats buffer.
1591 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(sc->fxp_stats));
1592 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_DUMP_ADR);
1595 * Attempt to load microcode if requested.
1597 if (ifp->if_flags & IFF_LINK0 && (sc->flags & FXP_FLAG_UCODE) == 0)
1601 * Initialize the multicast address list.
1603 if (fxp_mc_addrs(sc)) {
1605 mcsp->cb_status = 0;
1606 mcsp->cb_command = FXP_CB_COMMAND_MCAS | FXP_CB_COMMAND_EL;
1607 mcsp->link_addr = -1;
1609 * Start the multicast setup command.
1612 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
1613 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1614 /* ...and wait for it to complete. */
1615 fxp_dma_wait(&mcsp->cb_status, sc);
1619 * We temporarily use memory that contains the TxCB list to
1620 * construct the config CB. The TxCB list memory is rebuilt
1623 cbp = (struct fxp_cb_config *) sc->cbl_base;
1626 * This bcopy is kind of disgusting, but there are a bunch of must be
1627 * zero and must be one bits in this structure and this is the easiest
1628 * way to initialize them all to proper values.
1630 bcopy(fxp_cb_config_template,
1631 (void *)(uintptr_t)(volatile void *)&cbp->cb_status,
1632 sizeof(fxp_cb_config_template));
1635 cbp->cb_command = FXP_CB_COMMAND_CONFIG | FXP_CB_COMMAND_EL;
1636 cbp->link_addr = -1; /* (no) next command */
1637 cbp->byte_count = 22; /* (22) bytes to config */
1638 cbp->rx_fifo_limit = 8; /* rx fifo threshold (32 bytes) */
1639 cbp->tx_fifo_limit = 0; /* tx fifo threshold (0 bytes) */
1640 cbp->adaptive_ifs = 0; /* (no) adaptive interframe spacing */
1641 cbp->mwi_enable = sc->flags & FXP_FLAG_MWI_ENABLE ? 1 : 0;
1642 cbp->type_enable = 0; /* actually reserved */
1643 cbp->read_align_en = sc->flags & FXP_FLAG_READ_ALIGN ? 1 : 0;
1644 cbp->end_wr_on_cl = sc->flags & FXP_FLAG_WRITE_ALIGN ? 1 : 0;
1645 cbp->rx_dma_bytecount = 0; /* (no) rx DMA max */
1646 cbp->tx_dma_bytecount = 0; /* (no) tx DMA max */
1647 cbp->dma_mbce = 0; /* (disable) dma max counters */
1648 cbp->late_scb = 0; /* (don't) defer SCB update */
1649 cbp->direct_dma_dis = 1; /* disable direct rcv dma mode */
1650 cbp->tno_int_or_tco_en =0; /* (disable) tx not okay interrupt */
1651 cbp->ci_int = 1; /* interrupt on CU idle */
1652 cbp->ext_txcb_dis = sc->flags & FXP_FLAG_EXT_TXCB ? 0 : 1;
1653 cbp->ext_stats_dis = 1; /* disable extended counters */
1654 cbp->keep_overrun_rx = 0; /* don't pass overrun frames to host */
1655 cbp->save_bf = sc->revision == FXP_REV_82557 ? 1 : prm;
1656 cbp->disc_short_rx = !prm; /* discard short packets */
1657 cbp->underrun_retry = 1; /* retry mode (once) on DMA underrun */
1658 cbp->two_frames = 0; /* do not limit FIFO to 2 frames */
1659 cbp->dyn_tbd = 0; /* (no) dynamic TBD mode */
1660 cbp->mediatype = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 0 : 1;
1661 cbp->csma_dis = 0; /* (don't) disable link */
1662 cbp->tcp_udp_cksum = 0; /* (don't) enable checksum */
1663 cbp->vlan_tco = 0; /* (don't) enable vlan wakeup */
1664 cbp->link_wake_en = 0; /* (don't) assert PME# on link change */
1665 cbp->arp_wake_en = 0; /* (don't) assert PME# on arp */
1666 cbp->mc_wake_en = 0; /* (don't) enable PME# on mcmatch */
1667 cbp->nsai = 1; /* (don't) disable source addr insert */
1668 cbp->preamble_length = 2; /* (7 byte) preamble */
1669 cbp->loopback = 0; /* (don't) loopback */
1670 cbp->linear_priority = 0; /* (normal CSMA/CD operation) */
1671 cbp->linear_pri_mode = 0; /* (wait after xmit only) */
1672 cbp->interfrm_spacing = 6; /* (96 bits of) interframe spacing */
1673 cbp->promiscuous = prm; /* promiscuous mode */
1674 cbp->bcast_disable = 0; /* (don't) disable broadcasts */
1675 cbp->wait_after_win = 0; /* (don't) enable modified backoff alg*/
1676 cbp->ignore_ul = 0; /* consider U/L bit in IA matching */
1677 cbp->crc16_en = 0; /* (don't) enable crc-16 algorithm */
1678 cbp->crscdt = sc->flags & FXP_FLAG_SERIAL_MEDIA ? 1 : 0;
1680 cbp->stripping = !prm; /* truncate rx packet to byte count */
1681 cbp->padding = 1; /* (do) pad short tx packets */
1682 cbp->rcv_crc_xfer = 0; /* (don't) xfer CRC to host */
1683 cbp->long_rx_en = sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
1684 cbp->ia_wake_en = 0; /* (don't) wake up on address match */
1685 cbp->magic_pkt_dis = 0; /* (don't) disable magic packet */
1686 /* must set wake_en in PMCSR also */
1687 cbp->force_fdx = 0; /* (don't) force full duplex */
1688 cbp->fdx_pin_en = 1; /* (enable) FDX# pin */
1689 cbp->multi_ia = 0; /* (don't) accept multiple IAs */
1690 cbp->mc_all = sc->flags & FXP_FLAG_ALL_MCAST ? 1 : 0;
1692 if (sc->revision == FXP_REV_82557) {
1694 * The 82557 has no hardware flow control, the values
1695 * below are the defaults for the chip.
1697 cbp->fc_delay_lsb = 0;
1698 cbp->fc_delay_msb = 0x40;
1699 cbp->pri_fc_thresh = 3;
1701 cbp->rx_fc_restop = 0;
1702 cbp->rx_fc_restart = 0;
1704 cbp->pri_fc_loc = 1;
1706 cbp->fc_delay_lsb = 0x1f;
1707 cbp->fc_delay_msb = 0x01;
1708 cbp->pri_fc_thresh = 3;
1709 cbp->tx_fc_dis = 0; /* enable transmit FC */
1710 cbp->rx_fc_restop = 1; /* enable FC restop frames */
1711 cbp->rx_fc_restart = 1; /* enable FC restart frames */
1712 cbp->fc_filter = !prm; /* drop FC frames to host */
1713 cbp->pri_fc_loc = 1; /* FC pri location (byte31) */
1717 * Start the config command/DMA.
1720 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
1721 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1722 /* ...and wait for it to complete. */
1723 fxp_dma_wait(&cbp->cb_status, sc);
1726 * Now initialize the station address. Temporarily use the TxCB
1727 * memory area like we did above for the config CB.
1729 cb_ias = (struct fxp_cb_ias *) sc->cbl_base;
1730 cb_ias->cb_status = 0;
1731 cb_ias->cb_command = FXP_CB_COMMAND_IAS | FXP_CB_COMMAND_EL;
1732 cb_ias->link_addr = -1;
1733 bcopy(sc->arpcom.ac_enaddr,
1734 (void *)(uintptr_t)(volatile void *)cb_ias->macaddr,
1735 sizeof(sc->arpcom.ac_enaddr));
1738 * Start the IAS (Individual Address Setup) command/DMA.
1741 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1742 /* ...and wait for it to complete. */
1743 fxp_dma_wait(&cb_ias->cb_status, sc);
1746 * Initialize transmit control block (TxCB) list.
1750 bzero(txp, sizeof(struct fxp_cb_tx) * FXP_NTXCB);
1751 for (i = 0; i < FXP_NTXCB; i++) {
1752 txp[i].cb_status = FXP_CB_STATUS_C | FXP_CB_STATUS_OK;
1753 txp[i].cb_command = FXP_CB_COMMAND_NOP;
1755 vtophys(&txp[(i + 1) & FXP_TXCB_MASK].cb_status);
1756 if (sc->flags & FXP_FLAG_EXT_TXCB)
1757 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[2]);
1759 txp[i].tbd_array_addr = vtophys(&txp[i].tbd[0]);
1760 txp[i].next = &txp[(i + 1) & FXP_TXCB_MASK];
1763 * Set the suspend flag on the first TxCB and start the control
1764 * unit. It will execute the NOP and then suspend.
1766 txp->cb_command = FXP_CB_COMMAND_NOP | FXP_CB_COMMAND_S;
1767 sc->cbl_first = sc->cbl_last = txp;
1771 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
1774 * Initialize receiver buffer area - RFA.
1777 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL,
1778 vtophys(sc->rfa_headm->m_ext.ext_buf) + RFA_ALIGNMENT_FUDGE);
1779 fxp_scb_cmd(sc, FXP_SCB_COMMAND_RU_START);
1782 * Set current media.
1784 if (sc->miibus != NULL)
1785 mii_mediachg(device_get_softc(sc->miibus));
1787 ifp->if_flags |= IFF_RUNNING;
1788 ifp->if_flags &= ~IFF_OACTIVE;
1791 * Enable interrupts.
1793 #ifdef DEVICE_POLLING
1795 * ... but only do that if we are not polling. And because (presumably)
1796 * the default is interrupts on, we need to disable them explicitly!
1798 if ( ifp->if_ipending & IFF_POLLING )
1799 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE);
1801 #endif /* DEVICE_POLLING */
1802 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, 0);
1806 * Start stats updater.
1808 sc->stat_ch = timeout(fxp_tick, sc, hz);
1812 fxp_serial_ifmedia_upd(struct ifnet *ifp)
1819 fxp_serial_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1822 ifmr->ifm_active = IFM_ETHER|IFM_MANUAL;
1826 * Change media according to request.
1829 fxp_ifmedia_upd(struct ifnet *ifp)
1831 struct fxp_softc *sc = ifp->if_softc;
1832 struct mii_data *mii;
1834 mii = device_get_softc(sc->miibus);
1840 * Notify the world which media we're using.
1843 fxp_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1845 struct fxp_softc *sc = ifp->if_softc;
1846 struct mii_data *mii;
1848 mii = device_get_softc(sc->miibus);
1850 ifmr->ifm_active = mii->mii_media_active;
1851 ifmr->ifm_status = mii->mii_media_status;
1853 if (ifmr->ifm_status & IFM_10_T && sc->flags & FXP_FLAG_CU_RESUME_BUG)
1854 sc->cu_resume_bug = 1;
1856 sc->cu_resume_bug = 0;
1860 * Add a buffer to the end of the RFA buffer list.
1861 * Return 0 if successful, 1 for failure. A failure results in
1862 * adding the 'oldm' (if non-NULL) on to the end of the list -
1863 * tossing out its old contents and recycling it.
1864 * The RFA struct is stuck at the beginning of mbuf cluster and the
1865 * data pointer is fixed up to point just past it.
1868 fxp_add_rfabuf(struct fxp_softc *sc, struct mbuf *oldm)
1872 struct fxp_rfa *rfa, *p_rfa;
1874 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1875 if (m == NULL) { /* try to recycle the old mbuf instead */
1879 m->m_data = m->m_ext.ext_buf;
1883 * Move the data pointer up so that the incoming data packet
1884 * will be 32-bit aligned.
1886 m->m_data += RFA_ALIGNMENT_FUDGE;
1889 * Get a pointer to the base of the mbuf cluster and move
1890 * data start past it.
1892 rfa = mtod(m, struct fxp_rfa *);
1893 m->m_data += sizeof(struct fxp_rfa);
1894 rfa->size = (u_int16_t)(MCLBYTES - sizeof(struct fxp_rfa) - RFA_ALIGNMENT_FUDGE);
1897 * Initialize the rest of the RFA. Note that since the RFA
1898 * is misaligned, we cannot store values directly. Instead,
1899 * we use an optimized, inline copy.
1902 rfa->rfa_status = 0;
1903 rfa->rfa_control = FXP_RFA_CONTROL_EL;
1904 rfa->actual_size = 0;
1907 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->link_addr);
1908 fxp_lwcopy(&v, (volatile u_int32_t *) rfa->rbd_addr);
1911 * If there are other buffers already on the list, attach this
1912 * one to the end by fixing up the tail to point to this one.
1914 if (sc->rfa_headm != NULL) {
1915 p_rfa = (struct fxp_rfa *) (sc->rfa_tailm->m_ext.ext_buf +
1916 RFA_ALIGNMENT_FUDGE);
1917 sc->rfa_tailm->m_next = m;
1919 fxp_lwcopy(&v, (volatile u_int32_t *) p_rfa->link_addr);
1920 p_rfa->rfa_control = 0;
1930 fxp_miibus_readreg(device_t dev, int phy, int reg)
1932 struct fxp_softc *sc = device_get_softc(dev);
1936 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
1937 (FXP_MDI_READ << 26) | (reg << 16) | (phy << 21));
1939 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) & 0x10000000) == 0
1944 device_printf(dev, "fxp_miibus_readreg: timed out\n");
1946 return (value & 0xffff);
1950 fxp_miibus_writereg(device_t dev, int phy, int reg, int value)
1952 struct fxp_softc *sc = device_get_softc(dev);
1955 CSR_WRITE_4(sc, FXP_CSR_MDICONTROL,
1956 (FXP_MDI_WRITE << 26) | (reg << 16) | (phy << 21) |
1959 while ((CSR_READ_4(sc, FXP_CSR_MDICONTROL) & 0x10000000) == 0 &&
1964 device_printf(dev, "fxp_miibus_writereg: timed out\n");
1968 fxp_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1970 struct fxp_softc *sc = ifp->if_softc;
1971 struct ifreq *ifr = (struct ifreq *)data;
1972 struct mii_data *mii;
1981 error = ether_ioctl(ifp, command, data);
1985 if (ifp->if_flags & IFF_ALLMULTI)
1986 sc->flags |= FXP_FLAG_ALL_MCAST;
1988 sc->flags &= ~FXP_FLAG_ALL_MCAST;
1991 * If interface is marked up and not running, then start it.
1992 * If it is marked down and running, stop it.
1993 * XXX If it's up then re-initialize it. This is so flags
1994 * such as IFF_PROMISC are handled.
1996 if (ifp->if_flags & IFF_UP) {
1999 if (ifp->if_flags & IFF_RUNNING)
2006 if (ifp->if_flags & IFF_ALLMULTI)
2007 sc->flags |= FXP_FLAG_ALL_MCAST;
2009 sc->flags &= ~FXP_FLAG_ALL_MCAST;
2011 * Multicast list has changed; set the hardware filter
2014 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0)
2017 * fxp_mc_setup() can set FXP_FLAG_ALL_MCAST, so check it
2018 * again rather than else {}.
2020 if (sc->flags & FXP_FLAG_ALL_MCAST)
2027 if (sc->miibus != NULL) {
2028 mii = device_get_softc(sc->miibus);
2029 error = ifmedia_ioctl(ifp, ifr,
2030 &mii->mii_media, command);
2032 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, command);
2044 * Fill in the multicast address list and return number of entries.
2047 fxp_mc_addrs(struct fxp_softc *sc)
2049 struct fxp_cb_mcs *mcsp = sc->mcsp;
2050 struct ifnet *ifp = &sc->sc_if;
2051 struct ifmultiaddr *ifma;
2055 if ((sc->flags & FXP_FLAG_ALL_MCAST) == 0) {
2056 #if __FreeBSD_version < 500000
2057 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2059 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2061 if (ifma->ifma_addr->sa_family != AF_LINK)
2063 if (nmcasts >= MAXMCADDR) {
2064 sc->flags |= FXP_FLAG_ALL_MCAST;
2068 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
2069 (void *)(uintptr_t)(volatile void *)
2070 &sc->mcsp->mc_addr[nmcasts][0], 6);
2074 mcsp->mc_cnt = nmcasts * 6;
2079 * Program the multicast filter.
2081 * We have an artificial restriction that the multicast setup command
2082 * must be the first command in the chain, so we take steps to ensure
2083 * this. By requiring this, it allows us to keep up the performance of
2084 * the pre-initialized command ring (esp. link pointers) by not actually
2085 * inserting the mcsetup command in the ring - i.e. its link pointer
2086 * points to the TxCB ring, but the mcsetup descriptor itself is not part
2087 * of it. We then can do 'CU_START' on the mcsetup descriptor and have it
2088 * lead into the regular TxCB ring when it completes.
2090 * This function must be called at splimp.
2093 fxp_mc_setup(struct fxp_softc *sc)
2095 struct fxp_cb_mcs *mcsp = sc->mcsp;
2096 struct ifnet *ifp = &sc->sc_if;
2100 * If there are queued commands, we must wait until they are all
2101 * completed. If we are already waiting, then add a NOP command
2102 * with interrupt option so that we're notified when all commands
2103 * have been completed - fxp_start() ensures that no additional
2104 * TX commands will be added when need_mcsetup is true.
2106 if (sc->tx_queued) {
2107 struct fxp_cb_tx *txp;
2110 * need_mcsetup will be true if we are already waiting for the
2111 * NOP command to be completed (see below). In this case, bail.
2113 if (sc->need_mcsetup)
2115 sc->need_mcsetup = 1;
2118 * Add a NOP command with interrupt so that we are notified
2119 * when all TX commands have been processed.
2121 txp = sc->cbl_last->next;
2122 txp->mb_head = NULL;
2124 txp->cb_command = FXP_CB_COMMAND_NOP |
2125 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
2127 * Advance the end of list forward.
2129 sc->cbl_last->cb_command &= ~FXP_CB_COMMAND_S;
2133 * Issue a resume in case the CU has just suspended.
2136 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_RESUME);
2138 * Set a 5 second timer just in case we don't hear from the
2145 sc->need_mcsetup = 0;
2148 * Initialize multicast setup descriptor.
2150 mcsp->next = sc->cbl_base;
2151 mcsp->mb_head = NULL;
2152 mcsp->cb_status = 0;
2153 mcsp->cb_command = FXP_CB_COMMAND_MCAS |
2154 FXP_CB_COMMAND_S | FXP_CB_COMMAND_I;
2155 mcsp->link_addr = vtophys(&sc->cbl_base->cb_status);
2156 (void) fxp_mc_addrs(sc);
2157 sc->cbl_first = sc->cbl_last = (struct fxp_cb_tx *) mcsp;
2161 * Wait until command unit is not active. This should never
2162 * be the case when nothing is queued, but make sure anyway.
2165 while ((CSR_READ_1(sc, FXP_CSR_SCB_RUSCUS) >> 6) ==
2166 FXP_SCB_CUS_ACTIVE && --count)
2169 device_printf(sc->dev, "command queue timeout\n");
2174 * Start the multicast setup command.
2177 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&mcsp->cb_status));
2178 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2184 static u_int32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE;
2185 static u_int32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE;
2186 static u_int32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE;
2187 static u_int32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE;
2188 static u_int32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE;
2189 static u_int32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE;
2191 #define UCODE(x) x, sizeof(x)
2197 u_short int_delay_offset;
2198 u_short bundle_max_offset;
2200 { FXP_REV_82558_A4, UCODE(fxp_ucode_d101a), D101_CPUSAVER_DWORD, 0 },
2201 { FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0), D101_CPUSAVER_DWORD, 0 },
2202 { FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma),
2203 D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD },
2204 { FXP_REV_82559S_A, UCODE(fxp_ucode_d101s),
2205 D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD },
2206 { FXP_REV_82550, UCODE(fxp_ucode_d102),
2207 D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD },
2208 { FXP_REV_82550_C, UCODE(fxp_ucode_d102c),
2209 D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD },
2210 { 0, NULL, 0, 0, 0 }
2214 fxp_load_ucode(struct fxp_softc *sc)
2217 struct fxp_cb_ucode *cbp;
2219 for (uc = ucode_table; uc->ucode != NULL; uc++)
2220 if (sc->revision == uc->revision)
2222 if (uc->ucode == NULL)
2224 cbp = (struct fxp_cb_ucode *)sc->cbl_base;
2226 cbp->cb_command = FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL;
2227 cbp->link_addr = -1; /* (no) next command */
2228 memcpy(cbp->ucode, uc->ucode, uc->length);
2229 if (uc->int_delay_offset)
2230 *(u_short *)&cbp->ucode[uc->int_delay_offset] =
2231 sc->tunable_int_delay + sc->tunable_int_delay / 2;
2232 if (uc->bundle_max_offset)
2233 *(u_short *)&cbp->ucode[uc->bundle_max_offset] =
2234 sc->tunable_bundle_max;
2236 * Download the ucode to the chip.
2239 CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, vtophys(&cbp->cb_status));
2240 fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
2241 /* ...and wait for it to complete. */
2242 fxp_dma_wait(&cbp->cb_status, sc);
2243 device_printf(sc->dev,
2244 "Microcode loaded, int_delay: %d usec bundle_max: %d\n",
2245 sc->tunable_int_delay,
2246 uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
2247 sc->flags |= FXP_FLAG_UCODE;
2251 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
2255 value = *(int *)arg1;
2256 error = sysctl_handle_int(oidp, &value, 0, req);
2257 if (error || !req->newptr)
2259 if (value < low || value > high)
2261 *(int *)arg1 = value;
2266 * Interrupt delay is expressed in microseconds, a multiplier is used
2267 * to convert this to the appropriate clock ticks before using.
2270 sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)
2272 return (sysctl_int_range(oidp, arg1, arg2, req, 300, 3000));
2276 sysctl_hw_fxp_bundle_max(SYSCTL_HANDLER_ARGS)
2278 return (sysctl_int_range(oidp, arg1, arg2, req, 1, 0xffff));