2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
32 * $FreeBSD: src/sys/pci/if_ste.c,v 1.14.2.9 2003/02/05 22:03:57 mbr Exp $
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/sockio.h>
39 #include <sys/malloc.h>
40 #include <sys/kernel.h>
41 #include <sys/socket.h>
44 #include <net/if_arp.h>
45 #include <net/ethernet.h>
46 #include <net/if_dl.h>
47 #include <net/if_media.h>
48 #include <net/if_vlan_var.h>
52 #include <vm/vm.h> /* for vtophys */
53 #include <vm/pmap.h> /* for vtophys */
54 #include <machine/clock.h> /* for DELAY */
55 #include <machine/bus_memio.h>
56 #include <machine/bus_pio.h>
57 #include <machine/bus.h>
58 #include <machine/resource.h>
62 #include <dev/mii/mii.h>
63 #include <dev/mii/miivar.h>
65 #include <pci/pcireg.h>
66 #include <pci/pcivar.h>
68 /* "controller miibus0" required. See GENERIC if you get errors here. */
69 #include "miibus_if.h"
71 #define STE_USEIOSPACE
73 #include <pci/if_stereg.h>
76 static const char rcsid[] =
77 "$FreeBSD: src/sys/pci/if_ste.c,v 1.14.2.9 2003/02/05 22:03:57 mbr Exp $";
81 * Various supported device vendors/types and their names.
83 static struct ste_type ste_devs[] = {
84 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" },
85 { DL_VENDORID, DL_DEVICEID_550TX, "D-Link DFE-550TX 10/100BaseTX" },
89 static int ste_probe __P((device_t));
90 static int ste_attach __P((device_t));
91 static int ste_detach __P((device_t));
92 static void ste_init __P((void *));
93 static void ste_intr __P((void *));
94 static void ste_rxeof __P((struct ste_softc *));
95 static void ste_txeoc __P((struct ste_softc *));
96 static void ste_txeof __P((struct ste_softc *));
97 static void ste_stats_update __P((void *));
98 static void ste_stop __P((struct ste_softc *));
99 static void ste_reset __P((struct ste_softc *));
100 static int ste_ioctl __P((struct ifnet *, u_long, caddr_t));
101 static int ste_encap __P((struct ste_softc *, struct ste_chain *,
103 static void ste_start __P((struct ifnet *));
104 static void ste_watchdog __P((struct ifnet *));
105 static void ste_shutdown __P((device_t));
106 static int ste_newbuf __P((struct ste_softc *,
107 struct ste_chain_onefrag *,
109 static int ste_ifmedia_upd __P((struct ifnet *));
110 static void ste_ifmedia_sts __P((struct ifnet *, struct ifmediareq *));
112 static void ste_mii_sync __P((struct ste_softc *));
113 static void ste_mii_send __P((struct ste_softc *, u_int32_t, int));
114 static int ste_mii_readreg __P((struct ste_softc *,
115 struct ste_mii_frame *));
116 static int ste_mii_writereg __P((struct ste_softc *,
117 struct ste_mii_frame *));
118 static int ste_miibus_readreg __P((device_t, int, int));
119 static int ste_miibus_writereg __P((device_t, int, int, int));
120 static void ste_miibus_statchg __P((device_t));
122 static int ste_eeprom_wait __P((struct ste_softc *));
123 static int ste_read_eeprom __P((struct ste_softc *, caddr_t, int,
125 static void ste_wait __P((struct ste_softc *));
126 static u_int8_t ste_calchash __P((caddr_t));
127 static void ste_setmulti __P((struct ste_softc *));
128 static int ste_init_rx_list __P((struct ste_softc *));
129 static void ste_init_tx_list __P((struct ste_softc *));
131 #ifdef STE_USEIOSPACE
132 #define STE_RES SYS_RES_IOPORT
133 #define STE_RID STE_PCI_LOIO
135 #define STE_RES SYS_RES_MEMORY
136 #define STE_RID STE_PCI_LOMEM
139 static device_method_t ste_methods[] = {
140 /* Device interface */
141 DEVMETHOD(device_probe, ste_probe),
142 DEVMETHOD(device_attach, ste_attach),
143 DEVMETHOD(device_detach, ste_detach),
144 DEVMETHOD(device_shutdown, ste_shutdown),
147 DEVMETHOD(bus_print_child, bus_generic_print_child),
148 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
151 DEVMETHOD(miibus_readreg, ste_miibus_readreg),
152 DEVMETHOD(miibus_writereg, ste_miibus_writereg),
153 DEVMETHOD(miibus_statchg, ste_miibus_statchg),
158 static driver_t ste_driver = {
161 sizeof(struct ste_softc)
164 static devclass_t ste_devclass;
166 DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0);
167 DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0);
169 #define STE_SETBIT4(sc, reg, x) \
170 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
172 #define STE_CLRBIT4(sc, reg, x) \
173 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
175 #define STE_SETBIT2(sc, reg, x) \
176 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x)
178 #define STE_CLRBIT2(sc, reg, x) \
179 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x)
181 #define STE_SETBIT1(sc, reg, x) \
182 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x)
184 #define STE_CLRBIT1(sc, reg, x) \
185 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x)
188 #define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x)
189 #define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x)
192 * Sync the PHYs by setting data bit and strobing the clock 32 times.
194 static void ste_mii_sync(sc)
195 struct ste_softc *sc;
199 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA);
201 for (i = 0; i < 32; i++) {
202 MII_SET(STE_PHYCTL_MCLK);
204 MII_CLR(STE_PHYCTL_MCLK);
212 * Clock a series of bits through the MII.
214 static void ste_mii_send(sc, bits, cnt)
215 struct ste_softc *sc;
221 MII_CLR(STE_PHYCTL_MCLK);
223 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
225 MII_SET(STE_PHYCTL_MDATA);
227 MII_CLR(STE_PHYCTL_MDATA);
230 MII_CLR(STE_PHYCTL_MCLK);
232 MII_SET(STE_PHYCTL_MCLK);
237 * Read an PHY register through the MII.
239 static int ste_mii_readreg(sc, frame)
240 struct ste_softc *sc;
241 struct ste_mii_frame *frame;
249 * Set up frame for RX.
251 frame->mii_stdelim = STE_MII_STARTDELIM;
252 frame->mii_opcode = STE_MII_READOP;
253 frame->mii_turnaround = 0;
256 CSR_WRITE_2(sc, STE_PHYCTL, 0);
260 MII_SET(STE_PHYCTL_MDIR);
265 * Send command/address info.
267 ste_mii_send(sc, frame->mii_stdelim, 2);
268 ste_mii_send(sc, frame->mii_opcode, 2);
269 ste_mii_send(sc, frame->mii_phyaddr, 5);
270 ste_mii_send(sc, frame->mii_regaddr, 5);
273 MII_CLR(STE_PHYCTL_MDIR);
276 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA));
278 MII_SET(STE_PHYCTL_MCLK);
282 MII_CLR(STE_PHYCTL_MCLK);
284 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA;
285 MII_SET(STE_PHYCTL_MCLK);
289 * Now try reading data bits. If the ack failed, we still
290 * need to clock through 16 cycles to keep the PHY(s) in sync.
293 for(i = 0; i < 16; i++) {
294 MII_CLR(STE_PHYCTL_MCLK);
296 MII_SET(STE_PHYCTL_MCLK);
302 for (i = 0x8000; i; i >>= 1) {
303 MII_CLR(STE_PHYCTL_MCLK);
306 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA)
307 frame->mii_data |= i;
310 MII_SET(STE_PHYCTL_MCLK);
316 MII_CLR(STE_PHYCTL_MCLK);
318 MII_SET(STE_PHYCTL_MCLK);
329 * Write to a PHY register through the MII.
331 static int ste_mii_writereg(sc, frame)
332 struct ste_softc *sc;
333 struct ste_mii_frame *frame;
340 * Set up frame for TX.
343 frame->mii_stdelim = STE_MII_STARTDELIM;
344 frame->mii_opcode = STE_MII_WRITEOP;
345 frame->mii_turnaround = STE_MII_TURNAROUND;
348 * Turn on data output.
350 MII_SET(STE_PHYCTL_MDIR);
354 ste_mii_send(sc, frame->mii_stdelim, 2);
355 ste_mii_send(sc, frame->mii_opcode, 2);
356 ste_mii_send(sc, frame->mii_phyaddr, 5);
357 ste_mii_send(sc, frame->mii_regaddr, 5);
358 ste_mii_send(sc, frame->mii_turnaround, 2);
359 ste_mii_send(sc, frame->mii_data, 16);
362 MII_SET(STE_PHYCTL_MCLK);
364 MII_CLR(STE_PHYCTL_MCLK);
370 MII_CLR(STE_PHYCTL_MDIR);
377 static int ste_miibus_readreg(dev, phy, reg)
381 struct ste_softc *sc;
382 struct ste_mii_frame frame;
384 sc = device_get_softc(dev);
386 if ( sc->ste_one_phy && phy != 0 )
389 bzero((char *)&frame, sizeof(frame));
391 frame.mii_phyaddr = phy;
392 frame.mii_regaddr = reg;
393 ste_mii_readreg(sc, &frame);
395 return(frame.mii_data);
398 static int ste_miibus_writereg(dev, phy, reg, data)
402 struct ste_softc *sc;
403 struct ste_mii_frame frame;
405 sc = device_get_softc(dev);
406 bzero((char *)&frame, sizeof(frame));
408 frame.mii_phyaddr = phy;
409 frame.mii_regaddr = reg;
410 frame.mii_data = data;
412 ste_mii_writereg(sc, &frame);
417 static void ste_miibus_statchg(dev)
420 struct ste_softc *sc;
421 struct mii_data *mii;
424 sc = device_get_softc(dev);
425 mii = device_get_softc(sc->ste_miibus);
427 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
428 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX);
430 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX);
433 STE_SETBIT4(sc, STE_ASICCTL,STE_ASICCTL_RX_RESET |
434 STE_ASICCTL_TX_RESET);
435 for (i = 0; i < STE_TIMEOUT; i++) {
436 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY))
439 if (i == STE_TIMEOUT)
440 printf("ste%d: rx reset never completed\n", sc->ste_unit);
445 static int ste_ifmedia_upd(ifp)
448 struct ste_softc *sc;
449 struct mii_data *mii;
452 mii = device_get_softc(sc->ste_miibus);
454 if (mii->mii_instance) {
455 struct mii_softc *miisc;
456 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
457 miisc = LIST_NEXT(miisc, mii_list))
458 mii_phy_reset(miisc);
465 static void ste_ifmedia_sts(ifp, ifmr)
467 struct ifmediareq *ifmr;
469 struct ste_softc *sc;
470 struct mii_data *mii;
473 mii = device_get_softc(sc->ste_miibus);
476 ifmr->ifm_active = mii->mii_media_active;
477 ifmr->ifm_status = mii->mii_media_status;
482 static void ste_wait(sc)
483 struct ste_softc *sc;
487 for (i = 0; i < STE_TIMEOUT; i++) {
488 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG))
492 if (i == STE_TIMEOUT)
493 printf("ste%d: command never completed!\n", sc->ste_unit);
499 * The EEPROM is slow: give it time to come ready after issuing
502 static int ste_eeprom_wait(sc)
503 struct ste_softc *sc;
509 for (i = 0; i < 100; i++) {
510 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY)
517 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit);
525 * Read a sequence of words from the EEPROM. Note that ethernet address
526 * data is stored in the EEPROM in network byte order.
528 static int ste_read_eeprom(sc, dest, off, cnt, swap)
529 struct ste_softc *sc;
536 u_int16_t word = 0, *ptr;
538 if (ste_eeprom_wait(sc))
541 for (i = 0; i < cnt; i++) {
542 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i));
543 err = ste_eeprom_wait(sc);
546 word = CSR_READ_2(sc, STE_EEPROM_DATA);
547 ptr = (u_int16_t *)(dest + (i * 2));
557 static u_int8_t ste_calchash(addr)
561 u_int32_t crc, carry;
565 /* Compute CRC for the address value. */
566 crc = 0xFFFFFFFF; /* initial value */
568 for (i = 0; i < 6; i++) {
570 for (j = 0; j < 8; j++) {
571 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
575 crc = (crc ^ 0x04c11db6) | carry;
579 /* return the filter bit position */
580 return(crc & 0x0000003F);
583 static void ste_setmulti(sc)
584 struct ste_softc *sc;
588 u_int32_t hashes[2] = { 0, 0 };
589 struct ifmultiaddr *ifma;
591 ifp = &sc->arpcom.ac_if;
592 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
593 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
594 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
598 /* first, zot all the existing hash bits */
599 CSR_WRITE_2(sc, STE_MAR0, 0);
600 CSR_WRITE_2(sc, STE_MAR1, 0);
601 CSR_WRITE_2(sc, STE_MAR2, 0);
602 CSR_WRITE_2(sc, STE_MAR3, 0);
604 /* now program new ones */
605 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL;
606 ifma = ifma->ifma_link.le_next) {
607 if (ifma->ifma_addr->sa_family != AF_LINK)
609 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
611 hashes[0] |= (1 << h);
613 hashes[1] |= (1 << (h - 32));
616 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF);
617 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF);
618 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF);
619 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF);
620 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI);
621 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH);
626 static void ste_intr(xsc)
629 struct ste_softc *sc;
634 ifp = &sc->arpcom.ac_if;
636 /* See if this is really our interrupt. */
637 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH))
641 status = CSR_READ_2(sc, STE_ISR_ACK);
643 if (!(status & STE_INTRS))
646 if (status & STE_ISR_RX_DMADONE)
649 if (status & STE_ISR_TX_DMADONE)
652 if (status & STE_ISR_TX_DONE)
655 if (status & STE_ISR_STATS_OFLOW) {
656 untimeout(ste_stats_update, sc, sc->ste_stat_ch);
657 ste_stats_update(sc);
660 if (status & STE_ISR_LINKEVENT)
661 mii_pollstat(device_get_softc(sc->ste_miibus));
663 if (status & STE_ISR_HOSTERR) {
669 /* Re-enable interrupts */
670 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
672 if (ifp->if_snd.ifq_head != NULL)
679 * A frame has been uploaded: pass the resulting mbuf chain up to
680 * the higher level protocols.
682 static void ste_rxeof(sc)
683 struct ste_softc *sc;
685 struct ether_header *eh;
688 struct ste_chain_onefrag *cur_rx;
689 int total_len = 0, count=0;
692 ifp = &sc->arpcom.ac_if;
694 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status)
695 & STE_RXSTAT_DMADONE) {
696 if ((STE_RX_LIST_CNT - count) < 3) {
700 cur_rx = sc->ste_cdata.ste_rx_head;
701 sc->ste_cdata.ste_rx_head = cur_rx->ste_next;
704 * If an error occurs, update stats, clear the
705 * status word and leave the mbuf cluster in place:
706 * it should simply get re-used next time this descriptor
707 * comes up in the ring.
709 if (rxstat & STE_RXSTAT_FRAME_ERR) {
711 cur_rx->ste_ptr->ste_status = 0;
716 * If there error bit was not set, the upload complete
717 * bit should be set which means we have a valid packet.
718 * If not, something truly strange has happened.
720 if (!(rxstat & STE_RXSTAT_DMADONE)) {
721 printf("ste%d: bad receive status -- packet dropped",
724 cur_rx->ste_ptr->ste_status = 0;
728 /* No errors; receive the packet. */
729 m = cur_rx->ste_mbuf;
730 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN;
733 * Try to conjure up a new mbuf cluster. If that
734 * fails, it means we have an out of memory condition and
735 * should leave the buffer in place and continue. This will
736 * result in a lost packet, but there's little else we
737 * can do in this situation.
739 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) {
741 cur_rx->ste_ptr->ste_status = 0;
746 eh = mtod(m, struct ether_header *);
747 m->m_pkthdr.rcvif = ifp;
748 m->m_pkthdr.len = m->m_len = total_len;
750 /* Remove header from mbuf and pass it on. */
751 m_adj(m, sizeof(struct ether_header));
752 ether_input(ifp, eh, m);
754 cur_rx->ste_ptr->ste_status = 0;
761 static void ste_txeoc(sc)
762 struct ste_softc *sc;
767 ifp = &sc->arpcom.ac_if;
769 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) &
770 STE_TXSTATUS_TXDONE) {
771 if (txstat & STE_TXSTATUS_UNDERRUN ||
772 txstat & STE_TXSTATUS_EXCESSCOLLS ||
773 txstat & STE_TXSTATUS_RECLAIMERR) {
775 printf("ste%d: transmission error: %x\n",
776 sc->ste_unit, txstat);
781 if (txstat & STE_TXSTATUS_UNDERRUN &&
782 sc->ste_tx_thresh < STE_PACKET_SIZE) {
783 sc->ste_tx_thresh += STE_MIN_FRAMELEN;
784 printf("ste%d: tx underrun, increasing tx"
785 " start threshold to %d bytes\n",
786 sc->ste_unit, sc->ste_tx_thresh);
788 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
789 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH,
790 (STE_PACKET_SIZE >> 4));
793 CSR_WRITE_2(sc, STE_TX_STATUS, txstat);
799 static void ste_txeof(sc)
800 struct ste_softc *sc;
802 struct ste_chain *cur_tx = NULL;
806 ifp = &sc->arpcom.ac_if;
808 idx = sc->ste_cdata.ste_tx_cons;
809 while(idx != sc->ste_cdata.ste_tx_prod) {
810 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
812 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE))
815 if (cur_tx->ste_mbuf != NULL) {
816 m_freem(cur_tx->ste_mbuf);
817 cur_tx->ste_mbuf = NULL;
822 sc->ste_cdata.ste_tx_cnt--;
823 STE_INC(idx, STE_TX_LIST_CNT);
827 sc->ste_cdata.ste_tx_cons = idx;
830 ifp->if_flags &= ~IFF_OACTIVE;
835 static void ste_stats_update(xsc)
838 struct ste_softc *sc;
840 struct mii_data *mii;
846 ifp = &sc->arpcom.ac_if;
847 mii = device_get_softc(sc->ste_miibus);
849 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS)
850 + CSR_READ_1(sc, STE_MULTI_COLLS)
851 + CSR_READ_1(sc, STE_SINGLE_COLLS);
855 if (mii->mii_media_status & IFM_ACTIVE &&
856 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
859 * we don't get a call-back on re-init so do it
860 * otherwise we get stuck in the wrong link state
862 ste_miibus_statchg(sc->ste_dev);
863 if (ifp->if_snd.ifq_head != NULL)
868 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz);
876 * Probe for a Sundance ST201 chip. Check the PCI vendor and device
877 * IDs against our list and return a device name if we find a match.
879 static int ste_probe(dev)
886 while(t->ste_name != NULL) {
887 if ((pci_get_vendor(dev) == t->ste_vid) &&
888 (pci_get_device(dev) == t->ste_did)) {
889 device_set_desc(dev, t->ste_name);
899 * Attach the interface. Allocate softc structures, do ifmedia
900 * setup and ethernet/BPF attach.
902 static int ste_attach(dev)
907 struct ste_softc *sc;
909 int unit, error = 0, rid;
913 sc = device_get_softc(dev);
914 unit = device_get_unit(dev);
915 bzero(sc, sizeof(struct ste_softc));
919 * Only use one PHY since this chip reports multiple
920 * Note on the DFE-550 the PHY is at 1 on the DFE-580
921 * it is at 0 & 1. It is rev 0x12.
923 if (pci_get_vendor(dev) == DL_VENDORID &&
924 pci_get_device(dev) == DL_DEVICEID_550TX &&
925 pci_get_revid(dev) == 0x12 )
929 * Handle power management nonsense.
931 command = pci_read_config(dev, STE_PCI_CAPID, 4) & 0x000000FF;
932 if (command == 0x01) {
934 command = pci_read_config(dev, STE_PCI_PWRMGMTCTRL, 4);
935 if (command & STE_PSTATE_MASK) {
936 u_int32_t iobase, membase, irq;
938 /* Save important PCI config data. */
939 iobase = pci_read_config(dev, STE_PCI_LOIO, 4);
940 membase = pci_read_config(dev, STE_PCI_LOMEM, 4);
941 irq = pci_read_config(dev, STE_PCI_INTLINE, 4);
943 /* Reset the power state. */
944 printf("ste%d: chip is in D%d power mode "
945 "-- setting to D0\n", unit, command & STE_PSTATE_MASK);
946 command &= 0xFFFFFFFC;
947 pci_write_config(dev, STE_PCI_PWRMGMTCTRL, command, 4);
949 /* Restore PCI config data. */
950 pci_write_config(dev, STE_PCI_LOIO, iobase, 4);
951 pci_write_config(dev, STE_PCI_LOMEM, membase, 4);
952 pci_write_config(dev, STE_PCI_INTLINE, irq, 4);
957 * Map control/status registers.
959 command = pci_read_config(dev, PCIR_COMMAND, 4);
960 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN);
961 pci_write_config(dev, PCIR_COMMAND, command, 4);
962 command = pci_read_config(dev, PCIR_COMMAND, 4);
964 #ifdef STE_USEIOSPACE
965 if (!(command & PCIM_CMD_PORTEN)) {
966 printf("ste%d: failed to enable I/O ports!\n", unit);
971 if (!(command & PCIM_CMD_MEMEN)) {
972 printf("ste%d: failed to enable memory mapping!\n", unit);
979 sc->ste_res = bus_alloc_resource(dev, STE_RES, &rid,
980 0, ~0, 1, RF_ACTIVE);
982 if (sc->ste_res == NULL) {
983 printf ("ste%d: couldn't map ports/memory\n", unit);
988 sc->ste_btag = rman_get_bustag(sc->ste_res);
989 sc->ste_bhandle = rman_get_bushandle(sc->ste_res);
992 sc->ste_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
993 RF_SHAREABLE | RF_ACTIVE);
995 if (sc->ste_irq == NULL) {
996 printf("ste%d: couldn't map interrupt\n", unit);
997 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1002 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET,
1003 ste_intr, sc, &sc->ste_intrhand);
1006 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1007 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1008 printf("ste%d: couldn't set up irq\n", unit);
1012 callout_handle_init(&sc->ste_stat_ch);
1014 /* Reset the adapter. */
1018 * Get station address from the EEPROM.
1020 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
1021 STE_EEADDR_NODE0, 3, 0)) {
1022 printf("ste%d: failed to read station address\n", unit);
1023 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1024 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1025 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1031 * A Sundance chip was detected. Inform the world.
1033 printf("ste%d: Ethernet address: %6D\n", unit,
1034 sc->arpcom.ac_enaddr, ":");
1036 sc->ste_unit = unit;
1038 /* Allocate the descriptor queues. */
1039 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF,
1040 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1042 if (sc->ste_ldata == NULL) {
1043 printf("ste%d: no memory for list buffers!\n", unit);
1044 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1045 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1046 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1051 bzero(sc->ste_ldata, sizeof(struct ste_list_data));
1054 if (mii_phy_probe(dev, &sc->ste_miibus,
1055 ste_ifmedia_upd, ste_ifmedia_sts)) {
1056 printf("ste%d: MII without any phy!\n", sc->ste_unit);
1057 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1058 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1059 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1060 contigfree(sc->ste_ldata,
1061 sizeof(struct ste_list_data), M_DEVBUF);
1066 ifp = &sc->arpcom.ac_if;
1068 ifp->if_unit = unit;
1069 ifp->if_name = "ste";
1070 ifp->if_mtu = ETHERMTU;
1071 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1072 ifp->if_ioctl = ste_ioctl;
1073 ifp->if_output = ether_output;
1074 ifp->if_start = ste_start;
1075 ifp->if_watchdog = ste_watchdog;
1076 ifp->if_init = ste_init;
1077 ifp->if_baudrate = 10000000;
1078 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1;
1080 sc->ste_tx_thresh = STE_TXSTART_THRESH;
1083 * Call MI attach routine.
1085 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1088 * Tell the upper layer(s) we support long frames.
1090 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1097 static int ste_detach(dev)
1100 struct ste_softc *sc;
1106 sc = device_get_softc(dev);
1107 ifp = &sc->arpcom.ac_if;
1110 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1112 bus_generic_detach(dev);
1113 device_delete_child(dev, sc->ste_miibus);
1115 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand);
1116 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq);
1117 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res);
1119 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), M_DEVBUF);
1126 static int ste_newbuf(sc, c, m)
1127 struct ste_softc *sc;
1128 struct ste_chain_onefrag *c;
1131 struct mbuf *m_new = NULL;
1134 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1137 MCLGET(m_new, M_DONTWAIT);
1138 if (!(m_new->m_flags & M_EXT)) {
1142 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1145 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1146 m_new->m_data = m_new->m_ext.ext_buf;
1149 m_adj(m_new, ETHER_ALIGN);
1151 c->ste_mbuf = m_new;
1152 c->ste_ptr->ste_status = 0;
1153 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t));
1154 c->ste_ptr->ste_frag.ste_len = (1536 + EVL_ENCAPLEN) | STE_FRAG_LAST;
1159 static int ste_init_rx_list(sc)
1160 struct ste_softc *sc;
1162 struct ste_chain_data *cd;
1163 struct ste_list_data *ld;
1166 cd = &sc->ste_cdata;
1169 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1170 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i];
1171 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS)
1173 if (i == (STE_RX_LIST_CNT - 1)) {
1174 cd->ste_rx_chain[i].ste_next =
1175 &cd->ste_rx_chain[0];
1176 ld->ste_rx_list[i].ste_next =
1177 vtophys(&ld->ste_rx_list[0]);
1179 cd->ste_rx_chain[i].ste_next =
1180 &cd->ste_rx_chain[i + 1];
1181 ld->ste_rx_list[i].ste_next =
1182 vtophys(&ld->ste_rx_list[i + 1]);
1184 ld->ste_rx_list[i].ste_status = 0;
1187 cd->ste_rx_head = &cd->ste_rx_chain[0];
1192 static void ste_init_tx_list(sc)
1193 struct ste_softc *sc;
1195 struct ste_chain_data *cd;
1196 struct ste_list_data *ld;
1199 cd = &sc->ste_cdata;
1201 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1202 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i];
1203 cd->ste_tx_chain[i].ste_ptr->ste_next = 0;
1204 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0;
1205 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]);
1206 if (i == (STE_TX_LIST_CNT - 1))
1207 cd->ste_tx_chain[i].ste_next =
1208 &cd->ste_tx_chain[0];
1210 cd->ste_tx_chain[i].ste_next =
1211 &cd->ste_tx_chain[i + 1];
1213 cd->ste_tx_chain[i].ste_prev =
1214 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1];
1216 cd->ste_tx_chain[i].ste_prev =
1217 &cd->ste_tx_chain[i - 1];
1220 cd->ste_tx_prod = 0;
1221 cd->ste_tx_cons = 0;
1227 static void ste_init(xsc)
1230 struct ste_softc *sc;
1233 struct mii_data *mii;
1238 ifp = &sc->arpcom.ac_if;
1239 mii = device_get_softc(sc->ste_miibus);
1243 /* Init our MAC address */
1244 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1245 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]);
1249 if (ste_init_rx_list(sc) == ENOBUFS) {
1250 printf("ste%d: initialization failed: no "
1251 "memory for RX buffers\n", sc->ste_unit);
1257 /* Set RX polling interval */
1258 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 1);
1260 /* Init TX descriptors */
1261 ste_init_tx_list(sc);
1263 /* Set the TX freethresh value */
1264 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8);
1266 /* Set the TX start threshold for best performance. */
1267 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh);
1269 /* Set the TX reclaim threshold. */
1270 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4));
1272 /* Set up the RX filter. */
1273 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST);
1275 /* If we want promiscuous mode, set the allframes bit. */
1276 if (ifp->if_flags & IFF_PROMISC) {
1277 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC);
1279 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC);
1282 /* Set capture broadcast bit to accept broadcast frames. */
1283 if (ifp->if_flags & IFF_BROADCAST) {
1284 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST);
1286 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST);
1291 /* Load the address of the RX list. */
1292 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
1294 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR,
1295 vtophys(&sc->ste_ldata->ste_rx_list[0]));
1296 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1297 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL);
1299 /* Set TX polling interval (defer until we TX first packet */
1300 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0);
1302 /* Load address of the TX list */
1303 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1305 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0);
1306 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1307 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1309 sc->ste_tx_prev_idx=-1;
1311 /* Enable receiver and transmitter */
1312 CSR_WRITE_2(sc, STE_MACCTL0, 0);
1313 CSR_WRITE_2(sc, STE_MACCTL1, 0);
1314 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE);
1315 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE);
1317 /* Enable stats counters. */
1318 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE);
1320 /* Enable interrupts. */
1321 CSR_WRITE_2(sc, STE_ISR, 0xFFFF);
1322 CSR_WRITE_2(sc, STE_IMR, STE_INTRS);
1324 /* Accept VLAN length packets */
1325 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + EVL_ENCAPLEN);
1327 ste_ifmedia_upd(ifp);
1329 ifp->if_flags |= IFF_RUNNING;
1330 ifp->if_flags &= ~IFF_OACTIVE;
1334 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz);
1339 static void ste_stop(sc)
1340 struct ste_softc *sc;
1345 ifp = &sc->arpcom.ac_if;
1347 untimeout(ste_stats_update, sc, sc->ste_stat_ch);
1349 CSR_WRITE_2(sc, STE_IMR, 0);
1350 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE);
1351 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE);
1352 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE);
1353 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1354 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL);
1357 * Try really hard to stop the RX engine or under heavy RX
1358 * data chip will write into de-allocated memory.
1364 for (i = 0; i < STE_RX_LIST_CNT; i++) {
1365 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) {
1366 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf);
1367 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL;
1371 for (i = 0; i < STE_TX_LIST_CNT; i++) {
1372 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) {
1373 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf);
1374 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL;
1378 bzero(sc->ste_ldata, sizeof(struct ste_list_data));
1380 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
1385 static void ste_reset(sc)
1386 struct ste_softc *sc;
1390 STE_SETBIT4(sc, STE_ASICCTL,
1391 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET|
1392 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET|
1393 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET|
1394 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET|
1395 STE_ASICCTL_EXTRESET_RESET);
1399 for (i = 0; i < STE_TIMEOUT; i++) {
1400 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY))
1404 if (i == STE_TIMEOUT)
1405 printf("ste%d: global reset never completed\n", sc->ste_unit);
1410 static int ste_ioctl(ifp, command, data)
1415 struct ste_softc *sc;
1417 struct mii_data *mii;
1423 ifr = (struct ifreq *)data;
1429 error = ether_ioctl(ifp, command, data);
1432 if (ifp->if_flags & IFF_UP) {
1433 if (ifp->if_flags & IFF_RUNNING &&
1434 ifp->if_flags & IFF_PROMISC &&
1435 !(sc->ste_if_flags & IFF_PROMISC)) {
1436 STE_SETBIT1(sc, STE_RX_MODE,
1437 STE_RXMODE_PROMISC);
1438 } else if (ifp->if_flags & IFF_RUNNING &&
1439 !(ifp->if_flags & IFF_PROMISC) &&
1440 sc->ste_if_flags & IFF_PROMISC) {
1441 STE_CLRBIT1(sc, STE_RX_MODE,
1442 STE_RXMODE_PROMISC);
1444 if (!(ifp->if_flags & IFF_RUNNING)) {
1445 sc->ste_tx_thresh = STE_TXSTART_THRESH;
1449 if (ifp->if_flags & IFF_RUNNING)
1452 sc->ste_if_flags = ifp->if_flags;
1462 mii = device_get_softc(sc->ste_miibus);
1463 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1475 static int ste_encap(sc, c, m_head)
1476 struct ste_softc *sc;
1477 struct ste_chain *c;
1478 struct mbuf *m_head;
1481 struct ste_frag *f = NULL;
1490 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1491 if (m->m_len != 0) {
1492 if (frag == STE_MAXFRAGS)
1494 total_len += m->m_len;
1495 f = &d->ste_frags[frag];
1496 f->ste_addr = vtophys(mtod(m, vm_offset_t));
1497 f->ste_len = m->m_len;
1506 * We ran out of segments. We have to recopy this
1507 * mbuf chain first. Bail out if we can't get the
1508 * new buffers. Code borrowed from if_fxp.c.
1510 MGETHDR(mn, M_DONTWAIT, MT_DATA);
1515 if (m_head->m_pkthdr.len > MHLEN) {
1516 MCLGET(mn, M_DONTWAIT);
1517 if ((mn->m_flags & M_EXT) == 0) {
1523 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1525 mn->m_pkthdr.len = mn->m_len = m_head->m_pkthdr.len;
1531 c->ste_mbuf = m_head;
1532 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST;
1538 static void ste_start(ifp)
1541 struct ste_softc *sc;
1542 struct mbuf *m_head = NULL;
1543 struct ste_chain *cur_tx = NULL;
1551 if (ifp->if_flags & IFF_OACTIVE)
1554 idx = sc->ste_cdata.ste_tx_prod;
1556 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) {
1558 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) {
1559 ifp->if_flags |= IFF_OACTIVE;
1563 IF_DEQUEUE(&ifp->if_snd, m_head);
1567 cur_tx = &sc->ste_cdata.ste_tx_chain[idx];
1569 if (ste_encap(sc, cur_tx, m_head) != 0)
1572 cur_tx->ste_ptr->ste_next = 0;
1574 if(sc->ste_tx_prev_idx < 0){
1575 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1;
1576 /* Load address of the TX list */
1577 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL);
1580 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR,
1581 vtophys(&sc->ste_ldata->ste_tx_list[0]));
1583 /* Set TX polling interval to start TX engine */
1584 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64);
1586 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL);
1589 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1;
1590 sc->ste_cdata.ste_tx_chain[
1591 sc->ste_tx_prev_idx].ste_ptr->ste_next
1595 sc->ste_tx_prev_idx=idx;
1598 * If there's a BPF listener, bounce a copy of this frame
1602 bpf_mtap(ifp, cur_tx->ste_mbuf);
1604 STE_INC(idx, STE_TX_LIST_CNT);
1605 sc->ste_cdata.ste_tx_cnt++;
1607 sc->ste_cdata.ste_tx_prod = idx;
1613 static void ste_watchdog(ifp)
1616 struct ste_softc *sc;
1621 printf("ste%d: watchdog timeout\n", sc->ste_unit);
1629 if (ifp->if_snd.ifq_head != NULL)
1635 static void ste_shutdown(dev)
1638 struct ste_softc *sc;
1640 sc = device_get_softc(dev);