2 * Copyright (c) 2000 Taku YAMAMOTO <taku@cent.saitama-u.ac.jp>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * $Id: maestro.c,v 1.12 2000/09/06 03:32:34 taku Exp $
32 * Part of this code (especially in many magic numbers) was heavily inspired
33 * by the Linux driver originally written by
34 * Alan Cox <alan.cox@linux.org>, modified heavily by
35 * Zach Brown <zab@zabbo.net>.
37 * busdma()-ize and buffer size reduction were suggested by
38 * Cameron Grant <gandalf@vilnya.demon.co.uk>.
39 * Also he showed me the way to use busdma() suite.
41 * Internal speaker problems on NEC VersaPro's and Dell Inspiron 7500
43 * Munehiro Matsuda <haro@tk.kubota.co.jp>,
44 * who brought patches based on the Linux driver with some simplification.
47 #include <dev/sound/pcm/sound.h>
48 #include <dev/sound/pcm/ac97.h>
49 #include <pci/pcireg.h>
50 #include <pci/pcivar.h>
52 #include <dev/sound/pci/maestro_reg.h>
54 SND_DECLARE_FILE("$FreeBSD: src/sys/dev/sound/pci/maestro.c,v 1.2.2.5 2002/04/22 15:49:32 cg Exp $");
56 #define inline __inline
59 * PCI IDs of supported chips:
61 * MAESTRO-1 0x01001285
62 * MAESTRO-2 0x1968125d
63 * MAESTRO-2E 0x1978125d
66 #define MAESTRO_1_PCI_ID 0x01001285
67 #define MAESTRO_2_PCI_ID 0x1968125d
68 #define MAESTRO_2E_PCI_ID 0x1978125d
70 #define NEC_SUBID1 0x80581033 /* Taken from Linux driver */
71 #define NEC_SUBID2 0x803c1033 /* NEC VersaProNX VA26D */
74 # define AGG_MAXPLAYCH 4
77 #define AGG_DEFAULT_BUFSZ 0x4000 /* 0x1000, but gets underflows */
80 /* -----------------------------
84 struct agg_info *parent;
85 struct pcm_channel *channel;
86 struct snd_dbuf *buffer;
102 bus_space_handle_t sh;
103 bus_dma_tag_t parent_dmat;
105 struct resource *irq;
112 struct ac97_info *codec;
116 u_int playchns, active;
117 struct agg_chinfo pch[AGG_MAXPLAYCH];
118 struct agg_chinfo rch;
121 static inline void ringbus_setdest(struct agg_info*, int, int);
123 static inline u_int16_t wp_rdreg(struct agg_info*, u_int16_t);
124 static inline void wp_wrreg(struct agg_info*, u_int16_t, u_int16_t);
125 static inline u_int16_t wp_rdapu(struct agg_info*, int, u_int16_t);
126 static inline void wp_wrapu(struct agg_info*, int, u_int16_t, u_int16_t);
127 static inline void wp_settimer(struct agg_info*, u_int);
128 static inline void wp_starttimer(struct agg_info*);
129 static inline void wp_stoptimer(struct agg_info*);
131 static inline u_int16_t wc_rdreg(struct agg_info*, u_int16_t);
132 static inline void wc_wrreg(struct agg_info*, u_int16_t, u_int16_t);
133 static inline u_int16_t wc_rdchctl(struct agg_info*, int);
134 static inline void wc_wrchctl(struct agg_info*, int, u_int16_t);
136 static inline void agg_power(struct agg_info*, int);
138 static void agg_init(struct agg_info*);
140 static void aggch_start_dac(struct agg_chinfo*);
141 static void aggch_stop_dac(struct agg_chinfo*);
143 static inline void suppress_jitter(struct agg_chinfo*);
145 static inline u_int calc_timer_freq(struct agg_chinfo*);
146 static void set_timer(struct agg_info*);
148 static void agg_intr(void *);
149 static int agg_probe(device_t);
150 static int agg_attach(device_t);
151 static int agg_detach(device_t);
152 static int agg_suspend(device_t);
153 static int agg_resume(device_t);
154 static int agg_shutdown(device_t);
156 static void *dma_malloc(struct agg_info*, u_int32_t, bus_addr_t*);
157 static void dma_free(struct agg_info*, void *);
159 /* -----------------------------
165 /* -------------------------------------------------------------------- */
168 agg_ac97_init(kobj_t obj, void *sc)
170 struct agg_info *ess = sc;
172 return (bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT) & CODEC_STAT_MASK)? 0 : 1;
176 agg_rdcodec(kobj_t obj, void *sc, int regno)
178 struct agg_info *ess = sc;
181 /* We have to wait for a SAFE time to write addr/data */
182 for (t = 0; t < 20; t++) {
183 if ((bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT)
184 & CODEC_STAT_MASK) != CODEC_STAT_PROGLESS)
186 DELAY(2); /* 20.8us / 13 */
189 device_printf(ess->dev, "agg_rdcodec() PROGLESS timed out.\n");
191 bus_space_write_1(ess->st, ess->sh, PORT_CODEC_CMD,
192 CODEC_CMD_READ | regno);
193 DELAY(21); /* AC97 cycle = 20.8usec */
195 /* Wait for data retrieve */
196 for (t = 0; t < 20; t++) {
197 if ((bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT)
198 & CODEC_STAT_MASK) == CODEC_STAT_RW_DONE)
200 DELAY(2); /* 20.8us / 13 */
203 /* Timed out, but perform dummy read. */
204 device_printf(ess->dev, "agg_rdcodec() RW_DONE timed out.\n");
206 return bus_space_read_2(ess->st, ess->sh, PORT_CODEC_REG);
210 agg_wrcodec(kobj_t obj, void *sc, int regno, u_int32_t data)
213 struct agg_info *ess = sc;
215 /* We have to wait for a SAFE time to write addr/data */
216 for (t = 0; t < 20; t++) {
217 if ((bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT)
218 & CODEC_STAT_MASK) != CODEC_STAT_PROGLESS)
220 DELAY(2); /* 20.8us / 13 */
223 /* Timed out. Abort writing. */
224 device_printf(ess->dev, "agg_wrcodec() PROGLESS timed out.\n");
228 bus_space_write_2(ess->st, ess->sh, PORT_CODEC_REG, data);
229 bus_space_write_1(ess->st, ess->sh, PORT_CODEC_CMD,
230 CODEC_CMD_WRITE | regno);
235 static kobj_method_t agg_ac97_methods[] = {
236 KOBJMETHOD(ac97_init, agg_ac97_init),
237 KOBJMETHOD(ac97_read, agg_rdcodec),
238 KOBJMETHOD(ac97_write, agg_wrcodec),
241 AC97_DECLARE(agg_ac97);
243 /* -------------------------------------------------------------------- */
246 ringbus_setdest(struct agg_info *ess, int src, int dest)
250 data = bus_space_read_4(ess->st, ess->sh, PORT_RINGBUS_CTRL);
251 data &= ~(0xfU << src);
252 data |= (0xfU & dest) << src;
253 bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, data);
258 static inline u_int16_t
259 wp_rdreg(struct agg_info *ess, u_int16_t reg)
261 bus_space_write_2(ess->st, ess->sh, PORT_DSP_INDEX, reg);
262 return bus_space_read_2(ess->st, ess->sh, PORT_DSP_DATA);
266 wp_wrreg(struct agg_info *ess, u_int16_t reg, u_int16_t data)
268 bus_space_write_2(ess->st, ess->sh, PORT_DSP_INDEX, reg);
269 bus_space_write_2(ess->st, ess->sh, PORT_DSP_DATA, data);
273 apu_setindex(struct agg_info *ess, u_int16_t reg)
277 wp_wrreg(ess, WPREG_CRAM_PTR, reg);
278 /* Sometimes WP fails to set apu register index. */
279 for (t = 0; t < 1000; t++) {
280 if (bus_space_read_2(ess->st, ess->sh, PORT_DSP_DATA) == reg)
282 bus_space_write_2(ess->st, ess->sh, PORT_DSP_DATA, reg);
285 device_printf(ess->dev, "apu_setindex() timed out.\n");
288 static inline u_int16_t
289 wp_rdapu(struct agg_info *ess, int ch, u_int16_t reg)
293 apu_setindex(ess, ((unsigned)ch << 4) + reg);
294 ret = wp_rdreg(ess, WPREG_DATA_PORT);
299 wp_wrapu(struct agg_info *ess, int ch, u_int16_t reg, u_int16_t data)
303 apu_setindex(ess, ((unsigned)ch << 4) + reg);
304 wp_wrreg(ess, WPREG_DATA_PORT, data);
305 for (t = 0; t < 1000; t++) {
306 if (bus_space_read_2(ess->st, ess->sh, PORT_DSP_DATA) == data)
308 bus_space_write_2(ess->st, ess->sh, PORT_DSP_DATA, data);
311 device_printf(ess->dev, "wp_wrapu() timed out.\n");
315 wp_settimer(struct agg_info *ess, u_int freq)
317 u_int clock = 48000 << 2;
318 u_int prescale = 0, divide = (freq != 0) ? (clock / freq) : ~0;
320 RANGE(divide, 4, 32 << 8);
322 for (; divide > 32 << 1; divide >>= 1)
324 divide = (divide + 1) >> 1;
326 for (; prescale < 7 && divide > 2 && !(divide & 1); divide >>= 1)
329 wp_wrreg(ess, WPREG_TIMER_ENABLE, 0);
330 wp_wrreg(ess, WPREG_TIMER_FREQ,
331 (prescale << WP_TIMER_FREQ_PRESCALE_SHIFT) | (divide - 1));
332 wp_wrreg(ess, WPREG_TIMER_ENABLE, 1);
336 wp_starttimer(struct agg_info *ess)
338 wp_wrreg(ess, WPREG_TIMER_START, 1);
342 wp_stoptimer(struct agg_info *ess)
344 wp_wrreg(ess, WPREG_TIMER_START, 0);
345 bus_space_write_2(ess->st, ess->sh, PORT_INT_STAT, 1);
350 static inline u_int16_t
351 wc_rdreg(struct agg_info *ess, u_int16_t reg)
353 bus_space_write_2(ess->st, ess->sh, PORT_WAVCACHE_INDEX, reg);
354 return bus_space_read_2(ess->st, ess->sh, PORT_WAVCACHE_DATA);
358 wc_wrreg(struct agg_info *ess, u_int16_t reg, u_int16_t data)
360 bus_space_write_2(ess->st, ess->sh, PORT_WAVCACHE_INDEX, reg);
361 bus_space_write_2(ess->st, ess->sh, PORT_WAVCACHE_DATA, data);
364 static inline u_int16_t
365 wc_rdchctl(struct agg_info *ess, int ch)
367 return wc_rdreg(ess, ch << 3);
371 wc_wrchctl(struct agg_info *ess, int ch, u_int16_t data)
373 wc_wrreg(ess, ch << 3, data);
376 /* Power management */
379 agg_power(struct agg_info *ess, int status)
383 data = pci_read_config(ess->dev, CONF_PM_PTR, 1);
384 if (pci_read_config(ess->dev, data, 1) == PPMI_CID)
385 pci_write_config(ess->dev, data + PM_CTRL, status, 1);
389 /* -----------------------------
394 agg_initcodec(struct agg_info* ess)
398 if (bus_space_read_4(ess->st, ess->sh, PORT_RINGBUS_CTRL)
399 & RINGBUS_CTRL_ACLINK_ENABLED) {
400 bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, 0);
401 DELAY(104); /* 20.8us * (4 + 1) */
403 /* XXX - 2nd codec should be looked at. */
404 bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL,
405 RINGBUS_CTRL_AC97_SWRESET);
407 bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL,
408 RINGBUS_CTRL_ACLINK_ENABLED);
411 agg_rdcodec(NULL, ess, 0);
412 if (bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT)
414 bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, 0);
417 /* Try cold reset. */
418 device_printf(ess->dev, "will perform cold reset.\n");
419 data = bus_space_read_2(ess->st, ess->sh, PORT_GPIO_DIR);
420 if (pci_read_config(ess->dev, 0x58, 2) & 1)
423 ~bus_space_read_2(ess->st, ess->sh, PORT_GPIO_DATA);
424 bus_space_write_2(ess->st, ess->sh, PORT_GPIO_MASK, 0xff6);
425 bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DIR,
427 bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA, 0x000);
429 bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA, 0x001);
431 bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA, 0x009);
433 bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DIR, data);
434 DELAY(84); /* 20.8us * 4 */
435 bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL,
436 RINGBUS_CTRL_ACLINK_ENABLED);
442 agg_init(struct agg_info* ess)
446 /* Setup PCI config registers. */
448 /* Disable all legacy emulations. */
449 data = pci_read_config(ess->dev, CONF_LEGACY, 2);
450 data |= LEGACY_DISABLED;
451 pci_write_config(ess->dev, CONF_LEGACY, data, 2);
453 /* Disconnect from CHI. (Makes Dell inspiron 7500 work?)
454 * Enable posted write.
455 * Prefer PCI timing rather than that of ISA.
457 data = pci_read_config(ess->dev, CONF_MAESTRO, 4);
458 data |= MAESTRO_CHIBUS | MAESTRO_POSTEDWRITE | MAESTRO_DMA_PCITIMING;
459 data &= ~MAESTRO_SWAP_LR;
460 pci_write_config(ess->dev, CONF_MAESTRO, data, 4);
462 /* Reset direct sound. */
463 bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL,
464 HOSTINT_CTRL_DSOUND_RESET);
465 DELAY(10000); /* XXX - too long? */
466 bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL, 0);
469 /* Enable direct sound interruption and hardware volume control. */
470 bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL,
471 HOSTINT_CTRL_DSOUND_INT_ENABLED | HOSTINT_CTRL_HWVOL_ENABLED);
473 /* Setup Wave Processor. */
475 /* Enable WaveCache, set DMA base address. */
476 wp_wrreg(ess, WPREG_WAVE_ROMRAM,
477 WP_WAVE_VIRTUAL_ENABLED | WP_WAVE_DRAM_ENABLED);
478 bus_space_write_2(ess->st, ess->sh, PORT_WAVCACHE_CTRL,
479 WAVCACHE_ENABLED | WAVCACHE_WTSIZE_4MB);
481 for (data = WAVCACHE_PCMBAR; data < WAVCACHE_PCMBAR + 4; data++)
482 wc_wrreg(ess, data, ess->baseaddr >> WAVCACHE_BASEADDR_SHIFT);
484 /* Setup Codec/Ringbus. */
486 bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL,
487 RINGBUS_CTRL_RINGBUS_ENABLED | RINGBUS_CTRL_ACLINK_ENABLED);
489 wp_wrreg(ess, WPREG_BASE, 0x8500); /* Parallel I/O */
490 ringbus_setdest(ess, RINGBUS_SRC_ADC,
491 RINGBUS_DEST_STEREO | RINGBUS_DEST_DSOUND_IN);
492 ringbus_setdest(ess, RINGBUS_SRC_DSOUND,
493 RINGBUS_DEST_STEREO | RINGBUS_DEST_DAC);
495 /* Setup ASSP. Needed for Dell Inspiron 7500? */
496 bus_space_write_1(ess->st, ess->sh, PORT_ASSP_CTRL_B, 0x00);
497 bus_space_write_1(ess->st, ess->sh, PORT_ASSP_CTRL_A, 0x03);
498 bus_space_write_1(ess->st, ess->sh, PORT_ASSP_CTRL_C, 0x00);
502 * There seems to be speciality with NEC systems.
504 switch (pci_get_subvendor(ess->dev)
505 | (pci_get_subdevice(ess->dev) << 16)) {
508 /* Matthew Braithwaite <matt@braithwaite.net> reported that
509 * NEC Versa LX doesn't need GPIO operation. */
510 bus_space_write_2(ess->st, ess->sh, PORT_GPIO_MASK, 0x9ff);
511 bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DIR,
512 bus_space_read_2(ess->st, ess->sh, PORT_GPIO_DIR) | 0x600);
513 bus_space_write_2(ess->st, ess->sh, PORT_GPIO_DATA, 0x200);
518 /* Channel controller. */
521 aggch_start_dac(struct agg_chinfo *ch)
523 bus_addr_t wpwa = APU_USE_SYSMEM | (ch->offset >> 9);
524 u_int size = ch->parent->bufsz >> 1;
525 u_int speed = ch->speed;
526 bus_addr_t offset = ch->offset >> 1;
528 u_int16_t apuch = ch->num << 1;
532 switch (ch->aputype) {
533 case APUTYPE_16BITSTEREO:
539 case APUTYPE_8BITSTEREO:
543 case APUTYPE_8BITLINEAR:
548 dv = (((speed % 48000) << 16) + 24000) / 48000
549 + ((speed / 48000) << 16);
552 wp_wrapu(ch->parent, apuch, APUREG_WAVESPACE, wpwa & 0xff00);
553 wp_wrapu(ch->parent, apuch, APUREG_CURPTR, offset + cp);
554 wp_wrapu(ch->parent, apuch, APUREG_ENDPTR, offset + size);
555 wp_wrapu(ch->parent, apuch, APUREG_LOOPLEN, size);
556 wp_wrapu(ch->parent, apuch, APUREG_AMPLITUDE, 0xe800);
557 wp_wrapu(ch->parent, apuch, APUREG_POSITION, 0x8f00
558 | (RADIUS_CENTERCIRCLE << APU_RADIUS_SHIFT)
559 | ((PAN_FRONT + pan) << APU_PAN_SHIFT));
560 wp_wrapu(ch->parent, apuch, APUREG_FREQ_LOBYTE, APU_plus6dB
561 | ((dv & 0xff) << APU_FREQ_LOBYTE_SHIFT));
562 wp_wrapu(ch->parent, apuch, APUREG_FREQ_HIWORD, dv >> 8);
564 if (ch->aputype == APUTYPE_16BITSTEREO)
565 wpwa |= APU_STEREO >> 1;
567 } while (pan < 0 && apuch--);
569 wc_wrchctl(ch->parent, apuch, ch->wcreg_tpl);
570 wc_wrchctl(ch->parent, apuch + 1, ch->wcreg_tpl);
572 wp_wrapu(ch->parent, apuch, APUREG_APUTYPE,
573 (ch->aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
574 if (ch->wcreg_tpl & WAVCACHE_CHCTL_STEREO)
575 wp_wrapu(ch->parent, apuch + 1, APUREG_APUTYPE,
576 (ch->aputype << APU_APUTYPE_SHIFT) | APU_DMA_ENABLED | 0xf);
580 aggch_stop_dac(struct agg_chinfo *ch)
582 wp_wrapu(ch->parent, (ch->num << 1), APUREG_APUTYPE,
583 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
584 wp_wrapu(ch->parent, (ch->num << 1) + 1, APUREG_APUTYPE,
585 APUTYPE_INACTIVE << APU_APUTYPE_SHIFT);
589 * Stereo jitter suppressor.
590 * Sometimes playback pointers differ in stereo-paired channels.
591 * Calling this routine within intr fixes the problem.
594 suppress_jitter(struct agg_chinfo *ch)
596 if (ch->wcreg_tpl & WAVCACHE_CHCTL_STEREO) {
597 int cp, diff, halfsize = ch->parent->bufsz >> 2;
599 if (ch->aputype == APUTYPE_16BITSTEREO)
601 cp = wp_rdapu(ch->parent, (ch->num << 1), APUREG_CURPTR);
602 diff = wp_rdapu(ch->parent, (ch->num << 1) + 1, APUREG_CURPTR);
604 if (diff >> 1 && diff > -halfsize && diff < halfsize)
605 bus_space_write_2(ch->parent->st, ch->parent->sh,
611 calc_timer_freq(struct agg_chinfo *ch)
615 if (ch->aputype == APUTYPE_16BITSTEREO)
617 if (ch->aputype == APUTYPE_8BITLINEAR)
620 return (ch->speed * ss) / ch->blocksize;
624 set_timer(struct agg_info *ess)
629 for (i = 0; i < ess->playchns; i++)
630 if ((ess->active & (1 << i)) &&
631 (freq < calc_timer_freq(ess->pch + i)))
632 freq = calc_timer_freq(ess->pch + i);
634 wp_settimer(ess, freq);
638 /* -----------------------------
643 aggch_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
645 struct agg_info *ess = devinfo;
646 struct agg_chinfo *ch;
650 ch = (dir == PCMDIR_PLAY)? ess->pch + ess->playchns : &ess->rch;
655 ch->num = ess->playchns;
658 p = dma_malloc(ess, ess->bufsz, &physaddr);
661 sndbuf_setup(b, p, ess->bufsz);
663 ch->offset = physaddr - ess->baseaddr;
664 if (physaddr < ess->baseaddr || ch->offset > WPWA_MAXADDR) {
665 device_printf(ess->dev,
666 "offset %#llx exceeds limit. ", (long long)ch->offset);
667 dma_free(ess, sndbuf_getbuf(b));
671 ch->wcreg_tpl = (physaddr - 16) & WAVCACHE_CHCTL_ADDRTAG_MASK;
673 if (dir == PCMDIR_PLAY) {
676 device_printf(ess->dev, "pch[%d].offset = %#llx\n", ch->num, (long long)ch->offset);
677 } else if (bootverbose)
678 device_printf(ess->dev, "rch.offset = %#llx\n", (long long)ch->offset);
684 aggch_free(kobj_t obj, void *data)
686 struct agg_chinfo *ch = data;
687 struct agg_info *ess = ch->parent;
689 /* free up buffer - called after channel stopped */
690 dma_free(ess, sndbuf_getbuf(ch->buffer));
697 aggch_setplayformat(kobj_t obj, void *data, u_int32_t format)
699 struct agg_chinfo *ch = data;
701 u_int16_t aputype = APUTYPE_16BITLINEAR;
703 wcreg_tpl = ch->wcreg_tpl & WAVCACHE_CHCTL_ADDRTAG_MASK;
705 if (format & AFMT_STEREO) {
706 wcreg_tpl |= WAVCACHE_CHCTL_STEREO;
709 if (format & AFMT_U8 || format & AFMT_S8) {
711 if (format & AFMT_U8)
712 wcreg_tpl |= WAVCACHE_CHCTL_U8;
714 if (format & AFMT_BIGENDIAN || format & AFMT_U16_LE) {
715 format &= ~AFMT_BIGENDIAN & ~AFMT_U16_LE;
716 format |= AFMT_S16_LE;
718 ch->wcreg_tpl = wcreg_tpl;
719 ch->aputype = aputype;
724 aggch_setspeed(kobj_t obj, void *data, u_int32_t speed)
726 struct agg_chinfo *ch = data;
733 aggch_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
735 return ((struct agg_chinfo*)data)->blocksize = blocksize;
739 aggch_trigger(kobj_t obj, void *data, int go)
741 struct agg_chinfo *ch = data;
744 case PCMTRIG_EMLDMAWR:
747 ch->parent->active |= (1 << ch->num);
748 if (ch->dir == PCMDIR_PLAY)
750 #if 0 /* XXX - RECORDING */
757 ch->parent->active &= ~(1 << ch->num);
758 if (ch->dir == PCMDIR_PLAY)
760 #if 0 /* XXX - RECORDING */
767 if (ch->parent->active) {
768 set_timer(ch->parent);
769 wp_starttimer(ch->parent);
771 wp_stoptimer(ch->parent);
777 aggch_getplayptr(kobj_t obj, void *data)
779 struct agg_chinfo *ch = data;
782 cp = wp_rdapu(ch->parent, (ch->num << 1), APUREG_CURPTR);
783 if (ch->aputype == APUTYPE_16BITSTEREO)
784 cp = (0xffff << 2) & ((cp << 2) - ch->offset);
786 cp = (0xffff << 1) & ((cp << 1) - ch->offset);
791 static struct pcmchan_caps *
792 aggch_getcaps(kobj_t obj, void *data)
794 static u_int32_t playfmt[] = {
796 AFMT_STEREO | AFMT_U8,
798 AFMT_STEREO | AFMT_S8,
800 AFMT_STEREO | AFMT_S16_LE,
803 static struct pcmchan_caps playcaps = {2000, 96000, playfmt, 0};
805 static u_int32_t recfmt[] = {
807 AFMT_STEREO | AFMT_S8,
809 AFMT_STEREO | AFMT_S16_LE,
812 static struct pcmchan_caps reccaps = {4000, 48000, recfmt, 0};
814 return (((struct agg_chinfo*)data)->dir == PCMDIR_PLAY)?
815 &playcaps : &reccaps;
818 static kobj_method_t aggch_methods[] = {
819 KOBJMETHOD(channel_init, aggch_init),
820 KOBJMETHOD(channel_free, aggch_free),
821 KOBJMETHOD(channel_setformat, aggch_setplayformat),
822 KOBJMETHOD(channel_setspeed, aggch_setspeed),
823 KOBJMETHOD(channel_setblocksize, aggch_setblocksize),
824 KOBJMETHOD(channel_trigger, aggch_trigger),
825 KOBJMETHOD(channel_getptr, aggch_getplayptr),
826 KOBJMETHOD(channel_getcaps, aggch_getcaps),
829 CHANNEL_DECLARE(aggch);
831 /* -----------------------------
838 struct agg_info* ess = sc;
842 status = bus_space_read_1(ess->st, ess->sh, PORT_HOSTINT_STAT);
846 /* Acknowledge all. */
847 bus_space_write_2(ess->st, ess->sh, PORT_INT_STAT, 1);
848 bus_space_write_1(ess->st, ess->sh, PORT_HOSTINT_STAT, 0xff);
850 if (status & HOSTINT_STAT_HWVOL) {
853 event = bus_space_read_1(ess->st, ess->sh, PORT_HWVOL_MASTER);
856 mixer_hwvol_mute(ess->dev);
859 mixer_hwvol_step(ess->dev, 1, 1);
862 mixer_hwvol_step(ess->dev, -1, -1);
867 device_printf(ess->dev, "%s: unknown HWVOL event 0x%x\n",
868 device_get_nameunit(ess->dev), event);
870 bus_space_write_1(ess->st, ess->sh, PORT_HWVOL_MASTER,
874 for (i = 0; i < ess->playchns; i++)
875 if (ess->active & (1 << i)) {
876 suppress_jitter(ess->pch + i);
877 chn_intr(ess->pch[i].channel);
879 #if 0 /* XXX - RECORDING */
880 if (ess->active & (1 << i))
881 chn_intr(ess->rch.channel);
886 setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error)
888 bus_addr_t *phys = arg;
890 *phys = error? 0 : segs->ds_addr;
893 printf("setmap (%lx, %lx), nseg=%d, error=%d\n",
894 (unsigned long)segs->ds_addr, (unsigned long)segs->ds_len,
900 dma_malloc(struct agg_info *sc, u_int32_t sz, bus_addr_t *phys)
905 if (bus_dmamem_alloc(sc->parent_dmat, &buf, BUS_DMA_NOWAIT, &map))
907 if (bus_dmamap_load(sc->parent_dmat, map, buf, sz, setmap, phys, 0)
909 bus_dmamem_free(sc->parent_dmat, buf, map);
916 dma_free(struct agg_info *sc, void *buf)
918 bus_dmamem_free(sc->parent_dmat, buf, NULL);
922 agg_probe(device_t dev)
926 switch (pci_get_devid(dev)) {
927 case MAESTRO_1_PCI_ID:
928 s = "ESS Technology Maestro-1";
931 case MAESTRO_2_PCI_ID:
932 s = "ESS Technology Maestro-2";
935 case MAESTRO_2E_PCI_ID:
936 s = "ESS Technology Maestro-2E";
940 if (s != NULL && pci_get_class(dev) == PCIC_MULTIMEDIA) {
941 device_set_desc(dev, s);
948 agg_attach(device_t dev)
950 struct agg_info *ess = NULL;
953 int regid = PCIR_MAPS;
954 struct resource *reg = NULL;
955 struct ac97_info *codec = NULL;
957 struct resource *irq = NULL;
959 char status[SND_STATUSLEN];
961 if ((ess = malloc(sizeof *ess, M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) {
962 device_printf(dev, "cannot allocate softc\n");
967 ess->bufsz = pcm_getbuffersize(dev, 4096, AGG_DEFAULT_BUFSZ, 65536);
969 if (bus_dma_tag_create(/*parent*/NULL,
970 /*alignment*/1 << WAVCACHE_BASEADDR_SHIFT,
971 /*boundary*/WPWA_MAXADDR + 1,
972 /*lowaddr*/MAESTRO_MAXADDR, /*highaddr*/BUS_SPACE_MAXADDR,
973 /*filter*/NULL, /*filterarg*/NULL,
974 /*maxsize*/ess->bufsz, /*nsegments*/1, /*maxsegz*/0x3ffff,
975 /*flags*/0, &ess->parent_dmat) != 0) {
976 device_printf(dev, "unable to create dma tag\n");
980 ess->stat = dma_malloc(ess, ess->bufsz, &ess->baseaddr);
981 if (ess->stat == NULL) {
982 device_printf(dev, "cannot allocate status buffer\n");
986 device_printf(dev, "Maestro DMA base: %#llx\n",
987 (long long)ess->baseaddr);
989 agg_power(ess, PPMI_D0);
992 data = pci_read_config(dev, PCIR_COMMAND, 2);
993 data |= (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN);
994 pci_write_config(dev, PCIR_COMMAND, data, 2);
995 data = pci_read_config(dev, PCIR_COMMAND, 2);
997 if (data & PCIM_CMD_PORTEN) {
998 reg = bus_alloc_resource(dev, SYS_RES_IOPORT, ®id,
999 0, BUS_SPACE_UNRESTRICTED, 256, RF_ACTIVE);
1003 ess->st = rman_get_bustag(reg);
1004 ess->sh = rman_get_bushandle(reg);
1009 device_printf(dev, "unable to map register space\n");
1014 if (agg_rdcodec(NULL, ess, 0) == 0x80) {
1015 device_printf(dev, "PT101 codec detected!\n");
1018 codec = AC97_CREATE(dev, ess, agg_ac97);
1021 if (mixer_init(dev, ac97_getmixerclass(), codec) == -1)
1025 irq = bus_alloc_resource(dev, SYS_RES_IRQ, &irqid,
1026 0, BUS_SPACE_UNRESTRICTED, 1, RF_ACTIVE | RF_SHAREABLE);
1027 if (irq == NULL || snd_setup_intr(dev, irq, 0, agg_intr, ess, &ih)) {
1028 device_printf(dev, "unable to map interrupt\n");
1035 snprintf(status, SND_STATUSLEN, "at I/O port 0x%lx irq %ld",
1036 rman_get_start(reg), rman_get_start(irq));
1038 if (pcm_register(dev, ess, AGG_MAXPLAYCH, 1))
1041 mixer_hwvol_init(dev);
1042 for (data = 0; data < AGG_MAXPLAYCH; data++)
1043 pcm_addchan(dev, PCMDIR_PLAY, &aggch_class, ess);
1044 #if 0 /* XXX - RECORDING */
1045 pcm_addchan(dev, PCMDIR_REC, &aggrch_class, ess);
1047 pcm_setstatus(dev, status);
1053 ac97_destroy(codec);
1055 bus_teardown_intr(dev, irq, ih);
1057 bus_release_resource(dev, SYS_RES_IRQ, irqid, irq);
1059 bus_release_resource(dev, SYS_RES_IOPORT, regid, reg);
1061 agg_power(ess, PPMI_D3);
1062 if (ess->stat != NULL)
1063 dma_free(ess, ess->stat);
1064 if (ess->parent_dmat != NULL)
1065 bus_dma_tag_destroy(ess->parent_dmat);
1066 free(ess, M_DEVBUF);
1073 agg_detach(device_t dev)
1075 struct agg_info *ess = pcm_getdevinfo(dev);
1078 r = pcm_unregister(dev);
1082 ess = pcm_getdevinfo(dev);
1083 dma_free(ess, ess->stat);
1085 /* Power down everything except clock and vref. */
1086 agg_wrcodec(NULL, ess, AC97_REG_POWER, 0xd700);
1088 bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, 0);
1089 agg_power(ess, PPMI_D3);
1091 bus_teardown_intr(dev, ess->irq, ess->ih);
1092 bus_release_resource(dev, SYS_RES_IRQ, ess->irqid, ess->irq);
1093 bus_release_resource(dev, SYS_RES_IOPORT, ess->regid, ess->reg);
1094 bus_dma_tag_destroy(ess->parent_dmat);
1095 free(ess, M_DEVBUF);
1100 agg_suspend(device_t dev)
1102 struct agg_info *ess = pcm_getdevinfo(dev);
1107 bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL, 0);
1109 for (i = 0; i < ess->playchns; i++)
1110 aggch_stop_dac(ess->pch + i);
1112 #if 0 /* XXX - RECORDING */
1113 aggch_stop_adc(&ess->rch);
1116 /* Power down everything except clock. */
1117 agg_wrcodec(NULL, ess, AC97_REG_POWER, 0xdf00);
1119 bus_space_write_4(ess->st, ess->sh, PORT_RINGBUS_CTRL, 0);
1121 agg_power(ess, PPMI_D3);
1127 agg_resume(device_t dev)
1130 struct agg_info *ess = pcm_getdevinfo(dev);
1132 agg_power(ess, PPMI_D0);
1135 if (mixer_reinit(dev)) {
1136 device_printf(dev, "unable to reinitialize the mixer\n");
1141 for (i = 0; i < ess->playchns; i++)
1142 if (ess->active & (1 << i))
1143 aggch_start_dac(ess->pch + i);
1144 #if 0 /* XXX - RECORDING */
1145 if (ess->active & (1 << i))
1146 aggch_start_adc(&ess->rch);
1157 agg_shutdown(device_t dev)
1159 struct agg_info *ess = pcm_getdevinfo(dev);
1163 bus_space_write_2(ess->st, ess->sh, PORT_HOSTINT_CTRL, 0);
1165 for (i = 0; i < ess->playchns; i++)
1166 aggch_stop_dac(ess->pch + i);
1168 #if 0 /* XXX - RECORDING */
1169 aggch_stop_adc(&ess->rch);
1175 static device_method_t agg_methods[] = {
1176 DEVMETHOD(device_probe, agg_probe),
1177 DEVMETHOD(device_attach, agg_attach),
1178 DEVMETHOD(device_detach, agg_detach),
1179 DEVMETHOD(device_suspend, agg_suspend),
1180 DEVMETHOD(device_resume, agg_resume),
1181 DEVMETHOD(device_shutdown, agg_shutdown),
1186 static driver_t agg_driver = {
1192 DRIVER_MODULE(snd_maestro, pci, agg_driver, pcm_devclass, 0, 0);
1193 MODULE_DEPEND(snd_maestro, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER);
1194 MODULE_VERSION(snd_maestro, 1);