1 /******************************************************************************
3 Copyright (c) 2001-2011, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
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16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
36 * 82575EB Gigabit Network Connection
37 * 82575EB Gigabit Backplane Connection
38 * 82575GB Gigabit Network Connection
39 * 82576 Gigabit Network Connection
40 * 82576 Quad Port Gigabit Mezzanine Adapter
41 * 82580 Gigabit Network Connection
42 * I350 Gigabit Network Connection
45 #include "e1000_api.h"
46 #include "e1000_i210.h"
48 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw);
49 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw);
50 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw);
51 static void e1000_release_phy_82575(struct e1000_hw *hw);
52 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);
53 static void e1000_release_nvm_82575(struct e1000_hw *hw);
54 static s32 e1000_check_for_link_82575(struct e1000_hw *hw);
55 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw);
56 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
58 static s32 e1000_init_hw_82575(struct e1000_hw *hw);
59 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
60 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
62 static s32 e1000_reset_hw_82575(struct e1000_hw *hw);
63 static s32 e1000_reset_hw_82580(struct e1000_hw *hw);
64 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw,
65 u32 offset, u16 *data);
66 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw,
67 u32 offset, u16 data);
68 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
70 static s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
72 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
74 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
75 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw);
76 static s32 e1000_get_media_type_82575(struct e1000_hw *hw);
77 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
78 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
79 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
80 u32 offset, u16 data);
81 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
82 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
83 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
84 u16 *speed, u16 *duplex);
85 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
86 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
87 static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
88 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw);
89 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
90 static void e1000_config_collision_dist_82575(struct e1000_hw *hw);
91 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
92 static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
93 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
94 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
95 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
96 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
97 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
98 static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
100 static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
102 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
103 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
104 static void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value);
105 static void e1000_clear_vfta_i350(struct e1000_hw *hw);
107 static void e1000_i2c_start(struct e1000_hw *hw);
108 static void e1000_i2c_stop(struct e1000_hw *hw);
109 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
110 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
111 static s32 e1000_get_i2c_ack(struct e1000_hw *hw);
112 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
113 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
114 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
115 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
116 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
117 static bool e1000_get_i2c_data(u32 *i2cctl);
119 static const u16 e1000_82580_rxpbs_table[] = {
120 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
121 #define E1000_82580_RXPBS_TABLE_SIZE \
122 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
126 * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
127 * @hw: pointer to the HW structure
129 * Called to determine if the I2C pins are being used for I2C or as an
130 * external MDIO interface since the two options are mutually exclusive.
132 static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
135 bool ext_mdio = FALSE;
137 DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
139 switch (hw->mac.type) {
142 reg = E1000_READ_REG(hw, E1000_MDIC);
143 ext_mdio = !!(reg & E1000_MDIC_DEST);
147 reg = E1000_READ_REG(hw, E1000_MDICNFG);
148 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
157 * e1000_init_phy_params_82575 - Init PHY func ptrs.
158 * @hw: pointer to the HW structure
160 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
162 struct e1000_phy_info *phy = &hw->phy;
163 s32 ret_val = E1000_SUCCESS;
166 DEBUGFUNC("e1000_init_phy_params_82575");
168 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
169 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
171 if (hw->phy.media_type != e1000_media_type_copper) {
172 phy->type = e1000_phy_none;
176 phy->ops.power_up = e1000_power_up_phy_copper;
177 phy->ops.power_down = e1000_power_down_phy_copper_82575;
179 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
180 phy->reset_delay_us = 100;
182 phy->ops.acquire = e1000_acquire_phy_82575;
183 phy->ops.check_reset_block = e1000_check_reset_block_generic;
184 phy->ops.commit = e1000_phy_sw_reset_generic;
185 phy->ops.get_cfg_done = e1000_get_cfg_done_82575;
186 phy->ops.release = e1000_release_phy_82575;
188 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
190 if (e1000_sgmii_active_82575(hw)) {
191 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
192 ctrl_ext |= E1000_CTRL_I2C_ENA;
194 phy->ops.reset = e1000_phy_hw_reset_generic;
195 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
198 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
199 e1000_reset_mdicnfg_82580(hw);
201 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
202 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
203 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
205 switch (hw->mac.type) {
208 phy->ops.read_reg = e1000_read_phy_reg_82580;
209 phy->ops.write_reg = e1000_write_phy_reg_82580;
213 phy->ops.read_reg = e1000_read_phy_reg_gs40g;
214 phy->ops.write_reg = e1000_write_phy_reg_gs40g;
217 phy->ops.read_reg = e1000_read_phy_reg_igp;
218 phy->ops.write_reg = e1000_write_phy_reg_igp;
222 /* Set phy->phy_addr and phy->id. */
223 ret_val = e1000_get_phy_id_82575(hw);
225 /* Verify phy id and set remaining function pointers */
227 case I347AT4_E_PHY_ID:
228 case M88E1112_E_PHY_ID:
229 case M88E1340M_E_PHY_ID:
230 case M88E1111_I_PHY_ID:
231 phy->type = e1000_phy_m88;
232 phy->ops.check_polarity = e1000_check_polarity_m88;
233 phy->ops.get_info = e1000_get_phy_info_m88;
234 if (phy->id == I347AT4_E_PHY_ID ||
235 phy->id == M88E1112_E_PHY_ID ||
236 phy->id == M88E1340M_E_PHY_ID)
237 phy->ops.get_cable_length =
238 e1000_get_cable_length_m88_gen2;
240 phy->ops.get_cable_length = e1000_get_cable_length_m88;
241 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
243 case IGP03E1000_E_PHY_ID:
244 case IGP04E1000_E_PHY_ID:
245 phy->type = e1000_phy_igp_3;
246 phy->ops.check_polarity = e1000_check_polarity_igp;
247 phy->ops.get_info = e1000_get_phy_info_igp;
248 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
249 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
250 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
251 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
253 case I82580_I_PHY_ID:
255 phy->type = e1000_phy_82580;
256 phy->ops.check_polarity = e1000_check_polarity_82577;
257 phy->ops.force_speed_duplex =
258 e1000_phy_force_speed_duplex_82577;
259 phy->ops.get_cable_length = e1000_get_cable_length_82577;
260 phy->ops.get_info = e1000_get_phy_info_82577;
261 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
262 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
265 phy->type = e1000_phy_i210;
266 phy->ops.check_polarity = e1000_check_polarity_m88;
267 phy->ops.get_info = e1000_get_phy_info_m88;
268 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
269 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
270 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
271 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
274 ret_val = -E1000_ERR_PHY;
283 * e1000_init_nvm_params_82575 - Init NVM func ptrs.
284 * @hw: pointer to the HW structure
286 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
288 struct e1000_nvm_info *nvm = &hw->nvm;
289 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
292 DEBUGFUNC("e1000_init_nvm_params_82575");
294 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
295 E1000_EECD_SIZE_EX_SHIFT);
297 * Added to a constant, "size" becomes the left-shift value
298 * for setting word_size.
300 size += NVM_WORD_SIZE_BASE_SHIFT;
302 /* Just in case size is out of range, cap it to the largest
303 * EEPROM size supported
308 nvm->word_size = 1 << size;
309 if (hw->mac.type < e1000_i210) {
310 nvm->opcode_bits = 8;
313 switch (nvm->override) {
314 case e1000_nvm_override_spi_large:
316 nvm->address_bits = 16;
318 case e1000_nvm_override_spi_small:
320 nvm->address_bits = 8;
323 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
324 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
328 if (nvm->word_size == (1 << 15))
329 nvm->page_size = 128;
331 nvm->type = e1000_nvm_eeprom_spi;
333 nvm->type = e1000_nvm_flash_hw;
335 /* Function Pointers */
336 nvm->ops.acquire = e1000_acquire_nvm_82575;
337 nvm->ops.release = e1000_release_nvm_82575;
338 if (nvm->word_size < (1 << 15))
339 nvm->ops.read = e1000_read_nvm_eerd;
341 nvm->ops.read = e1000_read_nvm_spi;
343 nvm->ops.write = e1000_write_nvm_spi;
344 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
345 nvm->ops.update = e1000_update_nvm_checksum_generic;
346 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
348 /* override generic family function pointers for specific descendants */
349 switch (hw->mac.type) {
351 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
352 nvm->ops.update = e1000_update_nvm_checksum_82580;
355 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
356 nvm->ops.update = e1000_update_nvm_checksum_i350;
362 return E1000_SUCCESS;
366 * e1000_init_mac_params_82575 - Init MAC func ptrs.
367 * @hw: pointer to the HW structure
369 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
371 struct e1000_mac_info *mac = &hw->mac;
372 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
374 DEBUGFUNC("e1000_init_mac_params_82575");
376 /* Derives media type */
377 e1000_get_media_type_82575(hw);
378 /* Set mta register count */
379 mac->mta_reg_count = 128;
380 /* Set uta register count */
381 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
382 /* Set rar entry count */
383 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
384 if (mac->type == e1000_82576)
385 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
386 if (mac->type == e1000_82580)
387 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
388 if (mac->type == e1000_i350) {
389 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
390 /* Enable EEE default settings for i350 */
391 dev_spec->eee_disable = FALSE;
394 /* Set if part includes ASF firmware */
395 mac->asf_firmware_present = TRUE;
397 mac->has_fwsm = TRUE;
398 /* ARC supported; valid only if manageability features are enabled. */
399 mac->arc_subsystem_valid =
400 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
402 /* Function pointers */
404 /* bus type/speed/width */
405 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
407 if (mac->type >= e1000_82580)
408 mac->ops.reset_hw = e1000_reset_hw_82580;
410 mac->ops.reset_hw = e1000_reset_hw_82575;
411 /* hw initialization */
412 mac->ops.init_hw = e1000_init_hw_82575;
414 mac->ops.setup_link = e1000_setup_link_generic;
415 /* physical interface link setup */
416 mac->ops.setup_physical_interface =
417 (hw->phy.media_type == e1000_media_type_copper)
418 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
419 /* physical interface shutdown */
420 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
421 /* physical interface power up */
422 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
424 mac->ops.check_for_link = e1000_check_for_link_82575;
425 /* read mac address */
426 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
427 /* configure collision distance */
428 mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
429 /* multicast address update */
430 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
431 if (mac->type == e1000_i350) {
433 mac->ops.write_vfta = e1000_write_vfta_i350;
435 mac->ops.clear_vfta = e1000_clear_vfta_i350;
438 mac->ops.write_vfta = e1000_write_vfta_generic;
440 mac->ops.clear_vfta = e1000_clear_vfta_generic;
442 if (hw->mac.type >= e1000_82580)
443 mac->ops.validate_mdi_setting =
444 e1000_validate_mdi_setting_crossover_generic;
446 mac->ops.id_led_init = e1000_id_led_init_generic;
448 mac->ops.blink_led = e1000_blink_led_generic;
450 mac->ops.setup_led = e1000_setup_led_generic;
452 mac->ops.cleanup_led = e1000_cleanup_led_generic;
453 /* turn on/off LED */
454 mac->ops.led_on = e1000_led_on_generic;
455 mac->ops.led_off = e1000_led_off_generic;
456 /* clear hardware counters */
457 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
459 mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
460 /* acquire SW_FW sync */
461 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;
462 mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;
463 if (mac->type >= e1000_i210) {
464 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;
465 mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;
468 /* set lan id for port to determine which phy lock to use */
469 hw->mac.ops.set_lan_id(hw);
471 return E1000_SUCCESS;
475 * e1000_init_function_pointers_82575 - Init func ptrs.
476 * @hw: pointer to the HW structure
478 * Called to initialize all function pointers and parameters.
480 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
482 DEBUGFUNC("e1000_init_function_pointers_82575");
484 hw->mac.ops.init_params = e1000_init_mac_params_82575;
485 hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
486 hw->phy.ops.init_params = e1000_init_phy_params_82575;
487 hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
491 * e1000_acquire_phy_82575 - Acquire rights to access PHY
492 * @hw: pointer to the HW structure
494 * Acquire access rights to the correct PHY.
496 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
498 u16 mask = E1000_SWFW_PHY0_SM;
500 DEBUGFUNC("e1000_acquire_phy_82575");
502 if (hw->bus.func == E1000_FUNC_1)
503 mask = E1000_SWFW_PHY1_SM;
504 else if (hw->bus.func == E1000_FUNC_2)
505 mask = E1000_SWFW_PHY2_SM;
506 else if (hw->bus.func == E1000_FUNC_3)
507 mask = E1000_SWFW_PHY3_SM;
509 return hw->mac.ops.acquire_swfw_sync(hw, mask);
513 * e1000_release_phy_82575 - Release rights to access PHY
514 * @hw: pointer to the HW structure
516 * A wrapper to release access rights to the correct PHY.
518 static void e1000_release_phy_82575(struct e1000_hw *hw)
520 u16 mask = E1000_SWFW_PHY0_SM;
522 DEBUGFUNC("e1000_release_phy_82575");
524 if (hw->bus.func == E1000_FUNC_1)
525 mask = E1000_SWFW_PHY1_SM;
526 else if (hw->bus.func == E1000_FUNC_2)
527 mask = E1000_SWFW_PHY2_SM;
528 else if (hw->bus.func == E1000_FUNC_3)
529 mask = E1000_SWFW_PHY3_SM;
531 hw->mac.ops.release_swfw_sync(hw, mask);
535 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
536 * @hw: pointer to the HW structure
537 * @offset: register offset to be read
538 * @data: pointer to the read data
540 * Reads the PHY register at offset using the serial gigabit media independent
541 * interface and stores the retrieved information in data.
543 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
546 s32 ret_val = -E1000_ERR_PARAM;
548 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
550 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
551 DEBUGOUT1("PHY Address %u is out of range\n", offset);
555 ret_val = hw->phy.ops.acquire(hw);
559 ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
561 hw->phy.ops.release(hw);
568 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
569 * @hw: pointer to the HW structure
570 * @offset: register offset to write to
571 * @data: data to write at register offset
573 * Writes the data to PHY register at the offset using the serial gigabit
574 * media independent interface.
576 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
579 s32 ret_val = -E1000_ERR_PARAM;
581 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
583 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
584 DEBUGOUT1("PHY Address %d is out of range\n", offset);
588 ret_val = hw->phy.ops.acquire(hw);
592 ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
594 hw->phy.ops.release(hw);
601 * e1000_get_phy_id_82575 - Retrieve PHY addr and id
602 * @hw: pointer to the HW structure
604 * Retrieves the PHY address and ID for both PHY's which do and do not use
607 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
609 struct e1000_phy_info *phy = &hw->phy;
610 s32 ret_val = E1000_SUCCESS;
615 DEBUGFUNC("e1000_get_phy_id_82575");
618 * For SGMII PHYs, we try the list of possible addresses until
619 * we find one that works. For non-SGMII PHYs
620 * (e.g. integrated copper PHYs), an address of 1 should
621 * work. The result of this function should mean phy->phy_addr
622 * and phy->id are set correctly.
624 if (!e1000_sgmii_active_82575(hw)) {
626 ret_val = e1000_get_phy_id(hw);
630 if (e1000_sgmii_uses_mdio_82575(hw)) {
631 switch (hw->mac.type) {
634 mdic = E1000_READ_REG(hw, E1000_MDIC);
635 mdic &= E1000_MDIC_PHY_MASK;
636 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
640 mdic = E1000_READ_REG(hw, E1000_MDICNFG);
641 mdic &= E1000_MDICNFG_PHY_MASK;
642 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
645 ret_val = -E1000_ERR_PHY;
649 ret_val = e1000_get_phy_id(hw);
653 /* Power on sgmii phy if it is disabled */
654 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
655 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
656 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
657 E1000_WRITE_FLUSH(hw);
661 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
662 * Therefore, we need to test 1-7
664 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
665 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
666 if (ret_val == E1000_SUCCESS) {
667 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
670 * At the time of this writing, The M88 part is
671 * the only supported SGMII PHY product.
673 if (phy_id == M88_VENDOR)
676 DEBUGOUT1("PHY address %u was unreadable\n",
681 /* A valid PHY type couldn't be found. */
682 if (phy->addr == 8) {
684 ret_val = -E1000_ERR_PHY;
686 ret_val = e1000_get_phy_id(hw);
689 /* restore previous sfp cage power state */
690 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
697 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
698 * @hw: pointer to the HW structure
700 * Resets the PHY using the serial gigabit media independent interface.
702 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
704 s32 ret_val = E1000_SUCCESS;
706 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
709 * This isn't a TRUE "hard" reset, but is the only reset
710 * available to us at this time.
713 DEBUGOUT("Soft resetting SGMII attached PHY...\n");
715 if (!(hw->phy.ops.write_reg))
719 * SFP documentation requires the following to configure the SPF module
720 * to work on SGMII. No further documentation is given.
722 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
726 ret_val = hw->phy.ops.commit(hw);
733 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
734 * @hw: pointer to the HW structure
735 * @active: TRUE to enable LPLU, FALSE to disable
737 * Sets the LPLU D0 state according to the active flag. When
738 * activating LPLU this function also disables smart speed
739 * and vice versa. LPLU will not be activated unless the
740 * device autonegotiation advertisement meets standards of
741 * either 10 or 10/100 or 10/100/1000 at all duplexes.
742 * This is a function pointer entry point only called by
743 * PHY setup routines.
745 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
747 struct e1000_phy_info *phy = &hw->phy;
748 s32 ret_val = E1000_SUCCESS;
751 DEBUGFUNC("e1000_set_d0_lplu_state_82575");
753 if (!(hw->phy.ops.read_reg))
756 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
761 data |= IGP02E1000_PM_D0_LPLU;
762 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
767 /* When LPLU is enabled, we should disable SmartSpeed */
768 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
770 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
771 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
776 data &= ~IGP02E1000_PM_D0_LPLU;
777 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
780 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
781 * during Dx states where the power conservation is most
782 * important. During driver activity we should enable
783 * SmartSpeed, so performance is maintained.
785 if (phy->smart_speed == e1000_smart_speed_on) {
786 ret_val = phy->ops.read_reg(hw,
787 IGP01E1000_PHY_PORT_CONFIG,
792 data |= IGP01E1000_PSCFR_SMART_SPEED;
793 ret_val = phy->ops.write_reg(hw,
794 IGP01E1000_PHY_PORT_CONFIG,
798 } else if (phy->smart_speed == e1000_smart_speed_off) {
799 ret_val = phy->ops.read_reg(hw,
800 IGP01E1000_PHY_PORT_CONFIG,
805 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
806 ret_val = phy->ops.write_reg(hw,
807 IGP01E1000_PHY_PORT_CONFIG,
819 * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
820 * @hw: pointer to the HW structure
821 * @active: TRUE to enable LPLU, FALSE to disable
823 * Sets the LPLU D0 state according to the active flag. When
824 * activating LPLU this function also disables smart speed
825 * and vice versa. LPLU will not be activated unless the
826 * device autonegotiation advertisement meets standards of
827 * either 10 or 10/100 or 10/100/1000 at all duplexes.
828 * This is a function pointer entry point only called by
829 * PHY setup routines.
831 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
833 struct e1000_phy_info *phy = &hw->phy;
834 s32 ret_val = E1000_SUCCESS;
837 DEBUGFUNC("e1000_set_d0_lplu_state_82580");
839 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
842 data |= E1000_82580_PM_D0_LPLU;
844 /* When LPLU is enabled, we should disable SmartSpeed */
845 data &= ~E1000_82580_PM_SPD;
847 data &= ~E1000_82580_PM_D0_LPLU;
850 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
851 * during Dx states where the power conservation is most
852 * important. During driver activity we should enable
853 * SmartSpeed, so performance is maintained.
855 if (phy->smart_speed == e1000_smart_speed_on)
856 data |= E1000_82580_PM_SPD;
857 else if (phy->smart_speed == e1000_smart_speed_off)
858 data &= ~E1000_82580_PM_SPD;
861 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
866 * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
867 * @hw: pointer to the HW structure
868 * @active: boolean used to enable/disable lplu
870 * Success returns 0, Failure returns 1
872 * The low power link up (lplu) state is set to the power management level D3
873 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3
874 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
875 * is used during Dx states where the power conservation is most important.
876 * During driver activity, SmartSpeed should be enabled so performance is
879 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
881 struct e1000_phy_info *phy = &hw->phy;
882 s32 ret_val = E1000_SUCCESS;
885 DEBUGFUNC("e1000_set_d3_lplu_state_82580");
887 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
890 data &= ~E1000_82580_PM_D3_LPLU;
892 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
893 * during Dx states where the power conservation is most
894 * important. During driver activity we should enable
895 * SmartSpeed, so performance is maintained.
897 if (phy->smart_speed == e1000_smart_speed_on)
898 data |= E1000_82580_PM_SPD;
899 else if (phy->smart_speed == e1000_smart_speed_off)
900 data &= ~E1000_82580_PM_SPD;
901 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
902 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
903 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
904 data |= E1000_82580_PM_D3_LPLU;
905 /* When LPLU is enabled, we should disable SmartSpeed */
906 data &= ~E1000_82580_PM_SPD;
909 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
914 * e1000_acquire_nvm_82575 - Request for access to EEPROM
915 * @hw: pointer to the HW structure
917 * Acquire the necessary semaphores for exclusive access to the EEPROM.
918 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
919 * Return successful if access grant bit set, else clear the request for
920 * EEPROM access and return -E1000_ERR_NVM (-1).
922 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
926 DEBUGFUNC("e1000_acquire_nvm_82575");
928 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
933 * Check if there is some access
934 * error this access may hook on
936 if (hw->mac.type == e1000_i350) {
937 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
938 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
939 E1000_EECD_TIMEOUT)) {
940 /* Clear all access error flags */
941 E1000_WRITE_REG(hw, E1000_EECD, eecd |
942 E1000_EECD_ERROR_CLR);
943 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
946 if (hw->mac.type == e1000_82580) {
947 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
948 if (eecd & E1000_EECD_BLOCKED) {
949 /* Clear access error flag */
950 E1000_WRITE_REG(hw, E1000_EECD, eecd |
952 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
957 ret_val = e1000_acquire_nvm_generic(hw);
959 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
966 * e1000_release_nvm_82575 - Release exclusive access to EEPROM
967 * @hw: pointer to the HW structure
969 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
970 * then release the semaphores acquired.
972 static void e1000_release_nvm_82575(struct e1000_hw *hw)
974 DEBUGFUNC("e1000_release_nvm_82575");
976 e1000_release_nvm_generic(hw);
978 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
982 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
983 * @hw: pointer to the HW structure
984 * @mask: specifies which semaphore to acquire
986 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
987 * will also specify which port we're acquiring the lock for.
989 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
993 u32 fwmask = mask << 16;
994 s32 ret_val = E1000_SUCCESS;
995 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
997 DEBUGFUNC("e1000_acquire_swfw_sync_82575");
999 while (i < timeout) {
1000 if (e1000_get_hw_semaphore_generic(hw)) {
1001 ret_val = -E1000_ERR_SWFW_SYNC;
1005 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1006 if (!(swfw_sync & (fwmask | swmask)))
1010 * Firmware currently using resource (fwmask)
1011 * or other software thread using resource (swmask)
1013 e1000_put_hw_semaphore_generic(hw);
1019 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1020 ret_val = -E1000_ERR_SWFW_SYNC;
1024 swfw_sync |= swmask;
1025 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1027 e1000_put_hw_semaphore_generic(hw);
1034 * e1000_release_swfw_sync_82575 - Release SW/FW semaphore
1035 * @hw: pointer to the HW structure
1036 * @mask: specifies which semaphore to acquire
1038 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
1039 * will also specify which port we're releasing the lock for.
1041 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1045 DEBUGFUNC("e1000_release_swfw_sync_82575");
1047 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1050 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1052 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1054 e1000_put_hw_semaphore_generic(hw);
1058 * e1000_get_cfg_done_82575 - Read config done bit
1059 * @hw: pointer to the HW structure
1061 * Read the management control register for the config done bit for
1062 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1063 * to read the config done bit, so an error is *ONLY* logged and returns
1064 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
1065 * would not be able to be reset or change link.
1067 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1069 s32 timeout = PHY_CFG_TIMEOUT;
1070 s32 ret_val = E1000_SUCCESS;
1071 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1073 DEBUGFUNC("e1000_get_cfg_done_82575");
1075 if (hw->bus.func == E1000_FUNC_1)
1076 mask = E1000_NVM_CFG_DONE_PORT_1;
1077 else if (hw->bus.func == E1000_FUNC_2)
1078 mask = E1000_NVM_CFG_DONE_PORT_2;
1079 else if (hw->bus.func == E1000_FUNC_3)
1080 mask = E1000_NVM_CFG_DONE_PORT_3;
1082 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1088 DEBUGOUT("MNG configuration cycle has not completed.\n");
1090 /* If EEPROM is not marked present, init the PHY manually */
1091 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1092 (hw->phy.type == e1000_phy_igp_3))
1093 e1000_phy_init_script_igp3(hw);
1099 * e1000_get_link_up_info_82575 - Get link speed/duplex info
1100 * @hw: pointer to the HW structure
1101 * @speed: stores the current speed
1102 * @duplex: stores the current duplex
1104 * This is a wrapper function, if using the serial gigabit media independent
1105 * interface, use PCS to retrieve the link speed and duplex information.
1106 * Otherwise, use the generic function to get the link speed and duplex info.
1108 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1113 DEBUGFUNC("e1000_get_link_up_info_82575");
1115 if (hw->phy.media_type != e1000_media_type_copper)
1116 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1119 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1126 * e1000_check_for_link_82575 - Check for link
1127 * @hw: pointer to the HW structure
1129 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1130 * use the generic interface for determining link.
1132 static s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1137 DEBUGFUNC("e1000_check_for_link_82575");
1139 if (hw->phy.media_type != e1000_media_type_copper) {
1140 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1143 * Use this flag to determine if link needs to be checked or
1144 * not. If we have link clear the flag so that we do not
1145 * continue to check for link.
1147 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1150 * Configure Flow Control now that Auto-Neg has completed.
1151 * First, we need to restore the desired flow control
1152 * settings because we may have had to re-autoneg with a
1153 * different link partner.
1155 ret_val = e1000_config_fc_after_link_up_generic(hw);
1157 DEBUGOUT("Error configuring flow control\n");
1159 ret_val = e1000_check_for_copper_link_generic(hw);
1166 * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1167 * @hw: pointer to the HW structure
1169 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1173 DEBUGFUNC("e1000_power_up_serdes_link_82575");
1175 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1176 !e1000_sgmii_active_82575(hw))
1179 /* Enable PCS to turn on link */
1180 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1181 reg |= E1000_PCS_CFG_PCS_EN;
1182 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1184 /* Power up the laser */
1185 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1186 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1187 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1189 /* flush the write to verify completion */
1190 E1000_WRITE_FLUSH(hw);
1195 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1196 * @hw: pointer to the HW structure
1197 * @speed: stores the current speed
1198 * @duplex: stores the current duplex
1200 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1201 * duplex, then store the values in the pointers provided.
1203 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1204 u16 *speed, u16 *duplex)
1206 struct e1000_mac_info *mac = &hw->mac;
1209 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1212 * Read the PCS Status register for link state. For non-copper mode,
1213 * the status register is not accurate. The PCS status register is
1216 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1219 * The link up bit determines when link is up on autoneg.
1221 if (pcs & E1000_PCS_LSTS_LINK_OK) {
1222 mac->serdes_has_link = TRUE;
1224 /* Detect and store PCS speed */
1225 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1226 *speed = SPEED_1000;
1227 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1232 /* Detect and store PCS duplex */
1233 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1234 *duplex = FULL_DUPLEX;
1236 *duplex = HALF_DUPLEX;
1238 mac->serdes_has_link = FALSE;
1243 return E1000_SUCCESS;
1247 * e1000_shutdown_serdes_link_82575 - Remove link during power down
1248 * @hw: pointer to the HW structure
1250 * In the case of serdes shut down sfp and PCS on driver unload
1251 * when management pass thru is not enabled.
1253 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1257 DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1259 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1260 !e1000_sgmii_active_82575(hw))
1263 if (!e1000_enable_mng_pass_thru(hw)) {
1264 /* Disable PCS to turn off link */
1265 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1266 reg &= ~E1000_PCS_CFG_PCS_EN;
1267 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1269 /* shutdown the laser */
1270 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1271 reg |= E1000_CTRL_EXT_SDP3_DATA;
1272 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1274 /* flush the write to verify completion */
1275 E1000_WRITE_FLUSH(hw);
1283 * e1000_reset_hw_82575 - Reset hardware
1284 * @hw: pointer to the HW structure
1286 * This resets the hardware into a known state.
1288 static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1293 DEBUGFUNC("e1000_reset_hw_82575");
1296 * Prevent the PCI-E bus from sticking if there is no TLP connection
1297 * on the last TLP read/write transaction when MAC is reset.
1299 ret_val = e1000_disable_pcie_master_generic(hw);
1301 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1303 /* set the completion timeout for interface */
1304 ret_val = e1000_set_pcie_completion_timeout(hw);
1306 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1308 DEBUGOUT("Masking off all interrupts\n");
1309 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1311 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1312 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1313 E1000_WRITE_FLUSH(hw);
1317 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1319 DEBUGOUT("Issuing a global reset to MAC\n");
1320 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1322 ret_val = e1000_get_auto_rd_done_generic(hw);
1325 * When auto config read does not complete, do not
1326 * return with an error. This can happen in situations
1327 * where there is no eeprom and prevents getting link.
1329 DEBUGOUT("Auto Read Done did not complete\n");
1332 /* If EEPROM is not present, run manual init scripts */
1333 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1334 e1000_reset_init_script_82575(hw);
1336 /* Clear any pending interrupt events. */
1337 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1338 E1000_READ_REG(hw, E1000_ICR);
1340 /* Install any alternate MAC address into RAR0 */
1341 ret_val = e1000_check_alt_mac_addr_generic(hw);
1347 * e1000_init_hw_82575 - Initialize hardware
1348 * @hw: pointer to the HW structure
1350 * This inits the hardware readying it for operation.
1352 static s32 e1000_init_hw_82575(struct e1000_hw *hw)
1354 struct e1000_mac_info *mac = &hw->mac;
1356 u16 i, rar_count = mac->rar_entry_count;
1358 DEBUGFUNC("e1000_init_hw_82575");
1360 /* Initialize identification LED */
1361 ret_val = mac->ops.id_led_init(hw);
1363 DEBUGOUT("Error initializing identification LED\n");
1364 /* This is not fatal and we should not stop init due to this */
1367 /* Disabling VLAN filtering */
1368 DEBUGOUT("Initializing the IEEE VLAN\n");
1369 mac->ops.clear_vfta(hw);
1371 /* Setup the receive address */
1372 e1000_init_rx_addrs_generic(hw, rar_count);
1374 /* Zero out the Multicast HASH table */
1375 DEBUGOUT("Zeroing the MTA\n");
1376 for (i = 0; i < mac->mta_reg_count; i++)
1377 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1379 /* Zero out the Unicast HASH table */
1380 DEBUGOUT("Zeroing the UTA\n");
1381 for (i = 0; i < mac->uta_reg_count; i++)
1382 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1384 /* Setup link and flow control */
1385 ret_val = mac->ops.setup_link(hw);
1387 /* Set the default MTU size */
1388 hw->dev_spec._82575.mtu = 1500;
1391 * Clear all of the statistics registers (clear on read). It is
1392 * important that we do this after we have tried to establish link
1393 * because the symbol error count will increment wildly if there
1396 e1000_clear_hw_cntrs_82575(hw);
1402 * e1000_setup_copper_link_82575 - Configure copper link settings
1403 * @hw: pointer to the HW structure
1405 * Configures the link for auto-neg or forced speed and duplex. Then we check
1406 * for link, once link is established calls to configure collision distance
1407 * and flow control are called.
1409 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1415 DEBUGFUNC("e1000_setup_copper_link_82575");
1417 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1418 ctrl |= E1000_CTRL_SLU;
1419 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1420 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1422 /* Clear Go Link Disconnect bit */
1423 if (hw->mac.type >= e1000_82580) {
1424 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1425 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1426 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1429 ret_val = e1000_setup_serdes_link_82575(hw);
1433 if (e1000_sgmii_active_82575(hw)) {
1434 /* allow time for SFP cage time to power up phy */
1437 ret_val = hw->phy.ops.reset(hw);
1439 DEBUGOUT("Error resetting the PHY.\n");
1443 switch (hw->phy.type) {
1444 case e1000_phy_i210:
1446 if (hw->phy.id == I347AT4_E_PHY_ID ||
1447 hw->phy.id == M88E1112_E_PHY_ID ||
1448 hw->phy.id == M88E1340M_E_PHY_ID)
1449 ret_val = e1000_copper_link_setup_m88_gen2(hw);
1451 ret_val = e1000_copper_link_setup_m88(hw);
1453 case e1000_phy_igp_3:
1454 ret_val = e1000_copper_link_setup_igp(hw);
1456 case e1000_phy_82580:
1457 ret_val = e1000_copper_link_setup_82577(hw);
1460 ret_val = -E1000_ERR_PHY;
1467 ret_val = e1000_setup_copper_link_generic(hw);
1473 * e1000_setup_serdes_link_82575 - Setup link for serdes
1474 * @hw: pointer to the HW structure
1476 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1477 * used on copper connections where the serialized gigabit media independent
1478 * interface (sgmii), or serdes fiber is being used. Configures the link
1479 * for auto-negotiation or forces speed/duplex.
1481 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1483 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1485 s32 ret_val = E1000_SUCCESS;
1488 DEBUGFUNC("e1000_setup_serdes_link_82575");
1490 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1491 !e1000_sgmii_active_82575(hw))
1495 * On the 82575, SerDes loopback mode persists until it is
1496 * explicitly turned off or a power cycle is performed. A read to
1497 * the register does not indicate its status. Therefore, we ensure
1498 * loopback mode is disabled during initialization.
1500 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1502 /* power on the sfp cage if present */
1503 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1504 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1505 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1507 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1508 ctrl_reg |= E1000_CTRL_SLU;
1510 /* set both sw defined pins on 82575/82576*/
1511 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1512 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1514 reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1516 /* default pcs_autoneg to the same setting as mac autoneg */
1517 pcs_autoneg = hw->mac.autoneg;
1519 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1520 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1521 /* sgmii mode lets the phy handle forcing speed/duplex */
1523 /* autoneg time out should be disabled for SGMII mode */
1524 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1526 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1527 /* disable PCS autoneg and support parallel detect only */
1528 pcs_autoneg = FALSE;
1529 /* fall through to default case */
1531 if (hw->mac.type == e1000_82575 ||
1532 hw->mac.type == e1000_82576) {
1533 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1535 DEBUGOUT("NVM Read Error\n");
1539 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1540 pcs_autoneg = FALSE;
1544 * non-SGMII modes only supports a speed of 1000/Full for the
1545 * link so it is best to just force the MAC and let the pcs
1546 * link either autoneg or be forced to 1000/Full
1548 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1549 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1551 /* set speed of 1000/Full if speed/duplex is forced */
1552 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1556 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1559 * New SerDes mode allows for forcing speed or autonegotiating speed
1560 * at 1gb. Autoneg should be default set by most drivers. This is the
1561 * mode that will be compatible with older link partners and switches.
1562 * However, both are supported by the hardware and some drivers/tools.
1564 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1565 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1568 /* Set PCS register for autoneg */
1569 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1570 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1572 /* Disable force flow control for autoneg */
1573 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1575 /* Configure flow control advertisement for autoneg */
1576 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1577 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1579 switch (hw->fc.requested_mode) {
1581 case e1000_fc_rx_pause:
1582 anadv_reg |= E1000_TXCW_ASM_DIR;
1583 anadv_reg |= E1000_TXCW_PAUSE;
1585 case e1000_fc_tx_pause:
1586 anadv_reg |= E1000_TXCW_ASM_DIR;
1592 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1594 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1596 /* Set PCS register for forced link */
1597 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1599 /* Force flow control for forced link */
1600 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1602 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1605 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1607 if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1608 e1000_force_mac_fc_generic(hw);
1614 * e1000_get_media_type_82575 - derives current media type.
1615 * @hw: pointer to the HW structure
1617 * The media type is chosen reflecting few settings.
1618 * The following are taken into account:
1619 * - link mode set in the current port Init Control Word #3
1620 * - current link mode settings in CSR register
1621 * - MDIO vs. I2C PHY control interface chosen
1622 * - SFP module media type
1624 static s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1627 s32 ret_val = E1000_ERR_CONFIG;
1628 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1630 u32 current_link_mode = 0;
1631 u16 init_ctrl_wd_3 = 0;
1632 u8 init_ctrl_wd_3_offset = 0;
1633 u8 init_ctrl_wd_3_bit_offset = 0;
1635 /* Set internal phy as default */
1636 dev_spec->sgmii_active = FALSE;
1637 dev_spec->module_plugged = FALSE;
1640 * Check if NVM access method is attached already.
1641 * If it is then Init Control Word #3 is considered
1642 * otherwise runtime CSR register content is taken.
1645 /* Get CSR setting */
1646 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1648 /* Get link mode setting */
1649 if ((hw->nvm.ops.read) && (hw->nvm.ops.read != e1000_null_read_nvm)) {
1650 /* Take link mode from EEPROM */
1653 * Get LAN port ID to derive its
1654 * adequate Init Control Word #3
1656 lan_id = ((E1000_READ_REG(hw, E1000_STATUS) &
1657 E1000_STATUS_LAN_ID_MASK) >> E1000_STATUS_LAN_ID_OFFSET);
1659 * Derive Init Control Word #3 offset
1660 * and mask to pick up link mode setting.
1662 if (hw->mac.type < e1000_82580) {
1663 init_ctrl_wd_3_offset = lan_id ?
1664 NVM_INIT_CONTROL3_PORT_A : NVM_INIT_CONTROL3_PORT_B;
1665 init_ctrl_wd_3_bit_offset = NVM_WORD24_LNK_MODE_OFFSET;
1667 init_ctrl_wd_3_offset =
1668 NVM_82580_LAN_FUNC_OFFSET(lan_id) +
1669 NVM_INIT_CONTROL3_PORT_A;
1670 init_ctrl_wd_3_bit_offset =
1671 NVM_WORD24_82580_LNK_MODE_OFFSET;
1673 /* Read Init Control Word #3*/
1674 hw->nvm.ops.read(hw, init_ctrl_wd_3_offset, 1, &init_ctrl_wd_3);
1677 * Align link mode bits to
1678 * their CTRL_EXT location.
1680 current_link_mode = init_ctrl_wd_3;
1681 current_link_mode <<= (E1000_CTRL_EXT_LINK_MODE_OFFSET -
1682 init_ctrl_wd_3_bit_offset);
1683 current_link_mode &= E1000_CTRL_EXT_LINK_MODE_MASK;
1686 * Switch to CSR for all but internal PHY.
1688 if (current_link_mode != E1000_CTRL_EXT_LINK_MODE_GMII)
1689 /* Take link mode from CSR */
1690 current_link_mode = ctrl_ext &
1691 E1000_CTRL_EXT_LINK_MODE_MASK;
1693 /* Take link mode from CSR */
1694 current_link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1697 switch (current_link_mode) {
1699 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1700 hw->phy.media_type = e1000_media_type_internal_serdes;
1701 current_link_mode = E1000_CTRL_EXT_LINK_MODE_1000BASE_KX;
1703 case E1000_CTRL_EXT_LINK_MODE_GMII:
1704 hw->phy.media_type = e1000_media_type_copper;
1705 current_link_mode = E1000_CTRL_EXT_LINK_MODE_GMII;
1707 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1708 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1709 /* Get phy control interface type set (MDIO vs. I2C)*/
1710 if (e1000_sgmii_uses_mdio_82575(hw)) {
1711 hw->phy.media_type = e1000_media_type_copper;
1712 dev_spec->sgmii_active = TRUE;
1713 current_link_mode = E1000_CTRL_EXT_LINK_MODE_SGMII;
1715 ret_val = e1000_set_sfp_media_type_82575(hw);
1716 if (ret_val != E1000_SUCCESS)
1718 if (hw->phy.media_type ==
1719 e1000_media_type_internal_serdes) {
1720 /* Keep Link Mode as SGMII for 100BaseFX */
1721 if (!dev_spec->eth_flags.e100_base_fx) {
1723 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1725 } else if (hw->phy.media_type ==
1726 e1000_media_type_copper) {
1728 E1000_CTRL_EXT_LINK_MODE_SGMII;
1733 DEBUGOUT("Link mode mask doesn't fit bit field size\n");
1737 * Do not change current link mode setting
1738 * if media type is fibre or has not been
1741 if ((hw->phy.media_type != e1000_media_type_unknown) &&
1742 (hw->phy.media_type != e1000_media_type_fiber)) {
1743 /* Update link mode */
1744 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1745 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext |
1749 ret_val = E1000_SUCCESS;
1752 * If media type was not identified then return media type
1753 * defined by the CTRL_EXT settings.
1755 if (hw->phy.media_type == e1000_media_type_unknown) {
1756 if (current_link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII)
1757 hw->phy.media_type = e1000_media_type_copper;
1759 hw->phy.media_type = e1000_media_type_internal_serdes;
1766 * e1000_set_sfp_media_type_82575 - derives SFP module media type.
1767 * @hw: pointer to the HW structure
1769 * The media type is chosen based on SFP module.
1770 * compatibility flags retrieved from SFP ID EEPROM.
1772 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1774 s32 ret_val = E1000_ERR_CONFIG;
1776 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1777 struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1778 u8 tranceiver_type = 0;
1781 /* Turn I2C interface ON and power on sfp cage */
1782 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1783 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1784 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1786 E1000_WRITE_FLUSH(hw);
1788 /* Read SFP module data */
1790 ret_val = e1000_read_sfp_data_byte(hw,
1791 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1793 if (ret_val == E1000_SUCCESS)
1798 if (ret_val != E1000_SUCCESS)
1800 ret_val = e1000_read_sfp_data_byte(hw,
1801 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1803 if (ret_val != E1000_SUCCESS)
1806 * Check if there is some SFP
1807 * module plugged and powered
1809 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1810 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1811 dev_spec->module_plugged = TRUE;
1812 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1813 hw->phy.media_type = e1000_media_type_internal_serdes;
1814 } else if (eth_flags->e100_base_fx) {
1815 dev_spec->sgmii_active = TRUE;
1816 hw->phy.media_type = e1000_media_type_internal_serdes;
1817 } else if (eth_flags->e1000_base_t) {
1818 dev_spec->sgmii_active = TRUE;
1819 hw->phy.media_type = e1000_media_type_copper;
1821 hw->phy.media_type = e1000_media_type_unknown;
1822 DEBUGOUT("PHY module has not been recognized\n");
1826 hw->phy.media_type = e1000_media_type_unknown;
1828 ret_val = E1000_SUCCESS;
1830 /* Restore I2C interface setting */
1831 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1836 * e1000_valid_led_default_82575 - Verify a valid default LED config
1837 * @hw: pointer to the HW structure
1838 * @data: pointer to the NVM (EEPROM)
1840 * Read the EEPROM for the current default LED configuration. If the
1841 * LED configuration is not valid, set to a valid LED configuration.
1843 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1847 DEBUGFUNC("e1000_valid_led_default_82575");
1849 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1851 DEBUGOUT("NVM Read Error\n");
1855 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1856 switch (hw->phy.media_type) {
1857 case e1000_media_type_internal_serdes:
1858 *data = ID_LED_DEFAULT_82575_SERDES;
1860 case e1000_media_type_copper:
1862 *data = ID_LED_DEFAULT;
1871 * e1000_sgmii_active_82575 - Return sgmii state
1872 * @hw: pointer to the HW structure
1874 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1875 * which can be enabled for use in the embedded applications. Simply
1876 * return the current state of the sgmii interface.
1878 static bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1880 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1881 return dev_spec->sgmii_active;
1885 * e1000_reset_init_script_82575 - Inits HW defaults after reset
1886 * @hw: pointer to the HW structure
1888 * Inits recommended HW defaults after a reset when there is no EEPROM
1889 * detected. This is only for the 82575.
1891 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1893 DEBUGFUNC("e1000_reset_init_script_82575");
1895 if (hw->mac.type == e1000_82575) {
1896 DEBUGOUT("Running reset init script for 82575\n");
1897 /* SerDes configuration via SERDESCTRL */
1898 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1899 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1900 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1901 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1903 /* CCM configuration via CCMCTL register */
1904 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1905 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1907 /* PCIe lanes configuration */
1908 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1909 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1910 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1911 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1913 /* PCIe PLL Configuration */
1914 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1915 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1916 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1919 return E1000_SUCCESS;
1923 * e1000_read_mac_addr_82575 - Read device MAC address
1924 * @hw: pointer to the HW structure
1926 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
1928 s32 ret_val = E1000_SUCCESS;
1930 DEBUGFUNC("e1000_read_mac_addr_82575");
1933 * If there's an alternate MAC address place it in RAR0
1934 * so that it will override the Si installed default perm
1937 ret_val = e1000_check_alt_mac_addr_generic(hw);
1941 ret_val = e1000_read_mac_addr_generic(hw);
1948 * e1000_config_collision_dist_82575 - Configure collision distance
1949 * @hw: pointer to the HW structure
1951 * Configures the collision distance to the default value and is used
1952 * during link setup.
1954 static void e1000_config_collision_dist_82575(struct e1000_hw *hw)
1958 DEBUGFUNC("e1000_config_collision_dist_82575");
1960 tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
1962 tctl_ext &= ~E1000_TCTL_EXT_COLD;
1963 tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
1965 E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
1966 E1000_WRITE_FLUSH(hw);
1970 * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
1971 * @hw: pointer to the HW structure
1973 * In the case of a PHY power down to save power, or to turn off link during a
1974 * driver unload, or wake on lan is not enabled, remove the link.
1976 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
1978 struct e1000_phy_info *phy = &hw->phy;
1980 if (!(phy->ops.check_reset_block))
1983 /* If the management interface is not enabled, then power down */
1984 if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
1985 e1000_power_down_phy_copper(hw);
1991 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
1992 * @hw: pointer to the HW structure
1994 * Clears the hardware counters by reading the counter registers.
1996 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
1998 DEBUGFUNC("e1000_clear_hw_cntrs_82575");
2000 e1000_clear_hw_cntrs_base_generic(hw);
2002 E1000_READ_REG(hw, E1000_PRC64);
2003 E1000_READ_REG(hw, E1000_PRC127);
2004 E1000_READ_REG(hw, E1000_PRC255);
2005 E1000_READ_REG(hw, E1000_PRC511);
2006 E1000_READ_REG(hw, E1000_PRC1023);
2007 E1000_READ_REG(hw, E1000_PRC1522);
2008 E1000_READ_REG(hw, E1000_PTC64);
2009 E1000_READ_REG(hw, E1000_PTC127);
2010 E1000_READ_REG(hw, E1000_PTC255);
2011 E1000_READ_REG(hw, E1000_PTC511);
2012 E1000_READ_REG(hw, E1000_PTC1023);
2013 E1000_READ_REG(hw, E1000_PTC1522);
2015 E1000_READ_REG(hw, E1000_ALGNERRC);
2016 E1000_READ_REG(hw, E1000_RXERRC);
2017 E1000_READ_REG(hw, E1000_TNCRS);
2018 E1000_READ_REG(hw, E1000_CEXTERR);
2019 E1000_READ_REG(hw, E1000_TSCTC);
2020 E1000_READ_REG(hw, E1000_TSCTFC);
2022 E1000_READ_REG(hw, E1000_MGTPRC);
2023 E1000_READ_REG(hw, E1000_MGTPDC);
2024 E1000_READ_REG(hw, E1000_MGTPTC);
2026 E1000_READ_REG(hw, E1000_IAC);
2027 E1000_READ_REG(hw, E1000_ICRXOC);
2029 E1000_READ_REG(hw, E1000_ICRXPTC);
2030 E1000_READ_REG(hw, E1000_ICRXATC);
2031 E1000_READ_REG(hw, E1000_ICTXPTC);
2032 E1000_READ_REG(hw, E1000_ICTXATC);
2033 E1000_READ_REG(hw, E1000_ICTXQEC);
2034 E1000_READ_REG(hw, E1000_ICTXQMTC);
2035 E1000_READ_REG(hw, E1000_ICRXDMTC);
2037 E1000_READ_REG(hw, E1000_CBTMPC);
2038 E1000_READ_REG(hw, E1000_HTDPMC);
2039 E1000_READ_REG(hw, E1000_CBRMPC);
2040 E1000_READ_REG(hw, E1000_RPTHC);
2041 E1000_READ_REG(hw, E1000_HGPTC);
2042 E1000_READ_REG(hw, E1000_HTCBDPC);
2043 E1000_READ_REG(hw, E1000_HGORCL);
2044 E1000_READ_REG(hw, E1000_HGORCH);
2045 E1000_READ_REG(hw, E1000_HGOTCL);
2046 E1000_READ_REG(hw, E1000_HGOTCH);
2047 E1000_READ_REG(hw, E1000_LENERRS);
2049 /* This register should not be read in copper configurations */
2050 if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
2051 e1000_sgmii_active_82575(hw))
2052 E1000_READ_REG(hw, E1000_SCVPC);
2056 * e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
2057 * @hw: pointer to the HW structure
2059 * After rx enable if managability is enabled then there is likely some
2060 * bad data at the start of the fifo and possibly in the DMA fifo. This
2061 * function clears the fifos and flushes any packets that came in as rx was
2064 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
2066 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
2069 DEBUGFUNC("e1000_rx_fifo_workaround_82575");
2070 if (hw->mac.type != e1000_82575 ||
2071 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
2074 /* Disable all Rx queues */
2075 for (i = 0; i < 4; i++) {
2076 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
2077 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
2078 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
2080 /* Poll all queues to verify they have shut down */
2081 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
2084 for (i = 0; i < 4; i++)
2085 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
2086 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
2091 DEBUGOUT("Queue disable timed out after 10ms\n");
2093 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
2094 * incoming packets are rejected. Set enable and wait 2ms so that
2095 * any packet that was coming in as RCTL.EN was set is flushed
2097 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2098 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
2100 rlpml = E1000_READ_REG(hw, E1000_RLPML);
2101 E1000_WRITE_REG(hw, E1000_RLPML, 0);
2103 rctl = E1000_READ_REG(hw, E1000_RCTL);
2104 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
2105 temp_rctl |= E1000_RCTL_LPE;
2107 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
2108 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2109 E1000_WRITE_FLUSH(hw);
2112 /* Enable Rx queues that were previously enabled and restore our
2115 for (i = 0; i < 4; i++)
2116 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
2117 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2118 E1000_WRITE_FLUSH(hw);
2120 E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
2121 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2123 /* Flush receive errors generated by workaround */
2124 E1000_READ_REG(hw, E1000_ROC);
2125 E1000_READ_REG(hw, E1000_RNBC);
2126 E1000_READ_REG(hw, E1000_MPC);
2130 * e1000_set_pcie_completion_timeout - set pci-e completion timeout
2131 * @hw: pointer to the HW structure
2133 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2134 * however the hardware default for these parts is 500us to 1ms which is less
2135 * than the 10ms recommended by the pci-e spec. To address this we need to
2136 * increase the value to either 10ms to 200ms for capability version 1 config,
2137 * or 16ms to 55ms for version 2.
2139 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
2141 u32 gcr = E1000_READ_REG(hw, E1000_GCR);
2142 s32 ret_val = E1000_SUCCESS;
2145 /* only take action if timeout value is defaulted to 0 */
2146 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2150 * if capababilities version is type 1 we can write the
2151 * timeout of 10ms to 200ms through the GCR register
2153 if (!(gcr & E1000_GCR_CAP_VER2)) {
2154 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2159 * for version 2 capabilities we need to write the config space
2160 * directly in order to set the completion timeout value for
2163 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2168 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2170 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2173 /* disable completion timeout resend */
2174 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2176 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2181 * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2182 * @hw: pointer to the hardware struct
2183 * @enable: state to enter, either enabled or disabled
2184 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2186 * enables/disables L2 switch anti-spoofing functionality.
2188 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2192 switch (hw->mac.type) {
2194 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2196 dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2197 E1000_DTXSWC_VLAN_SPOOF_MASK);
2198 /* The PF can spoof - it has to in order to
2199 * support emulation mode NICs */
2200 dtxswc ^= (1 << pf | 1 << (pf +
2201 E1000_DTXSWC_VLAN_SPOOF_SHIFT));
2203 dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2204 E1000_DTXSWC_VLAN_SPOOF_MASK);
2206 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2209 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2211 dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2212 E1000_DTXSWC_VLAN_SPOOF_MASK);
2213 /* The PF can spoof - it has to in order to
2214 * support emulation mode NICs
2216 dtxswc ^= (1 << pf | 1 << (pf +
2217 E1000_DTXSWC_VLAN_SPOOF_SHIFT));
2219 dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2220 E1000_DTXSWC_VLAN_SPOOF_MASK);
2222 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2229 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2230 * @hw: pointer to the hardware struct
2231 * @enable: state to enter, either enabled or disabled
2233 * enables/disables L2 switch loopback functionality.
2235 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2239 switch (hw->mac.type) {
2241 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2243 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2245 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2246 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2249 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2251 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2253 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2254 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2257 /* Currently no other hardware supports loopback */
2265 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2266 * @hw: pointer to the hardware struct
2267 * @enable: state to enter, either enabled or disabled
2269 * enables/disables replication of packets across multiple pools.
2271 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2273 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2276 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2278 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2280 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2284 * e1000_read_phy_reg_82580 - Read 82580 MDI control register
2285 * @hw: pointer to the HW structure
2286 * @offset: register offset to be read
2287 * @data: pointer to the read data
2289 * Reads the MDI control register in the PHY at offset and stores the
2290 * information read to data.
2292 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2296 DEBUGFUNC("e1000_read_phy_reg_82580");
2298 ret_val = hw->phy.ops.acquire(hw);
2302 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2304 hw->phy.ops.release(hw);
2311 * e1000_write_phy_reg_82580 - Write 82580 MDI control register
2312 * @hw: pointer to the HW structure
2313 * @offset: register offset to write to
2314 * @data: data to write to register at offset
2316 * Writes data to MDI control register in the PHY at offset.
2318 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2322 DEBUGFUNC("e1000_write_phy_reg_82580");
2324 ret_val = hw->phy.ops.acquire(hw);
2328 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2330 hw->phy.ops.release(hw);
2337 * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2338 * @hw: pointer to the HW structure
2340 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2341 * the values found in the EEPROM. This addresses an issue in which these
2342 * bits are not restored from EEPROM after reset.
2344 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2346 s32 ret_val = E1000_SUCCESS;
2350 DEBUGFUNC("e1000_reset_mdicnfg_82580");
2352 if (hw->mac.type != e1000_82580)
2354 if (!e1000_sgmii_active_82575(hw))
2357 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2358 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2361 DEBUGOUT("NVM Read Error\n");
2365 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2366 if (nvm_data & NVM_WORD24_EXT_MDIO)
2367 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2368 if (nvm_data & NVM_WORD24_COM_MDIO)
2369 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2370 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2376 * e1000_reset_hw_82580 - Reset hardware
2377 * @hw: pointer to the HW structure
2379 * This resets function or entire device (all ports, etc.)
2382 static s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2384 s32 ret_val = E1000_SUCCESS;
2385 /* BH SW mailbox bit in SW_FW_SYNC */
2386 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2388 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2390 DEBUGFUNC("e1000_reset_hw_82580");
2392 hw->dev_spec._82575.global_device_reset = FALSE;
2394 /* Get current control state. */
2395 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2398 * Prevent the PCI-E bus from sticking if there is no TLP connection
2399 * on the last TLP read/write transaction when MAC is reset.
2401 ret_val = e1000_disable_pcie_master_generic(hw);
2403 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2405 DEBUGOUT("Masking off all interrupts\n");
2406 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2407 E1000_WRITE_REG(hw, E1000_RCTL, 0);
2408 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2409 E1000_WRITE_FLUSH(hw);
2413 /* Determine whether or not a global dev reset is requested */
2414 if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2416 global_device_reset = FALSE;
2418 if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2419 E1000_STAT_DEV_RST_SET))
2420 ctrl |= E1000_CTRL_DEV_RST;
2422 ctrl |= E1000_CTRL_RST;
2424 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2425 E1000_WRITE_FLUSH(hw);
2427 /* Add delay to insure DEV_RST has time to complete */
2428 if (global_device_reset)
2431 ret_val = e1000_get_auto_rd_done_generic(hw);
2434 * When auto config read does not complete, do not
2435 * return with an error. This can happen in situations
2436 * where there is no eeprom and prevents getting link.
2438 DEBUGOUT("Auto Read Done did not complete\n");
2441 /* If EEPROM is not present, run manual init scripts */
2442 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
2443 e1000_reset_init_script_82575(hw);
2445 /* clear global device reset status bit */
2446 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2448 /* Clear any pending interrupt events. */
2449 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2450 E1000_READ_REG(hw, E1000_ICR);
2452 ret_val = e1000_reset_mdicnfg_82580(hw);
2454 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2456 /* Install any alternate MAC address into RAR0 */
2457 ret_val = e1000_check_alt_mac_addr_generic(hw);
2459 /* Release semaphore */
2460 if (global_device_reset)
2461 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2467 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2468 * @data: data received by reading RXPBS register
2470 * The 82580 uses a table based approach for packet buffer allocation sizes.
2471 * This function converts the retrieved value into the correct table value
2472 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2473 * 0x0 36 72 144 1 2 4 8 16
2474 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2476 u16 e1000_rxpbs_adjust_82580(u32 data)
2480 if (data < E1000_82580_RXPBS_TABLE_SIZE)
2481 ret_val = e1000_82580_rxpbs_table[data];
2487 * e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2489 * @hw: pointer to the HW structure
2490 * @offset: offset in words of the checksum protected region
2492 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2493 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2495 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2497 s32 ret_val = E1000_SUCCESS;
2501 DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2503 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2504 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2506 DEBUGOUT("NVM Read Error\n");
2509 checksum += nvm_data;
2512 if (checksum != (u16) NVM_SUM) {
2513 DEBUGOUT("NVM Checksum Invalid\n");
2514 ret_val = -E1000_ERR_NVM;
2523 * e1000_update_nvm_checksum_with_offset - Update EEPROM
2525 * @hw: pointer to the HW structure
2526 * @offset: offset in words of the checksum protected region
2528 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2529 * up to the checksum. Then calculates the EEPROM checksum and writes the
2530 * value to the EEPROM.
2532 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2538 DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2540 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2541 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2543 DEBUGOUT("NVM Read Error while updating checksum.\n");
2546 checksum += nvm_data;
2548 checksum = (u16) NVM_SUM - checksum;
2549 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2552 DEBUGOUT("NVM Write Error while updating checksum.\n");
2559 * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2560 * @hw: pointer to the HW structure
2562 * Calculates the EEPROM section checksum by reading/adding each word of
2563 * the EEPROM and then verifies that the sum of the EEPROM is
2566 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2568 s32 ret_val = E1000_SUCCESS;
2569 u16 eeprom_regions_count = 1;
2573 DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2575 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2577 DEBUGOUT("NVM Read Error\n");
2581 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2582 /* if chekcsums compatibility bit is set validate checksums
2583 * for all 4 ports. */
2584 eeprom_regions_count = 4;
2587 for (j = 0; j < eeprom_regions_count; j++) {
2588 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2589 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2591 if (ret_val != E1000_SUCCESS)
2600 * e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2601 * @hw: pointer to the HW structure
2603 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2604 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2605 * checksum and writes the value to the EEPROM.
2607 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2613 DEBUGFUNC("e1000_update_nvm_checksum_82580");
2615 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2617 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2621 if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2622 /* set compatibility bit to validate checksums appropriately */
2623 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2624 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2627 DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2632 for (j = 0; j < 4; j++) {
2633 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2634 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2644 * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2645 * @hw: pointer to the HW structure
2647 * Calculates the EEPROM section checksum by reading/adding each word of
2648 * the EEPROM and then verifies that the sum of the EEPROM is
2651 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2653 s32 ret_val = E1000_SUCCESS;
2657 DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2659 for (j = 0; j < 4; j++) {
2660 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2661 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2663 if (ret_val != E1000_SUCCESS)
2672 * e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2673 * @hw: pointer to the HW structure
2675 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2676 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2677 * checksum and writes the value to the EEPROM.
2679 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2681 s32 ret_val = E1000_SUCCESS;
2685 DEBUGFUNC("e1000_update_nvm_checksum_i350");
2687 for (j = 0; j < 4; j++) {
2688 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2689 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2690 if (ret_val != E1000_SUCCESS)
2699 * e1000_set_eee_i350 - Enable/disable EEE support
2700 * @hw: pointer to the HW structure
2702 * Enable/disable EEE based on setting in dev_spec structure.
2705 s32 e1000_set_eee_i350(struct e1000_hw *hw)
2707 s32 ret_val = E1000_SUCCESS;
2710 DEBUGFUNC("e1000_set_eee_i350");
2712 if ((hw->mac.type < e1000_i350) ||
2713 (hw->phy.media_type != e1000_media_type_copper))
2715 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2716 eeer = E1000_READ_REG(hw, E1000_EEER);
2718 /* enable or disable per user setting */
2719 if (!(hw->dev_spec._82575.eee_disable)) {
2720 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2721 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2724 /* keep the LPI clock running before EEE is enabled */
2725 if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) {
2727 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
2728 eee_su &= ~E1000_EEE_SU_LPI_CLK_STP;
2729 E1000_WRITE_REG(hw, E1000_EEE_SU, eee_su);
2733 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2734 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2737 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2738 E1000_WRITE_REG(hw, E1000_EEER, eeer);
2739 E1000_READ_REG(hw, E1000_IPCNFG);
2740 E1000_READ_REG(hw, E1000_EEER);
2746 /* Due to a hw errata, if the host tries to configure the VFTA register
2747 * while performing queries from the BMC or DMA, then the VFTA in some
2748 * cases won't be written.
2752 * e1000_clear_vfta_i350 - Clear VLAN filter table
2753 * @hw: pointer to the HW structure
2755 * Clears the register array which contains the VLAN filter table by
2756 * setting all the values to 0.
2758 void e1000_clear_vfta_i350(struct e1000_hw *hw)
2763 DEBUGFUNC("e1000_clear_vfta_350");
2765 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
2766 for (i = 0; i < 10; i++)
2767 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
2769 E1000_WRITE_FLUSH(hw);
2774 * e1000_write_vfta_i350 - Write value to VLAN filter table
2775 * @hw: pointer to the HW structure
2776 * @offset: register offset in VLAN filter table
2777 * @value: register value written to VLAN filter table
2779 * Writes value at the given offset in the register array which stores
2780 * the VLAN filter table.
2782 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
2786 DEBUGFUNC("e1000_write_vfta_350");
2788 for (i = 0; i < 10; i++)
2789 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
2791 E1000_WRITE_FLUSH(hw);
2796 * e1000_set_i2c_bb - Enable I2C bit-bang
2797 * @hw: pointer to the HW structure
2799 * Enable I2C bit-bang interface
2802 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
2804 s32 ret_val = E1000_SUCCESS;
2805 u32 ctrl_ext, i2cparams;
2807 DEBUGFUNC("e1000_set_i2c_bb");
2809 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2810 ctrl_ext |= E1000_CTRL_I2C_ENA;
2811 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2812 E1000_WRITE_FLUSH(hw);
2814 i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
2815 i2cparams |= E1000_I2CBB_EN;
2816 i2cparams |= E1000_I2C_DATA_OE_N;
2817 i2cparams |= E1000_I2C_CLK_OE_N;
2818 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
2819 E1000_WRITE_FLUSH(hw);
2825 * e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
2826 * @hw: pointer to hardware structure
2827 * @byte_offset: byte offset to read
2828 * @dev_addr: device address
2831 * Performs byte read operation over I2C interface at
2832 * a specified device address.
2834 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
2835 u8 dev_addr, u8 *data)
2837 s32 status = E1000_SUCCESS;
2844 DEBUGFUNC("e1000_read_i2c_byte_generic");
2846 swfw_mask = E1000_SWFW_PHY0_SM;
2849 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
2851 status = E1000_ERR_SWFW_SYNC;
2855 e1000_i2c_start(hw);
2857 /* Device Address and write indication */
2858 status = e1000_clock_out_i2c_byte(hw, dev_addr);
2859 if (status != E1000_SUCCESS)
2862 status = e1000_get_i2c_ack(hw);
2863 if (status != E1000_SUCCESS)
2866 status = e1000_clock_out_i2c_byte(hw, byte_offset);
2867 if (status != E1000_SUCCESS)
2870 status = e1000_get_i2c_ack(hw);
2871 if (status != E1000_SUCCESS)
2874 e1000_i2c_start(hw);
2876 /* Device Address and read indication */
2877 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2878 if (status != E1000_SUCCESS)
2881 status = e1000_get_i2c_ack(hw);
2882 if (status != E1000_SUCCESS)
2885 status = e1000_clock_in_i2c_byte(hw, data);
2886 if (status != E1000_SUCCESS)
2889 status = e1000_clock_out_i2c_bit(hw, nack);
2890 if (status != E1000_SUCCESS)
2897 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2899 e1000_i2c_bus_clear(hw);
2901 if (retry < max_retry)
2902 DEBUGOUT("I2C byte read error - Retrying.\n");
2904 DEBUGOUT("I2C byte read error.\n");
2906 } while (retry < max_retry);
2908 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2916 * e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
2917 * @hw: pointer to hardware structure
2918 * @byte_offset: byte offset to write
2919 * @dev_addr: device address
2920 * @data: value to write
2922 * Performs byte write operation over I2C interface at
2923 * a specified device address.
2925 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
2926 u8 dev_addr, u8 data)
2928 s32 status = E1000_SUCCESS;
2933 DEBUGFUNC("e1000_write_i2c_byte_generic");
2935 swfw_mask = E1000_SWFW_PHY0_SM;
2937 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
2938 status = E1000_ERR_SWFW_SYNC;
2939 goto write_byte_out;
2943 e1000_i2c_start(hw);
2945 status = e1000_clock_out_i2c_byte(hw, dev_addr);
2946 if (status != E1000_SUCCESS)
2949 status = e1000_get_i2c_ack(hw);
2950 if (status != E1000_SUCCESS)
2953 status = e1000_clock_out_i2c_byte(hw, byte_offset);
2954 if (status != E1000_SUCCESS)
2957 status = e1000_get_i2c_ack(hw);
2958 if (status != E1000_SUCCESS)
2961 status = e1000_clock_out_i2c_byte(hw, data);
2962 if (status != E1000_SUCCESS)
2965 status = e1000_get_i2c_ack(hw);
2966 if (status != E1000_SUCCESS)
2973 e1000_i2c_bus_clear(hw);
2975 if (retry < max_retry)
2976 DEBUGOUT("I2C byte write error - Retrying.\n");
2978 DEBUGOUT("I2C byte write error.\n");
2979 } while (retry < max_retry);
2981 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2989 * e1000_i2c_start - Sets I2C start condition
2990 * @hw: pointer to hardware structure
2992 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2994 static void e1000_i2c_start(struct e1000_hw *hw)
2996 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
2998 DEBUGFUNC("e1000_i2c_start");
3000 /* Start condition must begin with data and clock high */
3001 e1000_set_i2c_data(hw, &i2cctl, 1);
3002 e1000_raise_i2c_clk(hw, &i2cctl);
3004 /* Setup time for start condition (4.7us) */
3005 usec_delay(E1000_I2C_T_SU_STA);
3007 e1000_set_i2c_data(hw, &i2cctl, 0);
3009 /* Hold time for start condition (4us) */
3010 usec_delay(E1000_I2C_T_HD_STA);
3012 e1000_lower_i2c_clk(hw, &i2cctl);
3014 /* Minimum low period of clock is 4.7 us */
3015 usec_delay(E1000_I2C_T_LOW);
3020 * e1000_i2c_stop - Sets I2C stop condition
3021 * @hw: pointer to hardware structure
3023 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
3025 static void e1000_i2c_stop(struct e1000_hw *hw)
3027 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3029 DEBUGFUNC("e1000_i2c_stop");
3031 /* Stop condition must begin with data low and clock high */
3032 e1000_set_i2c_data(hw, &i2cctl, 0);
3033 e1000_raise_i2c_clk(hw, &i2cctl);
3035 /* Setup time for stop condition (4us) */
3036 usec_delay(E1000_I2C_T_SU_STO);
3038 e1000_set_i2c_data(hw, &i2cctl, 1);
3040 /* bus free time between stop and start (4.7us)*/
3041 usec_delay(E1000_I2C_T_BUF);
3045 * e1000_clock_in_i2c_byte - Clocks in one byte via I2C
3046 * @hw: pointer to hardware structure
3047 * @data: data byte to clock in
3049 * Clocks in one byte data via I2C data/clock
3051 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3056 DEBUGFUNC("e1000_clock_in_i2c_byte");
3059 for (i = 7; i >= 0; i--) {
3060 e1000_clock_in_i2c_bit(hw, &bit);
3064 return E1000_SUCCESS;
3068 * e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3069 * @hw: pointer to hardware structure
3070 * @data: data byte clocked out
3072 * Clocks out one byte data via I2C data/clock
3074 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3076 s32 status = E1000_SUCCESS;
3081 DEBUGFUNC("e1000_clock_out_i2c_byte");
3083 for (i = 7; i >= 0; i--) {
3084 bit = (data >> i) & 0x1;
3085 status = e1000_clock_out_i2c_bit(hw, bit);
3087 if (status != E1000_SUCCESS)
3091 /* Release SDA line (set high) */
3092 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3094 i2cctl |= E1000_I2C_DATA_OE_N;
3095 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3096 E1000_WRITE_FLUSH(hw);
3102 * e1000_get_i2c_ack - Polls for I2C ACK
3103 * @hw: pointer to hardware structure
3105 * Clocks in/out one bit via I2C data/clock
3107 static s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3109 s32 status = E1000_SUCCESS;
3111 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3115 DEBUGFUNC("e1000_get_i2c_ack");
3117 e1000_raise_i2c_clk(hw, &i2cctl);
3119 /* Minimum high period of clock is 4us */
3120 usec_delay(E1000_I2C_T_HIGH);
3122 /* Wait until SCL returns high */
3123 for (i = 0; i < timeout; i++) {
3125 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3126 if (i2cctl & E1000_I2C_CLK_IN)
3129 if (!(i2cctl & E1000_I2C_CLK_IN))
3130 return E1000_ERR_I2C;
3132 ack = e1000_get_i2c_data(&i2cctl);
3134 DEBUGOUT("I2C ack was not received.\n");
3135 status = E1000_ERR_I2C;
3138 e1000_lower_i2c_clk(hw, &i2cctl);
3140 /* Minimum low period of clock is 4.7 us */
3141 usec_delay(E1000_I2C_T_LOW);
3147 * e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3148 * @hw: pointer to hardware structure
3149 * @data: read data value
3151 * Clocks in one bit via I2C data/clock
3153 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3155 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3157 DEBUGFUNC("e1000_clock_in_i2c_bit");
3159 e1000_raise_i2c_clk(hw, &i2cctl);
3161 /* Minimum high period of clock is 4us */
3162 usec_delay(E1000_I2C_T_HIGH);
3164 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3165 *data = e1000_get_i2c_data(&i2cctl);
3167 e1000_lower_i2c_clk(hw, &i2cctl);
3169 /* Minimum low period of clock is 4.7 us */
3170 usec_delay(E1000_I2C_T_LOW);
3172 return E1000_SUCCESS;
3176 * e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3177 * @hw: pointer to hardware structure
3178 * @data: data value to write
3180 * Clocks out one bit via I2C data/clock
3182 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3185 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3187 DEBUGFUNC("e1000_clock_out_i2c_bit");
3189 status = e1000_set_i2c_data(hw, &i2cctl, data);
3190 if (status == E1000_SUCCESS) {
3191 e1000_raise_i2c_clk(hw, &i2cctl);
3193 /* Minimum high period of clock is 4us */
3194 usec_delay(E1000_I2C_T_HIGH);
3196 e1000_lower_i2c_clk(hw, &i2cctl);
3198 /* Minimum low period of clock is 4.7 us.
3199 * This also takes care of the data hold time.
3201 usec_delay(E1000_I2C_T_LOW);
3203 status = E1000_ERR_I2C;
3204 DEBUGOUT1("I2C data was not set to %X\n", data);
3210 * e1000_raise_i2c_clk - Raises the I2C SCL clock
3211 * @hw: pointer to hardware structure
3212 * @i2cctl: Current value of I2CCTL register
3214 * Raises the I2C clock line '0'->'1'
3216 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3218 DEBUGFUNC("e1000_raise_i2c_clk");
3220 *i2cctl |= E1000_I2C_CLK_OUT;
3221 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3222 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3223 E1000_WRITE_FLUSH(hw);
3225 /* SCL rise time (1000ns) */
3226 usec_delay(E1000_I2C_T_RISE);
3230 * e1000_lower_i2c_clk - Lowers the I2C SCL clock
3231 * @hw: pointer to hardware structure
3232 * @i2cctl: Current value of I2CCTL register
3234 * Lowers the I2C clock line '1'->'0'
3236 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3239 DEBUGFUNC("e1000_lower_i2c_clk");
3241 *i2cctl &= ~E1000_I2C_CLK_OUT;
3242 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3243 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3244 E1000_WRITE_FLUSH(hw);
3246 /* SCL fall time (300ns) */
3247 usec_delay(E1000_I2C_T_FALL);
3251 * e1000_set_i2c_data - Sets the I2C data bit
3252 * @hw: pointer to hardware structure
3253 * @i2cctl: Current value of I2CCTL register
3254 * @data: I2C data value (0 or 1) to set
3256 * Sets the I2C data bit
3258 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3260 s32 status = E1000_SUCCESS;
3262 DEBUGFUNC("e1000_set_i2c_data");
3265 *i2cctl |= E1000_I2C_DATA_OUT;
3267 *i2cctl &= ~E1000_I2C_DATA_OUT;
3269 *i2cctl &= ~E1000_I2C_DATA_OE_N;
3270 *i2cctl |= E1000_I2C_CLK_OE_N;
3271 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3272 E1000_WRITE_FLUSH(hw);
3274 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3275 usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3277 *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3278 if (data != e1000_get_i2c_data(i2cctl)) {
3279 status = E1000_ERR_I2C;
3280 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3287 * e1000_get_i2c_data - Reads the I2C SDA data bit
3288 * @hw: pointer to hardware structure
3289 * @i2cctl: Current value of I2CCTL register
3291 * Returns the I2C data bit value
3293 static bool e1000_get_i2c_data(u32 *i2cctl)
3297 DEBUGFUNC("e1000_get_i2c_data");
3299 if (*i2cctl & E1000_I2C_DATA_IN)
3308 * e1000_i2c_bus_clear - Clears the I2C bus
3309 * @hw: pointer to hardware structure
3311 * Clears the I2C bus by sending nine clock pulses.
3312 * Used when data line is stuck low.
3314 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3316 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3319 DEBUGFUNC("e1000_i2c_bus_clear");
3321 e1000_i2c_start(hw);
3323 e1000_set_i2c_data(hw, &i2cctl, 1);
3325 for (i = 0; i < 9; i++) {
3326 e1000_raise_i2c_clk(hw, &i2cctl);
3328 /* Min high period of clock is 4us */
3329 usec_delay(E1000_I2C_T_HIGH);
3331 e1000_lower_i2c_clk(hw, &i2cctl);
3333 /* Min low period of clock is 4.7us*/
3334 usec_delay(E1000_I2C_T_LOW);
3337 e1000_i2c_start(hw);
3339 /* Put the i2c bus back to default state */