1 /* LRA (local register allocator) driver and LRA utilities.
2 Copyright (C) 2010-2015 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* The Local Register Allocator (LRA) is a replacement of former
23 reload pass. It is focused to simplify code solving the reload
24 pass tasks, to make the code maintenance easier, and to implement new
25 perspective optimizations.
27 The major LRA design solutions are:
28 o division small manageable, separated sub-tasks
29 o reflection of all transformations and decisions in RTL as more
31 o insn constraints as a primary source of the info (minimizing
32 number of target-depended macros/hooks)
34 In brief LRA works by iterative insn process with the final goal is
35 to satisfy all insn and address constraints:
36 o New reload insns (in brief reloads) and reload pseudos might be
38 o Some pseudos might be spilled to assign hard registers to
40 o Recalculating spilled pseudo values (rematerialization);
41 o Changing spilled pseudos to stack memory or their equivalences;
42 o Allocation stack memory changes the address displacement and
43 new iteration is needed.
45 Here is block diagram of LRA passes:
47 ------------------------
48 --------------- | Undo inheritance for | ---------------
49 | Memory-memory | | spilled pseudos, | | New (and old) |
50 | move coalesce |<---| splits for pseudos got |<-- | pseudos |
51 --------------- | the same hard regs, | | assignment |
52 Start | | and optional reloads | ---------------
53 | | ------------------------ ^
54 V | ---------------- |
55 ----------- V | Update virtual | |
56 | Remove |----> ------------>| register | |
57 | scratches | ^ | displacements | |
58 ----------- | ---------------- |
61 | ------------ pseudos -------------------
62 | |Constraints:| or insns | Inheritance/split |
63 | | RTL |--------->| transformations |
64 | | transfor- | | in EBB scope |
65 | substi- | mations | -------------------
66 | tutions ------------
69 | Spilled pseudo | -------------------
70 | to memory |<----| Rematerialization |
71 | substitution | -------------------
75 -------------------------
76 | Hard regs substitution, |
77 | devirtalization, and |------> Finish
78 | restoring scratches got |
80 -------------------------
82 To speed up the process:
83 o We process only insns affected by changes on previous
85 o We don't use DFA-infrastructure because it results in much slower
86 compiler speed than a special IR described below does;
87 o We use a special insn representation for quick access to insn
88 info which is always *synchronized* with the current RTL;
89 o Insn IR is minimized by memory. It is divided on three parts:
90 o one specific for each insn in RTL (only operand locations);
91 o one common for all insns in RTL with the same insn code
92 (different operand attributes from machine descriptions);
93 o one oriented for maintenance of live info (list of pseudos).
95 o all insns where the pseudo is referenced;
96 o live info (conflicting hard regs, live ranges, # of
98 o data used for assigning (preferred hard regs, costs etc).
100 This file contains LRA driver, LRA utility functions and data, and
101 code for dealing with scratches. */
105 #include "coretypes.h"
107 #include "hard-reg-set.h"
111 #include "insn-config.h"
112 #include "insn-codes.h"
115 #include "addresses.h"
118 #include "hash-set.h"
120 #include "machmode.h"
122 #include "function.h"
124 #include "wide-int.h"
128 #include "statistics.h"
129 #include "double-int.h"
131 #include "fixed-value.h"
137 #include "emit-rtl.h"
142 #include "dominance.h"
145 #include "cfgbuild.h"
146 #include "basic-block.h"
148 #include "tree-pass.h"
155 /* Dump bitmap SET with TITLE and BB INDEX. */
157 lra_dump_bitmap_with_title (const char *title, bitmap set, int index)
162 static const int max_nums_on_line = 10;
164 if (bitmap_empty_p (set))
166 fprintf (lra_dump_file, " %s %d:", title, index);
167 fprintf (lra_dump_file, "\n");
168 count = max_nums_on_line + 1;
169 EXECUTE_IF_SET_IN_BITMAP (set, 0, i, bi)
171 if (count > max_nums_on_line)
173 fprintf (lra_dump_file, "\n ");
176 fprintf (lra_dump_file, " %4u", i);
179 fprintf (lra_dump_file, "\n");
182 /* Hard registers currently not available for allocation. It can
183 changed after some hard registers become not eliminable. */
184 HARD_REG_SET lra_no_alloc_regs;
186 static int get_new_reg_value (void);
187 static void expand_reg_info (void);
188 static void invalidate_insn_recog_data (int);
189 static int get_insn_freq (rtx_insn *);
190 static void invalidate_insn_data_regno_info (lra_insn_recog_data_t,
193 /* Expand all regno related info needed for LRA. */
195 expand_reg_data (int old)
199 ira_expand_reg_equiv ();
200 for (int i = (int) max_reg_num () - 1; i >= old; i--)
201 lra_change_class (i, ALL_REGS, " Set", true);
204 /* Create and return a new reg of ORIGINAL mode. If ORIGINAL is NULL
205 or of VOIDmode, use MD_MODE for the new reg. Initialize its
206 register class to RCLASS. Print message about assigning class
207 RCLASS containing new register name TITLE unless it is NULL. Use
208 attributes of ORIGINAL if it is a register. The created register
209 will have unique held value. */
211 lra_create_new_reg_with_unique_value (machine_mode md_mode, rtx original,
212 enum reg_class rclass, const char *title)
217 if (original == NULL_RTX || (mode = GET_MODE (original)) == VOIDmode)
219 lra_assert (mode != VOIDmode);
220 new_reg = gen_reg_rtx (mode);
221 if (original == NULL_RTX || ! REG_P (original))
223 if (lra_dump_file != NULL)
224 fprintf (lra_dump_file, " Creating newreg=%i", REGNO (new_reg));
228 if (ORIGINAL_REGNO (original) >= FIRST_PSEUDO_REGISTER)
229 ORIGINAL_REGNO (new_reg) = ORIGINAL_REGNO (original);
230 REG_USERVAR_P (new_reg) = REG_USERVAR_P (original);
231 REG_POINTER (new_reg) = REG_POINTER (original);
232 REG_ATTRS (new_reg) = REG_ATTRS (original);
233 if (lra_dump_file != NULL)
234 fprintf (lra_dump_file, " Creating newreg=%i from oldreg=%i",
235 REGNO (new_reg), REGNO (original));
237 if (lra_dump_file != NULL)
240 fprintf (lra_dump_file, ", assigning class %s to%s%s r%d",
241 reg_class_names[rclass], *title == '\0' ? "" : " ",
242 title, REGNO (new_reg));
243 fprintf (lra_dump_file, "\n");
245 expand_reg_data (max_reg_num ());
246 setup_reg_classes (REGNO (new_reg), rclass, NO_REGS, rclass);
250 /* Analogous to the previous function but also inherits value of
253 lra_create_new_reg (machine_mode md_mode, rtx original,
254 enum reg_class rclass, const char *title)
259 = lra_create_new_reg_with_unique_value (md_mode, original, rclass, title);
260 if (original != NULL_RTX && REG_P (original))
261 lra_assign_reg_val (REGNO (original), REGNO (new_reg));
265 /* Set up for REGNO unique hold value. */
267 lra_set_regno_unique_value (int regno)
269 lra_reg_info[regno].val = get_new_reg_value ();
272 /* Invalidate INSN related info used by LRA. The info should never be
275 lra_invalidate_insn_data (rtx_insn *insn)
277 lra_invalidate_insn_regno_info (insn);
278 invalidate_insn_recog_data (INSN_UID (insn));
281 /* Mark INSN deleted and invalidate the insn related info used by
284 lra_set_insn_deleted (rtx_insn *insn)
286 lra_invalidate_insn_data (insn);
287 SET_INSN_DELETED (insn);
290 /* Delete an unneeded INSN and any previous insns who sole purpose is
291 loading data that is dead in INSN. */
293 lra_delete_dead_insn (rtx_insn *insn)
295 rtx_insn *prev = prev_real_insn (insn);
298 /* If the previous insn sets a register that dies in our insn,
300 if (prev && GET_CODE (PATTERN (prev)) == SET
301 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
302 && reg_mentioned_p (prev_dest, PATTERN (insn))
303 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
304 && ! side_effects_p (SET_SRC (PATTERN (prev))))
305 lra_delete_dead_insn (prev);
307 lra_set_insn_deleted (insn);
310 /* Emit insn x = y + z. Return NULL if we failed to do it.
311 Otherwise, return the insn. We don't use gen_add3_insn as it might
314 emit_add3_insn (rtx x, rtx y, rtx z)
318 last = get_last_insn ();
320 if (have_addptr3_insn (x, y, z))
322 rtx insn = gen_addptr3_insn (x, y, z);
324 /* If the target provides an "addptr" pattern it hopefully does
325 for a reason. So falling back to the normal add would be
327 lra_assert (insn != NULL_RTX);
332 rtx_insn *insn = emit_insn (gen_rtx_SET (VOIDmode, x,
333 gen_rtx_PLUS (GET_MODE (y), y, z)));
334 if (recog_memoized (insn) < 0)
336 delete_insns_since (last);
342 /* Emit insn x = x + y. Return the insn. We use gen_add2_insn as the
345 emit_add2_insn (rtx x, rtx y)
349 insn = emit_add3_insn (x, x, y);
350 if (insn == NULL_RTX)
352 insn = gen_add2_insn (x, y);
353 if (insn != NULL_RTX)
359 /* Target checks operands through operand predicates to recognize an
360 insn. We should have a special precaution to generate add insns
361 which are frequent results of elimination.
363 Emit insns for x = y + z. X can be used to store intermediate
364 values and should be not in Y and Z when we use X to store an
365 intermediate value. Y + Z should form [base] [+ index[ * scale]] [
366 + disp] where base and index are registers, disp and scale are
367 constants. Y should contain base if it is present, Z should
368 contain disp if any. index[*scale] can be part of Y or Z. */
370 lra_emit_add (rtx x, rtx y, rtx z)
374 rtx a1, a2, base, index, disp, scale, index_scale;
377 rtx add3_insn = emit_add3_insn (x, y, z);
378 old = max_reg_num ();
379 if (add3_insn != NULL)
383 disp = a2 = NULL_RTX;
384 if (GET_CODE (y) == PLUS)
398 index_scale = scale = NULL_RTX;
399 if (GET_CODE (a1) == MULT)
402 index = XEXP (a1, 0);
403 scale = XEXP (a1, 1);
406 else if (a2 != NULL_RTX && GET_CODE (a2) == MULT)
409 index = XEXP (a2, 0);
410 scale = XEXP (a2, 1);
418 if (! (REG_P (base) || GET_CODE (base) == SUBREG)
419 || (index != NULL_RTX
420 && ! (REG_P (index) || GET_CODE (index) == SUBREG))
421 || (disp != NULL_RTX && ! CONSTANT_P (disp))
422 || (scale != NULL_RTX && ! CONSTANT_P (scale)))
424 /* Probably we have no 3 op add. Last chance is to use 2-op
425 add insn. To succeed, don't move Z to X as an address
426 segment always comes in Y. Otherwise, we might fail when
427 adding the address segment to register. */
428 lra_assert (x != y && x != z);
429 emit_move_insn (x, y);
430 rtx insn = emit_add2_insn (x, z);
431 lra_assert (insn != NULL_RTX);
435 if (index_scale == NULL_RTX)
437 if (disp == NULL_RTX)
439 /* Generate x = index_scale; x = x + base. */
440 lra_assert (index_scale != NULL_RTX && base != NULL_RTX);
441 emit_move_insn (x, index_scale);
442 rtx insn = emit_add2_insn (x, base);
443 lra_assert (insn != NULL_RTX);
445 else if (scale == NULL_RTX)
447 /* Try x = base + disp. */
448 lra_assert (base != NULL_RTX);
449 last = get_last_insn ();
450 rtx_insn *move_insn =
451 emit_move_insn (x, gen_rtx_PLUS (GET_MODE (base), base, disp));
452 if (recog_memoized (move_insn) < 0)
454 delete_insns_since (last);
455 /* Generate x = disp; x = x + base. */
456 emit_move_insn (x, disp);
457 rtx add2_insn = emit_add2_insn (x, base);
458 lra_assert (add2_insn != NULL_RTX);
460 /* Generate x = x + index. */
461 if (index != NULL_RTX)
463 rtx insn = emit_add2_insn (x, index);
464 lra_assert (insn != NULL_RTX);
469 /* Try x = index_scale; x = x + disp; x = x + base. */
470 last = get_last_insn ();
471 rtx_insn *move_insn = emit_move_insn (x, index_scale);
473 if (recog_memoized (move_insn) >= 0)
475 rtx insn = emit_add2_insn (x, disp);
476 if (insn != NULL_RTX)
478 insn = emit_add2_insn (x, base);
479 if (insn != NULL_RTX)
485 delete_insns_since (last);
486 /* Generate x = disp; x = x + base; x = x + index_scale. */
487 emit_move_insn (x, disp);
488 rtx insn = emit_add2_insn (x, base);
489 lra_assert (insn != NULL_RTX);
490 insn = emit_add2_insn (x, index_scale);
491 lra_assert (insn != NULL_RTX);
496 /* Functions emit_... can create pseudos -- so expand the pseudo
498 if (old != max_reg_num ())
499 expand_reg_data (old);
502 /* The number of emitted reload insns so far. */
503 int lra_curr_reload_num;
505 /* Emit x := y, processing special case when y = u + v or y = u + v *
506 scale + w through emit_add (Y can be an address which is base +
507 index reg * scale + displacement in general case). X may be used
508 as intermediate result therefore it should be not in Y. */
510 lra_emit_move (rtx x, rtx y)
514 if (GET_CODE (y) != PLUS)
516 if (rtx_equal_p (x, y))
518 old = max_reg_num ();
519 emit_move_insn (x, y);
521 lra_reg_info[ORIGINAL_REGNO (x)].last_reload = ++lra_curr_reload_num;
522 /* Function emit_move can create pseudos -- so expand the pseudo
524 if (old != max_reg_num ())
525 expand_reg_data (old);
528 lra_emit_add (x, XEXP (y, 0), XEXP (y, 1));
531 /* Update insn operands which are duplication of operands whose
532 numbers are in array of NOPS (with end marker -1). The insn is
533 represented by its LRA internal representation ID. */
535 lra_update_dups (lra_insn_recog_data_t id, signed char *nops)
538 struct lra_static_insn_data *static_id = id->insn_static_data;
540 for (i = 0; i < static_id->n_dups; i++)
541 for (j = 0; (nop = nops[j]) >= 0; j++)
542 if (static_id->dup_num[i] == nop)
543 *id->dup_loc[i] = *id->operand_loc[nop];
548 /* This page contains code dealing with info about registers in the
551 /* Pools for insn reg info. */
552 static alloc_pool insn_reg_pool;
554 /* Initiate pool for insn reg info. */
556 init_insn_regs (void)
559 = create_alloc_pool ("insn regs", sizeof (struct lra_insn_reg), 100);
562 /* Create LRA insn related info about a reference to REGNO in INSN with
563 TYPE (in/out/inout), biggest reference mode MODE, flag that it is
564 reference through subreg (SUBREG_P), flag that is early clobbered
565 in the insn (EARLY_CLOBBER), and reference to the next insn reg
567 static struct lra_insn_reg *
568 new_insn_reg (rtx_insn *insn, int regno, enum op_type type,
570 bool subreg_p, bool early_clobber, struct lra_insn_reg *next)
572 struct lra_insn_reg *ir;
574 ir = (struct lra_insn_reg *) pool_alloc (insn_reg_pool);
576 ir->biggest_mode = mode;
577 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (lra_reg_info[regno].biggest_mode)
578 && NONDEBUG_INSN_P (insn))
579 lra_reg_info[regno].biggest_mode = mode;
580 ir->subreg_p = subreg_p;
581 ir->early_clobber = early_clobber;
587 /* Free insn reg info IR. */
589 free_insn_reg (struct lra_insn_reg *ir)
591 pool_free (insn_reg_pool, ir);
594 /* Free insn reg info list IR. */
596 free_insn_regs (struct lra_insn_reg *ir)
598 struct lra_insn_reg *next_ir;
600 for (; ir != NULL; ir = next_ir)
607 /* Finish pool for insn reg info. */
609 finish_insn_regs (void)
611 free_alloc_pool (insn_reg_pool);
616 /* This page contains code dealing LRA insn info (or in other words
617 LRA internal insn representation). */
619 /* Map INSN_CODE -> the static insn data. This info is valid during
620 all translation unit. */
621 struct lra_static_insn_data *insn_code_data[LAST_INSN_CODE];
623 /* Debug insns are represented as a special insn with one input
624 operand which is RTL expression in var_location. */
626 /* The following data are used as static insn operand data for all
627 debug insns. If structure lra_operand_data is changed, the
628 initializer should be changed too. */
629 static struct lra_operand_data debug_operand_data =
631 NULL, /* alternative */
632 VOIDmode, /* We are not interesting in the operand mode. */
637 /* The following data are used as static insn data for all debug
638 insns. If structure lra_static_insn_data is changed, the
639 initializer should be changed too. */
640 static struct lra_static_insn_data debug_insn_static_data =
643 0, /* Duplication operands #. */
644 -1, /* Commutative operand #. */
645 1, /* Operands #. There is only one operand which is debug RTL
647 0, /* Duplications #. */
648 0, /* Alternatives #. We are not interesting in alternatives
649 because we does not proceed debug_insns for reloads. */
650 NULL, /* Hard registers referenced in machine description. */
651 NULL /* Descriptions of operands in alternatives. */
654 /* Called once per compiler work to initialize some LRA data related
657 init_insn_code_data_once (void)
659 memset (insn_code_data, 0, sizeof (insn_code_data));
662 /* Called once per compiler work to finalize some LRA data related to
665 finish_insn_code_data_once (void)
669 for (i = 0; i < LAST_INSN_CODE; i++)
671 if (insn_code_data[i] != NULL)
672 free (insn_code_data[i]);
676 /* Return static insn data, allocate and setup if necessary. Although
677 dup_num is static data (it depends only on icode), to set it up we
678 need to extract insn first. So recog_data should be valid for
679 normal insn (ICODE >= 0) before the call. */
680 static struct lra_static_insn_data *
681 get_static_insn_data (int icode, int nop, int ndup, int nalt)
683 struct lra_static_insn_data *data;
686 lra_assert (icode < LAST_INSN_CODE);
687 if (icode >= 0 && (data = insn_code_data[icode]) != NULL)
689 lra_assert (nop >= 0 && ndup >= 0 && nalt >= 0);
690 n_bytes = sizeof (struct lra_static_insn_data)
691 + sizeof (struct lra_operand_data) * nop
692 + sizeof (int) * ndup;
693 data = XNEWVAR (struct lra_static_insn_data, n_bytes);
694 data->operand_alternative = NULL;
695 data->n_operands = nop;
697 data->n_alternatives = nalt;
698 data->operand = ((struct lra_operand_data *)
699 ((char *) data + sizeof (struct lra_static_insn_data)));
700 data->dup_num = ((int *) ((char *) data->operand
701 + sizeof (struct lra_operand_data) * nop));
706 insn_code_data[icode] = data;
707 for (i = 0; i < nop; i++)
709 data->operand[i].constraint
710 = insn_data[icode].operand[i].constraint;
711 data->operand[i].mode = insn_data[icode].operand[i].mode;
712 data->operand[i].strict_low = insn_data[icode].operand[i].strict_low;
713 data->operand[i].is_operator
714 = insn_data[icode].operand[i].is_operator;
715 data->operand[i].type
716 = (data->operand[i].constraint[0] == '=' ? OP_OUT
717 : data->operand[i].constraint[0] == '+' ? OP_INOUT
719 data->operand[i].is_address = false;
721 for (i = 0; i < ndup; i++)
722 data->dup_num[i] = recog_data.dup_num[i];
727 /* The current length of the following array. */
728 int lra_insn_recog_data_len;
730 /* Map INSN_UID -> the insn recog data (NULL if unknown). */
731 lra_insn_recog_data_t *lra_insn_recog_data;
733 /* Initialize LRA data about insns. */
735 init_insn_recog_data (void)
737 lra_insn_recog_data_len = 0;
738 lra_insn_recog_data = NULL;
742 /* Expand, if necessary, LRA data about insns. */
744 check_and_expand_insn_recog_data (int index)
748 if (lra_insn_recog_data_len > index)
750 old = lra_insn_recog_data_len;
751 lra_insn_recog_data_len = index * 3 / 2 + 1;
752 lra_insn_recog_data = XRESIZEVEC (lra_insn_recog_data_t,
754 lra_insn_recog_data_len);
755 for (i = old; i < lra_insn_recog_data_len; i++)
756 lra_insn_recog_data[i] = NULL;
759 /* Finish LRA DATA about insn. */
761 free_insn_recog_data (lra_insn_recog_data_t data)
763 if (data->operand_loc != NULL)
764 free (data->operand_loc);
765 if (data->dup_loc != NULL)
766 free (data->dup_loc);
767 if (data->arg_hard_regs != NULL)
768 free (data->arg_hard_regs);
769 if (data->icode < 0 && NONDEBUG_INSN_P (data->insn))
771 if (data->insn_static_data->operand_alternative != NULL)
772 free (const_cast <operand_alternative *>
773 (data->insn_static_data->operand_alternative));
774 free_insn_regs (data->insn_static_data->hard_regs);
775 free (data->insn_static_data);
777 free_insn_regs (data->regs);
782 /* Finish LRA data about all insns. */
784 finish_insn_recog_data (void)
787 lra_insn_recog_data_t data;
789 for (i = 0; i < lra_insn_recog_data_len; i++)
790 if ((data = lra_insn_recog_data[i]) != NULL)
791 free_insn_recog_data (data);
793 free (lra_insn_recog_data);
796 /* Setup info about operands in alternatives of LRA DATA of insn. */
798 setup_operand_alternative (lra_insn_recog_data_t data,
799 const operand_alternative *op_alt)
802 int icode = data->icode;
803 struct lra_static_insn_data *static_data = data->insn_static_data;
805 static_data->commutative = -1;
806 nop = static_data->n_operands;
807 nalt = static_data->n_alternatives;
808 static_data->operand_alternative = op_alt;
809 for (i = 0; i < nop; i++)
811 static_data->operand[i].early_clobber = false;
812 static_data->operand[i].is_address = false;
813 if (static_data->operand[i].constraint[0] == '%')
815 /* We currently only support one commutative pair of operands. */
816 if (static_data->commutative < 0)
817 static_data->commutative = i;
819 lra_assert (icode < 0); /* Asm */
820 /* The last operand should not be marked commutative. */
821 lra_assert (i != nop - 1);
824 for (j = 0; j < nalt; j++)
825 for (i = 0; i < nop; i++, op_alt++)
827 static_data->operand[i].early_clobber |= op_alt->earlyclobber;
828 static_data->operand[i].is_address |= op_alt->is_address;
832 /* Recursively process X and collect info about registers, which are
833 not the insn operands, in X with TYPE (in/out/inout) and flag that
834 it is early clobbered in the insn (EARLY_CLOBBER) and add the info
835 to LIST. X is a part of insn given by DATA. Return the result
837 static struct lra_insn_reg *
838 collect_non_operand_hard_regs (rtx *x, lra_insn_recog_data_t data,
839 struct lra_insn_reg *list,
840 enum op_type type, bool early_clobber)
842 int i, j, regno, last;
845 struct lra_insn_reg *curr;
847 enum rtx_code code = GET_CODE (op);
848 const char *fmt = GET_RTX_FORMAT (code);
850 for (i = 0; i < data->insn_static_data->n_operands; i++)
851 if (x == data->operand_loc[i])
852 /* It is an operand loc. Stop here. */
854 for (i = 0; i < data->insn_static_data->n_dups; i++)
855 if (x == data->dup_loc[i])
856 /* It is a dup loc. Stop here. */
858 mode = GET_MODE (op);
862 op = SUBREG_REG (op);
863 code = GET_CODE (op);
864 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (op)))
866 mode = GET_MODE (op);
867 if (GET_MODE_SIZE (mode) > REGMODE_NATURAL_SIZE (mode))
873 if ((regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER)
875 /* Process all regs even unallocatable ones as we need info
876 about all regs for rematerialization pass. */
877 for (last = regno + hard_regno_nregs[regno][mode];
881 for (curr = list; curr != NULL; curr = curr->next)
882 if (curr->regno == regno && curr->subreg_p == subreg_p
883 && curr->biggest_mode == mode)
885 if (curr->type != type)
886 curr->type = OP_INOUT;
887 if (curr->early_clobber != early_clobber)
888 curr->early_clobber = true;
893 /* This is a new hard regno or the info can not be
894 integrated into the found structure. */
898 /* This clobber is to inform popping floating
900 && ! (FIRST_STACK_REG <= regno
901 && regno <= LAST_STACK_REG));
903 list = new_insn_reg (data->insn, regno, type, mode, subreg_p,
904 early_clobber, list);
912 list = collect_non_operand_hard_regs (&SET_DEST (op), data,
913 list, OP_OUT, false);
914 list = collect_non_operand_hard_regs (&SET_SRC (op), data,
918 /* We treat clobber of non-operand hard registers as early
919 clobber (the behavior is expected from asm). */
920 list = collect_non_operand_hard_regs (&XEXP (op, 0), data,
923 case PRE_INC: case PRE_DEC: case POST_INC: case POST_DEC:
924 list = collect_non_operand_hard_regs (&XEXP (op, 0), data,
925 list, OP_INOUT, false);
927 case PRE_MODIFY: case POST_MODIFY:
928 list = collect_non_operand_hard_regs (&XEXP (op, 0), data,
929 list, OP_INOUT, false);
930 list = collect_non_operand_hard_regs (&XEXP (op, 1), data,
934 fmt = GET_RTX_FORMAT (code);
935 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
938 list = collect_non_operand_hard_regs (&XEXP (op, i), data,
940 else if (fmt[i] == 'E')
941 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
942 list = collect_non_operand_hard_regs (&XVECEXP (op, i, j), data,
949 /* Set up and return info about INSN. Set up the info if it is not set up
951 lra_insn_recog_data_t
952 lra_set_insn_recog_data (rtx_insn *insn)
954 lra_insn_recog_data_t data;
957 unsigned int uid = INSN_UID (insn);
958 struct lra_static_insn_data *insn_static_data;
960 check_and_expand_insn_recog_data (uid);
961 if (DEBUG_INSN_P (insn))
965 icode = INSN_CODE (insn);
967 /* It might be a new simple insn which is not recognized yet. */
968 INSN_CODE (insn) = icode = recog_memoized (insn);
970 data = XNEW (struct lra_insn_recog_data);
971 lra_insn_recog_data[uid] = data;
973 data->used_insn_alternative = -1;
976 if (DEBUG_INSN_P (insn))
978 data->insn_static_data = &debug_insn_static_data;
979 data->dup_loc = NULL;
980 data->arg_hard_regs = NULL;
981 data->preferred_alternatives = ALL_ALTERNATIVES;
982 data->operand_loc = XNEWVEC (rtx *, 1);
983 data->operand_loc[0] = &INSN_VAR_LOCATION_LOC (insn);
989 machine_mode operand_mode[MAX_RECOG_OPERANDS];
990 const char *constraints[MAX_RECOG_OPERANDS];
992 nop = asm_noperands (PATTERN (insn));
993 data->operand_loc = data->dup_loc = NULL;
997 /* It is a special insn like USE or CLOBBER. We should
998 recognize any regular insn otherwise LRA can do nothing
1000 gcc_assert (GET_CODE (PATTERN (insn)) == USE
1001 || GET_CODE (PATTERN (insn)) == CLOBBER
1002 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
1003 data->insn_static_data = insn_static_data
1004 = get_static_insn_data (-1, 0, 0, nalt);
1008 /* expand_asm_operands makes sure there aren't too many
1010 lra_assert (nop <= MAX_RECOG_OPERANDS);
1012 data->operand_loc = XNEWVEC (rtx *, nop);
1013 /* Now get the operand values and constraints out of the
1015 decode_asm_operands (PATTERN (insn), NULL,
1017 constraints, operand_mode, NULL);
1020 const char *p = recog_data.constraints[0];
1022 for (p = constraints[0]; *p; p++)
1025 data->insn_static_data = insn_static_data
1026 = get_static_insn_data (-1, nop, 0, nalt);
1027 for (i = 0; i < nop; i++)
1029 insn_static_data->operand[i].mode = operand_mode[i];
1030 insn_static_data->operand[i].constraint = constraints[i];
1031 insn_static_data->operand[i].strict_low = false;
1032 insn_static_data->operand[i].is_operator = false;
1033 insn_static_data->operand[i].is_address = false;
1036 for (i = 0; i < insn_static_data->n_operands; i++)
1037 insn_static_data->operand[i].type
1038 = (insn_static_data->operand[i].constraint[0] == '=' ? OP_OUT
1039 : insn_static_data->operand[i].constraint[0] == '+' ? OP_INOUT
1041 data->preferred_alternatives = ALL_ALTERNATIVES;
1044 operand_alternative *op_alt = XCNEWVEC (operand_alternative,
1046 preprocess_constraints (nop, nalt, constraints, op_alt);
1047 setup_operand_alternative (data, op_alt);
1052 insn_extract (insn);
1053 data->insn_static_data = insn_static_data
1054 = get_static_insn_data (icode, insn_data[icode].n_operands,
1055 insn_data[icode].n_dups,
1056 insn_data[icode].n_alternatives);
1057 n = insn_static_data->n_operands;
1062 locs = XNEWVEC (rtx *, n);
1063 memcpy (locs, recog_data.operand_loc, n * sizeof (rtx *));
1065 data->operand_loc = locs;
1066 n = insn_static_data->n_dups;
1071 locs = XNEWVEC (rtx *, n);
1072 memcpy (locs, recog_data.dup_loc, n * sizeof (rtx *));
1074 data->dup_loc = locs;
1075 data->preferred_alternatives = get_preferred_alternatives (insn);
1076 const operand_alternative *op_alt = preprocess_insn_constraints (icode);
1077 if (!insn_static_data->operand_alternative)
1078 setup_operand_alternative (data, op_alt);
1079 else if (op_alt != insn_static_data->operand_alternative)
1080 insn_static_data->operand_alternative = op_alt;
1082 if (GET_CODE (PATTERN (insn)) == CLOBBER || GET_CODE (PATTERN (insn)) == USE)
1083 insn_static_data->hard_regs = NULL;
1085 insn_static_data->hard_regs
1086 = collect_non_operand_hard_regs (&PATTERN (insn), data,
1087 NULL, OP_IN, false);
1088 data->arg_hard_regs = NULL;
1093 int n_hard_regs, regno, arg_hard_regs[FIRST_PSEUDO_REGISTER];
1096 /* Finding implicit hard register usage. We believe it will be
1097 not changed whatever transformations are used. Call insns
1098 are such example. */
1099 for (link = CALL_INSN_FUNCTION_USAGE (insn);
1101 link = XEXP (link, 1))
1102 if (((use_p = GET_CODE (XEXP (link, 0)) == USE)
1103 || GET_CODE (XEXP (link, 0)) == CLOBBER)
1104 && REG_P (XEXP (XEXP (link, 0), 0)))
1106 regno = REGNO (XEXP (XEXP (link, 0), 0));
1107 lra_assert (regno < FIRST_PSEUDO_REGISTER);
1108 /* It is an argument register. */
1109 for (i = (hard_regno_nregs
1110 [regno][GET_MODE (XEXP (XEXP (link, 0), 0))]) - 1;
1113 arg_hard_regs[n_hard_regs++]
1114 = regno + i + (use_p ? 0 : FIRST_PSEUDO_REGISTER);
1116 if (n_hard_regs != 0)
1118 arg_hard_regs[n_hard_regs++] = -1;
1119 data->arg_hard_regs = XNEWVEC (int, n_hard_regs);
1120 memcpy (data->arg_hard_regs, arg_hard_regs,
1121 sizeof (int) * n_hard_regs);
1124 /* Some output operand can be recognized only from the context not
1125 from the constraints which are empty in this case. Call insn may
1126 contain a hard register in set destination with empty constraint
1127 and extract_insn treats them as an input. */
1128 for (i = 0; i < insn_static_data->n_operands; i++)
1132 struct lra_operand_data *operand = &insn_static_data->operand[i];
1134 /* ??? Should we treat 'X' the same way. It looks to me that
1135 'X' means anything and empty constraint means we do not
1137 if (operand->type != OP_IN || *operand->constraint != '\0'
1138 || operand->is_operator)
1140 pat = PATTERN (insn);
1141 if (GET_CODE (pat) == SET)
1143 if (data->operand_loc[i] != &SET_DEST (pat))
1146 else if (GET_CODE (pat) == PARALLEL)
1148 for (j = XVECLEN (pat, 0) - 1; j >= 0; j--)
1150 set = XVECEXP (PATTERN (insn), 0, j);
1151 if (GET_CODE (set) == SET
1152 && &SET_DEST (set) == data->operand_loc[i])
1160 operand->type = OP_OUT;
1165 /* Return info about insn give by UID. The info should be already set
1167 static lra_insn_recog_data_t
1168 get_insn_recog_data_by_uid (int uid)
1170 lra_insn_recog_data_t data;
1172 data = lra_insn_recog_data[uid];
1173 lra_assert (data != NULL);
1177 /* Invalidate all info about insn given by its UID. */
1179 invalidate_insn_recog_data (int uid)
1181 lra_insn_recog_data_t data;
1183 data = lra_insn_recog_data[uid];
1184 lra_assert (data != NULL);
1185 free_insn_recog_data (data);
1186 lra_insn_recog_data[uid] = NULL;
1189 /* Update all the insn info about INSN. It is usually called when
1190 something in the insn was changed. Return the updated info. */
1191 lra_insn_recog_data_t
1192 lra_update_insn_recog_data (rtx_insn *insn)
1194 lra_insn_recog_data_t data;
1196 unsigned int uid = INSN_UID (insn);
1197 struct lra_static_insn_data *insn_static_data;
1198 HOST_WIDE_INT sp_offset = 0;
1200 check_and_expand_insn_recog_data (uid);
1201 if ((data = lra_insn_recog_data[uid]) != NULL
1202 && data->icode != INSN_CODE (insn))
1204 sp_offset = data->sp_offset;
1205 invalidate_insn_data_regno_info (data, insn, get_insn_freq (insn));
1206 invalidate_insn_recog_data (uid);
1211 data = lra_get_insn_recog_data (insn);
1212 /* Initiate or restore SP offset. */
1213 data->sp_offset = sp_offset;
1216 insn_static_data = data->insn_static_data;
1217 data->used_insn_alternative = -1;
1218 if (DEBUG_INSN_P (insn))
1220 if (data->icode < 0)
1223 machine_mode operand_mode[MAX_RECOG_OPERANDS];
1224 const char *constraints[MAX_RECOG_OPERANDS];
1226 nop = asm_noperands (PATTERN (insn));
1229 lra_assert (nop == data->insn_static_data->n_operands);
1230 /* Now get the operand values and constraints out of the
1232 decode_asm_operands (PATTERN (insn), NULL,
1234 constraints, operand_mode, NULL);
1235 #ifdef ENABLE_CHECKING
1239 for (i = 0; i < nop; i++)
1241 (insn_static_data->operand[i].mode == operand_mode[i]
1242 && insn_static_data->operand[i].constraint == constraints[i]
1243 && ! insn_static_data->operand[i].is_operator);
1247 #ifdef ENABLE_CHECKING
1251 for (i = 0; i < insn_static_data->n_operands; i++)
1253 (insn_static_data->operand[i].type
1254 == (insn_static_data->operand[i].constraint[0] == '=' ? OP_OUT
1255 : insn_static_data->operand[i].constraint[0] == '+' ? OP_INOUT
1262 insn_extract (insn);
1263 n = insn_static_data->n_operands;
1265 memcpy (data->operand_loc, recog_data.operand_loc, n * sizeof (rtx *));
1266 n = insn_static_data->n_dups;
1268 memcpy (data->dup_loc, recog_data.dup_loc, n * sizeof (rtx *));
1269 lra_assert (check_bool_attrs (insn));
1274 /* Set up that INSN is using alternative ALT now. */
1276 lra_set_used_insn_alternative (rtx_insn *insn, int alt)
1278 lra_insn_recog_data_t data;
1280 data = lra_get_insn_recog_data (insn);
1281 data->used_insn_alternative = alt;
1284 /* Set up that insn with UID is using alternative ALT now. The insn
1285 info should be already set up. */
1287 lra_set_used_insn_alternative_by_uid (int uid, int alt)
1289 lra_insn_recog_data_t data;
1291 check_and_expand_insn_recog_data (uid);
1292 data = lra_insn_recog_data[uid];
1293 lra_assert (data != NULL);
1294 data->used_insn_alternative = alt;
1299 /* This page contains code dealing with common register info and
1302 /* The size of the following array. */
1303 static int reg_info_size;
1304 /* Common info about each register. */
1305 struct lra_reg *lra_reg_info;
1307 /* Last register value. */
1308 static int last_reg_value;
1310 /* Return new register value. */
1312 get_new_reg_value (void)
1314 return ++last_reg_value;
1317 /* Pools for copies. */
1318 static alloc_pool copy_pool;
1320 /* Vec referring to pseudo copies. */
1321 static vec<lra_copy_t> copy_vec;
1323 /* Initialize I-th element of lra_reg_info. */
1325 initialize_lra_reg_info_element (int i)
1327 bitmap_initialize (&lra_reg_info[i].insn_bitmap, ®_obstack);
1329 lra_reg_info[i].no_stack_p = false;
1331 CLEAR_HARD_REG_SET (lra_reg_info[i].conflict_hard_regs);
1332 CLEAR_HARD_REG_SET (lra_reg_info[i].actual_call_used_reg_set);
1333 lra_reg_info[i].preferred_hard_regno1 = -1;
1334 lra_reg_info[i].preferred_hard_regno2 = -1;
1335 lra_reg_info[i].preferred_hard_regno_profit1 = 0;
1336 lra_reg_info[i].preferred_hard_regno_profit2 = 0;
1337 lra_reg_info[i].biggest_mode = VOIDmode;
1338 lra_reg_info[i].live_ranges = NULL;
1339 lra_reg_info[i].nrefs = lra_reg_info[i].freq = 0;
1340 lra_reg_info[i].last_reload = 0;
1341 lra_reg_info[i].restore_regno = -1;
1342 lra_reg_info[i].val = get_new_reg_value ();
1343 lra_reg_info[i].offset = 0;
1344 lra_reg_info[i].copies = NULL;
1347 /* Initialize common reg info and copies. */
1349 init_reg_info (void)
1354 reg_info_size = max_reg_num () * 3 / 2 + 1;
1355 lra_reg_info = XNEWVEC (struct lra_reg, reg_info_size);
1356 for (i = 0; i < reg_info_size; i++)
1357 initialize_lra_reg_info_element (i);
1359 = create_alloc_pool ("lra copies", sizeof (struct lra_copy), 100);
1360 copy_vec.create (100);
1364 /* Finish common reg info and copies. */
1366 finish_reg_info (void)
1370 for (i = 0; i < reg_info_size; i++)
1371 bitmap_clear (&lra_reg_info[i].insn_bitmap);
1372 free (lra_reg_info);
1374 free_alloc_pool (copy_pool);
1375 copy_vec.release ();
1378 /* Expand common reg info if it is necessary. */
1380 expand_reg_info (void)
1382 int i, old = reg_info_size;
1384 if (reg_info_size > max_reg_num ())
1386 reg_info_size = max_reg_num () * 3 / 2 + 1;
1387 lra_reg_info = XRESIZEVEC (struct lra_reg, lra_reg_info, reg_info_size);
1388 for (i = old; i < reg_info_size; i++)
1389 initialize_lra_reg_info_element (i);
1392 /* Free all copies. */
1394 lra_free_copies (void)
1398 while (copy_vec.length () != 0)
1400 cp = copy_vec.pop ();
1401 lra_reg_info[cp->regno1].copies = lra_reg_info[cp->regno2].copies = NULL;
1402 pool_free (copy_pool, cp);
1406 /* Create copy of two pseudos REGNO1 and REGNO2. The copy execution
1407 frequency is FREQ. */
1409 lra_create_copy (int regno1, int regno2, int freq)
1414 lra_assert (regno1 != regno2);
1415 regno1_dest_p = true;
1416 if (regno1 > regno2)
1420 regno1_dest_p = false;
1424 cp = (lra_copy_t) pool_alloc (copy_pool);
1425 copy_vec.safe_push (cp);
1426 cp->regno1_dest_p = regno1_dest_p;
1428 cp->regno1 = regno1;
1429 cp->regno2 = regno2;
1430 cp->regno1_next = lra_reg_info[regno1].copies;
1431 lra_reg_info[regno1].copies = cp;
1432 cp->regno2_next = lra_reg_info[regno2].copies;
1433 lra_reg_info[regno2].copies = cp;
1434 if (lra_dump_file != NULL)
1435 fprintf (lra_dump_file, " Creating copy r%d%sr%d@%d\n",
1436 regno1, regno1_dest_p ? "<-" : "->", regno2, freq);
1439 /* Return N-th (0, 1, ...) copy. If there is no copy, return
1442 lra_get_copy (int n)
1444 if (n >= (int) copy_vec.length ())
1451 /* This page contains code dealing with info about registers in
1454 /* Process X of insn UID recursively and add info (operand type is
1455 given by TYPE, flag of that it is early clobber is EARLY_CLOBBER)
1456 about registers in X to the insn DATA. */
1458 add_regs_to_insn_regno_info (lra_insn_recog_data_t data, rtx x, int uid,
1459 enum op_type type, bool early_clobber)
1466 struct lra_insn_reg *curr;
1468 code = GET_CODE (x);
1469 mode = GET_MODE (x);
1471 if (GET_CODE (x) == SUBREG)
1474 code = GET_CODE (x);
1475 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x)))
1477 mode = GET_MODE (x);
1478 if (GET_MODE_SIZE (mode) > REGMODE_NATURAL_SIZE (mode))
1485 /* Process all regs even unallocatable ones as we need info about
1486 all regs for rematerialization pass. */
1488 if (bitmap_set_bit (&lra_reg_info[regno].insn_bitmap, uid))
1490 data->regs = new_insn_reg (data->insn, regno, type, mode, subreg_p,
1491 early_clobber, data->regs);
1496 for (curr = data->regs; curr != NULL; curr = curr->next)
1497 if (curr->regno == regno)
1499 if (curr->subreg_p != subreg_p || curr->biggest_mode != mode)
1500 /* The info can not be integrated into the found
1502 data->regs = new_insn_reg (data->insn, regno, type, mode,
1503 subreg_p, early_clobber,
1507 if (curr->type != type)
1508 curr->type = OP_INOUT;
1509 if (curr->early_clobber != early_clobber)
1510 curr->early_clobber = true;
1521 add_regs_to_insn_regno_info (data, SET_DEST (x), uid, OP_OUT, false);
1522 add_regs_to_insn_regno_info (data, SET_SRC (x), uid, OP_IN, false);
1525 /* We treat clobber of non-operand hard registers as early
1526 clobber (the behavior is expected from asm). */
1527 add_regs_to_insn_regno_info (data, XEXP (x, 0), uid, OP_OUT, true);
1529 case PRE_INC: case PRE_DEC: case POST_INC: case POST_DEC:
1530 add_regs_to_insn_regno_info (data, XEXP (x, 0), uid, OP_INOUT, false);
1532 case PRE_MODIFY: case POST_MODIFY:
1533 add_regs_to_insn_regno_info (data, XEXP (x, 0), uid, OP_INOUT, false);
1534 add_regs_to_insn_regno_info (data, XEXP (x, 1), uid, OP_IN, false);
1537 if ((code != PARALLEL && code != EXPR_LIST) || type != OP_OUT)
1538 /* Some targets place small structures in registers for return
1539 values of functions, and those registers are wrapped in
1540 PARALLEL that we may see as the destination of a SET. Here
1543 (call_insn 13 12 14 2 (set (parallel:BLK [
1544 (expr_list:REG_DEP_TRUE (reg:DI 0 ax)
1546 (expr_list:REG_DEP_TRUE (reg:DI 1 dx)
1547 (const_int 8 [0x8]))
1549 (call (mem:QI (symbol_ref:DI (... */
1551 fmt = GET_RTX_FORMAT (code);
1552 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1555 add_regs_to_insn_regno_info (data, XEXP (x, i), uid, type, false);
1556 else if (fmt[i] == 'E')
1558 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1559 add_regs_to_insn_regno_info (data, XVECEXP (x, i, j), uid,
1566 /* Return execution frequency of INSN. */
1568 get_insn_freq (rtx_insn *insn)
1570 basic_block bb = BLOCK_FOR_INSN (insn);
1572 gcc_checking_assert (bb != NULL);
1573 return REG_FREQ_FROM_BB (bb);
1576 /* Invalidate all reg info of INSN with DATA and execution frequency
1577 FREQ. Update common info about the invalidated registers. */
1579 invalidate_insn_data_regno_info (lra_insn_recog_data_t data, rtx_insn *insn,
1585 struct lra_insn_reg *ir, *next_ir;
1587 uid = INSN_UID (insn);
1588 debug_p = DEBUG_INSN_P (insn);
1589 for (ir = data->regs; ir != NULL; ir = next_ir)
1594 bitmap_clear_bit (&lra_reg_info[i].insn_bitmap, uid);
1595 if (i >= FIRST_PSEUDO_REGISTER && ! debug_p)
1597 lra_reg_info[i].nrefs--;
1598 lra_reg_info[i].freq -= freq;
1599 lra_assert (lra_reg_info[i].nrefs >= 0 && lra_reg_info[i].freq >= 0);
1605 /* Invalidate all reg info of INSN. Update common info about the
1606 invalidated registers. */
1608 lra_invalidate_insn_regno_info (rtx_insn *insn)
1610 invalidate_insn_data_regno_info (lra_get_insn_recog_data (insn), insn,
1611 get_insn_freq (insn));
1614 /* Update common reg info from reg info of insn given by its DATA and
1615 execution frequency FREQ. */
1617 setup_insn_reg_info (lra_insn_recog_data_t data, int freq)
1620 struct lra_insn_reg *ir;
1622 for (ir = data->regs; ir != NULL; ir = ir->next)
1623 if ((i = ir->regno) >= FIRST_PSEUDO_REGISTER)
1625 lra_reg_info[i].nrefs++;
1626 lra_reg_info[i].freq += freq;
1630 /* Set up insn reg info of INSN. Update common reg info from reg info
1633 lra_update_insn_regno_info (rtx_insn *insn)
1636 lra_insn_recog_data_t data;
1637 struct lra_static_insn_data *static_data;
1641 if (! INSN_P (insn))
1643 data = lra_get_insn_recog_data (insn);
1644 static_data = data->insn_static_data;
1645 freq = get_insn_freq (insn);
1646 invalidate_insn_data_regno_info (data, insn, freq);
1647 uid = INSN_UID (insn);
1648 for (i = static_data->n_operands - 1; i >= 0; i--)
1649 add_regs_to_insn_regno_info (data, *data->operand_loc[i], uid,
1650 static_data->operand[i].type,
1651 static_data->operand[i].early_clobber);
1652 if ((code = GET_CODE (PATTERN (insn))) == CLOBBER || code == USE)
1653 add_regs_to_insn_regno_info (data, XEXP (PATTERN (insn), 0), uid,
1654 code == USE ? OP_IN : OP_OUT, false);
1656 /* On some targets call insns can refer to pseudos in memory in
1657 CALL_INSN_FUNCTION_USAGE list. Process them in order to
1658 consider their occurrences in calls for different
1659 transformations (e.g. inheritance) with given pseudos. */
1660 for (link = CALL_INSN_FUNCTION_USAGE (insn);
1662 link = XEXP (link, 1))
1663 if (((code = GET_CODE (XEXP (link, 0))) == USE || code == CLOBBER)
1664 && MEM_P (XEXP (XEXP (link, 0), 0)))
1665 add_regs_to_insn_regno_info (data, XEXP (XEXP (link, 0), 0), uid,
1666 code == USE ? OP_IN : OP_OUT, false);
1667 if (NONDEBUG_INSN_P (insn))
1668 setup_insn_reg_info (data, freq);
1671 /* Return reg info of insn given by it UID. */
1672 struct lra_insn_reg *
1673 lra_get_insn_regs (int uid)
1675 lra_insn_recog_data_t data;
1677 data = get_insn_recog_data_by_uid (uid);
1683 /* This page contains code dealing with stack of the insns which
1684 should be processed by the next constraint pass. */
1686 /* Bitmap used to put an insn on the stack only in one exemplar. */
1687 static sbitmap lra_constraint_insn_stack_bitmap;
1689 /* The stack itself. */
1690 vec<rtx_insn *> lra_constraint_insn_stack;
1692 /* Put INSN on the stack. If ALWAYS_UPDATE is true, always update the reg
1693 info for INSN, otherwise only update it if INSN is not already on the
1696 lra_push_insn_1 (rtx_insn *insn, bool always_update)
1698 unsigned int uid = INSN_UID (insn);
1700 lra_update_insn_regno_info (insn);
1701 if (uid >= SBITMAP_SIZE (lra_constraint_insn_stack_bitmap))
1702 lra_constraint_insn_stack_bitmap =
1703 sbitmap_resize (lra_constraint_insn_stack_bitmap, 3 * uid / 2, 0);
1704 if (bitmap_bit_p (lra_constraint_insn_stack_bitmap, uid))
1706 bitmap_set_bit (lra_constraint_insn_stack_bitmap, uid);
1707 if (! always_update)
1708 lra_update_insn_regno_info (insn);
1709 lra_constraint_insn_stack.safe_push (insn);
1712 /* Put INSN on the stack. */
1714 lra_push_insn (rtx_insn *insn)
1716 lra_push_insn_1 (insn, false);
1719 /* Put INSN on the stack and update its reg info. */
1721 lra_push_insn_and_update_insn_regno_info (rtx_insn *insn)
1723 lra_push_insn_1 (insn, true);
1726 /* Put insn with UID on the stack. */
1728 lra_push_insn_by_uid (unsigned int uid)
1730 lra_push_insn (lra_insn_recog_data[uid]->insn);
1733 /* Take the last-inserted insns off the stack and return it. */
1737 rtx_insn *insn = lra_constraint_insn_stack.pop ();
1738 bitmap_clear_bit (lra_constraint_insn_stack_bitmap, INSN_UID (insn));
1742 /* Return the current size of the insn stack. */
1744 lra_insn_stack_length (void)
1746 return lra_constraint_insn_stack.length ();
1749 /* Push insns FROM to TO (excluding it) going in reverse order. */
1751 push_insns (rtx_insn *from, rtx_insn *to)
1755 if (from == NULL_RTX)
1757 for (insn = from; insn != to; insn = PREV_INSN (insn))
1759 lra_push_insn (insn);
1762 /* Set up sp offset for insn in range [FROM, LAST]. The offset is
1763 taken from the next BB insn after LAST or zero if there in such
1766 setup_sp_offset (rtx_insn *from, rtx_insn *last)
1768 rtx_insn *before = next_nonnote_insn_bb (last);
1769 HOST_WIDE_INT offset = (before == NULL_RTX || ! INSN_P (before)
1770 ? 0 : lra_get_insn_recog_data (before)->sp_offset);
1772 for (rtx_insn *insn = from; insn != NEXT_INSN (last); insn = NEXT_INSN (insn))
1773 lra_get_insn_recog_data (insn)->sp_offset = offset;
1776 /* Emit insns BEFORE before INSN and insns AFTER after INSN. Put the
1777 insns onto the stack. Print about emitting the insns with
1780 lra_process_new_insns (rtx_insn *insn, rtx_insn *before, rtx_insn *after,
1785 if (before == NULL_RTX && after == NULL_RTX)
1787 if (lra_dump_file != NULL)
1789 dump_insn_slim (lra_dump_file, insn);
1790 if (before != NULL_RTX)
1792 fprintf (lra_dump_file," %s before:\n", title);
1793 dump_rtl_slim (lra_dump_file, before, NULL, -1, 0);
1795 if (after != NULL_RTX)
1797 fprintf (lra_dump_file, " %s after:\n", title);
1798 dump_rtl_slim (lra_dump_file, after, NULL, -1, 0);
1800 fprintf (lra_dump_file, "\n");
1802 if (before != NULL_RTX)
1804 emit_insn_before (before, insn);
1805 push_insns (PREV_INSN (insn), PREV_INSN (before));
1806 setup_sp_offset (before, PREV_INSN (insn));
1808 if (after != NULL_RTX)
1810 for (last = after; NEXT_INSN (last) != NULL_RTX; last = NEXT_INSN (last))
1812 emit_insn_after (after, insn);
1813 push_insns (last, insn);
1814 setup_sp_offset (after, last);
1820 /* Replace all references to register OLD_REGNO in *LOC with pseudo
1821 register NEW_REG. Try to simplify subreg of constant if SUBREG_P.
1822 Return true if any change was made. */
1824 lra_substitute_pseudo (rtx *loc, int old_regno, rtx new_reg, bool subreg_p)
1827 bool result = false;
1835 code = GET_CODE (x);
1836 if (code == SUBREG && subreg_p)
1838 rtx subst, inner = SUBREG_REG (x);
1839 /* Transform subreg of constant while we still have inner mode
1840 of the subreg. The subreg internal should not be an insn
1842 if (REG_P (inner) && (int) REGNO (inner) == old_regno
1843 && CONSTANT_P (new_reg)
1844 && (subst = simplify_subreg (GET_MODE (x), new_reg, GET_MODE (inner),
1845 SUBREG_BYTE (x))) != NULL_RTX)
1852 else if (code == REG && (int) REGNO (x) == old_regno)
1854 machine_mode mode = GET_MODE (x);
1855 machine_mode inner_mode = GET_MODE (new_reg);
1857 if (mode != inner_mode
1858 && ! (CONST_INT_P (new_reg) && SCALAR_INT_MODE_P (mode)))
1860 if (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (inner_mode)
1861 || ! SCALAR_INT_MODE_P (inner_mode))
1862 new_reg = gen_rtx_SUBREG (mode, new_reg, 0);
1864 new_reg = gen_lowpart_SUBREG (mode, new_reg);
1870 /* Scan all the operand sub-expressions. */
1871 fmt = GET_RTX_FORMAT (code);
1872 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1876 if (lra_substitute_pseudo (&XEXP (x, i), old_regno,
1880 else if (fmt[i] == 'E')
1882 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1883 if (lra_substitute_pseudo (&XVECEXP (x, i, j), old_regno,
1891 /* Call lra_substitute_pseudo within an insn. Try to simplify subreg
1892 of constant if SUBREG_P. This won't update the insn ptr, just the
1893 contents of the insn. */
1895 lra_substitute_pseudo_within_insn (rtx_insn *insn, int old_regno,
1896 rtx new_reg, bool subreg_p)
1899 return lra_substitute_pseudo (&loc, old_regno, new_reg, subreg_p);
1904 /* This page contains code dealing with scratches (changing them onto
1905 pseudos and restoring them from the pseudos).
1907 We change scratches into pseudos at the beginning of LRA to
1908 simplify dealing with them (conflicts, hard register assignments).
1910 If the pseudo denoting scratch was spilled it means that we do need
1911 a hard register for it. Such pseudos are transformed back to
1912 scratches at the end of LRA. */
1914 /* Description of location of a former scratch operand. */
1917 rtx_insn *insn; /* Insn where the scratch was. */
1918 int nop; /* Number of the operand which was a scratch. */
1921 typedef struct sloc *sloc_t;
1923 /* Locations of the former scratches. */
1924 static vec<sloc_t> scratches;
1926 /* Bitmap of scratch regnos. */
1927 static bitmap_head scratch_bitmap;
1929 /* Bitmap of scratch operands. */
1930 static bitmap_head scratch_operand_bitmap;
1932 /* Return true if pseudo REGNO is made of SCRATCH. */
1934 lra_former_scratch_p (int regno)
1936 return bitmap_bit_p (&scratch_bitmap, regno);
1939 /* Return true if the operand NOP of INSN is a former scratch. */
1941 lra_former_scratch_operand_p (rtx_insn *insn, int nop)
1943 return bitmap_bit_p (&scratch_operand_bitmap,
1944 INSN_UID (insn) * MAX_RECOG_OPERANDS + nop) != 0;
1947 /* Register operand NOP in INSN as a former scratch. It will be
1948 changed to scratch back, if it is necessary, at the LRA end. */
1950 lra_register_new_scratch_op (rtx_insn *insn, int nop)
1952 lra_insn_recog_data_t id = lra_get_insn_recog_data (insn);
1953 rtx op = *id->operand_loc[nop];
1954 sloc_t loc = XNEW (struct sloc);
1955 lra_assert (REG_P (op));
1958 scratches.safe_push (loc);
1959 bitmap_set_bit (&scratch_bitmap, REGNO (op));
1960 bitmap_set_bit (&scratch_operand_bitmap,
1961 INSN_UID (insn) * MAX_RECOG_OPERANDS + nop);
1962 add_reg_note (insn, REG_UNUSED, op);
1965 /* Change scratches onto pseudos and save their location. */
1967 remove_scratches (void)
1970 bool insn_changed_p;
1974 lra_insn_recog_data_t id;
1975 struct lra_static_insn_data *static_id;
1977 scratches.create (get_max_uid ());
1978 bitmap_initialize (&scratch_bitmap, ®_obstack);
1979 bitmap_initialize (&scratch_operand_bitmap, ®_obstack);
1980 FOR_EACH_BB_FN (bb, cfun)
1981 FOR_BB_INSNS (bb, insn)
1984 id = lra_get_insn_recog_data (insn);
1985 static_id = id->insn_static_data;
1986 insn_changed_p = false;
1987 for (i = 0; i < static_id->n_operands; i++)
1988 if (GET_CODE (*id->operand_loc[i]) == SCRATCH
1989 && GET_MODE (*id->operand_loc[i]) != VOIDmode)
1991 insn_changed_p = true;
1992 *id->operand_loc[i] = reg
1993 = lra_create_new_reg (static_id->operand[i].mode,
1994 *id->operand_loc[i], ALL_REGS, NULL);
1995 lra_register_new_scratch_op (insn, i);
1996 if (lra_dump_file != NULL)
1997 fprintf (lra_dump_file,
1998 "Removing SCRATCH in insn #%u (nop %d)\n",
1999 INSN_UID (insn), i);
2002 /* Because we might use DF right after caller-saves sub-pass
2003 we need to keep DF info up to date. */
2004 df_insn_rescan (insn);
2008 /* Changes pseudos created by function remove_scratches onto scratches. */
2010 restore_scratches (void)
2015 rtx_insn *last = NULL;
2016 lra_insn_recog_data_t id = NULL;
2018 for (i = 0; scratches.iterate (i, &loc); i++)
2020 if (last != loc->insn)
2023 id = lra_get_insn_recog_data (last);
2025 if (REG_P (*id->operand_loc[loc->nop])
2026 && ((regno = REGNO (*id->operand_loc[loc->nop]))
2027 >= FIRST_PSEUDO_REGISTER)
2028 && lra_get_regno_hard_regno (regno) < 0)
2030 /* It should be only case when scratch register with chosen
2031 constraint 'X' did not get memory or hard register. */
2032 lra_assert (lra_former_scratch_p (regno));
2033 *id->operand_loc[loc->nop]
2034 = gen_rtx_SCRATCH (GET_MODE (*id->operand_loc[loc->nop]));
2035 lra_update_dup (id, loc->nop);
2036 if (lra_dump_file != NULL)
2037 fprintf (lra_dump_file, "Restoring SCRATCH in insn #%u(nop %d)\n",
2038 INSN_UID (loc->insn), loc->nop);
2041 for (i = 0; scratches.iterate (i, &loc); i++)
2043 scratches.release ();
2044 bitmap_clear (&scratch_bitmap);
2045 bitmap_clear (&scratch_operand_bitmap);
2050 #ifdef ENABLE_CHECKING
2052 /* Function checks RTL for correctness. If FINAL_P is true, it is
2053 done at the end of LRA and the check is more rigorous. */
2055 check_rtl (bool final_p)
2060 lra_assert (! final_p || reload_completed);
2061 FOR_EACH_BB_FN (bb, cfun)
2062 FOR_BB_INSNS (bb, insn)
2063 if (NONDEBUG_INSN_P (insn)
2064 && GET_CODE (PATTERN (insn)) != USE
2065 && GET_CODE (PATTERN (insn)) != CLOBBER
2066 && GET_CODE (PATTERN (insn)) != ASM_INPUT)
2070 #ifdef ENABLED_CHECKING
2071 extract_constrain_insn (insn);
2075 /* LRA code is based on assumption that all addresses can be
2076 correctly decomposed. LRA can generate reloads for
2077 decomposable addresses. The decomposition code checks the
2078 correctness of the addresses. So we don't need to check
2079 the addresses here. Don't call insn_invalid_p here, it can
2080 change the code at this stage. */
2081 if (recog_memoized (insn) < 0 && asm_noperands (PATTERN (insn)) < 0)
2082 fatal_insn_not_found (insn);
2085 #endif /* #ifdef ENABLE_CHECKING */
2087 /* Determine if the current function has an exception receiver block
2088 that reaches the exit block via non-exceptional edges */
2090 has_nonexceptional_receiver (void)
2094 basic_block *tos, *worklist, bb;
2096 /* If we're not optimizing, then just err on the safe side. */
2100 /* First determine which blocks can reach exit via normal paths. */
2101 tos = worklist = XNEWVEC (basic_block, n_basic_blocks_for_fn (cfun) + 1);
2103 FOR_EACH_BB_FN (bb, cfun)
2104 bb->flags &= ~BB_REACHABLE;
2106 /* Place the exit block on our worklist. */
2107 EXIT_BLOCK_PTR_FOR_FN (cfun)->flags |= BB_REACHABLE;
2108 *tos++ = EXIT_BLOCK_PTR_FOR_FN (cfun);
2110 /* Iterate: find everything reachable from what we've already seen. */
2111 while (tos != worklist)
2115 FOR_EACH_EDGE (e, ei, bb->preds)
2116 if (e->flags & EDGE_ABNORMAL)
2123 basic_block src = e->src;
2125 if (!(src->flags & BB_REACHABLE))
2127 src->flags |= BB_REACHABLE;
2133 /* No exceptional block reached exit unexceptionally. */
2139 /* Process recursively X of INSN and add REG_INC notes if necessary. */
2141 add_auto_inc_notes (rtx_insn *insn, rtx x)
2143 enum rtx_code code = GET_CODE (x);
2147 if (code == MEM && auto_inc_p (XEXP (x, 0)))
2149 add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
2153 /* Scan all X sub-expressions. */
2154 fmt = GET_RTX_FORMAT (code);
2155 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2158 add_auto_inc_notes (insn, XEXP (x, i));
2159 else if (fmt[i] == 'E')
2160 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2161 add_auto_inc_notes (insn, XVECEXP (x, i, j));
2167 /* Remove all REG_DEAD and REG_UNUSED notes and regenerate REG_INC.
2168 We change pseudos by hard registers without notification of DF and
2169 that can make the notes obsolete. DF-infrastructure does not deal
2170 with REG_INC notes -- so we should regenerate them here. */
2172 update_inc_notes (void)
2178 FOR_EACH_BB_FN (bb, cfun)
2179 FOR_BB_INSNS (bb, insn)
2180 if (NONDEBUG_INSN_P (insn))
2182 pnote = ®_NOTES (insn);
2185 if (REG_NOTE_KIND (*pnote) == REG_DEAD
2186 || REG_NOTE_KIND (*pnote) == REG_UNUSED
2187 || REG_NOTE_KIND (*pnote) == REG_INC)
2188 *pnote = XEXP (*pnote, 1);
2190 pnote = &XEXP (*pnote, 1);
2193 add_auto_inc_notes (insn, PATTERN (insn));
2198 /* Set to 1 while in lra. */
2199 int lra_in_progress;
2201 /* Start of pseudo regnos before the LRA. */
2202 int lra_new_regno_start;
2204 /* Start of reload pseudo regnos before the new spill pass. */
2205 int lra_constraint_new_regno_start;
2207 /* Avoid spilling pseudos with regno more than the following value if
2209 int lra_bad_spill_regno_start;
2211 /* Inheritance pseudo regnos before the new spill pass. */
2212 bitmap_head lra_inheritance_pseudos;
2214 /* Split regnos before the new spill pass. */
2215 bitmap_head lra_split_regs;
2217 /* Reload pseudo regnos before the new assignmnet pass which still can
2218 be spilled after the assinment pass as memory is also accepted in
2219 insns for the reload pseudos. */
2220 bitmap_head lra_optional_reload_pseudos;
2222 /* Pseudo regnos used for subreg reloads before the new assignment
2223 pass. Such pseudos still can be spilled after the assinment
2225 bitmap_head lra_subreg_reload_pseudos;
2227 /* File used for output of LRA debug information. */
2228 FILE *lra_dump_file;
2230 /* True if we should try spill into registers of different classes
2231 instead of memory. */
2232 bool lra_reg_spill_p;
2234 /* Set up value LRA_REG_SPILL_P. */
2236 setup_reg_spill_flag (void)
2240 if (targetm.spill_class != NULL)
2241 for (cl = 0; cl < (int) LIM_REG_CLASSES; cl++)
2242 for (mode = 0; mode < MAX_MACHINE_MODE; mode++)
2243 if (targetm.spill_class ((enum reg_class) cl,
2244 (machine_mode) mode) != NO_REGS)
2246 lra_reg_spill_p = true;
2249 lra_reg_spill_p = false;
2252 /* True if the current function is too big to use regular algorithms
2253 in LRA. In other words, we should use simpler and faster algorithms
2254 in LRA. It also means we should not worry about generation code
2255 for caller saves. The value is set up in IRA. */
2258 /* Major LRA entry function. F is a file should be used to dump LRA
2264 bool live_p, scratch_p, inserted_p;
2268 timevar_push (TV_LRA);
2270 /* Make sure that the last insn is a note. Some subsequent passes
2272 emit_note (NOTE_INSN_DELETED);
2274 COPY_HARD_REG_SET (lra_no_alloc_regs, ira_no_alloc_regs);
2279 init_insn_recog_data ();
2281 #ifdef ENABLE_CHECKING
2282 /* Some quick check on RTL generated by previous passes. */
2286 lra_in_progress = 1;
2288 lra_live_range_iter = lra_coalesce_iter = lra_constraint_iter = 0;
2289 lra_assignment_iter = lra_assignment_iter_after_spill = 0;
2290 lra_inheritance_iter = lra_undo_inheritance_iter = 0;
2291 lra_rematerialization_iter = 0;
2293 setup_reg_spill_flag ();
2295 /* Function remove_scratches can creates new pseudos for clobbers --
2296 so set up lra_constraint_new_regno_start before its call to
2297 permit changing reg classes for pseudos created by this
2299 lra_constraint_new_regno_start = lra_new_regno_start = max_reg_num ();
2300 lra_bad_spill_regno_start = INT_MAX;
2301 remove_scratches ();
2302 scratch_p = lra_constraint_new_regno_start != max_reg_num ();
2304 /* A function that has a non-local label that can reach the exit
2305 block via non-exceptional paths must save all call-saved
2307 if (cfun->has_nonlocal_label && has_nonexceptional_receiver ())
2308 crtl->saves_all_registers = 1;
2310 if (crtl->saves_all_registers)
2311 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2312 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
2313 df_set_regs_ever_live (i, true);
2315 /* We don't DF from now and avoid its using because it is to
2316 expensive when a lot of RTL changes are made. */
2317 df_set_flags (DF_NO_INSN_RESCAN);
2318 lra_constraint_insn_stack.create (get_max_uid ());
2319 lra_constraint_insn_stack_bitmap = sbitmap_alloc (get_max_uid ());
2320 bitmap_clear (lra_constraint_insn_stack_bitmap);
2321 lra_live_ranges_init ();
2322 lra_constraints_init ();
2323 lra_curr_reload_num = 0;
2324 push_insns (get_last_insn (), NULL);
2325 /* It is needed for the 1st coalescing. */
2326 bitmap_initialize (&lra_inheritance_pseudos, ®_obstack);
2327 bitmap_initialize (&lra_split_regs, ®_obstack);
2328 bitmap_initialize (&lra_optional_reload_pseudos, ®_obstack);
2329 bitmap_initialize (&lra_subreg_reload_pseudos, ®_obstack);
2331 if (get_frame_size () != 0 && crtl->stack_alignment_needed)
2332 /* If we have a stack frame, we must align it now. The stack size
2333 may be a part of the offset computation for register
2335 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
2341 /* We should try to assign hard registers to scratches even
2342 if there were no RTL transformations in
2344 if (! lra_constraints (lra_constraint_iter == 0)
2345 && (lra_constraint_iter > 1
2346 || (! scratch_p && ! caller_save_needed)))
2348 /* Constraint transformations may result in that eliminable
2349 hard regs become uneliminable and pseudos which use them
2350 should be spilled. It is better to do it before pseudo
2353 For example, rs6000 can make
2354 RS6000_PIC_OFFSET_TABLE_REGNUM uneliminable if we started
2355 to use a constant pool. */
2356 lra_eliminate (false, false);
2357 /* Do inheritance only for regular algorithms. */
2363 lra_clear_live_ranges ();
2364 /* As a side-effect of lra_create_live_ranges, we calculate
2365 actual_call_used_reg_set, which is needed during
2367 lra_create_live_ranges (true, true);
2373 lra_clear_live_ranges ();
2374 /* We need live ranges for lra_assign -- so build them. But
2375 don't remove dead insns or change global live info as we
2376 can undo inheritance transformations after inheritance
2377 pseudo assigning. */
2378 lra_create_live_ranges (true, false);
2380 /* If we don't spill non-reload and non-inheritance pseudos,
2381 there is no sense to run memory-memory move coalescing.
2382 If inheritance pseudos were spilled, the memory-memory
2383 moves involving them will be removed by pass undoing
2389 bool spill_p = !lra_assign ();
2391 if (lra_undo_inheritance ())
2397 lra_create_live_ranges (true, true);
2400 if (lra_coalesce ())
2404 lra_clear_live_ranges ();
2407 /* Don't clear optional reloads bitmap until all constraints are
2408 satisfied as we need to differ them from regular reloads. */
2409 bitmap_clear (&lra_optional_reload_pseudos);
2410 bitmap_clear (&lra_subreg_reload_pseudos);
2411 bitmap_clear (&lra_inheritance_pseudos);
2412 bitmap_clear (&lra_split_regs);
2415 /* We need full live info for spilling pseudos into
2416 registers instead of memory. */
2417 lra_create_live_ranges (lra_reg_spill_p, true);
2420 /* We should check necessity for spilling here as the above live
2421 range pass can remove spilled pseudos. */
2422 if (! lra_need_for_spills_p ())
2424 /* Now we know what pseudos should be spilled. Try to
2425 rematerialize them first. */
2428 /* We need full live info -- see the comment above. */
2429 lra_create_live_ranges (lra_reg_spill_p, true);
2431 if (! lra_need_for_spills_p ())
2435 /* Assignment of stack slots changes elimination offsets for
2436 some eliminations. So update the offsets here. */
2437 lra_eliminate (false, false);
2438 lra_constraint_new_regno_start = max_reg_num ();
2439 if (lra_bad_spill_regno_start == INT_MAX
2440 && lra_inheritance_iter > LRA_MAX_INHERITANCE_PASSES
2441 && lra_rematerialization_iter > LRA_MAX_REMATERIALIZATION_PASSES)
2442 /* After switching off inheritance and rematerialization
2443 passes, avoid spilling reload pseudos will be created to
2444 prevent LRA cycling in some complicated cases. */
2445 lra_bad_spill_regno_start = lra_constraint_new_regno_start;
2446 lra_assignment_iter_after_spill = 0;
2448 restore_scratches ();
2449 lra_eliminate (true, false);
2450 lra_final_code_change ();
2451 lra_in_progress = 0;
2453 lra_clear_live_ranges ();
2454 lra_live_ranges_finish ();
2455 lra_constraints_finish ();
2457 sbitmap_free (lra_constraint_insn_stack_bitmap);
2458 lra_constraint_insn_stack.release ();
2459 finish_insn_recog_data ();
2460 regstat_free_n_sets_and_refs ();
2462 reload_completed = 1;
2463 update_inc_notes ();
2465 inserted_p = fixup_abnormal_edges ();
2467 /* We've possibly turned single trapping insn into multiple ones. */
2468 if (cfun->can_throw_non_call_exceptions)
2471 blocks = sbitmap_alloc (last_basic_block_for_fn (cfun));
2472 bitmap_ones (blocks);
2473 find_many_sub_basic_blocks (blocks);
2474 sbitmap_free (blocks);
2478 commit_edge_insertions ();
2480 /* Replacing pseudos with their memory equivalents might have
2481 created shared rtx. Subsequent passes would get confused
2482 by this, so unshare everything here. */
2483 unshare_all_rtl_again (get_insns ());
2485 #ifdef ENABLE_CHECKING
2489 timevar_pop (TV_LRA);
2492 /* Called once per compiler to initialize LRA data once. */
2494 lra_init_once (void)
2496 init_insn_code_data_once ();
2499 /* Called once per compiler to finish LRA data which are initialize
2502 lra_finish_once (void)
2504 finish_insn_code_data_once ();