drm/i915: Update to Linux 3.9.11
[dragonfly.git] / sys / dev / drm / i915 / i915_suspend.c
1 /*
2  *
3  * Copyright 2008 (c) Intel Corporation
4  *   Jesse Barnes <jbarnes@virtuousgeek.org>
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the
8  * "Software"), to deal in the Software without restriction, including
9  * without limitation the rights to use, copy, modify, merge, publish,
10  * distribute, sub license, and/or sell copies of the Software, and to
11  * permit persons to whom the Software is furnished to do so, subject to
12  * the following conditions:
13  *
14  * The above copyright notice and this permission notice (including the
15  * next paragraph) shall be included in all copies or substantial portions
16  * of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25  */
26
27 #include <drm/drmP.h>
28 #include <drm/i915_drm.h>
29 #include "intel_drv.h"
30 #include "i915_reg.h"
31
32 static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
33 {
34         struct drm_i915_private *dev_priv = dev->dev_private;
35
36         I915_WRITE8(index_port, reg);
37         return I915_READ8(data_port);
38 }
39
40 static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
41 {
42         struct drm_i915_private *dev_priv = dev->dev_private;
43
44         I915_READ8(st01);
45         I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
46         return I915_READ8(VGA_AR_DATA_READ);
47 }
48
49 static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
50 {
51         struct drm_i915_private *dev_priv = dev->dev_private;
52
53         I915_READ8(st01);
54         I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
55         I915_WRITE8(VGA_AR_DATA_WRITE, val);
56 }
57
58 static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
59 {
60         struct drm_i915_private *dev_priv = dev->dev_private;
61
62         I915_WRITE8(index_port, reg);
63         I915_WRITE8(data_port, val);
64 }
65
66 static void i915_save_vga(struct drm_device *dev)
67 {
68         struct drm_i915_private *dev_priv = dev->dev_private;
69         int i;
70         u16 cr_index, cr_data, st01;
71
72         /* VGA state */
73         dev_priv->regfile.saveVGA0 = I915_READ(VGA0);
74         dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
75         dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
76         dev_priv->regfile.saveVGACNTRL = I915_READ(i915_vgacntrl_reg(dev));
77
78         /* VGA color palette registers */
79         dev_priv->regfile.saveDACMASK = I915_READ8(VGA_DACMASK);
80
81         /* MSR bits */
82         dev_priv->regfile.saveMSR = I915_READ8(VGA_MSR_READ);
83         if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
84                 cr_index = VGA_CR_INDEX_CGA;
85                 cr_data = VGA_CR_DATA_CGA;
86                 st01 = VGA_ST01_CGA;
87         } else {
88                 cr_index = VGA_CR_INDEX_MDA;
89                 cr_data = VGA_CR_DATA_MDA;
90                 st01 = VGA_ST01_MDA;
91         }
92
93         /* CRT controller regs */
94         i915_write_indexed(dev, cr_index, cr_data, 0x11,
95                            i915_read_indexed(dev, cr_index, cr_data, 0x11) &
96                            (~0x80));
97         for (i = 0; i <= 0x24; i++)
98                 dev_priv->regfile.saveCR[i] =
99                         i915_read_indexed(dev, cr_index, cr_data, i);
100         /* Make sure we don't turn off CR group 0 writes */
101         dev_priv->regfile.saveCR[0x11] &= ~0x80;
102
103         /* Attribute controller registers */
104         I915_READ8(st01);
105         dev_priv->regfile.saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
106         for (i = 0; i <= 0x14; i++)
107                 dev_priv->regfile.saveAR[i] = i915_read_ar(dev, st01, i, 0);
108         I915_READ8(st01);
109         I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX);
110         I915_READ8(st01);
111
112         /* Graphics controller registers */
113         for (i = 0; i < 9; i++)
114                 dev_priv->regfile.saveGR[i] =
115                         i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);
116
117         dev_priv->regfile.saveGR[0x10] =
118                 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
119         dev_priv->regfile.saveGR[0x11] =
120                 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
121         dev_priv->regfile.saveGR[0x18] =
122                 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
123
124         /* Sequencer registers */
125         for (i = 0; i < 8; i++)
126                 dev_priv->regfile.saveSR[i] =
127                         i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
128 }
129
130 static void i915_restore_vga(struct drm_device *dev)
131 {
132         struct drm_i915_private *dev_priv = dev->dev_private;
133         int i;
134         u16 cr_index, cr_data, st01;
135
136         /* VGA state */
137         I915_WRITE(i915_vgacntrl_reg(dev), dev_priv->regfile.saveVGACNTRL);
138
139         I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
140         I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
141         I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
142         POSTING_READ(VGA_PD);
143         udelay(150);
144
145         /* MSR bits */
146         I915_WRITE8(VGA_MSR_WRITE, dev_priv->regfile.saveMSR);
147         if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
148                 cr_index = VGA_CR_INDEX_CGA;
149                 cr_data = VGA_CR_DATA_CGA;
150                 st01 = VGA_ST01_CGA;
151         } else {
152                 cr_index = VGA_CR_INDEX_MDA;
153                 cr_data = VGA_CR_DATA_MDA;
154                 st01 = VGA_ST01_MDA;
155         }
156
157         /* Sequencer registers, don't write SR07 */
158         for (i = 0; i < 7; i++)
159                 i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
160                                    dev_priv->regfile.saveSR[i]);
161
162         /* CRT controller regs */
163         /* Enable CR group 0 writes */
164         i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->regfile.saveCR[0x11]);
165         for (i = 0; i <= 0x24; i++)
166                 i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->regfile.saveCR[i]);
167
168         /* Graphics controller regs */
169         for (i = 0; i < 9; i++)
170                 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
171                                    dev_priv->regfile.saveGR[i]);
172
173         i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
174                            dev_priv->regfile.saveGR[0x10]);
175         i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
176                            dev_priv->regfile.saveGR[0x11]);
177         i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
178                            dev_priv->regfile.saveGR[0x18]);
179
180         /* Attribute controller registers */
181         I915_READ8(st01); /* switch back to index mode */
182         for (i = 0; i <= 0x14; i++)
183                 i915_write_ar(dev, st01, i, dev_priv->regfile.saveAR[i], 0);
184         I915_READ8(st01); /* switch back to index mode */
185         I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX | 0x20);
186         I915_READ8(st01);
187
188         /* VGA color palette registers */
189         I915_WRITE8(VGA_DACMASK, dev_priv->regfile.saveDACMASK);
190 }
191
192 static void i915_save_display(struct drm_device *dev)
193 {
194         struct drm_i915_private *dev_priv = dev->dev_private;
195
196         /* Display arbitration control */
197         if (INTEL_INFO(dev)->gen <= 4)
198                 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
199
200         /* This is only meaningful in non-KMS mode */
201         /* Don't regfile.save them in KMS mode */
202         if (!drm_core_check_feature(dev, DRIVER_MODESET))
203                 i915_save_display_reg(dev);
204
205         /* LVDS state */
206         if (HAS_PCH_SPLIT(dev)) {
207                 dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
208                 dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
209                 dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
210                 dev_priv->regfile.saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
211                 dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
212                 dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
213         } else {
214                 dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
215                 dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
216                 dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
217                 dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
218                 if (INTEL_INFO(dev)->gen >= 4)
219                         dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
220                 if (IS_MOBILE(dev) && !IS_I830(dev))
221                         dev_priv->regfile.saveLVDS = I915_READ(LVDS);
222         }
223
224         if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
225                 dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
226
227         if (HAS_PCH_SPLIT(dev)) {
228                 dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
229                 dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
230                 dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
231         } else {
232                 dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
233                 dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
234                 dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR);
235         }
236
237         /* Only regfile.save FBC state on the platform that supports FBC */
238         if (I915_HAS_FBC(dev)) {
239                 if (HAS_PCH_SPLIT(dev)) {
240                         dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE);
241                 } else if (IS_GM45(dev)) {
242                         dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
243                 } else {
244                         dev_priv->regfile.saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
245                         dev_priv->regfile.saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
246                         dev_priv->regfile.saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
247                         dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
248                 }
249         }
250
251         if (!drm_core_check_feature(dev, DRIVER_MODESET))
252                 i915_save_vga(dev);
253 }
254
255 static void i915_restore_display(struct drm_device *dev)
256 {
257         struct drm_i915_private *dev_priv = dev->dev_private;
258
259         /* Display arbitration */
260         if (INTEL_INFO(dev)->gen <= 4)
261                 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
262
263         if (!drm_core_check_feature(dev, DRIVER_MODESET))
264                 i915_restore_display_reg(dev);
265
266         /* LVDS state */
267         if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
268                 I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
269
270         if (HAS_PCH_SPLIT(dev)) {
271                 I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS);
272         } else if (IS_MOBILE(dev) && !IS_I830(dev))
273                 I915_WRITE(LVDS, dev_priv->regfile.saveLVDS);
274
275         if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
276                 I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL);
277
278         if (HAS_PCH_SPLIT(dev)) {
279                 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->regfile.saveBLC_PWM_CTL);
280                 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
281                 /* NOTE: BLC_PWM_CPU_CTL must be written after BLC_PWM_CPU_CTL2;
282                  * otherwise we get blank eDP screen after S3 on some machines
283                  */
284                 I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->regfile.saveBLC_CPU_PWM_CTL2);
285                 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->regfile.saveBLC_CPU_PWM_CTL);
286                 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
287                 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
288                 I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
289                 I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
290                 I915_WRITE(RSTDBYCTL,
291                            dev_priv->regfile.saveMCHBAR_RENDER_STANDBY);
292         } else {
293                 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS);
294                 I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL);
295                 I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL);
296                 I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
297                 I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
298                 I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
299                 I915_WRITE(PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
300         }
301
302         /* only restore FBC info on the platform that supports FBC*/
303         intel_disable_fbc(dev);
304         if (I915_HAS_FBC(dev)) {
305                 if (HAS_PCH_SPLIT(dev)) {
306                         I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
307                 } else if (IS_GM45(dev)) {
308                         I915_WRITE(DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
309                 } else {
310                         I915_WRITE(FBC_CFB_BASE, dev_priv->regfile.saveFBC_CFB_BASE);
311                         I915_WRITE(FBC_LL_BASE, dev_priv->regfile.saveFBC_LL_BASE);
312                         I915_WRITE(FBC_CONTROL2, dev_priv->regfile.saveFBC_CONTROL2);
313                         I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
314                 }
315         }
316
317         if (!drm_core_check_feature(dev, DRIVER_MODESET))
318                 i915_restore_vga(dev);
319         else
320                 i915_redisable_vga(dev);
321 }
322
323 int i915_save_state(struct drm_device *dev)
324 {
325         struct drm_i915_private *dev_priv = dev->dev_private;
326         int i;
327
328         pci_read_config_byte(dev->pdev, LBB, &dev_priv->regfile.saveLBB);
329
330         mutex_lock(&dev->struct_mutex);
331
332         i915_save_display(dev);
333
334         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
335                 /* Interrupt state */
336                 if (HAS_PCH_SPLIT(dev)) {
337                         dev_priv->regfile.saveDEIER = I915_READ(DEIER);
338                         dev_priv->regfile.saveDEIMR = I915_READ(DEIMR);
339                         dev_priv->regfile.saveGTIER = I915_READ(GTIER);
340                         dev_priv->regfile.saveGTIMR = I915_READ(GTIMR);
341                         dev_priv->regfile.saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);
342                         dev_priv->regfile.saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);
343                         dev_priv->regfile.saveMCHBAR_RENDER_STANDBY =
344                                 I915_READ(RSTDBYCTL);
345                         dev_priv->regfile.savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);
346                 } else {
347                         dev_priv->regfile.saveIER = I915_READ(IER);
348                         dev_priv->regfile.saveIMR = I915_READ(IMR);
349                 }
350         }
351
352         intel_disable_gt_powersave(dev);
353
354         /* Cache mode state */
355         dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
356
357         /* Memory Arbitration state */
358         dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
359
360         /* Scratch space */
361         for (i = 0; i < 16; i++) {
362                 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF00 + (i << 2));
363                 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF10 + (i << 2));
364         }
365         for (i = 0; i < 3; i++)
366                 dev_priv->regfile.saveSWF2[i] = I915_READ(SWF30 + (i << 2));
367
368         mutex_unlock(&dev->struct_mutex);
369
370         return 0;
371 }
372
373 int i915_restore_state(struct drm_device *dev)
374 {
375         struct drm_i915_private *dev_priv = dev->dev_private;
376         int i;
377
378         pci_write_config_byte(dev->pdev, LBB, dev_priv->regfile.saveLBB);
379
380         mutex_lock(&dev->struct_mutex);
381
382         i915_restore_display(dev);
383
384         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
385                 /* Interrupt state */
386                 if (HAS_PCH_SPLIT(dev)) {
387                         I915_WRITE(DEIER, dev_priv->regfile.saveDEIER);
388                         I915_WRITE(DEIMR, dev_priv->regfile.saveDEIMR);
389                         I915_WRITE(GTIER, dev_priv->regfile.saveGTIER);
390                         I915_WRITE(GTIMR, dev_priv->regfile.saveGTIMR);
391                         I915_WRITE(_FDI_RXA_IMR, dev_priv->regfile.saveFDI_RXA_IMR);
392                         I915_WRITE(_FDI_RXB_IMR, dev_priv->regfile.saveFDI_RXB_IMR);
393                         I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->regfile.savePCH_PORT_HOTPLUG);
394                 } else {
395                         I915_WRITE(IER, dev_priv->regfile.saveIER);
396                         I915_WRITE(IMR, dev_priv->regfile.saveIMR);
397                 }
398         }
399
400         /* Cache mode state */
401         I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | 0xffff0000);
402
403         /* Memory arbitration state */
404         I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
405
406         for (i = 0; i < 16; i++) {
407                 I915_WRITE(SWF00 + (i << 2), dev_priv->regfile.saveSWF0[i]);
408                 I915_WRITE(SWF10 + (i << 2), dev_priv->regfile.saveSWF1[i]);
409         }
410         for (i = 0; i < 3; i++)
411                 I915_WRITE(SWF30 + (i << 2), dev_priv->regfile.saveSWF2[i]);
412
413         mutex_unlock(&dev->struct_mutex);
414
415         intel_i2c_reset(dev);
416
417         return 0;
418 }