2 * Copyright (c) 2013-2014 Kevin Lo
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 /* $FreeBSD: head/sys/dev/usb/net/if_axge.c 276701 2015-01-05 15:04:17Z hselasky $ */
30 * ASIX Electronics AX88178A/AX88179 USB 2.0/3.0 gigabit ethernet driver.
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/condvar.h>
37 #include <sys/kernel.h>
39 #include <sys/module.h>
40 #include <sys/socket.h>
41 #include <sys/sysctl.h>
42 #include <sys/unistd.h>
45 #include <net/if_var.h>
46 #include <net/ifq_var.h>
48 #include <bus/u4b/usb.h>
49 #include <bus/u4b/usbdi.h>
50 #include <bus/u4b/usbdi_util.h>
53 #define USB_DEBUG_VAR axge_debug
54 #include <bus/u4b/usb_debug.h>
55 #include <bus/u4b/usb_process.h>
57 #include <bus/u4b/net/usb_ethernet.h>
58 #include <bus/u4b/net/if_axgereg.h>
61 * Various supported device vendors/products.
64 static const STRUCT_USB_HOST_ID axge_devs[] = {
65 #define AXGE_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) }
66 AXGE_DEV(ASIX, AX88178A),
67 AXGE_DEV(ASIX, AX88179),
68 AXGE_DEV(DLINK, DUB1312),
69 AXGE_DEV(SITECOMEU, LN032),
79 } __packed axge_bulk_size[] = {
80 { 7, 0x4f, 0x00, 0x12, 0xff },
81 { 7, 0x20, 0x03, 0x16, 0xff },
82 { 7, 0xae, 0x07, 0x18, 0xff },
83 { 7, 0xcc, 0x4c, 0x18, 0x08 }
88 static device_probe_t axge_probe;
89 static device_attach_t axge_attach;
90 static device_detach_t axge_detach;
92 static usb_callback_t axge_bulk_read_callback;
93 static usb_callback_t axge_bulk_write_callback;
95 static miibus_readreg_t axge_miibus_readreg;
96 static miibus_writereg_t axge_miibus_writereg;
97 static miibus_statchg_t axge_miibus_statchg;
99 static uether_fn_t axge_attach_post;
100 static uether_fn_t axge_init;
101 static uether_fn_t axge_stop;
102 static uether_fn_t axge_start;
103 static uether_fn_t axge_tick;
104 static uether_fn_t axge_setmulti;
105 static uether_fn_t axge_setpromisc;
107 static int axge_read_mem(struct axge_softc *, uint8_t, uint16_t,
108 uint16_t, void *, int);
109 static void axge_write_mem(struct axge_softc *, uint8_t, uint16_t,
110 uint16_t, void *, int);
111 static uint8_t axge_read_cmd_1(struct axge_softc *, uint8_t, uint16_t);
112 static uint16_t axge_read_cmd_2(struct axge_softc *, uint8_t, uint16_t,
114 static void axge_write_cmd_1(struct axge_softc *, uint8_t, uint16_t,
116 static void axge_write_cmd_2(struct axge_softc *, uint8_t, uint16_t,
118 static void axge_chip_init(struct axge_softc *);
119 static void axge_reset(struct axge_softc *);
121 static int axge_attach_post_sub(struct usb_ether *);
122 static int axge_ifmedia_upd(struct ifnet *);
123 static void axge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
124 static int axge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
125 static void axge_rx_frame(struct usb_ether *, struct usb_page_cache *, int);
126 static void axge_rxeof(struct usb_ether *, struct usb_page_cache *,
127 unsigned int, unsigned int, uint32_t);
128 static void axge_csum_cfg(struct usb_ether *);
130 #define AXGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
133 static int axge_debug = 0;
135 static SYSCTL_NODE(_hw_usb, OID_AUTO, axge, CTLFLAG_RW, 0, "USB axge");
136 SYSCTL_INT(_hw_usb_axge, OID_AUTO, debug, CTLFLAG_RW, &axge_debug, 0,
140 static const struct usb_config axge_config[AXGE_N_TRANSFER] = {
141 [AXGE_BULK_DT_WR] = {
143 .endpoint = UE_ADDR_ANY,
144 .direction = UE_DIR_OUT,
146 .bufsize = 16 * MCLBYTES,
147 .flags = {.pipe_bof = 1,.force_short_xfer = 1,},
148 .callback = axge_bulk_write_callback,
149 .timeout = 10000, /* 10 seconds */
151 [AXGE_BULK_DT_RD] = {
153 .endpoint = UE_ADDR_ANY,
154 .direction = UE_DIR_IN,
156 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
157 .callback = axge_bulk_read_callback,
158 .timeout = 0, /* no timeout */
162 static device_method_t axge_methods[] = {
163 /* Device interface. */
164 DEVMETHOD(device_probe, axge_probe),
165 DEVMETHOD(device_attach, axge_attach),
166 DEVMETHOD(device_detach, axge_detach),
169 DEVMETHOD(miibus_readreg, axge_miibus_readreg),
170 DEVMETHOD(miibus_writereg, axge_miibus_writereg),
171 DEVMETHOD(miibus_statchg, axge_miibus_statchg),
176 static driver_t axge_driver = {
178 .methods = axge_methods,
179 .size = sizeof(struct axge_softc),
182 static devclass_t axge_devclass;
184 DRIVER_MODULE(axge, uhub, axge_driver, axge_devclass, NULL, NULL);
185 DRIVER_MODULE(miibus, axge, miibus_driver, miibus_devclass, NULL, NULL);
186 MODULE_DEPEND(axge, uether, 1, 1, 1);
187 MODULE_DEPEND(axge, usb, 1, 1, 1);
188 MODULE_DEPEND(axge, ether, 1, 1, 1);
189 MODULE_DEPEND(axge, miibus, 1, 1, 1);
190 MODULE_VERSION(axge, 1);
192 static const struct usb_ether_methods axge_ue_methods = {
193 .ue_attach_post = axge_attach_post,
194 .ue_attach_post_sub = axge_attach_post_sub,
195 .ue_start = axge_start,
196 .ue_init = axge_init,
197 .ue_stop = axge_stop,
198 .ue_tick = axge_tick,
199 .ue_setmulti = axge_setmulti,
200 .ue_setpromisc = axge_setpromisc,
201 .ue_mii_upd = axge_ifmedia_upd,
202 .ue_mii_sts = axge_ifmedia_sts,
206 axge_read_mem(struct axge_softc *sc, uint8_t cmd, uint16_t index,
207 uint16_t val, void *buf, int len)
209 struct usb_device_request req;
211 AXGE_LOCK_ASSERT(sc);
213 req.bmRequestType = UT_READ_VENDOR_DEVICE;
215 USETW(req.wValue, val);
216 USETW(req.wIndex, index);
217 USETW(req.wLength, len);
219 return (uether_do_request(&sc->sc_ue, &req, buf, 1000));
223 axge_write_mem(struct axge_softc *sc, uint8_t cmd, uint16_t index,
224 uint16_t val, void *buf, int len)
226 struct usb_device_request req;
228 AXGE_LOCK_ASSERT(sc);
230 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
232 USETW(req.wValue, val);
233 USETW(req.wIndex, index);
234 USETW(req.wLength, len);
236 if (uether_do_request(&sc->sc_ue, &req, buf, 1000)) {
242 axge_read_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t reg)
246 axge_read_mem(sc, cmd, 1, reg, &val, 1);
251 axge_read_cmd_2(struct axge_softc *sc, uint8_t cmd, uint16_t index,
256 axge_read_mem(sc, cmd, index, reg, &val, 2);
261 axge_write_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t reg, uint8_t val)
263 axge_write_mem(sc, cmd, 1, reg, &val, 1);
267 axge_write_cmd_2(struct axge_softc *sc, uint8_t cmd, uint16_t index,
268 uint16_t reg, uint16_t val)
273 axge_write_mem(sc, cmd, index, reg, &temp, 2);
277 axge_miibus_readreg(device_t dev, int phy, int reg)
279 struct axge_softc *sc;
283 sc = device_get_softc(dev);
284 locked = lockowned(&sc->sc_lock);
288 val = axge_read_cmd_2(sc, AXGE_ACCESS_PHY, reg, phy);
297 axge_miibus_writereg(device_t dev, int phy, int reg, int val)
299 struct axge_softc *sc;
302 sc = device_get_softc(dev);
303 if (sc->sc_phyno != phy)
305 locked = lockowned(&sc->sc_lock);
309 axge_write_cmd_2(sc, AXGE_ACCESS_PHY, reg, phy, val);
318 axge_miibus_statchg(device_t dev)
320 struct axge_softc *sc;
321 struct mii_data *mii;
323 uint8_t link_status, tmp[5];
327 sc = device_get_softc(dev);
329 locked = lockowned(&sc->sc_lock);
333 ifp = uether_getifp(&sc->sc_ue);
334 if (mii == NULL || ifp == NULL ||
335 (ifp->if_flags & IFF_RUNNING) == 0)
338 sc->sc_flags &= ~AXGE_FLAG_LINK;
339 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
340 (IFM_ACTIVE | IFM_AVALID)) {
341 switch (IFM_SUBTYPE(mii->mii_media_active)) {
345 sc->sc_flags |= AXGE_FLAG_LINK;
352 /* Lost link, do nothing. */
353 if ((sc->sc_flags & AXGE_FLAG_LINK) == 0)
356 link_status = axge_read_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PLSR);
359 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
361 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
363 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
367 switch (IFM_SUBTYPE(mii->mii_media_active)) {
369 val |= MSR_GM | MSR_EN_125MHZ;
370 if (link_status & PLSR_USB_SS)
371 memcpy(tmp, &axge_bulk_size[0], 5);
372 else if (link_status & PLSR_USB_HS)
373 memcpy(tmp, &axge_bulk_size[1], 5);
375 memcpy(tmp, &axge_bulk_size[3], 5);
379 if (link_status & (PLSR_USB_SS | PLSR_USB_HS))
380 memcpy(tmp, &axge_bulk_size[2], 5);
382 memcpy(tmp, &axge_bulk_size[3], 5);
385 memcpy(tmp, &axge_bulk_size[3], 5);
388 /* Rx bulk configuration. */
389 axge_write_mem(sc, AXGE_ACCESS_MAC, 5, AXGE_RX_BULKIN_QCTRL, tmp, 5);
390 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, val);
397 axge_chip_init(struct axge_softc *sc)
399 /* Power up ethernet PHY. */
400 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, 0);
401 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, EPPRCR_IPRL);
402 uether_pause(&sc->sc_ue, hz / 4);
403 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CLK_SELECT,
404 AXGE_CLK_SELECT_ACS | AXGE_CLK_SELECT_BCS);
405 uether_pause(&sc->sc_ue, hz / 10);
409 axge_reset(struct axge_softc *sc)
411 struct usb_config_descriptor *cd;
414 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev);
416 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_lock,
417 cd->bConfigurationValue);
419 DPRINTF("reset failed (ignored)\n");
421 /* Wait a little while for the chip to get its brains in order. */
422 uether_pause(&sc->sc_ue, hz / 100);
424 /* Reinitialize controller to achieve full reset. */
429 axge_attach_post(struct usb_ether *ue)
431 struct axge_softc *sc;
433 sc = uether_getsc(ue);
436 /* Initialize controller and get station address. */
438 axge_read_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NIDR,
439 ue->ue_eaddr, ETHER_ADDR_LEN);
443 axge_attach_post_sub(struct usb_ether *ue)
445 struct axge_softc *sc;
449 sc = uether_getsc(ue);
450 ifp = uether_getifp(ue);
451 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
452 ifp->if_start = uether_start;
453 ifp->if_ioctl = axge_ioctl;
454 ifp->if_init = uether_init;
455 ifq_set_maxlen(&ifp->if_snd, ifqmaxlen);
456 ifq_set_ready(&ifp->if_snd);
458 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_TXCSUM | IFCAP_RXCSUM;
459 ifp->if_hwassist = AXGE_CSUM_FEATURES;
460 ifp->if_capenable = ifp->if_capabilities;
463 * NB: miibus assumes that the first member of the softc
464 * of it's parent is an arpcom structure
466 error = mii_phy_probe(ue->ue_dev, &ue->ue_miibus,
467 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts);
476 axge_ifmedia_upd(struct ifnet *ifp)
478 struct axge_softc *sc;
479 struct mii_data *mii;
480 struct mii_softc *miisc;
485 AXGE_LOCK_ASSERT(sc);
487 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
488 mii_phy_reset(miisc);
489 error = mii_mediachg(mii);
495 * Report current media status.
498 axge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
500 struct axge_softc *sc;
501 struct mii_data *mii;
507 ifmr->ifm_active = mii->mii_media_active;
508 ifmr->ifm_status = mii->mii_media_status;
513 * Probe for a AX88179 chip.
516 axge_probe(device_t dev)
518 struct usb_attach_arg *uaa;
520 uaa = device_get_ivars(dev);
521 if (uaa->usb_mode != USB_MODE_HOST)
523 if (uaa->info.bConfigIndex != AXGE_CONFIG_IDX)
525 if (uaa->info.bIfaceIndex != AXGE_IFACE_IDX)
528 return (usbd_lookup_id_by_uaa(axge_devs, sizeof(axge_devs), uaa));
532 * Attach the interface. Allocate softc structures, do ifmedia
533 * setup and ethernet/BPF attach.
536 axge_attach(device_t dev)
538 struct usb_attach_arg *uaa;
539 struct axge_softc *sc;
540 struct usb_ether *ue;
544 uaa = device_get_ivars(dev);
545 sc = device_get_softc(dev);
548 device_set_usb_desc(dev);
549 lockinit(&sc->sc_lock, device_get_nameunit(dev), 0, LK_CANRECURSE);
551 iface_index = AXGE_IFACE_IDX;
552 error = usbd_transfer_setup(uaa->device, &iface_index,
553 sc->sc_xfer, axge_config, AXGE_N_TRANSFER, sc, &sc->sc_lock);
555 device_printf(dev, "allocating USB transfers failed\n");
561 ue->ue_udev = uaa->device;
562 ue->ue_lock = &sc->sc_lock;
563 ue->ue_methods = &axge_ue_methods;
565 error = uether_ifattach(ue);
567 device_printf(dev, "could not attach interface\n");
570 return (0); /* success */
574 return (ENXIO); /* failure */
578 axge_detach(device_t dev)
580 struct axge_softc *sc;
581 struct usb_ether *ue;
583 sc = device_get_softc(dev);
585 usbd_transfer_unsetup(sc->sc_xfer, AXGE_N_TRANSFER);
587 lockuninit(&sc->sc_lock);
593 axge_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)
595 struct axge_softc *sc;
596 struct usb_ether *ue;
597 struct usb_page_cache *pc;
600 sc = usbd_xfer_softc(xfer);
602 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
604 switch (USB_GET_STATE(xfer)) {
605 case USB_ST_TRANSFERRED:
606 pc = usbd_xfer_get_frame(xfer, 0);
607 axge_rx_frame(ue, pc, actlen);
612 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
613 usbd_transfer_submit(xfer);
618 if (error != USB_ERR_CANCELLED) {
619 usbd_xfer_set_stall(xfer);
627 axge_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
629 struct axge_softc *sc;
631 struct usb_page_cache *pc;
636 sc = usbd_xfer_softc(xfer);
637 ifp = uether_getifp(&sc->sc_ue);
639 switch (USB_GET_STATE(xfer)) {
640 case USB_ST_TRANSFERRED:
641 ifq_clr_oactive(&ifp->if_snd);
645 if ((sc->sc_flags & AXGE_FLAG_LINK) == 0 ||
646 ifq_is_oactive(&ifp->if_snd)) {
648 * Don't send anything if there is no link or
649 * controller is busy.
654 for (nframes = 0; nframes < 16 &&
655 !ifq_is_empty(&ifp->if_snd); nframes++) {
656 m = ifq_dequeue(&ifp->if_snd);
659 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES,
662 pc = usbd_xfer_get_frame(xfer, nframes);
663 txhdr = htole32(m->m_pkthdr.len);
664 usbd_copy_in(pc, 0, &txhdr, sizeof(txhdr));
666 txhdr = htole32(txhdr);
667 usbd_copy_in(pc, 4, &txhdr, sizeof(txhdr));
669 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
670 pos += m->m_pkthdr.len;
671 if ((pos % usbd_xfer_max_framelen(xfer)) == 0)
676 * Update TX packet counter here. This is not
677 * correct way but it seems that there is no way
678 * to know how many packets are sent at the end
679 * of transfer because controller combines
680 * multiple writes into single one if there is
681 * room in TX buffer of controller.
683 IFNET_STAT_INC(ifp, opackets, 1);
686 * if there's a BPF listener, bounce a copy
687 * of this frame to him:
693 /* Set frame length. */
694 usbd_xfer_set_frame_len(xfer, nframes, pos);
697 usbd_xfer_set_frames(xfer, nframes);
698 usbd_transfer_submit(xfer);
699 ifq_set_oactive(&ifp->if_snd);
704 IFNET_STAT_INC(ifp, oerrors, 1);
705 ifq_clr_oactive(&ifp->if_snd);
707 if (error != USB_ERR_CANCELLED) {
708 usbd_xfer_set_stall(xfer);
717 axge_tick(struct usb_ether *ue)
719 struct axge_softc *sc;
720 struct mii_data *mii;
722 sc = uether_getsc(ue);
724 AXGE_LOCK_ASSERT(sc);
727 if ((sc->sc_flags & AXGE_FLAG_LINK) == 0) {
728 axge_miibus_statchg(ue->ue_dev);
729 if ((sc->sc_flags & AXGE_FLAG_LINK) != 0)
735 axge_setmulti(struct usb_ether *ue)
737 struct axge_softc *sc;
739 struct ifmultiaddr *ifma;
742 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
744 sc = uether_getsc(ue);
745 ifp = uether_getifp(ue);
747 AXGE_LOCK_ASSERT(sc);
749 rxmode = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR);
750 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
752 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode);
755 rxmode &= ~RCR_AMALL;
757 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
758 if (ifma->ifma_addr->sa_family != AF_LINK)
760 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
761 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
762 hashtbl[h / 8] |= 1 << (h % 8);
765 axge_write_mem(sc, AXGE_ACCESS_MAC, 8, AXGE_MFA, (void *)&hashtbl, 8);
766 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode);
770 axge_setpromisc(struct usb_ether *ue)
772 struct axge_softc *sc;
776 sc = uether_getsc(ue);
777 ifp = uether_getifp(ue);
778 rxmode = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR);
780 if (ifp->if_flags & IFF_PROMISC)
785 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode);
790 axge_start(struct usb_ether *ue)
792 struct axge_softc *sc;
794 sc = uether_getsc(ue);
796 * Start the USB transfers, if not already started.
798 usbd_transfer_start(sc->sc_xfer[AXGE_BULK_DT_RD]);
799 usbd_transfer_start(sc->sc_xfer[AXGE_BULK_DT_WR]);
803 axge_init(struct usb_ether *ue)
805 struct axge_softc *sc;
809 sc = uether_getsc(ue);
810 ifp = uether_getifp(ue);
811 AXGE_LOCK_ASSERT(sc);
813 if ((ifp->if_flags & IFF_RUNNING) != 0)
817 * Cancel pending I/O and free all RX/TX buffers.
823 /* Set MAC address. */
824 axge_write_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NIDR,
825 IF_LLADDR(ifp), ETHER_ADDR_LEN);
827 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PWLLR, 0x34);
828 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PWLHR, 0x52);
830 /* Configure TX/RX checksum offloading. */
833 /* Configure RX settings. */
834 rxmode = (RCR_AM | RCR_SO | RCR_DROP_CRCE);
835 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
838 /* If we want promiscuous mode, set the allframes bit. */
839 if (ifp->if_flags & IFF_PROMISC)
842 if (ifp->if_flags & IFF_BROADCAST)
845 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode);
847 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_MMSR,
848 MMSR_PME_TYPE | MMSR_PME_POL | MMSR_RWMP);
850 /* Load the multicast filter. */
853 usbd_xfer_set_stall(sc->sc_xfer[AXGE_BULK_DT_WR]);
855 ifp->if_flags |= IFF_RUNNING;
856 /* Switch to selected media. */
857 axge_ifmedia_upd(ifp);
861 axge_stop(struct usb_ether *ue)
863 struct axge_softc *sc;
866 sc = uether_getsc(ue);
867 ifp = uether_getifp(ue);
869 AXGE_LOCK_ASSERT(sc);
871 ifp->if_flags &= ~IFF_RUNNING;
872 ifq_clr_oactive(&ifp->if_snd);
873 sc->sc_flags &= ~AXGE_FLAG_LINK;
876 * Stop all the transfers, if not already stopped:
878 usbd_transfer_stop(sc->sc_xfer[AXGE_BULK_DT_WR]);
879 usbd_transfer_stop(sc->sc_xfer[AXGE_BULK_DT_RD]);
883 axge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *uc)
885 struct usb_ether *ue;
886 struct axge_softc *sc;
888 int error, mask, reinit;
891 sc = uether_getsc(ue);
892 ifr = (struct ifreq *)data;
895 if (cmd == SIOCSIFCAP) {
897 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
898 if ((mask & IFCAP_TXCSUM) != 0 &&
899 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
900 ifp->if_capenable ^= IFCAP_TXCSUM;
901 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
902 ifp->if_hwassist |= AXGE_CSUM_FEATURES;
904 ifp->if_hwassist &= ~AXGE_CSUM_FEATURES;
907 if ((mask & IFCAP_RXCSUM) != 0 &&
908 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
909 ifp->if_capenable ^= IFCAP_RXCSUM;
912 if (reinit > 0 && ifp->if_flags & IFF_RUNNING)
913 ifp->if_flags &= ~IFF_RUNNING;
920 error = uether_ioctl(ifp, cmd, data, uc);
926 axge_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen)
935 /* verify we have enough data */
936 if (actlen < (int)sizeof(rxhdr))
941 usbd_copy_out(pc, actlen - sizeof(rxhdr), &rxhdr, sizeof(rxhdr));
942 rxhdr = le32toh(rxhdr);
944 pkt_cnt = (uint16_t)rxhdr;
945 hdr_off = (uint16_t)(rxhdr >> 16);
948 /* verify the header offset */
949 if ((int)(hdr_off + sizeof(pkt_hdr)) > actlen) {
950 DPRINTF("End of packet headers\n");
953 if ((int)pos >= actlen) {
954 DPRINTF("Data position reached end\n");
957 usbd_copy_out(pc, hdr_off, &pkt_hdr, sizeof(pkt_hdr));
959 pkt_hdr = le32toh(pkt_hdr);
960 pktlen = (pkt_hdr >> 16) & 0x1fff;
961 if (pkt_hdr & (AXGE_RXHDR_CRC_ERR | AXGE_RXHDR_DROP_ERR)) {
962 DPRINTF("Dropped a packet\n");
963 IFNET_STAT_INC(uether_getifp(ue), ierrors, 1);
965 if (pktlen >= 6 && (int)(pos + pktlen) <= actlen) {
966 axge_rxeof(ue, pc, pos + 2, pktlen - 6, pkt_hdr);
968 DPRINTF("Invalid packet pos=%d len=%d\n",
969 (int)pos, (int)pktlen);
971 pos += (pktlen + 7) & ~7;
972 hdr_off += sizeof(pkt_hdr);
977 axge_rxeof(struct usb_ether *ue, struct usb_page_cache *pc,
978 unsigned int offset, unsigned int len, uint32_t pkt_hdr)
983 ifp = uether_getifp(ue);
984 if (len < ETHER_HDR_LEN || len > MCLBYTES - ETHER_ALIGN) {
985 IFNET_STAT_INC(ifp, ierrors, 1);
989 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
991 IFNET_STAT_INC(ifp, iqdrops, 1);
994 m->m_pkthdr.rcvif = ifp;
995 m->m_len = m->m_pkthdr.len = len + ETHER_ALIGN;
996 m_adj(m, ETHER_ALIGN);
998 usbd_copy_out(pc, offset, mtod(m, uint8_t *), len);
1000 IFNET_STAT_INC(ifp, ipackets, 1);
1002 if ((pkt_hdr & (AXGE_RXHDR_L4CSUM_ERR | AXGE_RXHDR_L3CSUM_ERR)) == 0) {
1003 if ((pkt_hdr & AXGE_RXHDR_L4_TYPE_MASK) ==
1004 AXGE_RXHDR_L4_TYPE_TCP ||
1005 (pkt_hdr & AXGE_RXHDR_L4_TYPE_MASK) ==
1006 AXGE_RXHDR_L4_TYPE_UDP) {
1007 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
1008 CSUM_PSEUDO_HDR | CSUM_IP_CHECKED | CSUM_IP_VALID;
1009 m->m_pkthdr.csum_data = 0xffff;
1013 IF_ENQUEUE(&ue->ue_rxq, m);
1017 axge_csum_cfg(struct usb_ether *ue)
1019 struct axge_softc *sc;
1023 sc = uether_getsc(ue);
1024 AXGE_LOCK_ASSERT(sc);
1025 ifp = uether_getifp(ue);
1028 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1029 csum |= CTCR_IP | CTCR_TCP | CTCR_UDP;
1030 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CTCR, csum);
1033 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1034 csum |= CRCR_IP | CRCR_TCP | CRCR_UDP;
1035 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CRCR, csum);