sys/bus/u4b/controller/xhci.c

   1 /* $FreeBSD: head/sys/dev/usb/controller/xhci.c 278477 2015-02-09 21:47:12Z hselasky $ */
   2 /*-
   3  * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 /*
  28  * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
  29  *
  30  * The XHCI 1.0 spec can be found at
  31  * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
  32  * and the USB 3.0 spec at
  33  * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
  34  */
  35
  36 /*
  37  * A few words about the design implementation: This driver emulates
  38  * the concept about TDs which is found in EHCI specification. This
  39  * way we achieve that the USB controller drivers look similar to
  40  * eachother which makes it easier to understand the code.
  41  */
  42
  43 #include <sys/stdint.h>
  44 #include <sys/param.h>
  45 #include <sys/queue.h>
  46 #include <sys/types.h>
  47 #include <sys/systm.h>
  48 #include <sys/kernel.h>
  49 #include <sys/bus.h>
  50 #include <sys/module.h>
  51 #include <sys/lock.h>
  52 #include <sys/condvar.h>
  53 #include <sys/sysctl.h>
  54 #include <sys/unistd.h>
  55 #include <sys/callout.h>
  56 #include <sys/malloc.h>
  57 #include <sys/priv.h>
  58
  59 #include <bus/u4b/usb.h>
  60 #include <bus/u4b/usbdi.h>
  61
  62 #define USB_DEBUG_VAR xhcidebug
  63
  64 #include <bus/u4b/usb_core.h>
  65 #include <bus/u4b/usb_debug.h>
  66 #include <bus/u4b/usb_busdma.h>
  67 #include <bus/u4b/usb_process.h>
  68 #include <bus/u4b/usb_transfer.h>
  69 #include <bus/u4b/usb_device.h>
  70 #include <bus/u4b/usb_hub.h>
  71 #include <bus/u4b/usb_util.h>
  72
  73 #include <bus/u4b/usb_controller.h>
  74 #include <bus/u4b/usb_bus.h>
  75 #include <bus/u4b/controller/xhci.h>
  76 #include <bus/u4b/controller/xhcireg.h>
  77
  78 #define XHCI_BUS2SC(bus) \
  79    ((struct xhci_softc *)(((uint8_t *)(bus)) - \
  80     ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
  81
  82 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
  83
  84 static int xhcistreams;
  85 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RW,
  86     &xhcistreams, 0, "Set to enable streams mode support");
  87 TUNABLE_INT("hw.usb.xhci.streams", &xhcistreams);
  88
  89
  90 #ifdef USB_DEBUG
  91 static int xhcidebug = 0;
  92 static int xhciroute = 0;
  93 static int xhcipolling = 0;
  94
  95 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW,
  96     &xhcidebug, 0, "Debug level");
  97 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug);
  98 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW,
  99     &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller");
 100 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute);
 101 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RW,
 102     &xhcipolling, 0, "Set to enable software interrupt polling for XHCI controller");
 103 TUNABLE_INT("hw.usb.xhci.use_polling", &xhcipolling);
 104 #else
 105 #define xhciroute 0
 106 #endif
 107
 108 #define XHCI_INTR_ENDPT 1
 109
 110 struct xhci_std_temp {
 111         struct xhci_softc       *sc;
 112         struct usb_page_cache   *pc;
 113         struct xhci_td          *td;
 114         struct xhci_td          *td_next;
 115         uint32_t                len;
 116         uint32_t                offset;
 117         uint32_t                max_packet_size;
 118         uint32_t                average;
 119         uint16_t                isoc_delta;
 120         uint16_t                isoc_frame;
 121         uint8_t                 shortpkt;
 122         uint8_t                 multishort;
 123         uint8_t                 last_frame;
 124         uint8_t                 trb_type;
 125         uint8_t                 direction;
 126         uint8_t                 tbc;
 127         uint8_t                 tlbpc;
 128         uint8_t                 step_td;
 129         uint8_t                 do_isoc_sync;
 130 };
 131
 132 static void     xhci_do_poll(struct usb_bus *);
 133 static void     xhci_device_done(struct usb_xfer *, usb_error_t);
 134 static void     xhci_root_intr(struct xhci_softc *);
 135 static void     xhci_free_device_ext(struct usb_device *);
 136 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
 137                     struct usb_endpoint_descriptor *);
 138 static usb_proc_callback_t xhci_configure_msg;
 139 static usb_error_t xhci_configure_device(struct usb_device *);
 140 static usb_error_t xhci_configure_endpoint(struct usb_device *,
 141                    struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *,
 142                    uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t,
 143                    uint8_t);
 144 static usb_error_t xhci_configure_mask(struct usb_device *,
 145                     uint32_t, uint8_t);
 146 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
 147                     uint64_t, uint8_t);
 148 static void xhci_endpoint_doorbell(struct usb_xfer *);
 149 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
 150 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
 151 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
 152 #ifdef USB_DEBUG
 153 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
 154 #endif
 155
 156 static const struct usb_bus_methods xhci_bus_methods;
 157
 158 #ifdef USB_DEBUG
 159 static void
 160 xhci_dump_trb(struct xhci_trb *trb)
 161 {
 162         DPRINTFN(5, "trb = %p\n", trb);
 163         DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
 164         DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
 165         DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
 166 }
 167
 168 static void
 169 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
 170 {
 171         DPRINTFN(5, "pep = %p\n", pep);
 172         DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
 173         DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
 174         DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
 175         DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
 176         DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
 177         DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
 178         DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
 179 }
 180
 181 static void
 182 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
 183 {
 184         DPRINTFN(5, "psl = %p\n", psl);
 185         DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
 186         DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
 187         DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
 188         DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
 189 }
 190 #endif
 191
 192 uint8_t
 193 xhci_use_polling(void)
 194 {
 195 #ifdef USB_DEBUG
 196         return (xhcipolling != 0);
 197 #else
 198         return (0);
 199 #endif
 200 }
 201
 202 static void
 203 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
 204 {
 205         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 206         uint8_t i;
 207
 208         cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
 209            sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
 210
 211         cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
 212            sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
 213
 214         for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) {
 215                 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
 216                     XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
 217         }
 218 }
 219
 220 static void
 221 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
 222 {
 223         if (sc->sc_ctx_is_64_byte) {
 224                 uint32_t offset;
 225                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 226                 /* all contexts are initially 32-bytes */
 227                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 228                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 229         }
 230         *ptr = htole32(val);
 231 }
 232
 233 static uint32_t
 234 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
 235 {
 236         if (sc->sc_ctx_is_64_byte) {
 237                 uint32_t offset;
 238                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 239                 /* all contexts are initially 32-bytes */
 240                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 241                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 242         }
 243         return (le32toh(*ptr));
 244 }
 245
 246 static void
 247 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
 248 {
 249         if (sc->sc_ctx_is_64_byte) {
 250                 uint32_t offset;
 251                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 252                 /* all contexts are initially 32-bytes */
 253                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 254                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 255         }
 256         *ptr = htole64(val);
 257 }
 258
 259 #ifdef USB_DEBUG
 260 static uint64_t
 261 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
 262 {
 263         if (sc->sc_ctx_is_64_byte) {
 264                 uint32_t offset;
 265                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 266                 /* all contexts are initially 32-bytes */
 267                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 268                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 269         }
 270         return (le64toh(*ptr));
 271 }
 272 #endif
 273
 274 static int
 275 xhci_reset_command_queue_locked(struct xhci_softc *sc)
 276 {
 277         struct usb_page_search buf_res;
 278         struct xhci_hw_root *phwr;
 279         uint64_t addr;
 280         uint32_t temp;
 281
 282         DPRINTF("\n");
 283
 284         temp = XREAD4(sc, oper, XHCI_CRCR_LO);
 285         if (temp & XHCI_CRCR_LO_CRR) {
 286                 DPRINTF("Command ring running\n");
 287                 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
 288
 289                 /*
 290                  * Try to abort the last command as per section
 291                  * 4.6.1.2 "Aborting a Command" of the XHCI
 292                  * specification:
 293                  */
 294
 295                 /* stop and cancel */
 296                 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
 297                 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
 298
 299                 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
 300                 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
 301
 302                 /* wait 250ms */
 303                 usb_pause_mtx(&sc->sc_bus.bus_lock, hz / 4);
 304
 305                 /* check if command ring is still running */
 306                 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
 307                 if (temp & XHCI_CRCR_LO_CRR) {
 308                         DPRINTF("Command ring still running\n");
 309                         return (USB_ERR_IOERROR);
 310                 }
 311         }
 312
 313         /* reset command ring */
 314         sc->sc_command_ccs = 1;
 315         sc->sc_command_idx = 0;
 316
 317         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 318
 319         /* setup command ring control base address */
 320         addr = buf_res.physaddr;
 321         phwr = buf_res.buffer;
 322         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 323
 324         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 325
 326         memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands));
 327         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 328
 329         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
 330
 331         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 332         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 333
 334         return (0);
 335 }
 336
 337 usb_error_t
 338 xhci_start_controller(struct xhci_softc *sc)
 339 {
 340         struct usb_page_search buf_res;
 341         struct xhci_hw_root *phwr;
 342         struct xhci_dev_ctx_addr *pdctxa;
 343         uint64_t addr;
 344         uint32_t temp;
 345         uint16_t i;
 346
 347         DPRINTF("\n");
 348
 349         sc->sc_event_ccs = 1;
 350         sc->sc_event_idx = 0;
 351         sc->sc_command_ccs = 1;
 352         sc->sc_command_idx = 0;
 353
 354         /* Reset controller */
 355         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
 356
 357         for (i = 0; i != 100; i++) {
 358                 usb_pause_mtx(NULL, hz / 100);
 359                 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
 360                     (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
 361                 if (!temp)
 362                         break;
 363         }
 364
 365         if (temp) {
 366                 device_printf(sc->sc_bus.parent, "Controller "
 367                     "reset timeout.\n");
 368                 return (USB_ERR_IOERROR);
 369         }
 370
 371         if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
 372                 device_printf(sc->sc_bus.parent, "Controller does "
 373                     "not support 4K page size.\n");
 374                 return (USB_ERR_IOERROR);
 375         }
 376
 377         temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
 378
 379         i = XHCI_HCS1_N_PORTS(temp);
 380
 381         if (i == 0) {
 382                 device_printf(sc->sc_bus.parent, "Invalid number "
 383                     "of ports: %u\n", i);
 384                 return (USB_ERR_IOERROR);
 385         }
 386
 387         sc->sc_noport = i;
 388         sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
 389
 390         if (sc->sc_noslot > XHCI_MAX_DEVICES)
 391                 sc->sc_noslot = XHCI_MAX_DEVICES;
 392
 393         /* setup number of device slots */
 394
 395         DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
 396             XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
 397
 398         XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
 399
 400         DPRINTF("Max slots: %u\n", sc->sc_noslot);
 401
 402         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 403
 404         sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
 405
 406         if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
 407                 device_printf(sc->sc_bus.parent, "XHCI request "
 408                     "too many scratchpads\n");
 409                 return (USB_ERR_NOMEM);
 410         }
 411
 412         DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
 413
 414         temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
 415
 416         sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
 417             XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
 418
 419         temp = XREAD4(sc, oper, XHCI_USBSTS);
 420
 421         /* clear interrupts */
 422         XWRITE4(sc, oper, XHCI_USBSTS, temp);
 423         /* disable all device notifications */
 424         XWRITE4(sc, oper, XHCI_DNCTRL, 0);
 425
 426         /* setup device context base address */
 427         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
 428         pdctxa = buf_res.buffer;
 429         memset(pdctxa, 0, sizeof(*pdctxa));
 430
 431         addr = buf_res.physaddr;
 432         addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
 433
 434         /* slot 0 points to the table of scratchpad pointers */
 435         pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
 436
 437         for (i = 0; i != sc->sc_noscratch; i++) {
 438                 struct usb_page_search buf_scp;
 439                 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
 440                 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
 441         }
 442
 443         addr = buf_res.physaddr;
 444
 445         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 446         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 447         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 448         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 449
 450         /* Setup event table size */
 451
 452         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 453
 454         DPRINTF("HCS2=0x%08x\n", temp);
 455
 456         temp = XHCI_HCS2_ERST_MAX(temp);
 457         temp = 1U << temp;
 458         if (temp > XHCI_MAX_RSEG)
 459                 temp = XHCI_MAX_RSEG;
 460
 461         sc->sc_erst_max = temp;
 462
 463         DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
 464             XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp);
 465
 466         XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp));
 467
 468         /* Check if we should use the default IMOD value */
 469         if (sc->sc_imod_default == 0)
 470                 sc->sc_imod_default = XHCI_IMOD_DEFAULT;
 471
 472         /* Setup interrupt rate */
 473         XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default);
 474
 475         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 476
 477         phwr = buf_res.buffer;
 478         addr = buf_res.physaddr;
 479         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
 480
 481         /* reset hardware root structure */
 482         memset(phwr, 0, sizeof(*phwr));
 483
 484         phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
 485         phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
 486
 487         DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
 488
 489         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
 490         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
 491
 492         addr = buf_res.physaddr;
 493
 494         DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
 495
 496         XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
 497         XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
 498
 499         /* Setup interrupter registers */
 500
 501         temp = XREAD4(sc, runt, XHCI_IMAN(0));
 502         temp |= XHCI_IMAN_INTR_ENA;
 503         XWRITE4(sc, runt, XHCI_IMAN(0), temp);
 504
 505         /* setup command ring control base address */
 506         addr = buf_res.physaddr;
 507         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 508
 509         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 510
 511         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 512         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 513
 514         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 515
 516         usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 517
 518         /* Go! */
 519         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
 520             XHCI_CMD_INTE | XHCI_CMD_HSEE);
 521
 522         for (i = 0; i != 100; i++) {
 523                 usb_pause_mtx(NULL, hz / 100);
 524                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 525                 if (!temp)
 526                         break;
 527         }
 528         if (temp) {
 529                 XWRITE4(sc, oper, XHCI_USBCMD, 0);
 530                 device_printf(sc->sc_bus.parent, "Run timeout.\n");
 531                 return (USB_ERR_IOERROR);
 532         }
 533
 534         /* catch any lost interrupts */
 535         xhci_do_poll(&sc->sc_bus);
 536
 537         if (sc->sc_port_route != NULL) {
 538                 /* Route all ports to the XHCI by default */
 539                 sc->sc_port_route(sc->sc_bus.parent,
 540                     ~xhciroute, xhciroute);
 541         }
 542         return (0);
 543 }
 544
 545 usb_error_t
 546 xhci_halt_controller(struct xhci_softc *sc)
 547 {
 548         uint32_t temp;
 549         uint16_t i;
 550
 551         DPRINTF("\n");
 552
 553         sc->sc_capa_off = 0;
 554         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 555         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
 556         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 557
 558         /* Halt controller */
 559         XWRITE4(sc, oper, XHCI_USBCMD, 0);
 560
 561         for (i = 0; i != 100; i++) {
 562                 usb_pause_mtx(NULL, hz / 100);
 563                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 564                 if (temp)
 565                         break;
 566         }
 567
 568         if (!temp) {
 569                 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
 570                 return (USB_ERR_IOERROR);
 571         }
 572         return (0);
 573 }
 574
 575 usb_error_t
 576 xhci_init(struct xhci_softc *sc, device_t self)
 577 {
 578         uint32_t temp;
 579
 580         DPRINTF("\n");
 581
 582         /* initialise some bus fields */
 583         sc->sc_bus.parent = self;
 584
 585         /* set the bus revision */
 586         sc->sc_bus.usbrev = USB_REV_3_0;
 587
 588         /* set up the bus struct */
 589         sc->sc_bus.methods = &xhci_bus_methods;
 590
 591         /* setup devices array */
 592         sc->sc_bus.devices = sc->sc_devices;
 593         sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
 594
 595         /* set default cycle state in case of early interrupts */
 596         sc->sc_event_ccs = 1;
 597         sc->sc_command_ccs = 1;
 598
 599         /* set up bus space offsets */
 600         sc->sc_capa_off = 0;
 601         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 602         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
 603         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 604
 605         DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
 606         DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
 607         DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
 608
 609         DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
 610
 611         temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
 612
 613         DPRINTF("HCS0 = 0x%08x\n", temp);
 614
 615         /* set up context size */
 616         if (XHCI_HCS0_CSZ(temp)) {
 617                 sc->sc_ctx_is_64_byte = 1;
 618         } else {
 619                 sc->sc_ctx_is_64_byte = 0;
 620         }
 621
 622         /* get DMA bits */
 623         sc->sc_bus.dma_bits = XHCI_HCS0_AC64(temp) ? 64 : 32;
 624
 625         device_printf(self, "%d bytes context size, %d-bit DMA\n",
 626             sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits);
 627
 628         /* get all DMA memory */
 629         if (usb_bus_mem_alloc_all(&sc->sc_bus,
 630             USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
 631                 return (ENOMEM);
 632         }
 633
 634         /* setup command queue mutex and condition varible */
 635         cv_init(&sc->sc_cmd_cv, "CMDQ");
 636         lockinit(&sc->sc_cmd_lock, "CMDQ lock", 0, LK_CANRECURSE);
 637
 638         sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
 639         sc->sc_config_msg[0].bus = &sc->sc_bus;
 640         sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
 641         sc->sc_config_msg[1].bus = &sc->sc_bus;
 642
 643         return (0);
 644 }
 645
 646 void
 647 xhci_uninit(struct xhci_softc *sc)
 648 {
 649         /*
 650          * NOTE: At this point the control transfer process is gone
 651          * and "xhci_configure_msg" is no longer called. Consequently
 652          * waiting for the configuration messages to complete is not
 653          * needed.
 654          */
 655         usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 656
 657         cv_destroy(&sc->sc_cmd_cv);
 658         lockuninit(&sc->sc_cmd_lock);
 659 }
 660
 661 static void
 662 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
 663 {
 664         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 665
 666         switch (state) {
 667         case USB_HW_POWER_SUSPEND:
 668                 DPRINTF("Stopping the XHCI\n");
 669                 xhci_halt_controller(sc);
 670                 break;
 671         case USB_HW_POWER_SHUTDOWN:
 672                 DPRINTF("Stopping the XHCI\n");
 673                 xhci_halt_controller(sc);
 674                 break;
 675         case USB_HW_POWER_RESUME:
 676                 DPRINTF("Starting the XHCI\n");
 677                 xhci_start_controller(sc);
 678                 break;
 679         default:
 680                 break;
 681         }
 682 }
 683
 684 static usb_error_t
 685 xhci_generic_done_sub(struct usb_xfer *xfer)
 686 {
 687         struct xhci_td *td;
 688         struct xhci_td *td_alt_next;
 689         uint32_t len;
 690         uint8_t status;
 691
 692         td = xfer->td_transfer_cache;
 693         td_alt_next = td->alt_next;
 694
 695         if (xfer->aframes != xfer->nframes)
 696                 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
 697
 698         while (1) {
 699
 700                 usb_pc_cpu_invalidate(td->page_cache);
 701
 702                 status = td->status;
 703                 len = td->remainder;
 704
 705                 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
 706                     xfer, (unsigned int)xfer->aframes,
 707                     (unsigned int)xfer->nframes,
 708                     (unsigned int)len, (unsigned int)td->len,
 709                     (unsigned int)status);
 710
 711                 /*
 712                  * Verify the status length and
 713                  * add the length to "frlengths[]":
 714                  */
 715                 if (len > td->len) {
 716                         /* should not happen */
 717                         DPRINTF("Invalid status length, "
 718                             "0x%04x/0x%04x bytes\n", len, td->len);
 719                         status = XHCI_TRB_ERROR_LENGTH;
 720                 } else if (xfer->aframes != xfer->nframes) {
 721                         xfer->frlengths[xfer->aframes] += td->len - len;
 722                 }
 723                 /* Check for last transfer */
 724                 if (((void *)td) == xfer->td_transfer_last) {
 725                         td = NULL;
 726                         break;
 727                 }
 728                 /* Check for transfer error */
 729                 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
 730                     status != XHCI_TRB_ERROR_SUCCESS) {
 731                         /* the transfer is finished */
 732                         td = NULL;
 733                         break;
 734                 }
 735                 /* Check for short transfer */
 736                 if (len > 0) {
 737                         if (xfer->flags_int.short_frames_ok ||
 738                             xfer->flags_int.isochronous_xfr ||
 739                             xfer->flags_int.control_xfr) {
 740                                 /* follow alt next */
 741                                 td = td->alt_next;
 742                         } else {
 743                                 /* the transfer is finished */
 744                                 td = NULL;
 745                         }
 746                         break;
 747                 }
 748                 td = td->obj_next;
 749
 750                 if (td->alt_next != td_alt_next) {
 751                         /* this USB frame is complete */
 752                         break;
 753                 }
 754         }
 755
 756         /* update transfer cache */
 757
 758         xfer->td_transfer_cache = td;
 759
 760         return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
 761             (status != XHCI_TRB_ERROR_SHORT_PKT &&
 762             status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
 763             USB_ERR_NORMAL_COMPLETION);
 764 }
 765
 766 static void
 767 xhci_generic_done(struct usb_xfer *xfer)
 768 {
 769         usb_error_t err = 0;
 770
 771         DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
 772             xfer, xfer->endpoint);
 773
 774         /* reset scanner */
 775
 776         xfer->td_transfer_cache = xfer->td_transfer_first;
 777
 778         if (xfer->flags_int.control_xfr) {
 779
 780                 if (xfer->flags_int.control_hdr)
 781                         err = xhci_generic_done_sub(xfer);
 782
 783                 xfer->aframes = 1;
 784
 785                 if (xfer->td_transfer_cache == NULL)
 786                         goto done;
 787         }
 788
 789         while (xfer->aframes != xfer->nframes) {
 790
 791                 err = xhci_generic_done_sub(xfer);
 792                 xfer->aframes++;
 793
 794                 if (xfer->td_transfer_cache == NULL)
 795                         goto done;
 796         }
 797
 798         if (xfer->flags_int.control_xfr &&
 799             !xfer->flags_int.control_act)
 800                 err = xhci_generic_done_sub(xfer);
 801 done:
 802         /* transfer is complete */
 803         xhci_device_done(xfer, err);
 804 }
 805
 806 static void
 807 xhci_activate_transfer(struct usb_xfer *xfer)
 808 {
 809         struct xhci_td *td;
 810
 811         td = xfer->td_transfer_cache;
 812
 813         usb_pc_cpu_invalidate(td->page_cache);
 814
 815         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 816
 817                 /* activate the transfer */
 818
 819                 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
 820                 usb_pc_cpu_flush(td->page_cache);
 821
 822                 xhci_endpoint_doorbell(xfer);
 823         }
 824 }
 825
 826 static void
 827 xhci_skip_transfer(struct usb_xfer *xfer)
 828 {
 829         struct xhci_td *td;
 830         struct xhci_td *td_last;
 831
 832         td = xfer->td_transfer_cache;
 833         td_last = xfer->td_transfer_last;
 834
 835         td = td->alt_next;
 836
 837         usb_pc_cpu_invalidate(td->page_cache);
 838
 839         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 840
 841                 usb_pc_cpu_invalidate(td_last->page_cache);
 842
 843                 /* copy LINK TRB to current waiting location */
 844
 845                 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
 846                 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
 847                 usb_pc_cpu_flush(td->page_cache);
 848
 849                 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
 850                 usb_pc_cpu_flush(td->page_cache);
 851
 852                 xhci_endpoint_doorbell(xfer);
 853         }
 854 }
 855
 856 /*------------------------------------------------------------------------*
 857  *      xhci_check_transfer
 858  *------------------------------------------------------------------------*/
 859 static void
 860 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
 861 {
 862         struct xhci_endpoint_ext *pepext;
 863         int64_t offset;
 864         uint64_t td_event;
 865         uint32_t temp;
 866         uint32_t remainder;
 867         uint16_t stream_id;
 868         uint16_t i;
 869         uint8_t status;
 870         uint8_t halted;
 871         uint8_t epno;
 872         uint8_t index;
 873
 874         /* decode TRB */
 875         td_event = le64toh(trb->qwTrb0);
 876         temp = le32toh(trb->dwTrb2);
 877
 878         remainder = XHCI_TRB_2_REM_GET(temp);
 879         status = XHCI_TRB_2_ERROR_GET(temp);
 880         stream_id = XHCI_TRB_2_STREAM_GET(temp);
 881
 882         temp = le32toh(trb->dwTrb3);
 883         epno = XHCI_TRB_3_EP_GET(temp);
 884         index = XHCI_TRB_3_SLOT_GET(temp);
 885
 886         /* check if error means halted */
 887         halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
 888             status != XHCI_TRB_ERROR_SUCCESS);
 889
 890         DPRINTF("slot=%u epno=%u stream=%u remainder=%u status=%u\n",
 891             index, epno, stream_id, remainder, status);
 892
 893         if (index > sc->sc_noslot) {
 894                 DPRINTF("Invalid slot.\n");
 895                 return;
 896         }
 897
 898         if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
 899                 DPRINTF("Invalid endpoint.\n");
 900                 return;
 901         }
 902
 903         pepext = &sc->sc_hw.devs[index].endp[epno];
 904
 905         if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS) {
 906                 stream_id = 0;
 907                 DPRINTF("stream_id=0\n");
 908         } else if (stream_id >= XHCI_MAX_STREAMS) {
 909                 DPRINTF("Invalid stream ID.\n");
 910                 return;
 911         }
 912
 913         /* try to find the USB transfer that generated the event */
 914         for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
 915                 struct usb_xfer *xfer;
 916                 struct xhci_td *td;
 917
 918                 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)];
 919                 if (xfer == NULL)
 920                         continue;
 921
 922                 td = xfer->td_transfer_cache;
 923
 924                 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
 925                         (long long)td_event,
 926                         (long long)td->td_self,
 927                         (long long)td->td_self + sizeof(td->td_trb));
 928
 929                 /*
 930                  * NOTE: Some XHCI implementations might not trigger
 931                  * an event on the last LINK TRB so we need to
 932                  * consider both the last and second last event
 933                  * address as conditions for a successful transfer.
 934                  *
 935                  * NOTE: We assume that the XHCI will only trigger one
 936                  * event per chain of TRBs.
 937                  */
 938
 939                 offset = td_event - td->td_self;
 940
 941                 if (offset >= 0 &&
 942                     offset < (int64_t)sizeof(td->td_trb)) {
 943
 944                         usb_pc_cpu_invalidate(td->page_cache);
 945
 946                         /* compute rest of remainder, if any */
 947                         for (i = (offset / 16) + 1; i < td->ntrb; i++) {
 948                                 temp = le32toh(td->td_trb[i].dwTrb2);
 949                                 remainder += XHCI_TRB_2_BYTES_GET(temp);
 950                         }
 951
 952                         DPRINTFN(5, "New remainder: %u\n", remainder);
 953
 954                         /* clear isochronous transfer errors */
 955                         if (xfer->flags_int.isochronous_xfr) {
 956                                 if (halted) {
 957                                         halted = 0;
 958                                         status = XHCI_TRB_ERROR_SUCCESS;
 959                                         remainder = td->len;
 960                                 }
 961                         }
 962
 963                         /* "td->remainder" is verified later */
 964                         td->remainder = remainder;
 965                         td->status = status;
 966
 967                         usb_pc_cpu_flush(td->page_cache);
 968
 969                         /*
 970                          * 1) Last transfer descriptor makes the
 971                          * transfer done
 972                          */
 973                         if (((void *)td) == xfer->td_transfer_last) {
 974                                 DPRINTF("TD is last\n");
 975                                 xhci_generic_done(xfer);
 976                                 break;
 977                         }
 978
 979                         /*
 980                          * 2) Any kind of error makes the transfer
 981                          * done
 982                          */
 983                         if (halted) {
 984                                 DPRINTF("TD has I/O error\n");
 985                                 xhci_generic_done(xfer);
 986                                 break;
 987                         }
 988
 989                         /*
 990                          * 3) If there is no alternate next transfer,
 991                          * a short packet also makes the transfer done
 992                          */
 993                         if (td->remainder > 0) {
 994                                 if (td->alt_next == NULL) {
 995                                         DPRINTF(
 996                                             "short TD has no alternate next\n");
 997                                         xhci_generic_done(xfer);
 998                                         break;
 999                                 }
1000                                 DPRINTF("TD has short pkt\n");
1001                                 if (xfer->flags_int.short_frames_ok ||
1002                                     xfer->flags_int.isochronous_xfr ||
1003                                     xfer->flags_int.control_xfr) {
1004                                         /* follow the alt next */
1005                                         xfer->td_transfer_cache = td->alt_next;
1006                                         xhci_activate_transfer(xfer);
1007                                         break;
1008                                 }
1009                                 xhci_skip_transfer(xfer);
1010                                 xhci_generic_done(xfer);
1011                                 break;
1012                         }
1013
1014                         /*
1015                          * 4) Transfer complete - go to next TD
1016                          */
1017                         DPRINTF("Following next TD\n");
1018                         xfer->td_transfer_cache = td->obj_next;
1019                         xhci_activate_transfer(xfer);
1020                         break;          /* there should only be one match */
1021                 }
1022         }
1023 }
1024
1025 static int
1026 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
1027 {
1028         if (sc->sc_cmd_addr == trb->qwTrb0) {
1029                 DPRINTF("Received command event\n");
1030                 sc->sc_cmd_result[0] = trb->dwTrb2;
1031                 sc->sc_cmd_result[1] = trb->dwTrb3;
1032                 cv_signal(&sc->sc_cmd_cv);
1033                 return (1);     /* command match */
1034         }
1035         return (0);
1036 }
1037
1038 static int
1039 xhci_interrupt_poll(struct xhci_softc *sc)
1040 {
1041         struct usb_page_search buf_res;
1042         struct xhci_hw_root *phwr;
1043         uint64_t addr;
1044         uint32_t temp;
1045         int retval = 0;
1046         uint16_t i;
1047         uint8_t event;
1048         uint8_t j;
1049         uint8_t k;
1050         uint8_t t;
1051
1052         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1053
1054         phwr = buf_res.buffer;
1055
1056         /* Receive any events */
1057
1058         usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1059
1060         i = sc->sc_event_idx;
1061         j = sc->sc_event_ccs;
1062         t = 2;
1063
1064         while (1) {
1065
1066                 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1067
1068                 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1069
1070                 if (j != k)
1071                         break;
1072
1073                 event = XHCI_TRB_3_TYPE_GET(temp);
1074
1075                 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1076                     i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1077                     (long)le32toh(phwr->hwr_events[i].dwTrb2),
1078                     (long)le32toh(phwr->hwr_events[i].dwTrb3));
1079
1080                 switch (event) {
1081                 case XHCI_TRB_EVENT_TRANSFER:
1082                         xhci_check_transfer(sc, &phwr->hwr_events[i]);
1083                         break;
1084                 case XHCI_TRB_EVENT_CMD_COMPLETE:
1085                         retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1086                         break;
1087                 default:
1088                         DPRINTF("Unhandled event = %u\n", event);
1089                         break;
1090                 }
1091
1092                 i++;
1093
1094                 if (i == XHCI_MAX_EVENTS) {
1095                         i = 0;
1096                         j ^= 1;
1097
1098                         /* check for timeout */
1099                         if (!--t)
1100                                 break;
1101                 }
1102         }
1103
1104         sc->sc_event_idx = i;
1105         sc->sc_event_ccs = j;
1106
1107         /*
1108          * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1109          * latched. That means to activate the register we need to
1110          * write both the low and high double word of the 64-bit
1111          * register.
1112          */
1113
1114         addr = buf_res.physaddr;
1115         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1116
1117         /* try to clear busy bit */
1118         addr |= XHCI_ERDP_LO_BUSY;
1119
1120         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1121         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1122
1123         return (retval);
1124 }
1125
1126 static usb_error_t
1127 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1128     uint16_t timeout_ms)
1129 {
1130         struct usb_page_search buf_res;
1131         struct xhci_hw_root *phwr;
1132         uint64_t addr;
1133         uint32_t temp;
1134         uint8_t i;
1135         uint8_t j;
1136         uint8_t timeout = 0;
1137         int err;
1138
1139         XHCI_CMD_ASSERT_LOCKED(sc);
1140
1141         /* get hardware root structure */
1142
1143         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1144
1145         phwr = buf_res.buffer;
1146
1147         /* Queue command */
1148
1149         USB_BUS_LOCK(&sc->sc_bus);
1150 retry:
1151         i = sc->sc_command_idx;
1152         j = sc->sc_command_ccs;
1153
1154         DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1155             i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1156             (long long)le64toh(trb->qwTrb0),
1157             (long)le32toh(trb->dwTrb2),
1158             (long)le32toh(trb->dwTrb3));
1159
1160         phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1161         phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1162
1163         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1164
1165         temp = trb->dwTrb3;
1166
1167         if (j)
1168                 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1169         else
1170                 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1171
1172         temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1173
1174         phwr->hwr_commands[i].dwTrb3 = temp;
1175
1176         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1177
1178         addr = buf_res.physaddr;
1179         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1180
1181         sc->sc_cmd_addr = htole64(addr);
1182
1183         i++;
1184
1185         if (i == (XHCI_MAX_COMMANDS - 1)) {
1186
1187                 if (j) {
1188                         temp = htole32(XHCI_TRB_3_TC_BIT |
1189                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1190                             XHCI_TRB_3_CYCLE_BIT);
1191                 } else {
1192                         temp = htole32(XHCI_TRB_3_TC_BIT |
1193                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1194                 }
1195
1196                 phwr->hwr_commands[i].dwTrb3 = temp;
1197
1198                 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1199
1200                 i = 0;
1201                 j ^= 1;
1202         }
1203
1204         sc->sc_command_idx = i;
1205         sc->sc_command_ccs = j;
1206
1207         XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1208
1209         err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_lock,
1210             USB_MS_TO_TICKS(timeout_ms));
1211
1212         /*
1213          * In some error cases event interrupts are not generated.
1214          * Poll one time to see if the command has completed.
1215          */
1216         if (err != 0 && xhci_interrupt_poll(sc) != 0) {
1217                 DPRINTF("Command was completed when polling\n");
1218                 err = 0;
1219         }
1220         if (err != 0) {
1221                 DPRINTF("Command timeout!\n");
1222                 /*
1223                  * After some weeks of continuous operation, it has
1224                  * been observed that the ASMedia Technology, ASM1042
1225                  * SuperSpeed USB Host Controller can suddenly stop
1226                  * accepting commands via the command queue. Try to
1227                  * first reset the command queue. If that fails do a
1228                  * host controller reset.
1229                  */
1230                 if (timeout == 0 &&
1231                     xhci_reset_command_queue_locked(sc) == 0) {
1232                         temp = le32toh(trb->dwTrb3);
1233
1234                         /*
1235                          * Avoid infinite XHCI reset loops if the set
1236                          * address command fails to respond due to a
1237                          * non-enumerating device:
1238                          */
1239                         if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE &&
1240                             (temp & XHCI_TRB_3_BSR_BIT) == 0) {
1241                                 DPRINTF("Set address timeout\n");
1242                         } else {
1243                                 timeout = 1;
1244                                 goto retry;
1245                         }
1246                 } else {
1247                         DPRINTF("Controller reset!\n");
1248                         usb_bus_reset_async_locked(&sc->sc_bus);
1249                 }
1250                 err = USB_ERR_TIMEOUT;
1251                 trb->dwTrb2 = 0;
1252                 trb->dwTrb3 = 0;
1253         } else {
1254                 temp = le32toh(sc->sc_cmd_result[0]);
1255                 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1256                         err = USB_ERR_IOERROR;
1257
1258                 trb->dwTrb2 = sc->sc_cmd_result[0];
1259                 trb->dwTrb3 = sc->sc_cmd_result[1];
1260         }
1261
1262         USB_BUS_UNLOCK(&sc->sc_bus);
1263
1264         return (err);
1265 }
1266
1267 #if 0
1268 static usb_error_t
1269 xhci_cmd_nop(struct xhci_softc *sc)
1270 {
1271         struct xhci_trb trb;
1272         uint32_t temp;
1273
1274         DPRINTF("\n");
1275
1276         trb.qwTrb0 = 0;
1277         trb.dwTrb2 = 0;
1278         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1279
1280         trb.dwTrb3 = htole32(temp);
1281
1282         return (xhci_do_command(sc, &trb, 100 /* ms */));
1283 }
1284 #endif
1285
1286 static usb_error_t
1287 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1288 {
1289         struct xhci_trb trb;
1290         uint32_t temp;
1291         usb_error_t err;
1292
1293         DPRINTF("\n");
1294
1295         trb.qwTrb0 = 0;
1296         trb.dwTrb2 = 0;
1297         trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1298
1299         err = xhci_do_command(sc, &trb, 100 /* ms */);
1300         if (err)
1301                 goto done;
1302
1303         temp = le32toh(trb.dwTrb3);
1304
1305         *pslot = XHCI_TRB_3_SLOT_GET(temp);
1306
1307 done:
1308         return (err);
1309 }
1310
1311 static usb_error_t
1312 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1313 {
1314         struct xhci_trb trb;
1315         uint32_t temp;
1316
1317         DPRINTF("\n");
1318
1319         trb.qwTrb0 = 0;
1320         trb.dwTrb2 = 0;
1321         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1322             XHCI_TRB_3_SLOT_SET(slot_id);
1323
1324         trb.dwTrb3 = htole32(temp);
1325
1326         return (xhci_do_command(sc, &trb, 100 /* ms */));
1327 }
1328
1329 static usb_error_t
1330 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1331     uint8_t bsr, uint8_t slot_id)
1332 {
1333         struct xhci_trb trb;
1334         uint32_t temp;
1335
1336         DPRINTF("\n");
1337
1338         trb.qwTrb0 = htole64(input_ctx);
1339         trb.dwTrb2 = 0;
1340         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1341             XHCI_TRB_3_SLOT_SET(slot_id);
1342
1343         if (bsr)
1344                 temp |= XHCI_TRB_3_BSR_BIT;
1345
1346         trb.dwTrb3 = htole32(temp);
1347
1348         return (xhci_do_command(sc, &trb, 500 /* ms */));
1349 }
1350
1351 static usb_error_t
1352 xhci_set_address(struct usb_device *udev, struct lock *lock, uint16_t address)
1353 {
1354         struct usb_page_search buf_inp;
1355         struct usb_page_search buf_dev;
1356         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1357         struct xhci_hw_dev *hdev;
1358         struct xhci_dev_ctx *pdev;
1359         struct xhci_endpoint_ext *pepext;
1360         uint32_t temp;
1361         uint16_t mps;
1362         usb_error_t err;
1363         uint8_t index;
1364
1365         /* the root HUB case is not handled here */
1366         if (udev->parent_hub == NULL)
1367                 return (USB_ERR_INVAL);
1368
1369         index = udev->controller_slot_id;
1370
1371         hdev =  &sc->sc_hw.devs[index];
1372
1373         if (lock != NULL)
1374                 lockmgr(lock, LK_RELEASE);
1375
1376         XHCI_CMD_LOCK(sc);
1377
1378         switch (hdev->state) {
1379         case XHCI_ST_DEFAULT:
1380         case XHCI_ST_ENABLED:
1381
1382                 hdev->state = XHCI_ST_ENABLED;
1383
1384                 /* set configure mask to slot and EP0 */
1385                 xhci_configure_mask(udev, 3, 0);
1386
1387                 /* configure input slot context structure */
1388                 err = xhci_configure_device(udev);
1389
1390                 if (err != 0) {
1391                         DPRINTF("Could not configure device\n");
1392                         break;
1393                 }
1394
1395                 /* configure input endpoint context structure */
1396                 switch (udev->speed) {
1397                 case USB_SPEED_LOW:
1398                 case USB_SPEED_FULL:
1399                         mps = 8;
1400                         break;
1401                 case USB_SPEED_HIGH:
1402                         mps = 64;
1403                         break;
1404                 default:
1405                         mps = 512;
1406                         break;
1407                 }
1408
1409                 pepext = xhci_get_endpoint_ext(udev,
1410                     &udev->ctrl_ep_desc);
1411                 err = xhci_configure_endpoint(udev,
1412                     &udev->ctrl_ep_desc, pepext,
1413                     0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT);
1414
1415                 if (err != 0) {
1416                         DPRINTF("Could not configure default endpoint\n");
1417                         break;
1418                 }
1419
1420                 /* execute set address command */
1421                 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1422
1423                 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1424                     (address == 0), index);
1425
1426                 if (err != 0) {
1427                         temp = le32toh(sc->sc_cmd_result[0]);
1428                         if (address == 0 && sc->sc_port_route != NULL &&
1429                             XHCI_TRB_2_ERROR_GET(temp) ==
1430                             XHCI_TRB_ERROR_PARAMETER) {
1431                                 /* LynxPoint XHCI - ports are not switchable */
1432                                 /* Un-route all ports from the XHCI */
1433                                 sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1434                         }
1435                         DPRINTF("Could not set address "
1436                             "for slot %u.\n", index);
1437                         if (address != 0)
1438                                 break;
1439                 }
1440
1441                 /* update device address to new value */
1442
1443                 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1444                 pdev = buf_dev.buffer;
1445                 usb_pc_cpu_invalidate(&hdev->device_pc);
1446
1447                 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1448                 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1449
1450                 /* update device state to new value */
1451
1452                 if (address != 0)
1453                         hdev->state = XHCI_ST_ADDRESSED;
1454                 else
1455                         hdev->state = XHCI_ST_DEFAULT;
1456                 break;
1457
1458         default:
1459                 DPRINTF("Wrong state for set address.\n");
1460                 err = USB_ERR_IOERROR;
1461                 break;
1462         }
1463         XHCI_CMD_UNLOCK(sc);
1464
1465         if (lock != NULL)
1466                 lockmgr(lock, LK_EXCLUSIVE);
1467
1468         return (err);
1469 }
1470
1471 static usb_error_t
1472 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1473     uint8_t deconfigure, uint8_t slot_id)
1474 {
1475         struct xhci_trb trb;
1476         uint32_t temp;
1477
1478         DPRINTF("\n");
1479
1480         trb.qwTrb0 = htole64(input_ctx);
1481         trb.dwTrb2 = 0;
1482         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1483             XHCI_TRB_3_SLOT_SET(slot_id);
1484
1485         if (deconfigure)
1486                 temp |= XHCI_TRB_3_DCEP_BIT;
1487
1488         trb.dwTrb3 = htole32(temp);
1489
1490         return (xhci_do_command(sc, &trb, 100 /* ms */));
1491 }
1492
1493 static usb_error_t
1494 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1495     uint8_t slot_id)
1496 {
1497         struct xhci_trb trb;
1498         uint32_t temp;
1499
1500         DPRINTF("\n");
1501
1502         trb.qwTrb0 = htole64(input_ctx);
1503         trb.dwTrb2 = 0;
1504         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1505             XHCI_TRB_3_SLOT_SET(slot_id);
1506         trb.dwTrb3 = htole32(temp);
1507
1508         return (xhci_do_command(sc, &trb, 100 /* ms */));
1509 }
1510
1511 static usb_error_t
1512 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1513     uint8_t ep_id, uint8_t slot_id)
1514 {
1515         struct xhci_trb trb;
1516         uint32_t temp;
1517
1518         DPRINTF("\n");
1519
1520         trb.qwTrb0 = 0;
1521         trb.dwTrb2 = 0;
1522         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1523             XHCI_TRB_3_SLOT_SET(slot_id) |
1524             XHCI_TRB_3_EP_SET(ep_id);
1525
1526         if (preserve)
1527                 temp |= XHCI_TRB_3_PRSV_BIT;
1528
1529         trb.dwTrb3 = htole32(temp);
1530
1531         return (xhci_do_command(sc, &trb, 100 /* ms */));
1532 }
1533
1534 static usb_error_t
1535 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1536     uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1537 {
1538         struct xhci_trb trb;
1539         uint32_t temp;
1540
1541         DPRINTF("\n");
1542
1543         trb.qwTrb0 = htole64(dequeue_ptr);
1544
1545         temp = XHCI_TRB_2_STREAM_SET(stream_id);
1546         trb.dwTrb2 = htole32(temp);
1547
1548         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1549             XHCI_TRB_3_SLOT_SET(slot_id) |
1550             XHCI_TRB_3_EP_SET(ep_id);
1551         trb.dwTrb3 = htole32(temp);
1552
1553         return (xhci_do_command(sc, &trb, 100 /* ms */));
1554 }
1555
1556 static usb_error_t
1557 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1558     uint8_t ep_id, uint8_t slot_id)
1559 {
1560         struct xhci_trb trb;
1561         uint32_t temp;
1562
1563         DPRINTF("\n");
1564
1565         trb.qwTrb0 = 0;
1566         trb.dwTrb2 = 0;
1567         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1568             XHCI_TRB_3_SLOT_SET(slot_id) |
1569             XHCI_TRB_3_EP_SET(ep_id);
1570
1571         if (suspend)
1572                 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1573
1574         trb.dwTrb3 = htole32(temp);
1575
1576         return (xhci_do_command(sc, &trb, 100 /* ms */));
1577 }
1578
1579 static usb_error_t
1580 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1581 {
1582         struct xhci_trb trb;
1583         uint32_t temp;
1584
1585         DPRINTF("\n");
1586
1587         trb.qwTrb0 = 0;
1588         trb.dwTrb2 = 0;
1589         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1590             XHCI_TRB_3_SLOT_SET(slot_id);
1591
1592         trb.dwTrb3 = htole32(temp);
1593
1594         return (xhci_do_command(sc, &trb, 100 /* ms */));
1595 }
1596
1597 /*------------------------------------------------------------------------*
1598  *      xhci_interrupt - XHCI interrupt handler
1599  *------------------------------------------------------------------------*/
1600 void
1601 xhci_interrupt(struct xhci_softc *sc)
1602 {
1603         uint32_t status;
1604         uint32_t temp;
1605
1606         USB_BUS_LOCK(&sc->sc_bus);
1607
1608         status = XREAD4(sc, oper, XHCI_USBSTS);
1609
1610         /* acknowledge interrupts, if any */
1611         if (status != 0) {
1612                 XWRITE4(sc, oper, XHCI_USBSTS, status);
1613                 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1614         }
1615
1616         temp = XREAD4(sc, runt, XHCI_IMAN(0));
1617
1618         /* force clearing of pending interrupts */
1619         if (temp & XHCI_IMAN_INTR_PEND)
1620                 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1621
1622         /* check for event(s) */
1623         xhci_interrupt_poll(sc);
1624
1625         if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1626             XHCI_STS_HSE | XHCI_STS_HCE)) {
1627
1628                 if (status & XHCI_STS_PCD) {
1629                         xhci_root_intr(sc);
1630                 }
1631
1632                 if (status & XHCI_STS_HCH) {
1633                         kprintf("%s: host controller halted\n",
1634                             __func__);
1635                 }
1636
1637                 if (status & XHCI_STS_HSE) {
1638                         kprintf("%s: host system error\n",
1639                             __func__);
1640                 }
1641
1642                 if (status & XHCI_STS_HCE) {
1643                         kprintf("%s: host controller error\n",
1644                            __func__);
1645                 }
1646         }
1647         USB_BUS_UNLOCK(&sc->sc_bus);
1648 }
1649
1650 /*------------------------------------------------------------------------*
1651  *      xhci_timeout - XHCI timeout handler
1652  *------------------------------------------------------------------------*/
1653 static void
1654 xhci_timeout(void *arg)
1655 {
1656         struct usb_xfer *xfer = arg;
1657
1658         DPRINTF("xfer=%p\n", xfer);
1659
1660         USB_BUS_LOCK_ASSERT(xfer->xroot->bus);
1661
1662         /* transfer is transferred */
1663         xhci_device_done(xfer, USB_ERR_TIMEOUT);
1664 }
1665
1666 static void
1667 xhci_do_poll(struct usb_bus *bus)
1668 {
1669         struct xhci_softc *sc = XHCI_BUS2SC(bus);
1670
1671         USB_BUS_LOCK(&sc->sc_bus);
1672         xhci_interrupt_poll(sc);
1673         USB_BUS_UNLOCK(&sc->sc_bus);
1674 }
1675
1676 static void
1677 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1678 {
1679         struct usb_page_search buf_res;
1680         struct xhci_td *td;
1681         struct xhci_td *td_next;
1682         struct xhci_td *td_alt_next;
1683         struct xhci_td *td_first;
1684         uint32_t buf_offset;
1685         uint32_t average;
1686         uint32_t len_old;
1687         uint32_t npkt_off;
1688         uint32_t dword;
1689         uint8_t shortpkt_old;
1690         uint8_t precompute;
1691         uint8_t x;
1692
1693         td_alt_next = NULL;
1694         buf_offset = 0;
1695         shortpkt_old = temp->shortpkt;
1696         len_old = temp->len;
1697         npkt_off = 0;
1698         precompute = 1;
1699
1700 restart:
1701
1702         td = temp->td;
1703         td_next = td_first = temp->td_next;
1704
1705         while (1) {
1706
1707                 if (temp->len == 0) {
1708
1709                         if (temp->shortpkt)
1710                                 break;
1711
1712                         /* send a Zero Length Packet, ZLP, last */
1713
1714                         temp->shortpkt = 1;
1715                         average = 0;
1716
1717                 } else {
1718
1719                         average = temp->average;
1720
1721                         if (temp->len < average) {
1722                                 if (temp->len % temp->max_packet_size) {
1723                                         temp->shortpkt = 1;
1724                                 }
1725                                 average = temp->len;
1726                         }
1727                 }
1728
1729                 if (td_next == NULL)
1730                         panic("%s: out of XHCI transfer descriptors!", __func__);
1731
1732                 /* get next TD */
1733
1734                 td = td_next;
1735                 td_next = td->obj_next;
1736
1737                 /* check if we are pre-computing */
1738
1739                 if (precompute) {
1740
1741                         /* update remaining length */
1742
1743                         temp->len -= average;
1744
1745                         continue;
1746                 }
1747                 /* fill out current TD */
1748
1749                 td->len = average;
1750                 td->remainder = 0;
1751                 td->status = 0;
1752
1753                 /* update remaining length */
1754
1755                 temp->len -= average;
1756
1757                 /* reset TRB index */
1758
1759                 x = 0;
1760
1761                 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1762                         /* immediate data */
1763
1764                         if (average > 8)
1765                                 average = 8;
1766
1767                         td->td_trb[0].qwTrb0 = 0;
1768
1769                         usbd_copy_out(temp->pc, temp->offset + buf_offset,
1770                            (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1771                            average);
1772
1773                         dword = XHCI_TRB_2_BYTES_SET(8) |
1774                             XHCI_TRB_2_TDSZ_SET(0) |
1775                             XHCI_TRB_2_IRQ_SET(0);
1776
1777                         td->td_trb[0].dwTrb2 = htole32(dword);
1778
1779                         dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1780                           XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1781
1782                         /* check wLength */
1783                         if (td->td_trb[0].qwTrb0 &
1784                            htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1785                                 if (td->td_trb[0].qwTrb0 &
1786                                     htole64(XHCI_TRB_0_DIR_IN_MASK))
1787                                         dword |= XHCI_TRB_3_TRT_IN;
1788                                 else
1789                                         dword |= XHCI_TRB_3_TRT_OUT;
1790                         }
1791
1792                         td->td_trb[0].dwTrb3 = htole32(dword);
1793 #ifdef USB_DEBUG
1794                         xhci_dump_trb(&td->td_trb[x]);
1795 #endif
1796                         x++;
1797
1798                 } else do {
1799
1800                         uint32_t npkt;
1801
1802                         /* fill out buffer pointers */
1803
1804                         if (average == 0) {
1805                                 memset(&buf_res, 0, sizeof(buf_res));
1806                         } else {
1807                                 usbd_get_page(temp->pc, temp->offset +
1808                                     buf_offset, &buf_res);
1809
1810                                 /* get length to end of page */
1811                                 if (buf_res.length > average)
1812                                         buf_res.length = average;
1813
1814                                 /* check for maximum length */
1815                                 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1816                                         buf_res.length = XHCI_TD_PAGE_SIZE;
1817
1818                                 npkt_off += buf_res.length;
1819                         }
1820
1821                         /* setup npkt */
1822                         npkt = (len_old - npkt_off + temp->max_packet_size - 1) /
1823                             temp->max_packet_size;
1824
1825                         if (npkt == 0)
1826                                 npkt = 1;
1827                         else if (npkt > 31)
1828                                 npkt = 31;
1829
1830                         /* fill out TRB's */
1831                         td->td_trb[x].qwTrb0 =
1832                             htole64((uint64_t)buf_res.physaddr);
1833
1834                         dword =
1835                           XHCI_TRB_2_BYTES_SET(buf_res.length) |
1836                           XHCI_TRB_2_TDSZ_SET(npkt) |
1837                           XHCI_TRB_2_IRQ_SET(0);
1838
1839                         td->td_trb[x].dwTrb2 = htole32(dword);
1840
1841                         switch (temp->trb_type) {
1842                         case XHCI_TRB_TYPE_ISOCH:
1843                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1844                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1845                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1846                                 if (td != td_first) {
1847                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1848                                 } else if (temp->do_isoc_sync != 0) {
1849                                         temp->do_isoc_sync = 0;
1850                                         /* wait until "isoc_frame" */
1851                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1852                                             XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1853                                 } else {
1854                                         /* start data transfer at next interval */
1855                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1856                                             XHCI_TRB_3_ISO_SIA_BIT;
1857                                 }
1858                                 if (temp->direction == UE_DIR_IN)
1859                                         dword |= XHCI_TRB_3_ISP_BIT;
1860                                 break;
1861                         case XHCI_TRB_TYPE_DATA_STAGE:
1862                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1863                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE);
1864                                 if (temp->direction == UE_DIR_IN)
1865                                         dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1866                                 /*
1867                                  * Section 3.2.9 in the XHCI
1868                                  * specification about control
1869                                  * transfers says that we should use a
1870                                  * normal-TRB if there are more TRBs
1871                                  * extending the data-stage
1872                                  * TRB. Update the "trb_type".
1873                                  */
1874                                 temp->trb_type = XHCI_TRB_TYPE_NORMAL;
1875                                 break;
1876                         case XHCI_TRB_TYPE_STATUS_STAGE:
1877                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1878                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE);
1879                                 if (temp->direction == UE_DIR_IN)
1880                                         dword |= XHCI_TRB_3_DIR_IN;
1881                                 break;
1882                         default:        /* XHCI_TRB_TYPE_NORMAL */
1883                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1884                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1885                                 if (temp->direction == UE_DIR_IN)
1886                                         dword |= XHCI_TRB_3_ISP_BIT;
1887                                 break;
1888                         }
1889                         td->td_trb[x].dwTrb3 = htole32(dword);
1890
1891                         average -= buf_res.length;
1892                         buf_offset += buf_res.length;
1893 #ifdef USB_DEBUG
1894                         xhci_dump_trb(&td->td_trb[x]);
1895 #endif
1896                         x++;
1897
1898                 } while (average != 0);
1899
1900                 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1901
1902                 /* store number of data TRB's */
1903
1904                 td->ntrb = x;
1905
1906                 DPRINTF("NTRB=%u\n", x);
1907
1908                 /* fill out link TRB */
1909
1910                 if (td_next != NULL) {
1911                         /* link the current TD with the next one */
1912                         td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1913                         DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1914                 } else {
1915                         /* this field will get updated later */
1916                         DPRINTF("NOLINK\n");
1917                 }
1918
1919                 dword = XHCI_TRB_2_IRQ_SET(0);
1920
1921                 td->td_trb[x].dwTrb2 = htole32(dword);
1922
1923                 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1924                     XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT |
1925                     /*
1926                      * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint
1927                      * frame only receives a single short packet event
1928                      * by setting the CHAIN bit in the LINK field. In
1929                      * addition some XHCI controllers have problems
1930                      * sending a ZLP unless the CHAIN-BIT is set in
1931                      * the LINK TRB.
1932                      */
1933                     XHCI_TRB_3_CHAIN_BIT;
1934
1935                 td->td_trb[x].dwTrb3 = htole32(dword);
1936
1937                 td->alt_next = td_alt_next;
1938 #ifdef USB_DEBUG
1939                 xhci_dump_trb(&td->td_trb[x]);
1940 #endif
1941                 usb_pc_cpu_flush(td->page_cache);
1942         }
1943
1944         if (precompute) {
1945                 precompute = 0;
1946
1947                 /* setup alt next pointer, if any */
1948                 if (temp->last_frame) {
1949                         td_alt_next = NULL;
1950                 } else {
1951                         /* we use this field internally */
1952                         td_alt_next = td_next;
1953                 }
1954
1955                 /* restore */
1956                 temp->shortpkt = shortpkt_old;
1957                 temp->len = len_old;
1958                 goto restart;
1959         }
1960
1961         /*
1962          * Remove cycle bit from the first TRB if we are
1963          * stepping them:
1964          */
1965         if (temp->step_td != 0) {
1966                 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1967                 usb_pc_cpu_flush(td_first->page_cache);
1968         }
1969
1970         /* clear TD SIZE to zero, hence this is the last TRB */
1971         /* remove chain bit because this is the last data TRB in the chain */
1972         td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
1973         td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1974         /* remove CHAIN-BIT from last LINK TRB */
1975         td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1976
1977         usb_pc_cpu_flush(td->page_cache);
1978
1979         temp->td = td;
1980         temp->td_next = td_next;
1981 }
1982
1983 static void
1984 xhci_setup_generic_chain(struct usb_xfer *xfer)
1985 {
1986         struct xhci_std_temp temp;
1987         struct xhci_td *td;
1988         uint32_t x;
1989         uint32_t y;
1990         uint8_t mult;
1991
1992         temp.do_isoc_sync = 0;
1993         temp.step_td = 0;
1994         temp.tbc = 0;
1995         temp.tlbpc = 0;
1996         temp.average = xfer->max_hc_frame_size;
1997         temp.max_packet_size = xfer->max_packet_size;
1998         temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
1999         temp.pc = NULL;
2000         temp.last_frame = 0;
2001         temp.offset = 0;
2002         temp.multishort = xfer->flags_int.isochronous_xfr ||
2003             xfer->flags_int.control_xfr ||
2004             xfer->flags_int.short_frames_ok;
2005
2006         /* toggle the DMA set we are using */
2007         xfer->flags_int.curr_dma_set ^= 1;
2008
2009         /* get next DMA set */
2010         td = xfer->td_start[xfer->flags_int.curr_dma_set];
2011
2012         temp.td = NULL;
2013         temp.td_next = td;
2014
2015         xfer->td_transfer_first = td;
2016         xfer->td_transfer_cache = td;
2017
2018         if (xfer->flags_int.isochronous_xfr) {
2019                 uint8_t shift;
2020
2021                 /* compute multiplier for ISOCHRONOUS transfers */
2022                 mult = xfer->endpoint->ecomp ?
2023                     UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes)
2024                     : 0;
2025                 /* check for USB 2.0 multiplier */
2026                 if (mult == 0) {
2027                         mult = (xfer->endpoint->edesc->
2028                             wMaxPacketSize[1] >> 3) & 3;
2029                 }
2030                 /* range check */
2031                 if (mult > 2)
2032                         mult = 3;
2033                 else
2034                         mult++;
2035
2036                 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
2037
2038                 DPRINTF("MFINDEX=0x%08x\n", x);
2039
2040                 switch (usbd_get_speed(xfer->xroot->udev)) {
2041                 case USB_SPEED_FULL:
2042                         shift = 3;
2043                         temp.isoc_delta = 8;    /* 1ms */
2044                         x += temp.isoc_delta - 1;
2045                         x &= ~(temp.isoc_delta - 1);
2046                         break;
2047                 default:
2048                         shift = usbd_xfer_get_fps_shift(xfer);
2049                         temp.isoc_delta = 1U << shift;
2050                         x += temp.isoc_delta - 1;
2051                         x &= ~(temp.isoc_delta - 1);
2052                         /* simple frame load balancing */
2053                         x += xfer->endpoint->usb_uframe;
2054                         break;
2055                 }
2056
2057                 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
2058
2059                 if ((xfer->endpoint->is_synced == 0) ||
2060                     (y < (xfer->nframes << shift)) ||
2061                     (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
2062                         /*
2063                          * If there is data underflow or the pipe
2064                          * queue is empty we schedule the transfer a
2065                          * few frames ahead of the current frame
2066                          * position. Else two isochronous transfers
2067                          * might overlap.
2068                          */
2069                         xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
2070                         xfer->endpoint->is_synced = 1;
2071                         temp.do_isoc_sync = 1;
2072
2073                         DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2074                 }
2075
2076                 /* compute isochronous completion time */
2077
2078                 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
2079
2080                 xfer->isoc_time_complete =
2081                     usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2082                     (y / 8) + (((xfer->nframes << shift) + 7) / 8);
2083
2084                 x = 0;
2085                 temp.isoc_frame = xfer->endpoint->isoc_next;
2086                 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2087
2088                 xfer->endpoint->isoc_next += xfer->nframes << shift;
2089
2090         } else if (xfer->flags_int.control_xfr) {
2091
2092                 /* check if we should prepend a setup message */
2093
2094                 if (xfer->flags_int.control_hdr) {
2095
2096                         temp.len = xfer->frlengths[0];
2097                         temp.pc = xfer->frbuffers + 0;
2098                         temp.shortpkt = temp.len ? 1 : 0;
2099                         temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2100                         temp.direction = 0;
2101
2102                         /* check for last frame */
2103                         if (xfer->nframes == 1) {
2104                                 /* no STATUS stage yet, SETUP is last */
2105                                 if (xfer->flags_int.control_act)
2106                                         temp.last_frame = 1;
2107                         }
2108
2109                         xhci_setup_generic_chain_sub(&temp);
2110                 }
2111                 x = 1;
2112                 mult = 1;
2113                 temp.isoc_delta = 0;
2114                 temp.isoc_frame = 0;
2115                 temp.trb_type = xfer->flags_int.control_did_data ?
2116                     XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE;
2117         } else {
2118                 x = 0;
2119                 mult = 1;
2120                 temp.isoc_delta = 0;
2121                 temp.isoc_frame = 0;
2122                 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2123         }
2124
2125         if (x != xfer->nframes) {
2126                 /* setup page_cache pointer */
2127                 temp.pc = xfer->frbuffers + x;
2128                 /* set endpoint direction */
2129                 temp.direction = UE_GET_DIR(xfer->endpointno);
2130         }
2131
2132         while (x != xfer->nframes) {
2133
2134                 /* DATA0 / DATA1 message */
2135
2136                 temp.len = xfer->frlengths[x];
2137                 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2138                     x != 0 && temp.multishort == 0);
2139
2140                 x++;
2141
2142                 if (x == xfer->nframes) {
2143                         if (xfer->flags_int.control_xfr) {
2144                                 /* no STATUS stage yet, DATA is last */
2145                                 if (xfer->flags_int.control_act)
2146                                         temp.last_frame = 1;
2147                         } else {
2148                                 temp.last_frame = 1;
2149                         }
2150                 }
2151                 if (temp.len == 0) {
2152
2153                         /* make sure that we send an USB packet */
2154
2155                         temp.shortpkt = 0;
2156
2157                         temp.tbc = 0;
2158                         temp.tlbpc = mult - 1;
2159
2160                 } else if (xfer->flags_int.isochronous_xfr) {
2161
2162                         uint8_t tdpc;
2163
2164                         /*
2165                          * Isochronous transfers don't have short
2166                          * packet termination:
2167                          */
2168
2169                         temp.shortpkt = 1;
2170
2171                         /* isochronous transfers have a transfer limit */
2172
2173                         if (temp.len > xfer->max_frame_size)
2174                                 temp.len = xfer->max_frame_size;
2175
2176                         /* compute TD packet count */
2177                         tdpc = (temp.len + xfer->max_packet_size - 1) /
2178                             xfer->max_packet_size;
2179
2180                         temp.tbc = ((tdpc + mult - 1) / mult) - 1;
2181                         temp.tlbpc = (tdpc % mult);
2182
2183                         if (temp.tlbpc == 0)
2184                                 temp.tlbpc = mult - 1;
2185                         else
2186                                 temp.tlbpc--;
2187                 } else {
2188
2189                         /* regular data transfer */
2190
2191                         temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2192                 }
2193
2194                 xhci_setup_generic_chain_sub(&temp);
2195
2196                 if (xfer->flags_int.isochronous_xfr) {
2197                         temp.offset += xfer->frlengths[x - 1];
2198                         temp.isoc_frame += temp.isoc_delta;
2199                 } else {
2200                         /* get next Page Cache pointer */
2201                         temp.pc = xfer->frbuffers + x;
2202                 }
2203         }
2204
2205         /* check if we should append a status stage */
2206
2207         if (xfer->flags_int.control_xfr &&
2208             !xfer->flags_int.control_act) {
2209
2210                 /*
2211                  * Send a DATA1 message and invert the current
2212                  * endpoint direction.
2213                  */
2214                 temp.step_td = (xfer->nframes != 0);
2215                 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2216                 temp.len = 0;
2217                 temp.pc = NULL;
2218                 temp.shortpkt = 0;
2219                 temp.last_frame = 1;
2220                 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2221
2222                 xhci_setup_generic_chain_sub(&temp);
2223         }
2224
2225         td = temp.td;
2226
2227         /* must have at least one frame! */
2228
2229         xfer->td_transfer_last = td;
2230
2231         DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2232 }
2233
2234 static void
2235 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2236 {
2237         struct usb_page_search buf_res;
2238         struct xhci_dev_ctx_addr *pdctxa;
2239
2240         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2241
2242         pdctxa = buf_res.buffer;
2243
2244         DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2245
2246         pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2247
2248         usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2249 }
2250
2251 static usb_error_t
2252 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2253 {
2254         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2255         struct usb_page_search buf_inp;
2256         struct xhci_input_dev_ctx *pinp;
2257         uint32_t temp;
2258         uint8_t index;
2259         uint8_t x;
2260
2261         index = udev->controller_slot_id;
2262
2263         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2264
2265         pinp = buf_inp.buffer;
2266
2267         if (drop) {
2268                 mask &= XHCI_INCTX_NON_CTRL_MASK;
2269                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2270                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2271         } else {
2272                 /*
2273                  * Some hardware requires that we drop the endpoint
2274                  * context before adding it again:
2275                  */
2276                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0,
2277                     mask & XHCI_INCTX_NON_CTRL_MASK);
2278
2279                 /* Add new endpoint context */
2280                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2281
2282                 /* find most significant set bit */
2283                 for (x = 31; x != 1; x--) {
2284                         if (mask & (1 << x))
2285                                 break;
2286                 }
2287
2288                 /* adjust */
2289                 x--;
2290
2291                 /* figure out the maximum number of contexts */
2292                 if (x > sc->sc_hw.devs[index].context_num)
2293                         sc->sc_hw.devs[index].context_num = x;
2294                 else
2295                         x = sc->sc_hw.devs[index].context_num;
2296
2297                 /* update number of contexts */
2298                 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2299                 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2300                 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2301                 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2302         }
2303         usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2304         return (0);
2305 }
2306
2307 static usb_error_t
2308 xhci_configure_endpoint(struct usb_device *udev,
2309     struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext,
2310     uint16_t interval, uint8_t max_packet_count,
2311     uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size,
2312     uint16_t max_frame_size, uint8_t ep_mode)
2313 {
2314         struct usb_page_search buf_inp;
2315         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2316         struct xhci_input_dev_ctx *pinp;
2317         uint64_t ring_addr = pepext->physaddr;
2318         uint32_t temp;
2319         uint8_t index;
2320         uint8_t epno;
2321         uint8_t type;
2322
2323         index = udev->controller_slot_id;
2324
2325         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2326
2327         pinp = buf_inp.buffer;
2328
2329         epno = edesc->bEndpointAddress;
2330         type = edesc->bmAttributes & UE_XFERTYPE;
2331
2332         if (type == UE_CONTROL)
2333                 epno |= UE_DIR_IN;
2334
2335         epno = XHCI_EPNO2EPID(epno);
2336
2337         if (epno == 0)
2338                 return (USB_ERR_NO_PIPE);               /* invalid */
2339
2340         if (max_packet_count == 0)
2341                 return (USB_ERR_BAD_BUFSIZE);
2342
2343         max_packet_count--;
2344
2345         if (mult == 0)
2346                 return (USB_ERR_BAD_BUFSIZE);
2347
2348         /* store endpoint mode */
2349         pepext->trb_ep_mode = ep_mode;
2350         usb_pc_cpu_flush(pepext->page_cache);
2351
2352         if (ep_mode == USB_EP_MODE_STREAMS) {
2353                 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2354                     XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) |
2355                     XHCI_EPCTX_0_LSA_SET(1);
2356
2357                 ring_addr += sizeof(struct xhci_trb) *
2358                     XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS;
2359         } else {
2360                 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2361                     XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2362                     XHCI_EPCTX_0_LSA_SET(0);
2363
2364                 ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2365         }
2366
2367         switch (udev->speed) {
2368         case USB_SPEED_FULL:
2369         case USB_SPEED_LOW:
2370                 /* 1ms -> 125us */
2371                 fps_shift += 3;
2372                 break;
2373         default:
2374                 break;
2375         }
2376
2377         switch (type) {
2378         case UE_INTERRUPT:
2379                 if (fps_shift > 3)
2380                         fps_shift--;
2381                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2382                 break;
2383         case UE_ISOCHRONOUS:
2384                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2385
2386                 switch (udev->speed) {
2387                 case USB_SPEED_SUPER:
2388                         if (mult > 3)
2389                                 mult = 3;
2390                         temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2391                         max_packet_count /= mult;
2392                         break;
2393                 default:
2394                         break;
2395                 }
2396                 break;
2397         default:
2398                 break;
2399         }
2400
2401         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2402
2403         temp =
2404             XHCI_EPCTX_1_HID_SET(0) |
2405             XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2406             XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2407
2408         /*
2409          * Always enable the "three strikes and you are gone" feature
2410          * except for ISOCHRONOUS endpoints. This is suggested by
2411          * section 4.3.3 in the XHCI specification about device slot
2412          * initialisation.
2413          */
2414         if (type != UE_ISOCHRONOUS)
2415                 temp |= XHCI_EPCTX_1_CERR_SET(3);
2416
2417         switch (type) {
2418         case UE_CONTROL:
2419                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2420                 break;
2421         case UE_ISOCHRONOUS:
2422                 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2423                 break;
2424         case UE_BULK:
2425                 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2426                 break;
2427         default:
2428                 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2429                 break;
2430         }
2431
2432         /* check for IN direction */
2433         if (epno & 1)
2434                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2435
2436         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2437         xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2438
2439         switch (edesc->bmAttributes & UE_XFERTYPE) {
2440         case UE_INTERRUPT:
2441         case UE_ISOCHRONOUS:
2442                 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2443                     XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2444                     max_frame_size));
2445                 break;
2446         case UE_CONTROL:
2447                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2448                 break;
2449         default:
2450                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2451                 break;
2452         }
2453
2454         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2455
2456 #ifdef USB_DEBUG
2457         xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2458 #endif
2459         usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2460
2461         return (0);             /* success */
2462 }
2463
2464 static usb_error_t
2465 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2466 {
2467         struct xhci_endpoint_ext *pepext;
2468         struct usb_endpoint_ss_comp_descriptor *ecomp;
2469         usb_stream_t x;
2470
2471         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2472             xfer->endpoint->edesc);
2473
2474         ecomp = xfer->endpoint->ecomp;
2475
2476         for (x = 0; x != XHCI_MAX_STREAMS; x++) {
2477                 uint64_t temp;
2478
2479                 /* halt any transfers */
2480                 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0;
2481
2482                 /* compute start of TRB ring for stream "x" */
2483                 temp = pepext->physaddr +
2484                     (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) +
2485                     XHCI_SCTX_0_SCT_SEC_TR_RING;
2486
2487                 /* make tree structure */
2488                 pepext->trb[(XHCI_MAX_TRANSFERS *
2489                     XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp);
2490
2491                 /* reserved fields */
2492                 pepext->trb[(XHCI_MAX_TRANSFERS *
2493                     XHCI_MAX_STREAMS) + x].dwTrb2 = 0;
2494                 pepext->trb[(XHCI_MAX_TRANSFERS *
2495                     XHCI_MAX_STREAMS) + x].dwTrb3 = 0;
2496         }
2497         usb_pc_cpu_flush(pepext->page_cache);
2498
2499         return (xhci_configure_endpoint(xfer->xroot->udev,
2500             xfer->endpoint->edesc, pepext,
2501             xfer->interval, xfer->max_packet_count,
2502             (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1,
2503             usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2504             xfer->max_frame_size, xfer->endpoint->ep_mode));
2505 }
2506
2507 static usb_error_t
2508 xhci_configure_device(struct usb_device *udev)
2509 {
2510         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2511         struct usb_page_search buf_inp;
2512         struct usb_page_cache *pcinp;
2513         struct xhci_input_dev_ctx *pinp;
2514         struct usb_device *hubdev;
2515         uint32_t temp;
2516         uint32_t route;
2517         uint32_t rh_port;
2518         uint8_t is_hub;
2519         uint8_t index;
2520         uint8_t depth;
2521
2522         index = udev->controller_slot_id;
2523
2524         DPRINTF("index=%u\n", index);
2525
2526         pcinp = &sc->sc_hw.devs[index].input_pc;
2527
2528         usbd_get_page(pcinp, 0, &buf_inp);
2529
2530         pinp = buf_inp.buffer;
2531
2532         rh_port = 0;
2533         route = 0;
2534
2535         /* figure out route string and root HUB port number */
2536
2537         for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2538
2539                 if (hubdev->parent_hub == NULL)
2540                         break;
2541
2542                 depth = hubdev->parent_hub->depth;
2543
2544                 /*
2545                  * NOTE: HS/FS/LS devices and the SS root HUB can have
2546                  * more than 15 ports
2547                  */
2548
2549                 rh_port = hubdev->port_no;
2550
2551                 if (depth == 0)
2552                         break;
2553
2554                 if (rh_port > 15)
2555                         rh_port = 15;
2556
2557                 if (depth < 6)
2558                         route |= rh_port << (4 * (depth - 1));
2559         }
2560
2561         DPRINTF("Route=0x%08x\n", route);
2562
2563         temp = XHCI_SCTX_0_ROUTE_SET(route) |
2564             XHCI_SCTX_0_CTX_NUM_SET(
2565             sc->sc_hw.devs[index].context_num + 1);
2566
2567         switch (udev->speed) {
2568         case USB_SPEED_LOW:
2569                 temp |= XHCI_SCTX_0_SPEED_SET(2);
2570                 if (udev->parent_hs_hub != NULL &&
2571                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2572                     UDPROTO_HSHUBMTT) {
2573                         DPRINTF("Device inherits MTT\n");
2574                         temp |= XHCI_SCTX_0_MTT_SET(1);
2575                 }
2576                 break;
2577         case USB_SPEED_HIGH:
2578                 temp |= XHCI_SCTX_0_SPEED_SET(3);
2579                 if (sc->sc_hw.devs[index].nports != 0 &&
2580                     udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2581                         DPRINTF("HUB supports MTT\n");
2582                         temp |= XHCI_SCTX_0_MTT_SET(1);
2583                 }
2584                 break;
2585         case USB_SPEED_FULL:
2586                 temp |= XHCI_SCTX_0_SPEED_SET(1);
2587                 if (udev->parent_hs_hub != NULL &&
2588                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2589                     UDPROTO_HSHUBMTT) {
2590                         DPRINTF("Device inherits MTT\n");
2591                         temp |= XHCI_SCTX_0_MTT_SET(1);
2592                 }
2593                 break;
2594         default:
2595                 temp |= XHCI_SCTX_0_SPEED_SET(4);
2596                 break;
2597         }
2598
2599         is_hub = sc->sc_hw.devs[index].nports != 0 &&
2600             (udev->speed == USB_SPEED_SUPER ||
2601             udev->speed == USB_SPEED_HIGH);
2602
2603         if (is_hub) {
2604                 temp |= XHCI_SCTX_0_HUB_SET(1);
2605         }
2606
2607         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2608
2609         temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2610
2611         if (is_hub) {
2612                 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2613                     sc->sc_hw.devs[index].nports);
2614         }
2615
2616         switch (udev->speed) {
2617         case USB_SPEED_SUPER:
2618                 switch (sc->sc_hw.devs[index].state) {
2619                 case XHCI_ST_ADDRESSED:
2620                 case XHCI_ST_CONFIGURED:
2621                         /* enable power save */
2622                         temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2623                         break;
2624                 default:
2625                         /* disable power save */
2626                         break;
2627                 }
2628                 break;
2629         default:
2630                 break;
2631         }
2632
2633         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2634
2635         temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2636
2637         if (is_hub) {
2638                 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2639                     sc->sc_hw.devs[index].tt);
2640         }
2641
2642         hubdev = udev->parent_hs_hub;
2643
2644         /* check if we should activate the transaction translator */
2645         switch (udev->speed) {
2646         case USB_SPEED_FULL:
2647         case USB_SPEED_LOW:
2648                 if (hubdev != NULL) {
2649                         temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2650                             hubdev->controller_slot_id);
2651                         temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2652                             udev->hs_port_no);
2653                 }
2654                 break;
2655         default:
2656                 break;
2657         }
2658
2659         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2660
2661         /*
2662          * These fields should be initialized to zero, according to
2663          * XHCI section 6.2.2 - slot context:
2664          */
2665         temp = XHCI_SCTX_3_DEV_ADDR_SET(0) |
2666             XHCI_SCTX_3_SLOT_STATE_SET(0);
2667
2668         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2669
2670 #ifdef USB_DEBUG
2671         xhci_dump_device(sc, &pinp->ctx_slot);
2672 #endif
2673         usb_pc_cpu_flush(pcinp);
2674
2675         return (0);             /* success */
2676 }
2677
2678 static usb_error_t
2679 xhci_alloc_device_ext(struct usb_device *udev)
2680 {
2681         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2682         struct usb_page_search buf_dev;
2683         struct usb_page_search buf_ep;
2684         struct xhci_trb *trb;
2685         struct usb_page_cache *pc;
2686         struct usb_page *pg;
2687         uint64_t addr;
2688         uint8_t index;
2689         uint8_t i;
2690
2691         index = udev->controller_slot_id;
2692
2693         pc = &sc->sc_hw.devs[index].device_pc;
2694         pg = &sc->sc_hw.devs[index].device_pg;
2695
2696         /* need to initialize the page cache */
2697         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2698
2699         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2700             (2 * sizeof(struct xhci_dev_ctx)) :
2701             sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2702                 goto error;
2703
2704         usbd_get_page(pc, 0, &buf_dev);
2705
2706         pc = &sc->sc_hw.devs[index].input_pc;
2707         pg = &sc->sc_hw.devs[index].input_pg;
2708
2709         /* need to initialize the page cache */
2710         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2711
2712         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2713             (2 * sizeof(struct xhci_input_dev_ctx)) :
2714             sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2715                 goto error;
2716         }
2717
2718         /* initialize all endpoint LINK TRBs */
2719
2720         for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2721
2722                 pc = &sc->sc_hw.devs[index].endpoint_pc[i];
2723                 pg = &sc->sc_hw.devs[index].endpoint_pg[i];
2724
2725                 /* need to initialize the page cache */
2726                 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2727
2728                 if (usb_pc_alloc_mem(pc, pg,
2729                     sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) {
2730                         goto error;
2731                 }
2732
2733                 /* lookup endpoint TRB ring */
2734                 usbd_get_page(pc, 0, &buf_ep);
2735
2736                 /* get TRB pointer */
2737                 trb = buf_ep.buffer;
2738                 trb += XHCI_MAX_TRANSFERS - 1;
2739
2740                 /* get TRB start address */
2741                 addr = buf_ep.physaddr;
2742
2743                 /* create LINK TRB */
2744                 trb->qwTrb0 = htole64(addr);
2745                 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2746                 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2747                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2748
2749                 usb_pc_cpu_flush(pc);
2750         }
2751
2752         xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2753
2754         return (0);
2755
2756 error:
2757         xhci_free_device_ext(udev);
2758
2759         return (USB_ERR_NOMEM);
2760 }
2761
2762 static void
2763 xhci_free_device_ext(struct usb_device *udev)
2764 {
2765         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2766         uint8_t index;
2767         uint8_t i;
2768
2769         index = udev->controller_slot_id;
2770         xhci_set_slot_pointer(sc, index, 0);
2771
2772         usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2773         usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2774         for (i = 0; i != XHCI_MAX_ENDPOINTS; i++)
2775                 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]);
2776 }
2777
2778 static struct xhci_endpoint_ext *
2779 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2780 {
2781         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2782         struct xhci_endpoint_ext *pepext;
2783         struct usb_page_cache *pc;
2784         struct usb_page_search buf_ep;
2785         uint8_t epno;
2786         uint8_t index;
2787
2788         epno = edesc->bEndpointAddress;
2789         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2790                 epno |= UE_DIR_IN;
2791
2792         epno = XHCI_EPNO2EPID(epno);
2793
2794         index = udev->controller_slot_id;
2795
2796         pc = &sc->sc_hw.devs[index].endpoint_pc[epno];
2797
2798         usbd_get_page(pc, 0, &buf_ep);
2799
2800         pepext = &sc->sc_hw.devs[index].endp[epno];
2801         pepext->page_cache = pc;
2802         pepext->trb = buf_ep.buffer;
2803         pepext->physaddr = buf_ep.physaddr;
2804
2805         return (pepext);
2806 }
2807
2808 static void
2809 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2810 {
2811         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2812         uint8_t epno;
2813         uint8_t index;
2814
2815         epno = xfer->endpointno;
2816         if (xfer->flags_int.control_xfr)
2817                 epno |= UE_DIR_IN;
2818
2819         epno = XHCI_EPNO2EPID(epno);
2820         index = xfer->xroot->udev->controller_slot_id;
2821
2822         if (xfer->xroot->udev->flags.self_suspended == 0) {
2823                 XWRITE4(sc, door, XHCI_DOORBELL(index),
2824                     epno | XHCI_DB_SID_SET(xfer->stream_id));
2825         }
2826 }
2827
2828 static void
2829 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2830 {
2831         struct xhci_endpoint_ext *pepext;
2832
2833         if (xfer->flags_int.bandwidth_reclaimed) {
2834                 xfer->flags_int.bandwidth_reclaimed = 0;
2835
2836                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2837                     xfer->endpoint->edesc);
2838
2839                 pepext->trb_used[xfer->stream_id]--;
2840
2841                 pepext->xfer[xfer->qh_pos] = NULL;
2842
2843                 if (error && pepext->trb_running != 0) {
2844                         pepext->trb_halted = 1;
2845                         pepext->trb_running = 0;
2846                 }
2847         }
2848 }
2849
2850 static usb_error_t
2851 xhci_transfer_insert(struct usb_xfer *xfer)
2852 {
2853         struct xhci_td *td_first;
2854         struct xhci_td *td_last;
2855         struct xhci_trb *trb_link;
2856         struct xhci_endpoint_ext *pepext;
2857         uint64_t addr;
2858         usb_stream_t id;
2859         uint8_t i;
2860         uint8_t inext;
2861         uint8_t trb_limit;
2862
2863         DPRINTFN(8, "\n");
2864
2865         id = xfer->stream_id;
2866
2867         /* check if already inserted */
2868         if (xfer->flags_int.bandwidth_reclaimed) {
2869                 DPRINTFN(8, "Already in schedule\n");
2870                 return (0);
2871         }
2872
2873         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2874             xfer->endpoint->edesc);
2875
2876         td_first = xfer->td_transfer_first;
2877         td_last = xfer->td_transfer_last;
2878         addr = pepext->physaddr;
2879
2880         switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2881         case UE_CONTROL:
2882         case UE_INTERRUPT:
2883                 /* single buffered */
2884                 trb_limit = 1;
2885                 break;
2886         default:
2887                 /* multi buffered */
2888                 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2889                 break;
2890         }
2891
2892         if (pepext->trb_used[id] >= trb_limit) {
2893                 DPRINTFN(8, "Too many TDs queued.\n");
2894                 return (USB_ERR_NOMEM);
2895         }
2896
2897         /* check for stopped condition, after putting transfer on interrupt queue */
2898         if (pepext->trb_running == 0) {
2899                 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2900
2901                 DPRINTFN(8, "Not running\n");
2902
2903                 /* start configuration */
2904                 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
2905                     &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2906                 return (0);
2907         }
2908
2909         pepext->trb_used[id]++;
2910
2911         /* get current TRB index */
2912         i = pepext->trb_index[id];
2913
2914         /* get next TRB index */
2915         inext = (i + 1);
2916
2917         /* the last entry of the ring is a hardcoded link TRB */
2918         if (inext >= (XHCI_MAX_TRANSFERS - 1))
2919                 inext = 0;
2920
2921         /* store next TRB index, before stream ID offset is added */
2922         pepext->trb_index[id] = inext;
2923
2924         /* offset for stream */
2925         i += id * XHCI_MAX_TRANSFERS;
2926         inext += id * XHCI_MAX_TRANSFERS;
2927
2928         /* compute terminating return address */
2929         addr += (inext * sizeof(struct xhci_trb));
2930
2931         /* compute link TRB pointer */
2932         trb_link = td_last->td_trb + td_last->ntrb;
2933
2934         /* update next pointer of last link TRB */
2935         trb_link->qwTrb0 = htole64(addr);
2936         trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2937         trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2938             XHCI_TRB_3_CYCLE_BIT |
2939             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2940
2941 #ifdef USB_DEBUG
2942         xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2943 #endif
2944         usb_pc_cpu_flush(td_last->page_cache);
2945
2946         /* write ahead chain end marker */
2947
2948         pepext->trb[inext].qwTrb0 = 0;
2949         pepext->trb[inext].dwTrb2 = 0;
2950         pepext->trb[inext].dwTrb3 = 0;
2951
2952         /* update next pointer of link TRB */
2953
2954         pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
2955         pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2956
2957 #ifdef USB_DEBUG
2958         xhci_dump_trb(&pepext->trb[i]);
2959 #endif
2960         usb_pc_cpu_flush(pepext->page_cache);
2961
2962         /* toggle cycle bit which activates the transfer chain */
2963
2964         pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2965             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2966
2967         usb_pc_cpu_flush(pepext->page_cache);
2968
2969         DPRINTF("qh_pos = %u\n", i);
2970
2971         pepext->xfer[i] = xfer;
2972
2973         xfer->qh_pos = i;
2974
2975         xfer->flags_int.bandwidth_reclaimed = 1;
2976
2977         xhci_endpoint_doorbell(xfer);
2978
2979         return (0);
2980 }
2981
2982 static void
2983 xhci_root_intr(struct xhci_softc *sc)
2984 {
2985         uint16_t i;
2986
2987         USB_BUS_LOCK_ASSERT(&sc->sc_bus);
2988
2989         /* clear any old interrupt data */
2990         memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2991
2992         for (i = 1; i <= sc->sc_noport; i++) {
2993                 /* pick out CHANGE bits from the status register */
2994                 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
2995                     XHCI_PS_CSC | XHCI_PS_PEC |
2996                     XHCI_PS_OCC | XHCI_PS_WRC |
2997                     XHCI_PS_PRC | XHCI_PS_PLC |
2998                     XHCI_PS_CEC)) {
2999                         sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
3000                         DPRINTF("port %d changed\n", i);
3001                 }
3002         }
3003         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
3004             sizeof(sc->sc_hub_idata));
3005 }
3006
3007 /*------------------------------------------------------------------------*
3008  *      xhci_device_done - XHCI done handler
3009  *
3010  * NOTE: This function can be called two times in a row on
3011  * the same USB transfer. From close and from interrupt.
3012  *------------------------------------------------------------------------*/
3013 static void
3014 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
3015 {
3016         DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
3017             xfer, xfer->endpoint, error);
3018
3019         /* remove transfer from HW queue */
3020         xhci_transfer_remove(xfer, error);
3021
3022         /* dequeue transfer and start next transfer */
3023         usbd_transfer_done(xfer, error);
3024 }
3025
3026 /*------------------------------------------------------------------------*
3027  * XHCI data transfer support (generic type)
3028  *------------------------------------------------------------------------*/
3029 static void
3030 xhci_device_generic_open(struct usb_xfer *xfer)
3031 {
3032         if (xfer->flags_int.isochronous_xfr) {
3033                 switch (xfer->xroot->udev->speed) {
3034                 case USB_SPEED_FULL:
3035                         break;
3036                 default:
3037                         usb_hs_bandwidth_alloc(xfer);
3038                         break;
3039                 }
3040         }
3041 }
3042
3043 static void
3044 xhci_device_generic_close(struct usb_xfer *xfer)
3045 {
3046         DPRINTF("\n");
3047
3048         xhci_device_done(xfer, USB_ERR_CANCELLED);
3049
3050         if (xfer->flags_int.isochronous_xfr) {
3051                 switch (xfer->xroot->udev->speed) {
3052                 case USB_SPEED_FULL:
3053                         break;
3054                 default:
3055                         usb_hs_bandwidth_free(xfer);
3056                         break;
3057                 }
3058         }
3059 }
3060
3061 static void
3062 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
3063     usb_stream_t stream_id, struct usb_xfer *enter_xfer)
3064 {
3065         struct usb_xfer *xfer;
3066
3067         /* check if there is a current transfer */
3068         xfer = ep->endpoint_q[stream_id].curr;
3069         if (xfer == NULL)
3070                 return;
3071
3072         /*
3073          * Check if the current transfer is started and then pickup
3074          * the next one, if any. Else wait for next start event due to
3075          * block on failure feature.
3076          */
3077         if (!xfer->flags_int.bandwidth_reclaimed)
3078                 return;
3079
3080         xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head);
3081         if (xfer == NULL) {
3082                 /*
3083                  * In case of enter we have to consider that the
3084                  * transfer is queued by the USB core after the enter
3085                  * method is called.
3086                  */
3087                 xfer = enter_xfer;
3088
3089                 if (xfer == NULL)
3090                         return;
3091         }
3092
3093         /* try to multi buffer */
3094         xhci_transfer_insert(xfer);
3095 }
3096
3097 static void
3098 xhci_device_generic_enter(struct usb_xfer *xfer)
3099 {
3100         DPRINTF("\n");
3101
3102         /* setup TD's and QH */
3103         xhci_setup_generic_chain(xfer);
3104
3105         xhci_device_generic_multi_enter(xfer->endpoint,
3106             xfer->stream_id, xfer);
3107 }
3108
3109 static void
3110 xhci_device_generic_start(struct usb_xfer *xfer)
3111 {
3112         DPRINTF("\n");
3113
3114         /* try to insert xfer on HW queue */
3115         xhci_transfer_insert(xfer);
3116
3117         /* try to multi buffer */
3118         xhci_device_generic_multi_enter(xfer->endpoint,
3119             xfer->stream_id, NULL);
3120
3121         /* add transfer last on interrupt queue */
3122         usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3123
3124         /* start timeout, if any */
3125         if (xfer->timeout != 0)
3126                 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
3127 }
3128
3129 static const struct usb_pipe_methods xhci_device_generic_methods =
3130 {
3131         .open = xhci_device_generic_open,
3132         .close = xhci_device_generic_close,
3133         .enter = xhci_device_generic_enter,
3134         .start = xhci_device_generic_start,
3135 };
3136
3137 /*------------------------------------------------------------------------*
3138  * xhci root HUB support
3139  *------------------------------------------------------------------------*
3140  * Simulate a hardware HUB by handling all the necessary requests.
3141  *------------------------------------------------------------------------*/
3142
3143 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3144
3145 static const
3146 struct usb_device_descriptor xhci_devd =
3147 {
3148         .bLength = sizeof(xhci_devd),
3149         .bDescriptorType = UDESC_DEVICE,        /* type */
3150         HSETW(.bcdUSB, 0x0300),                 /* USB version */
3151         .bDeviceClass = UDCLASS_HUB,            /* class */
3152         .bDeviceSubClass = UDSUBCLASS_HUB,      /* subclass */
3153         .bDeviceProtocol = UDPROTO_SSHUB,       /* protocol */
3154         .bMaxPacketSize = 9,                    /* max packet size */
3155         HSETW(.idVendor, 0x0000),               /* vendor */
3156         HSETW(.idProduct, 0x0000),              /* product */
3157         HSETW(.bcdDevice, 0x0100),              /* device version */
3158         .iManufacturer = 1,
3159         .iProduct = 2,
3160         .iSerialNumber = 0,
3161         .bNumConfigurations = 1,                /* # of configurations */
3162 };
3163
3164 static const
3165 struct xhci_bos_desc xhci_bosd = {
3166         .bosd = {
3167                 .bLength = sizeof(xhci_bosd.bosd),
3168                 .bDescriptorType = UDESC_BOS,
3169                 HSETW(.wTotalLength, sizeof(xhci_bosd)),
3170                 .bNumDeviceCaps = 3,
3171         },
3172         .usb2extd = {
3173                 .bLength = sizeof(xhci_bosd.usb2extd),
3174                 .bDescriptorType = 1,
3175                 .bDevCapabilityType = 2,
3176                 .bmAttributes[0] = 2,
3177         },
3178         .usbdcd = {
3179                 .bLength = sizeof(xhci_bosd.usbdcd),
3180                 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
3181                 .bDevCapabilityType = 3,
3182                 .bmAttributes = 0, /* XXX */
3183                 HSETW(.wSpeedsSupported, 0x000C),
3184                 .bFunctionalitySupport = 8,
3185                 .bU1DevExitLat = 255,   /* dummy - not used */
3186                 .wU2DevExitLat = { 0x00, 0x08 },
3187         },
3188         .cidd = {
3189                 .bLength = sizeof(xhci_bosd.cidd),
3190                 .bDescriptorType = 1,
3191                 .bDevCapabilityType = 4,
3192                 .bReserved = 0,
3193                 .bContainerID = 0, /* XXX */
3194         },
3195 };
3196
3197 static const
3198 struct xhci_config_desc xhci_confd = {
3199         .confd = {
3200                 .bLength = sizeof(xhci_confd.confd),
3201                 .bDescriptorType = UDESC_CONFIG,
3202                 .wTotalLength[0] = sizeof(xhci_confd),
3203                 .bNumInterface = 1,
3204                 .bConfigurationValue = 1,
3205                 .iConfiguration = 0,
3206                 .bmAttributes = UC_SELF_POWERED,
3207                 .bMaxPower = 0          /* max power */
3208         },
3209         .ifcd = {
3210                 .bLength = sizeof(xhci_confd.ifcd),
3211                 .bDescriptorType = UDESC_INTERFACE,
3212                 .bNumEndpoints = 1,
3213                 .bInterfaceClass = UICLASS_HUB,
3214                 .bInterfaceSubClass = UISUBCLASS_HUB,
3215                 .bInterfaceProtocol = 0,
3216         },
3217         .endpd = {
3218                 .bLength = sizeof(xhci_confd.endpd),
3219                 .bDescriptorType = UDESC_ENDPOINT,
3220                 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3221                 .bmAttributes = UE_INTERRUPT,
3222                 .wMaxPacketSize[0] = 2,         /* max 15 ports */
3223                 .bInterval = 255,
3224         },
3225         .endpcd = {
3226                 .bLength = sizeof(xhci_confd.endpcd),
3227                 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3228                 .bMaxBurst = 0,
3229                 .bmAttributes = 0,
3230         },
3231 };
3232
3233 static const
3234 struct usb_hub_ss_descriptor xhci_hubd = {
3235         .bLength = sizeof(xhci_hubd),
3236         .bDescriptorType = UDESC_SS_HUB,
3237 };
3238
3239 static usb_error_t
3240 xhci_roothub_exec(struct usb_device *udev,
3241     struct usb_device_request *req, const void **pptr, uint16_t *plength)
3242 {
3243         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3244         const char *str_ptr;
3245         const void *ptr;
3246         uint32_t port;
3247         uint32_t v;
3248         uint16_t len;
3249         uint16_t i;
3250         uint16_t value;
3251         uint16_t index;
3252         uint8_t j;
3253         usb_error_t err;
3254
3255         USB_BUS_LOCK_ASSERT(&sc->sc_bus);
3256
3257         /* buffer reset */
3258         ptr = (const void *)&sc->sc_hub_desc;
3259         len = 0;
3260         err = 0;
3261
3262         value = UGETW(req->wValue);
3263         index = UGETW(req->wIndex);
3264
3265         DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3266             "wValue=0x%04x wIndex=0x%04x\n",
3267             req->bmRequestType, req->bRequest,
3268             UGETW(req->wLength), value, index);
3269
3270 #define C(x,y) ((x) | ((y) << 8))
3271         switch (C(req->bRequest, req->bmRequestType)) {
3272         case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3273         case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3274         case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3275                 /*
3276                  * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3277                  * for the integrated root hub.
3278                  */
3279                 break;
3280         case C(UR_GET_CONFIG, UT_READ_DEVICE):
3281                 len = 1;
3282                 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3283                 break;
3284         case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3285                 switch (value >> 8) {
3286                 case UDESC_DEVICE:
3287                         if ((value & 0xff) != 0) {
3288                                 err = USB_ERR_IOERROR;
3289                                 goto done;
3290                         }
3291                         len = sizeof(xhci_devd);
3292                         ptr = (const void *)&xhci_devd;
3293                         break;
3294
3295                 case UDESC_BOS:
3296                         if ((value & 0xff) != 0) {
3297                                 err = USB_ERR_IOERROR;
3298                                 goto done;
3299                         }
3300                         len = sizeof(xhci_bosd);
3301                         ptr = (const void *)&xhci_bosd;
3302                         break;
3303
3304                 case UDESC_CONFIG:
3305                         if ((value & 0xff) != 0) {
3306                                 err = USB_ERR_IOERROR;
3307                                 goto done;
3308                         }
3309                         len = sizeof(xhci_confd);
3310                         ptr = (const void *)&xhci_confd;
3311                         break;
3312
3313                 case UDESC_STRING:
3314                         switch (value & 0xff) {
3315                         case 0: /* Language table */
3316                                 str_ptr = "\001";
3317                                 break;
3318
3319                         case 1: /* Vendor */
3320                                 str_ptr = sc->sc_vendor;
3321                                 break;
3322
3323                         case 2: /* Product */
3324                                 str_ptr = "XHCI root HUB";
3325                                 break;
3326
3327                         default:
3328                                 str_ptr = "";
3329                                 break;
3330                         }
3331
3332                         len = usb_make_str_desc(
3333                             sc->sc_hub_desc.temp,
3334                             sizeof(sc->sc_hub_desc.temp),
3335                             str_ptr);
3336                         break;
3337
3338                 default:
3339                         err = USB_ERR_IOERROR;
3340                         goto done;
3341                 }
3342                 break;
3343         case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3344                 len = 1;
3345                 sc->sc_hub_desc.temp[0] = 0;
3346                 break;
3347         case C(UR_GET_STATUS, UT_READ_DEVICE):
3348                 len = 2;
3349                 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3350                 break;
3351         case C(UR_GET_STATUS, UT_READ_INTERFACE):
3352         case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3353                 len = 2;
3354                 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3355                 break;
3356         case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3357                 if (value >= XHCI_MAX_DEVICES) {
3358                         err = USB_ERR_IOERROR;
3359                         goto done;
3360                 }
3361                 break;
3362         case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3363                 if (value != 0 && value != 1) {
3364                         err = USB_ERR_IOERROR;
3365                         goto done;
3366                 }
3367                 sc->sc_conf = value;
3368                 break;
3369         case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3370                 break;
3371         case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3372         case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3373         case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3374                 err = USB_ERR_IOERROR;
3375                 goto done;
3376         case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3377                 break;
3378         case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3379                 break;
3380                 /* Hub requests */
3381         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3382                 break;
3383         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3384                 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3385
3386                 if ((index < 1) ||
3387                     (index > sc->sc_noport)) {
3388                         err = USB_ERR_IOERROR;
3389                         goto done;
3390                 }
3391                 port = XHCI_PORTSC(index);
3392
3393                 v = XREAD4(sc, oper, port);
3394                 i = XHCI_PS_PLS_GET(v);
3395                 v &= ~XHCI_PS_CLEAR;
3396
3397                 switch (value) {
3398                 case UHF_C_BH_PORT_RESET:
3399                         XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3400                         break;
3401                 case UHF_C_PORT_CONFIG_ERROR:
3402                         XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3403                         break;
3404                 case UHF_C_PORT_SUSPEND:
3405                 case UHF_C_PORT_LINK_STATE:
3406                         XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3407                         break;
3408                 case UHF_C_PORT_CONNECTION:
3409                         XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3410                         break;
3411                 case UHF_C_PORT_ENABLE:
3412                         XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3413                         break;
3414                 case UHF_C_PORT_OVER_CURRENT:
3415                         XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3416                         break;
3417                 case UHF_C_PORT_RESET:
3418                         XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3419                         break;
3420                 case UHF_PORT_ENABLE:
3421                         XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3422                         break;
3423                 case UHF_PORT_POWER:
3424                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3425                         break;
3426                 case UHF_PORT_INDICATOR:
3427                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3428                         break;
3429                 case UHF_PORT_SUSPEND:
3430
3431                         /* U3 -> U15 */
3432                         if (i == 3) {
3433                                 XWRITE4(sc, oper, port, v |
3434                                     XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3435                         }
3436
3437                         /* wait 20ms for resume sequence to complete */
3438                         usb_pause_mtx(&sc->sc_bus.bus_lock, hz / 50);
3439
3440                         /* U0 */
3441                         XWRITE4(sc, oper, port, v |
3442                             XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3443                         break;
3444                 default:
3445                         err = USB_ERR_IOERROR;
3446                         goto done;
3447                 }
3448                 break;
3449
3450         case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3451                 if ((value & 0xff) != 0) {
3452                         err = USB_ERR_IOERROR;
3453                         goto done;
3454                 }
3455
3456                 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3457
3458                 sc->sc_hub_desc.hubd = xhci_hubd;
3459
3460                 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3461
3462                 if (XHCI_HCS0_PPC(v))
3463                         i = UHD_PWR_INDIVIDUAL;
3464                 else
3465                         i = UHD_PWR_GANGED;
3466
3467                 if (XHCI_HCS0_PIND(v))
3468                         i |= UHD_PORT_IND;
3469
3470                 i |= UHD_OC_INDIVIDUAL;
3471
3472                 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3473
3474                 /* see XHCI section 5.4.9: */
3475                 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3476
3477                 for (j = 1; j <= sc->sc_noport; j++) {
3478
3479                         v = XREAD4(sc, oper, XHCI_PORTSC(j));
3480                         if (v & XHCI_PS_DR) {
3481                                 sc->sc_hub_desc.hubd.
3482                                     DeviceRemovable[j / 8] |= 1U << (j % 8);
3483                         }
3484                 }
3485                 len = sc->sc_hub_desc.hubd.bLength;
3486                 break;
3487
3488         case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3489                 len = 16;
3490                 memset(sc->sc_hub_desc.temp, 0, 16);
3491                 break;
3492
3493         case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3494                 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3495
3496                 if ((index < 1) ||
3497                     (index > sc->sc_noport)) {
3498                         err = USB_ERR_IOERROR;
3499                         goto done;
3500                 }
3501
3502                 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3503
3504                 DPRINTFN(9, "port status=0x%08x\n", v);
3505
3506                 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3507
3508                 switch (XHCI_PS_SPEED_GET(v)) {
3509                 case 3:
3510                         i |= UPS_HIGH_SPEED;
3511                         break;
3512                 case 2:
3513                         i |= UPS_LOW_SPEED;
3514                         break;
3515                 case 1:
3516                         /* FULL speed */
3517                         break;
3518                 default:
3519                         i |= UPS_OTHER_SPEED;
3520                         break;
3521                 }
3522
3523                 if (v & XHCI_PS_CCS)
3524                         i |= UPS_CURRENT_CONNECT_STATUS;
3525                 if (v & XHCI_PS_PED)
3526                         i |= UPS_PORT_ENABLED;
3527                 if (v & XHCI_PS_OCA)
3528                         i |= UPS_OVERCURRENT_INDICATOR;
3529                 if (v & XHCI_PS_PR)
3530                         i |= UPS_RESET;
3531                 if (v & XHCI_PS_PP) {
3532                         /*
3533                          * The USB 3.0 RH is using the
3534                          * USB 2.0's power bit
3535                          */
3536                         i |= UPS_PORT_POWER;
3537                 }
3538                 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3539
3540                 i = 0;
3541                 if (v & XHCI_PS_CSC)
3542                         i |= UPS_C_CONNECT_STATUS;
3543                 if (v & XHCI_PS_PEC)
3544                         i |= UPS_C_PORT_ENABLED;
3545                 if (v & XHCI_PS_OCC)
3546                         i |= UPS_C_OVERCURRENT_INDICATOR;
3547                 if (v & XHCI_PS_WRC)
3548                         i |= UPS_C_BH_PORT_RESET;
3549                 if (v & XHCI_PS_PRC)
3550                         i |= UPS_C_PORT_RESET;
3551                 if (v & XHCI_PS_PLC)
3552                         i |= UPS_C_PORT_LINK_STATE;
3553                 if (v & XHCI_PS_CEC)
3554                         i |= UPS_C_PORT_CONFIG_ERROR;
3555
3556                 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3557                 len = sizeof(sc->sc_hub_desc.ps);
3558                 break;
3559
3560         case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3561                 err = USB_ERR_IOERROR;
3562                 goto done;
3563
3564         case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3565                 break;
3566
3567         case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3568
3569                 i = index >> 8;
3570                 index &= 0x00FF;
3571
3572                 if ((index < 1) ||
3573                     (index > sc->sc_noport)) {
3574                         err = USB_ERR_IOERROR;
3575                         goto done;
3576                 }
3577
3578                 port = XHCI_PORTSC(index);
3579                 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3580
3581                 switch (value) {
3582                 case UHF_PORT_U1_TIMEOUT:
3583                         if (XHCI_PS_SPEED_GET(v) != 4) {
3584                                 err = USB_ERR_IOERROR;
3585                                 goto done;
3586                         }
3587                         port = XHCI_PORTPMSC(index);
3588                         v = XREAD4(sc, oper, port);
3589                         v &= ~XHCI_PM3_U1TO_SET(0xFF);
3590                         v |= XHCI_PM3_U1TO_SET(i);
3591                         XWRITE4(sc, oper, port, v);
3592                         break;
3593                 case UHF_PORT_U2_TIMEOUT:
3594                         if (XHCI_PS_SPEED_GET(v) != 4) {
3595                                 err = USB_ERR_IOERROR;
3596                                 goto done;
3597                         }
3598                         port = XHCI_PORTPMSC(index);
3599                         v = XREAD4(sc, oper, port);
3600                         v &= ~XHCI_PM3_U2TO_SET(0xFF);
3601                         v |= XHCI_PM3_U2TO_SET(i);
3602                         XWRITE4(sc, oper, port, v);
3603                         break;
3604                 case UHF_BH_PORT_RESET:
3605                         XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3606                         break;
3607                 case UHF_PORT_LINK_STATE:
3608                         XWRITE4(sc, oper, port, v |
3609                             XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3610                         /* 4ms settle time */
3611                         usb_pause_mtx(&sc->sc_bus.bus_lock, hz / 250);
3612                         break;
3613                 case UHF_PORT_ENABLE:
3614                         DPRINTFN(3, "set port enable %d\n", index);
3615                         break;
3616                 case UHF_PORT_SUSPEND:
3617                         DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3618                         j = XHCI_PS_SPEED_GET(v);
3619                         if ((j < 1) || (j > 3)) {
3620                                 /* non-supported speed */
3621                                 err = USB_ERR_IOERROR;
3622                                 goto done;
3623                         }
3624                         XWRITE4(sc, oper, port, v |
3625                             XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3626                         break;
3627                 case UHF_PORT_RESET:
3628                         DPRINTFN(6, "reset port %d\n", index);
3629                         XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3630                         break;
3631                 case UHF_PORT_POWER:
3632                         DPRINTFN(3, "set port power %d\n", index);
3633                         XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3634                         break;
3635                 case UHF_PORT_TEST:
3636                         DPRINTFN(3, "set port test %d\n", index);
3637                         break;
3638                 case UHF_PORT_INDICATOR:
3639                         DPRINTFN(3, "set port indicator %d\n", index);
3640
3641                         v &= ~XHCI_PS_PIC_SET(3);
3642                         v |= XHCI_PS_PIC_SET(1);
3643
3644                         XWRITE4(sc, oper, port, v);
3645                         break;
3646                 default:
3647                         err = USB_ERR_IOERROR;
3648                         goto done;
3649                 }
3650                 break;
3651
3652         case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3653         case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3654         case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3655         case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3656                 break;
3657         default:
3658                 err = USB_ERR_IOERROR;
3659                 goto done;
3660         }
3661 done:
3662         *plength = len;
3663         *pptr = ptr;
3664         return (err);
3665 }
3666
3667 static void
3668 xhci_xfer_setup(struct usb_setup_params *parm)
3669 {
3670         struct usb_page_search page_info;
3671         struct usb_page_cache *pc;
3672         struct xhci_softc *sc;
3673         struct usb_xfer *xfer;
3674         void *last_obj;
3675         uint32_t ntd;
3676         uint32_t n;
3677
3678         sc = XHCI_BUS2SC(parm->udev->bus);
3679         xfer = parm->curr_xfer;
3680
3681         /*
3682          * The proof for the "ntd" formula is illustrated like this:
3683          *
3684          * +------------------------------------+
3685          * |                                    |
3686          * |         |remainder ->              |
3687          * |   +-----+---+                      |
3688          * |   | xxx | x | frm 0                |
3689          * |   +-----+---++                     |
3690          * |   | xxx | xx | frm 1               |
3691          * |   +-----+----+                     |
3692          * |            ...                     |
3693          * +------------------------------------+
3694          *
3695          * "xxx" means a completely full USB transfer descriptor
3696          *
3697          * "x" and "xx" means a short USB packet
3698          *
3699          * For the remainder of an USB transfer modulo
3700          * "max_data_length" we need two USB transfer descriptors.
3701          * One to transfer the remaining data and one to finalise with
3702          * a zero length packet in case the "force_short_xfer" flag is
3703          * set. We only need two USB transfer descriptors in the case
3704          * where the transfer length of the first one is a factor of
3705          * "max_frame_size". The rest of the needed USB transfer
3706          * descriptors is given by the buffer size divided by the
3707          * maximum data payload.
3708          */
3709         parm->hc_max_packet_size = 0x400;
3710         parm->hc_max_packet_count = 16 * 3;
3711         parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3712
3713         xfer->flags_int.bdma_enable = 1;
3714
3715         usbd_transfer_setup_sub(parm);
3716
3717         if (xfer->flags_int.isochronous_xfr) {
3718                 ntd = ((1 * xfer->nframes)
3719                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3720         } else if (xfer->flags_int.control_xfr) {
3721                 ntd = ((2 * xfer->nframes) + 1  /* STATUS */
3722                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3723         } else {
3724                 ntd = ((2 * xfer->nframes)
3725                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3726         }
3727
3728 alloc_dma_set:
3729
3730         if (parm->err)
3731                 return;
3732
3733         /*
3734          * Allocate queue heads and transfer descriptors
3735          */
3736         last_obj = NULL;
3737
3738         if (usbd_transfer_setup_sub_malloc(
3739             parm, &pc, sizeof(struct xhci_td),
3740             XHCI_TD_ALIGN, ntd)) {
3741                 parm->err = USB_ERR_NOMEM;
3742                 return;
3743         }
3744         if (parm->buf) {
3745                 for (n = 0; n != ntd; n++) {
3746                         struct xhci_td *td;
3747
3748                         usbd_get_page(pc + n, 0, &page_info);
3749
3750                         td = page_info.buffer;
3751
3752                         /* init TD */
3753                         td->td_self = page_info.physaddr;
3754                         td->obj_next = last_obj;
3755                         td->page_cache = pc + n;
3756
3757                         last_obj = td;
3758
3759                         usb_pc_cpu_flush(pc + n);
3760                 }
3761         }
3762         xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3763
3764         if (!xfer->flags_int.curr_dma_set) {
3765                 xfer->flags_int.curr_dma_set = 1;
3766                 goto alloc_dma_set;
3767         }
3768 }
3769
3770 static usb_error_t
3771 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3772 {
3773         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3774         struct usb_page_search buf_inp;
3775         struct usb_device *udev;
3776         struct xhci_endpoint_ext *pepext;
3777         struct usb_endpoint_descriptor *edesc;
3778         struct usb_page_cache *pcinp;
3779         usb_error_t err;
3780         usb_stream_t stream_id;
3781         uint8_t index;
3782         uint8_t epno;
3783
3784         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3785             xfer->endpoint->edesc);
3786
3787         udev = xfer->xroot->udev;
3788         index = udev->controller_slot_id;
3789
3790         pcinp = &sc->sc_hw.devs[index].input_pc;
3791
3792         usbd_get_page(pcinp, 0, &buf_inp);
3793
3794         edesc = xfer->endpoint->edesc;
3795
3796         epno = edesc->bEndpointAddress;
3797         stream_id = xfer->stream_id;
3798
3799         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3800                 epno |= UE_DIR_IN;
3801
3802         epno = XHCI_EPNO2EPID(epno);
3803
3804         if (epno == 0)
3805                 return (USB_ERR_NO_PIPE);               /* invalid */
3806
3807         XHCI_CMD_LOCK(sc);
3808
3809         /* configure endpoint */
3810
3811         err = xhci_configure_endpoint_by_xfer(xfer);
3812
3813         if (err != 0) {
3814                 XHCI_CMD_UNLOCK(sc);
3815                 return (err);
3816         }
3817
3818         /*
3819          * Get the endpoint into the stopped state according to the
3820          * endpoint context state diagram in the XHCI specification:
3821          */
3822
3823         err = xhci_cmd_stop_ep(sc, 0, epno, index);
3824
3825         if (err != 0)
3826                 DPRINTF("Could not stop endpoint %u\n", epno);
3827
3828         err = xhci_cmd_reset_ep(sc, 0, epno, index);
3829
3830         if (err != 0)
3831                 DPRINTF("Could not reset endpoint %u\n", epno);
3832
3833         err = xhci_cmd_set_tr_dequeue_ptr(sc,
3834             (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) *
3835             XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1),
3836             stream_id, epno, index);
3837
3838         if (err != 0)
3839                 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3840
3841         /*
3842          * Get the endpoint into the running state according to the
3843          * endpoint context state diagram in the XHCI specification:
3844          */
3845
3846         xhci_configure_mask(udev, (1U << epno) | 1U, 0);
3847
3848         err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3849
3850         if (err != 0)
3851                 DPRINTF("Could not configure endpoint %u\n", epno);
3852
3853         err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3854
3855         if (err != 0)
3856                 DPRINTF("Could not configure endpoint %u\n", epno);
3857
3858         XHCI_CMD_UNLOCK(sc);
3859
3860         return (0);
3861 }
3862
3863 static void
3864 xhci_xfer_unsetup(struct usb_xfer *xfer)
3865 {
3866         return;
3867 }
3868
3869 static void
3870 xhci_start_dma_delay(struct usb_xfer *xfer)
3871 {
3872         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3873
3874         /* put transfer on interrupt queue (again) */
3875         usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3876
3877         (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
3878             &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3879 }
3880
3881 static void
3882 xhci_configure_msg(struct usb_proc_msg *pm)
3883 {
3884         struct xhci_softc *sc;
3885         struct xhci_endpoint_ext *pepext;
3886         struct usb_xfer *xfer;
3887
3888         sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3889
3890 restart:
3891         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3892
3893                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3894                     xfer->endpoint->edesc);
3895
3896                 if ((pepext->trb_halted != 0) ||
3897                     (pepext->trb_running == 0)) {
3898
3899                         uint16_t i;
3900
3901                         /* clear halted and running */
3902                         pepext->trb_halted = 0;
3903                         pepext->trb_running = 0;
3904
3905                         /* nuke remaining buffered transfers */
3906
3907                         for (i = 0; i != (XHCI_MAX_TRANSFERS *
3908                             XHCI_MAX_STREAMS); i++) {
3909                                 /*
3910                                  * NOTE: We need to use the timeout
3911                                  * error code here else existing
3912                                  * isochronous clients can get
3913                                  * confused:
3914                                  */
3915                                 if (pepext->xfer[i] != NULL) {
3916                                         xhci_device_done(pepext->xfer[i],
3917                                             USB_ERR_TIMEOUT);
3918                                 }
3919                         }
3920
3921                         /*
3922                          * NOTE: The USB transfer cannot vanish in
3923                          * this state!
3924                          */
3925
3926                         USB_BUS_UNLOCK(&sc->sc_bus);
3927
3928                         xhci_configure_reset_endpoint(xfer);
3929
3930                         USB_BUS_LOCK(&sc->sc_bus);
3931
3932                         /* check if halted is still cleared */
3933                         if (pepext->trb_halted == 0) {
3934                                 pepext->trb_running = 1;
3935                                 memset(pepext->trb_index, 0,
3936                                     sizeof(pepext->trb_index));
3937                         }
3938                         goto restart;
3939                 }
3940
3941                 if (xfer->flags_int.did_dma_delay) {
3942
3943                         /* remove transfer from interrupt queue (again) */
3944                         usbd_transfer_dequeue(xfer);
3945
3946                         /* we are finally done */
3947                         usb_dma_delay_done_cb(xfer);
3948
3949                         /* queue changed - restart */
3950                         goto restart;
3951                 }
3952         }
3953
3954         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3955
3956                 /* try to insert xfer on HW queue */
3957                 xhci_transfer_insert(xfer);
3958
3959                 /* try to multi buffer */
3960                 xhci_device_generic_multi_enter(xfer->endpoint,
3961                     xfer->stream_id, NULL);
3962         }
3963 }
3964
3965 static void
3966 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3967     struct usb_endpoint *ep)
3968 {
3969         struct xhci_endpoint_ext *pepext;
3970
3971         DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
3972             ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
3973
3974         if (udev->parent_hub == NULL) {
3975                 /* root HUB has special endpoint handling */
3976                 return;
3977         }
3978
3979         ep->methods = &xhci_device_generic_methods;
3980
3981         pepext = xhci_get_endpoint_ext(udev, edesc);
3982
3983         USB_BUS_LOCK(udev->bus);
3984         pepext->trb_halted = 1;
3985         pepext->trb_running = 0;
3986         USB_BUS_UNLOCK(udev->bus);
3987 }
3988
3989 static void
3990 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
3991 {
3992
3993 }
3994
3995 static void
3996 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3997 {
3998         struct xhci_endpoint_ext *pepext;
3999
4000         DPRINTF("\n");
4001
4002         if (udev->flags.usb_mode != USB_MODE_HOST) {
4003                 /* not supported */
4004                 return;
4005         }
4006         if (udev->parent_hub == NULL) {
4007                 /* root HUB has special endpoint handling */
4008                 return;
4009         }
4010
4011         pepext = xhci_get_endpoint_ext(udev, ep->edesc);
4012
4013         USB_BUS_LOCK(udev->bus);
4014         pepext->trb_halted = 1;
4015         pepext->trb_running = 0;
4016         USB_BUS_UNLOCK(udev->bus);
4017 }
4018
4019 static usb_error_t
4020 xhci_device_init(struct usb_device *udev)
4021 {
4022         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4023         usb_error_t err;
4024         uint8_t temp;
4025
4026         /* no init for root HUB */
4027         if (udev->parent_hub == NULL)
4028                 return (0);
4029
4030         XHCI_CMD_LOCK(sc);
4031
4032         /* set invalid default */
4033
4034         udev->controller_slot_id = sc->sc_noslot + 1;
4035
4036         /* try to get a new slot ID from the XHCI */
4037
4038         err = xhci_cmd_enable_slot(sc, &temp);
4039
4040         if (err) {
4041                 XHCI_CMD_UNLOCK(sc);
4042                 return (err);
4043         }
4044
4045         if (temp > sc->sc_noslot) {
4046                 XHCI_CMD_UNLOCK(sc);
4047                 return (USB_ERR_BAD_ADDRESS);
4048         }
4049
4050         if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
4051                 DPRINTF("slot %u already allocated.\n", temp);
4052                 XHCI_CMD_UNLOCK(sc);
4053                 return (USB_ERR_BAD_ADDRESS);
4054         }
4055
4056         /* store slot ID for later reference */
4057
4058         udev->controller_slot_id = temp;
4059
4060         /* reset data structure */
4061
4062         memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
4063
4064         /* set mark slot allocated */
4065
4066         sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
4067
4068         err = xhci_alloc_device_ext(udev);
4069
4070         XHCI_CMD_UNLOCK(sc);
4071
4072         /* get device into default state */
4073
4074         if (err == 0)
4075                 err = xhci_set_address(udev, NULL, 0);
4076
4077         return (err);
4078 }
4079
4080 static void
4081 xhci_device_uninit(struct usb_device *udev)
4082 {
4083         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4084         uint8_t index;
4085
4086         /* no init for root HUB */
4087         if (udev->parent_hub == NULL)
4088                 return;
4089
4090         XHCI_CMD_LOCK(sc);
4091
4092         index = udev->controller_slot_id;
4093
4094         if (index <= sc->sc_noslot) {
4095                 xhci_cmd_disable_slot(sc, index);
4096                 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
4097
4098                 /* free device extension */
4099                 xhci_free_device_ext(udev);
4100         }
4101
4102         XHCI_CMD_UNLOCK(sc);
4103 }
4104
4105 static void
4106 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4107 {
4108         /*
4109          * Wait until the hardware has finished any possible use of
4110          * the transfer descriptor(s)
4111          */
4112         *pus = 2048;                    /* microseconds */
4113 }
4114
4115 static void
4116 xhci_device_resume(struct usb_device *udev)
4117 {
4118         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4119         uint8_t index;
4120         uint8_t n;
4121         uint8_t p;
4122
4123         DPRINTF("\n");
4124
4125         /* check for root HUB */
4126         if (udev->parent_hub == NULL)
4127                 return;
4128
4129         index = udev->controller_slot_id;
4130
4131         XHCI_CMD_LOCK(sc);
4132
4133         /* blindly resume all endpoints */
4134
4135         USB_BUS_LOCK(udev->bus);
4136
4137         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4138                 for (p = 0; p != XHCI_MAX_STREAMS; p++) {
4139                         XWRITE4(sc, door, XHCI_DOORBELL(index),
4140                             n | XHCI_DB_SID_SET(p));
4141                 }
4142         }
4143
4144         USB_BUS_UNLOCK(udev->bus);
4145
4146         XHCI_CMD_UNLOCK(sc);
4147 }
4148
4149 static void
4150 xhci_device_suspend(struct usb_device *udev)
4151 {
4152         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4153         uint8_t index;
4154         uint8_t n;
4155         usb_error_t err;
4156
4157         DPRINTF("\n");
4158
4159         /* check for root HUB */
4160         if (udev->parent_hub == NULL)
4161                 return;
4162
4163         index = udev->controller_slot_id;
4164
4165         XHCI_CMD_LOCK(sc);
4166
4167         /* blindly suspend all endpoints */
4168
4169         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4170                 err = xhci_cmd_stop_ep(sc, 1, n, index);
4171                 if (err != 0) {
4172                         DPRINTF("Failed to suspend endpoint "
4173                             "%u on slot %u (ignored).\n", n, index);
4174                 }
4175         }
4176
4177         XHCI_CMD_UNLOCK(sc);
4178 }
4179
4180 static void
4181 xhci_set_hw_power(struct usb_bus *bus)
4182 {
4183         DPRINTF("\n");
4184 }
4185
4186 static void
4187 xhci_device_state_change(struct usb_device *udev)
4188 {
4189         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4190         struct usb_page_search buf_inp;
4191         usb_error_t err;
4192         uint8_t index;
4193
4194         /* check for root HUB */
4195         if (udev->parent_hub == NULL)
4196                 return;
4197
4198         index = udev->controller_slot_id;
4199
4200         DPRINTF("\n");
4201
4202         if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4203                 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4204                     &sc->sc_hw.devs[index].tt);
4205                 if (err != 0)
4206                         sc->sc_hw.devs[index].nports = 0;
4207         }
4208
4209         XHCI_CMD_LOCK(sc);
4210
4211         switch (usb_get_device_state(udev)) {
4212         case USB_STATE_POWERED:
4213                 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4214                         break;
4215
4216                 /* set default state */
4217                 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4218
4219                 /* reset number of contexts */
4220                 sc->sc_hw.devs[index].context_num = 0;
4221
4222                 err = xhci_cmd_reset_dev(sc, index);
4223
4224                 if (err != 0) {
4225                         DPRINTF("Device reset failed "
4226                             "for slot %u.\n", index);
4227                 }
4228                 break;
4229
4230         case USB_STATE_ADDRESSED:
4231                 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4232                         break;
4233
4234                 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4235
4236                 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4237
4238                 if (err) {
4239                         DPRINTF("Failed to deconfigure "
4240                             "slot %u.\n", index);
4241                 }
4242                 break;
4243
4244         case USB_STATE_CONFIGURED:
4245                 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
4246                         break;
4247
4248                 /* set configured state */
4249                 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4250
4251                 /* reset number of contexts */
4252                 sc->sc_hw.devs[index].context_num = 0;
4253
4254                 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4255
4256                 xhci_configure_mask(udev, 3, 0);
4257
4258                 err = xhci_configure_device(udev);
4259                 if (err != 0) {
4260                         DPRINTF("Could not configure device "
4261                             "at slot %u.\n", index);
4262                 }
4263
4264                 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4265                 if (err != 0) {
4266                         DPRINTF("Could not evaluate device "
4267                             "context at slot %u.\n", index);
4268                 }
4269                 break;
4270
4271         default:
4272                 break;
4273         }
4274         XHCI_CMD_UNLOCK(sc);
4275 }
4276
4277 static usb_error_t
4278 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep,
4279     uint8_t ep_mode)
4280 {
4281         switch (ep_mode) {
4282         case USB_EP_MODE_DEFAULT:
4283                 return (0);
4284         case USB_EP_MODE_STREAMS:
4285                 if (xhcistreams == 0 ||
4286                     (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK ||
4287                     udev->speed != USB_SPEED_SUPER)
4288                         return (USB_ERR_INVAL);
4289                 return (0);
4290         default:
4291                 return (USB_ERR_INVAL);
4292         }
4293 }
4294
4295 static const struct usb_bus_methods xhci_bus_methods = {
4296         .endpoint_init = xhci_ep_init,
4297         .endpoint_uninit = xhci_ep_uninit,
4298         .xfer_setup = xhci_xfer_setup,
4299         .xfer_unsetup = xhci_xfer_unsetup,
4300         .get_dma_delay = xhci_get_dma_delay,
4301         .device_init = xhci_device_init,
4302         .device_uninit = xhci_device_uninit,
4303         .device_resume = xhci_device_resume,
4304         .device_suspend = xhci_device_suspend,
4305         .set_hw_power = xhci_set_hw_power,
4306         .roothub_exec = xhci_roothub_exec,
4307         .xfer_poll = xhci_do_poll,
4308         .start_dma_delay = xhci_start_dma_delay,
4309         .set_address = xhci_set_address,
4310         .clear_stall = xhci_ep_clear_stall,
4311         .device_state_change = xhci_device_state_change,
4312         .set_hw_power_sleep = xhci_set_hw_power_sleep,
4313         .set_endpoint_mode = xhci_set_endpoint_mode,
4314 };