2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
37 #include "opt_ifpoll.h"
39 #include <sys/param.h>
41 #include <sys/endian.h>
42 #include <sys/kernel.h>
43 #include <sys/interrupt.h>
45 #include <sys/malloc.h>
46 #include <sys/queue.h>
48 #include <sys/serialize.h>
49 #include <sys/socket.h>
50 #include <sys/sockio.h>
51 #include <sys/sysctl.h>
53 #include <netinet/ip.h>
54 #include <netinet/tcp.h>
57 #include <net/ethernet.h>
59 #include <net/if_arp.h>
60 #include <net/if_dl.h>
61 #include <net/if_media.h>
62 #include <net/if_poll.h>
63 #include <net/if_types.h>
64 #include <net/ifq_var.h>
65 #include <net/toeplitz.h>
66 #include <net/toeplitz2.h>
67 #include <net/vlan/if_vlan_var.h>
68 #include <net/vlan/if_vlan_ether.h>
70 #include <dev/netif/mii_layer/mii.h>
71 #include <dev/netif/mii_layer/miivar.h>
72 #include <dev/netif/mii_layer/brgphyreg.h>
74 #include <bus/pci/pcidevs.h>
75 #include <bus/pci/pcireg.h>
76 #include <bus/pci/pcivar.h>
78 #include <dev/netif/bge/if_bgereg.h>
79 #include <dev/netif/bnx/if_bnxvar.h>
81 /* "device miibus" required. See GENERIC if you get errors here. */
82 #include "miibus_if.h"
84 #define BNX_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
86 #define BNX_INTR_CKINTVL ((10 * hz) / 1000) /* 10ms */
89 #define BNX_RSS_DPRINTF(sc, lvl, fmt, ...) \
91 if (sc->bnx_rss_debug >= lvl) \
92 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
94 #else /* !BNX_RSS_DEBUG */
95 #define BNX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
96 #endif /* BNX_RSS_DEBUG */
98 static const struct bnx_type {
103 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717,
104 "Broadcom BCM5717 Gigabit Ethernet" },
105 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717C,
106 "Broadcom BCM5717C Gigabit Ethernet" },
107 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5718,
108 "Broadcom BCM5718 Gigabit Ethernet" },
109 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5719,
110 "Broadcom BCM5719 Gigabit Ethernet" },
111 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720_ALT,
112 "Broadcom BCM5720 Gigabit Ethernet" },
114 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5725,
115 "Broadcom BCM5725 Gigabit Ethernet" },
116 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5727,
117 "Broadcom BCM5727 Gigabit Ethernet" },
118 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5762,
119 "Broadcom BCM5762 Gigabit Ethernet" },
121 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57761,
122 "Broadcom BCM57761 Gigabit Ethernet" },
123 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57762,
124 "Broadcom BCM57762 Gigabit Ethernet" },
125 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57765,
126 "Broadcom BCM57765 Gigabit Ethernet" },
127 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57766,
128 "Broadcom BCM57766 Gigabit Ethernet" },
129 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57781,
130 "Broadcom BCM57781 Gigabit Ethernet" },
131 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57782,
132 "Broadcom BCM57782 Gigabit Ethernet" },
133 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57785,
134 "Broadcom BCM57785 Gigabit Ethernet" },
135 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57786,
136 "Broadcom BCM57786 Gigabit Ethernet" },
137 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57791,
138 "Broadcom BCM57791 Fast Ethernet" },
139 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57795,
140 "Broadcom BCM57795 Fast Ethernet" },
145 static const int bnx_tx_mailbox[BNX_TX_RING_MAX] = {
146 BGE_MBX_TX_HOST_PROD0_LO,
147 BGE_MBX_TX_HOST_PROD0_HI,
148 BGE_MBX_TX_HOST_PROD1_LO,
149 BGE_MBX_TX_HOST_PROD1_HI
152 #define BNX_IS_JUMBO_CAPABLE(sc) ((sc)->bnx_flags & BNX_FLAG_JUMBO)
153 #define BNX_IS_5717_PLUS(sc) ((sc)->bnx_flags & BNX_FLAG_5717_PLUS)
154 #define BNX_IS_57765_PLUS(sc) ((sc)->bnx_flags & BNX_FLAG_57765_PLUS)
155 #define BNX_IS_57765_FAMILY(sc) \
156 ((sc)->bnx_flags & BNX_FLAG_57765_FAMILY)
158 typedef int (*bnx_eaddr_fcn_t)(struct bnx_softc *, uint8_t[]);
160 static int bnx_probe(device_t);
161 static int bnx_attach(device_t);
162 static int bnx_detach(device_t);
163 static void bnx_shutdown(device_t);
164 static int bnx_suspend(device_t);
165 static int bnx_resume(device_t);
166 static int bnx_miibus_readreg(device_t, int, int);
167 static int bnx_miibus_writereg(device_t, int, int, int);
168 static void bnx_miibus_statchg(device_t);
170 static void bnx_handle_status(struct bnx_softc *);
172 static void bnx_npoll(struct ifnet *, struct ifpoll_info *);
173 static void bnx_npoll_rx(struct ifnet *, void *, int);
174 static void bnx_npoll_tx(struct ifnet *, void *, int);
175 static void bnx_npoll_tx_notag(struct ifnet *, void *, int);
176 static void bnx_npoll_status(struct ifnet *);
177 static void bnx_npoll_status_notag(struct ifnet *);
179 static void bnx_intr_legacy(void *);
180 static void bnx_msi(void *);
181 static void bnx_intr(struct bnx_softc *);
182 static void bnx_msix_status(void *);
183 static void bnx_msix_tx_status(void *);
184 static void bnx_msix_rx(void *);
185 static void bnx_msix_rxtx(void *);
186 static void bnx_enable_intr(struct bnx_softc *);
187 static void bnx_disable_intr(struct bnx_softc *);
188 static void bnx_txeof(struct bnx_tx_ring *, uint16_t);
189 static void bnx_rxeof(struct bnx_rx_ret_ring *, uint16_t, int);
190 static int bnx_alloc_intr(struct bnx_softc *);
191 static int bnx_setup_intr(struct bnx_softc *);
192 static void bnx_free_intr(struct bnx_softc *);
193 static void bnx_teardown_intr(struct bnx_softc *, int);
194 static int bnx_alloc_msix(struct bnx_softc *);
195 static void bnx_free_msix(struct bnx_softc *, boolean_t);
196 static void bnx_check_intr_rxtx(void *);
197 static void bnx_check_intr_rx(void *);
198 static void bnx_check_intr_tx(void *);
199 static void bnx_rx_std_refill_ithread(void *);
200 static void bnx_rx_std_refill(void *, void *);
201 static void bnx_rx_std_refill_sched_ipi(void *);
202 static void bnx_rx_std_refill_stop(void *);
203 static void bnx_rx_std_refill_sched(struct bnx_rx_ret_ring *,
204 struct bnx_rx_std_ring *);
206 static void bnx_start(struct ifnet *, struct ifaltq_subque *);
207 static int bnx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
208 static void bnx_init(void *);
209 static void bnx_stop(struct bnx_softc *);
210 static void bnx_watchdog(struct ifaltq_subque *);
211 static int bnx_ifmedia_upd(struct ifnet *);
212 static void bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *);
213 static void bnx_tick(void *);
214 static void bnx_serialize(struct ifnet *, enum ifnet_serialize);
215 static void bnx_deserialize(struct ifnet *, enum ifnet_serialize);
216 static int bnx_tryserialize(struct ifnet *, enum ifnet_serialize);
218 static void bnx_serialize_assert(struct ifnet *, enum ifnet_serialize,
221 static void bnx_serialize_skipmain(struct bnx_softc *);
222 static void bnx_deserialize_skipmain(struct bnx_softc *sc);
224 static int bnx_alloc_jumbo_mem(struct bnx_softc *);
225 static void bnx_free_jumbo_mem(struct bnx_softc *);
226 static struct bnx_jslot
227 *bnx_jalloc(struct bnx_softc *);
228 static void bnx_jfree(void *);
229 static void bnx_jref(void *);
230 static int bnx_newbuf_std(struct bnx_rx_ret_ring *, int, int);
231 static int bnx_newbuf_jumbo(struct bnx_softc *, int, int);
232 static void bnx_setup_rxdesc_std(struct bnx_rx_std_ring *, int);
233 static void bnx_setup_rxdesc_jumbo(struct bnx_softc *, int);
234 static int bnx_init_rx_ring_std(struct bnx_rx_std_ring *);
235 static void bnx_free_rx_ring_std(struct bnx_rx_std_ring *);
236 static int bnx_init_rx_ring_jumbo(struct bnx_softc *);
237 static void bnx_free_rx_ring_jumbo(struct bnx_softc *);
238 static void bnx_free_tx_ring(struct bnx_tx_ring *);
239 static int bnx_init_tx_ring(struct bnx_tx_ring *);
240 static int bnx_create_tx_ring(struct bnx_tx_ring *);
241 static void bnx_destroy_tx_ring(struct bnx_tx_ring *);
242 static int bnx_create_rx_ret_ring(struct bnx_rx_ret_ring *);
243 static void bnx_destroy_rx_ret_ring(struct bnx_rx_ret_ring *);
244 static int bnx_dma_alloc(device_t);
245 static void bnx_dma_free(struct bnx_softc *);
246 static int bnx_dma_block_alloc(struct bnx_softc *, bus_size_t,
247 bus_dma_tag_t *, bus_dmamap_t *, void **, bus_addr_t *);
248 static void bnx_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
250 bnx_defrag_shortdma(struct mbuf *);
251 static int bnx_encap(struct bnx_tx_ring *, struct mbuf **,
253 static int bnx_setup_tso(struct bnx_tx_ring *, struct mbuf **,
254 uint16_t *, uint16_t *);
255 static void bnx_setup_serialize(struct bnx_softc *);
256 static void bnx_set_tick_cpuid(struct bnx_softc *, boolean_t);
257 static void bnx_setup_ring_cnt(struct bnx_softc *);
259 static struct pktinfo *bnx_rss_info(struct pktinfo *,
260 const struct bge_rx_bd *);
261 static void bnx_init_rss(struct bnx_softc *);
262 static void bnx_reset(struct bnx_softc *);
263 static int bnx_chipinit(struct bnx_softc *);
264 static int bnx_blockinit(struct bnx_softc *);
265 static void bnx_stop_block(struct bnx_softc *, bus_size_t, uint32_t);
266 static void bnx_enable_msi(struct bnx_softc *, boolean_t);
267 static void bnx_setmulti(struct bnx_softc *);
268 static void bnx_setpromisc(struct bnx_softc *);
269 static void bnx_stats_update_regs(struct bnx_softc *);
270 static uint32_t bnx_dma_swap_options(struct bnx_softc *);
272 static uint32_t bnx_readmem_ind(struct bnx_softc *, uint32_t);
273 static void bnx_writemem_ind(struct bnx_softc *, uint32_t, uint32_t);
275 static uint32_t bnx_readreg_ind(struct bnx_softc *, uint32_t);
277 static void bnx_writemem_direct(struct bnx_softc *, uint32_t, uint32_t);
278 static void bnx_writembx(struct bnx_softc *, int, int);
279 static int bnx_read_nvram(struct bnx_softc *, caddr_t, int, int);
280 static uint8_t bnx_eeprom_getbyte(struct bnx_softc *, uint32_t, uint8_t *);
281 static int bnx_read_eeprom(struct bnx_softc *, caddr_t, uint32_t, size_t);
283 static void bnx_tbi_link_upd(struct bnx_softc *, uint32_t);
284 static void bnx_copper_link_upd(struct bnx_softc *, uint32_t);
285 static void bnx_autopoll_link_upd(struct bnx_softc *, uint32_t);
286 static void bnx_link_poll(struct bnx_softc *);
288 static int bnx_get_eaddr_mem(struct bnx_softc *, uint8_t[]);
289 static int bnx_get_eaddr_nvram(struct bnx_softc *, uint8_t[]);
290 static int bnx_get_eaddr_eeprom(struct bnx_softc *, uint8_t[]);
291 static int bnx_get_eaddr(struct bnx_softc *, uint8_t[]);
293 static void bnx_coal_change(struct bnx_softc *);
294 static int bnx_sysctl_force_defrag(SYSCTL_HANDLER_ARGS);
295 static int bnx_sysctl_tx_wreg(SYSCTL_HANDLER_ARGS);
296 static int bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
297 static int bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
298 static int bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS);
299 static int bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS);
300 static int bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS);
301 static int bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS);
302 static int bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *,
305 static int bnx_sysctl_npoll_offset(SYSCTL_HANDLER_ARGS);
306 static int bnx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
307 static int bnx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
309 static int bnx_sysctl_std_refill(SYSCTL_HANDLER_ARGS);
311 static int bnx_msi_enable = 1;
312 static int bnx_msix_enable = 1;
314 static int bnx_rx_rings = 0; /* auto */
315 static int bnx_tx_rings = 0; /* auto */
317 TUNABLE_INT("hw.bnx.msi.enable", &bnx_msi_enable);
318 TUNABLE_INT("hw.bnx.msix.enable", &bnx_msix_enable);
319 TUNABLE_INT("hw.bnx.rx_rings", &bnx_rx_rings);
320 TUNABLE_INT("hw.bnx.tx_rings", &bnx_tx_rings);
322 static device_method_t bnx_methods[] = {
323 /* Device interface */
324 DEVMETHOD(device_probe, bnx_probe),
325 DEVMETHOD(device_attach, bnx_attach),
326 DEVMETHOD(device_detach, bnx_detach),
327 DEVMETHOD(device_shutdown, bnx_shutdown),
328 DEVMETHOD(device_suspend, bnx_suspend),
329 DEVMETHOD(device_resume, bnx_resume),
332 DEVMETHOD(bus_print_child, bus_generic_print_child),
333 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
336 DEVMETHOD(miibus_readreg, bnx_miibus_readreg),
337 DEVMETHOD(miibus_writereg, bnx_miibus_writereg),
338 DEVMETHOD(miibus_statchg, bnx_miibus_statchg),
343 static DEFINE_CLASS_0(bnx, bnx_driver, bnx_methods, sizeof(struct bnx_softc));
344 static devclass_t bnx_devclass;
346 DECLARE_DUMMY_MODULE(if_bnx);
347 DRIVER_MODULE(if_bnx, pci, bnx_driver, bnx_devclass, NULL, NULL);
348 DRIVER_MODULE(miibus, bnx, miibus_driver, miibus_devclass, NULL, NULL);
351 bnx_readmem_ind(struct bnx_softc *sc, uint32_t off)
353 device_t dev = sc->bnx_dev;
356 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
357 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
358 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
363 bnx_writemem_ind(struct bnx_softc *sc, uint32_t off, uint32_t val)
365 device_t dev = sc->bnx_dev;
367 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
368 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
369 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
373 bnx_writemem_direct(struct bnx_softc *sc, uint32_t off, uint32_t val)
375 CSR_WRITE_4(sc, off, val);
379 bnx_writembx(struct bnx_softc *sc, int off, int val)
381 CSR_WRITE_4(sc, off, val);
385 * Read a sequence of bytes from NVRAM.
388 bnx_read_nvram(struct bnx_softc *sc, caddr_t dest, int off, int cnt)
394 * Read a byte of data stored in the EEPROM at address 'addr.' The
395 * BCM570x supports both the traditional bitbang interface and an
396 * auto access interface for reading the EEPROM. We use the auto
400 bnx_eeprom_getbyte(struct bnx_softc *sc, uint32_t addr, uint8_t *dest)
406 * Enable use of auto EEPROM access so we can avoid
407 * having to use the bitbang method.
409 BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
411 /* Reset the EEPROM, load the clock period. */
412 CSR_WRITE_4(sc, BGE_EE_ADDR,
413 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
416 /* Issue the read EEPROM command. */
417 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
419 /* Wait for completion */
420 for(i = 0; i < BNX_TIMEOUT * 10; i++) {
422 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
426 if (i == BNX_TIMEOUT) {
427 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
432 byte = CSR_READ_4(sc, BGE_EE_DATA);
434 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
440 * Read a sequence of bytes from the EEPROM.
443 bnx_read_eeprom(struct bnx_softc *sc, caddr_t dest, uint32_t off, size_t len)
449 for (byte = 0, err = 0, i = 0; i < len; i++) {
450 err = bnx_eeprom_getbyte(sc, off + i, &byte);
460 bnx_miibus_readreg(device_t dev, int phy, int reg)
462 struct bnx_softc *sc = device_get_softc(dev);
466 KASSERT(phy == sc->bnx_phyno,
467 ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
469 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
470 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
471 CSR_WRITE_4(sc, BGE_MI_MODE,
472 sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
476 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
477 BGE_MIPHY(phy) | BGE_MIREG(reg));
479 /* Poll for the PHY register access to complete. */
480 for (i = 0; i < BNX_TIMEOUT; i++) {
482 val = CSR_READ_4(sc, BGE_MI_COMM);
483 if ((val & BGE_MICOMM_BUSY) == 0) {
485 val = CSR_READ_4(sc, BGE_MI_COMM);
489 if (i == BNX_TIMEOUT) {
490 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
491 "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
495 /* Restore the autopoll bit if necessary. */
496 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
497 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
501 if (val & BGE_MICOMM_READFAIL)
504 return (val & 0xFFFF);
508 bnx_miibus_writereg(device_t dev, int phy, int reg, int val)
510 struct bnx_softc *sc = device_get_softc(dev);
513 KASSERT(phy == sc->bnx_phyno,
514 ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
516 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
517 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
518 CSR_WRITE_4(sc, BGE_MI_MODE,
519 sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
523 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
524 BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
526 for (i = 0; i < BNX_TIMEOUT; i++) {
528 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
530 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
534 if (i == BNX_TIMEOUT) {
535 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
536 "(phy %d, reg %d, val %d)\n", phy, reg, val);
539 /* Restore the autopoll bit if necessary. */
540 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
541 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
549 bnx_miibus_statchg(device_t dev)
551 struct bnx_softc *sc;
552 struct mii_data *mii;
554 sc = device_get_softc(dev);
555 mii = device_get_softc(sc->bnx_miibus);
557 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
558 (IFM_ACTIVE | IFM_AVALID)) {
559 switch (IFM_SUBTYPE(mii->mii_media_active)) {
576 if (sc->bnx_link == 0)
579 BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
580 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
581 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
582 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
584 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
587 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
588 BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
590 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
595 * Memory management for jumbo frames.
598 bnx_alloc_jumbo_mem(struct bnx_softc *sc)
600 struct ifnet *ifp = &sc->arpcom.ac_if;
601 struct bnx_jslot *entry;
607 * Create tag for jumbo mbufs.
608 * This is really a bit of a kludge. We allocate a special
609 * jumbo buffer pool which (thanks to the way our DMA
610 * memory allocation works) will consist of contiguous
611 * pages. This means that even though a jumbo buffer might
612 * be larger than a page size, we don't really need to
613 * map it into more than one DMA segment. However, the
614 * default mbuf tag will result in multi-segment mappings,
615 * so we have to create a special jumbo mbuf tag that
616 * lets us get away with mapping the jumbo buffers as
617 * a single segment. I think eventually the driver should
618 * be changed so that it uses ordinary mbufs and cluster
619 * buffers, i.e. jumbo frames can span multiple DMA
620 * descriptors. But that's a project for another day.
624 * Create DMA stuffs for jumbo RX ring.
626 error = bnx_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
627 &sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
628 &sc->bnx_cdata.bnx_rx_jumbo_ring_map,
629 (void *)&sc->bnx_ldata.bnx_rx_jumbo_ring,
630 &sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
632 if_printf(ifp, "could not create jumbo RX ring\n");
637 * Create DMA stuffs for jumbo buffer block.
639 error = bnx_dma_block_alloc(sc, BNX_JMEM,
640 &sc->bnx_cdata.bnx_jumbo_tag,
641 &sc->bnx_cdata.bnx_jumbo_map,
642 (void **)&sc->bnx_ldata.bnx_jumbo_buf,
645 if_printf(ifp, "could not create jumbo buffer\n");
649 SLIST_INIT(&sc->bnx_jfree_listhead);
652 * Now divide it up into 9K pieces and save the addresses
653 * in an array. Note that we play an evil trick here by using
654 * the first few bytes in the buffer to hold the the address
655 * of the softc structure for this interface. This is because
656 * bnx_jfree() needs it, but it is called by the mbuf management
657 * code which will not pass it to us explicitly.
659 for (i = 0, ptr = sc->bnx_ldata.bnx_jumbo_buf; i < BNX_JSLOTS; i++) {
660 entry = &sc->bnx_cdata.bnx_jslots[i];
662 entry->bnx_buf = ptr;
663 entry->bnx_paddr = paddr;
664 entry->bnx_inuse = 0;
666 SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead, entry, jslot_link);
675 bnx_free_jumbo_mem(struct bnx_softc *sc)
677 /* Destroy jumbo RX ring. */
678 bnx_dma_block_free(sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
679 sc->bnx_cdata.bnx_rx_jumbo_ring_map,
680 sc->bnx_ldata.bnx_rx_jumbo_ring);
682 /* Destroy jumbo buffer block. */
683 bnx_dma_block_free(sc->bnx_cdata.bnx_jumbo_tag,
684 sc->bnx_cdata.bnx_jumbo_map,
685 sc->bnx_ldata.bnx_jumbo_buf);
689 * Allocate a jumbo buffer.
691 static struct bnx_jslot *
692 bnx_jalloc(struct bnx_softc *sc)
694 struct bnx_jslot *entry;
696 lwkt_serialize_enter(&sc->bnx_jslot_serializer);
697 entry = SLIST_FIRST(&sc->bnx_jfree_listhead);
699 SLIST_REMOVE_HEAD(&sc->bnx_jfree_listhead, jslot_link);
700 entry->bnx_inuse = 1;
702 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
704 lwkt_serialize_exit(&sc->bnx_jslot_serializer);
709 * Adjust usage count on a jumbo buffer.
714 struct bnx_jslot *entry = (struct bnx_jslot *)arg;
715 struct bnx_softc *sc = entry->bnx_sc;
718 panic("bnx_jref: can't find softc pointer!");
720 if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
721 panic("bnx_jref: asked to reference buffer "
722 "that we don't manage!");
723 } else if (entry->bnx_inuse == 0) {
724 panic("bnx_jref: buffer already free!");
726 atomic_add_int(&entry->bnx_inuse, 1);
731 * Release a jumbo buffer.
736 struct bnx_jslot *entry = (struct bnx_jslot *)arg;
737 struct bnx_softc *sc = entry->bnx_sc;
740 panic("bnx_jfree: can't find softc pointer!");
742 if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
743 panic("bnx_jfree: asked to free buffer that we don't manage!");
744 } else if (entry->bnx_inuse == 0) {
745 panic("bnx_jfree: buffer already free!");
748 * Possible MP race to 0, use the serializer. The atomic insn
749 * is still needed for races against bnx_jref().
751 lwkt_serialize_enter(&sc->bnx_jslot_serializer);
752 atomic_subtract_int(&entry->bnx_inuse, 1);
753 if (entry->bnx_inuse == 0) {
754 SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead,
757 lwkt_serialize_exit(&sc->bnx_jslot_serializer);
763 * Intialize a standard receive ring descriptor.
766 bnx_newbuf_std(struct bnx_rx_ret_ring *ret, int i, int init)
768 struct mbuf *m_new = NULL;
769 bus_dma_segment_t seg;
772 struct bnx_rx_buf *rb;
774 rb = &ret->bnx_std->bnx_rx_std_buf[i];
775 KASSERT(!rb->bnx_rx_refilled, ("RX buf %dth has been refilled", i));
777 m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
782 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
783 m_adj(m_new, ETHER_ALIGN);
785 error = bus_dmamap_load_mbuf_segment(ret->bnx_rx_mtag,
786 ret->bnx_rx_tmpmap, m_new, &seg, 1, &nsegs, BUS_DMA_NOWAIT);
793 bus_dmamap_sync(ret->bnx_rx_mtag, rb->bnx_rx_dmamap,
794 BUS_DMASYNC_POSTREAD);
795 bus_dmamap_unload(ret->bnx_rx_mtag, rb->bnx_rx_dmamap);
798 map = ret->bnx_rx_tmpmap;
799 ret->bnx_rx_tmpmap = rb->bnx_rx_dmamap;
801 rb->bnx_rx_dmamap = map;
802 rb->bnx_rx_mbuf = m_new;
803 rb->bnx_rx_paddr = seg.ds_addr;
804 rb->bnx_rx_len = m_new->m_len;
807 rb->bnx_rx_refilled = 1;
812 bnx_setup_rxdesc_std(struct bnx_rx_std_ring *std, int i)
814 struct bnx_rx_buf *rb;
819 rb = &std->bnx_rx_std_buf[i];
820 KASSERT(rb->bnx_rx_refilled, ("RX buf %dth is not refilled", i));
822 paddr = rb->bnx_rx_paddr;
823 len = rb->bnx_rx_len;
827 rb->bnx_rx_refilled = 0;
829 r = &std->bnx_rx_std_ring[i];
830 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(paddr);
831 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(paddr);
834 r->bge_flags = BGE_RXBDFLAG_END;
838 * Initialize a jumbo receive ring descriptor. This allocates
839 * a jumbo buffer from the pool managed internally by the driver.
842 bnx_newbuf_jumbo(struct bnx_softc *sc, int i, int init)
844 struct mbuf *m_new = NULL;
845 struct bnx_jslot *buf;
848 /* Allocate the mbuf. */
849 MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
853 /* Allocate the jumbo buffer */
854 buf = bnx_jalloc(sc);
860 /* Attach the buffer to the mbuf. */
861 m_new->m_ext.ext_arg = buf;
862 m_new->m_ext.ext_buf = buf->bnx_buf;
863 m_new->m_ext.ext_free = bnx_jfree;
864 m_new->m_ext.ext_ref = bnx_jref;
865 m_new->m_ext.ext_size = BNX_JUMBO_FRAMELEN;
867 m_new->m_flags |= M_EXT;
869 m_new->m_data = m_new->m_ext.ext_buf;
870 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
872 paddr = buf->bnx_paddr;
873 m_adj(m_new, ETHER_ALIGN);
874 paddr += ETHER_ALIGN;
876 /* Save necessary information */
877 sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_rx_mbuf = m_new;
878 sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_rx_paddr = paddr;
880 /* Set up the descriptor. */
881 bnx_setup_rxdesc_jumbo(sc, i);
886 bnx_setup_rxdesc_jumbo(struct bnx_softc *sc, int i)
889 struct bnx_rx_buf *rc;
891 r = &sc->bnx_ldata.bnx_rx_jumbo_ring[i];
892 rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
894 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bnx_rx_paddr);
895 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bnx_rx_paddr);
896 r->bge_len = rc->bnx_rx_mbuf->m_len;
898 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
902 bnx_init_rx_ring_std(struct bnx_rx_std_ring *std)
906 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
907 /* Use the first RX return ring's tmp RX mbuf DMA map */
908 error = bnx_newbuf_std(&std->bnx_sc->bnx_rx_ret_ring[0], i, 1);
911 bnx_setup_rxdesc_std(std, i);
914 std->bnx_rx_std_refill = 0;
915 std->bnx_rx_std_running = 0;
917 lwkt_serialize_handler_enable(&std->bnx_rx_std_serialize);
919 std->bnx_rx_std = BGE_STD_RX_RING_CNT - 1;
920 bnx_writembx(std->bnx_sc, BGE_MBX_RX_STD_PROD_LO, std->bnx_rx_std);
926 bnx_free_rx_ring_std(struct bnx_rx_std_ring *std)
930 lwkt_serialize_handler_disable(&std->bnx_rx_std_serialize);
932 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
933 struct bnx_rx_buf *rb = &std->bnx_rx_std_buf[i];
935 rb->bnx_rx_refilled = 0;
936 if (rb->bnx_rx_mbuf != NULL) {
937 bus_dmamap_unload(std->bnx_rx_mtag, rb->bnx_rx_dmamap);
938 m_freem(rb->bnx_rx_mbuf);
939 rb->bnx_rx_mbuf = NULL;
941 bzero(&std->bnx_rx_std_ring[i], sizeof(struct bge_rx_bd));
946 bnx_init_rx_ring_jumbo(struct bnx_softc *sc)
951 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
952 error = bnx_newbuf_jumbo(sc, i, 1);
957 sc->bnx_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
959 rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
960 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
961 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
963 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
969 bnx_free_rx_ring_jumbo(struct bnx_softc *sc)
973 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
974 struct bnx_rx_buf *rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
976 if (rc->bnx_rx_mbuf != NULL) {
977 m_freem(rc->bnx_rx_mbuf);
978 rc->bnx_rx_mbuf = NULL;
980 bzero(&sc->bnx_ldata.bnx_rx_jumbo_ring[i],
981 sizeof(struct bge_rx_bd));
986 bnx_free_tx_ring(struct bnx_tx_ring *txr)
990 for (i = 0; i < BGE_TX_RING_CNT; i++) {
991 struct bnx_tx_buf *buf = &txr->bnx_tx_buf[i];
993 if (buf->bnx_tx_mbuf != NULL) {
994 bus_dmamap_unload(txr->bnx_tx_mtag,
996 m_freem(buf->bnx_tx_mbuf);
997 buf->bnx_tx_mbuf = NULL;
999 bzero(&txr->bnx_tx_ring[i], sizeof(struct bge_tx_bd));
1001 txr->bnx_tx_saved_considx = BNX_TXCONS_UNSET;
1005 bnx_init_tx_ring(struct bnx_tx_ring *txr)
1007 txr->bnx_tx_cnt = 0;
1008 txr->bnx_tx_saved_considx = 0;
1009 txr->bnx_tx_prodidx = 0;
1011 /* Initialize transmit producer index for host-memory send ring. */
1012 bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, txr->bnx_tx_prodidx);
1018 bnx_setmulti(struct bnx_softc *sc)
1021 struct ifmultiaddr *ifma;
1022 uint32_t hashes[4] = { 0, 0, 0, 0 };
1025 ifp = &sc->arpcom.ac_if;
1027 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1028 for (i = 0; i < 4; i++)
1029 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1033 /* First, zot all the existing filters. */
1034 for (i = 0; i < 4; i++)
1035 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1037 /* Now program new ones. */
1038 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1039 if (ifma->ifma_addr->sa_family != AF_LINK)
1042 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1043 ETHER_ADDR_LEN) & 0x7f;
1044 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1047 for (i = 0; i < 4; i++)
1048 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1052 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1053 * self-test results.
1056 bnx_chipinit(struct bnx_softc *sc)
1058 uint32_t dma_rw_ctl, mode_ctl;
1061 /* Set endian type before we access any non-PCI registers. */
1062 pci_write_config(sc->bnx_dev, BGE_PCI_MISC_CTL,
1063 BGE_INIT | BGE_PCIMISCCTL_TAGGED_STATUS, 4);
1065 /* Clear the MAC control register */
1066 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1069 * Clear the MAC statistics block in the NIC's
1072 for (i = BGE_STATS_BLOCK;
1073 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1074 BNX_MEMWIN_WRITE(sc, i, 0);
1076 for (i = BGE_STATUS_BLOCK;
1077 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1078 BNX_MEMWIN_WRITE(sc, i, 0);
1080 if (BNX_IS_57765_FAMILY(sc)) {
1083 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0) {
1084 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
1085 val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
1087 /* Access the lower 1K of PL PCI-E block registers. */
1088 CSR_WRITE_4(sc, BGE_MODE_CTL,
1089 val | BGE_MODECTL_PCIE_PL_SEL);
1091 val = CSR_READ_4(sc, BGE_PCIE_PL_LO_PHYCTL5);
1092 val |= BGE_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ;
1093 CSR_WRITE_4(sc, BGE_PCIE_PL_LO_PHYCTL5, val);
1095 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1097 if (sc->bnx_chiprev != BGE_CHIPREV_57765_AX) {
1098 /* Fix transmit hangs */
1099 val = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL);
1100 val |= BGE_CPMU_PADRNG_CTL_RDIV2;
1101 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, val);
1103 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
1104 val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
1106 /* Access the lower 1K of DL PCI-E block registers. */
1107 CSR_WRITE_4(sc, BGE_MODE_CTL,
1108 val | BGE_MODECTL_PCIE_DL_SEL);
1110 val = CSR_READ_4(sc, BGE_PCIE_DL_LO_FTSMAX);
1111 val &= ~BGE_PCIE_DL_LO_FTSMAX_MASK;
1112 val |= BGE_PCIE_DL_LO_FTSMAX_VAL;
1113 CSR_WRITE_4(sc, BGE_PCIE_DL_LO_FTSMAX, val);
1115 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1118 val = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK);
1119 val &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK;
1120 val |= BGE_CPMU_LSPD_10MB_MACCLK_6_25;
1121 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, val);
1125 * Set up the PCI DMA control register.
1127 dma_rw_ctl = pci_read_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, 4);
1129 * Disable 32bytes cache alignment for DMA write to host memory
1132 * 64bytes cache alignment for DMA write to host memory is still
1135 dma_rw_ctl |= BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1136 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
1137 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1139 * Enable HW workaround for controllers that misinterpret
1140 * a status tag update and leave interrupts permanently
1143 if (sc->bnx_asicrev != BGE_ASICREV_BCM5717 &&
1144 sc->bnx_asicrev != BGE_ASICREV_BCM5762 &&
1145 !BNX_IS_57765_FAMILY(sc))
1146 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1148 if_printf(&sc->arpcom.ac_if, "DMA read/write %#x\n",
1151 pci_write_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1154 * Set up general mode register.
1156 mode_ctl = bnx_dma_swap_options(sc) | BGE_MODECTL_MAC_ATTN_INTR |
1157 BGE_MODECTL_HOST_SEND_BDS | BGE_MODECTL_TX_NO_PHDR_CSUM;
1158 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1161 * Disable memory write invalidate. Apparently it is not supported
1162 * properly by these devices. Also ensure that INTx isn't disabled,
1163 * as these chips need it even when using MSI.
1165 PCI_CLRBIT(sc->bnx_dev, BGE_PCI_CMD,
1166 (PCIM_CMD_MWRICEN | PCIM_CMD_INTxDIS), 4);
1168 /* Set the timer prescaler (always 66Mhz) */
1169 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1175 bnx_blockinit(struct bnx_softc *sc)
1177 struct bnx_intr_data *intr;
1178 struct bge_rcb *rcb;
1185 * Initialize the memory window pointer register so that
1186 * we can access the first 32K of internal NIC RAM. This will
1187 * allow us to set up the TX send ring RCBs and the RX return
1188 * ring RCBs, plus other things which live in NIC memory.
1190 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1192 /* Configure mbuf pool watermarks */
1193 if (BNX_IS_57765_PLUS(sc)) {
1194 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1195 if (sc->arpcom.ac_if.if_mtu > ETHERMTU) {
1196 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1197 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1199 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1200 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1203 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1204 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1205 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1208 /* Configure DMA resource watermarks */
1209 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1210 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1212 /* Enable buffer manager */
1213 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
1215 * Change the arbitration algorithm of TXMBUF read request to
1216 * round-robin instead of priority based for BCM5719. When
1217 * TXFIFO is almost empty, RDMA will hold its request until
1218 * TXFIFO is not almost empty.
1220 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719)
1221 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
1222 if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1223 sc->bnx_chipid == BGE_CHIPID_BCM5719_A0 ||
1224 sc->bnx_chipid == BGE_CHIPID_BCM5720_A0)
1225 val |= BGE_BMANMODE_LOMBUF_ATTN;
1226 CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
1228 /* Poll for buffer manager start indication */
1229 for (i = 0; i < BNX_TIMEOUT; i++) {
1230 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1235 if (i == BNX_TIMEOUT) {
1236 if_printf(&sc->arpcom.ac_if,
1237 "buffer manager failed to start\n");
1241 /* Enable flow-through queues */
1242 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1243 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1245 /* Wait until queue initialization is complete */
1246 for (i = 0; i < BNX_TIMEOUT; i++) {
1247 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1252 if (i == BNX_TIMEOUT) {
1253 if_printf(&sc->arpcom.ac_if,
1254 "flow-through queue init failed\n");
1259 * Summary of rings supported by the controller:
1261 * Standard Receive Producer Ring
1262 * - This ring is used to feed receive buffers for "standard"
1263 * sized frames (typically 1536 bytes) to the controller.
1265 * Jumbo Receive Producer Ring
1266 * - This ring is used to feed receive buffers for jumbo sized
1267 * frames (i.e. anything bigger than the "standard" frames)
1268 * to the controller.
1270 * Mini Receive Producer Ring
1271 * - This ring is used to feed receive buffers for "mini"
1272 * sized frames to the controller.
1273 * - This feature required external memory for the controller
1274 * but was never used in a production system. Should always
1277 * Receive Return Ring
1278 * - After the controller has placed an incoming frame into a
1279 * receive buffer that buffer is moved into a receive return
1280 * ring. The driver is then responsible to passing the
1281 * buffer up to the stack. BCM5718/BCM57785 families support
1282 * multiple receive return rings.
1285 * - This ring is used for outgoing frames. BCM5719/BCM5720
1286 * support multiple send rings.
1289 /* Initialize the standard receive producer ring control block. */
1290 rcb = &sc->bnx_ldata.bnx_info.bnx_std_rx_rcb;
1291 rcb->bge_hostaddr.bge_addr_lo =
1292 BGE_ADDR_LO(sc->bnx_rx_std_ring.bnx_rx_std_ring_paddr);
1293 rcb->bge_hostaddr.bge_addr_hi =
1294 BGE_ADDR_HI(sc->bnx_rx_std_ring.bnx_rx_std_ring_paddr);
1295 if (BNX_IS_57765_PLUS(sc)) {
1297 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
1298 * Bits 15-2 : Maximum RX frame size
1299 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled
1302 rcb->bge_maxlen_flags =
1303 BGE_RCB_MAXLEN_FLAGS(512, BNX_MAX_FRAMELEN << 2);
1306 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1307 * Bits 15-2 : Reserved (should be 0)
1308 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
1311 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1313 if (BNX_IS_5717_PLUS(sc))
1314 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
1316 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1317 /* Write the standard receive producer ring control block. */
1318 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1319 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1320 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1321 if (!BNX_IS_5717_PLUS(sc))
1322 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1323 /* Reset the standard receive producer ring producer index. */
1324 bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1327 * Initialize the jumbo RX producer ring control
1328 * block. We set the 'ring disabled' bit in the
1329 * flags field until we're actually ready to start
1330 * using this ring (i.e. once we set the MTU
1331 * high enough to require it).
1333 if (BNX_IS_JUMBO_CAPABLE(sc)) {
1334 rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
1335 /* Get the jumbo receive producer ring RCB parameters. */
1336 rcb->bge_hostaddr.bge_addr_lo =
1337 BGE_ADDR_LO(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1338 rcb->bge_hostaddr.bge_addr_hi =
1339 BGE_ADDR_HI(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1340 rcb->bge_maxlen_flags =
1341 BGE_RCB_MAXLEN_FLAGS(BNX_MAX_FRAMELEN,
1342 BGE_RCB_FLAG_RING_DISABLED);
1343 if (BNX_IS_5717_PLUS(sc))
1344 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
1346 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1347 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1348 rcb->bge_hostaddr.bge_addr_hi);
1349 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1350 rcb->bge_hostaddr.bge_addr_lo);
1351 /* Program the jumbo receive producer ring RCB parameters. */
1352 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1353 rcb->bge_maxlen_flags);
1354 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1355 /* Reset the jumbo receive producer ring producer index. */
1356 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1360 * The BD ring replenish thresholds control how often the
1361 * hardware fetches new BD's from the producer rings in host
1362 * memory. Setting the value too low on a busy system can
1363 * starve the hardware and recue the throughpout.
1365 * Set the BD ring replentish thresholds. The recommended
1366 * values are 1/8th the number of descriptors allocated to
1370 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1371 if (BNX_IS_JUMBO_CAPABLE(sc)) {
1372 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1373 BGE_JUMBO_RX_RING_CNT/8);
1375 if (BNX_IS_57765_PLUS(sc)) {
1376 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
1377 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
1381 * Disable all send rings by setting the 'ring disabled' bit
1382 * in the flags field of all the TX send ring control blocks,
1383 * located in NIC memory.
1385 if (BNX_IS_5717_PLUS(sc))
1387 else if (BNX_IS_57765_FAMILY(sc) ||
1388 sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1392 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1393 for (i = 0; i < limit; i++) {
1394 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1395 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1396 vrcb += sizeof(struct bge_rcb);
1400 * Configure send ring RCBs
1402 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1403 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
1404 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
1406 BGE_HOSTADDR(taddr, txr->bnx_tx_ring_paddr);
1407 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi,
1409 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo,
1411 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1412 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1413 vrcb += sizeof(struct bge_rcb);
1417 * Disable all receive return rings by setting the
1418 * 'ring disabled' bit in the flags field of all the receive
1419 * return ring control blocks, located in NIC memory.
1421 if (BNX_IS_5717_PLUS(sc)) {
1422 /* Should be 17, use 16 until we get an SRAM map. */
1424 } else if (BNX_IS_57765_FAMILY(sc) ||
1425 sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1430 /* Disable all receive return rings. */
1431 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1432 for (i = 0; i < limit; i++) {
1433 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1434 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1435 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1436 BGE_RCB_FLAG_RING_DISABLED);
1437 bnx_writembx(sc, BGE_MBX_RX_CONS0_LO +
1438 (i * (sizeof(uint64_t))), 0);
1439 vrcb += sizeof(struct bge_rcb);
1443 * Set up receive return rings.
1445 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1446 for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
1447 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[i];
1449 BGE_HOSTADDR(taddr, ret->bnx_rx_ret_ring_paddr);
1450 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi,
1452 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo,
1454 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1455 BGE_RCB_MAXLEN_FLAGS(BNX_RETURN_RING_CNT, 0));
1456 vrcb += sizeof(struct bge_rcb);
1459 /* Set random backoff seed for TX */
1460 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1461 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1462 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1463 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1464 BGE_TX_BACKOFF_SEED_MASK);
1466 /* Set inter-packet gap */
1468 if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1469 sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1470 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
1471 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
1473 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
1476 * Specify which ring to use for packets that don't match
1479 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1482 * Configure number of RX lists. One interrupt distribution
1483 * list, sixteen active lists, one bad frames class.
1485 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1487 /* Inialize RX list placement stats mask. */
1488 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1489 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1491 /* Disable host coalescing until we get it set up */
1492 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1494 /* Poll to make sure it's shut down. */
1495 for (i = 0; i < BNX_TIMEOUT; i++) {
1496 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1501 if (i == BNX_TIMEOUT) {
1502 if_printf(&sc->arpcom.ac_if,
1503 "host coalescing engine failed to idle\n");
1507 /* Set up host coalescing defaults */
1508 sc->bnx_coal_chg = BNX_RX_COAL_TICKS_CHG |
1509 BNX_TX_COAL_TICKS_CHG |
1510 BNX_RX_COAL_BDS_CHG |
1511 BNX_TX_COAL_BDS_CHG |
1512 BNX_RX_COAL_BDS_INT_CHG |
1513 BNX_TX_COAL_BDS_INT_CHG;
1514 bnx_coal_change(sc);
1517 * Set up addresses of status blocks
1519 intr = &sc->bnx_intr_data[0];
1520 bzero(intr->bnx_status_block, BGE_STATUS_BLK_SZ);
1521 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1522 BGE_ADDR_HI(intr->bnx_status_block_paddr));
1523 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1524 BGE_ADDR_LO(intr->bnx_status_block_paddr));
1525 for (i = 1; i < sc->bnx_intr_cnt; ++i) {
1526 intr = &sc->bnx_intr_data[i];
1527 bzero(intr->bnx_status_block, BGE_STATUS_BLK_SZ);
1528 CSR_WRITE_4(sc, BGE_VEC1_STATUSBLK_ADDR_HI + ((i - 1) * 8),
1529 BGE_ADDR_HI(intr->bnx_status_block_paddr));
1530 CSR_WRITE_4(sc, BGE_VEC1_STATUSBLK_ADDR_LO + ((i - 1) * 8),
1531 BGE_ADDR_LO(intr->bnx_status_block_paddr));
1534 /* Set up status block partail update size. */
1535 val = BGE_STATBLKSZ_32BYTE;
1538 * Does not seem to have visible effect in both
1539 * bulk data (1472B UDP datagram) and tiny data
1540 * (18B UDP datagram) TX tests.
1542 val |= BGE_HCCMODE_CLRTICK_TX;
1544 /* Turn on host coalescing state machine */
1545 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1547 /* Turn on RX BD completion state machine and enable attentions */
1548 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1549 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1551 /* Turn on RX list placement state machine */
1552 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1554 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1555 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1556 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1557 BGE_MACMODE_FRMHDR_DMA_ENB;
1559 if (sc->bnx_flags & BNX_FLAG_TBI)
1560 val |= BGE_PORTMODE_TBI;
1561 else if (sc->bnx_flags & BNX_FLAG_MII_SERDES)
1562 val |= BGE_PORTMODE_GMII;
1564 val |= BGE_PORTMODE_MII;
1566 /* Turn on DMA, clear stats */
1567 CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1569 /* Set misc. local control, enable interrupts on attentions */
1570 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1573 /* Assert GPIO pins for PHY reset */
1574 BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1575 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1576 BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1577 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1580 if (sc->bnx_intr_type == PCI_INTR_TYPE_MSIX)
1581 bnx_enable_msi(sc, TRUE);
1583 /* Turn on write DMA state machine */
1584 val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1585 /* Enable host coalescing bug fix. */
1586 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1587 if (sc->bnx_asicrev == BGE_ASICREV_BCM5785) {
1588 /* Request larger DMA burst size to get better performance. */
1589 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1591 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1594 if (BNX_IS_57765_PLUS(sc)) {
1595 uint32_t dmactl, dmactl_reg;
1597 if (sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1598 dmactl_reg = BGE_RDMA_RSRVCTRL2;
1600 dmactl_reg = BGE_RDMA_RSRVCTRL;
1602 dmactl = CSR_READ_4(sc, dmactl_reg);
1604 * Adjust tx margin to prevent TX data corruption and
1605 * fix internal FIFO overflow.
1607 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1608 sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1609 sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1610 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
1611 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
1612 BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
1613 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
1614 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
1615 BGE_RDMA_RSRVCTRL_TXMRGN_320B;
1618 * Enable fix for read DMA FIFO overruns.
1619 * The fix is to limit the number of RX BDs
1620 * the hardware would fetch at a fime.
1622 CSR_WRITE_4(sc, dmactl_reg,
1623 dmactl | BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
1626 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719) {
1627 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
1628 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
1629 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
1630 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1631 } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1632 sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1635 if (sc->bnx_asicrev == BGE_ASICREV_BCM5762)
1636 ctrl_reg = BGE_RDMA_LSO_CRPTEN_CTRL2;
1638 ctrl_reg = BGE_RDMA_LSO_CRPTEN_CTRL;
1641 * Allow 4KB burst length reads for non-LSO frames.
1642 * Enable 512B burst length reads for buffer descriptors.
1644 CSR_WRITE_4(sc, ctrl_reg,
1645 CSR_READ_4(sc, ctrl_reg) |
1646 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
1647 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1650 /* Turn on read DMA state machine */
1651 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1652 if (sc->bnx_asicrev == BGE_ASICREV_BCM5717)
1653 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
1654 if (sc->bnx_asicrev == BGE_ASICREV_BCM5784 ||
1655 sc->bnx_asicrev == BGE_ASICREV_BCM5785 ||
1656 sc->bnx_asicrev == BGE_ASICREV_BCM57780) {
1657 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1658 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1659 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1661 if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
1662 sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
1663 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
1664 BGE_RDMAMODE_H2BNC_VLAN_DET;
1666 * Allow multiple outstanding read requests from
1667 * non-LSO read DMA engine.
1669 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
1671 if (sc->bnx_asicrev == BGE_ASICREV_BCM57766)
1672 val |= BGE_RDMAMODE_JMB_2K_MMRR;
1673 if (sc->bnx_flags & BNX_FLAG_TSO)
1674 val |= BGE_RDMAMODE_TSO4_ENABLE;
1675 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1676 CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1679 /* Turn on RX data completion state machine */
1680 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1682 /* Turn on RX BD initiator state machine */
1683 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1685 /* Turn on RX data and RX BD initiator state machine */
1686 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1688 /* Turn on send BD completion state machine */
1689 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1691 /* Turn on send data completion state machine */
1692 val = BGE_SDCMODE_ENABLE;
1693 if (sc->bnx_asicrev == BGE_ASICREV_BCM5761)
1694 val |= BGE_SDCMODE_CDELAY;
1695 CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1697 /* Turn on send data initiator state machine */
1698 if (sc->bnx_flags & BNX_FLAG_TSO) {
1699 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
1700 BGE_SDIMODE_HW_LSO_PRE_DMA);
1702 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1705 /* Turn on send BD initiator state machine */
1706 val = BGE_SBDIMODE_ENABLE;
1707 if (sc->bnx_tx_ringcnt > 1)
1708 val |= BGE_SBDIMODE_MULTI_TXR;
1709 CSR_WRITE_4(sc, BGE_SBDI_MODE, val);
1711 /* Turn on send BD selector state machine */
1712 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1714 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1715 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1716 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1718 /* ack/clear link change events */
1719 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1720 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1721 BGE_MACSTAT_LINK_CHANGED);
1722 CSR_WRITE_4(sc, BGE_MI_STS, 0);
1725 * Enable attention when the link has changed state for
1726 * devices that use auto polling.
1728 if (sc->bnx_flags & BNX_FLAG_TBI) {
1729 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1731 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
1732 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
1738 * Clear any pending link state attention.
1739 * Otherwise some link state change events may be lost until attention
1740 * is cleared by bnx_intr() -> bnx_softc.bnx_link_upd() sequence.
1741 * It's not necessary on newer BCM chips - perhaps enabling link
1742 * state change attentions implies clearing pending attention.
1744 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1745 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1746 BGE_MACSTAT_LINK_CHANGED);
1748 /* Enable link state change attentions. */
1749 BNX_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1755 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1756 * against our list and return its name if we find a match. Note
1757 * that since the Broadcom controller contains VPD support, we
1758 * can get the device name string from the controller itself instead
1759 * of the compiled-in string. This is a little slow, but it guarantees
1760 * we'll always announce the right product name.
1763 bnx_probe(device_t dev)
1765 const struct bnx_type *t;
1766 uint16_t product, vendor;
1768 if (!pci_is_pcie(dev))
1771 product = pci_get_device(dev);
1772 vendor = pci_get_vendor(dev);
1774 for (t = bnx_devs; t->bnx_name != NULL; t++) {
1775 if (vendor == t->bnx_vid && product == t->bnx_did)
1778 if (t->bnx_name == NULL)
1781 device_set_desc(dev, t->bnx_name);
1786 bnx_attach(device_t dev)
1789 struct bnx_softc *sc;
1790 struct bnx_rx_std_ring *std;
1792 int error = 0, rid, capmask, i, std_cpuid, std_cpuid_def;
1793 uint8_t ether_addr[ETHER_ADDR_LEN];
1795 uintptr_t mii_priv = 0;
1796 #if defined(BNX_TSO_DEBUG) || defined(BNX_RSS_DEBUG) || defined(BNX_TSS_DEBUG)
1799 #ifdef IFPOLL_ENABLE
1800 int offset, offset_def;
1803 sc = device_get_softc(dev);
1805 callout_init_mp(&sc->bnx_tick_timer);
1806 lwkt_serialize_init(&sc->bnx_jslot_serializer);
1807 lwkt_serialize_init(&sc->bnx_main_serialize);
1809 /* Always setup interrupt mailboxes */
1810 for (i = 0; i < BNX_INTR_MAX; ++i) {
1811 callout_init_mp(&sc->bnx_intr_data[i].bnx_intr_timer);
1812 sc->bnx_intr_data[i].bnx_sc = sc;
1813 sc->bnx_intr_data[i].bnx_intr_mbx = BGE_MBX_IRQ0_LO + (i * 8);
1814 sc->bnx_intr_data[i].bnx_intr_rid = -1;
1815 sc->bnx_intr_data[i].bnx_intr_cpuid = -1;
1818 product = pci_get_device(dev);
1820 #ifndef BURN_BRIDGES
1821 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1824 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1825 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1827 device_printf(dev, "chip is in D%d power mode "
1828 "-- setting to D0\n", pci_get_powerstate(dev));
1830 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1832 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1833 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1835 #endif /* !BURN_BRIDGE */
1838 * Map control/status registers.
1840 pci_enable_busmaster(dev);
1843 sc->bnx_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1846 if (sc->bnx_res == NULL) {
1847 device_printf(dev, "couldn't map memory\n");
1851 sc->bnx_btag = rman_get_bustag(sc->bnx_res);
1852 sc->bnx_bhandle = rman_get_bushandle(sc->bnx_res);
1854 /* Save various chip information */
1856 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1857 BGE_PCIMISCCTL_ASICREV_SHIFT;
1858 if (BGE_ASICREV(sc->bnx_chipid) == BGE_ASICREV_USE_PRODID_REG) {
1859 /* All chips having dedicated ASICREV register have CPMU */
1860 sc->bnx_flags |= BNX_FLAG_CPMU;
1863 case PCI_PRODUCT_BROADCOM_BCM5717:
1864 case PCI_PRODUCT_BROADCOM_BCM5717C:
1865 case PCI_PRODUCT_BROADCOM_BCM5718:
1866 case PCI_PRODUCT_BROADCOM_BCM5719:
1867 case PCI_PRODUCT_BROADCOM_BCM5720_ALT:
1868 case PCI_PRODUCT_BROADCOM_BCM5725:
1869 case PCI_PRODUCT_BROADCOM_BCM5727:
1870 case PCI_PRODUCT_BROADCOM_BCM5762:
1871 sc->bnx_chipid = pci_read_config(dev,
1872 BGE_PCI_GEN2_PRODID_ASICREV, 4);
1875 case PCI_PRODUCT_BROADCOM_BCM57761:
1876 case PCI_PRODUCT_BROADCOM_BCM57762:
1877 case PCI_PRODUCT_BROADCOM_BCM57765:
1878 case PCI_PRODUCT_BROADCOM_BCM57766:
1879 case PCI_PRODUCT_BROADCOM_BCM57781:
1880 case PCI_PRODUCT_BROADCOM_BCM57782:
1881 case PCI_PRODUCT_BROADCOM_BCM57785:
1882 case PCI_PRODUCT_BROADCOM_BCM57786:
1883 case PCI_PRODUCT_BROADCOM_BCM57791:
1884 case PCI_PRODUCT_BROADCOM_BCM57795:
1885 sc->bnx_chipid = pci_read_config(dev,
1886 BGE_PCI_GEN15_PRODID_ASICREV, 4);
1890 sc->bnx_chipid = pci_read_config(dev,
1891 BGE_PCI_PRODID_ASICREV, 4);
1895 if (sc->bnx_chipid == BGE_CHIPID_BCM5717_C0)
1896 sc->bnx_chipid = BGE_CHIPID_BCM5720_A0;
1898 sc->bnx_asicrev = BGE_ASICREV(sc->bnx_chipid);
1899 sc->bnx_chiprev = BGE_CHIPREV(sc->bnx_chipid);
1901 switch (sc->bnx_asicrev) {
1902 case BGE_ASICREV_BCM5717:
1903 case BGE_ASICREV_BCM5719:
1904 case BGE_ASICREV_BCM5720:
1905 sc->bnx_flags |= BNX_FLAG_5717_PLUS | BNX_FLAG_57765_PLUS;
1908 case BGE_ASICREV_BCM5762:
1909 sc->bnx_flags |= BNX_FLAG_57765_PLUS;
1912 case BGE_ASICREV_BCM57765:
1913 case BGE_ASICREV_BCM57766:
1914 sc->bnx_flags |= BNX_FLAG_57765_FAMILY | BNX_FLAG_57765_PLUS;
1918 sc->bnx_flags |= BNX_FLAG_TSO;
1919 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 &&
1920 sc->bnx_chipid == BGE_CHIPID_BCM5719_A0)
1921 sc->bnx_flags &= ~BNX_FLAG_TSO;
1923 if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1924 BNX_IS_57765_FAMILY(sc)) {
1926 * All BCM57785 and BCM5718 families chips have a bug that
1927 * under certain situation interrupt will not be enabled
1928 * even if status tag is written to interrupt mailbox.
1930 * While BCM5719 and BCM5720 have a hardware workaround
1931 * which could fix the above bug.
1932 * See the comment near BGE_PCIDMARWCTL_TAGGED_STATUS_WA in
1935 * For the rest of the chips in these two families, we will
1936 * have to poll the status block at high rate (10ms currently)
1937 * to check whether the interrupt is hosed or not.
1938 * See bnx_check_intr_*() for details.
1940 sc->bnx_flags |= BNX_FLAG_STATUSTAG_BUG;
1943 sc->bnx_pciecap = pci_get_pciecap_ptr(sc->bnx_dev);
1944 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1945 sc->bnx_asicrev == BGE_ASICREV_BCM5720)
1946 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_2048);
1948 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
1949 device_printf(dev, "CHIP ID 0x%08x; "
1950 "ASIC REV 0x%02x; CHIP REV 0x%02x\n",
1951 sc->bnx_chipid, sc->bnx_asicrev, sc->bnx_chiprev);
1954 * Set various PHY quirk flags.
1957 capmask = MII_CAPMASK_DEFAULT;
1958 if (product == PCI_PRODUCT_BROADCOM_BCM57791 ||
1959 product == PCI_PRODUCT_BROADCOM_BCM57795) {
1961 capmask &= ~BMSR_EXTSTAT;
1964 mii_priv |= BRGPHY_FLAG_WIRESPEED;
1965 if (sc->bnx_chipid == BGE_CHIPID_BCM5762_A0)
1966 mii_priv |= BRGPHY_FLAG_5762_A0;
1968 /* Initialize if_name earlier, so if_printf could be used */
1969 ifp = &sc->arpcom.ac_if;
1970 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1972 /* Try to reset the chip. */
1975 if (bnx_chipinit(sc)) {
1976 device_printf(dev, "chip initialization failed\n");
1982 * Get station address
1984 error = bnx_get_eaddr(sc, ether_addr);
1986 device_printf(dev, "failed to read station address\n");
1990 /* Setup RX/TX and interrupt count */
1991 bnx_setup_ring_cnt(sc);
1993 if ((sc->bnx_rx_retcnt == 1 && sc->bnx_tx_ringcnt == 1) ||
1994 (sc->bnx_rx_retcnt > 1 && sc->bnx_tx_ringcnt > 1)) {
1996 * The RX ring and the corresponding TX ring processing
1997 * should be on the same CPU, since they share the same
2000 sc->bnx_flags |= BNX_FLAG_RXTX_BUNDLE;
2002 device_printf(dev, "RX/TX bundle\n");
2003 if (sc->bnx_tx_ringcnt > 1) {
2005 * Multiple TX rings do not share status block
2006 * with link status, so link status will have
2007 * to save its own status_tag.
2009 sc->bnx_flags |= BNX_FLAG_STATUS_HASTAG;
2011 device_printf(dev, "status needs tag\n");
2014 KKASSERT(sc->bnx_rx_retcnt > 1 && sc->bnx_tx_ringcnt == 1);
2016 device_printf(dev, "RX/TX not bundled\n");
2019 error = bnx_dma_alloc(dev);
2023 #ifdef IFPOLL_ENABLE
2024 if (sc->bnx_flags & BNX_FLAG_RXTX_BUNDLE) {
2026 * NPOLLING RX/TX CPU offset
2028 if (sc->bnx_rx_retcnt == ncpus2) {
2032 (sc->bnx_rx_retcnt * device_get_unit(dev)) % ncpus2;
2033 offset = device_getenv_int(dev, "npoll.offset",
2035 if (offset >= ncpus2 ||
2036 offset % sc->bnx_rx_retcnt != 0) {
2037 device_printf(dev, "invalid npoll.offset %d, "
2038 "use %d\n", offset, offset_def);
2039 offset = offset_def;
2042 sc->bnx_npoll_rxoff = offset;
2043 sc->bnx_npoll_txoff = offset;
2046 * NPOLLING RX CPU offset
2048 if (sc->bnx_rx_retcnt == ncpus2) {
2052 (sc->bnx_rx_retcnt * device_get_unit(dev)) % ncpus2;
2053 offset = device_getenv_int(dev, "npoll.rxoff",
2055 if (offset >= ncpus2 ||
2056 offset % sc->bnx_rx_retcnt != 0) {
2057 device_printf(dev, "invalid npoll.rxoff %d, "
2058 "use %d\n", offset, offset_def);
2059 offset = offset_def;
2062 sc->bnx_npoll_rxoff = offset;
2065 * NPOLLING TX CPU offset
2067 offset_def = device_get_unit(dev) % ncpus2;
2068 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
2069 if (offset >= ncpus2) {
2070 device_printf(dev, "invalid npoll.txoff %d, use %d\n",
2071 offset, offset_def);
2072 offset = offset_def;
2074 sc->bnx_npoll_txoff = offset;
2076 #endif /* IFPOLL_ENABLE */
2079 * Allocate interrupt
2081 error = bnx_alloc_intr(sc);
2085 /* Setup serializers */
2086 bnx_setup_serialize(sc);
2088 /* Set default tuneable values. */
2089 sc->bnx_rx_coal_ticks = BNX_RX_COAL_TICKS_DEF;
2090 sc->bnx_tx_coal_ticks = BNX_TX_COAL_TICKS_DEF;
2091 sc->bnx_rx_coal_bds = BNX_RX_COAL_BDS_DEF;
2092 sc->bnx_tx_coal_bds = BNX_TX_COAL_BDS_DEF;
2093 sc->bnx_rx_coal_bds_int = BNX_RX_COAL_BDS_INT_DEF;
2094 sc->bnx_tx_coal_bds_int = BNX_TX_COAL_BDS_INT_DEF;
2096 /* Set up ifnet structure */
2098 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2099 ifp->if_ioctl = bnx_ioctl;
2100 ifp->if_start = bnx_start;
2101 #ifdef IFPOLL_ENABLE
2102 ifp->if_npoll = bnx_npoll;
2104 ifp->if_init = bnx_init;
2105 ifp->if_serialize = bnx_serialize;
2106 ifp->if_deserialize = bnx_deserialize;
2107 ifp->if_tryserialize = bnx_tryserialize;
2109 ifp->if_serialize_assert = bnx_serialize_assert;
2111 ifp->if_mtu = ETHERMTU;
2112 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2114 ifp->if_capabilities |= IFCAP_HWCSUM;
2115 ifp->if_hwassist = BNX_CSUM_FEATURES;
2116 if (sc->bnx_flags & BNX_FLAG_TSO) {
2117 ifp->if_capabilities |= IFCAP_TSO;
2118 ifp->if_hwassist |= CSUM_TSO;
2120 if (BNX_RSS_ENABLED(sc))
2121 ifp->if_capabilities |= IFCAP_RSS;
2122 ifp->if_capenable = ifp->if_capabilities;
2124 ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
2125 ifq_set_ready(&ifp->if_snd);
2126 ifq_set_subq_cnt(&ifp->if_snd, sc->bnx_tx_ringcnt);
2128 if (sc->bnx_tx_ringcnt > 1) {
2129 ifp->if_mapsubq = ifq_mapsubq_mask;
2130 ifq_set_subq_mask(&ifp->if_snd, sc->bnx_tx_ringcnt - 1);
2134 * Figure out what sort of media we have by checking the
2135 * hardware config word in the first 32k of NIC internal memory,
2136 * or fall back to examining the EEPROM if necessary.
2137 * Note: on some BCM5700 cards, this value appears to be unset.
2138 * If that's the case, we have to rely on identifying the NIC
2139 * by its PCI subsystem ID, as we do below for the SysKonnect
2142 if (bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) {
2143 hwcfg = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2145 if (bnx_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2147 device_printf(dev, "failed to read EEPROM\n");
2151 hwcfg = ntohl(hwcfg);
2154 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2155 if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
2156 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
2157 sc->bnx_flags |= BNX_FLAG_TBI;
2160 if (sc->bnx_flags & BNX_FLAG_CPMU)
2161 sc->bnx_mi_mode = BGE_MIMODE_500KHZ_CONST;
2163 sc->bnx_mi_mode = BGE_MIMODE_BASE;
2165 /* Setup link status update stuffs */
2166 if (sc->bnx_flags & BNX_FLAG_TBI) {
2167 sc->bnx_link_upd = bnx_tbi_link_upd;
2168 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
2169 } else if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
2170 sc->bnx_link_upd = bnx_autopoll_link_upd;
2171 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
2173 sc->bnx_link_upd = bnx_copper_link_upd;
2174 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
2177 /* Set default PHY address */
2181 * PHY address mapping for various devices.
2183 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
2184 * ---------+-------+-------+-------+-------+
2185 * BCM57XX | 1 | X | X | X |
2186 * BCM5704 | 1 | X | 1 | X |
2187 * BCM5717 | 1 | 8 | 2 | 9 |
2188 * BCM5719 | 1 | 8 | 2 | 9 |
2189 * BCM5720 | 1 | 8 | 2 | 9 |
2191 * Other addresses may respond but they are not
2192 * IEEE compliant PHYs and should be ignored.
2194 if (BNX_IS_5717_PLUS(sc)) {
2197 f = pci_get_function(dev);
2198 if (sc->bnx_chipid == BGE_CHIPID_BCM5717_A0) {
2199 if (CSR_READ_4(sc, BGE_SGDIG_STS) &
2200 BGE_SGDIGSTS_IS_SERDES)
2201 sc->bnx_phyno = f + 8;
2203 sc->bnx_phyno = f + 1;
2205 if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
2206 BGE_CPMU_PHY_STRAP_IS_SERDES)
2207 sc->bnx_phyno = f + 8;
2209 sc->bnx_phyno = f + 1;
2213 if (sc->bnx_flags & BNX_FLAG_TBI) {
2214 ifmedia_init(&sc->bnx_ifmedia, IFM_IMASK,
2215 bnx_ifmedia_upd, bnx_ifmedia_sts);
2216 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2217 ifmedia_add(&sc->bnx_ifmedia,
2218 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2219 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2220 ifmedia_set(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO);
2221 sc->bnx_ifmedia.ifm_media = sc->bnx_ifmedia.ifm_cur->ifm_media;
2223 struct mii_probe_args mii_args;
2225 mii_probe_args_init(&mii_args, bnx_ifmedia_upd, bnx_ifmedia_sts);
2226 mii_args.mii_probemask = 1 << sc->bnx_phyno;
2227 mii_args.mii_capmask = capmask;
2228 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
2229 mii_args.mii_priv = mii_priv;
2231 error = mii_probe(dev, &sc->bnx_miibus, &mii_args);
2233 device_printf(dev, "MII without any PHY!\n");
2239 * Create sysctl nodes.
2241 sysctl_ctx_init(&sc->bnx_sysctl_ctx);
2242 sc->bnx_sysctl_tree = SYSCTL_ADD_NODE(&sc->bnx_sysctl_ctx,
2243 SYSCTL_STATIC_CHILDREN(_hw),
2245 device_get_nameunit(dev),
2247 if (sc->bnx_sysctl_tree == NULL) {
2248 device_printf(dev, "can't add sysctl node\n");
2253 SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2254 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2255 "rx_rings", CTLFLAG_RD, &sc->bnx_rx_retcnt, 0, "# of RX rings");
2256 SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2257 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2258 "tx_rings", CTLFLAG_RD, &sc->bnx_tx_ringcnt, 0, "# of TX rings");
2260 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2261 SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2262 OID_AUTO, "rx_coal_ticks",
2263 CTLTYPE_INT | CTLFLAG_RW,
2264 sc, 0, bnx_sysctl_rx_coal_ticks, "I",
2265 "Receive coalescing ticks (usec).");
2266 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2267 SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2268 OID_AUTO, "tx_coal_ticks",
2269 CTLTYPE_INT | CTLFLAG_RW,
2270 sc, 0, bnx_sysctl_tx_coal_ticks, "I",
2271 "Transmit coalescing ticks (usec).");
2272 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2273 SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2274 OID_AUTO, "rx_coal_bds",
2275 CTLTYPE_INT | CTLFLAG_RW,
2276 sc, 0, bnx_sysctl_rx_coal_bds, "I",
2277 "Receive max coalesced BD count.");
2278 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2279 SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2280 OID_AUTO, "tx_coal_bds",
2281 CTLTYPE_INT | CTLFLAG_RW,
2282 sc, 0, bnx_sysctl_tx_coal_bds, "I",
2283 "Transmit max coalesced BD count.");
2285 * A common design characteristic for many Broadcom
2286 * client controllers is that they only support a
2287 * single outstanding DMA read operation on the PCIe
2288 * bus. This means that it will take twice as long to
2289 * fetch a TX frame that is split into header and
2290 * payload buffers as it does to fetch a single,
2291 * contiguous TX frame (2 reads vs. 1 read). For these
2292 * controllers, coalescing buffers to reduce the number
2293 * of memory reads is effective way to get maximum
2294 * performance(about 940Mbps). Without collapsing TX
2295 * buffers the maximum TCP bulk transfer performance
2296 * is about 850Mbps. However forcing coalescing mbufs
2297 * consumes a lot of CPU cycles, so leave it off by
2300 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2301 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2302 "force_defrag", CTLTYPE_INT | CTLFLAG_RW,
2303 sc, 0, bnx_sysctl_force_defrag, "I",
2304 "Force defragment on TX path");
2306 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2307 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2308 "tx_wreg", CTLTYPE_INT | CTLFLAG_RW,
2309 sc, 0, bnx_sysctl_tx_wreg, "I",
2310 "# of segments before writing to hardware register");
2312 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2313 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2314 "std_refill", CTLTYPE_INT | CTLFLAG_RW,
2315 sc, 0, bnx_sysctl_std_refill, "I",
2316 "# of packets received before scheduling standard refilling");
2318 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2319 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2320 "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2321 sc, 0, bnx_sysctl_rx_coal_bds_int, "I",
2322 "Receive max coalesced BD count during interrupt.");
2323 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2324 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2325 "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2326 sc, 0, bnx_sysctl_tx_coal_bds_int, "I",
2327 "Transmit max coalesced BD count during interrupt.");
2329 #ifdef IFPOLL_ENABLE
2330 if (sc->bnx_flags & BNX_FLAG_RXTX_BUNDLE) {
2331 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2332 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2333 "npoll_offset", CTLTYPE_INT | CTLFLAG_RW,
2334 sc, 0, bnx_sysctl_npoll_offset, "I",
2335 "NPOLLING cpu offset");
2337 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2338 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2339 "npoll_rxoff", CTLTYPE_INT | CTLFLAG_RW,
2340 sc, 0, bnx_sysctl_npoll_rxoff, "I",
2341 "NPOLLING RX cpu offset");
2342 SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2343 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2344 "npoll_txoff", CTLTYPE_INT | CTLFLAG_RW,
2345 sc, 0, bnx_sysctl_npoll_txoff, "I",
2346 "NPOLLING TX cpu offset");
2350 #ifdef BNX_RSS_DEBUG
2351 SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2352 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2353 "std_refill_mask", CTLFLAG_RD,
2354 &sc->bnx_rx_std_ring.bnx_rx_std_refill, 0, "");
2355 SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2356 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2357 "rss_debug", CTLFLAG_RW, &sc->bnx_rss_debug, 0, "");
2358 for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
2359 ksnprintf(desc, sizeof(desc), "rx_pkt%d", i);
2360 SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2361 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2362 desc, CTLFLAG_RW, &sc->bnx_rx_ret_ring[i].bnx_rx_pkt, "");
2365 #ifdef BNX_TSS_DEBUG
2366 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
2367 ksnprintf(desc, sizeof(desc), "tx_pkt%d", i);
2368 SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2369 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2370 desc, CTLFLAG_RW, &sc->bnx_tx_ring[i].bnx_tx_pkt, "");
2374 SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2375 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2376 "norxbds", CTLFLAG_RW, &sc->bnx_norxbds, "");
2378 SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2379 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2380 "errors", CTLFLAG_RW, &sc->bnx_errors, "");
2382 #ifdef BNX_TSO_DEBUG
2383 for (i = 0; i < BNX_TSO_NSTATS; ++i) {
2384 ksnprintf(desc, sizeof(desc), "tso%d", i + 1);
2385 SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2386 SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2387 desc, CTLFLAG_RW, &sc->bnx_tsosegs[i], "");
2392 * Call MI attach routine.
2394 ether_ifattach(ifp, ether_addr, NULL);
2396 /* Setup TX rings and subqueues */
2397 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
2398 struct ifaltq_subque *ifsq = ifq_get_subq(&ifp->if_snd, i);
2399 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
2401 ifsq_set_cpuid(ifsq, txr->bnx_tx_cpuid);
2402 ifsq_set_hw_serialize(ifsq, &txr->bnx_tx_serialize);
2403 ifsq_set_priv(ifsq, txr);
2404 txr->bnx_ifsq = ifsq;
2406 ifsq_watchdog_init(&txr->bnx_tx_watchdog, ifsq, bnx_watchdog);
2409 device_printf(dev, "txr %d -> cpu%d\n", i,
2414 error = bnx_setup_intr(sc);
2416 ether_ifdetach(ifp);
2419 bnx_set_tick_cpuid(sc, FALSE);
2422 * Create RX standard ring refilling thread
2424 std_cpuid_def = device_get_unit(dev) % ncpus;
2425 std_cpuid = device_getenv_int(dev, "std.cpuid", std_cpuid_def);
2426 if (std_cpuid < 0 || std_cpuid >= ncpus) {
2427 device_printf(dev, "invalid std.cpuid %d, use %d\n",
2428 std_cpuid, std_cpuid_def);
2429 std_cpuid = std_cpuid_def;
2432 std = &sc->bnx_rx_std_ring;
2433 lwkt_create(bnx_rx_std_refill_ithread, std, NULL,
2434 &std->bnx_rx_std_ithread, TDF_NOSTART | TDF_INTTHREAD, std_cpuid,
2435 "%s std", device_get_nameunit(dev));
2436 lwkt_setpri(&std->bnx_rx_std_ithread, TDPRI_INT_MED);
2437 std->bnx_rx_std_ithread.td_preemptable = lwkt_preempt;
2438 sc->bnx_flags |= BNX_FLAG_STD_THREAD;
2447 bnx_detach(device_t dev)
2449 struct bnx_softc *sc = device_get_softc(dev);
2451 if (device_is_attached(dev)) {
2452 struct ifnet *ifp = &sc->arpcom.ac_if;
2454 ifnet_serialize_all(ifp);
2457 bnx_teardown_intr(sc, sc->bnx_intr_cnt);
2458 ifnet_deserialize_all(ifp);
2460 ether_ifdetach(ifp);
2463 if (sc->bnx_flags & BNX_FLAG_STD_THREAD) {
2464 struct bnx_rx_std_ring *std = &sc->bnx_rx_std_ring;
2466 tsleep_interlock(std, 0);
2468 if (std->bnx_rx_std_ithread.td_gd == mycpu) {
2469 bnx_rx_std_refill_stop(std);
2471 lwkt_send_ipiq(std->bnx_rx_std_ithread.td_gd,
2472 bnx_rx_std_refill_stop, std);
2475 tsleep(std, PINTERLOCKED, "bnx_detach", 0);
2477 device_printf(dev, "RX std ithread exited\n");
2479 lwkt_synchronize_ipiqs("bnx_detach_ipiq");
2482 if (sc->bnx_flags & BNX_FLAG_TBI)
2483 ifmedia_removeall(&sc->bnx_ifmedia);
2485 device_delete_child(dev, sc->bnx_miibus);
2486 bus_generic_detach(dev);
2490 if (sc->bnx_msix_mem_res != NULL) {
2491 bus_release_resource(dev, SYS_RES_MEMORY, sc->bnx_msix_mem_rid,
2492 sc->bnx_msix_mem_res);
2494 if (sc->bnx_res != NULL) {
2495 bus_release_resource(dev, SYS_RES_MEMORY,
2496 BGE_PCI_BAR0, sc->bnx_res);
2499 if (sc->bnx_sysctl_tree != NULL)
2500 sysctl_ctx_free(&sc->bnx_sysctl_ctx);
2504 if (sc->bnx_serialize != NULL)
2505 kfree(sc->bnx_serialize, M_DEVBUF);
2511 bnx_reset(struct bnx_softc *sc)
2514 uint32_t cachesize, command, pcistate, reset;
2515 void (*write_op)(struct bnx_softc *, uint32_t, uint32_t);
2521 write_op = bnx_writemem_direct;
2523 /* Save some important PCI state. */
2524 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2525 command = pci_read_config(dev, BGE_PCI_CMD, 4);
2526 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2528 pci_write_config(dev, BGE_PCI_MISC_CTL,
2529 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2530 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2531 BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2533 /* Disable fastboot on controllers that support it. */
2535 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2536 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2539 * Write the magic number to SRAM at offset 0xB50.
2540 * When firmware finishes its initialization it will
2541 * write ~BGE_MAGIC_NUMBER to the same location.
2543 bnx_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2545 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2547 /* XXX: Broadcom Linux driver. */
2548 /* Force PCI-E 1.0a mode */
2549 if (!BNX_IS_57765_PLUS(sc) &&
2550 CSR_READ_4(sc, BGE_PCIE_PHY_TSTCTL) ==
2551 (BGE_PCIE_PHY_TSTCTL_PSCRAM |
2552 BGE_PCIE_PHY_TSTCTL_PCIE10)) {
2553 CSR_WRITE_4(sc, BGE_PCIE_PHY_TSTCTL,
2554 BGE_PCIE_PHY_TSTCTL_PSCRAM);
2556 if (sc->bnx_chipid != BGE_CHIPID_BCM5750_A0) {
2557 /* Prevent PCIE link training during global reset */
2558 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2563 * Set GPHY Power Down Override to leave GPHY
2564 * powered up in D0 uninitialized.
2566 if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0)
2567 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
2569 /* Issue global reset */
2570 write_op(sc, BGE_MISC_CFG, reset);
2574 /* XXX: Broadcom Linux driver. */
2575 if (sc->bnx_chipid == BGE_CHIPID_BCM5750_A0) {
2578 DELAY(500000); /* wait for link training to complete */
2579 v = pci_read_config(dev, 0xc4, 4);
2580 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2583 devctl = pci_read_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL, 2);
2585 /* Disable no snoop and disable relaxed ordering. */
2586 devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP);
2588 /* Old PCI-E chips only support 128 bytes Max PayLoad Size. */
2589 if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0) {
2590 devctl &= ~PCIEM_DEVCTL_MAX_PAYLOAD_MASK;
2591 devctl |= PCIEM_DEVCTL_MAX_PAYLOAD_128;
2594 pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL,
2597 /* Clear error status. */
2598 pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVSTS,
2599 PCIEM_DEVSTS_CORR_ERR |
2600 PCIEM_DEVSTS_NFATAL_ERR |
2601 PCIEM_DEVSTS_FATAL_ERR |
2602 PCIEM_DEVSTS_UNSUPP_REQ, 2);
2604 /* Reset some of the PCI state that got zapped by reset */
2605 pci_write_config(dev, BGE_PCI_MISC_CTL,
2606 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2607 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2608 BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2609 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2610 pci_write_config(dev, BGE_PCI_CMD, command, 4);
2611 write_op(sc, BGE_MISC_CFG, (65 << 1));
2613 /* Enable memory arbiter */
2614 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2617 * Poll until we see the 1's complement of the magic number.
2618 * This indicates that the firmware initialization is complete.
2620 for (i = 0; i < BNX_FIRMWARE_TIMEOUT; i++) {
2621 val = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2622 if (val == ~BGE_MAGIC_NUMBER)
2626 if (i == BNX_FIRMWARE_TIMEOUT) {
2627 if_printf(&sc->arpcom.ac_if, "firmware handshake "
2628 "timed out, found 0x%08x\n", val);
2631 /* BCM57765 A0 needs additional time before accessing. */
2632 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
2636 * XXX Wait for the value of the PCISTATE register to
2637 * return to its original pre-reset state. This is a
2638 * fairly good indicator of reset completion. If we don't
2639 * wait for the reset to fully complete, trying to read
2640 * from the device's non-PCI registers may yield garbage
2643 for (i = 0; i < BNX_TIMEOUT; i++) {
2644 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2649 /* Fix up byte swapping */
2650 CSR_WRITE_4(sc, BGE_MODE_CTL, bnx_dma_swap_options(sc));
2652 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2655 * The 5704 in TBI mode apparently needs some special
2656 * adjustment to insure the SERDES drive level is set
2659 if (sc->bnx_asicrev == BGE_ASICREV_BCM5704 &&
2660 (sc->bnx_flags & BNX_FLAG_TBI)) {
2663 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2664 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2665 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2668 CSR_WRITE_4(sc, BGE_MI_MODE,
2669 sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
2672 /* XXX: Broadcom Linux driver. */
2673 if (!BNX_IS_57765_PLUS(sc)) {
2676 /* Enable Data FIFO protection. */
2677 v = CSR_READ_4(sc, BGE_PCIE_TLDLPL_PORT);
2678 CSR_WRITE_4(sc, BGE_PCIE_TLDLPL_PORT, v | (1 << 25));
2683 if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
2684 BNX_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
2685 CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
2690 * Frame reception handling. This is called if there's a frame
2691 * on the receive return list.
2693 * Note: we have to be able to handle two possibilities here:
2694 * 1) the frame is from the jumbo recieve ring
2695 * 2) the frame is from the standard receive ring
2699 bnx_rxeof(struct bnx_rx_ret_ring *ret, uint16_t rx_prod, int count)
2701 struct bnx_softc *sc = ret->bnx_sc;
2702 struct bnx_rx_std_ring *std = ret->bnx_std;
2703 struct ifnet *ifp = &sc->arpcom.ac_if;
2705 while (ret->bnx_rx_saved_considx != rx_prod && count != 0) {
2706 struct pktinfo pi0, *pi = NULL;
2707 struct bge_rx_bd *cur_rx;
2708 struct bnx_rx_buf *rb;
2710 struct mbuf *m = NULL;
2711 uint16_t vlan_tag = 0;
2716 cur_rx = &ret->bnx_rx_ret_ring[ret->bnx_rx_saved_considx];
2718 rxidx = cur_rx->bge_idx;
2719 KKASSERT(rxidx < BGE_STD_RX_RING_CNT);
2721 BNX_INC(ret->bnx_rx_saved_considx, BNX_RETURN_RING_CNT);
2722 #ifdef BNX_RSS_DEBUG
2726 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2728 vlan_tag = cur_rx->bge_vlan_tag;
2731 if (ret->bnx_rx_cnt >= ret->bnx_rx_cntmax)
2732 bnx_rx_std_refill_sched(ret, std);
2735 rb = &std->bnx_rx_std_buf[rxidx];
2736 m = rb->bnx_rx_mbuf;
2737 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2738 IFNET_STAT_INC(ifp, ierrors, 1);
2740 rb->bnx_rx_refilled = 1;
2743 if (bnx_newbuf_std(ret, rxidx, 0)) {
2744 IFNET_STAT_INC(ifp, ierrors, 1);
2748 IFNET_STAT_INC(ifp, ipackets, 1);
2749 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2750 m->m_pkthdr.rcvif = ifp;
2752 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2753 (cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
2754 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2755 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2756 if ((cur_rx->bge_error_flag &
2757 BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
2758 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2760 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
2761 m->m_pkthdr.csum_data =
2762 cur_rx->bge_tcp_udp_csum;
2763 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2767 if (ifp->if_capenable & IFCAP_RSS) {
2768 pi = bnx_rss_info(&pi0, cur_rx);
2770 (cur_rx->bge_flags & BGE_RXBDFLAG_RSS_HASH)) {
2771 m->m_flags |= M_HASH;
2773 toeplitz_hash(cur_rx->bge_hash);
2778 * If we received a packet with a vlan tag, pass it
2779 * to vlan_input() instead of ether_input().
2782 m->m_flags |= M_VLANTAG;
2783 m->m_pkthdr.ether_vlantag = vlan_tag;
2785 ether_input_pkt(ifp, m, pi);
2787 bnx_writembx(sc, ret->bnx_rx_mbx, ret->bnx_rx_saved_considx);
2789 if (ret->bnx_rx_cnt > 0)
2790 bnx_rx_std_refill_sched(ret, std);
2794 bnx_txeof(struct bnx_tx_ring *txr, uint16_t tx_cons)
2796 struct ifnet *ifp = &txr->bnx_sc->arpcom.ac_if;
2799 * Go through our tx ring and free mbufs for those
2800 * frames that have been sent.
2802 while (txr->bnx_tx_saved_considx != tx_cons) {
2803 struct bnx_tx_buf *buf;
2806 idx = txr->bnx_tx_saved_considx;
2807 buf = &txr->bnx_tx_buf[idx];
2808 if (buf->bnx_tx_mbuf != NULL) {
2809 IFNET_STAT_INC(ifp, opackets, 1);
2810 #ifdef BNX_TSS_DEBUG
2813 bus_dmamap_unload(txr->bnx_tx_mtag,
2814 buf->bnx_tx_dmamap);
2815 m_freem(buf->bnx_tx_mbuf);
2816 buf->bnx_tx_mbuf = NULL;
2819 BNX_INC(txr->bnx_tx_saved_considx, BGE_TX_RING_CNT);
2822 if ((BGE_TX_RING_CNT - txr->bnx_tx_cnt) >=
2823 (BNX_NSEG_RSVD + BNX_NSEG_SPARE))
2824 ifsq_clr_oactive(txr->bnx_ifsq);
2826 if (txr->bnx_tx_cnt == 0)
2827 txr->bnx_tx_watchdog.wd_timer = 0;
2829 if (!ifsq_is_empty(txr->bnx_ifsq))
2830 ifsq_devstart(txr->bnx_ifsq);
2834 bnx_handle_status(struct bnx_softc *sc)
2838 status = *sc->bnx_hw_status;
2840 if (status & BGE_STATFLAG_ERROR) {
2846 val = CSR_READ_4(sc, BGE_FLOW_ATTN);
2847 if (val & ~BGE_FLOWATTN_MB_LOWAT) {
2848 if_printf(&sc->arpcom.ac_if,
2849 "flow attn 0x%08x\n", val);
2853 val = CSR_READ_4(sc, BGE_MSI_STATUS);
2854 if (val & ~BGE_MSISTAT_MSI_PCI_REQ) {
2855 if_printf(&sc->arpcom.ac_if,
2856 "msi status 0x%08x\n", val);
2860 val = CSR_READ_4(sc, BGE_RDMA_STATUS);
2862 if_printf(&sc->arpcom.ac_if,
2863 "rmda status 0x%08x\n", val);
2867 val = CSR_READ_4(sc, BGE_WDMA_STATUS);
2869 if_printf(&sc->arpcom.ac_if,
2870 "wdma status 0x%08x\n", val);
2875 bnx_serialize_skipmain(sc);
2877 bnx_deserialize_skipmain(sc);
2881 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bnx_link_evt)
2885 #ifdef IFPOLL_ENABLE
2888 bnx_npoll_rx(struct ifnet *ifp __unused, void *xret, int cycle)
2890 struct bnx_rx_ret_ring *ret = xret;
2893 ASSERT_SERIALIZED(&ret->bnx_rx_ret_serialize);
2895 ret->bnx_saved_status_tag = *ret->bnx_hw_status_tag;
2898 rx_prod = *ret->bnx_rx_considx;
2899 if (ret->bnx_rx_saved_considx != rx_prod)
2900 bnx_rxeof(ret, rx_prod, cycle);
2904 bnx_npoll_tx_notag(struct ifnet *ifp __unused, void *xtxr, int cycle __unused)
2906 struct bnx_tx_ring *txr = xtxr;
2909 ASSERT_SERIALIZED(&txr->bnx_tx_serialize);
2911 tx_cons = *txr->bnx_tx_considx;
2912 if (txr->bnx_tx_saved_considx != tx_cons)
2913 bnx_txeof(txr, tx_cons);
2917 bnx_npoll_tx(struct ifnet *ifp, void *xtxr, int cycle)
2919 struct bnx_tx_ring *txr = xtxr;
2921 ASSERT_SERIALIZED(&txr->bnx_tx_serialize);
2923 txr->bnx_saved_status_tag = *txr->bnx_hw_status_tag;
2925 bnx_npoll_tx_notag(ifp, txr, cycle);
2929 bnx_npoll_status_notag(struct ifnet *ifp)
2931 struct bnx_softc *sc = ifp->if_softc;
2933 ASSERT_SERIALIZED(&sc->bnx_main_serialize);
2935 bnx_handle_status(sc);
2939 bnx_npoll_status(struct ifnet *ifp)
2941 struct bnx_softc *sc = ifp->if_softc;
2943 ASSERT_SERIALIZED(&sc->bnx_main_serialize);
2945 sc->bnx_saved_status_tag = *sc->bnx_hw_status_tag;
2947 bnx_npoll_status_notag(ifp);
2951 bnx_npoll(struct ifnet *ifp, struct ifpoll_info *info)
2953 struct bnx_softc *sc = ifp->if_softc;
2956 ASSERT_IFNET_SERIALIZED_ALL(ifp);
2959 if (sc->bnx_flags & BNX_FLAG_STATUS_HASTAG)
2960 info->ifpi_status.status_func = bnx_npoll_status;
2962 info->ifpi_status.status_func = bnx_npoll_status_notag;
2963 info->ifpi_status.serializer = &sc->bnx_main_serialize;
2965 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
2966 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
2967 int idx = i + sc->bnx_npoll_txoff;
2969 KKASSERT(idx < ncpus2);
2970 if (sc->bnx_flags & BNX_FLAG_RXTX_BUNDLE) {
2971 info->ifpi_tx[idx].poll_func =
2974 info->ifpi_tx[idx].poll_func = bnx_npoll_tx;
2976 info->ifpi_tx[idx].arg = txr;
2977 info->ifpi_tx[idx].serializer = &txr->bnx_tx_serialize;
2978 ifsq_set_cpuid(txr->bnx_ifsq, idx);
2981 for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
2982 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[i];
2983 int idx = i + sc->bnx_npoll_rxoff;
2985 KKASSERT(idx < ncpus2);
2986 info->ifpi_rx[idx].poll_func = bnx_npoll_rx;
2987 info->ifpi_rx[idx].arg = ret;
2988 info->ifpi_rx[idx].serializer =
2989 &ret->bnx_rx_ret_serialize;
2992 if (ifp->if_flags & IFF_RUNNING) {
2993 bnx_disable_intr(sc);
2994 bnx_set_tick_cpuid(sc, TRUE);
2997 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
2998 ifsq_set_cpuid(sc->bnx_tx_ring[i].bnx_ifsq,
2999 sc->bnx_tx_ring[i].bnx_tx_cpuid);
3001 if (ifp->if_flags & IFF_RUNNING) {
3002 bnx_enable_intr(sc);
3003 bnx_set_tick_cpuid(sc, FALSE);
3008 #endif /* IFPOLL_ENABLE */
3011 bnx_intr_legacy(void *xsc)
3013 struct bnx_softc *sc = xsc;
3014 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[0];
3016 if (ret->bnx_saved_status_tag == *ret->bnx_hw_status_tag) {
3019 val = pci_read_config(sc->bnx_dev, BGE_PCI_PCISTATE, 4);
3020 if (val & BGE_PCISTAT_INTR_NOTACT)
3026 * Interrupt will have to be disabled if tagged status
3027 * is used, else interrupt will always be asserted on
3028 * certain chips (at least on BCM5750 AX/BX).
3030 bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3042 bnx_intr(struct bnx_softc *sc)
3044 struct ifnet *ifp = &sc->arpcom.ac_if;
3045 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[0];
3047 ASSERT_SERIALIZED(&sc->bnx_main_serialize);
3049 ret->bnx_saved_status_tag = *ret->bnx_hw_status_tag;
3051 * Use a load fence to ensure that status_tag is saved
3052 * before rx_prod, tx_cons and status.
3056 bnx_handle_status(sc);
3058 if (ifp->if_flags & IFF_RUNNING) {
3059 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0];
3060 uint16_t rx_prod, tx_cons;
3062 lwkt_serialize_enter(&ret->bnx_rx_ret_serialize);
3063 rx_prod = *ret->bnx_rx_considx;
3064 if (ret->bnx_rx_saved_considx != rx_prod)
3065 bnx_rxeof(ret, rx_prod, -1);
3066 lwkt_serialize_exit(&ret->bnx_rx_ret_serialize);
3068 lwkt_serialize_enter(&txr->bnx_tx_serialize);
3069 tx_cons = *txr->bnx_tx_considx;
3070 if (txr->bnx_tx_saved_considx != tx_cons)
3071 bnx_txeof(txr, tx_cons);
3072 lwkt_serialize_exit(&txr->bnx_tx_serialize);
3075 bnx_writembx(sc, BGE_MBX_IRQ0_LO, ret->bnx_saved_status_tag << 24);
3079 bnx_msix_tx_status(void *xtxr)
3081 struct bnx_tx_ring *txr = xtxr;
3082 struct bnx_softc *sc = txr->bnx_sc;
3083 struct ifnet *ifp = &sc->arpcom.ac_if;
3085 ASSERT_SERIALIZED(&sc->bnx_main_serialize);
3087 txr->bnx_saved_status_tag = *txr->bnx_hw_status_tag;
3089 * Use a load fence to ensure that status_tag is saved
3090 * before tx_cons and status.
3094 bnx_handle_status(sc);
3096 if (ifp->if_flags & IFF_RUNNING) {
3099 lwkt_serialize_enter(&txr->bnx_tx_serialize);
3100 tx_cons = *txr->bnx_tx_considx;
3101 if (txr->bnx_tx_saved_considx != tx_cons)
3102 bnx_txeof(txr, tx_cons);
3103 lwkt_serialize_exit(&txr->bnx_tx_serialize);
3106 bnx_writembx(sc, BGE_MBX_IRQ0_LO, txr->bnx_saved_status_tag << 24);
3110 bnx_msix_rx(void *xret)
3112 struct bnx_rx_ret_ring *ret = xret;
3115 ASSERT_SERIALIZED(&ret->bnx_rx_ret_serialize);
3117 ret->bnx_saved_status_tag = *ret->bnx_hw_status_tag;
3119 * Use a load fence to ensure that status_tag is saved
3124 rx_prod = *ret->bnx_rx_considx;
3125 if (ret->bnx_rx_saved_considx != rx_prod)
3126 bnx_rxeof(ret, rx_prod, -1);
3128 bnx_writembx(ret->bnx_sc, ret->bnx_msix_mbx,
3129 ret->bnx_saved_status_tag << 24);
3133 bnx_msix_rxtx(void *xret)
3135 struct bnx_rx_ret_ring *ret = xret;
3136 struct bnx_tx_ring *txr = ret->bnx_txr;
3137 uint16_t rx_prod, tx_cons;
3139 ASSERT_SERIALIZED(&ret->bnx_rx_ret_serialize);
3141 ret->bnx_saved_status_tag = *ret->bnx_hw_status_tag;
3143 * Use a load fence to ensure that status_tag is saved
3144 * before rx_prod and tx_cons.
3148 rx_prod = *ret->bnx_rx_considx;
3149 if (ret->bnx_rx_saved_considx != rx_prod)
3150 bnx_rxeof(ret, rx_prod, -1);
3152 lwkt_serialize_enter(&txr->bnx_tx_serialize);
3153 tx_cons = *txr->bnx_tx_considx;
3154 if (txr->bnx_tx_saved_considx != tx_cons)
3155 bnx_txeof(txr, tx_cons);
3156 lwkt_serialize_exit(&txr->bnx_tx_serialize);
3158 bnx_writembx(ret->bnx_sc, ret->bnx_msix_mbx,
3159 ret->bnx_saved_status_tag << 24);
3163 bnx_msix_status(void *xsc)
3165 struct bnx_softc *sc = xsc;
3167 ASSERT_SERIALIZED(&sc->bnx_main_serialize);
3169 sc->bnx_saved_status_tag = *sc->bnx_hw_status_tag;
3171 * Use a load fence to ensure that status_tag is saved
3176 bnx_handle_status(sc);
3178 bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_saved_status_tag << 24);
3184 struct bnx_softc *sc = xsc;
3186 lwkt_serialize_enter(&sc->bnx_main_serialize);
3188 bnx_stats_update_regs(sc);
3190 if (sc->bnx_flags & BNX_FLAG_TBI) {
3192 * Since in TBI mode auto-polling can't be used we should poll
3193 * link status manually. Here we register pending link event
3194 * and trigger interrupt.
3197 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3198 } else if (!sc->bnx_link) {
3199 mii_tick(device_get_softc(sc->bnx_miibus));
3202 callout_reset_bycpu(&sc->bnx_tick_timer, hz, bnx_tick, sc,
3203 sc->bnx_tick_cpuid);
3205 lwkt_serialize_exit(&sc->bnx_main_serialize);
3209 bnx_stats_update_regs(struct bnx_softc *sc)
3211 struct ifnet *ifp = &sc->arpcom.ac_if;
3212 struct bge_mac_stats_regs stats;
3216 s = (uint32_t *)&stats;
3217 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
3218 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
3222 IFNET_STAT_SET(ifp, collisions,
3223 (stats.dot3StatsSingleCollisionFrames +
3224 stats.dot3StatsMultipleCollisionFrames +
3225 stats.dot3StatsExcessiveCollisions +
3226 stats.dot3StatsLateCollisions));
3228 val = CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
3229 sc->bnx_norxbds += val;
3233 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
3234 * pointers to descriptors.
3237 bnx_encap(struct bnx_tx_ring *txr, struct mbuf **m_head0, uint32_t *txidx,
3240 struct bge_tx_bd *d = NULL;
3241 uint16_t csum_flags = 0, vlan_tag = 0, mss = 0;
3242 bus_dma_segment_t segs[BNX_NSEG_NEW];
3244 int error, maxsegs, nsegs, idx, i;
3245 struct mbuf *m_head = *m_head0, *m_new;
3247 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3248 #ifdef BNX_TSO_DEBUG
3252 error = bnx_setup_tso(txr, m_head0, &mss, &csum_flags);
3257 #ifdef BNX_TSO_DEBUG
3258 tso_nsegs = (m_head->m_pkthdr.len /
3259 m_head->m_pkthdr.tso_segsz) - 1;
3260 if (tso_nsegs > (BNX_TSO_NSTATS - 1))
3261 tso_nsegs = BNX_TSO_NSTATS - 1;
3262 else if (tso_nsegs < 0)
3264 txr->bnx_sc->bnx_tsosegs[tso_nsegs]++;
3266 } else if (m_head->m_pkthdr.csum_flags & BNX_CSUM_FEATURES) {
3267 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3268 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3269 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
3270 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3271 if (m_head->m_flags & M_LASTFRAG)
3272 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
3273 else if (m_head->m_flags & M_FRAG)
3274 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
3276 if (m_head->m_flags & M_VLANTAG) {
3277 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
3278 vlan_tag = m_head->m_pkthdr.ether_vlantag;
3282 map = txr->bnx_tx_buf[idx].bnx_tx_dmamap;
3284 maxsegs = (BGE_TX_RING_CNT - txr->bnx_tx_cnt) - BNX_NSEG_RSVD;
3285 KASSERT(maxsegs >= BNX_NSEG_SPARE,
3286 ("not enough segments %d", maxsegs));
3288 if (maxsegs > BNX_NSEG_NEW)
3289 maxsegs = BNX_NSEG_NEW;
3292 * Pad outbound frame to BGE_MIN_FRAMELEN for an unusual reason.
3293 * The bge hardware will pad out Tx runts to BGE_MIN_FRAMELEN,
3294 * but when such padded frames employ the bge IP/TCP checksum
3295 * offload, the hardware checksum assist gives incorrect results
3296 * (possibly from incorporating its own padding into the UDP/TCP
3297 * checksum; who knows). If we pad such runts with zeros, the
3298 * onboard checksum comes out correct.
3300 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
3301 m_head->m_pkthdr.len < BNX_MIN_FRAMELEN) {
3302 error = m_devpad(m_head, BNX_MIN_FRAMELEN);
3307 if ((txr->bnx_tx_flags & BNX_TX_FLAG_SHORTDMA) &&
3308 m_head->m_next != NULL) {
3309 m_new = bnx_defrag_shortdma(m_head);
3310 if (m_new == NULL) {
3314 *m_head0 = m_head = m_new;
3316 if ((m_head->m_pkthdr.csum_flags & CSUM_TSO) == 0 &&
3317 (txr->bnx_tx_flags & BNX_TX_FLAG_FORCE_DEFRAG) &&
3318 m_head->m_next != NULL) {
3320 * Forcefully defragment mbuf chain to overcome hardware
3321 * limitation which only support a single outstanding
3322 * DMA read operation. If it fails, keep moving on using
3323 * the original mbuf chain.
3325 m_new = m_defrag(m_head, MB_DONTWAIT);
3327 *m_head0 = m_head = m_new;
3330 error = bus_dmamap_load_mbuf_defrag(txr->bnx_tx_mtag, map,
3331 m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3334 *segs_used += nsegs;
3337 bus_dmamap_sync(txr->bnx_tx_mtag, map, BUS_DMASYNC_PREWRITE);
3339 for (i = 0; ; i++) {
3340 d = &txr->bnx_tx_ring[idx];
3342 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
3343 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
3344 d->bge_len = segs[i].ds_len;
3345 d->bge_flags = csum_flags;
3346 d->bge_vlan_tag = vlan_tag;
3351 BNX_INC(idx, BGE_TX_RING_CNT);
3353 /* Mark the last segment as end of packet... */
3354 d->bge_flags |= BGE_TXBDFLAG_END;
3357 * Insure that the map for this transmission is placed at
3358 * the array index of the last descriptor in this chain.
3360 txr->bnx_tx_buf[*txidx].bnx_tx_dmamap = txr->bnx_tx_buf[idx].bnx_tx_dmamap;
3361 txr->bnx_tx_buf[idx].bnx_tx_dmamap = map;
3362 txr->bnx_tx_buf[idx].bnx_tx_mbuf = m_head;
3363 txr->bnx_tx_cnt += nsegs;
3365 BNX_INC(idx, BGE_TX_RING_CNT);
3376 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3377 * to the mbuf data regions directly in the transmit descriptors.
3380 bnx_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
3382 struct bnx_tx_ring *txr = ifsq_get_priv(ifsq);
3383 struct mbuf *m_head = NULL;
3387 KKASSERT(txr->bnx_ifsq == ifsq);
3388 ASSERT_SERIALIZED(&txr->bnx_tx_serialize);
3390 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq))
3393 prodidx = txr->bnx_tx_prodidx;
3395 while (txr->bnx_tx_buf[prodidx].bnx_tx_mbuf == NULL) {
3397 * Sanity check: avoid coming within BGE_NSEG_RSVD
3398 * descriptors of the end of the ring. Also make
3399 * sure there are BGE_NSEG_SPARE descriptors for
3400 * jumbo buffers' or TSO segments' defragmentation.
3402 if ((BGE_TX_RING_CNT - txr->bnx_tx_cnt) <
3403 (BNX_NSEG_RSVD + BNX_NSEG_SPARE)) {
3404 ifsq_set_oactive(ifsq);
3408 m_head = ifsq_dequeue(ifsq, NULL);
3413 * Pack the data into the transmit ring. If we
3414 * don't have room, set the OACTIVE flag and wait
3415 * for the NIC to drain the ring.
3417 if (bnx_encap(txr, &m_head, &prodidx, &nsegs)) {
3418 ifsq_set_oactive(ifsq);
3419 IFNET_STAT_INC(ifp, oerrors, 1);
3423 if (nsegs >= txr->bnx_tx_wreg) {
3425 bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, prodidx);
3429 ETHER_BPF_MTAP(ifp, m_head);
3432 * Set a timeout in case the chip goes out to lunch.
3434 txr->bnx_tx_watchdog.wd_timer = 5;
3439 bnx_writembx(txr->bnx_sc, txr->bnx_tx_mbx, prodidx);
3441 txr->bnx_tx_prodidx = prodidx;
3447 struct bnx_softc *sc = xsc;
3448 struct ifnet *ifp = &sc->arpcom.ac_if;
3454 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3456 /* Cancel pending I/O and flush buffers. */
3462 * Init the various state machines, ring
3463 * control blocks and firmware.
3465 if (bnx_blockinit(sc)) {
3466 if_printf(ifp, "initialization failure\n");
3472 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3473 ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
3475 /* Load our MAC address. */
3476 m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
3477 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3478 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3480 /* Enable or disable promiscuous mode as needed. */
3483 /* Program multicast filter. */
3487 if (bnx_init_rx_ring_std(&sc->bnx_rx_std_ring)) {
3488 if_printf(ifp, "RX ring initialization failed\n");
3493 /* Init jumbo RX ring. */
3494 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3495 if (bnx_init_rx_ring_jumbo(sc)) {
3496 if_printf(ifp, "Jumbo RX ring initialization failed\n");
3502 /* Init our RX return ring index */
3503 for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
3504 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[i];
3506 ret->bnx_rx_saved_considx = 0;
3507 ret->bnx_rx_cnt = 0;
3511 for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3512 bnx_init_tx_ring(&sc->bnx_tx_ring[i]);
3514 /* Enable TX MAC state machine lockup fix. */
3515 mode = CSR_READ_4(sc, BGE_TX_MODE);
3516 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
3517 if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
3518 sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
3519 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3520 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
3521 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3523 /* Turn on transmitter */
3524 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
3526 /* Initialize RSS */
3527 mode = BGE_RXMODE_ENABLE;
3528 if (BNX_RSS_ENABLED(sc)) {
3530 mode |= BGE_RXMODE_RSS_ENABLE |
3531 BGE_RXMODE_RSS_HASH_MASK_BITS |
3532 BGE_RXMODE_RSS_IPV4_HASH |
3533 BGE_RXMODE_RSS_TCP_IPV4_HASH;
3535 /* Turn on receiver */
3536 BNX_SETBIT(sc, BGE_RX_MODE, mode);
3539 * Set the number of good frames to receive after RX MBUF
3540 * Low Watermark has been reached. After the RX MAC receives
3541 * this number of frames, it will drop subsequent incoming
3542 * frames until the MBUF High Watermark is reached.
3544 if (BNX_IS_57765_FAMILY(sc))
3545 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
3547 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
3549 if (sc->bnx_intr_type == PCI_INTR_TYPE_MSI ||
3550 sc->bnx_intr_type == PCI_INTR_TYPE_MSIX) {
3552 if_printf(ifp, "MSI_MODE: %#x\n",
3553 CSR_READ_4(sc, BGE_MSI_MODE));
3557 /* Tell firmware we're alive. */
3558 BNX_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3560 /* Enable host interrupts if polling(4) is not enabled. */
3561 PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4);
3564 #ifdef IFPOLL_ENABLE
3565 if (ifp->if_flags & IFF_NPOLLING)
3569 bnx_disable_intr(sc);
3571 bnx_enable_intr(sc);
3572 bnx_set_tick_cpuid(sc, polling);
3574 bnx_ifmedia_upd(ifp);
3576 ifp->if_flags |= IFF_RUNNING;
3577 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
3578 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
3580 ifsq_clr_oactive(txr->bnx_ifsq);
3581 ifsq_watchdog_start(&txr->bnx_tx_watchdog);
3584 callout_reset_bycpu(&sc->bnx_tick_timer, hz, bnx_tick, sc,
3585 sc->bnx_tick_cpuid);
3589 * Set media options.
3592 bnx_ifmedia_upd(struct ifnet *ifp)
3594 struct bnx_softc *sc = ifp->if_softc;
3596 /* If this is a 1000baseX NIC, enable the TBI port. */
3597 if (sc->bnx_flags & BNX_FLAG_TBI) {
3598 struct ifmedia *ifm = &sc->bnx_ifmedia;
3600 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3603 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3608 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3609 BNX_CLRBIT(sc, BGE_MAC_MODE,
3610 BGE_MACMODE_HALF_DUPLEX);
3612 BNX_SETBIT(sc, BGE_MAC_MODE,
3613 BGE_MACMODE_HALF_DUPLEX);
3620 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3624 if (mii->mii_instance) {
3625 struct mii_softc *miisc;
3627 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3628 mii_phy_reset(miisc);
3633 * Force an interrupt so that we will call bnx_link_upd
3634 * if needed and clear any pending link state attention.
3635 * Without this we are not getting any further interrupts
3636 * for link state changes and thus will not UP the link and
3637 * not be able to send in bnx_start. The only way to get
3638 * things working was to receive a packet and get an RX
3641 * bnx_tick should help for fiber cards and we might not
3642 * need to do this here if BNX_FLAG_TBI is set but as
3643 * we poll for fiber anyway it should not harm.
3645 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3651 * Report current media status.
3654 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3656 struct bnx_softc *sc = ifp->if_softc;
3658 if (sc->bnx_flags & BNX_FLAG_TBI) {
3659 ifmr->ifm_status = IFM_AVALID;
3660 ifmr->ifm_active = IFM_ETHER;
3661 if (CSR_READ_4(sc, BGE_MAC_STS) &
3662 BGE_MACSTAT_TBI_PCS_SYNCHED) {
3663 ifmr->ifm_status |= IFM_ACTIVE;
3665 ifmr->ifm_active |= IFM_NONE;
3669 ifmr->ifm_active |= IFM_1000_SX;
3670 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3671 ifmr->ifm_active |= IFM_HDX;
3673 ifmr->ifm_active |= IFM_FDX;
3675 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3678 ifmr->ifm_active = mii->mii_media_active;
3679 ifmr->ifm_status = mii->mii_media_status;
3684 bnx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3686 struct bnx_softc *sc = ifp->if_softc;
3687 struct ifreq *ifr = (struct ifreq *)data;
3688 int mask, error = 0;
3690 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3694 if ((!BNX_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3695 (BNX_IS_JUMBO_CAPABLE(sc) &&
3696 ifr->ifr_mtu > BNX_JUMBO_MTU)) {
3698 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3699 ifp->if_mtu = ifr->ifr_mtu;
3700 if (ifp->if_flags & IFF_RUNNING)
3705 if (ifp->if_flags & IFF_UP) {
3706 if (ifp->if_flags & IFF_RUNNING) {
3707 mask = ifp->if_flags ^ sc->bnx_if_flags;
3710 * If only the state of the PROMISC flag
3711 * changed, then just use the 'set promisc
3712 * mode' command instead of reinitializing
3713 * the entire NIC. Doing a full re-init
3714 * means reloading the firmware and waiting
3715 * for it to start up, which may take a
3716 * second or two. Similarly for ALLMULTI.
3718 if (mask & IFF_PROMISC)
3720 if (mask & IFF_ALLMULTI)
3725 } else if (ifp->if_flags & IFF_RUNNING) {
3728 sc->bnx_if_flags = ifp->if_flags;
3732 if (ifp->if_flags & IFF_RUNNING)
3737 if (sc->bnx_flags & BNX_FLAG_TBI) {
3738 error = ifmedia_ioctl(ifp, ifr,
3739 &sc->bnx_ifmedia, command);
3741 struct mii_data *mii;
3743 mii = device_get_softc(sc->bnx_miibus);
3744 error = ifmedia_ioctl(ifp, ifr,
3745 &mii->mii_media, command);
3749 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3750 if (mask & IFCAP_HWCSUM) {
3751 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3752 if (ifp->if_capenable & IFCAP_TXCSUM)
3753 ifp->if_hwassist |= BNX_CSUM_FEATURES;
3755 ifp->if_hwassist &= ~BNX_CSUM_FEATURES;
3757 if (mask & IFCAP_TSO) {
3758 ifp->if_capenable ^= (mask & IFCAP_TSO);
3759 if (ifp->if_capenable & IFCAP_TSO)
3760 ifp->if_hwassist |= CSUM_TSO;
3762 ifp->if_hwassist &= ~CSUM_TSO;
3764 if (mask & IFCAP_RSS)
3765 ifp->if_capenable ^= IFCAP_RSS;
3768 error = ether_ioctl(ifp, command, data);
3775 bnx_watchdog(struct ifaltq_subque *ifsq)
3777 struct ifnet *ifp = ifsq_get_ifp(ifsq);
3778 struct bnx_softc *sc = ifp->if_softc;
3781 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3783 if_printf(ifp, "watchdog timeout -- resetting\n");
3787 IFNET_STAT_INC(ifp, oerrors, 1);
3789 for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3790 ifsq_devstart_sched(sc->bnx_tx_ring[i].bnx_ifsq);
3794 * Stop the adapter and free any mbufs allocated to the
3798 bnx_stop(struct bnx_softc *sc)
3800 struct ifnet *ifp = &sc->arpcom.ac_if;
3803 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3805 callout_stop(&sc->bnx_tick_timer);
3808 * Disable all of the receiver blocks
3810 bnx_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3811 bnx_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3812 bnx_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3813 bnx_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3814 bnx_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3815 bnx_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3818 * Disable all of the transmit blocks
3820 bnx_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3821 bnx_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3822 bnx_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3823 bnx_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3824 bnx_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3825 bnx_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3828 * Shut down all of the memory managers and related
3831 bnx_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3832 bnx_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3833 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3834 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3836 /* Disable host interrupts. */
3837 bnx_disable_intr(sc);
3840 * Tell firmware we're shutting down.
3842 BNX_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3844 /* Free the RX lists. */
3845 bnx_free_rx_ring_std(&sc->bnx_rx_std_ring);
3847 /* Free jumbo RX list. */
3848 if (BNX_IS_JUMBO_CAPABLE(sc))
3849 bnx_free_rx_ring_jumbo(sc);
3851 /* Free TX buffers. */
3852 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
3853 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
3855 txr->bnx_saved_status_tag = 0;
3856 bnx_free_tx_ring(txr);
3859 /* Clear saved status tag */
3860 for (i = 0; i < sc->bnx_rx_retcnt; ++i)
3861 sc->bnx_rx_ret_ring[i].bnx_saved_status_tag = 0;
3864 sc->bnx_coal_chg = 0;
3866 ifp->if_flags &= ~IFF_RUNNING;
3867 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
3868 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
3870 ifsq_clr_oactive(txr->bnx_ifsq);
3871 ifsq_watchdog_stop(&txr->bnx_tx_watchdog);
3876 * Stop all chip I/O so that the kernel's probe routines don't
3877 * get confused by errant DMAs when rebooting.
3880 bnx_shutdown(device_t dev)
3882 struct bnx_softc *sc = device_get_softc(dev);
3883 struct ifnet *ifp = &sc->arpcom.ac_if;
3885 ifnet_serialize_all(ifp);
3888 ifnet_deserialize_all(ifp);
3892 bnx_suspend(device_t dev)
3894 struct bnx_softc *sc = device_get_softc(dev);
3895 struct ifnet *ifp = &sc->arpcom.ac_if;
3897 ifnet_serialize_all(ifp);
3899 ifnet_deserialize_all(ifp);
3905 bnx_resume(device_t dev)
3907 struct bnx_softc *sc = device_get_softc(dev);
3908 struct ifnet *ifp = &sc->arpcom.ac_if;
3910 ifnet_serialize_all(ifp);
3912 if (ifp->if_flags & IFF_UP) {
3916 for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3917 ifsq_devstart_sched(sc->bnx_tx_ring[i].bnx_ifsq);
3920 ifnet_deserialize_all(ifp);
3926 bnx_setpromisc(struct bnx_softc *sc)
3928 struct ifnet *ifp = &sc->arpcom.ac_if;
3930 if (ifp->if_flags & IFF_PROMISC)
3931 BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3933 BNX_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3937 bnx_dma_free(struct bnx_softc *sc)
3939 struct bnx_rx_std_ring *std = &sc->bnx_rx_std_ring;
3942 /* Destroy RX return rings */
3943 if (sc->bnx_rx_ret_ring != NULL) {
3944 for (i = 0; i < sc->bnx_rx_retcnt; ++i)
3945 bnx_destroy_rx_ret_ring(&sc->bnx_rx_ret_ring[i]);
3946 kfree(sc->bnx_rx_ret_ring, M_DEVBUF);
3949 /* Destroy RX mbuf DMA stuffs. */
3950 if (std->bnx_rx_mtag != NULL) {
3951 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3952 KKASSERT(std->bnx_rx_std_buf[i].bnx_rx_mbuf == NULL);
3953 bus_dmamap_destroy(std->bnx_rx_mtag,
3954 std->bnx_rx_std_buf[i].bnx_rx_dmamap);
3956 bus_dma_tag_destroy(std->bnx_rx_mtag);
3959 /* Destroy standard RX ring */
3960 bnx_dma_block_free(std->bnx_rx_std_ring_tag,
3961 std->bnx_rx_std_ring_map, std->bnx_rx_std_ring);
3963 /* Destroy TX rings */
3964 if (sc->bnx_tx_ring != NULL) {
3965 for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
3966 bnx_destroy_tx_ring(&sc->bnx_tx_ring[i]);
3967 kfree(sc->bnx_tx_ring, M_DEVBUF);
3970 if (BNX_IS_JUMBO_CAPABLE(sc))
3971 bnx_free_jumbo_mem(sc);
3973 /* Destroy status blocks */
3974 for (i = 0; i < sc->bnx_intr_cnt; ++i) {
3975 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
3977 bnx_dma_block_free(intr->bnx_status_tag,
3978 intr->bnx_status_map, intr->bnx_status_block);
3981 /* Destroy the parent tag */
3982 if (sc->bnx_cdata.bnx_parent_tag != NULL)
3983 bus_dma_tag_destroy(sc->bnx_cdata.bnx_parent_tag);
3987 bnx_dma_alloc(device_t dev)
3989 struct bnx_softc *sc = device_get_softc(dev);
3990 struct bnx_rx_std_ring *std = &sc->bnx_rx_std_ring;
3994 * Allocate the parent bus DMA tag appropriate for PCI.
3996 * All of the NetExtreme/NetLink controllers have 4GB boundary
3998 * Whenever an address crosses a multiple of the 4GB boundary
3999 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
4000 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
4001 * state machine will lockup and cause the device to hang.
4003 error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G,
4004 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
4005 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
4006 0, &sc->bnx_cdata.bnx_parent_tag);
4008 device_printf(dev, "could not create parent DMA tag\n");
4013 * Create DMA stuffs for status blocks.
4015 for (i = 0; i < sc->bnx_intr_cnt; ++i) {
4016 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
4018 error = bnx_dma_block_alloc(sc,
4019 __VM_CACHELINE_ALIGN(BGE_STATUS_BLK_SZ),
4020 &intr->bnx_status_tag, &intr->bnx_status_map,
4021 (void *)&intr->bnx_status_block,
4022 &intr->bnx_status_block_paddr);
4025 "could not create %dth status block\n", i);
4029 sc->bnx_hw_status = &sc->bnx_intr_data[0].bnx_status_block->bge_status;
4030 if (sc->bnx_flags & BNX_FLAG_STATUS_HASTAG) {
4031 sc->bnx_hw_status_tag =
4032 &sc->bnx_intr_data[0].bnx_status_block->bge_status_tag;
4036 * Create DMA tag and maps for RX mbufs.
4039 lwkt_serialize_init(&std->bnx_rx_std_serialize);
4040 error = bus_dma_tag_create(sc->bnx_cdata.bnx_parent_tag, 1, 0,
4041 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
4042 NULL, NULL, MCLBYTES, 1, MCLBYTES,
4043 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK, &std->bnx_rx_mtag);
4045 device_printf(dev, "could not create RX mbuf DMA tag\n");
4049 for (i = 0; i < BGE_STD_RX_RING_CNT; ++i) {
4050 error = bus_dmamap_create(std->bnx_rx_mtag, BUS_DMA_WAITOK,
4051 &std->bnx_rx_std_buf[i].bnx_rx_dmamap);
4055 for (j = 0; j < i; ++j) {
4056 bus_dmamap_destroy(std->bnx_rx_mtag,
4057 std->bnx_rx_std_buf[j].bnx_rx_dmamap);
4059 bus_dma_tag_destroy(std->bnx_rx_mtag);
4060 std->bnx_rx_mtag = NULL;
4063 "could not create %dth RX mbuf DMA map\n", i);
4069 * Create DMA stuffs for standard RX ring.
4071 error = bnx_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
4072 &std->bnx_rx_std_ring_tag,
4073 &std->bnx_rx_std_ring_map,
4074 (void *)&std->bnx_rx_std_ring,
4075 &std->bnx_rx_std_ring_paddr);
4077 device_printf(dev, "could not create std RX ring\n");
4082 * Create RX return rings
4084 mbx = BGE_MBX_RX_CONS0_LO;
4085 sc->bnx_rx_ret_ring = kmalloc_cachealign(
4086 sizeof(struct bnx_rx_ret_ring) * sc->bnx_rx_retcnt, M_DEVBUF,
4088 for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
4089 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[i];
4090 struct bnx_intr_data *intr;
4094 ret->bnx_rx_mbx = mbx;
4095 ret->bnx_rx_cntmax = (BGE_STD_RX_RING_CNT / 4) /
4097 ret->bnx_rx_mask = 1 << i;
4099 if (!BNX_RSS_ENABLED(sc)) {
4100 intr = &sc->bnx_intr_data[0];
4102 KKASSERT(i + 1 < sc->bnx_intr_cnt);
4103 intr = &sc->bnx_intr_data[i + 1];
4107 ret->bnx_rx_considx =
4108 &intr->bnx_status_block->bge_idx[0].bge_rx_prod_idx;
4109 } else if (i == 1) {
4110 ret->bnx_rx_considx =
4111 &intr->bnx_status_block->bge_rx_jumbo_cons_idx;
4112 } else if (i == 2) {
4113 ret->bnx_rx_considx =
4114 &intr->bnx_status_block->bge_rsvd1;
4115 } else if (i == 3) {
4116 ret->bnx_rx_considx =
4117 &intr->bnx_status_block->bge_rx_mini_cons_idx;
4119 panic("unknown RX return ring %d\n", i);
4121 ret->bnx_hw_status_tag =
4122 &intr->bnx_status_block->bge_status_tag;
4124 error = bnx_create_rx_ret_ring(ret);
4127 "could not create %dth RX ret ring\n", i);
4136 sc->bnx_tx_ring = kmalloc_cachealign(
4137 sizeof(struct bnx_tx_ring) * sc->bnx_tx_ringcnt, M_DEVBUF,
4139 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
4140 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[i];
4141 struct bnx_intr_data *intr;
4144 txr->bnx_tx_mbx = bnx_tx_mailbox[i];
4146 if (sc->bnx_tx_ringcnt == 1) {
4147 intr = &sc->bnx_intr_data[0];
4149 KKASSERT(i + 1 < sc->bnx_intr_cnt);
4150 intr = &sc->bnx_intr_data[i + 1];
4153 if ((sc->bnx_flags & BNX_FLAG_RXTX_BUNDLE) == 0) {
4154 txr->bnx_hw_status_tag =
4155 &intr->bnx_status_block->bge_status_tag;
4157 txr->bnx_tx_considx =
4158 &intr->bnx_status_block->bge_idx[0].bge_tx_cons_idx;
4160 error = bnx_create_tx_ring(txr);
4163 "could not create %dth TX ring\n", i);
4169 * Create jumbo buffer pool.
4171 if (BNX_IS_JUMBO_CAPABLE(sc)) {
4172 error = bnx_alloc_jumbo_mem(sc);
4175 "could not create jumbo buffer pool\n");
4184 bnx_dma_block_alloc(struct bnx_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
4185 bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
4190 error = bus_dmamem_coherent(sc->bnx_cdata.bnx_parent_tag, PAGE_SIZE, 0,
4191 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
4192 size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
4196 *tag = dmem.dmem_tag;
4197 *map = dmem.dmem_map;
4198 *addr = dmem.dmem_addr;
4199 *paddr = dmem.dmem_busaddr;
4205 bnx_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
4208 bus_dmamap_unload(tag, map);
4209 bus_dmamem_free(tag, addr, map);
4210 bus_dma_tag_destroy(tag);
4215 bnx_tbi_link_upd(struct bnx_softc *sc, uint32_t status)
4217 struct ifnet *ifp = &sc->arpcom.ac_if;
4219 #define PCS_ENCODE_ERR (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
4222 * Sometimes PCS encoding errors are detected in
4223 * TBI mode (on fiber NICs), and for some reason
4224 * the chip will signal them as link changes.
4225 * If we get a link change event, but the 'PCS
4226 * encoding error' bit in the MAC status register
4227 * is set, don't bother doing a link check.
4228 * This avoids spurious "gigabit link up" messages
4229 * that sometimes appear on fiber NICs during
4230 * periods of heavy traffic.
4232 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
4233 if (!sc->bnx_link) {
4235 if (sc->bnx_asicrev == BGE_ASICREV_BCM5704) {
4236 BNX_CLRBIT(sc, BGE_MAC_MODE,
4237 BGE_MACMODE_TBI_SEND_CFGS);
4239 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
4242 if_printf(ifp, "link UP\n");
4244 ifp->if_link_state = LINK_STATE_UP;
4245 if_link_state_change(ifp);
4247 } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
4252 if_printf(ifp, "link DOWN\n");
4254 ifp->if_link_state = LINK_STATE_DOWN;
4255 if_link_state_change(ifp);
4259 #undef PCS_ENCODE_ERR
4261 /* Clear the attention. */
4262 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4263 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4264 BGE_MACSTAT_LINK_CHANGED);
4268 bnx_copper_link_upd(struct bnx_softc *sc, uint32_t status __unused)
4270 struct ifnet *ifp = &sc->arpcom.ac_if;
4271 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
4274 bnx_miibus_statchg(sc->bnx_dev);
4278 if_printf(ifp, "link UP\n");
4280 if_printf(ifp, "link DOWN\n");
4283 /* Clear the attention. */
4284 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4285 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4286 BGE_MACSTAT_LINK_CHANGED);
4290 bnx_autopoll_link_upd(struct bnx_softc *sc, uint32_t status __unused)
4292 struct ifnet *ifp = &sc->arpcom.ac_if;
4293 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
4297 if (!sc->bnx_link &&
4298 (mii->mii_media_status & IFM_ACTIVE) &&
4299 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4302 if_printf(ifp, "link UP\n");
4303 } else if (sc->bnx_link &&
4304 (!(mii->mii_media_status & IFM_ACTIVE) ||
4305 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4308 if_printf(ifp, "link DOWN\n");
4311 /* Clear the attention. */
4312 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4313 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4314 BGE_MACSTAT_LINK_CHANGED);
4318 bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
4320 struct bnx_softc *sc = arg1;
4322 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
4323 &sc->bnx_rx_coal_ticks,
4324 BNX_RX_COAL_TICKS_MIN, BNX_RX_COAL_TICKS_MAX,
4325 BNX_RX_COAL_TICKS_CHG);
4329 bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
4331 struct bnx_softc *sc = arg1;
4333 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
4334 &sc->bnx_tx_coal_ticks,
4335 BNX_TX_COAL_TICKS_MIN, BNX_TX_COAL_TICKS_MAX,
4336 BNX_TX_COAL_TICKS_CHG);
4340 bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS)
4342 struct bnx_softc *sc = arg1;
4344 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
4345 &sc->bnx_rx_coal_bds,
4346 BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
4347 BNX_RX_COAL_BDS_CHG);
4351 bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS)
4353 struct bnx_softc *sc = arg1;
4355 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
4356 &sc->bnx_tx_coal_bds,
4357 BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
4358 BNX_TX_COAL_BDS_CHG);
4362 bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS)
4364 struct bnx_softc *sc = arg1;
4366 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
4367 &sc->bnx_rx_coal_bds_int,
4368 BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
4369 BNX_RX_COAL_BDS_INT_CHG);
4373 bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS)
4375 struct bnx_softc *sc = arg1;
4377 return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
4378 &sc->bnx_tx_coal_bds_int,
4379 BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
4380 BNX_TX_COAL_BDS_INT_CHG);
4384 bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
4385 int coal_min, int coal_max, uint32_t coal_chg_mask)
4387 struct bnx_softc *sc = arg1;
4388 struct ifnet *ifp = &sc->arpcom.ac_if;
4391 ifnet_serialize_all(ifp);
4394 error = sysctl_handle_int(oidp, &v, 0, req);
4395 if (!error && req->newptr != NULL) {
4396 if (v < coal_min || v > coal_max) {
4400 sc->bnx_coal_chg |= coal_chg_mask;
4402 /* Commit changes */
4403 bnx_coal_change(sc);
4407 ifnet_deserialize_all(ifp);
4412 bnx_coal_change(struct bnx_softc *sc)
4414 struct ifnet *ifp = &sc->arpcom.ac_if;
4417 ASSERT_IFNET_SERIALIZED_ALL(ifp);
4419 if (sc->bnx_coal_chg & BNX_RX_COAL_TICKS_CHG) {
4420 if (sc->bnx_rx_retcnt == 1) {
4421 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
4422 sc->bnx_rx_coal_ticks);
4425 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, 0);
4426 for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
4427 CSR_WRITE_4(sc, BGE_VEC1_RX_COAL_TICKS +
4428 (i * BGE_VEC_COALSET_SIZE),
4429 sc->bnx_rx_coal_ticks);
4432 for (; i < BNX_INTR_MAX - 1; ++i) {
4433 CSR_WRITE_4(sc, BGE_VEC1_RX_COAL_TICKS +
4434 (i * BGE_VEC_COALSET_SIZE), 0);
4437 if_printf(ifp, "rx_coal_ticks -> %u\n",
4438 sc->bnx_rx_coal_ticks);
4442 if (sc->bnx_coal_chg & BNX_TX_COAL_TICKS_CHG) {
4443 if (sc->bnx_tx_ringcnt == 1) {
4444 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
4445 sc->bnx_tx_coal_ticks);
4448 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, 0);
4449 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
4450 CSR_WRITE_4(sc, BGE_VEC1_TX_COAL_TICKS +
4451 (i * BGE_VEC_COALSET_SIZE),
4452 sc->bnx_tx_coal_ticks);
4455 for (; i < BNX_INTR_MAX - 1; ++i) {
4456 CSR_WRITE_4(sc, BGE_VEC1_TX_COAL_TICKS +
4457 (i * BGE_VEC_COALSET_SIZE), 0);
4460 if_printf(ifp, "tx_coal_ticks -> %u\n",
4461 sc->bnx_tx_coal_ticks);
4465 if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_CHG) {
4466 if (sc->bnx_rx_retcnt == 1) {
4467 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
4468 sc->bnx_rx_coal_bds);
4471 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, 0);
4472 for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
4473 CSR_WRITE_4(sc, BGE_VEC1_RX_MAX_COAL_BDS +
4474 (i * BGE_VEC_COALSET_SIZE),
4475 sc->bnx_rx_coal_bds);
4478 for (; i < BNX_INTR_MAX - 1; ++i) {
4479 CSR_WRITE_4(sc, BGE_VEC1_RX_MAX_COAL_BDS +
4480 (i * BGE_VEC_COALSET_SIZE), 0);
4483 if_printf(ifp, "rx_coal_bds -> %u\n",
4484 sc->bnx_rx_coal_bds);
4488 if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_CHG) {
4489 if (sc->bnx_tx_ringcnt == 1) {
4490 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
4491 sc->bnx_tx_coal_bds);
4494 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, 0);
4495 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
4496 CSR_WRITE_4(sc, BGE_VEC1_TX_MAX_COAL_BDS +
4497 (i * BGE_VEC_COALSET_SIZE),
4498 sc->bnx_tx_coal_bds);
4501 for (; i < BNX_INTR_MAX - 1; ++i) {
4502 CSR_WRITE_4(sc, BGE_VEC1_TX_MAX_COAL_BDS +
4503 (i * BGE_VEC_COALSET_SIZE), 0);
4506 if_printf(ifp, "tx_coal_bds -> %u\n",
4507 sc->bnx_tx_coal_bds);
4511 if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_INT_CHG) {
4512 if (sc->bnx_rx_retcnt == 1) {
4513 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT,
4514 sc->bnx_rx_coal_bds_int);
4517 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
4518 for (i = 0; i < sc->bnx_rx_retcnt; ++i) {
4519 CSR_WRITE_4(sc, BGE_VEC1_RX_MAX_COAL_BDS_INT +
4520 (i * BGE_VEC_COALSET_SIZE),
4521 sc->bnx_rx_coal_bds_int);
4524 for (; i < BNX_INTR_MAX - 1; ++i) {
4525 CSR_WRITE_4(sc, BGE_VEC1_RX_MAX_COAL_BDS_INT +
4526 (i * BGE_VEC_COALSET_SIZE), 0);
4529 if_printf(ifp, "rx_coal_bds_int -> %u\n",
4530 sc->bnx_rx_coal_bds_int);
4534 if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_INT_CHG) {
4535 if (sc->bnx_tx_ringcnt == 1) {
4536 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT,
4537 sc->bnx_tx_coal_bds_int);
4540 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
4541 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
4542 CSR_WRITE_4(sc, BGE_VEC1_TX_MAX_COAL_BDS_INT +
4543 (i * BGE_VEC_COALSET_SIZE),
4544 sc->bnx_tx_coal_bds_int);
4547 for (; i < BNX_INTR_MAX - 1; ++i) {
4548 CSR_WRITE_4(sc, BGE_VEC1_TX_MAX_COAL_BDS_INT +
4549 (i * BGE_VEC_COALSET_SIZE), 0);
4552 if_printf(ifp, "tx_coal_bds_int -> %u\n",
4553 sc->bnx_tx_coal_bds_int);
4557 sc->bnx_coal_chg = 0;
4561 bnx_check_intr_rxtx(void *xintr)
4563 struct bnx_intr_data *intr = xintr;
4564 struct bnx_rx_ret_ring *ret;
4565 struct bnx_tx_ring *txr;
4568 lwkt_serialize_enter(intr->bnx_intr_serialize);
4570 KKASSERT(mycpuid == intr->bnx_intr_cpuid);
4572 ifp = &intr->bnx_sc->arpcom.ac_if;
4573 if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) != IFF_RUNNING) {
4574 lwkt_serialize_exit(intr->bnx_intr_serialize);
4578 txr = intr->bnx_txr;
4579 ret = intr->bnx_ret;
4581 if (*ret->bnx_rx_considx != ret->bnx_rx_saved_considx ||
4582 *txr->bnx_tx_considx != txr->bnx_tx_saved_considx) {
4583 if (intr->bnx_rx_check_considx == ret->bnx_rx_saved_considx &&
4584 intr->bnx_tx_check_considx == txr->bnx_tx_saved_considx) {
4585 if (!intr->bnx_intr_maylose) {
4586 intr->bnx_intr_maylose = TRUE;
4590 if_printf(ifp, "lost interrupt\n");
4591 intr->bnx_intr_func(intr->bnx_intr_arg);
4594 intr->bnx_intr_maylose = FALSE;
4595 intr->bnx_rx_check_considx = ret->bnx_rx_saved_considx;
4596 intr->bnx_tx_check_considx = txr->bnx_tx_saved_considx;
4599 callout_reset(&intr->bnx_intr_timer, BNX_INTR_CKINTVL,
4600 intr->bnx_intr_check, intr);
4601 lwkt_serialize_exit(intr->bnx_intr_serialize);
4605 bnx_check_intr_tx(void *xintr)
4607 struct bnx_intr_data *intr = xintr;
4608 struct bnx_tx_ring *txr;
4611 lwkt_serialize_enter(intr->bnx_intr_serialize);
4613 KKASSERT(mycpuid == intr->bnx_intr_cpuid);
4615 ifp = &intr->bnx_sc->arpcom.ac_if;
4616 if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) != IFF_RUNNING) {
4617 lwkt_serialize_exit(intr->bnx_intr_serialize);
4621 txr = intr->bnx_txr;
4623 if (*txr->bnx_tx_considx != txr->bnx_tx_saved_considx) {
4624 if (intr->bnx_tx_check_considx == txr->bnx_tx_saved_considx) {
4625 if (!intr->bnx_intr_maylose) {
4626 intr->bnx_intr_maylose = TRUE;
4630 if_printf(ifp, "lost interrupt\n");
4631 intr->bnx_intr_func(intr->bnx_intr_arg);
4634 intr->bnx_intr_maylose = FALSE;
4635 intr->bnx_tx_check_considx = txr->bnx_tx_saved_considx;
4638 callout_reset(&intr->bnx_intr_timer, BNX_INTR_CKINTVL,
4639 intr->bnx_intr_check, intr);
4640 lwkt_serialize_exit(intr->bnx_intr_serialize);
4644 bnx_check_intr_rx(void *xintr)
4646 struct bnx_intr_data *intr = xintr;
4647 struct bnx_rx_ret_ring *ret;
4650 lwkt_serialize_enter(intr->bnx_intr_serialize);
4652 KKASSERT(mycpuid == intr->bnx_intr_cpuid);
4654 ifp = &intr->bnx_sc->arpcom.ac_if;
4655 if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) != IFF_RUNNING) {
4656 lwkt_serialize_exit(intr->bnx_intr_serialize);
4660 ret = intr->bnx_ret;
4662 if (*ret->bnx_rx_considx != ret->bnx_rx_saved_considx) {
4663 if (intr->bnx_rx_check_considx == ret->bnx_rx_saved_considx) {
4664 if (!intr->bnx_intr_maylose) {
4665 intr->bnx_intr_maylose = TRUE;
4669 if_printf(ifp, "lost interrupt\n");
4670 intr->bnx_intr_func(intr->bnx_intr_arg);
4673 intr->bnx_intr_maylose = FALSE;
4674 intr->bnx_rx_check_considx = ret->bnx_rx_saved_considx;
4677 callout_reset(&intr->bnx_intr_timer, BNX_INTR_CKINTVL,
4678 intr->bnx_intr_check, intr);
4679 lwkt_serialize_exit(intr->bnx_intr_serialize);
4683 bnx_enable_intr(struct bnx_softc *sc)
4685 struct ifnet *ifp = &sc->arpcom.ac_if;
4688 for (i = 0; i < sc->bnx_intr_cnt; ++i) {
4689 lwkt_serialize_handler_enable(
4690 sc->bnx_intr_data[i].bnx_intr_serialize);
4696 for (i = 0; i < sc->bnx_intr_cnt; ++i) {
4697 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
4699 bnx_writembx(sc, intr->bnx_intr_mbx,
4700 (*intr->bnx_saved_status_tag) << 24);
4701 /* XXX Linux driver */
4702 bnx_writembx(sc, intr->bnx_intr_mbx,
4703 (*intr->bnx_saved_status_tag) << 24);
4707 * Unmask the interrupt when we stop polling.
4709 PCI_CLRBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
4710 BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
4713 * Trigger another interrupt, since above writing
4714 * to interrupt mailbox0 may acknowledge pending
4717 BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4719 if (sc->bnx_flags & BNX_FLAG_STATUSTAG_BUG) {
4721 if_printf(ifp, "status tag bug workaround\n");
4723 for (i = 0; i < sc->bnx_intr_cnt; ++i) {
4724 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
4726 if (intr->bnx_intr_check == NULL)
4728 intr->bnx_intr_maylose = FALSE;
4729 intr->bnx_rx_check_considx = 0;
4730 intr->bnx_tx_check_considx = 0;
4731 callout_reset_bycpu(&intr->bnx_intr_timer,
4732 BNX_INTR_CKINTVL, intr->bnx_intr_check, intr,
4733 intr->bnx_intr_cpuid);
4739 bnx_disable_intr(struct bnx_softc *sc)
4743 for (i = 0; i < sc->bnx_intr_cnt; ++i) {
4744 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
4746 callout_stop(&intr->bnx_intr_timer);
4747 intr->bnx_intr_maylose = FALSE;
4748 intr->bnx_rx_check_considx = 0;
4749 intr->bnx_tx_check_considx = 0;
4753 * Mask the interrupt when we start polling.
4755 PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
4756 BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
4759 * Acknowledge possible asserted interrupt.
4761 for (i = 0; i < BNX_INTR_MAX; ++i)
4762 bnx_writembx(sc, sc->bnx_intr_data[i].bnx_intr_mbx, 1);
4764 for (i = 0; i < sc->bnx_intr_cnt; ++i) {
4765 lwkt_serialize_handler_disable(
4766 sc->bnx_intr_data[i].bnx_intr_serialize);
4771 bnx_get_eaddr_mem(struct bnx_softc *sc, uint8_t ether_addr[])
4776 mac_addr = bnx_readmem_ind(sc, 0x0c14);
4777 if ((mac_addr >> 16) == 0x484b) {
4778 ether_addr[0] = (uint8_t)(mac_addr >> 8);
4779 ether_addr[1] = (uint8_t)mac_addr;
4780 mac_addr = bnx_readmem_ind(sc, 0x0c18);
4781 ether_addr[2] = (uint8_t)(mac_addr >> 24);
4782 ether_addr[3] = (uint8_t)(mac_addr >> 16);
4783 ether_addr[4] = (uint8_t)(mac_addr >> 8);
4784 ether_addr[5] = (uint8_t)mac_addr;
4791 bnx_get_eaddr_nvram(struct bnx_softc *sc, uint8_t ether_addr[])
4793 int mac_offset = BGE_EE_MAC_OFFSET;
4795 if (BNX_IS_5717_PLUS(sc)) {
4798 f = pci_get_function(sc->bnx_dev);
4800 mac_offset = BGE_EE_MAC_OFFSET_5717;
4802 mac_offset += BGE_EE_MAC_OFFSET_5717_OFF;
4805 return bnx_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN);
4809 bnx_get_eaddr_eeprom(struct bnx_softc *sc, uint8_t ether_addr[])
4811 if (sc->bnx_flags & BNX_FLAG_NO_EEPROM)
4814 return bnx_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
4819 bnx_get_eaddr(struct bnx_softc *sc, uint8_t eaddr[])
4821 static const bnx_eaddr_fcn_t bnx_eaddr_funcs[] = {
4822 /* NOTE: Order is critical */
4824 bnx_get_eaddr_nvram,
4825 bnx_get_eaddr_eeprom,
4828 const bnx_eaddr_fcn_t *func;
4830 for (func = bnx_eaddr_funcs; *func != NULL; ++func) {
4831 if ((*func)(sc, eaddr) == 0)
4834 return (*func == NULL ? ENXIO : 0);
4838 * NOTE: 'm' is not freed upon failure
4841 bnx_defrag_shortdma(struct mbuf *m)
4847 * If device receive two back-to-back send BDs with less than
4848 * or equal to 8 total bytes then the device may hang. The two
4849 * back-to-back send BDs must in the same frame for this failure
4850 * to occur. Scan mbuf chains and see whether two back-to-back
4851 * send BDs are there. If this is the case, allocate new mbuf
4852 * and copy the frame to workaround the silicon bug.
4854 for (n = m, found = 0; n != NULL; n = n->m_next) {
4865 n = m_defrag(m, MB_DONTWAIT);
4872 bnx_stop_block(struct bnx_softc *sc, bus_size_t reg, uint32_t bit)
4876 BNX_CLRBIT(sc, reg, bit);
4877 for (i = 0; i < BNX_TIMEOUT; i++) {
4878 if ((CSR_READ_4(sc, reg) & bit) == 0)
4885 bnx_link_poll(struct bnx_softc *sc)
4889 status = CSR_READ_4(sc, BGE_MAC_STS);
4890 if ((status & sc->bnx_link_chg) || sc->bnx_link_evt) {
4891 sc->bnx_link_evt = 0;
4892 sc->bnx_link_upd(sc, status);
4897 bnx_enable_msi(struct bnx_softc *sc, boolean_t is_msix)
4901 msi_mode = CSR_READ_4(sc, BGE_MSI_MODE);
4902 msi_mode |= BGE_MSIMODE_ENABLE;
4905 * 5718-PG105-R says that "one shot" mode does not work
4906 * if MSI is used, however, it obviously works.
4908 msi_mode &= ~BGE_MSIMODE_ONESHOT_DISABLE;
4910 msi_mode |= BGE_MSIMODE_MSIX_MULTIMODE;
4912 msi_mode &= ~BGE_MSIMODE_MSIX_MULTIMODE;
4913 CSR_WRITE_4(sc, BGE_MSI_MODE, msi_mode);
4917 bnx_dma_swap_options(struct bnx_softc *sc)
4919 uint32_t dma_options;
4921 dma_options = BGE_MODECTL_WORDSWAP_NONFRAME |
4922 BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA;
4923 #if BYTE_ORDER == BIG_ENDIAN
4924 dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
4926 if (sc->bnx_asicrev == BGE_ASICREV_BCM5720 ||
4927 sc->bnx_asicrev == BGE_ASICREV_BCM5762) {
4928 dma_options |= BGE_MODECTL_BYTESWAP_B2HRX_DATA |
4929 BGE_MODECTL_WORDSWAP_B2HRX_DATA | BGE_MODECTL_B2HRX_ENABLE |
4930 BGE_MODECTL_HTX2B_ENABLE;
4936 bnx_setup_tso(struct bnx_tx_ring *txr, struct mbuf **mp,
4937 uint16_t *mss0, uint16_t *flags0)
4942 int thoff, iphlen, hoff, hlen;
4943 uint16_t flags, mss;
4946 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4948 hoff = m->m_pkthdr.csum_lhlen;
4949 iphlen = m->m_pkthdr.csum_iphlen;
4950 thoff = m->m_pkthdr.csum_thlen;
4952 KASSERT(hoff > 0, ("invalid ether header len"));
4953 KASSERT(iphlen > 0, ("invalid ip header len"));
4954 KASSERT(thoff > 0, ("invalid tcp header len"));
4956 if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
4957 m = m_pullup(m, hoff + iphlen + thoff);
4964 ip = mtodoff(m, struct ip *, hoff);
4965 th = mtodoff(m, struct tcphdr *, hoff + iphlen);
4967 mss = m->m_pkthdr.tso_segsz;
4968 flags = BGE_TXBDFLAG_CPU_PRE_DMA | BGE_TXBDFLAG_CPU_POST_DMA;
4970 ip->ip_len = htons(mss + iphlen + thoff);
4973 hlen = (iphlen + thoff) >> 2;
4974 mss |= ((hlen & 0x3) << 14);
4975 flags |= ((hlen & 0xf8) << 7) | ((hlen & 0x4) << 2);
4984 bnx_create_tx_ring(struct bnx_tx_ring *txr)
4986 bus_size_t txmaxsz, txmaxsegsz;
4989 lwkt_serialize_init(&txr->bnx_tx_serialize);
4992 * Create DMA tag and maps for TX mbufs.
4994 if (txr->bnx_sc->bnx_flags & BNX_FLAG_TSO)
4995 txmaxsz = IP_MAXPACKET + sizeof(struct ether_vlan_header);
4997 txmaxsz = BNX_JUMBO_FRAMELEN;
4998 if (txr->bnx_sc->bnx_asicrev == BGE_ASICREV_BCM57766)
4999 txmaxsegsz = MCLBYTES;
5001 txmaxsegsz = PAGE_SIZE;
5002 error = bus_dma_tag_create(txr->bnx_sc->bnx_cdata.bnx_parent_tag,
5003 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
5004 txmaxsz, BNX_NSEG_NEW, txmaxsegsz,
5005 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
5008 device_printf(txr->bnx_sc->bnx_dev,
5009 "could not create TX mbuf DMA tag\n");
5013 for (i = 0; i < BGE_TX_RING_CNT; i++) {
5014 error = bus_dmamap_create(txr->bnx_tx_mtag,
5015 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
5016 &txr->bnx_tx_buf[i].bnx_tx_dmamap);
5020 for (j = 0; j < i; ++j) {
5021 bus_dmamap_destroy(txr->bnx_tx_mtag,
5022 txr->bnx_tx_buf[j].bnx_tx_dmamap);
5024 bus_dma_tag_destroy(txr->bnx_tx_mtag);
5025 txr->bnx_tx_mtag = NULL;
5027 device_printf(txr->bnx_sc->bnx_dev,
5028 "could not create TX mbuf DMA map\n");
5034 * Create DMA stuffs for TX ring.
5036 error = bnx_dma_block_alloc(txr->bnx_sc, BGE_TX_RING_SZ,
5037 &txr->bnx_tx_ring_tag,
5038 &txr->bnx_tx_ring_map,
5039 (void *)&txr->bnx_tx_ring,
5040 &txr->bnx_tx_ring_paddr);
5042 device_printf(txr->bnx_sc->bnx_dev,
5043 "could not create TX ring\n");
5047 txr->bnx_tx_flags |= BNX_TX_FLAG_SHORTDMA;
5048 txr->bnx_tx_wreg = BNX_TX_WREG_NSEGS;
5054 bnx_destroy_tx_ring(struct bnx_tx_ring *txr)
5056 /* Destroy TX mbuf DMA stuffs. */
5057 if (txr->bnx_tx_mtag != NULL) {
5060 for (i = 0; i < BGE_TX_RING_CNT; i++) {
5061 KKASSERT(txr->bnx_tx_buf[i].bnx_tx_mbuf == NULL);
5062 bus_dmamap_destroy(txr->bnx_tx_mtag,
5063 txr->bnx_tx_buf[i].bnx_tx_dmamap);
5065 bus_dma_tag_destroy(txr->bnx_tx_mtag);
5068 /* Destroy TX ring */
5069 bnx_dma_block_free(txr->bnx_tx_ring_tag,
5070 txr->bnx_tx_ring_map, txr->bnx_tx_ring);
5074 bnx_sysctl_force_defrag(SYSCTL_HANDLER_ARGS)
5076 struct bnx_softc *sc = (void *)arg1;
5077 struct ifnet *ifp = &sc->arpcom.ac_if;
5078 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0];
5079 int error, defrag, i;
5081 if (txr->bnx_tx_flags & BNX_TX_FLAG_FORCE_DEFRAG)
5086 error = sysctl_handle_int(oidp, &defrag, 0, req);
5087 if (error || req->newptr == NULL)
5090 ifnet_serialize_all(ifp);
5091 for (i = 0; i < sc->bnx_tx_ringcnt; ++i) {
5092 txr = &sc->bnx_tx_ring[i];
5094 txr->bnx_tx_flags |= BNX_TX_FLAG_FORCE_DEFRAG;
5096 txr->bnx_tx_flags &= ~BNX_TX_FLAG_FORCE_DEFRAG;
5098 ifnet_deserialize_all(ifp);
5104 bnx_sysctl_tx_wreg(SYSCTL_HANDLER_ARGS)
5106 struct bnx_softc *sc = (void *)arg1;
5107 struct ifnet *ifp = &sc->arpcom.ac_if;
5108 struct bnx_tx_ring *txr = &sc->bnx_tx_ring[0];
5109 int error, tx_wreg, i;
5111 tx_wreg = txr->bnx_tx_wreg;
5112 error = sysctl_handle_int(oidp, &tx_wreg, 0, req);
5113 if (error || req->newptr == NULL)
5116 ifnet_serialize_all(ifp);
5117 for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
5118 sc->bnx_tx_ring[i].bnx_tx_wreg = tx_wreg;
5119 ifnet_deserialize_all(ifp);
5125 bnx_create_rx_ret_ring(struct bnx_rx_ret_ring *ret)
5129 lwkt_serialize_init(&ret->bnx_rx_ret_serialize);
5132 * Create DMA stuffs for RX return ring.
5134 error = bnx_dma_block_alloc(ret->bnx_sc,
5135 BGE_RX_RTN_RING_SZ(BNX_RETURN_RING_CNT),
5136 &ret->bnx_rx_ret_ring_tag,
5137 &ret->bnx_rx_ret_ring_map,
5138 (void *)&ret->bnx_rx_ret_ring,
5139 &ret->bnx_rx_ret_ring_paddr);
5141 device_printf(ret->bnx_sc->bnx_dev,
5142 "could not create RX ret ring\n");
5146 /* Shadow standard ring's RX mbuf DMA tag */
5147 ret->bnx_rx_mtag = ret->bnx_std->bnx_rx_mtag;
5150 * Create tmp DMA map for RX mbufs.
5152 error = bus_dmamap_create(ret->bnx_rx_mtag, BUS_DMA_WAITOK,
5153 &ret->bnx_rx_tmpmap);
5155 device_printf(ret->bnx_sc->bnx_dev,
5156 "could not create tmp RX mbuf DMA map\n");
5157 ret->bnx_rx_mtag = NULL;
5164 bnx_destroy_rx_ret_ring(struct bnx_rx_ret_ring *ret)
5166 /* Destroy tmp RX mbuf DMA map */
5167 if (ret->bnx_rx_mtag != NULL)
5168 bus_dmamap_destroy(ret->bnx_rx_mtag, ret->bnx_rx_tmpmap);
5170 /* Destroy RX return ring */
5171 bnx_dma_block_free(ret->bnx_rx_ret_ring_tag,
5172 ret->bnx_rx_ret_ring_map, ret->bnx_rx_ret_ring);
5176 bnx_alloc_intr(struct bnx_softc *sc)
5178 struct bnx_intr_data *intr;
5182 if (sc->bnx_intr_cnt > 1) {
5183 error = bnx_alloc_msix(sc);
5186 KKASSERT(sc->bnx_intr_type == PCI_INTR_TYPE_MSIX);
5190 KKASSERT(sc->bnx_intr_cnt == 1);
5192 intr = &sc->bnx_intr_data[0];
5193 intr->bnx_ret = &sc->bnx_rx_ret_ring[0];
5194 intr->bnx_txr = &sc->bnx_tx_ring[0];
5195 intr->bnx_intr_serialize = &sc->bnx_main_serialize;
5196 intr->bnx_intr_check = bnx_check_intr_rxtx;
5197 intr->bnx_saved_status_tag = &intr->bnx_ret->bnx_saved_status_tag;
5199 sc->bnx_intr_type = pci_alloc_1intr(sc->bnx_dev, bnx_msi_enable,
5200 &intr->bnx_intr_rid, &intr_flags);
5202 intr->bnx_intr_res = bus_alloc_resource_any(sc->bnx_dev, SYS_RES_IRQ,
5203 &intr->bnx_intr_rid, intr_flags);
5204 if (intr->bnx_intr_res == NULL) {
5205 device_printf(sc->bnx_dev, "could not alloc interrupt\n");
5209 if (sc->bnx_intr_type == PCI_INTR_TYPE_MSI) {
5210 bnx_enable_msi(sc, FALSE);
5211 intr->bnx_intr_func = bnx_msi;
5213 device_printf(sc->bnx_dev, "oneshot MSI\n");
5215 intr->bnx_intr_func = bnx_intr_legacy;
5217 intr->bnx_intr_arg = sc;
5218 intr->bnx_intr_cpuid = rman_get_cpuid(intr->bnx_intr_res);
5220 intr->bnx_txr->bnx_tx_cpuid = intr->bnx_intr_cpuid;
5226 bnx_setup_intr(struct bnx_softc *sc)
5230 for (i = 0; i < sc->bnx_intr_cnt; ++i) {
5231 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
5233 error = bus_setup_intr_descr(sc->bnx_dev, intr->bnx_intr_res,
5234 INTR_MPSAFE, intr->bnx_intr_func, intr->bnx_intr_arg,
5235 &intr->bnx_intr_hand, intr->bnx_intr_serialize,
5236 intr->bnx_intr_desc);
5238 device_printf(sc->bnx_dev,
5239 "could not set up %dth intr\n", i);
5240 bnx_teardown_intr(sc, i);
5248 bnx_teardown_intr(struct bnx_softc *sc, int cnt)
5252 for (i = 0; i < cnt; ++i) {
5253 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
5255 bus_teardown_intr(sc->bnx_dev, intr->bnx_intr_res,
5256 intr->bnx_intr_hand);
5261 bnx_free_intr(struct bnx_softc *sc)
5263 if (sc->bnx_intr_type != PCI_INTR_TYPE_MSIX) {
5264 struct bnx_intr_data *intr;
5266 KKASSERT(sc->bnx_intr_cnt <= 1);
5267 intr = &sc->bnx_intr_data[0];
5269 if (intr->bnx_intr_res != NULL) {
5270 bus_release_resource(sc->bnx_dev, SYS_RES_IRQ,
5271 intr->bnx_intr_rid, intr->bnx_intr_res);
5273 if (sc->bnx_intr_type == PCI_INTR_TYPE_MSI)
5274 pci_release_msi(sc->bnx_dev);
5276 bnx_free_msix(sc, TRUE);
5281 bnx_setup_serialize(struct bnx_softc *sc)
5286 * Allocate serializer array
5289 /* Main + RX STD + TX + RX RET */
5290 sc->bnx_serialize_cnt = 1 + 1 + sc->bnx_tx_ringcnt + sc->bnx_rx_retcnt;
5293 kmalloc(sc->bnx_serialize_cnt * sizeof(struct lwkt_serialize *),
5294 M_DEVBUF, M_WAITOK | M_ZERO);
5299 * NOTE: Order is critical
5304 KKASSERT(i < sc->bnx_serialize_cnt);
5305 sc->bnx_serialize[i++] = &sc->bnx_main_serialize;
5307 KKASSERT(i < sc->bnx_serialize_cnt);
5308 sc->bnx_serialize[i++] = &sc->bnx_rx_std_ring.bnx_rx_std_serialize;
5310 for (j = 0; j < sc->bnx_rx_retcnt; ++j) {
5311 KKASSERT(i < sc->bnx_serialize_cnt);
5312 sc->bnx_serialize[i++] =
5313 &sc->bnx_rx_ret_ring[j].bnx_rx_ret_serialize;
5316 for (j = 0; j < sc->bnx_tx_ringcnt; ++j) {
5317 KKASSERT(i < sc->bnx_serialize_cnt);
5318 sc->bnx_serialize[i++] =
5319 &sc->bnx_tx_ring[j].bnx_tx_serialize;
5322 KKASSERT(i == sc->bnx_serialize_cnt);
5326 bnx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
5328 struct bnx_softc *sc = ifp->if_softc;
5330 ifnet_serialize_array_enter(sc->bnx_serialize,
5331 sc->bnx_serialize_cnt, slz);
5335 bnx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
5337 struct bnx_softc *sc = ifp->if_softc;
5339 ifnet_serialize_array_exit(sc->bnx_serialize,
5340 sc->bnx_serialize_cnt, slz);
5344 bnx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
5346 struct bnx_softc *sc = ifp->if_softc;
5348 return ifnet_serialize_array_try(sc->bnx_serialize,
5349 sc->bnx_serialize_cnt, slz);
5355 bnx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
5356 boolean_t serialized)
5358 struct bnx_softc *sc = ifp->if_softc;
5360 ifnet_serialize_array_assert(sc->bnx_serialize, sc->bnx_serialize_cnt,
5364 #endif /* INVARIANTS */
5366 #ifdef IFPOLL_ENABLE
5369 bnx_sysctl_npoll_offset(SYSCTL_HANDLER_ARGS)
5371 struct bnx_softc *sc = (void *)arg1;
5372 struct ifnet *ifp = &sc->arpcom.ac_if;
5375 off = sc->bnx_npoll_rxoff;
5376 error = sysctl_handle_int(oidp, &off, 0, req);
5377 if (error || req->newptr == NULL)
5382 ifnet_serialize_all(ifp);
5383 if (off >= ncpus2 || off % sc->bnx_rx_retcnt != 0) {
5387 sc->bnx_npoll_txoff = off;
5388 sc->bnx_npoll_rxoff = off;
5390 ifnet_deserialize_all(ifp);
5396 bnx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
5398 struct bnx_softc *sc = (void *)arg1;
5399 struct ifnet *ifp = &sc->arpcom.ac_if;
5402 off = sc->bnx_npoll_rxoff;
5403 error = sysctl_handle_int(oidp, &off, 0, req);
5404 if (error || req->newptr == NULL)
5409 ifnet_serialize_all(ifp);
5410 if (off >= ncpus2 || off % sc->bnx_rx_retcnt != 0) {
5414 sc->bnx_npoll_rxoff = off;
5416 ifnet_deserialize_all(ifp);
5422 bnx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
5424 struct bnx_softc *sc = (void *)arg1;
5425 struct ifnet *ifp = &sc->arpcom.ac_if;
5428 off = sc->bnx_npoll_txoff;
5429 error = sysctl_handle_int(oidp, &off, 0, req);
5430 if (error || req->newptr == NULL)
5435 ifnet_serialize_all(ifp);
5436 if (off >= ncpus2) {
5440 sc->bnx_npoll_txoff = off;
5442 ifnet_deserialize_all(ifp);
5447 #endif /* IFPOLL_ENABLE */
5450 bnx_set_tick_cpuid(struct bnx_softc *sc, boolean_t polling)
5453 sc->bnx_tick_cpuid = 0; /* XXX */
5455 sc->bnx_tick_cpuid = sc->bnx_intr_data[0].bnx_intr_cpuid;
5459 bnx_rx_std_refill_ithread(void *xstd)
5461 struct bnx_rx_std_ring *std = xstd;
5462 struct globaldata *gd = mycpu;
5466 while (!std->bnx_rx_std_stop) {
5467 if (std->bnx_rx_std_refill) {
5468 lwkt_serialize_handler_call(
5469 &std->bnx_rx_std_serialize,
5470 bnx_rx_std_refill, std, NULL);
5476 atomic_poll_release_int(&std->bnx_rx_std_running);
5479 if (!std->bnx_rx_std_refill && !std->bnx_rx_std_stop) {
5480 lwkt_deschedule_self(gd->gd_curthread);
5493 bnx_rx_std_refill(void *xstd, void *frame __unused)
5495 struct bnx_rx_std_ring *std = xstd;
5496 int cnt, refill_mask;
5502 refill_mask = std->bnx_rx_std_refill;
5503 atomic_clear_int(&std->bnx_rx_std_refill, refill_mask);
5505 while (refill_mask) {
5506 uint16_t check_idx = std->bnx_rx_std;
5509 ret_idx = bsfl(refill_mask);
5511 struct bnx_rx_buf *rb;
5514 BNX_INC(check_idx, BGE_STD_RX_RING_CNT);
5515 rb = &std->bnx_rx_std_buf[check_idx];
5516 refilled = rb->bnx_rx_refilled;
5519 bnx_setup_rxdesc_std(std, check_idx);
5520 std->bnx_rx_std = check_idx;
5523 bnx_writembx(std->bnx_sc,
5524 BGE_MBX_RX_STD_PROD_LO,
5532 refill_mask &= ~(1 << ret_idx);
5536 bnx_writembx(std->bnx_sc, BGE_MBX_RX_STD_PROD_LO,
5540 if (std->bnx_rx_std_refill)
5543 atomic_poll_release_int(&std->bnx_rx_std_running);
5546 if (std->bnx_rx_std_refill)
5551 bnx_sysctl_std_refill(SYSCTL_HANDLER_ARGS)
5553 struct bnx_softc *sc = (void *)arg1;
5554 struct ifnet *ifp = &sc->arpcom.ac_if;
5555 struct bnx_rx_ret_ring *ret = &sc->bnx_rx_ret_ring[0];
5556 int error, cntmax, i;
5558 cntmax = ret->bnx_rx_cntmax;
5559 error = sysctl_handle_int(oidp, &cntmax, 0, req);
5560 if (error || req->newptr == NULL)
5563 ifnet_serialize_all(ifp);
5565 if ((cntmax * sc->bnx_rx_retcnt) > BGE_STD_RX_RING_CNT / 2) {
5570 for (i = 0; i < sc->bnx_tx_ringcnt; ++i)
5571 sc->bnx_rx_ret_ring[i].bnx_rx_cntmax = cntmax;
5575 ifnet_deserialize_all(ifp);
5581 bnx_init_rss(struct bnx_softc *sc)
5583 uint8_t key[BGE_RSS_KEYREG_CNT * BGE_RSS_KEYREG_SIZE];
5586 KKASSERT(BNX_RSS_ENABLED(sc));
5589 for (j = 0; j < BGE_RSS_INDIR_TBL_CNT; ++j) {
5592 for (i = 0; i < BGE_RSS_INDIR_TBLENT_CNT; ++i) {
5595 q = r % sc->bnx_rx_retcnt;
5596 tbl |= q << (BGE_RSS_INDIR_TBLENT_SHIFT *
5597 (BGE_RSS_INDIR_TBLENT_CNT - i - 1));
5601 BNX_RSS_DPRINTF(sc, 1, "tbl%d %08x\n", j, tbl);
5602 CSR_WRITE_4(sc, BGE_RSS_INDIR_TBL(j), tbl);
5605 toeplitz_get_key(key, sizeof(key));
5606 for (i = 0; i < BGE_RSS_KEYREG_CNT; ++i) {
5609 keyreg = BGE_RSS_KEYREG_VAL(key, i);
5611 BNX_RSS_DPRINTF(sc, 1, "key%d %08x\n", i, keyreg);
5612 CSR_WRITE_4(sc, BGE_RSS_KEYREG(i), keyreg);
5617 bnx_setup_ring_cnt(struct bnx_softc *sc)
5619 int msix_enable, i, msix_cnt, msix_cnt2, ring_max;
5621 sc->bnx_tx_ringcnt = 1;
5622 sc->bnx_rx_retcnt = 1;
5623 sc->bnx_intr_cnt = 1;
5625 msix_enable = device_getenv_int(sc->bnx_dev, "msix.enable",
5633 msix_cnt = pci_msix_count(sc->bnx_dev);
5638 while ((1 << (i + 1)) <= msix_cnt)
5643 * One MSI-X vector is dedicated to status or single TX queue,
5644 * so make sure that there are enough MSI-X vectors.
5646 if (msix_cnt == msix_cnt2) {
5649 * This probably will not happen; 57785/5718 families
5650 * come with at least 5 MSI-X vectors.
5653 if (msix_cnt2 <= 1) {
5654 device_printf(sc->bnx_dev,
5655 "MSI-X count %d could not be used\n", msix_cnt);
5658 device_printf(sc->bnx_dev, "MSI-X count %d is power of 2\n",
5663 * Setup RX ring count
5665 ring_max = BNX_RX_RING_MAX;
5666 if (ring_max > msix_cnt2)
5667 ring_max = msix_cnt2;
5668 sc->bnx_rx_retcnt = device_getenv_int(sc->bnx_dev, "rx_rings",
5670 sc->bnx_rx_retcnt = if_ring_count2(sc->bnx_rx_retcnt, ring_max);
5672 if (sc->bnx_rx_retcnt == 1)
5676 * We need one extra MSI-X vector for link status or
5677 * TX ring (if only one TX ring is enabled).
5679 sc->bnx_intr_cnt = sc->bnx_rx_retcnt + 1;
5682 * Setup TX ring count
5684 * Currently only BCM5719 and BCM5720 support multiple TX rings
5685 * and the TX ring count must be less than the RX ring count.
5687 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
5688 sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
5689 ring_max = BNX_TX_RING_MAX;
5690 if (ring_max > msix_cnt2)
5691 ring_max = msix_cnt2;
5692 if (ring_max > sc->bnx_rx_retcnt)
5693 ring_max = sc->bnx_rx_retcnt;
5694 sc->bnx_tx_ringcnt = device_getenv_int(sc->bnx_dev, "tx_rings",
5696 sc->bnx_tx_ringcnt = if_ring_count2(sc->bnx_tx_ringcnt,
5702 bnx_alloc_msix(struct bnx_softc *sc)
5704 struct bnx_intr_data *intr;
5705 boolean_t setup = FALSE;
5706 int error, i, offset, offset_def;
5708 KKASSERT(sc->bnx_intr_cnt > 1);
5709 KKASSERT(sc->bnx_intr_cnt == sc->bnx_rx_retcnt + 1);
5711 if (sc->bnx_flags & BNX_FLAG_RXTX_BUNDLE) {
5715 intr = &sc->bnx_intr_data[0];
5717 intr->bnx_intr_serialize = &sc->bnx_main_serialize;
5718 intr->bnx_saved_status_tag = &sc->bnx_saved_status_tag;
5720 intr->bnx_intr_func = bnx_msix_status;
5721 intr->bnx_intr_arg = sc;
5722 intr->bnx_intr_cpuid = 0; /* XXX */
5724 ksnprintf(intr->bnx_intr_desc0, sizeof(intr->bnx_intr_desc0),
5725 "%s sts", device_get_nameunit(sc->bnx_dev));
5726 intr->bnx_intr_desc = intr->bnx_intr_desc0;
5731 if (sc->bnx_rx_retcnt == ncpus2) {
5734 offset_def = (sc->bnx_rx_retcnt *
5735 device_get_unit(sc->bnx_dev)) % ncpus2;
5737 offset = device_getenv_int(sc->bnx_dev,
5738 "msix.offset", offset_def);
5739 if (offset >= ncpus2 ||
5740 offset % sc->bnx_rx_retcnt != 0) {
5741 device_printf(sc->bnx_dev,
5742 "invalid msix.offset %d, use %d\n",
5743 offset, offset_def);
5744 offset = offset_def;
5748 for (i = 1; i < sc->bnx_intr_cnt; ++i) {
5751 intr = &sc->bnx_intr_data[i];
5753 KKASSERT(idx < sc->bnx_rx_retcnt);
5754 intr->bnx_ret = &sc->bnx_rx_ret_ring[idx];
5755 if (idx < sc->bnx_tx_ringcnt) {
5756 intr->bnx_txr = &sc->bnx_tx_ring[idx];
5757 intr->bnx_ret->bnx_txr = intr->bnx_txr;
5760 intr->bnx_intr_serialize =
5761 &intr->bnx_ret->bnx_rx_ret_serialize;
5762 intr->bnx_saved_status_tag =
5763 &intr->bnx_ret->bnx_saved_status_tag;
5765 intr->bnx_intr_arg = intr->bnx_ret;
5766 KKASSERT(idx + offset < ncpus2);
5767 intr->bnx_intr_cpuid = idx + offset;
5769 if (intr->bnx_txr == NULL) {
5770 intr->bnx_intr_check = bnx_check_intr_rx;
5771 intr->bnx_intr_func = bnx_msix_rx;
5772 ksnprintf(intr->bnx_intr_desc0,
5773 sizeof(intr->bnx_intr_desc0), "%s rx%d",
5774 device_get_nameunit(sc->bnx_dev), idx);
5776 intr->bnx_intr_check = bnx_check_intr_rxtx;
5777 intr->bnx_intr_func = bnx_msix_rxtx;
5778 ksnprintf(intr->bnx_intr_desc0,
5779 sizeof(intr->bnx_intr_desc0), "%s rxtx%d",
5780 device_get_nameunit(sc->bnx_dev), idx);
5782 intr->bnx_txr->bnx_tx_cpuid =
5783 intr->bnx_intr_cpuid;
5785 intr->bnx_intr_desc = intr->bnx_intr_desc0;
5787 intr->bnx_ret->bnx_msix_mbx = intr->bnx_intr_mbx;
5791 * TX ring and link status
5793 offset_def = device_get_unit(sc->bnx_dev) % ncpus2;
5794 offset = device_getenv_int(sc->bnx_dev, "msix.txoff",
5796 if (offset >= ncpus2) {
5797 device_printf(sc->bnx_dev,
5798 "invalid msix.txoff %d, use %d\n",
5799 offset, offset_def);
5800 offset = offset_def;
5803 intr = &sc->bnx_intr_data[0];
5805 intr->bnx_txr = &sc->bnx_tx_ring[0];
5806 intr->bnx_intr_serialize = &sc->bnx_main_serialize;
5807 intr->bnx_intr_check = bnx_check_intr_tx;
5808 intr->bnx_saved_status_tag =
5809 &intr->bnx_txr->bnx_saved_status_tag;
5811 intr->bnx_intr_func = bnx_msix_tx_status;
5812 intr->bnx_intr_arg = intr->bnx_txr;
5813 intr->bnx_intr_cpuid = offset;
5815 ksnprintf(intr->bnx_intr_desc0, sizeof(intr->bnx_intr_desc0),
5816 "%s ststx", device_get_nameunit(sc->bnx_dev));
5817 intr->bnx_intr_desc = intr->bnx_intr_desc0;
5819 intr->bnx_txr->bnx_tx_cpuid = intr->bnx_intr_cpuid;
5824 if (sc->bnx_rx_retcnt == ncpus2) {
5827 offset_def = (sc->bnx_rx_retcnt *
5828 device_get_unit(sc->bnx_dev)) % ncpus2;
5830 offset = device_getenv_int(sc->bnx_dev,
5831 "msix.rxoff", offset_def);
5832 if (offset >= ncpus2 ||
5833 offset % sc->bnx_rx_retcnt != 0) {
5834 device_printf(sc->bnx_dev,
5835 "invalid msix.rxoff %d, use %d\n",
5836 offset, offset_def);
5837 offset = offset_def;
5841 for (i = 1; i < sc->bnx_intr_cnt; ++i) {
5844 intr = &sc->bnx_intr_data[i];
5846 KKASSERT(idx < sc->bnx_rx_retcnt);
5847 intr->bnx_ret = &sc->bnx_rx_ret_ring[idx];
5848 intr->bnx_intr_serialize =
5849 &intr->bnx_ret->bnx_rx_ret_serialize;
5850 intr->bnx_intr_check = bnx_check_intr_rx;
5851 intr->bnx_saved_status_tag =
5852 &intr->bnx_ret->bnx_saved_status_tag;
5854 intr->bnx_intr_func = bnx_msix_rx;
5855 intr->bnx_intr_arg = intr->bnx_ret;
5856 KKASSERT(idx + offset < ncpus2);
5857 intr->bnx_intr_cpuid = idx + offset;
5859 ksnprintf(intr->bnx_intr_desc0,
5860 sizeof(intr->bnx_intr_desc0), "%s rx%d",
5861 device_get_nameunit(sc->bnx_dev), idx);
5862 intr->bnx_intr_desc = intr->bnx_intr_desc0;
5864 intr->bnx_ret->bnx_msix_mbx = intr->bnx_intr_mbx;
5868 sc->bnx_msix_mem_rid = PCIR_BAR(4);
5869 sc->bnx_msix_mem_res = bus_alloc_resource_any(sc->bnx_dev,
5870 SYS_RES_MEMORY, &sc->bnx_msix_mem_rid, RF_ACTIVE);
5871 if (sc->bnx_msix_mem_res == NULL) {
5872 device_printf(sc->bnx_dev, "could not alloc MSI-X table\n");
5876 bnx_enable_msi(sc, TRUE);
5878 error = pci_setup_msix(sc->bnx_dev);
5880 device_printf(sc->bnx_dev, "could not setup MSI-X\n");
5885 for (i = 0; i < sc->bnx_intr_cnt; ++i) {
5886 intr = &sc->bnx_intr_data[i];
5888 error = pci_alloc_msix_vector(sc->bnx_dev, i,
5889 &intr->bnx_intr_rid, intr->bnx_intr_cpuid);
5891 device_printf(sc->bnx_dev,
5892 "could not alloc MSI-X %d on cpu%d\n",
5893 i, intr->bnx_intr_cpuid);
5897 intr->bnx_intr_res = bus_alloc_resource_any(sc->bnx_dev,
5898 SYS_RES_IRQ, &intr->bnx_intr_rid, RF_ACTIVE);
5899 if (intr->bnx_intr_res == NULL) {
5900 device_printf(sc->bnx_dev,
5901 "could not alloc MSI-X %d resource\n", i);
5907 pci_enable_msix(sc->bnx_dev);
5908 sc->bnx_intr_type = PCI_INTR_TYPE_MSIX;
5911 bnx_free_msix(sc, setup);
5916 bnx_free_msix(struct bnx_softc *sc, boolean_t setup)
5920 KKASSERT(sc->bnx_intr_cnt > 1);
5922 for (i = 0; i < sc->bnx_intr_cnt; ++i) {
5923 struct bnx_intr_data *intr = &sc->bnx_intr_data[i];
5925 if (intr->bnx_intr_res != NULL) {
5926 bus_release_resource(sc->bnx_dev, SYS_RES_IRQ,
5927 intr->bnx_intr_rid, intr->bnx_intr_res);
5929 if (intr->bnx_intr_rid >= 0) {
5930 pci_release_msix_vector(sc->bnx_dev,
5931 intr->bnx_intr_rid);
5935 pci_teardown_msix(sc->bnx_dev);
5939 bnx_rx_std_refill_sched_ipi(void *xret)
5941 struct bnx_rx_ret_ring *ret = xret;
5942 struct bnx_rx_std_ring *std = ret->bnx_std;
5943 struct globaldata *gd = mycpu;
5947 atomic_set_int(&std->bnx_rx_std_refill, ret->bnx_rx_mask);
5950 KKASSERT(std->bnx_rx_std_ithread.td_gd == gd);
5951 lwkt_schedule(&std->bnx_rx_std_ithread);
5957 bnx_rx_std_refill_stop(void *xstd)
5959 struct bnx_rx_std_ring *std = xstd;
5960 struct globaldata *gd = mycpu;
5964 std->bnx_rx_std_stop = 1;
5967 KKASSERT(std->bnx_rx_std_ithread.td_gd == gd);
5968 lwkt_schedule(&std->bnx_rx_std_ithread);
5974 bnx_serialize_skipmain(struct bnx_softc *sc)
5976 lwkt_serialize_array_enter(sc->bnx_serialize,
5977 sc->bnx_serialize_cnt, 1);
5981 bnx_deserialize_skipmain(struct bnx_softc *sc)
5983 lwkt_serialize_array_exit(sc->bnx_serialize,
5984 sc->bnx_serialize_cnt, 1);
5988 bnx_rx_std_refill_sched(struct bnx_rx_ret_ring *ret,
5989 struct bnx_rx_std_ring *std)
5991 struct globaldata *gd = mycpu;
5993 ret->bnx_rx_cnt = 0;
5998 atomic_set_int(&std->bnx_rx_std_refill, ret->bnx_rx_mask);
6000 if (atomic_poll_acquire_int(&std->bnx_rx_std_running)) {
6001 if (std->bnx_rx_std_ithread.td_gd == gd) {
6002 lwkt_schedule(&std->bnx_rx_std_ithread);
6005 std->bnx_rx_std_ithread.td_gd,
6006 bnx_rx_std_refill_sched_ipi, ret);
6013 static struct pktinfo *
6014 bnx_rss_info(struct pktinfo *pi, const struct bge_rx_bd *cur_rx)
6016 /* Don't pick up IPv6 packet */
6017 if (cur_rx->bge_flags & BGE_RXBDFLAG_IPV6)
6020 /* Don't pick up IP packet w/o IP checksum */
6021 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) == 0 ||
6022 (cur_rx->bge_error_flag & BGE_RXERRFLAG_IP_CSUM_NOK))
6025 /* Don't pick up IP packet w/o TCP/UDP checksum */
6026 if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) == 0)
6029 /* May be IP fragment */
6030 if (cur_rx->bge_tcp_udp_csum != 0xffff)
6033 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_IS_TCP)
6034 pi->pi_l3proto = IPPROTO_TCP;
6036 pi->pi_l3proto = IPPROTO_UDP;
6037 pi->pi_netisr = NETISR_IP;