1 /******************************************************************************
3 Copyright (c) 2006-2013, Myricom Inc.
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
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13 contributors may be used to endorse or promote products derived from
14 this software without specific prior written permission.
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17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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28 $FreeBSD: head/sys/dev/mxge/if_mxge.c 254263 2013-08-12 23:30:01Z scottl $
30 ***************************************************************************/
32 #include "opt_ifpoll.h"
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/linker.h>
38 #include <sys/firmware.h>
39 #include <sys/endian.h>
40 #include <sys/in_cksum.h>
41 #include <sys/sockio.h>
43 #include <sys/malloc.h>
44 #include <sys/kernel.h>
45 #include <sys/module.h>
46 #include <sys/serialize.h>
47 #include <sys/socket.h>
48 #include <sys/sysctl.h>
51 #include <net/if_arp.h>
52 #include <net/ifq_var.h>
53 #include <net/ethernet.h>
54 #include <net/if_dl.h>
55 #include <net/if_media.h>
56 #include <net/if_poll.h>
60 #include <net/if_types.h>
61 #include <net/vlan/if_vlan_var.h>
63 #include <net/toeplitz.h>
65 #include <netinet/in_systm.h>
66 #include <netinet/in.h>
67 #include <netinet/ip.h>
68 #include <netinet/tcp.h>
73 #include <bus/pci/pcireg.h>
74 #include <bus/pci/pcivar.h>
75 #include <bus/pci/pci_private.h> /* XXX for pci_cfg_restore */
77 #include <vm/vm.h> /* for pmap_mapdev() */
80 #if defined(__i386__) || defined(__x86_64__)
81 #include <machine/specialreg.h>
84 #include <dev/netif/mxge/mxge_mcp.h>
85 #include <dev/netif/mxge/mcp_gen_header.h>
86 #include <dev/netif/mxge/if_mxge_var.h>
88 #define MXGE_RX_SMALL_BUFLEN (MHLEN - MXGEFW_PAD)
89 #define MXGE_HWRSS_KEYLEN 16
92 static int mxge_nvidia_ecrc_enable = 1;
93 static int mxge_force_firmware = 0;
94 static int mxge_intr_coal_delay = MXGE_INTR_COAL_DELAY;
95 static int mxge_deassert_wait = 1;
96 static int mxge_flow_control = 1;
97 static int mxge_ticks;
98 static int mxge_num_slices = 0;
99 static int mxge_always_promisc = 0;
100 static int mxge_throttle = 0;
101 static int mxge_msi_enable = 1;
102 static int mxge_msix_enable = 1;
103 static int mxge_multi_tx = 1;
105 * Don't use RSS by default, its just too slow
107 static int mxge_use_rss = 0;
109 static const char *mxge_fw_unaligned = "mxge_ethp_z8e";
110 static const char *mxge_fw_aligned = "mxge_eth_z8e";
111 static const char *mxge_fw_rss_aligned = "mxge_rss_eth_z8e";
112 static const char *mxge_fw_rss_unaligned = "mxge_rss_ethp_z8e";
114 TUNABLE_INT("hw.mxge.num_slices", &mxge_num_slices);
115 TUNABLE_INT("hw.mxge.flow_control_enabled", &mxge_flow_control);
116 TUNABLE_INT("hw.mxge.intr_coal_delay", &mxge_intr_coal_delay);
117 TUNABLE_INT("hw.mxge.nvidia_ecrc_enable", &mxge_nvidia_ecrc_enable);
118 TUNABLE_INT("hw.mxge.force_firmware", &mxge_force_firmware);
119 TUNABLE_INT("hw.mxge.deassert_wait", &mxge_deassert_wait);
120 TUNABLE_INT("hw.mxge.ticks", &mxge_ticks);
121 TUNABLE_INT("hw.mxge.always_promisc", &mxge_always_promisc);
122 TUNABLE_INT("hw.mxge.throttle", &mxge_throttle);
123 TUNABLE_INT("hw.mxge.multi_tx", &mxge_multi_tx);
124 TUNABLE_INT("hw.mxge.use_rss", &mxge_use_rss);
125 TUNABLE_INT("hw.mxge.msi.enable", &mxge_msi_enable);
126 TUNABLE_INT("hw.mxge.msix.enable", &mxge_msix_enable);
128 static int mxge_probe(device_t dev);
129 static int mxge_attach(device_t dev);
130 static int mxge_detach(device_t dev);
131 static int mxge_shutdown(device_t dev);
133 static int mxge_alloc_intr(struct mxge_softc *sc);
134 static void mxge_free_intr(struct mxge_softc *sc);
135 static int mxge_setup_intr(struct mxge_softc *sc);
136 static void mxge_teardown_intr(struct mxge_softc *sc, int cnt);
138 static device_method_t mxge_methods[] = {
139 /* Device interface */
140 DEVMETHOD(device_probe, mxge_probe),
141 DEVMETHOD(device_attach, mxge_attach),
142 DEVMETHOD(device_detach, mxge_detach),
143 DEVMETHOD(device_shutdown, mxge_shutdown),
147 static driver_t mxge_driver = {
150 sizeof(mxge_softc_t),
153 static devclass_t mxge_devclass;
155 /* Declare ourselves to be a child of the PCI bus.*/
156 DRIVER_MODULE(mxge, pci, mxge_driver, mxge_devclass, NULL, NULL);
157 MODULE_DEPEND(mxge, firmware, 1, 1, 1);
158 MODULE_DEPEND(mxge, zlib, 1, 1, 1);
160 static int mxge_load_firmware(mxge_softc_t *sc, int adopt);
161 static int mxge_send_cmd(mxge_softc_t *sc, uint32_t cmd, mxge_cmd_t *data);
162 static void mxge_close(mxge_softc_t *sc, int down);
163 static int mxge_open(mxge_softc_t *sc);
164 static void mxge_tick(void *arg);
165 static void mxge_watchdog_reset(mxge_softc_t *sc);
166 static void mxge_warn_stuck(mxge_softc_t *sc, mxge_tx_ring_t *tx, int slice);
169 mxge_probe(device_t dev)
171 if (pci_get_vendor(dev) == MXGE_PCI_VENDOR_MYRICOM &&
172 (pci_get_device(dev) == MXGE_PCI_DEVICE_Z8E ||
173 pci_get_device(dev) == MXGE_PCI_DEVICE_Z8E_9)) {
174 int rev = pci_get_revid(dev);
177 case MXGE_PCI_REV_Z8E:
178 device_set_desc(dev, "Myri10G-PCIE-8A");
180 case MXGE_PCI_REV_Z8ES:
181 device_set_desc(dev, "Myri10G-PCIE-8B");
184 device_set_desc(dev, "Myri10G-PCIE-8??");
185 device_printf(dev, "Unrecognized rev %d NIC\n", rev);
194 mxge_enable_wc(mxge_softc_t *sc)
196 #if defined(__i386__) || defined(__x86_64__)
200 len = rman_get_size(sc->mem_res);
201 pmap_change_attr((vm_offset_t) sc->sram, len / PAGE_SIZE,
202 PAT_WRITE_COMBINING);
207 mxge_dma_alloc(mxge_softc_t *sc, bus_dmamem_t *dma, size_t bytes,
208 bus_size_t alignment)
213 if (bytes > 4096 && alignment == 4096)
218 err = bus_dmamem_coherent(sc->parent_dmat, alignment, boundary,
219 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, bytes,
220 BUS_DMA_WAITOK | BUS_DMA_ZERO, dma);
222 device_printf(sc->dev, "bus_dmamem_coherent failed: %d\n", err);
229 mxge_dma_free(bus_dmamem_t *dma)
231 bus_dmamap_unload(dma->dmem_tag, dma->dmem_map);
232 bus_dmamem_free(dma->dmem_tag, dma->dmem_addr, dma->dmem_map);
233 bus_dma_tag_destroy(dma->dmem_tag);
237 * The eeprom strings on the lanaiX have the format
243 mxge_parse_strings(mxge_softc_t *sc)
246 int i, found_mac, found_sn2;
249 ptr = sc->eeprom_strings;
252 while (*ptr != '\0') {
253 if (strncmp(ptr, "MAC=", 4) == 0) {
256 sc->mac_addr[i] = strtoul(ptr, &endptr, 16);
257 if (endptr - ptr != 2)
266 } else if (strncmp(ptr, "PC=", 3) == 0) {
268 strlcpy(sc->product_code_string, ptr,
269 sizeof(sc->product_code_string));
270 } else if (!found_sn2 && (strncmp(ptr, "SN=", 3) == 0)) {
272 strlcpy(sc->serial_number_string, ptr,
273 sizeof(sc->serial_number_string));
274 } else if (strncmp(ptr, "SN2=", 4) == 0) {
275 /* SN2 takes precedence over SN */
278 strlcpy(sc->serial_number_string, ptr,
279 sizeof(sc->serial_number_string));
281 while (*ptr++ != '\0') {}
288 device_printf(sc->dev, "failed to parse eeprom_strings\n");
292 #if defined(__i386__) || defined(__x86_64__)
295 mxge_enable_nvidia_ecrc(mxge_softc_t *sc)
298 unsigned long base, off;
300 device_t pdev, mcp55;
301 uint16_t vendor_id, device_id, word;
302 uintptr_t bus, slot, func, ivend, idev;
305 if (!mxge_nvidia_ecrc_enable)
308 pdev = device_get_parent(device_get_parent(sc->dev));
310 device_printf(sc->dev, "could not find parent?\n");
313 vendor_id = pci_read_config(pdev, PCIR_VENDOR, 2);
314 device_id = pci_read_config(pdev, PCIR_DEVICE, 2);
316 if (vendor_id != 0x10de)
321 if (device_id == 0x005d) {
322 /* ck804, base address is magic */
324 } else if (device_id >= 0x0374 && device_id <= 0x378) {
325 /* mcp55, base address stored in chipset */
326 mcp55 = pci_find_bsf(0, 0, 0);
328 0x10de == pci_read_config(mcp55, PCIR_VENDOR, 2) &&
329 0x0369 == pci_read_config(mcp55, PCIR_DEVICE, 2)) {
330 word = pci_read_config(mcp55, 0x90, 2);
331 base = ((unsigned long)word & 0x7ffeU) << 25;
339 * Test below is commented because it is believed that doing
340 * config read/write beyond 0xff will access the config space
341 * for the next larger function. Uncomment this and remove
342 * the hacky pmap_mapdev() way of accessing config space when
343 * DragonFly grows support for extended pcie config space access.
347 * See if we can, by some miracle, access the extended
350 val = pci_read_config(pdev, 0x178, 4);
351 if (val != 0xffffffff) {
353 pci_write_config(pdev, 0x178, val, 4);
358 * Rather than using normal pci config space writes, we must
359 * map the Nvidia config space ourselves. This is because on
360 * opteron/nvidia class machine the 0xe000000 mapping is
361 * handled by the nvidia chipset, that means the internal PCI
362 * device (the on-chip northbridge), or the amd-8131 bridge
363 * and things behind them are not visible by this method.
366 BUS_READ_IVAR(device_get_parent(pdev), pdev,
368 BUS_READ_IVAR(device_get_parent(pdev), pdev,
369 PCI_IVAR_SLOT, &slot);
370 BUS_READ_IVAR(device_get_parent(pdev), pdev,
371 PCI_IVAR_FUNCTION, &func);
372 BUS_READ_IVAR(device_get_parent(pdev), pdev,
373 PCI_IVAR_VENDOR, &ivend);
374 BUS_READ_IVAR(device_get_parent(pdev), pdev,
375 PCI_IVAR_DEVICE, &idev);
377 off = base + 0x00100000UL * (unsigned long)bus +
378 0x00001000UL * (unsigned long)(func + 8 * slot);
380 /* map it into the kernel */
381 va = pmap_mapdev(trunc_page((vm_paddr_t)off), PAGE_SIZE);
383 device_printf(sc->dev, "pmap_kenter_temporary didn't\n");
386 /* get a pointer to the config space mapped into the kernel */
387 cfgptr = va + (off & PAGE_MASK);
389 /* make sure that we can really access it */
390 vendor_id = *(uint16_t *)(cfgptr + PCIR_VENDOR);
391 device_id = *(uint16_t *)(cfgptr + PCIR_DEVICE);
392 if (!(vendor_id == ivend && device_id == idev)) {
393 device_printf(sc->dev, "mapping failed: 0x%x:0x%x\n",
394 vendor_id, device_id);
395 pmap_unmapdev((vm_offset_t)va, PAGE_SIZE);
399 ptr32 = (uint32_t*)(cfgptr + 0x178);
402 if (val == 0xffffffff) {
403 device_printf(sc->dev, "extended mapping failed\n");
404 pmap_unmapdev((vm_offset_t)va, PAGE_SIZE);
408 pmap_unmapdev((vm_offset_t)va, PAGE_SIZE);
410 device_printf(sc->dev, "Enabled ECRC on upstream "
411 "Nvidia bridge at %d:%d:%d\n",
412 (int)bus, (int)slot, (int)func);
416 #else /* __i386__ || __x86_64__ */
419 mxge_enable_nvidia_ecrc(mxge_softc_t *sc)
421 device_printf(sc->dev, "Nforce 4 chipset on non-x86/x86_64!?!?!\n");
427 mxge_dma_test(mxge_softc_t *sc, int test_type)
430 bus_addr_t dmatest_bus = sc->dmabench_dma.dmem_busaddr;
433 const char *test = " ";
436 * Run a small DMA test.
437 * The magic multipliers to the length tell the firmware
438 * to do DMA read, write, or read+write tests. The
439 * results are returned in cmd.data0. The upper 16
440 * bits of the return is the number of transfers completed.
441 * The lower 16 bits is the time in 0.5us ticks that the
442 * transfers took to complete.
445 len = sc->tx_boundary;
447 cmd.data0 = MXGE_LOWPART_TO_U32(dmatest_bus);
448 cmd.data1 = MXGE_HIGHPART_TO_U32(dmatest_bus);
449 cmd.data2 = len * 0x10000;
450 status = mxge_send_cmd(sc, test_type, &cmd);
455 sc->read_dma = ((cmd.data0>>16) * len * 2) / (cmd.data0 & 0xffff);
457 cmd.data0 = MXGE_LOWPART_TO_U32(dmatest_bus);
458 cmd.data1 = MXGE_HIGHPART_TO_U32(dmatest_bus);
459 cmd.data2 = len * 0x1;
460 status = mxge_send_cmd(sc, test_type, &cmd);
465 sc->write_dma = ((cmd.data0>>16) * len * 2) / (cmd.data0 & 0xffff);
467 cmd.data0 = MXGE_LOWPART_TO_U32(dmatest_bus);
468 cmd.data1 = MXGE_HIGHPART_TO_U32(dmatest_bus);
469 cmd.data2 = len * 0x10001;
470 status = mxge_send_cmd(sc, test_type, &cmd);
475 sc->read_write_dma = ((cmd.data0>>16) * len * 2 * 2) /
476 (cmd.data0 & 0xffff);
479 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST) {
480 device_printf(sc->dev, "DMA %s benchmark failed: %d\n",
487 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
488 * when the PCI-E Completion packets are aligned on an 8-byte
489 * boundary. Some PCI-E chip sets always align Completion packets; on
490 * the ones that do not, the alignment can be enforced by enabling
491 * ECRC generation (if supported).
493 * When PCI-E Completion packets are not aligned, it is actually more
494 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
496 * If the driver can neither enable ECRC nor verify that it has
497 * already been enabled, then it must use a firmware image which works
498 * around unaligned completion packets (ethp_z8e.dat), and it should
499 * also ensure that it never gives the device a Read-DMA which is
500 * larger than 2KB by setting the tx_boundary to 2KB. If ECRC is
501 * enabled, then the driver should use the aligned (eth_z8e.dat)
502 * firmware image, and set tx_boundary to 4KB.
505 mxge_firmware_probe(mxge_softc_t *sc)
507 device_t dev = sc->dev;
511 sc->tx_boundary = 4096;
514 * Verify the max read request size was set to 4KB
515 * before trying the test with 4KB.
517 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) {
518 pectl = pci_read_config(dev, reg + 0x8, 2);
519 if ((pectl & (5 << 12)) != (5 << 12)) {
520 device_printf(dev, "Max Read Req. size != 4k (0x%x)\n",
522 sc->tx_boundary = 2048;
527 * Load the optimized firmware (which assumes aligned PCIe
528 * completions) in order to see if it works on this host.
530 sc->fw_name = mxge_fw_aligned;
531 status = mxge_load_firmware(sc, 1);
536 * Enable ECRC if possible
538 mxge_enable_nvidia_ecrc(sc);
541 * Run a DMA test which watches for unaligned completions and
542 * aborts on the first one seen. Not required on Z8ES or newer.
544 if (pci_get_revid(sc->dev) >= MXGE_PCI_REV_Z8ES)
547 status = mxge_dma_test(sc, MXGEFW_CMD_UNALIGNED_TEST);
549 return 0; /* keep the aligned firmware */
552 device_printf(dev, "DMA test failed: %d\n", status);
553 if (status == ENOSYS) {
554 device_printf(dev, "Falling back to ethp! "
555 "Please install up to date fw\n");
561 mxge_select_firmware(mxge_softc_t *sc)
564 int force_firmware = mxge_force_firmware;
567 force_firmware = sc->throttle;
569 if (force_firmware != 0) {
570 if (force_firmware == 1)
575 device_printf(sc->dev,
576 "Assuming %s completions (forced)\n",
577 aligned ? "aligned" : "unaligned");
583 * If the PCIe link width is 4 or less, we can use the aligned
584 * firmware and skip any checks
586 if (sc->link_width != 0 && sc->link_width <= 4) {
587 device_printf(sc->dev, "PCIe x%d Link, "
588 "expect reduced performance\n", sc->link_width);
593 if (mxge_firmware_probe(sc) == 0)
598 sc->fw_name = mxge_fw_aligned;
599 sc->tx_boundary = 4096;
601 sc->fw_name = mxge_fw_unaligned;
602 sc->tx_boundary = 2048;
604 return mxge_load_firmware(sc, 0);
608 mxge_validate_firmware(mxge_softc_t *sc, const mcp_gen_header_t *hdr)
610 if (be32toh(hdr->mcp_type) != MCP_TYPE_ETH) {
611 if_printf(sc->ifp, "Bad firmware type: 0x%x\n",
612 be32toh(hdr->mcp_type));
616 /* Save firmware version for sysctl */
617 strlcpy(sc->fw_version, hdr->version, sizeof(sc->fw_version));
619 if_printf(sc->ifp, "firmware id: %s\n", hdr->version);
621 ksscanf(sc->fw_version, "%d.%d.%d", &sc->fw_ver_major,
622 &sc->fw_ver_minor, &sc->fw_ver_tiny);
624 if (!(sc->fw_ver_major == MXGEFW_VERSION_MAJOR &&
625 sc->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
626 if_printf(sc->ifp, "Found firmware version %s\n",
628 if_printf(sc->ifp, "Driver needs %d.%d\n",
629 MXGEFW_VERSION_MAJOR, MXGEFW_VERSION_MINOR);
636 z_alloc(void *nil, u_int items, u_int size)
638 return kmalloc(items * size, M_TEMP, M_WAITOK);
642 z_free(void *nil, void *ptr)
648 mxge_load_firmware_helper(mxge_softc_t *sc, uint32_t *limit)
651 char *inflate_buffer;
652 const struct firmware *fw;
653 const mcp_gen_header_t *hdr;
660 fw = firmware_get(sc->fw_name);
662 if_printf(sc->ifp, "Could not find firmware image %s\n",
667 /* Setup zlib and decompress f/w */
668 bzero(&zs, sizeof(zs));
671 status = inflateInit(&zs);
672 if (status != Z_OK) {
678 * The uncompressed size is stored as the firmware version,
679 * which would otherwise go unused
681 fw_len = (size_t)fw->version;
682 inflate_buffer = kmalloc(fw_len, M_TEMP, M_WAITOK);
683 zs.avail_in = fw->datasize;
684 zs.next_in = __DECONST(char *, fw->data);
685 zs.avail_out = fw_len;
686 zs.next_out = inflate_buffer;
687 status = inflate(&zs, Z_FINISH);
688 if (status != Z_STREAM_END) {
689 if_printf(sc->ifp, "zlib %d\n", status);
691 goto abort_with_buffer;
696 htobe32(*(const uint32_t *)(inflate_buffer + MCP_HEADER_PTR_OFFSET));
697 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw_len) {
698 if_printf(sc->ifp, "Bad firmware file");
700 goto abort_with_buffer;
702 hdr = (const void*)(inflate_buffer + hdr_offset);
704 status = mxge_validate_firmware(sc, hdr);
706 goto abort_with_buffer;
708 /* Copy the inflated firmware to NIC SRAM. */
709 for (i = 0; i < fw_len; i += 256) {
710 mxge_pio_copy(sc->sram + MXGE_FW_OFFSET + i, inflate_buffer + i,
711 min(256U, (unsigned)(fw_len - i)));
720 kfree(inflate_buffer, M_TEMP);
723 firmware_put(fw, FIRMWARE_UNLOAD);
728 * Enable or disable periodic RDMAs from the host to make certain
729 * chipsets resend dropped PCIe messages
732 mxge_dummy_rdma(mxge_softc_t *sc, int enable)
735 volatile uint32_t *confirm;
736 volatile char *submit;
737 uint32_t *buf, dma_low, dma_high;
740 buf = (uint32_t *)((unsigned long)(buf_bytes + 7) & ~7UL);
742 /* Clear confirmation addr */
743 confirm = (volatile uint32_t *)sc->cmd;
748 * Send an rdma command to the PCIe engine, and wait for the
749 * response in the confirmation address. The firmware should
750 * write a -1 there to indicate it is alive and well
752 dma_low = MXGE_LOWPART_TO_U32(sc->cmd_dma.dmem_busaddr);
753 dma_high = MXGE_HIGHPART_TO_U32(sc->cmd_dma.dmem_busaddr);
754 buf[0] = htobe32(dma_high); /* confirm addr MSW */
755 buf[1] = htobe32(dma_low); /* confirm addr LSW */
756 buf[2] = htobe32(0xffffffff); /* confirm data */
757 dma_low = MXGE_LOWPART_TO_U32(sc->zeropad_dma.dmem_busaddr);
758 dma_high = MXGE_HIGHPART_TO_U32(sc->zeropad_dma.dmem_busaddr);
759 buf[3] = htobe32(dma_high); /* dummy addr MSW */
760 buf[4] = htobe32(dma_low); /* dummy addr LSW */
761 buf[5] = htobe32(enable); /* enable? */
763 submit = (volatile char *)(sc->sram + MXGEFW_BOOT_DUMMY_RDMA);
765 mxge_pio_copy(submit, buf, 64);
770 while (*confirm != 0xffffffff && i < 20) {
774 if (*confirm != 0xffffffff) {
775 if_printf(sc->ifp, "dummy rdma %s failed (%p = 0x%x)",
776 (enable ? "enable" : "disable"), confirm, *confirm);
781 mxge_send_cmd(mxge_softc_t *sc, uint32_t cmd, mxge_cmd_t *data)
784 char buf_bytes[sizeof(*buf) + 8];
785 volatile mcp_cmd_response_t *response = sc->cmd;
786 volatile char *cmd_addr = sc->sram + MXGEFW_ETH_CMD;
787 uint32_t dma_low, dma_high;
788 int err, sleep_total = 0;
790 /* Ensure buf is aligned to 8 bytes */
791 buf = (mcp_cmd_t *)((unsigned long)(buf_bytes + 7) & ~7UL);
793 buf->data0 = htobe32(data->data0);
794 buf->data1 = htobe32(data->data1);
795 buf->data2 = htobe32(data->data2);
796 buf->cmd = htobe32(cmd);
797 dma_low = MXGE_LOWPART_TO_U32(sc->cmd_dma.dmem_busaddr);
798 dma_high = MXGE_HIGHPART_TO_U32(sc->cmd_dma.dmem_busaddr);
800 buf->response_addr.low = htobe32(dma_low);
801 buf->response_addr.high = htobe32(dma_high);
803 response->result = 0xffffffff;
805 mxge_pio_copy((volatile void *)cmd_addr, buf, sizeof (*buf));
811 for (sleep_total = 0; sleep_total < 20; sleep_total++) {
813 switch (be32toh(response->result)) {
815 data->data0 = be32toh(response->data);
821 case MXGEFW_CMD_UNKNOWN:
824 case MXGEFW_CMD_ERROR_UNALIGNED:
827 case MXGEFW_CMD_ERROR_BUSY:
830 case MXGEFW_CMD_ERROR_I2C_ABSENT:
834 if_printf(sc->ifp, "command %d failed, result = %d\n",
835 cmd, be32toh(response->result));
843 if_printf(sc->ifp, "command %d timed out result = %d\n",
844 cmd, be32toh(response->result));
850 mxge_adopt_running_firmware(mxge_softc_t *sc)
852 struct mcp_gen_header *hdr;
853 const size_t bytes = sizeof(struct mcp_gen_header);
858 * Find running firmware header
861 htobe32(*(volatile uint32_t *)(sc->sram + MCP_HEADER_PTR_OFFSET));
863 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > sc->sram_size) {
864 if_printf(sc->ifp, "Running firmware has bad header offset "
865 "(%zu)\n", hdr_offset);
870 * Copy header of running firmware from SRAM to host memory to
873 hdr = kmalloc(bytes, M_DEVBUF, M_WAITOK);
874 bus_space_read_region_1(rman_get_bustag(sc->mem_res),
875 rman_get_bushandle(sc->mem_res), hdr_offset, (char *)hdr, bytes);
876 status = mxge_validate_firmware(sc, hdr);
877 kfree(hdr, M_DEVBUF);
880 * Check to see if adopted firmware has bug where adopting
881 * it will cause broadcasts to be filtered unless the NIC
882 * is kept in ALLMULTI mode
884 if (sc->fw_ver_major == 1 && sc->fw_ver_minor == 4 &&
885 sc->fw_ver_tiny >= 4 && sc->fw_ver_tiny <= 11) {
886 sc->adopted_rx_filter_bug = 1;
887 if_printf(sc->ifp, "Adopting fw %d.%d.%d: "
888 "working around rx filter bug\n",
889 sc->fw_ver_major, sc->fw_ver_minor, sc->fw_ver_tiny);
896 mxge_load_firmware(mxge_softc_t *sc, int adopt)
898 volatile uint32_t *confirm;
899 volatile char *submit;
901 uint32_t *buf, size, dma_low, dma_high;
904 buf = (uint32_t *)((unsigned long)(buf_bytes + 7) & ~7UL);
906 size = sc->sram_size;
907 status = mxge_load_firmware_helper(sc, &size);
913 * Try to use the currently running firmware, if
916 status = mxge_adopt_running_firmware(sc);
919 "failed to adopt running firmware\n");
922 if_printf(sc->ifp, "Successfully adopted running firmware\n");
924 if (sc->tx_boundary == 4096) {
926 "Using firmware currently running on NIC. "
928 if_printf(sc->ifp, "performance consider loading "
929 "optimized firmware\n");
931 sc->fw_name = mxge_fw_unaligned;
932 sc->tx_boundary = 2048;
936 /* Clear confirmation addr */
937 confirm = (volatile uint32_t *)sc->cmd;
942 * Send a reload command to the bootstrap MCP, and wait for the
943 * response in the confirmation address. The firmware should
944 * write a -1 there to indicate it is alive and well
947 dma_low = MXGE_LOWPART_TO_U32(sc->cmd_dma.dmem_busaddr);
948 dma_high = MXGE_HIGHPART_TO_U32(sc->cmd_dma.dmem_busaddr);
950 buf[0] = htobe32(dma_high); /* confirm addr MSW */
951 buf[1] = htobe32(dma_low); /* confirm addr LSW */
952 buf[2] = htobe32(0xffffffff); /* confirm data */
955 * FIX: All newest firmware should un-protect the bottom of
956 * the sram before handoff. However, the very first interfaces
957 * do not. Therefore the handoff copy must skip the first 8 bytes
959 /* where the code starts*/
960 buf[3] = htobe32(MXGE_FW_OFFSET + 8);
961 buf[4] = htobe32(size - 8); /* length of code */
962 buf[5] = htobe32(8); /* where to copy to */
963 buf[6] = htobe32(0); /* where to jump to */
965 submit = (volatile char *)(sc->sram + MXGEFW_BOOT_HANDOFF);
966 mxge_pio_copy(submit, buf, 64);
971 while (*confirm != 0xffffffff && i < 20) {
975 if (*confirm != 0xffffffff) {
976 if_printf(sc->ifp,"handoff failed (%p = 0x%x)",
984 mxge_update_mac_address(mxge_softc_t *sc)
987 uint8_t *addr = sc->mac_addr;
989 cmd.data0 = (addr[0] << 24) | (addr[1] << 16) |
990 (addr[2] << 8) | addr[3];
991 cmd.data1 = (addr[4] << 8) | (addr[5]);
992 return mxge_send_cmd(sc, MXGEFW_SET_MAC_ADDRESS, &cmd);
996 mxge_change_pause(mxge_softc_t *sc, int pause)
1002 status = mxge_send_cmd(sc, MXGEFW_ENABLE_FLOW_CONTROL, &cmd);
1004 status = mxge_send_cmd(sc, MXGEFW_DISABLE_FLOW_CONTROL, &cmd);
1006 if_printf(sc->ifp, "Failed to set flow control mode\n");
1014 mxge_change_promisc(mxge_softc_t *sc, int promisc)
1019 if (mxge_always_promisc)
1023 status = mxge_send_cmd(sc, MXGEFW_ENABLE_PROMISC, &cmd);
1025 status = mxge_send_cmd(sc, MXGEFW_DISABLE_PROMISC, &cmd);
1027 if_printf(sc->ifp, "Failed to set promisc mode\n");
1031 mxge_set_multicast_list(mxge_softc_t *sc)
1034 struct ifmultiaddr *ifma;
1035 struct ifnet *ifp = sc->ifp;
1038 /* This firmware is known to not support multicast */
1039 if (!sc->fw_multicast_support)
1042 /* Disable multicast filtering while we play with the lists*/
1043 err = mxge_send_cmd(sc, MXGEFW_ENABLE_ALLMULTI, &cmd);
1045 if_printf(ifp, "Failed MXGEFW_ENABLE_ALLMULTI, "
1046 "error status: %d\n", err);
1050 if (sc->adopted_rx_filter_bug)
1053 if (ifp->if_flags & IFF_ALLMULTI) {
1054 /* Request to disable multicast filtering, so quit here */
1058 /* Flush all the filters */
1059 err = mxge_send_cmd(sc, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS, &cmd);
1061 if_printf(ifp, "Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS, "
1062 "error status: %d\n", err);
1067 * Walk the multicast list, and add each address
1069 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1070 if (ifma->ifma_addr->sa_family != AF_LINK)
1073 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1075 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr) + 4,
1077 cmd.data0 = htonl(cmd.data0);
1078 cmd.data1 = htonl(cmd.data1);
1079 err = mxge_send_cmd(sc, MXGEFW_JOIN_MULTICAST_GROUP, &cmd);
1081 if_printf(ifp, "Failed MXGEFW_JOIN_MULTICAST_GROUP, "
1082 "error status: %d\n", err);
1083 /* Abort, leaving multicast filtering off */
1088 /* Enable multicast filtering */
1089 err = mxge_send_cmd(sc, MXGEFW_DISABLE_ALLMULTI, &cmd);
1091 if_printf(ifp, "Failed MXGEFW_DISABLE_ALLMULTI, "
1092 "error status: %d\n", err);
1098 mxge_max_mtu(mxge_softc_t *sc)
1103 if (MJUMPAGESIZE - MXGEFW_PAD > MXGEFW_MAX_MTU)
1104 return MXGEFW_MAX_MTU - MXGEFW_PAD;
1106 /* try to set nbufs to see if it we can
1107 use virtually contiguous jumbos */
1109 status = mxge_send_cmd(sc, MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS,
1112 return MXGEFW_MAX_MTU - MXGEFW_PAD;
1114 /* otherwise, we're limited to MJUMPAGESIZE */
1115 return MJUMPAGESIZE - MXGEFW_PAD;
1120 mxge_reset(mxge_softc_t *sc, int interrupts_setup)
1122 struct mxge_slice_state *ss;
1123 mxge_rx_done_t *rx_done;
1124 volatile uint32_t *irq_claim;
1126 int slice, status, rx_intr_size;
1129 * Try to send a reset command to the card to see if it
1132 memset(&cmd, 0, sizeof (cmd));
1133 status = mxge_send_cmd(sc, MXGEFW_CMD_RESET, &cmd);
1135 if_printf(sc->ifp, "failed reset\n");
1139 mxge_dummy_rdma(sc, 1);
1142 * Set the intrq size
1143 * XXX assume 4byte mcp_slot
1145 rx_intr_size = sc->rx_intr_slots * sizeof(mcp_slot_t);
1146 cmd.data0 = rx_intr_size;
1147 status = mxge_send_cmd(sc, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd);
1150 * Even though we already know how many slices are supported
1151 * via mxge_slice_probe(), MXGEFW_CMD_GET_MAX_RSS_QUEUES
1152 * has magic side effects, and must be called after a reset.
1153 * It must be called prior to calling any RSS related cmds,
1154 * including assigning an interrupt queue for anything but
1155 * slice 0. It must also be called *after*
1156 * MXGEFW_CMD_SET_INTRQ_SIZE, since the intrq size is used by
1157 * the firmware to compute offsets.
1159 if (sc->num_slices > 1) {
1160 /* Ask the maximum number of slices it supports */
1161 status = mxge_send_cmd(sc, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd);
1163 if_printf(sc->ifp, "failed to get number of slices\n");
1168 * MXGEFW_CMD_ENABLE_RSS_QUEUES must be called prior
1169 * to setting up the interrupt queue DMA
1171 cmd.data0 = sc->num_slices;
1172 cmd.data1 = MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE;
1173 if (sc->num_tx_rings > 1)
1174 cmd.data1 |= MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES;
1175 status = mxge_send_cmd(sc, MXGEFW_CMD_ENABLE_RSS_QUEUES, &cmd);
1177 if_printf(sc->ifp, "failed to set number of slices\n");
1182 if (interrupts_setup) {
1183 /* Now exchange information about interrupts */
1184 for (slice = 0; slice < sc->num_slices; slice++) {
1185 ss = &sc->ss[slice];
1187 rx_done = &ss->rx_data.rx_done;
1188 memset(rx_done->entry, 0, rx_intr_size);
1191 MXGE_LOWPART_TO_U32(ss->rx_done_dma.dmem_busaddr);
1193 MXGE_HIGHPART_TO_U32(ss->rx_done_dma.dmem_busaddr);
1195 status |= mxge_send_cmd(sc, MXGEFW_CMD_SET_INTRQ_DMA,
1200 status |= mxge_send_cmd(sc, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET,
1202 sc->intr_coal_delay_ptr = (volatile uint32_t *)(sc->sram + cmd.data0);
1204 status |= mxge_send_cmd(sc, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd);
1205 irq_claim = (volatile uint32_t *)(sc->sram + cmd.data0);
1207 status |= mxge_send_cmd(sc, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET, &cmd);
1208 sc->irq_deassert = (volatile uint32_t *)(sc->sram + cmd.data0);
1211 if_printf(sc->ifp, "failed set interrupt parameters\n");
1215 *sc->intr_coal_delay_ptr = htobe32(sc->intr_coal_delay);
1217 /* Run a DMA benchmark */
1218 mxge_dma_test(sc, MXGEFW_DMA_TEST);
1220 for (slice = 0; slice < sc->num_slices; slice++) {
1221 ss = &sc->ss[slice];
1223 ss->irq_claim = irq_claim + (2 * slice);
1225 /* Reset mcp/driver shared state back to 0 */
1226 ss->rx_data.rx_done.idx = 0;
1229 ss->tx.pkt_done = 0;
1230 ss->tx.queue_active = 0;
1231 ss->tx.activate = 0;
1232 ss->tx.deactivate = 0;
1233 ss->rx_data.rx_big.cnt = 0;
1234 ss->rx_data.rx_small.cnt = 0;
1235 if (ss->fw_stats != NULL)
1236 bzero(ss->fw_stats, sizeof(*ss->fw_stats));
1238 sc->rdma_tags_available = 15;
1240 status = mxge_update_mac_address(sc);
1241 mxge_change_promisc(sc, sc->ifp->if_flags & IFF_PROMISC);
1242 mxge_change_pause(sc, sc->pause);
1243 mxge_set_multicast_list(sc);
1246 cmd.data0 = sc->throttle;
1247 if (mxge_send_cmd(sc, MXGEFW_CMD_SET_THROTTLE_FACTOR, &cmd))
1248 if_printf(sc->ifp, "can't enable throttle\n");
1254 mxge_change_throttle(SYSCTL_HANDLER_ARGS)
1259 unsigned int throttle;
1262 throttle = sc->throttle;
1263 err = sysctl_handle_int(oidp, &throttle, arg2, req);
1267 if (throttle == sc->throttle)
1270 if (throttle < MXGE_MIN_THROTTLE || throttle > MXGE_MAX_THROTTLE)
1273 ifnet_serialize_all(sc->ifp);
1275 cmd.data0 = throttle;
1276 err = mxge_send_cmd(sc, MXGEFW_CMD_SET_THROTTLE_FACTOR, &cmd);
1278 sc->throttle = throttle;
1280 ifnet_deserialize_all(sc->ifp);
1285 mxge_change_use_rss(SYSCTL_HANDLER_ARGS)
1291 use_rss = sc->use_rss;
1292 err = sysctl_handle_int(oidp, &use_rss, arg2, req);
1296 if (use_rss == sc->use_rss)
1299 ifnet_serialize_all(sc->ifp);
1301 sc->use_rss = use_rss;
1302 if (sc->ifp->if_flags & IFF_RUNNING) {
1307 ifnet_deserialize_all(sc->ifp);
1312 mxge_change_intr_coal(SYSCTL_HANDLER_ARGS)
1315 unsigned int intr_coal_delay;
1319 intr_coal_delay = sc->intr_coal_delay;
1320 err = sysctl_handle_int(oidp, &intr_coal_delay, arg2, req);
1324 if (intr_coal_delay == sc->intr_coal_delay)
1327 if (intr_coal_delay == 0 || intr_coal_delay > 1000*1000)
1330 ifnet_serialize_all(sc->ifp);
1332 *sc->intr_coal_delay_ptr = htobe32(intr_coal_delay);
1333 sc->intr_coal_delay = intr_coal_delay;
1335 ifnet_deserialize_all(sc->ifp);
1340 mxge_change_flow_control(SYSCTL_HANDLER_ARGS)
1343 unsigned int enabled;
1347 enabled = sc->pause;
1348 err = sysctl_handle_int(oidp, &enabled, arg2, req);
1352 if (enabled == sc->pause)
1355 ifnet_serialize_all(sc->ifp);
1356 err = mxge_change_pause(sc, enabled);
1357 ifnet_deserialize_all(sc->ifp);
1363 mxge_handle_be32(SYSCTL_HANDLER_ARGS)
1369 arg2 = be32toh(*(int *)arg1);
1371 err = sysctl_handle_int(oidp, arg1, arg2, req);
1377 mxge_rem_sysctls(mxge_softc_t *sc)
1379 if (sc->ss != NULL) {
1380 struct mxge_slice_state *ss;
1383 for (slice = 0; slice < sc->num_slices; slice++) {
1384 ss = &sc->ss[slice];
1385 if (ss->sysctl_tree != NULL) {
1386 sysctl_ctx_free(&ss->sysctl_ctx);
1387 ss->sysctl_tree = NULL;
1392 if (sc->slice_sysctl_tree != NULL) {
1393 sysctl_ctx_free(&sc->slice_sysctl_ctx);
1394 sc->slice_sysctl_tree = NULL;
1397 if (sc->sysctl_tree != NULL) {
1398 sysctl_ctx_free(&sc->sysctl_ctx);
1399 sc->sysctl_tree = NULL;
1404 mxge_add_sysctls(mxge_softc_t *sc)
1406 struct sysctl_ctx_list *ctx;
1407 struct sysctl_oid_list *children;
1409 struct mxge_slice_state *ss;
1413 ctx = &sc->sysctl_ctx;
1414 sysctl_ctx_init(ctx);
1415 sc->sysctl_tree = SYSCTL_ADD_NODE(ctx, SYSCTL_STATIC_CHILDREN(_hw),
1416 OID_AUTO, device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "");
1417 if (sc->sysctl_tree == NULL) {
1418 device_printf(sc->dev, "can't add sysctl node\n");
1422 children = SYSCTL_CHILDREN(sc->sysctl_tree);
1423 fw = sc->ss[0].fw_stats;
1426 * Random information
1428 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version",
1429 CTLFLAG_RD, &sc->fw_version, 0, "firmware version");
1431 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "serial_number",
1432 CTLFLAG_RD, &sc->serial_number_string, 0, "serial number");
1434 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "product_code",
1435 CTLFLAG_RD, &sc->product_code_string, 0, "product code");
1437 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "pcie_link_width",
1438 CTLFLAG_RD, &sc->link_width, 0, "link width");
1440 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_boundary",
1441 CTLFLAG_RD, &sc->tx_boundary, 0, "tx boundary");
1443 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "write_combine",
1444 CTLFLAG_RD, &sc->wc, 0, "write combining PIO");
1446 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "read_dma_MBs",
1447 CTLFLAG_RD, &sc->read_dma, 0, "DMA Read speed in MB/s");
1449 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "write_dma_MBs",
1450 CTLFLAG_RD, &sc->write_dma, 0, "DMA Write speed in MB/s");
1452 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "read_write_dma_MBs",
1453 CTLFLAG_RD, &sc->read_write_dma, 0,
1454 "DMA concurrent Read/Write speed in MB/s");
1456 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "watchdog_resets",
1457 CTLFLAG_RD, &sc->watchdog_resets, 0,
1458 "Number of times NIC was reset");
1461 * Performance related tunables
1463 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "intr_coal_delay",
1464 CTLTYPE_INT|CTLFLAG_RW, sc, 0, mxge_change_intr_coal, "I",
1465 "Interrupt coalescing delay in usecs");
1467 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "throttle",
1468 CTLTYPE_INT|CTLFLAG_RW, sc, 0, mxge_change_throttle, "I",
1469 "Transmit throttling");
1471 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "flow_control_enabled",
1472 CTLTYPE_INT|CTLFLAG_RW, sc, 0, mxge_change_flow_control, "I",
1473 "Interrupt coalescing delay in usecs");
1475 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "use_rss",
1476 CTLTYPE_INT|CTLFLAG_RW, sc, 0, mxge_change_use_rss, "I",
1479 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "deassert_wait",
1480 CTLFLAG_RW, &mxge_deassert_wait, 0,
1481 "Wait for IRQ line to go low in ihandler");
1484 * Stats block from firmware is in network byte order.
1487 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "link_up",
1488 CTLTYPE_INT|CTLFLAG_RD, &fw->link_up, 0,
1489 mxge_handle_be32, "I", "link up");
1491 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_tags_available",
1492 CTLTYPE_INT|CTLFLAG_RD, &fw->rdma_tags_available, 0,
1493 mxge_handle_be32, "I", "rdma_tags_available");
1495 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dropped_bad_crc32",
1496 CTLTYPE_INT|CTLFLAG_RD, &fw->dropped_bad_crc32, 0,
1497 mxge_handle_be32, "I", "dropped_bad_crc32");
1499 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dropped_bad_phy",
1500 CTLTYPE_INT|CTLFLAG_RD, &fw->dropped_bad_phy, 0,
1501 mxge_handle_be32, "I", "dropped_bad_phy");
1503 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dropped_link_error_or_filtered",
1504 CTLTYPE_INT|CTLFLAG_RD, &fw->dropped_link_error_or_filtered, 0,
1505 mxge_handle_be32, "I", "dropped_link_error_or_filtered");
1507 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dropped_link_overflow",
1508 CTLTYPE_INT|CTLFLAG_RD, &fw->dropped_link_overflow, 0,
1509 mxge_handle_be32, "I", "dropped_link_overflow");
1511 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dropped_multicast_filtered",
1512 CTLTYPE_INT|CTLFLAG_RD, &fw->dropped_multicast_filtered, 0,
1513 mxge_handle_be32, "I", "dropped_multicast_filtered");
1515 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dropped_no_big_buffer",
1516 CTLTYPE_INT|CTLFLAG_RD, &fw->dropped_no_big_buffer, 0,
1517 mxge_handle_be32, "I", "dropped_no_big_buffer");
1519 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dropped_no_small_buffer",
1520 CTLTYPE_INT|CTLFLAG_RD, &fw->dropped_no_small_buffer, 0,
1521 mxge_handle_be32, "I", "dropped_no_small_buffer");
1523 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dropped_overrun",
1524 CTLTYPE_INT|CTLFLAG_RD, &fw->dropped_overrun, 0,
1525 mxge_handle_be32, "I", "dropped_overrun");
1527 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dropped_pause",
1528 CTLTYPE_INT|CTLFLAG_RD, &fw->dropped_pause, 0,
1529 mxge_handle_be32, "I", "dropped_pause");
1531 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dropped_runt",
1532 CTLTYPE_INT|CTLFLAG_RD, &fw->dropped_runt, 0,
1533 mxge_handle_be32, "I", "dropped_runt");
1535 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dropped_unicast_filtered",
1536 CTLTYPE_INT|CTLFLAG_RD, &fw->dropped_unicast_filtered, 0,
1537 mxge_handle_be32, "I", "dropped_unicast_filtered");
1539 /* add counters exported for debugging from all slices */
1540 sysctl_ctx_init(&sc->slice_sysctl_ctx);
1541 sc->slice_sysctl_tree = SYSCTL_ADD_NODE(&sc->slice_sysctl_ctx,
1542 children, OID_AUTO, "slice", CTLFLAG_RD, 0, "");
1543 if (sc->slice_sysctl_tree == NULL) {
1544 device_printf(sc->dev, "can't add slice sysctl node\n");
1548 for (slice = 0; slice < sc->num_slices; slice++) {
1549 ss = &sc->ss[slice];
1550 sysctl_ctx_init(&ss->sysctl_ctx);
1551 ctx = &ss->sysctl_ctx;
1552 children = SYSCTL_CHILDREN(sc->slice_sysctl_tree);
1553 ksprintf(slice_num, "%d", slice);
1554 ss->sysctl_tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO,
1555 slice_num, CTLFLAG_RD, 0, "");
1556 if (ss->sysctl_tree == NULL) {
1557 device_printf(sc->dev,
1558 "can't add %d slice sysctl node\n", slice);
1559 return; /* XXX continue? */
1561 children = SYSCTL_CHILDREN(ss->sysctl_tree);
1564 * XXX change to ULONG
1567 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_small_cnt",
1568 CTLFLAG_RD, &ss->rx_data.rx_small.cnt, 0, "rx_small_cnt");
1570 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_big_cnt",
1571 CTLFLAG_RD, &ss->rx_data.rx_big.cnt, 0, "rx_small_cnt");
1573 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_req",
1574 CTLFLAG_RD, &ss->tx.req, 0, "tx_req");
1576 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_done",
1577 CTLFLAG_RD, &ss->tx.done, 0, "tx_done");
1579 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_pkt_done",
1580 CTLFLAG_RD, &ss->tx.pkt_done, 0, "tx_done");
1582 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_queue_active",
1583 CTLFLAG_RD, &ss->tx.queue_active, 0, "tx_queue_active");
1585 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_activate",
1586 CTLFLAG_RD, &ss->tx.activate, 0, "tx_activate");
1588 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_deactivate",
1589 CTLFLAG_RD, &ss->tx.deactivate, 0, "tx_deactivate");
1594 * Copy an array of mcp_kreq_ether_send_t's to the mcp. Copy
1595 * backwards one at a time and handle ring wraps
1597 static __inline void
1598 mxge_submit_req_backwards(mxge_tx_ring_t *tx,
1599 mcp_kreq_ether_send_t *src, int cnt)
1601 int idx, starting_slot;
1603 starting_slot = tx->req;
1606 idx = (starting_slot + cnt) & tx->mask;
1607 mxge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
1613 * Copy an array of mcp_kreq_ether_send_t's to the mcp. Copy
1614 * at most 32 bytes at a time, so as to avoid involving the software
1615 * pio handler in the nic. We re-write the first segment's flags
1616 * to mark them valid only after writing the entire chain
1618 static __inline void
1619 mxge_submit_req(mxge_tx_ring_t *tx, mcp_kreq_ether_send_t *src, int cnt)
1623 volatile uint32_t *dst_ints;
1624 mcp_kreq_ether_send_t *srcp;
1625 volatile mcp_kreq_ether_send_t *dstp, *dst;
1628 idx = tx->req & tx->mask;
1630 last_flags = src->flags;
1633 dst = dstp = &tx->lanai[idx];
1636 if ((idx + cnt) < tx->mask) {
1637 for (i = 0; i < cnt - 1; i += 2) {
1638 mxge_pio_copy(dstp, srcp, 2 * sizeof(*src));
1639 wmb(); /* force write every 32 bytes */
1645 * Submit all but the first request, and ensure
1646 * that it is submitted below
1648 mxge_submit_req_backwards(tx, src, cnt);
1652 /* Submit the first request */
1653 mxge_pio_copy(dstp, srcp, sizeof(*src));
1654 wmb(); /* barrier before setting valid flag */
1657 /* Re-write the last 32-bits with the valid flags */
1658 src->flags = last_flags;
1659 src_ints = (uint32_t *)src;
1661 dst_ints = (volatile uint32_t *)dst;
1663 *dst_ints = *src_ints;
1669 mxge_pullup_tso(struct mbuf **mp)
1671 int hoff, iphlen, thoff;
1675 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
1677 iphlen = m->m_pkthdr.csum_iphlen;
1678 thoff = m->m_pkthdr.csum_thlen;
1679 hoff = m->m_pkthdr.csum_lhlen;
1681 KASSERT(iphlen > 0, ("invalid ip hlen"));
1682 KASSERT(thoff > 0, ("invalid tcp hlen"));
1683 KASSERT(hoff > 0, ("invalid ether hlen"));
1685 if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
1686 m = m_pullup(m, hoff + iphlen + thoff);
1697 mxge_encap_tso(mxge_tx_ring_t *tx, struct mxge_buffer_state *info_map,
1698 struct mbuf *m, int busdma_seg_cnt)
1700 mcp_kreq_ether_send_t *req;
1701 bus_dma_segment_t *seg;
1702 uint32_t low, high_swapped;
1703 int len, seglen, cum_len, cum_len_next;
1704 int next_is_first, chop, cnt, rdma_count, small;
1705 uint16_t pseudo_hdr_offset, cksum_offset, mss;
1706 uint8_t flags, flags_next;
1707 struct mxge_buffer_state *info_last;
1708 bus_dmamap_t map = info_map->map;
1710 mss = m->m_pkthdr.tso_segsz;
1713 * Negative cum_len signifies to the send loop that we are
1714 * still in the header portion of the TSO packet.
1716 cum_len = -(m->m_pkthdr.csum_lhlen + m->m_pkthdr.csum_iphlen +
1717 m->m_pkthdr.csum_thlen);
1720 * TSO implies checksum offload on this hardware
1722 cksum_offset = m->m_pkthdr.csum_lhlen + m->m_pkthdr.csum_iphlen;
1723 flags = MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST;
1726 * For TSO, pseudo_hdr_offset holds mss. The firmware figures
1727 * out where to put the checksum by parsing the header.
1729 pseudo_hdr_offset = htobe16(mss);
1737 * "rdma_count" is the number of RDMAs belonging to the current
1738 * packet BEFORE the current send request. For non-TSO packets,
1739 * this is equal to "count".
1741 * For TSO packets, rdma_count needs to be reset to 0 after a
1744 * The rdma_count field of the send request is the number of
1745 * RDMAs of the packet starting at that request. For TSO send
1746 * requests with one ore more cuts in the middle, this is the
1747 * number of RDMAs starting after the last cut in the request.
1748 * All previous segments before the last cut implicitly have 1
1751 * Since the number of RDMAs is not known beforehand, it must be
1752 * filled-in retroactively - after each segmentation cut or at
1753 * the end of the entire packet.
1756 while (busdma_seg_cnt) {
1758 * Break the busdma segment up into pieces
1760 low = MXGE_LOWPART_TO_U32(seg->ds_addr);
1761 high_swapped = htobe32(MXGE_HIGHPART_TO_U32(seg->ds_addr));
1765 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
1767 cum_len_next = cum_len + seglen;
1768 (req - rdma_count)->rdma_count = rdma_count + 1;
1769 if (__predict_true(cum_len >= 0)) {
1771 chop = (cum_len_next > mss);
1772 cum_len_next = cum_len_next % mss;
1773 next_is_first = (cum_len_next == 0);
1774 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
1776 next_is_first * MXGEFW_FLAGS_FIRST;
1777 rdma_count |= -(chop | next_is_first);
1778 rdma_count += chop & !next_is_first;
1779 } else if (cum_len_next >= 0) {
1784 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
1785 flags_next = MXGEFW_FLAGS_TSO_PLD |
1786 MXGEFW_FLAGS_FIRST |
1787 (small * MXGEFW_FLAGS_SMALL);
1790 req->addr_high = high_swapped;
1791 req->addr_low = htobe32(low);
1792 req->pseudo_hdr_offset = pseudo_hdr_offset;
1794 req->rdma_count = 1;
1795 req->length = htobe16(seglen);
1796 req->cksum_offset = cksum_offset;
1798 flags | ((cum_len & 1) * MXGEFW_FLAGS_ALIGN_ODD);
1801 cum_len = cum_len_next;
1806 if (__predict_false(cksum_offset > seglen))
1807 cksum_offset -= seglen;
1810 if (__predict_false(cnt > tx->max_desc))
1816 (req - rdma_count)->rdma_count = rdma_count;
1820 req->flags |= MXGEFW_FLAGS_TSO_LAST;
1821 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP | MXGEFW_FLAGS_FIRST)));
1823 info_last = &tx->info[((cnt - 1) + tx->req) & tx->mask];
1825 info_map->map = info_last->map;
1826 info_last->map = map;
1829 mxge_submit_req(tx, tx->req_list, cnt);
1831 if (tx->send_go != NULL && tx->queue_active == 0) {
1832 /* Tell the NIC to start polling this slice */
1834 tx->queue_active = 1;
1841 bus_dmamap_unload(tx->dmat, tx->info[tx->req & tx->mask].map);
1847 mxge_encap(mxge_tx_ring_t *tx, struct mbuf *m, bus_addr_t zeropad)
1849 mcp_kreq_ether_send_t *req;
1850 bus_dma_segment_t *seg;
1852 int cnt, cum_len, err, i, idx, odd_flag;
1853 uint16_t pseudo_hdr_offset;
1854 uint8_t flags, cksum_offset;
1855 struct mxge_buffer_state *info_map, *info_last;
1857 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1858 err = mxge_pullup_tso(&m);
1859 if (__predict_false(err))
1864 * Map the frame for DMA
1866 idx = tx->req & tx->mask;
1867 info_map = &tx->info[idx];
1868 map = info_map->map;
1870 err = bus_dmamap_load_mbuf_defrag(tx->dmat, map, &m,
1871 tx->seg_list, tx->max_desc - 2, &cnt, BUS_DMA_NOWAIT);
1872 if (__predict_false(err != 0))
1874 bus_dmamap_sync(tx->dmat, map, BUS_DMASYNC_PREWRITE);
1877 * TSO is different enough, we handle it in another routine
1879 if (m->m_pkthdr.csum_flags & CSUM_TSO)
1880 return mxge_encap_tso(tx, info_map, m, cnt);
1884 pseudo_hdr_offset = 0;
1885 flags = MXGEFW_FLAGS_NO_TSO;
1888 * Checksum offloading
1890 if (m->m_pkthdr.csum_flags & CSUM_DELAY_DATA) {
1891 cksum_offset = m->m_pkthdr.csum_lhlen + m->m_pkthdr.csum_iphlen;
1892 pseudo_hdr_offset = cksum_offset + m->m_pkthdr.csum_data;
1893 pseudo_hdr_offset = htobe16(pseudo_hdr_offset);
1894 req->cksum_offset = cksum_offset;
1895 flags |= MXGEFW_FLAGS_CKSUM;
1896 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
1900 if (m->m_pkthdr.len < MXGEFW_SEND_SMALL_SIZE)
1901 flags |= MXGEFW_FLAGS_SMALL;
1904 * Convert segments into a request list
1908 req->flags = MXGEFW_FLAGS_FIRST;
1909 for (i = 0; i < cnt; i++) {
1910 req->addr_low = htobe32(MXGE_LOWPART_TO_U32(seg->ds_addr));
1911 req->addr_high = htobe32(MXGE_HIGHPART_TO_U32(seg->ds_addr));
1912 req->length = htobe16(seg->ds_len);
1913 req->cksum_offset = cksum_offset;
1914 if (cksum_offset > seg->ds_len)
1915 cksum_offset -= seg->ds_len;
1918 req->pseudo_hdr_offset = pseudo_hdr_offset;
1919 req->pad = 0; /* complete solid 16-byte block */
1920 req->rdma_count = 1;
1921 req->flags |= flags | ((cum_len & 1) * odd_flag);
1922 cum_len += seg->ds_len;
1930 * Pad runt to 60 bytes
1934 req->addr_low = htobe32(MXGE_LOWPART_TO_U32(zeropad));
1935 req->addr_high = htobe32(MXGE_HIGHPART_TO_U32(zeropad));
1936 req->length = htobe16(60 - cum_len);
1937 req->cksum_offset = 0;
1938 req->pseudo_hdr_offset = pseudo_hdr_offset;
1939 req->pad = 0; /* complete solid 16-byte block */
1940 req->rdma_count = 1;
1941 req->flags |= flags | ((cum_len & 1) * odd_flag);
1945 tx->req_list[0].rdma_count = cnt;
1947 /* print what the firmware will see */
1948 for (i = 0; i < cnt; i++) {
1949 kprintf("%d: addr: 0x%x 0x%x len:%d pso%d,"
1950 "cso:%d, flags:0x%x, rdma:%d\n",
1951 i, (int)ntohl(tx->req_list[i].addr_high),
1952 (int)ntohl(tx->req_list[i].addr_low),
1953 (int)ntohs(tx->req_list[i].length),
1954 (int)ntohs(tx->req_list[i].pseudo_hdr_offset),
1955 tx->req_list[i].cksum_offset, tx->req_list[i].flags,
1956 tx->req_list[i].rdma_count);
1958 kprintf("--------------\n");
1960 info_last = &tx->info[((cnt - 1) + tx->req) & tx->mask];
1962 info_map->map = info_last->map;
1963 info_last->map = map;
1966 mxge_submit_req(tx, tx->req_list, cnt);
1968 if (tx->send_go != NULL && tx->queue_active == 0) {
1969 /* Tell the NIC to start polling this slice */
1971 tx->queue_active = 1;
1983 mxge_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1985 mxge_softc_t *sc = ifp->if_softc;
1986 mxge_tx_ring_t *tx = ifsq_get_priv(ifsq);
1990 KKASSERT(tx->ifsq == ifsq);
1991 ASSERT_SERIALIZED(&tx->tx_serialize);
1993 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq))
1996 zeropad = sc->zeropad_dma.dmem_busaddr;
1997 while (tx->mask - (tx->req - tx->done) > tx->max_desc) {
2001 m = ifsq_dequeue(ifsq);
2006 error = mxge_encap(tx, m, zeropad);
2010 IFNET_STAT_INC(ifp, oerrors, 1);
2013 /* Ran out of transmit slots */
2014 ifsq_set_oactive(ifsq);
2017 tx->watchdog.wd_timer = 5;
2021 mxge_watchdog(struct ifaltq_subque *ifsq)
2023 struct ifnet *ifp = ifsq_get_ifp(ifsq);
2024 struct mxge_softc *sc = ifp->if_softc;
2025 uint32_t rx_pause = be32toh(sc->ss->fw_stats->dropped_pause);
2026 mxge_tx_ring_t *tx = ifsq_get_priv(ifsq);
2028 ASSERT_IFNET_SERIALIZED_ALL(ifp);
2030 /* Check for pause blocking before resetting */
2031 if (tx->watchdog_rx_pause == rx_pause) {
2032 mxge_warn_stuck(sc, tx, 0);
2033 mxge_watchdog_reset(sc);
2036 if_printf(ifp, "Flow control blocking xmits, "
2037 "check link partner\n");
2039 tx->watchdog_rx_pause = rx_pause;
2043 * Copy an array of mcp_kreq_ether_recv_t's to the mcp. Copy
2044 * at most 32 bytes at a time, so as to avoid involving the software
2045 * pio handler in the nic. We re-write the first segment's low
2046 * DMA address to mark it valid only after we write the entire chunk
2049 static __inline void
2050 mxge_submit_8rx(volatile mcp_kreq_ether_recv_t *dst,
2051 mcp_kreq_ether_recv_t *src)
2055 low = src->addr_low;
2056 src->addr_low = 0xffffffff;
2057 mxge_pio_copy(dst, src, 4 * sizeof (*src));
2059 mxge_pio_copy(dst + 4, src + 4, 4 * sizeof (*src));
2061 src->addr_low = low;
2062 dst->addr_low = low;
2067 mxge_get_buf_small(mxge_rx_ring_t *rx, bus_dmamap_t map, int idx,
2070 bus_dma_segment_t seg;
2072 int cnt, err, mflag;
2074 mflag = MB_DONTWAIT;
2075 if (__predict_false(init))
2078 m = m_gethdr(mflag, MT_DATA);
2081 if (__predict_false(init)) {
2083 * During initialization, there
2084 * is nothing to setup; bail out
2090 m->m_len = m->m_pkthdr.len = MHLEN;
2092 err = bus_dmamap_load_mbuf_segment(rx->dmat, map, m,
2093 &seg, 1, &cnt, BUS_DMA_NOWAIT);
2096 if (__predict_false(init)) {
2098 * During initialization, there
2099 * is nothing to setup; bail out
2106 rx->info[idx].m = m;
2107 rx->shadow[idx].addr_low = htobe32(MXGE_LOWPART_TO_U32(seg.ds_addr));
2108 rx->shadow[idx].addr_high = htobe32(MXGE_HIGHPART_TO_U32(seg.ds_addr));
2112 mxge_submit_8rx(&rx->lanai[idx - 7], &rx->shadow[idx - 7]);
2117 mxge_get_buf_big(mxge_rx_ring_t *rx, bus_dmamap_t map, int idx,
2120 bus_dma_segment_t seg;
2122 int cnt, err, mflag;
2124 mflag = MB_DONTWAIT;
2125 if (__predict_false(init))
2128 if (rx->cl_size == MCLBYTES)
2129 m = m_getcl(mflag, MT_DATA, M_PKTHDR);
2131 m = m_getjcl(mflag, MT_DATA, M_PKTHDR, MJUMPAGESIZE);
2134 if (__predict_false(init)) {
2136 * During initialization, there
2137 * is nothing to setup; bail out
2143 m->m_len = m->m_pkthdr.len = rx->cl_size;
2145 err = bus_dmamap_load_mbuf_segment(rx->dmat, map, m,
2146 &seg, 1, &cnt, BUS_DMA_NOWAIT);
2149 if (__predict_false(init)) {
2151 * During initialization, there
2152 * is nothing to setup; bail out
2159 rx->info[idx].m = m;
2160 rx->shadow[idx].addr_low = htobe32(MXGE_LOWPART_TO_U32(seg.ds_addr));
2161 rx->shadow[idx].addr_high = htobe32(MXGE_HIGHPART_TO_U32(seg.ds_addr));
2165 mxge_submit_8rx(&rx->lanai[idx - 7], &rx->shadow[idx - 7]);
2170 * Myri10GE hardware checksums are not valid if the sender
2171 * padded the frame with non-zero padding. This is because
2172 * the firmware just does a simple 16-bit 1s complement
2173 * checksum across the entire frame, excluding the first 14
2174 * bytes. It is best to simply to check the checksum and
2175 * tell the stack about it only if the checksum is good
2177 static __inline uint16_t
2178 mxge_rx_csum(struct mbuf *m, int csum)
2180 const struct ether_header *eh;
2181 const struct ip *ip;
2184 eh = mtod(m, const struct ether_header *);
2186 /* Only deal with IPv4 TCP & UDP for now */
2187 if (__predict_false(eh->ether_type != htons(ETHERTYPE_IP)))
2190 ip = (const struct ip *)(eh + 1);
2191 if (__predict_false(ip->ip_p != IPPROTO_TCP && ip->ip_p != IPPROTO_UDP))
2195 c = in_pseudo(ip->ip_src.s_addr, ip->ip_dst.s_addr,
2196 htonl(ntohs(csum) + ntohs(ip->ip_len) +
2197 - (ip->ip_hl << 2) + ip->ip_p));
2206 mxge_vlan_tag_remove(struct mbuf *m, uint32_t *csum)
2208 struct ether_vlan_header *evl;
2211 evl = mtod(m, struct ether_vlan_header *);
2214 * Fix checksum by subtracting EVL_ENCAPLEN bytes after
2215 * what the firmware thought was the end of the ethernet
2219 /* Put checksum into host byte order */
2220 *csum = ntohs(*csum);
2222 partial = ntohl(*(uint32_t *)(mtod(m, char *) + ETHER_HDR_LEN));
2224 *csum += ((*csum) < ~partial);
2225 *csum = ((*csum) >> 16) + ((*csum) & 0xFFFF);
2226 *csum = ((*csum) >> 16) + ((*csum) & 0xFFFF);
2229 * Restore checksum to network byte order;
2230 * later consumers expect this
2232 *csum = htons(*csum);
2235 m->m_pkthdr.ether_vlantag = ntohs(evl->evl_tag);
2236 m->m_flags |= M_VLANTAG;
2239 * Remove the 802.1q header by copying the Ethernet
2240 * addresses over it and adjusting the beginning of
2241 * the data in the mbuf. The encapsulated Ethernet
2242 * type field is already in place.
2244 bcopy((char *)evl, (char *)evl + EVL_ENCAPLEN,
2245 ETHER_HDR_LEN - ETHER_TYPE_LEN);
2246 m_adj(m, EVL_ENCAPLEN);
2250 static __inline void
2251 mxge_rx_done_big(struct ifnet *ifp, mxge_rx_ring_t *rx,
2252 uint32_t len, uint32_t csum)
2255 const struct ether_header *eh;
2256 bus_dmamap_t old_map;
2259 idx = rx->cnt & rx->mask;
2262 /* Save a pointer to the received mbuf */
2263 m = rx->info[idx].m;
2265 /* Try to replace the received mbuf */
2266 if (mxge_get_buf_big(rx, rx->extra_map, idx, FALSE)) {
2267 /* Drop the frame -- the old mbuf is re-cycled */
2268 IFNET_STAT_INC(ifp, ierrors, 1);
2272 /* Unmap the received buffer */
2273 old_map = rx->info[idx].map;
2274 bus_dmamap_sync(rx->dmat, old_map, BUS_DMASYNC_POSTREAD);
2275 bus_dmamap_unload(rx->dmat, old_map);
2277 /* Swap the bus_dmamap_t's */
2278 rx->info[idx].map = rx->extra_map;
2279 rx->extra_map = old_map;
2282 * mcp implicitly skips 1st 2 bytes so that packet is properly
2285 m->m_data += MXGEFW_PAD;
2287 m->m_pkthdr.rcvif = ifp;
2288 m->m_len = m->m_pkthdr.len = len;
2290 IFNET_STAT_INC(ifp, ipackets, 1);
2292 eh = mtod(m, const struct ether_header *);
2293 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2294 mxge_vlan_tag_remove(m, &csum);
2296 /* If the checksum is valid, mark it in the mbuf header */
2297 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2298 mxge_rx_csum(m, csum) == 0) {
2299 /* Tell the stack that the checksum is good */
2300 m->m_pkthdr.csum_data = 0xffff;
2301 m->m_pkthdr.csum_flags = CSUM_PSEUDO_HDR |
2304 ifp->if_input(ifp, m, NULL, -1);
2307 static __inline void
2308 mxge_rx_done_small(struct ifnet *ifp, mxge_rx_ring_t *rx,
2309 uint32_t len, uint32_t csum)
2311 const struct ether_header *eh;
2313 bus_dmamap_t old_map;
2316 idx = rx->cnt & rx->mask;
2319 /* Save a pointer to the received mbuf */
2320 m = rx->info[idx].m;
2322 /* Try to replace the received mbuf */
2323 if (mxge_get_buf_small(rx, rx->extra_map, idx, FALSE)) {
2324 /* Drop the frame -- the old mbuf is re-cycled */
2325 IFNET_STAT_INC(ifp, ierrors, 1);
2329 /* Unmap the received buffer */
2330 old_map = rx->info[idx].map;
2331 bus_dmamap_sync(rx->dmat, old_map, BUS_DMASYNC_POSTREAD);
2332 bus_dmamap_unload(rx->dmat, old_map);
2334 /* Swap the bus_dmamap_t's */
2335 rx->info[idx].map = rx->extra_map;
2336 rx->extra_map = old_map;
2339 * mcp implicitly skips 1st 2 bytes so that packet is properly
2342 m->m_data += MXGEFW_PAD;
2344 m->m_pkthdr.rcvif = ifp;
2345 m->m_len = m->m_pkthdr.len = len;
2347 IFNET_STAT_INC(ifp, ipackets, 1);
2349 eh = mtod(m, const struct ether_header *);
2350 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2351 mxge_vlan_tag_remove(m, &csum);
2353 /* If the checksum is valid, mark it in the mbuf header */
2354 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2355 mxge_rx_csum(m, csum) == 0) {
2356 /* Tell the stack that the checksum is good */
2357 m->m_pkthdr.csum_data = 0xffff;
2358 m->m_pkthdr.csum_flags = CSUM_PSEUDO_HDR |
2361 ifp->if_input(ifp, m, NULL, -1);
2364 static __inline void
2365 mxge_clean_rx_done(struct ifnet *ifp, struct mxge_rx_data *rx_data, int cycle)
2367 mxge_rx_done_t *rx_done = &rx_data->rx_done;
2369 while (rx_done->entry[rx_done->idx].length != 0 && cycle != 0) {
2370 uint16_t length, checksum;
2372 length = ntohs(rx_done->entry[rx_done->idx].length);
2373 rx_done->entry[rx_done->idx].length = 0;
2375 checksum = rx_done->entry[rx_done->idx].checksum;
2377 if (length <= MXGE_RX_SMALL_BUFLEN) {
2378 mxge_rx_done_small(ifp, &rx_data->rx_small,
2381 mxge_rx_done_big(ifp, &rx_data->rx_big,
2386 rx_done->idx &= rx_done->mask;
2391 static __inline void
2392 mxge_tx_done(struct ifnet *ifp, mxge_tx_ring_t *tx, uint32_t mcp_idx)
2394 ASSERT_SERIALIZED(&tx->tx_serialize);
2396 while (tx->pkt_done != mcp_idx) {
2400 idx = tx->done & tx->mask;
2403 m = tx->info[idx].m;
2405 * mbuf and DMA map only attached to the first
2410 IFNET_STAT_INC(ifp, opackets, 1);
2411 tx->info[idx].m = NULL;
2412 bus_dmamap_unload(tx->dmat, tx->info[idx].map);
2418 * If we have space, clear OACTIVE to tell the stack that
2419 * its OK to send packets
2421 if (tx->req - tx->done < (tx->mask + 1) / 2) {
2422 ifsq_clr_oactive(tx->ifsq);
2423 if (tx->req == tx->done) {
2424 /* Reset watchdog */
2425 tx->watchdog.wd_timer = 0;
2429 if (!ifsq_is_empty(tx->ifsq))
2430 ifsq_devstart(tx->ifsq);
2432 if (tx->send_stop != NULL && tx->req == tx->done) {
2434 * Let the NIC stop polling this queue, since there
2435 * are no more transmits pending
2438 tx->queue_active = 0;
2444 static struct mxge_media_type mxge_xfp_media_types[] = {
2445 {IFM_10G_CX4, 0x7f, "10GBASE-CX4 (module)"},
2446 {IFM_10G_SR, (1 << 7), "10GBASE-SR"},
2447 {IFM_10G_LR, (1 << 6), "10GBASE-LR"},
2448 {0, (1 << 5), "10GBASE-ER"},
2449 {IFM_10G_LRM, (1 << 4), "10GBASE-LRM"},
2450 {0, (1 << 3), "10GBASE-SW"},
2451 {0, (1 << 2), "10GBASE-LW"},
2452 {0, (1 << 1), "10GBASE-EW"},
2453 {0, (1 << 0), "Reserved"}
2456 static struct mxge_media_type mxge_sfp_media_types[] = {
2457 {IFM_10G_TWINAX, 0, "10GBASE-Twinax"},
2458 {0, (1 << 7), "Reserved"},
2459 {IFM_10G_LRM, (1 << 6), "10GBASE-LRM"},
2460 {IFM_10G_LR, (1 << 5), "10GBASE-LR"},
2461 {IFM_10G_SR, (1 << 4), "10GBASE-SR"},
2462 {IFM_10G_TWINAX,(1 << 0), "10GBASE-Twinax"}
2466 mxge_media_set(mxge_softc_t *sc, int media_type)
2468 ifmedia_add(&sc->media, IFM_ETHER | IFM_FDX | media_type, 0, NULL);
2469 ifmedia_set(&sc->media, IFM_ETHER | IFM_FDX | media_type);
2470 sc->current_media = media_type;
2471 sc->media.ifm_media = sc->media.ifm_cur->ifm_media;
2475 mxge_media_init(mxge_softc_t *sc)
2480 ifmedia_removeall(&sc->media);
2481 mxge_media_set(sc, IFM_AUTO);
2484 * Parse the product code to deterimine the interface type
2485 * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
2486 * after the 3rd dash in the driver's cached copy of the
2487 * EEPROM's product code string.
2489 ptr = sc->product_code_string;
2491 if_printf(sc->ifp, "Missing product code\n");
2495 for (i = 0; i < 3; i++, ptr++) {
2496 ptr = strchr(ptr, '-');
2498 if_printf(sc->ifp, "only %d dashes in PC?!?\n", i);
2502 if (*ptr == 'C' || *(ptr +1) == 'C') {
2504 sc->connector = MXGE_CX4;
2505 mxge_media_set(sc, IFM_10G_CX4);
2506 } else if (*ptr == 'Q') {
2507 /* -Q is Quad Ribbon Fiber */
2508 sc->connector = MXGE_QRF;
2509 if_printf(sc->ifp, "Quad Ribbon Fiber Media\n");
2510 /* DragonFly has no media type for Quad ribbon fiber */
2511 } else if (*ptr == 'R') {
2513 sc->connector = MXGE_XFP;
2514 } else if (*ptr == 'S' || *(ptr +1) == 'S') {
2515 /* -S or -2S is SFP+ */
2516 sc->connector = MXGE_SFP;
2518 if_printf(sc->ifp, "Unknown media type: %c\n", *ptr);
2523 * Determine the media type for a NIC. Some XFPs will identify
2524 * themselves only when their link is up, so this is initiated via a
2525 * link up interrupt. However, this can potentially take up to
2526 * several milliseconds, so it is run via the watchdog routine, rather
2527 * than in the interrupt handler itself.
2530 mxge_media_probe(mxge_softc_t *sc)
2533 const char *cage_type;
2534 struct mxge_media_type *mxge_media_types = NULL;
2535 int i, err, ms, mxge_media_type_entries;
2538 sc->need_media_probe = 0;
2540 if (sc->connector == MXGE_XFP) {
2542 mxge_media_types = mxge_xfp_media_types;
2543 mxge_media_type_entries = NELEM(mxge_xfp_media_types);
2544 byte = MXGE_XFP_COMPLIANCE_BYTE;
2546 } else if (sc->connector == MXGE_SFP) {
2547 /* -S or -2S is SFP+ */
2548 mxge_media_types = mxge_sfp_media_types;
2549 mxge_media_type_entries = NELEM(mxge_sfp_media_types);
2553 /* nothing to do; media type cannot change */
2558 * At this point we know the NIC has an XFP cage, so now we
2559 * try to determine what is in the cage by using the
2560 * firmware's XFP I2C commands to read the XFP 10GbE compilance
2561 * register. We read just one byte, which may take over
2565 cmd.data0 = 0; /* just fetch 1 byte, not all 256 */
2567 err = mxge_send_cmd(sc, MXGEFW_CMD_I2C_READ, &cmd);
2568 if (err == MXGEFW_CMD_ERROR_I2C_FAILURE)
2569 if_printf(sc->ifp, "failed to read XFP\n");
2570 if (err == MXGEFW_CMD_ERROR_I2C_ABSENT)
2571 if_printf(sc->ifp, "Type R/S with no XFP!?!?\n");
2572 if (err != MXGEFW_CMD_OK)
2575 /* Now we wait for the data to be cached */
2577 err = mxge_send_cmd(sc, MXGEFW_CMD_I2C_BYTE, &cmd);
2578 for (ms = 0; err == EBUSY && ms < 50; ms++) {
2581 err = mxge_send_cmd(sc, MXGEFW_CMD_I2C_BYTE, &cmd);
2583 if (err != MXGEFW_CMD_OK) {
2584 if_printf(sc->ifp, "failed to read %s (%d, %dms)\n",
2585 cage_type, err, ms);
2589 if (cmd.data0 == mxge_media_types[0].bitmask) {
2591 if_printf(sc->ifp, "%s:%s\n", cage_type,
2592 mxge_media_types[0].name);
2594 if (sc->current_media != mxge_media_types[0].flag) {
2595 mxge_media_init(sc);
2596 mxge_media_set(sc, mxge_media_types[0].flag);
2600 for (i = 1; i < mxge_media_type_entries; i++) {
2601 if (cmd.data0 & mxge_media_types[i].bitmask) {
2603 if_printf(sc->ifp, "%s:%s\n", cage_type,
2604 mxge_media_types[i].name);
2607 if (sc->current_media != mxge_media_types[i].flag) {
2608 mxge_media_init(sc);
2609 mxge_media_set(sc, mxge_media_types[i].flag);
2615 if_printf(sc->ifp, "%s media 0x%x unknown\n", cage_type,
2621 mxge_intr_status(struct mxge_softc *sc, const mcp_irq_data_t *stats)
2623 if (sc->link_state != stats->link_up) {
2624 sc->link_state = stats->link_up;
2625 if (sc->link_state) {
2626 sc->ifp->if_link_state = LINK_STATE_UP;
2627 if_link_state_change(sc->ifp);
2629 if_printf(sc->ifp, "link up\n");
2631 sc->ifp->if_link_state = LINK_STATE_DOWN;
2632 if_link_state_change(sc->ifp);
2634 if_printf(sc->ifp, "link down\n");
2636 sc->need_media_probe = 1;
2639 if (sc->rdma_tags_available != be32toh(stats->rdma_tags_available)) {
2640 sc->rdma_tags_available = be32toh(stats->rdma_tags_available);
2641 if_printf(sc->ifp, "RDMA timed out! %d tags left\n",
2642 sc->rdma_tags_available);
2645 if (stats->link_down) {
2646 sc->down_cnt += stats->link_down;
2648 sc->ifp->if_link_state = LINK_STATE_DOWN;
2649 if_link_state_change(sc->ifp);
2654 mxge_serialize_skipmain(struct mxge_softc *sc)
2656 lwkt_serialize_array_enter(sc->serializes, sc->nserialize, 1);
2660 mxge_deserialize_skipmain(struct mxge_softc *sc)
2662 lwkt_serialize_array_exit(sc->serializes, sc->nserialize, 1);
2666 mxge_legacy(void *arg)
2668 struct mxge_slice_state *ss = arg;
2669 mxge_softc_t *sc = ss->sc;
2670 mcp_irq_data_t *stats = ss->fw_stats;
2671 mxge_tx_ring_t *tx = &ss->tx;
2672 mxge_rx_done_t *rx_done = &ss->rx_data.rx_done;
2673 uint32_t send_done_count;
2676 ASSERT_SERIALIZED(&sc->main_serialize);
2678 /* Make sure the DMA has finished */
2681 valid = stats->valid;
2683 /* Lower legacy IRQ */
2684 *sc->irq_deassert = 0;
2685 if (!mxge_deassert_wait) {
2686 /* Don't wait for conf. that irq is low */
2690 mxge_serialize_skipmain(sc);
2693 * Loop while waiting for legacy irq deassertion
2694 * XXX do we really want to loop?
2697 /* Check for transmit completes and receives */
2698 send_done_count = be32toh(stats->send_done_count);
2699 while ((send_done_count != tx->pkt_done) ||
2700 (rx_done->entry[rx_done->idx].length != 0)) {
2701 if (send_done_count != tx->pkt_done) {
2702 mxge_tx_done(&sc->arpcom.ac_if, tx,
2703 (int)send_done_count);
2705 mxge_clean_rx_done(&sc->arpcom.ac_if, &ss->rx_data, -1);
2706 send_done_count = be32toh(stats->send_done_count);
2708 if (mxge_deassert_wait)
2710 } while (*((volatile uint8_t *)&stats->valid));
2712 mxge_deserialize_skipmain(sc);
2714 /* Fw link & error stats meaningful only on the first slice */
2715 if (__predict_false(stats->stats_updated))
2716 mxge_intr_status(sc, stats);
2718 /* Check to see if we have rx token to pass back */
2720 *ss->irq_claim = be32toh(3);
2721 *(ss->irq_claim + 1) = be32toh(3);
2727 struct mxge_slice_state *ss = arg;
2728 mxge_softc_t *sc = ss->sc;
2729 mcp_irq_data_t *stats = ss->fw_stats;
2730 mxge_tx_ring_t *tx = &ss->tx;
2731 mxge_rx_done_t *rx_done = &ss->rx_data.rx_done;
2732 uint32_t send_done_count;
2734 #ifndef IFPOLL_ENABLE
2735 const boolean_t polling = FALSE;
2737 boolean_t polling = FALSE;
2740 ASSERT_SERIALIZED(&sc->main_serialize);
2742 /* Make sure the DMA has finished */
2743 if (__predict_false(!stats->valid))
2746 valid = stats->valid;
2749 #ifdef IFPOLL_ENABLE
2750 if (sc->arpcom.ac_if.if_flags & IFF_NPOLLING)
2755 /* Check for receives */
2756 lwkt_serialize_enter(&ss->rx_data.rx_serialize);
2757 if (rx_done->entry[rx_done->idx].length != 0)
2758 mxge_clean_rx_done(&sc->arpcom.ac_if, &ss->rx_data, -1);
2759 lwkt_serialize_exit(&ss->rx_data.rx_serialize);
2763 * Check for transmit completes
2766 * Since pkt_done is only changed by mxge_tx_done(),
2767 * which is called only in interrupt handler, the
2768 * check w/o holding tx serializer is MPSAFE.
2770 send_done_count = be32toh(stats->send_done_count);
2771 if (send_done_count != tx->pkt_done) {
2772 lwkt_serialize_enter(&tx->tx_serialize);
2773 mxge_tx_done(&sc->arpcom.ac_if, tx, (int)send_done_count);
2774 lwkt_serialize_exit(&tx->tx_serialize);
2777 if (__predict_false(stats->stats_updated))
2778 mxge_intr_status(sc, stats);
2780 /* Check to see if we have rx token to pass back */
2781 if (!polling && (valid & 0x1))
2782 *ss->irq_claim = be32toh(3);
2783 *(ss->irq_claim + 1) = be32toh(3);
2787 mxge_msix_rx(void *arg)
2789 struct mxge_slice_state *ss = arg;
2790 mxge_rx_done_t *rx_done = &ss->rx_data.rx_done;
2792 #ifdef IFPOLL_ENABLE
2793 if (ss->sc->arpcom.ac_if.if_flags & IFF_NPOLLING)
2797 ASSERT_SERIALIZED(&ss->rx_data.rx_serialize);
2799 if (rx_done->entry[rx_done->idx].length != 0)
2800 mxge_clean_rx_done(&ss->sc->arpcom.ac_if, &ss->rx_data, -1);
2802 *ss->irq_claim = be32toh(3);
2806 mxge_msix_rxtx(void *arg)
2808 struct mxge_slice_state *ss = arg;
2809 mxge_softc_t *sc = ss->sc;
2810 mcp_irq_data_t *stats = ss->fw_stats;
2811 mxge_tx_ring_t *tx = &ss->tx;
2812 mxge_rx_done_t *rx_done = &ss->rx_data.rx_done;
2813 uint32_t send_done_count;
2815 #ifndef IFPOLL_ENABLE
2816 const boolean_t polling = FALSE;
2818 boolean_t polling = FALSE;
2821 ASSERT_SERIALIZED(&ss->rx_data.rx_serialize);
2823 /* Make sure the DMA has finished */
2824 if (__predict_false(!stats->valid))
2827 valid = stats->valid;
2830 #ifdef IFPOLL_ENABLE
2831 if (sc->arpcom.ac_if.if_flags & IFF_NPOLLING)
2835 /* Check for receives */
2836 if (!polling && rx_done->entry[rx_done->idx].length != 0)
2837 mxge_clean_rx_done(&sc->arpcom.ac_if, &ss->rx_data, -1);
2840 * Check for transmit completes
2843 * Since pkt_done is only changed by mxge_tx_done(),
2844 * which is called only in interrupt handler, the
2845 * check w/o holding tx serializer is MPSAFE.
2847 send_done_count = be32toh(stats->send_done_count);
2848 if (send_done_count != tx->pkt_done) {
2849 lwkt_serialize_enter(&tx->tx_serialize);
2850 mxge_tx_done(&sc->arpcom.ac_if, tx, (int)send_done_count);
2851 lwkt_serialize_exit(&tx->tx_serialize);
2854 /* Check to see if we have rx token to pass back */
2855 if (!polling && (valid & 0x1))
2856 *ss->irq_claim = be32toh(3);
2857 *(ss->irq_claim + 1) = be32toh(3);
2861 mxge_init(void *arg)
2863 struct mxge_softc *sc = arg;
2865 ASSERT_IFNET_SERIALIZED_ALL(sc->ifp);
2866 if ((sc->ifp->if_flags & IFF_RUNNING) == 0)
2871 mxge_free_slice_mbufs(struct mxge_slice_state *ss)
2875 for (i = 0; i <= ss->rx_data.rx_big.mask; i++) {
2876 if (ss->rx_data.rx_big.info[i].m == NULL)
2878 bus_dmamap_unload(ss->rx_data.rx_big.dmat,
2879 ss->rx_data.rx_big.info[i].map);
2880 m_freem(ss->rx_data.rx_big.info[i].m);
2881 ss->rx_data.rx_big.info[i].m = NULL;
2884 for (i = 0; i <= ss->rx_data.rx_small.mask; i++) {
2885 if (ss->rx_data.rx_small.info[i].m == NULL)
2887 bus_dmamap_unload(ss->rx_data.rx_small.dmat,
2888 ss->rx_data.rx_small.info[i].map);
2889 m_freem(ss->rx_data.rx_small.info[i].m);
2890 ss->rx_data.rx_small.info[i].m = NULL;
2893 /* Transmit ring used only on the first slice */
2894 if (ss->tx.info == NULL)
2897 for (i = 0; i <= ss->tx.mask; i++) {
2898 if (ss->tx.info[i].m == NULL)
2900 bus_dmamap_unload(ss->tx.dmat, ss->tx.info[i].map);
2901 m_freem(ss->tx.info[i].m);
2902 ss->tx.info[i].m = NULL;
2907 mxge_free_mbufs(mxge_softc_t *sc)
2911 for (slice = 0; slice < sc->num_slices; slice++)
2912 mxge_free_slice_mbufs(&sc->ss[slice]);
2916 mxge_free_slice_rings(struct mxge_slice_state *ss)
2920 if (ss->rx_data.rx_done.entry != NULL) {
2921 mxge_dma_free(&ss->rx_done_dma);
2922 ss->rx_data.rx_done.entry = NULL;
2925 if (ss->tx.req_list != NULL) {
2926 kfree(ss->tx.req_list, M_DEVBUF);
2927 ss->tx.req_list = NULL;
2930 if (ss->tx.seg_list != NULL) {
2931 kfree(ss->tx.seg_list, M_DEVBUF);
2932 ss->tx.seg_list = NULL;
2935 if (ss->rx_data.rx_small.shadow != NULL) {
2936 kfree(ss->rx_data.rx_small.shadow, M_DEVBUF);
2937 ss->rx_data.rx_small.shadow = NULL;
2940 if (ss->rx_data.rx_big.shadow != NULL) {
2941 kfree(ss->rx_data.rx_big.shadow, M_DEVBUF);
2942 ss->rx_data.rx_big.shadow = NULL;
2945 if (ss->tx.info != NULL) {
2946 if (ss->tx.dmat != NULL) {
2947 for (i = 0; i <= ss->tx.mask; i++) {
2948 bus_dmamap_destroy(ss->tx.dmat,
2949 ss->tx.info[i].map);
2951 bus_dma_tag_destroy(ss->tx.dmat);
2953 kfree(ss->tx.info, M_DEVBUF);
2957 if (ss->rx_data.rx_small.info != NULL) {
2958 if (ss->rx_data.rx_small.dmat != NULL) {
2959 for (i = 0; i <= ss->rx_data.rx_small.mask; i++) {
2960 bus_dmamap_destroy(ss->rx_data.rx_small.dmat,
2961 ss->rx_data.rx_small.info[i].map);
2963 bus_dmamap_destroy(ss->rx_data.rx_small.dmat,
2964 ss->rx_data.rx_small.extra_map);
2965 bus_dma_tag_destroy(ss->rx_data.rx_small.dmat);
2967 kfree(ss->rx_data.rx_small.info, M_DEVBUF);
2968 ss->rx_data.rx_small.info = NULL;
2971 if (ss->rx_data.rx_big.info != NULL) {
2972 if (ss->rx_data.rx_big.dmat != NULL) {
2973 for (i = 0; i <= ss->rx_data.rx_big.mask; i++) {
2974 bus_dmamap_destroy(ss->rx_data.rx_big.dmat,
2975 ss->rx_data.rx_big.info[i].map);
2977 bus_dmamap_destroy(ss->rx_data.rx_big.dmat,
2978 ss->rx_data.rx_big.extra_map);
2979 bus_dma_tag_destroy(ss->rx_data.rx_big.dmat);
2981 kfree(ss->rx_data.rx_big.info, M_DEVBUF);
2982 ss->rx_data.rx_big.info = NULL;
2987 mxge_free_rings(mxge_softc_t *sc)
2994 for (slice = 0; slice < sc->num_slices; slice++)
2995 mxge_free_slice_rings(&sc->ss[slice]);
2999 mxge_alloc_slice_rings(struct mxge_slice_state *ss, int rx_ring_entries,
3000 int tx_ring_entries)
3002 mxge_softc_t *sc = ss->sc;
3007 * Allocate per-slice receive resources
3010 ss->rx_data.rx_small.mask = ss->rx_data.rx_big.mask =
3011 rx_ring_entries - 1;
3012 ss->rx_data.rx_done.mask = (2 * rx_ring_entries) - 1;
3014 /* Allocate the rx shadow rings */
3015 bytes = rx_ring_entries * sizeof(*ss->rx_data.rx_small.shadow);
3016 ss->rx_data.rx_small.shadow = kmalloc(bytes, M_DEVBUF, M_ZERO|M_WAITOK);
3018 bytes = rx_ring_entries * sizeof(*ss->rx_data.rx_big.shadow);
3019 ss->rx_data.rx_big.shadow = kmalloc(bytes, M_DEVBUF, M_ZERO|M_WAITOK);
3021 /* Allocate the rx host info rings */
3022 bytes = rx_ring_entries * sizeof(*ss->rx_data.rx_small.info);
3023 ss->rx_data.rx_small.info = kmalloc(bytes, M_DEVBUF, M_ZERO|M_WAITOK);
3025 bytes = rx_ring_entries * sizeof(*ss->rx_data.rx_big.info);
3026 ss->rx_data.rx_big.info = kmalloc(bytes, M_DEVBUF, M_ZERO|M_WAITOK);
3028 /* Allocate the rx busdma resources */
3029 err = bus_dma_tag_create(sc->parent_dmat, /* parent */
3031 4096, /* boundary */
3032 BUS_SPACE_MAXADDR, /* low */
3033 BUS_SPACE_MAXADDR, /* high */
3034 NULL, NULL, /* filter */
3035 MHLEN, /* maxsize */
3037 MHLEN, /* maxsegsize */
3038 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW,
3040 &ss->rx_data.rx_small.dmat); /* tag */
3042 device_printf(sc->dev, "Err %d allocating rx_small dmat\n",
3047 err = bus_dmamap_create(ss->rx_data.rx_small.dmat, BUS_DMA_WAITOK,
3048 &ss->rx_data.rx_small.extra_map);
3050 device_printf(sc->dev, "Err %d extra rx_small dmamap\n", err);
3051 bus_dma_tag_destroy(ss->rx_data.rx_small.dmat);
3052 ss->rx_data.rx_small.dmat = NULL;
3055 for (i = 0; i <= ss->rx_data.rx_small.mask; i++) {
3056 err = bus_dmamap_create(ss->rx_data.rx_small.dmat,
3057 BUS_DMA_WAITOK, &ss->rx_data.rx_small.info[i].map);
3061 device_printf(sc->dev, "Err %d rx_small dmamap\n", err);
3063 for (j = 0; j < i; ++j) {
3064 bus_dmamap_destroy(ss->rx_data.rx_small.dmat,
3065 ss->rx_data.rx_small.info[j].map);
3067 bus_dmamap_destroy(ss->rx_data.rx_small.dmat,
3068 ss->rx_data.rx_small.extra_map);
3069 bus_dma_tag_destroy(ss->rx_data.rx_small.dmat);
3070 ss->rx_data.rx_small.dmat = NULL;
3075 err = bus_dma_tag_create(sc->parent_dmat, /* parent */
3077 4096, /* boundary */
3078 BUS_SPACE_MAXADDR, /* low */
3079 BUS_SPACE_MAXADDR, /* high */
3080 NULL, NULL, /* filter */
3083 4096, /* maxsegsize*/
3084 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW,
3086 &ss->rx_data.rx_big.dmat); /* tag */
3088 device_printf(sc->dev, "Err %d allocating rx_big dmat\n",
3093 err = bus_dmamap_create(ss->rx_data.rx_big.dmat, BUS_DMA_WAITOK,
3094 &ss->rx_data.rx_big.extra_map);
3096 device_printf(sc->dev, "Err %d extra rx_big dmamap\n", err);
3097 bus_dma_tag_destroy(ss->rx_data.rx_big.dmat);
3098 ss->rx_data.rx_big.dmat = NULL;
3101 for (i = 0; i <= ss->rx_data.rx_big.mask; i++) {
3102 err = bus_dmamap_create(ss->rx_data.rx_big.dmat, BUS_DMA_WAITOK,
3103 &ss->rx_data.rx_big.info[i].map);
3107 device_printf(sc->dev, "Err %d rx_big dmamap\n", err);
3108 for (j = 0; j < i; ++j) {
3109 bus_dmamap_destroy(ss->rx_data.rx_big.dmat,
3110 ss->rx_data.rx_big.info[j].map);
3112 bus_dmamap_destroy(ss->rx_data.rx_big.dmat,
3113 ss->rx_data.rx_big.extra_map);
3114 bus_dma_tag_destroy(ss->rx_data.rx_big.dmat);
3115 ss->rx_data.rx_big.dmat = NULL;
3121 * Now allocate TX resources
3124 ss->tx.mask = tx_ring_entries - 1;
3125 ss->tx.max_desc = MIN(MXGE_MAX_SEND_DESC, tx_ring_entries / 4);
3128 * Allocate the tx request copy block; MUST be at least 8 bytes
3131 bytes = sizeof(*ss->tx.req_list) * (ss->tx.max_desc + 4);
3132 ss->tx.req_list = kmalloc_cachealign(__VM_CACHELINE_ALIGN(bytes),
3133 M_DEVBUF, M_WAITOK);
3135 /* Allocate the tx busdma segment list */
3136 bytes = sizeof(*ss->tx.seg_list) * ss->tx.max_desc;
3137 ss->tx.seg_list = kmalloc(bytes, M_DEVBUF, M_WAITOK);
3139 /* Allocate the tx host info ring */
3140 bytes = tx_ring_entries * sizeof(*ss->tx.info);
3141 ss->tx.info = kmalloc(bytes, M_DEVBUF, M_ZERO|M_WAITOK);
3143 /* Allocate the tx busdma resources */
3144 err = bus_dma_tag_create(sc->parent_dmat, /* parent */
3146 sc->tx_boundary, /* boundary */
3147 BUS_SPACE_MAXADDR, /* low */
3148 BUS_SPACE_MAXADDR, /* high */
3149 NULL, NULL, /* filter */
3151 sizeof(struct ether_vlan_header),
3153 ss->tx.max_desc - 2, /* num segs */
3154 sc->tx_boundary, /* maxsegsz */
3155 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
3156 BUS_DMA_ONEBPAGE, /* flags */
3157 &ss->tx.dmat); /* tag */
3159 device_printf(sc->dev, "Err %d allocating tx dmat\n", err);
3164 * Now use these tags to setup DMA maps for each slot in the ring
3166 for (i = 0; i <= ss->tx.mask; i++) {
3167 err = bus_dmamap_create(ss->tx.dmat,
3168 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &ss->tx.info[i].map);
3172 device_printf(sc->dev, "Err %d tx dmamap\n", err);
3173 for (j = 0; j < i; ++j) {
3174 bus_dmamap_destroy(ss->tx.dmat,
3175 ss->tx.info[j].map);
3177 bus_dma_tag_destroy(ss->tx.dmat);
3186 mxge_alloc_rings(mxge_softc_t *sc)
3190 int tx_ring_entries, rx_ring_entries;
3193 /* Get ring sizes */
3194 err = mxge_send_cmd(sc, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd);
3196 device_printf(sc->dev, "Cannot determine tx ring sizes\n");
3199 tx_ring_size = cmd.data0;
3201 tx_ring_entries = tx_ring_size / sizeof(mcp_kreq_ether_send_t);
3202 rx_ring_entries = sc->rx_intr_slots / 2;
3205 device_printf(sc->dev, "tx desc %d, rx desc %d\n",
3206 tx_ring_entries, rx_ring_entries);
3209 ifq_set_maxlen(&sc->ifp->if_snd, tx_ring_entries - 1);
3210 ifq_set_ready(&sc->ifp->if_snd);
3211 ifq_set_subq_cnt(&sc->ifp->if_snd, sc->num_tx_rings);
3213 if (sc->num_tx_rings > 1) {
3214 sc->ifp->if_mapsubq = ifq_mapsubq_mask;
3215 ifq_set_subq_mask(&sc->ifp->if_snd, sc->num_tx_rings - 1);
3218 for (slice = 0; slice < sc->num_slices; slice++) {
3219 err = mxge_alloc_slice_rings(&sc->ss[slice],
3220 rx_ring_entries, tx_ring_entries);
3222 device_printf(sc->dev,
3223 "alloc %d slice rings failed\n", slice);
3231 mxge_choose_params(int mtu, int *cl_size)
3233 int bufsize = mtu + ETHER_HDR_LEN + EVL_ENCAPLEN + MXGEFW_PAD;
3235 if (bufsize < MCLBYTES) {
3236 *cl_size = MCLBYTES;
3238 KASSERT(bufsize < MJUMPAGESIZE, ("invalid MTU %d", mtu));
3239 *cl_size = MJUMPAGESIZE;
3244 mxge_slice_open(struct mxge_slice_state *ss, int cl_size)
3249 slice = ss - ss->sc->ss;
3252 * Get the lanai pointers to the send and receive rings
3256 if (ss->sc->num_tx_rings == 1) {
3259 err = mxge_send_cmd(ss->sc, MXGEFW_CMD_GET_SEND_OFFSET,
3261 ss->tx.lanai = (volatile mcp_kreq_ether_send_t *)
3262 (ss->sc->sram + cmd.data0);
3263 /* Leave send_go and send_stop as NULL */
3267 err = mxge_send_cmd(ss->sc, MXGEFW_CMD_GET_SEND_OFFSET, &cmd);
3268 ss->tx.lanai = (volatile mcp_kreq_ether_send_t *)
3269 (ss->sc->sram + cmd.data0);
3270 ss->tx.send_go = (volatile uint32_t *)
3271 (ss->sc->sram + MXGEFW_ETH_SEND_GO + 64 * slice);
3272 ss->tx.send_stop = (volatile uint32_t *)
3273 (ss->sc->sram + MXGEFW_ETH_SEND_STOP + 64 * slice);
3277 err |= mxge_send_cmd(ss->sc, MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd);
3278 ss->rx_data.rx_small.lanai =
3279 (volatile mcp_kreq_ether_recv_t *)(ss->sc->sram + cmd.data0);
3282 err |= mxge_send_cmd(ss->sc, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd);
3283 ss->rx_data.rx_big.lanai =
3284 (volatile mcp_kreq_ether_recv_t *)(ss->sc->sram + cmd.data0);
3287 if_printf(ss->sc->ifp,
3288 "failed to get ring sizes or locations\n");
3293 * Stock small receive ring
3295 for (i = 0; i <= ss->rx_data.rx_small.mask; i++) {
3296 err = mxge_get_buf_small(&ss->rx_data.rx_small,
3297 ss->rx_data.rx_small.info[i].map, i, TRUE);
3299 if_printf(ss->sc->ifp, "alloced %d/%d smalls\n", i,
3300 ss->rx_data.rx_small.mask + 1);
3306 * Stock big receive ring
3308 for (i = 0; i <= ss->rx_data.rx_big.mask; i++) {
3309 ss->rx_data.rx_big.shadow[i].addr_low = 0xffffffff;
3310 ss->rx_data.rx_big.shadow[i].addr_high = 0xffffffff;
3313 ss->rx_data.rx_big.cl_size = cl_size;
3315 for (i = 0; i <= ss->rx_data.rx_big.mask; i++) {
3316 err = mxge_get_buf_big(&ss->rx_data.rx_big,
3317 ss->rx_data.rx_big.info[i].map, i, TRUE);
3319 if_printf(ss->sc->ifp, "alloced %d/%d bigs\n", i,
3320 ss->rx_data.rx_big.mask + 1);
3328 mxge_open(mxge_softc_t *sc)
3330 struct ifnet *ifp = sc->ifp;
3332 int err, slice, cl_size, i;
3334 volatile uint8_t *itable;
3335 struct mxge_slice_state *ss;
3337 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3339 /* Copy the MAC address in case it was overridden */
3340 bcopy(IF_LLADDR(ifp), sc->mac_addr, ETHER_ADDR_LEN);
3342 err = mxge_reset(sc, 1);
3344 if_printf(ifp, "failed to reset\n");
3348 if (sc->num_slices > 1) {
3349 /* Setup the indirection table */
3350 cmd.data0 = sc->num_slices;
3351 err = mxge_send_cmd(sc, MXGEFW_CMD_SET_RSS_TABLE_SIZE, &cmd);
3353 err |= mxge_send_cmd(sc, MXGEFW_CMD_GET_RSS_TABLE_OFFSET, &cmd);
3355 if_printf(ifp, "failed to setup rss tables\n");
3359 /* Just enable an identity mapping */
3360 itable = sc->sram + cmd.data0;
3361 for (i = 0; i < sc->num_slices; i++)
3362 itable[i] = (uint8_t)i;
3365 volatile uint8_t *hwkey;
3366 uint8_t swkey[MXGE_HWRSS_KEYLEN];
3368 err = mxge_send_cmd(sc, MXGEFW_CMD_GET_RSS_KEY_OFFSET,
3371 if_printf(ifp, "failed to get rsskey\n");
3374 hwkey = sc->sram + cmd.data0;
3376 toeplitz_get_key(swkey, MXGE_HWRSS_KEYLEN);
3377 for (i = 0; i < MXGE_HWRSS_KEYLEN; ++i)
3378 hwkey[i] = swkey[i];
3381 err = mxge_send_cmd(sc, MXGEFW_CMD_RSS_KEY_UPDATED,
3384 if_printf(ifp, "failed to update rsskey\n");
3388 if_printf(ifp, "RSS key updated\n");
3394 if_printf(ifp, "input hash: RSS\n");
3395 cmd.data1 = MXGEFW_RSS_HASH_TYPE_IPV4 |
3396 MXGEFW_RSS_HASH_TYPE_TCP_IPV4;
3399 if_printf(ifp, "input hash: SRC_DST_PORT\n");
3400 cmd.data1 = MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT;
3402 err = mxge_send_cmd(sc, MXGEFW_CMD_SET_RSS_ENABLE, &cmd);
3404 if_printf(ifp, "failed to enable slices\n");
3409 cmd.data0 = MXGEFW_TSO_MODE_NDIS;
3410 err = mxge_send_cmd(sc, MXGEFW_CMD_SET_TSO_MODE, &cmd);
3413 * Can't change TSO mode to NDIS, never allow TSO then
3415 if_printf(ifp, "failed to set TSO mode\n");
3416 ifp->if_capenable &= ~IFCAP_TSO;
3417 ifp->if_capabilities &= ~IFCAP_TSO;
3418 ifp->if_hwassist &= ~CSUM_TSO;
3421 mxge_choose_params(ifp->if_mtu, &cl_size);
3424 err = mxge_send_cmd(sc, MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS, &cmd);
3426 * Error is only meaningful if we're trying to set
3427 * MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS > 1
3431 * Give the firmware the mtu and the big and small buffer
3432 * sizes. The firmware wants the big buf size to be a power
3433 * of two. Luckily, DragonFly's clusters are powers of two
3435 cmd.data0 = ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN;
3436 err = mxge_send_cmd(sc, MXGEFW_CMD_SET_MTU, &cmd);
3438 cmd.data0 = MXGE_RX_SMALL_BUFLEN;
3439 err |= mxge_send_cmd(sc, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd);
3441 cmd.data0 = cl_size;
3442 err |= mxge_send_cmd(sc, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd);
3445 if_printf(ifp, "failed to setup params\n");
3449 /* Now give him the pointer to the stats block */
3450 for (slice = 0; slice < sc->num_slices; slice++) {
3451 ss = &sc->ss[slice];
3452 cmd.data0 = MXGE_LOWPART_TO_U32(ss->fw_stats_dma.dmem_busaddr);
3453 cmd.data1 = MXGE_HIGHPART_TO_U32(ss->fw_stats_dma.dmem_busaddr);
3454 cmd.data2 = sizeof(struct mcp_irq_data);
3455 cmd.data2 |= (slice << 16);
3456 err |= mxge_send_cmd(sc, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd);
3460 bus = sc->ss->fw_stats_dma.dmem_busaddr;
3461 bus += offsetof(struct mcp_irq_data, send_done_count);
3462 cmd.data0 = MXGE_LOWPART_TO_U32(bus);
3463 cmd.data1 = MXGE_HIGHPART_TO_U32(bus);
3464 err = mxge_send_cmd(sc, MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
3467 /* Firmware cannot support multicast without STATS_DMA_V2 */
3468 sc->fw_multicast_support = 0;
3470 sc->fw_multicast_support = 1;
3474 if_printf(ifp, "failed to setup params\n");
3478 for (slice = 0; slice < sc->num_slices; slice++) {
3479 err = mxge_slice_open(&sc->ss[slice], cl_size);
3481 if_printf(ifp, "couldn't open slice %d\n", slice);
3486 /* Finally, start the firmware running */
3487 err = mxge_send_cmd(sc, MXGEFW_CMD_ETHERNET_UP, &cmd);
3489 if_printf(ifp, "Couldn't bring up link\n");
3493 ifp->if_flags |= IFF_RUNNING;
3494 for (i = 0; i < sc->num_tx_rings; ++i) {
3495 mxge_tx_ring_t *tx = &sc->ss[i].tx;
3497 ifsq_clr_oactive(tx->ifsq);
3498 ifsq_watchdog_start(&tx->watchdog);
3504 mxge_free_mbufs(sc);
3509 mxge_close(mxge_softc_t *sc, int down)
3511 struct ifnet *ifp = sc->ifp;
3513 int err, old_down_cnt, i;
3515 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3518 old_down_cnt = sc->down_cnt;
3521 err = mxge_send_cmd(sc, MXGEFW_CMD_ETHERNET_DOWN, &cmd);
3523 if_printf(ifp, "Couldn't bring down link\n");
3525 if (old_down_cnt == sc->down_cnt) {
3530 ifnet_deserialize_all(ifp);
3531 DELAY(10 * sc->intr_coal_delay);
3532 ifnet_serialize_all(ifp);
3536 if (old_down_cnt == sc->down_cnt)
3537 if_printf(ifp, "never got down irq\n");
3539 mxge_free_mbufs(sc);
3541 ifp->if_flags &= ~IFF_RUNNING;
3542 for (i = 0; i < sc->num_tx_rings; ++i) {
3543 mxge_tx_ring_t *tx = &sc->ss[i].tx;
3545 ifsq_clr_oactive(tx->ifsq);
3546 ifsq_watchdog_stop(&tx->watchdog);
3551 mxge_setup_cfg_space(mxge_softc_t *sc)
3553 device_t dev = sc->dev;
3555 uint16_t lnk, pectl;
3557 /* Find the PCIe link width and set max read request to 4KB */
3558 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) {
3559 lnk = pci_read_config(dev, reg + 0x12, 2);
3560 sc->link_width = (lnk >> 4) & 0x3f;
3562 if (sc->pectl == 0) {
3563 pectl = pci_read_config(dev, reg + 0x8, 2);
3564 pectl = (pectl & ~0x7000) | (5 << 12);
3565 pci_write_config(dev, reg + 0x8, pectl, 2);
3568 /* Restore saved pectl after watchdog reset */
3569 pci_write_config(dev, reg + 0x8, sc->pectl, 2);
3573 /* Enable DMA and memory space access */
3574 pci_enable_busmaster(dev);
3578 mxge_read_reboot(mxge_softc_t *sc)
3580 device_t dev = sc->dev;
3583 /* Find the vendor specific offset */
3584 if (pci_find_extcap(dev, PCIY_VENDOR, &vs) != 0) {
3585 if_printf(sc->ifp, "could not find vendor specific offset\n");
3586 return (uint32_t)-1;
3588 /* Enable read32 mode */
3589 pci_write_config(dev, vs + 0x10, 0x3, 1);
3590 /* Tell NIC which register to read */
3591 pci_write_config(dev, vs + 0x18, 0xfffffff0, 4);
3592 return pci_read_config(dev, vs + 0x14, 4);
3596 mxge_watchdog_reset(mxge_softc_t *sc)
3598 struct pci_devinfo *dinfo;
3605 if_printf(sc->ifp, "Watchdog reset!\n");
3608 * Check to see if the NIC rebooted. If it did, then all of
3609 * PCI config space has been reset, and things like the
3610 * busmaster bit will be zero. If this is the case, then we
3611 * must restore PCI config space before the NIC can be used
3614 cmd = pci_read_config(sc->dev, PCIR_COMMAND, 2);
3615 if (cmd == 0xffff) {
3617 * Maybe the watchdog caught the NIC rebooting; wait
3618 * up to 100ms for it to finish. If it does not come
3619 * back, then give up
3622 cmd = pci_read_config(sc->dev, PCIR_COMMAND, 2);
3624 if_printf(sc->ifp, "NIC disappeared!\n");
3626 if ((cmd & PCIM_CMD_BUSMASTEREN) == 0) {
3627 /* Print the reboot status */
3628 reboot = mxge_read_reboot(sc);
3629 if_printf(sc->ifp, "NIC rebooted, status = 0x%x\n", reboot);
3631 running = sc->ifp->if_flags & IFF_RUNNING;
3634 * Quiesce NIC so that TX routines will not try to
3635 * xmit after restoration of BAR
3638 /* Mark the link as down */
3639 if (sc->link_state) {
3640 sc->ifp->if_link_state = LINK_STATE_DOWN;
3641 if_link_state_change(sc->ifp);
3645 /* Restore PCI configuration space */
3646 dinfo = device_get_ivars(sc->dev);
3647 pci_cfg_restore(sc->dev, dinfo);
3649 /* And redo any changes we made to our config space */
3650 mxge_setup_cfg_space(sc);
3653 err = mxge_load_firmware(sc, 0);
3655 if_printf(sc->ifp, "Unable to re-load f/w\n");
3656 if (running && !err) {
3659 err = mxge_open(sc);
3661 for (i = 0; i < sc->num_tx_rings; ++i)
3662 ifsq_devstart_sched(sc->ss[i].tx.ifsq);
3664 sc->watchdog_resets++;
3666 if_printf(sc->ifp, "NIC did not reboot, not resetting\n");
3670 if_printf(sc->ifp, "watchdog reset failed\n");
3674 callout_reset(&sc->co_hdl, mxge_ticks, mxge_tick, sc);
3679 mxge_warn_stuck(mxge_softc_t *sc, mxge_tx_ring_t *tx, int slice)
3681 if_printf(sc->ifp, "slice %d struck? ring state:\n", slice);
3682 if_printf(sc->ifp, "tx.req=%d tx.done=%d, tx.queue_active=%d\n",
3683 tx->req, tx->done, tx->queue_active);
3684 if_printf(sc->ifp, "tx.activate=%d tx.deactivate=%d\n",
3685 tx->activate, tx->deactivate);
3686 if_printf(sc->ifp, "pkt_done=%d fw=%d\n",
3687 tx->pkt_done, be32toh(sc->ss->fw_stats->send_done_count));
3691 mxge_update_stats(mxge_softc_t *sc)
3693 u_long ipackets, opackets, pkts;
3695 IFNET_STAT_GET(sc->ifp, ipackets, ipackets);
3696 IFNET_STAT_GET(sc->ifp, opackets, opackets);
3698 pkts = ipackets - sc->ipackets;
3699 pkts += opackets - sc->opackets;
3701 sc->ipackets = ipackets;
3702 sc->opackets = opackets;
3708 mxge_tick(void *arg)
3710 mxge_softc_t *sc = arg;
3715 lwkt_serialize_enter(&sc->main_serialize);
3718 if (sc->ifp->if_flags & IFF_RUNNING) {
3719 /* Aggregate stats from different slices */
3720 pkts = mxge_update_stats(sc);
3721 if (sc->need_media_probe)
3722 mxge_media_probe(sc);
3727 /* Ensure NIC did not suffer h/w fault while idle */
3728 cmd = pci_read_config(sc->dev, PCIR_COMMAND, 2);
3729 if ((cmd & PCIM_CMD_BUSMASTEREN) == 0) {
3731 mxge_serialize_skipmain(sc);
3732 mxge_watchdog_reset(sc);
3733 mxge_deserialize_skipmain(sc);
3737 /* Look less often if NIC is idle */
3742 callout_reset(&sc->co_hdl, ticks, mxge_tick, sc);
3744 lwkt_serialize_exit(&sc->main_serialize);
3748 mxge_media_change(struct ifnet *ifp)
3754 mxge_change_mtu(mxge_softc_t *sc, int mtu)
3756 struct ifnet *ifp = sc->ifp;
3757 int real_mtu, old_mtu;
3760 real_mtu = mtu + ETHER_HDR_LEN + EVL_ENCAPLEN;
3761 if (mtu > sc->max_mtu || real_mtu < 60)
3764 old_mtu = ifp->if_mtu;
3766 if (ifp->if_flags & IFF_RUNNING) {
3768 err = mxge_open(sc);
3770 ifp->if_mtu = old_mtu;
3779 mxge_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
3781 mxge_softc_t *sc = ifp->if_softc;
3786 ifmr->ifm_status = IFM_AVALID;
3787 ifmr->ifm_active = IFM_ETHER | IFM_FDX;
3788 ifmr->ifm_status |= sc->link_state ? IFM_ACTIVE : 0;
3789 ifmr->ifm_active |= sc->current_media;
3793 mxge_ioctl(struct ifnet *ifp, u_long command, caddr_t data,
3794 struct ucred *cr __unused)
3796 mxge_softc_t *sc = ifp->if_softc;
3797 struct ifreq *ifr = (struct ifreq *)data;
3800 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3805 err = mxge_change_mtu(sc, ifr->ifr_mtu);
3812 if (ifp->if_flags & IFF_UP) {
3813 if (!(ifp->if_flags & IFF_RUNNING)) {
3814 err = mxge_open(sc);
3817 * Take care of PROMISC and ALLMULTI
3820 mxge_change_promisc(sc,
3821 ifp->if_flags & IFF_PROMISC);
3822 mxge_set_multicast_list(sc);
3825 if (ifp->if_flags & IFF_RUNNING)
3832 mxge_set_multicast_list(sc);
3836 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3837 if (mask & IFCAP_TXCSUM) {
3838 ifp->if_capenable ^= IFCAP_TXCSUM;
3839 if (ifp->if_capenable & IFCAP_TXCSUM)
3840 ifp->if_hwassist |= CSUM_TCP | CSUM_UDP;
3842 ifp->if_hwassist &= ~(CSUM_TCP | CSUM_UDP);
3844 if (mask & IFCAP_TSO) {
3845 ifp->if_capenable ^= IFCAP_TSO;
3846 if (ifp->if_capenable & IFCAP_TSO)
3847 ifp->if_hwassist |= CSUM_TSO;
3849 ifp->if_hwassist &= ~CSUM_TSO;
3851 if (mask & IFCAP_RXCSUM)
3852 ifp->if_capenable ^= IFCAP_RXCSUM;
3853 if (mask & IFCAP_VLAN_HWTAGGING)
3854 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3858 mxge_media_probe(sc);
3859 err = ifmedia_ioctl(ifp, (struct ifreq *)data,
3860 &sc->media, command);
3864 err = ether_ioctl(ifp, command, data);
3871 mxge_fetch_tunables(mxge_softc_t *sc)
3873 sc->intr_coal_delay = mxge_intr_coal_delay;
3874 if (sc->intr_coal_delay < 0 || sc->intr_coal_delay > (10 * 1000))
3875 sc->intr_coal_delay = MXGE_INTR_COAL_DELAY;
3878 if (mxge_ticks == 0)
3879 mxge_ticks = hz / 2;
3881 sc->pause = mxge_flow_control;
3882 sc->use_rss = mxge_use_rss;
3884 sc->throttle = mxge_throttle;
3885 if (sc->throttle && sc->throttle > MXGE_MAX_THROTTLE)
3886 sc->throttle = MXGE_MAX_THROTTLE;
3887 if (sc->throttle && sc->throttle < MXGE_MIN_THROTTLE)
3888 sc->throttle = MXGE_MIN_THROTTLE;
3892 mxge_free_slices(mxge_softc_t *sc)
3894 struct mxge_slice_state *ss;
3900 for (i = 0; i < sc->num_slices; i++) {
3902 if (ss->fw_stats != NULL) {
3903 mxge_dma_free(&ss->fw_stats_dma);
3904 ss->fw_stats = NULL;
3906 if (ss->rx_data.rx_done.entry != NULL) {
3907 mxge_dma_free(&ss->rx_done_dma);
3908 ss->rx_data.rx_done.entry = NULL;
3911 kfree(sc->ss, M_DEVBUF);
3916 mxge_alloc_slices(mxge_softc_t *sc)
3919 struct mxge_slice_state *ss;
3921 int err, i, rx_ring_size;
3923 err = mxge_send_cmd(sc, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd);
3925 device_printf(sc->dev, "Cannot determine rx ring size\n");
3928 rx_ring_size = cmd.data0;
3929 sc->rx_intr_slots = 2 * (rx_ring_size / sizeof (mcp_dma_addr_t));
3931 bytes = sizeof(*sc->ss) * sc->num_slices;
3932 sc->ss = kmalloc_cachealign(bytes, M_DEVBUF, M_WAITOK | M_ZERO);
3934 for (i = 0; i < sc->num_slices; i++) {
3939 lwkt_serialize_init(&ss->rx_data.rx_serialize);
3940 lwkt_serialize_init(&ss->tx.tx_serialize);
3944 * Allocate per-slice rx interrupt queue
3945 * XXX assume 4bytes mcp_slot
3947 bytes = sc->rx_intr_slots * sizeof(mcp_slot_t);
3948 err = mxge_dma_alloc(sc, &ss->rx_done_dma, bytes, 4096);
3950 device_printf(sc->dev,
3951 "alloc %d slice rx_done failed\n", i);
3954 ss->rx_data.rx_done.entry = ss->rx_done_dma.dmem_addr;
3957 * Allocate the per-slice firmware stats
3959 bytes = sizeof(*ss->fw_stats);
3960 err = mxge_dma_alloc(sc, &ss->fw_stats_dma,
3961 sizeof(*ss->fw_stats), 64);
3963 device_printf(sc->dev,
3964 "alloc %d fw_stats failed\n", i);
3967 ss->fw_stats = ss->fw_stats_dma.dmem_addr;
3973 mxge_slice_probe(mxge_softc_t *sc)
3975 int status, max_intr_slots, max_slices, num_slices;
3976 int msix_cnt, msix_enable, i, multi_tx;
3981 sc->num_tx_rings = 1;
3983 num_slices = device_getenv_int(sc->dev, "num_slices", mxge_num_slices);
3984 if (num_slices == 1)
3990 msix_enable = device_getenv_int(sc->dev, "msix.enable",
3995 msix_cnt = pci_msix_count(sc->dev);
4000 * Round down MSI-X vector count to the nearest power of 2
4003 while ((1 << (i + 1)) <= msix_cnt)
4008 * Now load the slice aware firmware see what it supports
4010 old_fw = sc->fw_name;
4011 if (old_fw == mxge_fw_aligned)
4012 sc->fw_name = mxge_fw_rss_aligned;
4014 sc->fw_name = mxge_fw_rss_unaligned;
4015 status = mxge_load_firmware(sc, 0);
4017 device_printf(sc->dev, "Falling back to a single slice\n");
4022 * Try to send a reset command to the card to see if it is alive
4024 memset(&cmd, 0, sizeof(cmd));
4025 status = mxge_send_cmd(sc, MXGEFW_CMD_RESET, &cmd);
4027 device_printf(sc->dev, "failed reset\n");
4032 * Get rx ring size to calculate rx interrupt queue size
4034 status = mxge_send_cmd(sc, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd);
4036 device_printf(sc->dev, "Cannot determine rx ring size\n");
4039 max_intr_slots = 2 * (cmd.data0 / sizeof(mcp_dma_addr_t));
4042 * Tell it the size of the rx interrupt queue
4044 cmd.data0 = max_intr_slots * sizeof(struct mcp_slot);
4045 status = mxge_send_cmd(sc, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd);
4047 device_printf(sc->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
4052 * Ask the maximum number of slices it supports
4054 status = mxge_send_cmd(sc, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd);
4056 device_printf(sc->dev,
4057 "failed MXGEFW_CMD_GET_MAX_RSS_QUEUES\n");
4060 max_slices = cmd.data0;
4063 * Round down max slices count to the nearest power of 2
4066 while ((1 << (i + 1)) <= max_slices)
4068 max_slices = 1 << i;
4070 if (max_slices > msix_cnt)
4071 max_slices = msix_cnt;
4073 sc->num_slices = num_slices;
4074 sc->num_slices = if_ring_count2(sc->num_slices, max_slices);
4076 multi_tx = device_getenv_int(sc->dev, "multi_tx", mxge_multi_tx);
4078 sc->num_tx_rings = sc->num_slices;
4081 device_printf(sc->dev, "using %d slices, max %d\n",
4082 sc->num_slices, max_slices);
4085 if (sc->num_slices == 1)
4090 sc->fw_name = old_fw;
4091 mxge_load_firmware(sc, 0);
4095 mxge_setup_serialize(struct mxge_softc *sc)
4099 /* Main + rx + tx */
4100 sc->nserialize = (2 * sc->num_slices) + 1;
4102 kmalloc(sc->nserialize * sizeof(struct lwkt_serialize *),
4103 M_DEVBUF, M_WAITOK | M_ZERO);
4108 * NOTE: Order is critical
4111 KKASSERT(i < sc->nserialize);
4112 sc->serializes[i++] = &sc->main_serialize;
4114 for (slice = 0; slice < sc->num_slices; ++slice) {
4115 KKASSERT(i < sc->nserialize);
4116 sc->serializes[i++] = &sc->ss[slice].rx_data.rx_serialize;
4119 for (slice = 0; slice < sc->num_slices; ++slice) {
4120 KKASSERT(i < sc->nserialize);
4121 sc->serializes[i++] = &sc->ss[slice].tx.tx_serialize;
4124 KKASSERT(i == sc->nserialize);
4128 mxge_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
4130 struct mxge_softc *sc = ifp->if_softc;
4132 ifnet_serialize_array_enter(sc->serializes, sc->nserialize, slz);
4136 mxge_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
4138 struct mxge_softc *sc = ifp->if_softc;
4140 ifnet_serialize_array_exit(sc->serializes, sc->nserialize, slz);
4144 mxge_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
4146 struct mxge_softc *sc = ifp->if_softc;
4148 return ifnet_serialize_array_try(sc->serializes, sc->nserialize, slz);
4154 mxge_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
4155 boolean_t serialized)
4157 struct mxge_softc *sc = ifp->if_softc;
4159 ifnet_serialize_array_assert(sc->serializes, sc->nserialize,
4163 #endif /* INVARIANTS */
4165 #ifdef IFPOLL_ENABLE
4168 mxge_npoll_rx(struct ifnet *ifp, void *xss, int cycle)
4170 struct mxge_slice_state *ss = xss;
4171 mxge_rx_done_t *rx_done = &ss->rx_data.rx_done;
4173 ASSERT_SERIALIZED(&ss->rx_data.rx_serialize);
4175 if (rx_done->entry[rx_done->idx].length != 0) {
4176 mxge_clean_rx_done(&ss->sc->arpcom.ac_if, &ss->rx_data, cycle);
4180 * This register writting obviously has cost,
4181 * however, if we don't hand back the rx token,
4182 * the upcoming packets may suffer rediculously
4183 * large delay, as observed on 8AL-C using ping(8).
4185 *ss->irq_claim = be32toh(3);
4190 mxge_npoll(struct ifnet *ifp, struct ifpoll_info *info)
4192 struct mxge_softc *sc = ifp->if_softc;
4199 * Only poll rx; polling tx and status don't seem to work
4201 for (i = 0; i < sc->num_slices; ++i) {
4202 struct mxge_slice_state *ss = &sc->ss[i];
4203 int idx = ss->intr_cpuid;
4205 KKASSERT(idx < ncpus2);
4206 info->ifpi_rx[idx].poll_func = mxge_npoll_rx;
4207 info->ifpi_rx[idx].arg = ss;
4208 info->ifpi_rx[idx].serializer = &ss->rx_data.rx_serialize;
4212 #endif /* IFPOLL_ENABLE */
4215 mxge_attach(device_t dev)
4217 mxge_softc_t *sc = device_get_softc(dev);
4218 struct ifnet *ifp = &sc->arpcom.ac_if;
4222 * Avoid rewriting half the lines in this file to use
4223 * &sc->arpcom.ac_if instead
4227 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
4228 ifmedia_init(&sc->media, 0, mxge_media_change, mxge_media_status);
4230 lwkt_serialize_init(&sc->main_serialize);
4232 mxge_fetch_tunables(sc);
4234 err = bus_dma_tag_create(NULL, /* parent */
4237 BUS_SPACE_MAXADDR, /* low */
4238 BUS_SPACE_MAXADDR, /* high */
4239 NULL, NULL, /* filter */
4240 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */
4242 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
4244 &sc->parent_dmat); /* tag */
4246 device_printf(dev, "Err %d allocating parent dmat\n", err);
4250 callout_init_mp(&sc->co_hdl);
4252 mxge_setup_cfg_space(sc);
4255 * Map the board into the kernel
4258 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
4260 if (sc->mem_res == NULL) {
4261 device_printf(dev, "could not map memory\n");
4266 sc->sram = rman_get_virtual(sc->mem_res);
4267 sc->sram_size = 2*1024*1024 - (2*(48*1024)+(32*1024)) - 0x100;
4268 if (sc->sram_size > rman_get_size(sc->mem_res)) {
4269 device_printf(dev, "impossible memory region size %ld\n",
4270 rman_get_size(sc->mem_res));
4276 * Make NULL terminated copy of the EEPROM strings section of
4279 bzero(sc->eeprom_strings, MXGE_EEPROM_STRINGS_SIZE);
4280 bus_space_read_region_1(rman_get_bustag(sc->mem_res),
4281 rman_get_bushandle(sc->mem_res),
4282 sc->sram_size - MXGE_EEPROM_STRINGS_SIZE,
4283 sc->eeprom_strings, MXGE_EEPROM_STRINGS_SIZE - 2);
4284 err = mxge_parse_strings(sc);
4286 device_printf(dev, "parse EEPROM string failed\n");
4291 * Enable write combining for efficient use of PCIe bus
4296 * Allocate the out of band DMA memory
4298 err = mxge_dma_alloc(sc, &sc->cmd_dma, sizeof(mxge_cmd_t), 64);
4300 device_printf(dev, "alloc cmd DMA buf failed\n");
4303 sc->cmd = sc->cmd_dma.dmem_addr;
4305 err = mxge_dma_alloc(sc, &sc->zeropad_dma, 64, 64);
4307 device_printf(dev, "alloc zeropad DMA buf failed\n");
4311 err = mxge_dma_alloc(sc, &sc->dmabench_dma, 4096, 4096);
4313 device_printf(dev, "alloc dmabench DMA buf failed\n");
4317 /* Select & load the firmware */
4318 err = mxge_select_firmware(sc);
4320 device_printf(dev, "select firmware failed\n");
4324 mxge_slice_probe(sc);
4325 err = mxge_alloc_slices(sc);
4327 device_printf(dev, "alloc slices failed\n");
4331 err = mxge_alloc_intr(sc);
4333 device_printf(dev, "alloc intr failed\n");
4337 /* Setup serializes */
4338 mxge_setup_serialize(sc);
4340 err = mxge_reset(sc, 0);
4342 device_printf(dev, "reset failed\n");
4346 err = mxge_alloc_rings(sc);
4348 device_printf(dev, "failed to allocate rings\n");
4352 ifp->if_baudrate = IF_Gbps(10UL);
4353 ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO;
4354 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_TSO;
4356 ifp->if_capabilities |= IFCAP_VLAN_MTU;
4358 /* Well, its software, sigh */
4359 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
4361 ifp->if_capenable = ifp->if_capabilities;
4364 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
4365 ifp->if_init = mxge_init;
4366 ifp->if_ioctl = mxge_ioctl;
4367 ifp->if_start = mxge_start;
4368 #ifdef IFPOLL_ENABLE
4369 if (sc->intr_type != PCI_INTR_TYPE_LEGACY)
4370 ifp->if_npoll = mxge_npoll;
4372 ifp->if_serialize = mxge_serialize;
4373 ifp->if_deserialize = mxge_deserialize;
4374 ifp->if_tryserialize = mxge_tryserialize;
4376 ifp->if_serialize_assert = mxge_serialize_assert;
4379 /* Increase TSO burst length */
4380 ifp->if_tsolen = (32 * ETHERMTU);
4382 /* Initialise the ifmedia structure */
4383 mxge_media_init(sc);
4384 mxge_media_probe(sc);
4386 ether_ifattach(ifp, sc->mac_addr, NULL);
4388 /* Setup TX rings and subqueues */
4389 for (i = 0; i < sc->num_tx_rings; ++i) {
4390 struct ifaltq_subque *ifsq = ifq_get_subq(&ifp->if_snd, i);
4391 struct mxge_slice_state *ss = &sc->ss[i];
4393 ifsq_set_cpuid(ifsq, ss->intr_cpuid);
4394 ifsq_set_hw_serialize(ifsq, &ss->tx.tx_serialize);
4395 ifsq_set_priv(ifsq, &ss->tx);
4398 ifsq_watchdog_init(&ss->tx.watchdog, ifsq, mxge_watchdog);
4403 * We are not ready to do "gather" jumbo frame, so
4404 * limit MTU to MJUMPAGESIZE
4406 sc->max_mtu = MJUMPAGESIZE -
4407 ETHER_HDR_LEN - EVL_ENCAPLEN - MXGEFW_PAD - 1;
4410 err = mxge_setup_intr(sc);
4412 device_printf(dev, "alloc and setup intr failed\n");
4413 ether_ifdetach(ifp);
4417 mxge_add_sysctls(sc);
4419 callout_reset_bycpu(&sc->co_hdl, mxge_ticks, mxge_tick, sc,
4420 sc->ss[0].intr_cpuid);
4429 mxge_detach(device_t dev)
4431 mxge_softc_t *sc = device_get_softc(dev);
4433 if (device_is_attached(dev)) {
4434 struct ifnet *ifp = sc->ifp;
4436 ifnet_serialize_all(ifp);
4439 if (ifp->if_flags & IFF_RUNNING)
4441 callout_stop(&sc->co_hdl);
4443 mxge_teardown_intr(sc, sc->num_slices);
4445 ifnet_deserialize_all(ifp);
4447 callout_terminate(&sc->co_hdl);
4449 ether_ifdetach(ifp);
4451 ifmedia_removeall(&sc->media);
4453 if (sc->cmd != NULL && sc->zeropad_dma.dmem_addr != NULL &&
4455 mxge_dummy_rdma(sc, 0);
4458 mxge_rem_sysctls(sc);
4459 mxge_free_rings(sc);
4461 /* MUST after sysctls, intr and rings are freed */
4462 mxge_free_slices(sc);
4464 if (sc->dmabench_dma.dmem_addr != NULL)
4465 mxge_dma_free(&sc->dmabench_dma);
4466 if (sc->zeropad_dma.dmem_addr != NULL)
4467 mxge_dma_free(&sc->zeropad_dma);
4468 if (sc->cmd_dma.dmem_addr != NULL)
4469 mxge_dma_free(&sc->cmd_dma);
4471 if (sc->msix_table_res != NULL) {
4472 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(2),
4473 sc->msix_table_res);
4475 if (sc->mem_res != NULL) {
4476 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BARS,
4480 if (sc->parent_dmat != NULL)
4481 bus_dma_tag_destroy(sc->parent_dmat);
4487 mxge_shutdown(device_t dev)
4493 mxge_free_msix(struct mxge_softc *sc, boolean_t setup)
4497 KKASSERT(sc->num_slices > 1);
4499 for (i = 0; i < sc->num_slices; ++i) {
4500 struct mxge_slice_state *ss = &sc->ss[i];
4502 if (ss->intr_res != NULL) {
4503 bus_release_resource(sc->dev, SYS_RES_IRQ,
4504 ss->intr_rid, ss->intr_res);
4506 if (ss->intr_rid >= 0)
4507 pci_release_msix_vector(sc->dev, ss->intr_rid);
4510 pci_teardown_msix(sc->dev);
4514 mxge_alloc_msix(struct mxge_softc *sc)
4516 struct mxge_slice_state *ss;
4517 int offset, rid, error, i;
4518 boolean_t setup = FALSE;
4520 KKASSERT(sc->num_slices > 1);
4522 if (sc->num_slices == ncpus2) {
4527 offset_def = (sc->num_slices * device_get_unit(sc->dev)) %
4530 offset = device_getenv_int(sc->dev, "msix.offset", offset_def);
4531 if (offset >= ncpus2 ||
4532 offset % sc->num_slices != 0) {
4533 device_printf(sc->dev, "invalid msix.offset %d, "
4534 "use %d\n", offset, offset_def);
4535 offset = offset_def;
4541 ss->intr_serialize = &sc->main_serialize;
4542 ss->intr_func = mxge_msi;
4543 ksnprintf(ss->intr_desc0, sizeof(ss->intr_desc0),
4544 "%s comb", device_get_nameunit(sc->dev));
4545 ss->intr_desc = ss->intr_desc0;
4546 ss->intr_cpuid = offset;
4548 for (i = 1; i < sc->num_slices; ++i) {
4551 ss->intr_serialize = &ss->rx_data.rx_serialize;
4552 if (sc->num_tx_rings == 1) {
4553 ss->intr_func = mxge_msix_rx;
4554 ksnprintf(ss->intr_desc0, sizeof(ss->intr_desc0),
4555 "%s rx", device_get_nameunit(sc->dev));
4557 ss->intr_func = mxge_msix_rxtx;
4558 ksnprintf(ss->intr_desc0, sizeof(ss->intr_desc0),
4559 "%s rxtx", device_get_nameunit(sc->dev));
4561 ss->intr_desc = ss->intr_desc0;
4562 ss->intr_cpuid = offset + i;
4566 sc->msix_table_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
4568 if (sc->msix_table_res == NULL) {
4569 device_printf(sc->dev, "couldn't alloc MSI-X table res\n");
4573 error = pci_setup_msix(sc->dev);
4575 device_printf(sc->dev, "could not setup MSI-X\n");
4580 for (i = 0; i < sc->num_slices; ++i) {
4583 error = pci_alloc_msix_vector(sc->dev, i, &ss->intr_rid,
4586 device_printf(sc->dev, "could not alloc "
4587 "MSI-X %d on cpu%d\n", i, ss->intr_cpuid);
4591 ss->intr_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
4592 &ss->intr_rid, RF_ACTIVE);
4593 if (ss->intr_res == NULL) {
4594 device_printf(sc->dev, "could not alloc "
4595 "MSI-X %d resource\n", i);
4601 pci_enable_msix(sc->dev);
4602 sc->intr_type = PCI_INTR_TYPE_MSIX;
4605 mxge_free_msix(sc, setup);
4610 mxge_alloc_intr(struct mxge_softc *sc)
4612 struct mxge_slice_state *ss;
4615 if (sc->num_slices > 1) {
4618 error = mxge_alloc_msix(sc);
4621 KKASSERT(sc->intr_type == PCI_INTR_TYPE_MSIX);
4627 sc->intr_type = pci_alloc_1intr(sc->dev, mxge_msi_enable,
4628 &ss->intr_rid, &irq_flags);
4630 ss->intr_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
4631 &ss->intr_rid, irq_flags);
4632 if (ss->intr_res == NULL) {
4633 device_printf(sc->dev, "could not alloc interrupt\n");
4637 if (sc->intr_type == PCI_INTR_TYPE_LEGACY)
4638 ss->intr_func = mxge_legacy;
4640 ss->intr_func = mxge_msi;
4641 ss->intr_serialize = &sc->main_serialize;
4642 ss->intr_cpuid = rman_get_cpuid(ss->intr_res);
4648 mxge_setup_intr(struct mxge_softc *sc)
4652 for (i = 0; i < sc->num_slices; ++i) {
4653 struct mxge_slice_state *ss = &sc->ss[i];
4656 error = bus_setup_intr_descr(sc->dev, ss->intr_res,
4657 INTR_MPSAFE, ss->intr_func, ss, &ss->intr_hand,
4658 ss->intr_serialize, ss->intr_desc);
4660 device_printf(sc->dev, "can't setup %dth intr\n", i);
4661 mxge_teardown_intr(sc, i);
4669 mxge_teardown_intr(struct mxge_softc *sc, int cnt)
4676 for (i = 0; i < cnt; ++i) {
4677 struct mxge_slice_state *ss = &sc->ss[i];
4679 bus_teardown_intr(sc->dev, ss->intr_res, ss->intr_hand);
4684 mxge_free_intr(struct mxge_softc *sc)
4689 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
4690 struct mxge_slice_state *ss = &sc->ss[0];
4692 if (ss->intr_res != NULL) {
4693 bus_release_resource(sc->dev, SYS_RES_IRQ,
4694 ss->intr_rid, ss->intr_res);
4696 if (sc->intr_type == PCI_INTR_TYPE_MSI)
4697 pci_release_msi(sc->dev);
4699 mxge_free_msix(sc, TRUE);