2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
37 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Engineer, Wind River Systems
44 * The Broadcom BCM5700 is based on technology originally developed by
45 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
46 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
47 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
48 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
49 * frames, highly configurable RX filtering, and 16 RX and TX queues
50 * (which, along with RX filter rules, can be used for QOS applications).
51 * Other features, such as TCP segmentation, may be available as part
52 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
53 * firmware images can be stored in hardware and need not be compiled
56 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
57 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
59 * The BCM5701 is a single-chip solution incorporating both the BCM5700
60 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
61 * does not support external SSRAM.
63 * Broadcom also produces a variation of the BCM5700 under the "Altima"
64 * brand name, which is functionally similar but lacks PCI-X support.
66 * Without external SSRAM, you can only have at most 4 TX rings,
67 * and the use of the mini RX ring is disabled. This seems to imply
68 * that these features are simply not available on the BCM5701. As a
69 * result, this driver does not implement any support for the mini RX
73 #include "opt_ifpoll.h"
75 #include <sys/param.h>
77 #include <sys/endian.h>
78 #include <sys/kernel.h>
80 #include <sys/interrupt.h>
82 #include <sys/malloc.h>
83 #include <sys/queue.h>
85 #include <sys/serialize.h>
86 #include <sys/socket.h>
87 #include <sys/sockio.h>
88 #include <sys/sysctl.h>
90 #include <netinet/ip.h>
91 #include <netinet/tcp.h>
94 #include <net/ethernet.h>
96 #include <net/if_arp.h>
97 #include <net/if_dl.h>
98 #include <net/if_media.h>
99 #include <net/if_poll.h>
100 #include <net/if_types.h>
101 #include <net/ifq_var.h>
102 #include <net/vlan/if_vlan_var.h>
103 #include <net/vlan/if_vlan_ether.h>
105 #include <dev/netif/mii_layer/mii.h>
106 #include <dev/netif/mii_layer/miivar.h>
107 #include <dev/netif/mii_layer/brgphyreg.h>
110 #include <bus/pci/pcireg.h>
111 #include <bus/pci/pcivar.h>
113 #include <dev/netif/bge/if_bgereg.h>
114 #include <dev/netif/bge/if_bgevar.h>
116 /* "device miibus" required. See GENERIC if you get errors here. */
117 #include "miibus_if.h"
119 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP)
121 #define BGE_RESET_SHUTDOWN 0
122 #define BGE_RESET_START 1
123 #define BGE_RESET_SUSPEND 2
125 static const struct bge_type {
130 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
131 "3COM 3C996 Gigabit Ethernet" },
133 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
134 "Alteon BCM5700 Gigabit Ethernet" },
135 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
136 "Alteon BCM5701 Gigabit Ethernet" },
138 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
139 "Altima AC1000 Gigabit Ethernet" },
140 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
141 "Altima AC1002 Gigabit Ethernet" },
142 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
143 "Altima AC9100 Gigabit Ethernet" },
145 { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
146 "Apple BCM5701 Gigabit Ethernet" },
148 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
149 "Broadcom BCM5700 Gigabit Ethernet" },
150 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
151 "Broadcom BCM5701 Gigabit Ethernet" },
152 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
153 "Broadcom BCM5702 Gigabit Ethernet" },
154 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
155 "Broadcom BCM5702X Gigabit Ethernet" },
156 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
157 "Broadcom BCM5702 Gigabit Ethernet" },
158 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
159 "Broadcom BCM5703 Gigabit Ethernet" },
160 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
161 "Broadcom BCM5703X Gigabit Ethernet" },
162 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
163 "Broadcom BCM5703 Gigabit Ethernet" },
164 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
165 "Broadcom BCM5704C Dual Gigabit Ethernet" },
166 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
167 "Broadcom BCM5704S Dual Gigabit Ethernet" },
168 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
169 "Broadcom BCM5704S Dual Gigabit Ethernet" },
170 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
171 "Broadcom BCM5705 Gigabit Ethernet" },
172 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
173 "Broadcom BCM5705F Gigabit Ethernet" },
174 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
175 "Broadcom BCM5705K Gigabit Ethernet" },
176 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
177 "Broadcom BCM5705M Gigabit Ethernet" },
178 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
179 "Broadcom BCM5705M Gigabit Ethernet" },
180 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
181 "Broadcom BCM5714C Gigabit Ethernet" },
182 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
183 "Broadcom BCM5714S Gigabit Ethernet" },
184 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
185 "Broadcom BCM5715 Gigabit Ethernet" },
186 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
187 "Broadcom BCM5715S Gigabit Ethernet" },
188 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
189 "Broadcom BCM5720 Gigabit Ethernet" },
190 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
191 "Broadcom BCM5721 Gigabit Ethernet" },
192 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
193 "Broadcom BCM5722 Gigabit Ethernet" },
194 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5723,
195 "Broadcom BCM5723 Gigabit Ethernet" },
196 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
197 "Broadcom BCM5750 Gigabit Ethernet" },
198 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
199 "Broadcom BCM5750M Gigabit Ethernet" },
200 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
201 "Broadcom BCM5751 Gigabit Ethernet" },
202 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
203 "Broadcom BCM5751F Gigabit Ethernet" },
204 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
205 "Broadcom BCM5751M Gigabit Ethernet" },
206 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
207 "Broadcom BCM5752 Gigabit Ethernet" },
208 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
209 "Broadcom BCM5752M Gigabit Ethernet" },
210 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
211 "Broadcom BCM5753 Gigabit Ethernet" },
212 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
213 "Broadcom BCM5753F Gigabit Ethernet" },
214 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
215 "Broadcom BCM5753M Gigabit Ethernet" },
216 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
217 "Broadcom BCM5754 Gigabit Ethernet" },
218 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
219 "Broadcom BCM5754M Gigabit Ethernet" },
220 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
221 "Broadcom BCM5755 Gigabit Ethernet" },
222 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
223 "Broadcom BCM5755M Gigabit Ethernet" },
224 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
225 "Broadcom BCM5756 Gigabit Ethernet" },
226 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761,
227 "Broadcom BCM5761 Gigabit Ethernet" },
228 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761E,
229 "Broadcom BCM5761E Gigabit Ethernet" },
230 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761S,
231 "Broadcom BCM5761S Gigabit Ethernet" },
232 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761SE,
233 "Broadcom BCM5761SE Gigabit Ethernet" },
234 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5764,
235 "Broadcom BCM5764 Gigabit Ethernet" },
236 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
237 "Broadcom BCM5780 Gigabit Ethernet" },
238 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
239 "Broadcom BCM5780S Gigabit Ethernet" },
240 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
241 "Broadcom BCM5781 Gigabit Ethernet" },
242 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
243 "Broadcom BCM5782 Gigabit Ethernet" },
244 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5784,
245 "Broadcom BCM5784 Gigabit Ethernet" },
246 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785F,
247 "Broadcom BCM5785F Gigabit Ethernet" },
248 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785G,
249 "Broadcom BCM5785G Gigabit Ethernet" },
250 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
251 "Broadcom BCM5786 Gigabit Ethernet" },
252 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
253 "Broadcom BCM5787 Gigabit Ethernet" },
254 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
255 "Broadcom BCM5787F Gigabit Ethernet" },
256 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
257 "Broadcom BCM5787M Gigabit Ethernet" },
258 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
259 "Broadcom BCM5788 Gigabit Ethernet" },
260 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
261 "Broadcom BCM5789 Gigabit Ethernet" },
262 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
263 "Broadcom BCM5901 Fast Ethernet" },
264 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
265 "Broadcom BCM5901A2 Fast Ethernet" },
266 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
267 "Broadcom BCM5903M Fast Ethernet" },
268 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906,
269 "Broadcom BCM5906 Fast Ethernet"},
270 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M,
271 "Broadcom BCM5906M Fast Ethernet"},
272 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57760,
273 "Broadcom BCM57760 Gigabit Ethernet"},
274 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57780,
275 "Broadcom BCM57780 Gigabit Ethernet"},
276 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57788,
277 "Broadcom BCM57788 Gigabit Ethernet"},
278 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57790,
279 "Broadcom BCM57790 Gigabit Ethernet"},
280 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
281 "SysKonnect Gigabit Ethernet" },
286 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
287 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
288 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
289 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
290 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
291 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
292 #define BGE_IS_5788(sc) ((sc)->bge_flags & BGE_FLAG_5788)
294 #define BGE_IS_CRIPPLED(sc) \
295 (BGE_IS_5788((sc)) || (sc)->bge_asicrev == BGE_ASICREV_BCM5700)
297 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
299 static int bge_probe(device_t);
300 static int bge_attach(device_t);
301 static int bge_detach(device_t);
302 static void bge_txeof(struct bge_softc *, uint16_t);
303 static void bge_rxeof(struct bge_softc *, uint16_t, int);
305 static void bge_tick(void *);
306 static void bge_stats_update(struct bge_softc *);
307 static void bge_stats_update_regs(struct bge_softc *);
309 bge_defrag_shortdma(struct mbuf *);
310 static int bge_encap(struct bge_softc *, struct mbuf **,
312 static void bge_xmit(struct bge_softc *, uint32_t);
313 static int bge_setup_tso(struct bge_softc *, struct mbuf **,
314 uint16_t *, uint16_t *);
317 static void bge_npoll(struct ifnet *, struct ifpoll_info *);
318 static void bge_npoll_compat(struct ifnet *, void *, int );
320 static void bge_intr_crippled(void *);
321 static void bge_intr_legacy(void *);
322 static void bge_msi(void *);
323 static void bge_msi_oneshot(void *);
324 static void bge_intr(struct bge_softc *);
325 static void bge_enable_intr(struct bge_softc *);
326 static void bge_disable_intr(struct bge_softc *);
327 static void bge_start(struct ifnet *, struct ifaltq_subque *);
328 static int bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
329 static void bge_init(void *);
330 static void bge_stop(struct bge_softc *);
331 static void bge_watchdog(struct ifnet *);
332 static void bge_shutdown(device_t);
333 static int bge_suspend(device_t);
334 static int bge_resume(device_t);
335 static int bge_ifmedia_upd(struct ifnet *);
336 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
338 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
339 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
341 static uint8_t bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
342 static int bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
344 static void bge_setmulti(struct bge_softc *);
345 static void bge_setpromisc(struct bge_softc *);
346 static void bge_enable_msi(struct bge_softc *sc);
348 static int bge_alloc_jumbo_mem(struct bge_softc *);
349 static void bge_free_jumbo_mem(struct bge_softc *);
350 static struct bge_jslot
351 *bge_jalloc(struct bge_softc *);
352 static void bge_jfree(void *);
353 static void bge_jref(void *);
354 static int bge_newbuf_std(struct bge_softc *, int, int);
355 static int bge_newbuf_jumbo(struct bge_softc *, int, int);
356 static void bge_setup_rxdesc_std(struct bge_softc *, int);
357 static void bge_setup_rxdesc_jumbo(struct bge_softc *, int);
358 static int bge_init_rx_ring_std(struct bge_softc *);
359 static void bge_free_rx_ring_std(struct bge_softc *);
360 static int bge_init_rx_ring_jumbo(struct bge_softc *);
361 static void bge_free_rx_ring_jumbo(struct bge_softc *);
362 static void bge_free_tx_ring(struct bge_softc *);
363 static int bge_init_tx_ring(struct bge_softc *);
365 static int bge_chipinit(struct bge_softc *);
366 static int bge_blockinit(struct bge_softc *);
367 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t);
369 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
370 static void bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
372 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
374 static void bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
375 static void bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
376 static void bge_writembx(struct bge_softc *, int, int);
378 static int bge_miibus_readreg(device_t, int, int);
379 static int bge_miibus_writereg(device_t, int, int, int);
380 static void bge_miibus_statchg(device_t);
381 static void bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
382 static void bge_tbi_link_upd(struct bge_softc *, uint32_t);
383 static void bge_copper_link_upd(struct bge_softc *, uint32_t);
384 static void bge_autopoll_link_upd(struct bge_softc *, uint32_t);
385 static void bge_link_poll(struct bge_softc *);
387 static void bge_reset(struct bge_softc *);
389 static int bge_dma_alloc(struct bge_softc *);
390 static void bge_dma_free(struct bge_softc *);
391 static int bge_dma_block_alloc(struct bge_softc *, bus_size_t,
392 bus_dma_tag_t *, bus_dmamap_t *,
393 void **, bus_addr_t *);
394 static void bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
396 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
397 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
398 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
399 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
401 static void bge_coal_change(struct bge_softc *);
402 static int bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
403 static int bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
404 static int bge_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS);
405 static int bge_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS);
406 static int bge_sysctl_rx_coal_ticks_int(SYSCTL_HANDLER_ARGS);
407 static int bge_sysctl_tx_coal_ticks_int(SYSCTL_HANDLER_ARGS);
408 static int bge_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS);
409 static int bge_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS);
410 static int bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *,
413 static void bge_sig_post_reset(struct bge_softc *, int);
414 static void bge_sig_legacy(struct bge_softc *, int);
415 static void bge_sig_pre_reset(struct bge_softc *, int);
416 static void bge_stop_fw(struct bge_softc *);
417 static void bge_asf_driver_up(struct bge_softc *);
419 static void bge_ape_lock_init(struct bge_softc *);
420 static void bge_ape_read_fw_ver(struct bge_softc *);
421 static int bge_ape_lock(struct bge_softc *, int);
422 static void bge_ape_unlock(struct bge_softc *, int);
423 static void bge_ape_send_event(struct bge_softc *, uint32_t);
424 static void bge_ape_driver_state_change(struct bge_softc *, int);
427 * Set following tunable to 1 for some IBM blade servers with the DNLK
428 * switch module. Auto negotiation is broken for those configurations.
430 static int bge_fake_autoneg = 0;
431 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
433 static int bge_msi_enable = 1;
434 TUNABLE_INT("hw.bge.msi.enable", &bge_msi_enable);
436 static int bge_allow_asf = 1;
437 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf);
439 #if !defined(KTR_IF_BGE)
440 #define KTR_IF_BGE KTR_ALL
442 KTR_INFO_MASTER(if_bge);
443 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr");
444 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt");
445 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt");
446 #define logif(name) KTR_LOG(if_bge_ ## name)
448 static device_method_t bge_methods[] = {
449 /* Device interface */
450 DEVMETHOD(device_probe, bge_probe),
451 DEVMETHOD(device_attach, bge_attach),
452 DEVMETHOD(device_detach, bge_detach),
453 DEVMETHOD(device_shutdown, bge_shutdown),
454 DEVMETHOD(device_suspend, bge_suspend),
455 DEVMETHOD(device_resume, bge_resume),
458 DEVMETHOD(bus_print_child, bus_generic_print_child),
459 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
462 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
463 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
464 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
469 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
470 static devclass_t bge_devclass;
472 DECLARE_DUMMY_MODULE(if_bge);
473 MODULE_DEPEND(if_bge, miibus, 1, 1, 1);
474 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, NULL, NULL);
475 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, NULL, NULL);
478 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
480 device_t dev = sc->bge_dev;
483 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
484 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
487 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
488 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
489 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
494 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
496 device_t dev = sc->bge_dev;
498 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
499 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
502 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
503 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
504 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
509 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
511 device_t dev = sc->bge_dev;
513 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
514 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
519 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
521 device_t dev = sc->bge_dev;
523 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
524 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
528 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
530 CSR_WRITE_4(sc, off, val);
534 bge_writembx(struct bge_softc *sc, int off, int val)
536 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
537 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
539 CSR_WRITE_4(sc, off, val);
540 if (sc->bge_mbox_reorder)
545 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
547 uint32_t access, byte = 0;
551 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
552 for (i = 0; i < 8000; i++) {
553 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
561 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
562 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
564 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
565 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
566 for (i = 0; i < BGE_TIMEOUT * 10; i++) {
568 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
574 if (i == BGE_TIMEOUT * 10) {
575 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n");
580 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
582 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
584 /* Disable access. */
585 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
588 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
589 CSR_READ_4(sc, BGE_NVRAM_SWARB);
595 * Read a sequence of bytes from NVRAM.
598 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
603 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
606 for (i = 0; i < cnt; i++) {
607 err = bge_nvram_getbyte(sc, off + i, &byte);
613 return (err ? 1 : 0);
617 * Read a byte of data stored in the EEPROM at address 'addr.' The
618 * BCM570x supports both the traditional bitbang interface and an
619 * auto access interface for reading the EEPROM. We use the auto
623 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
629 * Enable use of auto EEPROM access so we can avoid
630 * having to use the bitbang method.
632 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
634 /* Reset the EEPROM, load the clock period. */
635 CSR_WRITE_4(sc, BGE_EE_ADDR,
636 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
639 /* Issue the read EEPROM command. */
640 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
642 /* Wait for completion */
643 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
645 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
649 if (i == BGE_TIMEOUT) {
650 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
655 byte = CSR_READ_4(sc, BGE_EE_DATA);
657 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
663 * Read a sequence of bytes from the EEPROM.
666 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
672 for (byte = 0, err = 0, i = 0; i < len; i++) {
673 err = bge_eeprom_getbyte(sc, off + i, &byte);
683 bge_miibus_readreg(device_t dev, int phy, int reg)
685 struct bge_softc *sc = device_get_softc(dev);
689 KASSERT(phy == sc->bge_phyno,
690 ("invalid phyno %d, should be %d", phy, sc->bge_phyno));
692 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
695 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
696 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
697 CSR_WRITE_4(sc, BGE_MI_MODE,
698 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
702 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
703 BGE_MIPHY(phy) | BGE_MIREG(reg));
705 /* Poll for the PHY register access to complete. */
706 for (i = 0; i < BGE_TIMEOUT; i++) {
708 val = CSR_READ_4(sc, BGE_MI_COMM);
709 if ((val & BGE_MICOMM_BUSY) == 0) {
711 val = CSR_READ_4(sc, BGE_MI_COMM);
715 if (i == BGE_TIMEOUT) {
716 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
717 "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
721 /* Restore the autopoll bit if necessary. */
722 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
723 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
727 bge_ape_unlock(sc, sc->bge_phy_ape_lock);
729 if (val & BGE_MICOMM_READFAIL)
732 return (val & 0xFFFF);
736 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
738 struct bge_softc *sc = device_get_softc(dev);
741 KASSERT(phy == sc->bge_phyno,
742 ("invalid phyno %d, should be %d", phy, sc->bge_phyno));
744 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
745 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
748 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
751 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
752 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
753 CSR_WRITE_4(sc, BGE_MI_MODE,
754 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
758 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
759 BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
761 for (i = 0; i < BGE_TIMEOUT; i++) {
763 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
765 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
769 if (i == BGE_TIMEOUT) {
770 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
771 "(phy %d, reg %d, val %d)\n", phy, reg, val);
774 /* Restore the autopoll bit if necessary. */
775 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
776 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
780 bge_ape_unlock(sc, sc->bge_phy_ape_lock);
786 bge_miibus_statchg(device_t dev)
788 struct bge_softc *sc;
789 struct mii_data *mii;
792 sc = device_get_softc(dev);
793 if ((sc->arpcom.ac_if.if_flags & IFF_RUNNING) == 0)
796 mii = device_get_softc(sc->bge_miibus);
798 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
799 (IFM_ACTIVE | IFM_AVALID)) {
800 switch (IFM_SUBTYPE(mii->mii_media_active)) {
808 if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
820 if (sc->bge_link == 0)
824 * APE firmware touches these registers to keep the MAC
825 * connected to the outside world. Try to keep the
829 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) &
830 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX);
832 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
833 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
834 mac_mode |= BGE_PORTMODE_GMII;
836 mac_mode |= BGE_PORTMODE_MII;
838 if ((mii->mii_media_active & IFM_GMASK) != IFM_FDX)
839 mac_mode |= BGE_MACMODE_HALF_DUPLEX;
841 CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode);
846 * Memory management for jumbo frames.
849 bge_alloc_jumbo_mem(struct bge_softc *sc)
851 struct ifnet *ifp = &sc->arpcom.ac_if;
852 struct bge_jslot *entry;
858 * Create tag for jumbo mbufs.
859 * This is really a bit of a kludge. We allocate a special
860 * jumbo buffer pool which (thanks to the way our DMA
861 * memory allocation works) will consist of contiguous
862 * pages. This means that even though a jumbo buffer might
863 * be larger than a page size, we don't really need to
864 * map it into more than one DMA segment. However, the
865 * default mbuf tag will result in multi-segment mappings,
866 * so we have to create a special jumbo mbuf tag that
867 * lets us get away with mapping the jumbo buffers as
868 * a single segment. I think eventually the driver should
869 * be changed so that it uses ordinary mbufs and cluster
870 * buffers, i.e. jumbo frames can span multiple DMA
871 * descriptors. But that's a project for another day.
875 * Create DMA stuffs for jumbo RX ring.
877 error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
878 &sc->bge_cdata.bge_rx_jumbo_ring_tag,
879 &sc->bge_cdata.bge_rx_jumbo_ring_map,
880 (void *)&sc->bge_ldata.bge_rx_jumbo_ring,
881 &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
883 if_printf(ifp, "could not create jumbo RX ring\n");
888 * Create DMA stuffs for jumbo buffer block.
890 error = bge_dma_block_alloc(sc, BGE_JMEM,
891 &sc->bge_cdata.bge_jumbo_tag,
892 &sc->bge_cdata.bge_jumbo_map,
893 (void **)&sc->bge_ldata.bge_jumbo_buf,
896 if_printf(ifp, "could not create jumbo buffer\n");
900 SLIST_INIT(&sc->bge_jfree_listhead);
903 * Now divide it up into 9K pieces and save the addresses
904 * in an array. Note that we play an evil trick here by using
905 * the first few bytes in the buffer to hold the the address
906 * of the softc structure for this interface. This is because
907 * bge_jfree() needs it, but it is called by the mbuf management
908 * code which will not pass it to us explicitly.
910 for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
911 entry = &sc->bge_cdata.bge_jslots[i];
913 entry->bge_buf = ptr;
914 entry->bge_paddr = paddr;
915 entry->bge_inuse = 0;
917 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
926 bge_free_jumbo_mem(struct bge_softc *sc)
928 /* Destroy jumbo RX ring. */
929 bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
930 sc->bge_cdata.bge_rx_jumbo_ring_map,
931 sc->bge_ldata.bge_rx_jumbo_ring);
933 /* Destroy jumbo buffer block. */
934 bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
935 sc->bge_cdata.bge_jumbo_map,
936 sc->bge_ldata.bge_jumbo_buf);
940 * Allocate a jumbo buffer.
942 static struct bge_jslot *
943 bge_jalloc(struct bge_softc *sc)
945 struct bge_jslot *entry;
947 lwkt_serialize_enter(&sc->bge_jslot_serializer);
948 entry = SLIST_FIRST(&sc->bge_jfree_listhead);
950 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
951 entry->bge_inuse = 1;
953 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
955 lwkt_serialize_exit(&sc->bge_jslot_serializer);
960 * Adjust usage count on a jumbo buffer.
965 struct bge_jslot *entry = (struct bge_jslot *)arg;
966 struct bge_softc *sc = entry->bge_sc;
969 panic("bge_jref: can't find softc pointer!");
971 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
972 panic("bge_jref: asked to reference buffer "
973 "that we don't manage!");
974 } else if (entry->bge_inuse == 0) {
975 panic("bge_jref: buffer already free!");
977 atomic_add_int(&entry->bge_inuse, 1);
982 * Release a jumbo buffer.
987 struct bge_jslot *entry = (struct bge_jslot *)arg;
988 struct bge_softc *sc = entry->bge_sc;
991 panic("bge_jfree: can't find softc pointer!");
993 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
994 panic("bge_jfree: asked to free buffer that we don't manage!");
995 } else if (entry->bge_inuse == 0) {
996 panic("bge_jfree: buffer already free!");
999 * Possible MP race to 0, use the serializer. The atomic insn
1000 * is still needed for races against bge_jref().
1002 lwkt_serialize_enter(&sc->bge_jslot_serializer);
1003 atomic_subtract_int(&entry->bge_inuse, 1);
1004 if (entry->bge_inuse == 0) {
1005 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
1008 lwkt_serialize_exit(&sc->bge_jslot_serializer);
1014 * Intialize a standard receive ring descriptor.
1017 bge_newbuf_std(struct bge_softc *sc, int i, int init)
1019 struct mbuf *m_new = NULL;
1020 bus_dma_segment_t seg;
1024 m_new = m_getcl(init ? M_WAITOK : M_NOWAIT, MT_DATA, M_PKTHDR);
1027 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1029 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1030 m_adj(m_new, ETHER_ALIGN);
1032 error = bus_dmamap_load_mbuf_segment(sc->bge_cdata.bge_rx_mtag,
1033 sc->bge_cdata.bge_rx_tmpmap, m_new,
1034 &seg, 1, &nsegs, BUS_DMA_NOWAIT);
1041 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1042 sc->bge_cdata.bge_rx_std_dmamap[i],
1043 BUS_DMASYNC_POSTREAD);
1044 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1045 sc->bge_cdata.bge_rx_std_dmamap[i]);
1048 map = sc->bge_cdata.bge_rx_tmpmap;
1049 sc->bge_cdata.bge_rx_tmpmap = sc->bge_cdata.bge_rx_std_dmamap[i];
1050 sc->bge_cdata.bge_rx_std_dmamap[i] = map;
1052 sc->bge_cdata.bge_rx_std_chain[i].bge_mbuf = m_new;
1053 sc->bge_cdata.bge_rx_std_chain[i].bge_paddr = seg.ds_addr;
1055 bge_setup_rxdesc_std(sc, i);
1060 bge_setup_rxdesc_std(struct bge_softc *sc, int i)
1062 struct bge_rxchain *rc;
1063 struct bge_rx_bd *r;
1065 rc = &sc->bge_cdata.bge_rx_std_chain[i];
1066 r = &sc->bge_ldata.bge_rx_std_ring[i];
1068 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1069 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1070 r->bge_len = rc->bge_mbuf->m_len;
1072 r->bge_flags = BGE_RXBDFLAG_END;
1076 * Initialize a jumbo receive ring descriptor. This allocates
1077 * a jumbo buffer from the pool managed internally by the driver.
1080 bge_newbuf_jumbo(struct bge_softc *sc, int i, int init)
1082 struct mbuf *m_new = NULL;
1083 struct bge_jslot *buf;
1086 /* Allocate the mbuf. */
1087 MGETHDR(m_new, init ? M_WAITOK : M_NOWAIT, MT_DATA);
1091 /* Allocate the jumbo buffer */
1092 buf = bge_jalloc(sc);
1098 /* Attach the buffer to the mbuf. */
1099 m_new->m_ext.ext_arg = buf;
1100 m_new->m_ext.ext_buf = buf->bge_buf;
1101 m_new->m_ext.ext_free = bge_jfree;
1102 m_new->m_ext.ext_ref = bge_jref;
1103 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
1105 m_new->m_flags |= M_EXT;
1107 m_new->m_data = m_new->m_ext.ext_buf;
1108 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
1110 paddr = buf->bge_paddr;
1111 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
1112 m_adj(m_new, ETHER_ALIGN);
1113 paddr += ETHER_ALIGN;
1116 /* Save necessary information */
1117 sc->bge_cdata.bge_rx_jumbo_chain[i].bge_mbuf = m_new;
1118 sc->bge_cdata.bge_rx_jumbo_chain[i].bge_paddr = paddr;
1120 /* Set up the descriptor. */
1121 bge_setup_rxdesc_jumbo(sc, i);
1126 bge_setup_rxdesc_jumbo(struct bge_softc *sc, int i)
1128 struct bge_rx_bd *r;
1129 struct bge_rxchain *rc;
1131 r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
1132 rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1134 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
1135 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
1136 r->bge_len = rc->bge_mbuf->m_len;
1138 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
1142 bge_init_rx_ring_std(struct bge_softc *sc)
1146 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1147 error = bge_newbuf_std(sc, i, 1);
1152 sc->bge_std = BGE_STD_RX_RING_CNT - 1;
1153 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
1159 bge_free_rx_ring_std(struct bge_softc *sc)
1163 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1164 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_std_chain[i];
1166 if (rc->bge_mbuf != NULL) {
1167 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1168 sc->bge_cdata.bge_rx_std_dmamap[i]);
1169 m_freem(rc->bge_mbuf);
1170 rc->bge_mbuf = NULL;
1172 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
1173 sizeof(struct bge_rx_bd));
1178 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1180 struct bge_rcb *rcb;
1183 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1184 error = bge_newbuf_jumbo(sc, i, 1);
1189 sc->bge_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
1191 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1192 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
1193 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1195 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
1201 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1205 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1206 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
1208 if (rc->bge_mbuf != NULL) {
1209 m_freem(rc->bge_mbuf);
1210 rc->bge_mbuf = NULL;
1212 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
1213 sizeof(struct bge_rx_bd));
1218 bge_free_tx_ring(struct bge_softc *sc)
1222 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1223 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1224 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1225 sc->bge_cdata.bge_tx_dmamap[i]);
1226 m_freem(sc->bge_cdata.bge_tx_chain[i]);
1227 sc->bge_cdata.bge_tx_chain[i] = NULL;
1229 bzero(&sc->bge_ldata.bge_tx_ring[i],
1230 sizeof(struct bge_tx_bd));
1235 bge_init_tx_ring(struct bge_softc *sc)
1238 sc->bge_tx_saved_considx = 0;
1239 sc->bge_tx_prodidx = 0;
1241 /* Initialize transmit producer index for host-memory send ring. */
1242 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1244 /* 5700 b2 errata */
1245 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1246 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1248 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1249 /* 5700 b2 errata */
1250 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1251 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1257 bge_setmulti(struct bge_softc *sc)
1260 struct ifmultiaddr *ifma;
1261 uint32_t hashes[4] = { 0, 0, 0, 0 };
1264 ifp = &sc->arpcom.ac_if;
1266 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1267 for (i = 0; i < 4; i++)
1268 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1272 /* First, zot all the existing filters. */
1273 for (i = 0; i < 4; i++)
1274 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1276 /* Now program new ones. */
1277 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1278 if (ifma->ifma_addr->sa_family != AF_LINK)
1281 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1282 ETHER_ADDR_LEN) & 0x7f;
1283 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1286 for (i = 0; i < 4; i++)
1287 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1291 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1292 * self-test results.
1295 bge_chipinit(struct bge_softc *sc)
1298 uint32_t dma_rw_ctl, mode_ctl;
1301 /* Set endian type before we access any non-PCI registers. */
1302 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
1303 BGE_INIT | sc->bge_pci_miscctl, 4);
1306 * Clear the MAC statistics block in the NIC's
1309 for (i = BGE_STATS_BLOCK;
1310 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1311 BGE_MEMWIN_WRITE(sc, i, 0);
1313 for (i = BGE_STATUS_BLOCK;
1314 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1315 BGE_MEMWIN_WRITE(sc, i, 0);
1317 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1319 * Fix data corruption caused by non-qword write with WB.
1320 * Fix master abort in PCI mode.
1321 * Fix PCI latency timer.
1323 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1324 val |= (1 << 10) | (1 << 12) | (1 << 13);
1325 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1328 /* Set up the PCI DMA control register. */
1329 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD;
1330 if (sc->bge_flags & BGE_FLAG_PCIE) {
1332 /* DMA read watermark not used on PCI-E */
1333 dma_rw_ctl |= (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1334 } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1336 if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1337 dma_rw_ctl |= (0x4 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1338 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1339 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1340 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5714) {
1341 dma_rw_ctl |= (0x4 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1342 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1343 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1344 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1345 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1346 uint32_t rd_wat = 0x7;
1349 clkctl = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1350 if ((sc->bge_flags & BGE_FLAG_MAXADDR_40BIT) &&
1351 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1353 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1354 } else if (clkctl == 0x6 || clkctl == 0x7) {
1356 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1358 if (sc->bge_asicrev == BGE_ASICREV_BCM5703)
1361 dma_rw_ctl |= (rd_wat << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1362 (3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1363 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1365 dma_rw_ctl |= (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1366 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1370 /* Conventional PCI bus */
1371 dma_rw_ctl |= (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1372 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1373 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1374 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1378 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1379 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1380 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1381 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1382 sc->bge_asicrev == BGE_ASICREV_BCM5701) {
1383 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1384 BGE_PCIDMARWCTL_ASRT_ALL_BE;
1386 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1389 * Set up general mode register.
1391 mode_ctl = BGE_DMA_SWAP_OPTIONS|
1392 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1393 BGE_MODECTL_TX_NO_PHDR_CSUM;
1396 * BCM5701 B5 have a bug causing data corruption when using
1397 * 64-bit DMA reads, which can be terminated early and then
1398 * completed later as 32-bit accesses, in combination with
1401 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1402 sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1403 mode_ctl |= BGE_MODECTL_FORCE_PCI32;
1406 * Tell the firmware the driver is running
1408 if (sc->bge_asf_mode & ASF_STACKUP)
1409 mode_ctl |= BGE_MODECTL_STACKUP;
1411 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1414 * Disable memory write invalidate. Apparently it is not supported
1415 * properly by these devices. Also ensure that INTx isn't disabled,
1416 * as these chips need it even when using MSI.
1418 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD,
1419 (PCIM_CMD_MWRICEN | PCIM_CMD_INTxDIS), 4);
1421 /* Set the timer prescaler (always 66Mhz) */
1422 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1424 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1425 DELAY(40); /* XXX */
1427 /* Put PHY into ready state */
1428 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1429 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1437 bge_blockinit(struct bge_softc *sc)
1439 struct bge_rcb *rcb;
1446 * Initialize the memory window pointer register so that
1447 * we can access the first 32K of internal NIC RAM. This will
1448 * allow us to set up the TX send ring RCBs and the RX return
1449 * ring RCBs, plus other things which live in NIC memory.
1451 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1453 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1455 if (!BGE_IS_5705_PLUS(sc)) {
1456 /* Configure mbuf memory pool */
1457 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1458 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1459 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1461 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1463 /* Configure DMA resource pool */
1464 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1465 BGE_DMA_DESCRIPTORS);
1466 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1469 /* Configure mbuf pool watermarks */
1470 if (!BGE_IS_5705_PLUS(sc)) {
1471 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1472 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1473 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1474 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1475 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1476 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1477 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1479 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1480 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1481 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1484 /* Configure DMA resource watermarks */
1485 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1486 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1488 /* Enable buffer manager */
1489 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1490 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1492 /* Poll for buffer manager start indication */
1493 for (i = 0; i < BGE_TIMEOUT; i++) {
1494 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1499 if (i == BGE_TIMEOUT) {
1500 if_printf(&sc->arpcom.ac_if,
1501 "buffer manager failed to start\n");
1505 /* Enable flow-through queues */
1506 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1507 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1509 /* Wait until queue initialization is complete */
1510 for (i = 0; i < BGE_TIMEOUT; i++) {
1511 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1516 if (i == BGE_TIMEOUT) {
1517 if_printf(&sc->arpcom.ac_if,
1518 "flow-through queue init failed\n");
1523 * Summary of rings supported by the controller:
1525 * Standard Receive Producer Ring
1526 * - This ring is used to feed receive buffers for "standard"
1527 * sized frames (typically 1536 bytes) to the controller.
1529 * Jumbo Receive Producer Ring
1530 * - This ring is used to feed receive buffers for jumbo sized
1531 * frames (i.e. anything bigger than the "standard" frames)
1532 * to the controller.
1534 * Mini Receive Producer Ring
1535 * - This ring is used to feed receive buffers for "mini"
1536 * sized frames to the controller.
1537 * - This feature required external memory for the controller
1538 * but was never used in a production system. Should always
1541 * Receive Return Ring
1542 * - After the controller has placed an incoming frame into a
1543 * receive buffer that buffer is moved into a receive return
1544 * ring. The driver is then responsible to passing the
1545 * buffer up to the stack. Many versions of the controller
1546 * support multiple RR rings.
1549 * - This ring is used for outgoing frames. Many versions of
1550 * the controller support multiple send rings.
1553 /* Initialize the standard receive producer ring control block. */
1554 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1555 rcb->bge_hostaddr.bge_addr_lo =
1556 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1557 rcb->bge_hostaddr.bge_addr_hi =
1558 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1559 if (BGE_IS_5705_PLUS(sc)) {
1561 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1562 * Bits 15-2 : Reserved (should be 0)
1563 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
1566 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1569 * Ring size is always XXX entries
1570 * Bits 31-16: Maximum RX frame size
1571 * Bits 15-2 : Reserved (should be 0)
1572 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled
1575 rcb->bge_maxlen_flags =
1576 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1578 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1579 /* Write the standard receive producer ring control block. */
1580 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1581 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1582 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1583 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1584 /* Reset the standard receive producer ring producer index. */
1585 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1588 * Initialize the jumbo RX producer ring control
1589 * block. We set the 'ring disabled' bit in the
1590 * flags field until we're actually ready to start
1591 * using this ring (i.e. once we set the MTU
1592 * high enough to require it).
1594 if (BGE_IS_JUMBO_CAPABLE(sc)) {
1595 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1596 /* Get the jumbo receive producer ring RCB parameters. */
1597 rcb->bge_hostaddr.bge_addr_lo =
1598 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1599 rcb->bge_hostaddr.bge_addr_hi =
1600 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1601 rcb->bge_maxlen_flags =
1602 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1603 BGE_RCB_FLAG_RING_DISABLED);
1604 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1605 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1606 rcb->bge_hostaddr.bge_addr_hi);
1607 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1608 rcb->bge_hostaddr.bge_addr_lo);
1609 /* Program the jumbo receive producer ring RCB parameters. */
1610 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1611 rcb->bge_maxlen_flags);
1612 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1613 /* Reset the jumbo receive producer ring producer index. */
1614 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1617 /* Disable the mini receive producer ring RCB. */
1618 if (BGE_IS_5700_FAMILY(sc)) {
1619 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1620 rcb->bge_maxlen_flags =
1621 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1622 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1623 rcb->bge_maxlen_flags);
1624 /* Reset the mini receive producer ring producer index. */
1625 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1628 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
1629 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
1630 (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
1631 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
1632 sc->bge_chipid == BGE_CHIPID_BCM5906_A2)) {
1633 CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
1634 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
1638 * The BD ring replenish thresholds control how often the
1639 * hardware fetches new BD's from the producer rings in host
1640 * memory. Setting the value too low on a busy system can
1641 * starve the hardware and recue the throughpout.
1643 * Set the BD ring replentish thresholds. The recommended
1644 * values are 1/8th the number of descriptors allocated to
1647 if (BGE_IS_5705_PLUS(sc))
1650 val = BGE_STD_RX_RING_CNT / 8;
1651 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1652 if (BGE_IS_JUMBO_CAPABLE(sc)) {
1653 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1654 BGE_JUMBO_RX_RING_CNT/8);
1658 * Disable all send rings by setting the 'ring disabled' bit
1659 * in the flags field of all the TX send ring control blocks,
1660 * located in NIC memory.
1662 if (!BGE_IS_5705_PLUS(sc)) {
1663 /* 5700 to 5704 had 16 send rings. */
1664 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
1668 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1669 for (i = 0; i < limit; i++) {
1670 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1671 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1672 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1673 vrcb += sizeof(struct bge_rcb);
1676 /* Configure send ring RCB 0 (we use only the first ring) */
1677 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1678 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1679 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1680 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1681 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1682 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1683 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1684 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1687 * Disable all receive return rings by setting the
1688 * 'ring diabled' bit in the flags field of all the receive
1689 * return ring control blocks, located in NIC memory.
1691 if (!BGE_IS_5705_PLUS(sc))
1692 limit = BGE_RX_RINGS_MAX;
1693 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755)
1697 /* Disable all receive return rings. */
1698 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1699 for (i = 0; i < limit; i++) {
1700 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1701 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1702 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1703 BGE_RCB_FLAG_RING_DISABLED);
1704 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1705 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
1706 (i * (sizeof(uint64_t))), 0);
1707 vrcb += sizeof(struct bge_rcb);
1711 * Set up receive return ring 0. Note that the NIC address
1712 * for RX return rings is 0x0. The return rings live entirely
1713 * within the host, so the nicaddr field in the RCB isn't used.
1715 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1716 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1717 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1718 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1719 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1720 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1721 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1723 /* Set random backoff seed for TX */
1724 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1725 (sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1726 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1727 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5]) &
1728 BGE_TX_BACKOFF_SEED_MASK);
1730 /* Set inter-packet gap */
1731 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1734 * Specify which ring to use for packets that don't match
1737 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1740 * Configure number of RX lists. One interrupt distribution
1741 * list, sixteen active lists, one bad frames class.
1743 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1745 /* Inialize RX list placement stats mask. */
1746 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1747 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1749 /* Disable host coalescing until we get it set up */
1750 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1752 /* Poll to make sure it's shut down. */
1753 for (i = 0; i < BGE_TIMEOUT; i++) {
1754 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1759 if (i == BGE_TIMEOUT) {
1760 if_printf(&sc->arpcom.ac_if,
1761 "host coalescing engine failed to idle\n");
1765 /* Set up host coalescing defaults */
1766 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1767 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1768 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_coal_bds);
1769 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_coal_bds);
1770 if (!BGE_IS_5705_PLUS(sc)) {
1771 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT,
1772 sc->bge_rx_coal_ticks_int);
1773 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT,
1774 sc->bge_tx_coal_ticks_int);
1778 * The datasheet (57XX-PG105-R) says BCM5705+ do not
1779 * have following two registers; obviously it is wrong.
1781 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, sc->bge_rx_coal_bds_int);
1782 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, sc->bge_tx_coal_bds_int);
1784 /* Set up address of statistics block */
1785 if (!BGE_IS_5705_PLUS(sc)) {
1786 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1787 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1788 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1789 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1791 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1792 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1793 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1796 /* Set up address of status block */
1797 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
1798 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1799 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1800 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1801 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1804 * Set up status block partail update size.
1806 * Because only single TX ring, RX produce ring and Rx return ring
1807 * are used, ask device to update only minimum part of status block
1808 * except for BCM5700 AX/BX, whose status block partial update size
1809 * can't be configured.
1811 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1812 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
1813 /* XXX Actually reserved on BCM5700 AX/BX */
1814 val = BGE_STATBLKSZ_FULL;
1816 val = BGE_STATBLKSZ_32BYTE;
1820 * Does not seem to have visible effect in both
1821 * bulk data (1472B UDP datagram) and tiny data
1822 * (18B UDP datagram) TX tests.
1824 if (!BGE_IS_CRIPPLED(sc))
1825 val |= BGE_HCCMODE_CLRTICK_TX;
1828 /* Turn on host coalescing state machine */
1829 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1831 /* Turn on RX BD completion state machine and enable attentions */
1832 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1833 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1835 /* Turn on RX list placement state machine */
1836 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1838 /* Turn on RX list selector state machine. */
1839 if (!BGE_IS_5705_PLUS(sc))
1840 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1842 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1843 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1844 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1845 BGE_MACMODE_FRMHDR_DMA_ENB;
1847 if (sc->bge_flags & BGE_FLAG_TBI)
1848 val |= BGE_PORTMODE_TBI;
1849 else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
1850 val |= BGE_PORTMODE_GMII;
1852 val |= BGE_PORTMODE_MII;
1854 /* Allow APE to send/receive frames. */
1855 if (sc->bge_mfw_flags & BGE_MFW_ON_APE)
1856 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
1858 /* Turn on DMA, clear stats */
1859 CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1862 /* Set misc. local control, enable interrupts on attentions */
1863 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1866 /* Assert GPIO pins for PHY reset */
1867 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1868 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1869 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1870 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1873 /* Turn on DMA completion state machine */
1874 if (!BGE_IS_5705_PLUS(sc))
1875 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1877 /* Turn on write DMA state machine */
1878 val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1879 if (BGE_IS_5755_PLUS(sc)) {
1880 /* Enable host coalescing bug fix. */
1881 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1883 if (sc->bge_asicrev == BGE_ASICREV_BCM5785) {
1884 /* Request larger DMA burst size to get better performance. */
1885 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1887 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1890 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
1891 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1892 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1893 sc->bge_asicrev == BGE_ASICREV_BCM57780) {
1895 * Enable fix for read DMA FIFO overruns.
1896 * The fix is to limit the number of RX BDs
1897 * the hardware would fetch at a fime.
1899 val = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
1900 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL,
1901 val| BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
1904 /* Turn on read DMA state machine */
1905 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1906 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
1907 sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
1908 sc->bge_asicrev == BGE_ASICREV_BCM57780)
1909 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1910 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1911 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1912 if (sc->bge_flags & BGE_FLAG_PCIE)
1913 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1914 if (sc->bge_flags & BGE_FLAG_TSO)
1915 val |= BGE_RDMAMODE_TSO4_ENABLE;
1916 CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1919 /* Turn on RX data completion state machine */
1920 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1922 /* Turn on RX BD initiator state machine */
1923 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1925 /* Turn on RX data and RX BD initiator state machine */
1926 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1928 /* Turn on Mbuf cluster free state machine */
1929 if (!BGE_IS_5705_PLUS(sc))
1930 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1932 /* Turn on send BD completion state machine */
1933 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1935 /* Turn on send data completion state machine */
1936 val = BGE_SDCMODE_ENABLE;
1937 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
1938 val |= BGE_SDCMODE_CDELAY;
1939 CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1941 /* Turn on send data initiator state machine */
1942 if (sc->bge_flags & BGE_FLAG_TSO)
1943 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
1944 BGE_SDIMODE_HW_LSO_PRE_DMA);
1946 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1948 /* Turn on send BD initiator state machine */
1949 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1951 /* Turn on send BD selector state machine */
1952 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1954 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1955 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1956 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1958 /* ack/clear link change events */
1959 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1960 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1961 BGE_MACSTAT_LINK_CHANGED);
1962 CSR_WRITE_4(sc, BGE_MI_STS, 0);
1965 * Enable attention when the link has changed state for
1966 * devices that use auto polling.
1968 if (sc->bge_flags & BGE_FLAG_TBI) {
1969 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1971 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
1972 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1975 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1976 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1977 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1978 BGE_EVTENB_MI_INTERRUPT);
1983 * Clear any pending link state attention.
1984 * Otherwise some link state change events may be lost until attention
1985 * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1986 * It's not necessary on newer BCM chips - perhaps enabling link
1987 * state change attentions implies clearing pending attention.
1989 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1990 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1991 BGE_MACSTAT_LINK_CHANGED);
1993 /* Enable link state change attentions. */
1994 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
2000 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
2001 * against our list and return its name if we find a match. Note
2002 * that since the Broadcom controller contains VPD support, we
2003 * can get the device name string from the controller itself instead
2004 * of the compiled-in string. This is a little slow, but it guarantees
2005 * we'll always announce the right product name.
2008 bge_probe(device_t dev)
2010 const struct bge_type *t;
2011 uint16_t product, vendor;
2013 product = pci_get_device(dev);
2014 vendor = pci_get_vendor(dev);
2016 for (t = bge_devs; t->bge_name != NULL; t++) {
2017 if (vendor == t->bge_vid && product == t->bge_did)
2020 if (t->bge_name == NULL)
2023 device_set_desc(dev, t->bge_name);
2028 bge_attach(device_t dev)
2031 struct bge_softc *sc;
2032 struct sysctl_ctx_list *ctx;
2033 struct sysctl_oid *tree;
2034 uint32_t hwcfg = 0, misccfg;
2035 int error = 0, rid, capmask;
2036 uint8_t ether_addr[ETHER_ADDR_LEN];
2037 uint16_t product, vendor;
2038 driver_intr_t *intr_func;
2039 uintptr_t mii_priv = 0;
2043 sc = device_get_softc(dev);
2045 callout_init_mp(&sc->bge_stat_timer);
2046 lwkt_serialize_init(&sc->bge_jslot_serializer);
2048 sc->bge_func_addr = pci_get_function(dev);
2049 product = pci_get_device(dev);
2050 vendor = pci_get_vendor(dev);
2052 #ifndef BURN_BRIDGES
2053 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
2056 irq = pci_read_config(dev, PCIR_INTLINE, 4);
2057 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
2059 device_printf(dev, "chip is in D%d power mode "
2060 "-- setting to D0\n", pci_get_powerstate(dev));
2062 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
2064 pci_write_config(dev, PCIR_INTLINE, irq, 4);
2065 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
2067 #endif /* !BURN_BRIDGE */
2070 * Map control/status registers.
2072 pci_enable_busmaster(dev);
2075 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2078 if (sc->bge_res == NULL) {
2079 device_printf(dev, "couldn't map memory\n");
2083 sc->bge_btag = rman_get_bustag(sc->bge_res);
2084 sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
2086 /* Save various chip information */
2088 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2089 BGE_PCIMISCCTL_ASICREV_SHIFT;
2090 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) {
2091 /* All chips, which use BGE_PCI_PRODID_ASICREV, have CPMU */
2092 sc->bge_flags |= BGE_FLAG_CPMU;
2093 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
2095 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
2096 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
2098 /* Save chipset family. */
2099 switch (sc->bge_asicrev) {
2100 case BGE_ASICREV_BCM5755:
2101 case BGE_ASICREV_BCM5761:
2102 case BGE_ASICREV_BCM5784:
2103 case BGE_ASICREV_BCM5785:
2104 case BGE_ASICREV_BCM5787:
2105 case BGE_ASICREV_BCM57780:
2106 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
2110 case BGE_ASICREV_BCM5700:
2111 case BGE_ASICREV_BCM5701:
2112 case BGE_ASICREV_BCM5703:
2113 case BGE_ASICREV_BCM5704:
2114 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
2117 case BGE_ASICREV_BCM5714_A0:
2118 case BGE_ASICREV_BCM5780:
2119 case BGE_ASICREV_BCM5714:
2120 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
2123 case BGE_ASICREV_BCM5750:
2124 case BGE_ASICREV_BCM5752:
2125 case BGE_ASICREV_BCM5906:
2126 sc->bge_flags |= BGE_FLAG_575X_PLUS;
2129 case BGE_ASICREV_BCM5705:
2130 sc->bge_flags |= BGE_FLAG_5705_PLUS;
2134 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
2135 sc->bge_flags |= BGE_FLAG_NO_EEPROM;
2137 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
2138 sc->bge_flags |= BGE_FLAG_APE;
2140 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
2141 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2142 (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
2143 misccfg == BGE_MISCCFG_BOARD_ID_5788M))
2144 sc->bge_flags |= BGE_FLAG_5788;
2146 /* BCM5755 or higher and BCM5906 have short DMA bug. */
2147 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
2148 sc->bge_flags |= BGE_FLAG_SHORTDMA;
2151 * Increase STD RX ring prod index by at most 8 for BCM5750,
2152 * BCM5752 and BCM5755 to workaround hardware errata.
2154 if (sc->bge_asicrev == BGE_ASICREV_BCM5750 ||
2155 sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2156 sc->bge_asicrev == BGE_ASICREV_BCM5755)
2157 sc->bge_rx_wreg = 8;
2160 * Check if this is a PCI-X or PCI Express device.
2162 if (BGE_IS_5705_PLUS(sc)) {
2163 if (pci_is_pcie(dev)) {
2164 sc->bge_flags |= BGE_FLAG_PCIE;
2165 sc->bge_pciecap = pci_get_pciecap_ptr(sc->bge_dev);
2166 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
2170 * Check if the device is in PCI-X Mode.
2171 * (This bit is not valid on PCI Express controllers.)
2173 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
2174 BGE_PCISTATE_PCI_BUSMODE) == 0) {
2175 sc->bge_flags |= BGE_FLAG_PCIX;
2176 sc->bge_pcixcap = pci_get_pcixcap_ptr(sc->bge_dev);
2177 sc->bge_mbox_reorder = device_getenv_int(sc->bge_dev,
2181 device_printf(dev, "CHIP ID 0x%08x; "
2182 "ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
2183 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
2184 (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X"
2185 : ((sc->bge_flags & BGE_FLAG_PCIE) ?
2189 * The 40bit DMA bug applies to the 5714/5715 controllers and is
2190 * not actually a MAC controller bug but an issue with the embedded
2191 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
2193 if ((sc->bge_flags & BGE_FLAG_PCIX) &&
2194 (BGE_IS_5714_FAMILY(sc) || device_getenv_int(dev, "dma40b", 0)))
2195 sc->bge_flags |= BGE_FLAG_MAXADDR_40BIT;
2198 * When using the BCM5701 in PCI-X mode, data corruption has
2199 * been observed in the first few bytes of some received packets.
2200 * Aligning the packet buffer in memory eliminates the corruption.
2201 * Unfortunately, this misaligns the packet payloads. On platforms
2202 * which do not support unaligned accesses, we will realign the
2203 * payloads by copying the received packets.
2205 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
2206 (sc->bge_flags & BGE_FLAG_PCIX))
2207 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
2209 if (!BGE_IS_CRIPPLED(sc)) {
2210 if (device_getenv_int(dev, "status_tag", 1)) {
2211 sc->bge_flags |= BGE_FLAG_STATUS_TAG;
2212 sc->bge_pci_miscctl = BGE_PCIMISCCTL_TAGGED_STATUS;
2214 device_printf(dev, "enable status tag\n");
2218 if (BGE_IS_5755_PLUS(sc)) {
2220 * BCM5754 and BCM5787 shares the same ASIC id so
2221 * explicit device id check is required.
2222 * Due to unknown reason TSO does not work on BCM5755M.
2224 if (product != PCI_PRODUCT_BROADCOM_BCM5754 &&
2225 product != PCI_PRODUCT_BROADCOM_BCM5754M &&
2226 product != PCI_PRODUCT_BROADCOM_BCM5755M)
2227 sc->bge_flags |= BGE_FLAG_TSO;
2231 * Set various PHY quirk flags.
2234 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2235 sc->bge_asicrev == BGE_ASICREV_BCM5701) &&
2236 pci_get_subvendor(dev) == PCI_VENDOR_DELL)
2237 mii_priv |= BRGPHY_FLAG_NO_3LED;
2239 capmask = MII_CAPMASK_DEFAULT;
2240 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
2241 (misccfg == 0x4000 || misccfg == 0x8000)) ||
2242 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2243 vendor == PCI_VENDOR_BROADCOM &&
2244 (product == PCI_PRODUCT_BROADCOM_BCM5901 ||
2245 product == PCI_PRODUCT_BROADCOM_BCM5901A2 ||
2246 product == PCI_PRODUCT_BROADCOM_BCM5705F)) ||
2247 (vendor == PCI_VENDOR_BROADCOM &&
2248 (product == PCI_PRODUCT_BROADCOM_BCM5751F ||
2249 product == PCI_PRODUCT_BROADCOM_BCM5753F ||
2250 product == PCI_PRODUCT_BROADCOM_BCM5787F)) ||
2251 product == PCI_PRODUCT_BROADCOM_BCM57790 ||
2252 sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2254 capmask &= ~BMSR_EXTSTAT;
2257 mii_priv |= BRGPHY_FLAG_WIRESPEED;
2258 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
2259 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
2260 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
2261 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
2262 sc->bge_asicrev == BGE_ASICREV_BCM5906)
2263 mii_priv &= ~BRGPHY_FLAG_WIRESPEED;
2265 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
2266 sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
2267 mii_priv |= BRGPHY_FLAG_CRC_BUG;
2269 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
2270 sc->bge_chiprev == BGE_CHIPREV_5704_AX)
2271 mii_priv |= BRGPHY_FLAG_ADC_BUG;
2273 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
2274 mii_priv |= BRGPHY_FLAG_5704_A0;
2276 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
2277 mii_priv |= BRGPHY_FLAG_5906;
2279 if (BGE_IS_5705_PLUS(sc) &&
2280 sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
2281 /* sc->bge_asicrev != BGE_ASICREV_BCM5717 && */
2282 sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
2283 /* sc->bge_asicrev != BGE_ASICREV_BCM57765 && */
2284 sc->bge_asicrev != BGE_ASICREV_BCM57780) {
2285 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2286 sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2287 sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2288 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2289 if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
2290 product != PCI_PRODUCT_BROADCOM_BCM5756)
2291 mii_priv |= BRGPHY_FLAG_JITTER_BUG;
2292 if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
2293 mii_priv |= BRGPHY_FLAG_ADJUST_TRIM;
2295 mii_priv |= BRGPHY_FLAG_BER_BUG;
2300 * Chips with APE need BAR2 access for APE registers/memory.
2302 if (sc->bge_flags & BGE_FLAG_APE) {
2306 sc->bge_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
2308 if (sc->bge_res2 == NULL) {
2309 device_printf(dev, "couldn't map BAR2 memory\n");
2314 /* Enable APE register/memory access by host driver. */
2315 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2316 pcistate |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
2317 BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
2318 BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
2319 pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4);
2321 bge_ape_lock_init(sc);
2322 bge_ape_read_fw_ver(sc);
2326 * Allocate interrupt
2328 msi_enable = bge_msi_enable;
2329 if ((sc->bge_flags & BGE_FLAG_STATUS_TAG) == 0) {
2330 /* If "tagged status" is disabled, don't enable MSI */
2332 } else if (msi_enable) {
2333 msi_enable = 0; /* Disable by default */
2334 if (BGE_IS_575X_PLUS(sc)) {
2336 /* XXX we filter all 5714 chips */
2337 if (sc->bge_asicrev == BGE_ASICREV_BCM5714 ||
2338 (sc->bge_asicrev == BGE_ASICREV_BCM5750 &&
2339 (sc->bge_chiprev == BGE_CHIPREV_5750_AX ||
2340 sc->bge_chiprev == BGE_CHIPREV_5750_BX)))
2342 else if (BGE_IS_5755_PLUS(sc) ||
2343 sc->bge_asicrev == BGE_ASICREV_BCM5906)
2344 sc->bge_flags |= BGE_FLAG_ONESHOT_MSI;
2348 if (pci_find_extcap(dev, PCIY_MSI, &sc->bge_msicap)) {
2349 device_printf(dev, "no MSI capability\n");
2354 sc->bge_irq_type = pci_alloc_1intr(dev, msi_enable, &sc->bge_irq_rid,
2357 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->bge_irq_rid,
2359 if (sc->bge_irq == NULL) {
2360 device_printf(dev, "couldn't map interrupt\n");
2365 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI)
2368 sc->bge_flags &= ~BGE_FLAG_ONESHOT_MSI;
2370 /* Initialize if_name earlier, so if_printf could be used */
2371 ifp = &sc->arpcom.ac_if;
2372 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2374 sc->bge_asf_mode = 0;
2375 /* No ASF if APE present. */
2376 if ((sc->bge_flags & BGE_FLAG_APE) == 0) {
2377 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) ==
2378 BGE_SRAM_DATA_SIG_MAGIC)) {
2379 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) &
2381 sc->bge_asf_mode |= ASF_ENABLE;
2382 sc->bge_asf_mode |= ASF_STACKUP;
2383 if (BGE_IS_575X_PLUS(sc))
2384 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
2390 * Try to reset the chip.
2393 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
2395 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
2396 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
2398 if (bge_chipinit(sc)) {
2399 device_printf(dev, "chip initialization failed\n");
2405 * Get station address
2407 error = bge_get_eaddr(sc, ether_addr);
2409 device_printf(dev, "failed to read station address\n");
2413 /* 5705/5750 limits RX return ring to 512 entries. */
2414 if (BGE_IS_5705_PLUS(sc))
2415 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2417 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2419 error = bge_dma_alloc(sc);
2423 /* Set default tuneable values. */
2424 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
2425 sc->bge_rx_coal_ticks = BGE_RX_COAL_TICKS_DEF;
2426 sc->bge_tx_coal_ticks = BGE_TX_COAL_TICKS_DEF;
2427 sc->bge_rx_coal_bds = BGE_RX_COAL_BDS_DEF;
2428 sc->bge_tx_coal_bds = BGE_TX_COAL_BDS_DEF;
2429 if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
2430 sc->bge_rx_coal_ticks_int = BGE_RX_COAL_TICKS_DEF;
2431 sc->bge_tx_coal_ticks_int = BGE_TX_COAL_TICKS_DEF;
2432 sc->bge_rx_coal_bds_int = BGE_RX_COAL_BDS_DEF;
2433 sc->bge_tx_coal_bds_int = BGE_TX_COAL_BDS_DEF;
2435 sc->bge_rx_coal_ticks_int = BGE_RX_COAL_TICKS_MIN;
2436 sc->bge_tx_coal_ticks_int = BGE_TX_COAL_TICKS_MIN;
2437 sc->bge_rx_coal_bds_int = BGE_RX_COAL_BDS_MIN;
2438 sc->bge_tx_coal_bds_int = BGE_TX_COAL_BDS_MIN;
2440 sc->bge_tx_wreg = BGE_TX_WREG_NSEGS;
2442 /* Set up TX spare and reserved descriptor count */
2443 if (sc->bge_flags & BGE_FLAG_TSO) {
2444 sc->bge_txspare = BGE_NSEG_SPARE_TSO;
2445 sc->bge_txrsvd = BGE_NSEG_RSVD_TSO;
2447 sc->bge_txspare = BGE_NSEG_SPARE;
2448 sc->bge_txrsvd = BGE_NSEG_RSVD;
2451 /* Set up ifnet structure */
2453 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2454 ifp->if_ioctl = bge_ioctl;
2455 ifp->if_start = bge_start;
2456 #ifdef IFPOLL_ENABLE
2457 ifp->if_npoll = bge_npoll;
2459 ifp->if_watchdog = bge_watchdog;
2460 ifp->if_init = bge_init;
2461 ifp->if_mtu = ETHERMTU;
2462 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2463 ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
2464 ifq_set_ready(&ifp->if_snd);
2467 * 5700 B0 chips do not support checksumming correctly due
2470 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
2471 ifp->if_capabilities |= IFCAP_HWCSUM;
2472 ifp->if_hwassist |= BGE_CSUM_FEATURES;
2474 if (sc->bge_flags & BGE_FLAG_TSO) {
2475 ifp->if_capabilities |= IFCAP_TSO;
2476 ifp->if_hwassist |= CSUM_TSO;
2478 ifp->if_capenable = ifp->if_capabilities;
2481 * Figure out what sort of media we have by checking the
2482 * hardware config word in the first 32k of NIC internal memory,
2483 * or fall back to examining the EEPROM if necessary.
2484 * Note: on some BCM5700 cards, this value appears to be unset.
2485 * If that's the case, we have to rely on identifying the NIC
2486 * by its PCI subsystem ID, as we do below for the SysKonnect
2489 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC) {
2490 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG);
2492 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2494 device_printf(dev, "failed to read EEPROM\n");
2498 hwcfg = ntohl(hwcfg);
2501 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2502 if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
2503 (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
2504 if (BGE_IS_5714_FAMILY(sc))
2505 sc->bge_flags |= BGE_FLAG_MII_SERDES;
2507 sc->bge_flags |= BGE_FLAG_TBI;
2511 if (sc->bge_flags & BGE_FLAG_CPMU)
2512 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
2514 sc->bge_mi_mode = BGE_MIMODE_BASE;
2515 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705) {
2516 /* Enable auto polling for BCM570[0-5]. */
2517 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
2520 /* Setup link status update stuffs */
2521 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2522 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
2523 sc->bge_link_upd = bge_bcm5700_link_upd;
2524 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
2525 } else if (sc->bge_flags & BGE_FLAG_TBI) {
2526 sc->bge_link_upd = bge_tbi_link_upd;
2527 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2528 } else if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2529 sc->bge_link_upd = bge_autopoll_link_upd;
2530 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2532 sc->bge_link_upd = bge_copper_link_upd;
2533 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
2537 * Broadcom's own driver always assumes the internal
2538 * PHY is at GMII address 1. On some chips, the PHY responds
2539 * to accesses at all addresses, which could cause us to
2540 * bogusly attach the PHY 32 times at probe type. Always
2541 * restricting the lookup to address 1 is simpler than
2542 * trying to figure out which chips revisions should be
2547 if (sc->bge_flags & BGE_FLAG_TBI) {
2548 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
2549 bge_ifmedia_upd, bge_ifmedia_sts);
2550 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2551 ifmedia_add(&sc->bge_ifmedia,
2552 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2553 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2554 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
2555 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
2557 struct mii_probe_args mii_args;
2561 * Do transceiver setup and tell the firmware the
2562 * driver is down so we can try to get access the
2563 * probe if ASF is running. Retry a couple of times
2564 * if we get a conflict with the ASF firmware accessing
2568 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2570 bge_asf_driver_up(sc);
2572 mii_probe_args_init(&mii_args, bge_ifmedia_upd, bge_ifmedia_sts);
2573 mii_args.mii_probemask = 1 << sc->bge_phyno;
2574 mii_args.mii_capmask = capmask;
2575 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
2576 mii_args.mii_priv = mii_priv;
2578 error = mii_probe(dev, &sc->bge_miibus, &mii_args);
2581 device_printf(sc->bge_dev, "Probe MII again\n");
2582 bge_miibus_writereg(sc->bge_dev,
2583 sc->bge_phyno, MII_BMCR, BMCR_RESET);
2586 device_printf(dev, "MII without any PHY!\n");
2591 * Now tell the firmware we are going up after probing the PHY
2593 if (sc->bge_asf_mode & ASF_STACKUP)
2594 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2597 ctx = device_get_sysctl_ctx(sc->bge_dev);
2598 tree = device_get_sysctl_tree(sc->bge_dev);
2600 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "rx_coal_ticks",
2601 CTLTYPE_INT | CTLFLAG_RW,
2602 sc, 0, bge_sysctl_rx_coal_ticks, "I",
2603 "Receive coalescing ticks (usec).");
2604 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_coal_ticks",
2605 CTLTYPE_INT | CTLFLAG_RW,
2606 sc, 0, bge_sysctl_tx_coal_ticks, "I",
2607 "Transmit coalescing ticks (usec).");
2608 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "rx_coal_bds",
2609 CTLTYPE_INT | CTLFLAG_RW,
2610 sc, 0, bge_sysctl_rx_coal_bds, "I",
2611 "Receive max coalesced BD count.");
2612 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_coal_bds",
2613 CTLTYPE_INT | CTLFLAG_RW,
2614 sc, 0, bge_sysctl_tx_coal_bds, "I",
2615 "Transmit max coalesced BD count.");
2617 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_wreg", CTLFLAG_RW,
2618 &sc->bge_tx_wreg, 0,
2619 "# of segments before writing to hardware register");
2621 if (sc->bge_flags & BGE_FLAG_PCIE) {
2623 * A common design characteristic for many Broadcom
2624 * client controllers is that they only support a
2625 * single outstanding DMA read operation on the PCIe
2626 * bus. This means that it will take twice as long to
2627 * fetch a TX frame that is split into header and
2628 * payload buffers as it does to fetch a single,
2629 * contiguous TX frame (2 reads vs. 1 read). For these
2630 * controllers, coalescing buffers to reduce the number
2631 * of memory reads is effective way to get maximum
2632 * performance(about 940Mbps). Without collapsing TX
2633 * buffers the maximum TCP bulk transfer performance
2634 * is about 850Mbps. However forcing coalescing mbufs
2635 * consumes a lot of CPU cycles, so leave it off by
2638 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
2639 "force_defrag", CTLFLAG_RW,
2640 &sc->bge_force_defrag, 0,
2641 "Force defragment on TX path");
2643 if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
2644 if (!BGE_IS_5705_PLUS(sc)) {
2645 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
2646 "rx_coal_ticks_int", CTLTYPE_INT | CTLFLAG_RW,
2647 sc, 0, bge_sysctl_rx_coal_ticks_int, "I",
2648 "Receive coalescing ticks "
2649 "during interrupt (usec).");
2650 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
2651 "tx_coal_ticks_int", CTLTYPE_INT | CTLFLAG_RW,
2652 sc, 0, bge_sysctl_tx_coal_ticks_int, "I",
2653 "Transmit coalescing ticks "
2654 "during interrupt (usec).");
2656 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
2657 "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2658 sc, 0, bge_sysctl_rx_coal_bds_int, "I",
2659 "Receive max coalesced BD count during interrupt.");
2660 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
2661 "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2662 sc, 0, bge_sysctl_tx_coal_bds_int, "I",
2663 "Transmit max coalesced BD count during interrupt.");
2667 * Call MI attach routine.
2669 ether_ifattach(ifp, ether_addr, NULL);
2671 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->bge_irq));
2673 #ifdef IFPOLL_ENABLE
2675 ifpoll_compat_setup(&sc->bge_npoll, ctx, tree,
2676 device_get_unit(dev), ifp->if_serializer);
2679 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) {
2680 if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) {
2681 intr_func = bge_msi_oneshot;
2683 device_printf(dev, "oneshot MSI\n");
2685 intr_func = bge_msi;
2687 } else if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
2688 intr_func = bge_intr_legacy;
2690 intr_func = bge_intr_crippled;
2692 error = bus_setup_intr(dev, sc->bge_irq, INTR_MPSAFE, intr_func, sc,
2693 &sc->bge_intrhand, ifp->if_serializer);
2695 ether_ifdetach(ifp);
2696 device_printf(dev, "couldn't set up irq\n");
2707 bge_detach(device_t dev)
2709 struct bge_softc *sc = device_get_softc(dev);
2711 if (device_is_attached(dev)) {
2712 struct ifnet *ifp = &sc->arpcom.ac_if;
2714 lwkt_serialize_enter(ifp->if_serializer);
2716 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
2717 lwkt_serialize_exit(ifp->if_serializer);
2719 ether_ifdetach(ifp);
2722 if (sc->bge_flags & BGE_FLAG_TBI)
2723 ifmedia_removeall(&sc->bge_ifmedia);
2725 device_delete_child(dev, sc->bge_miibus);
2726 bus_generic_detach(dev);
2728 if (sc->bge_irq != NULL) {
2729 bus_release_resource(dev, SYS_RES_IRQ, sc->bge_irq_rid,
2732 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI)
2733 pci_release_msi(dev);
2735 if (sc->bge_res != NULL) {
2736 bus_release_resource(dev, SYS_RES_MEMORY,
2737 BGE_PCI_BAR0, sc->bge_res);
2739 if (sc->bge_res2 != NULL) {
2740 bus_release_resource(dev, SYS_RES_MEMORY,
2741 PCIR_BAR(2), sc->bge_res2);
2750 bge_reset(struct bge_softc *sc)
2752 device_t dev = sc->bge_dev;
2753 uint32_t cachesize, command, reset, mac_mode, mac_mode_mask;
2754 void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
2757 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE;
2758 if (sc->bge_mfw_flags & BGE_MFW_ON_APE)
2759 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
2760 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask;
2762 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
2763 sc->bge_asicrev != BGE_ASICREV_BCM5906) {
2764 if (sc->bge_flags & BGE_FLAG_PCIE)
2765 write_op = bge_writemem_direct;
2767 write_op = bge_writemem_ind;
2769 write_op = bge_writereg_ind;
2772 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
2773 sc->bge_asicrev != BGE_ASICREV_BCM5701) {
2774 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
2775 for (i = 0; i < 8000; i++) {
2776 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) &
2777 BGE_NVRAMSWARB_GNT1)
2783 if_printf(&sc->arpcom.ac_if,
2784 "NVRAM lock timedout!\n");
2788 /* Take APE lock when performing reset. */
2789 bge_ape_lock(sc, BGE_APE_LOCK_GRC);
2791 /* Save some important PCI state. */
2792 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2793 command = pci_read_config(dev, BGE_PCI_CMD, 4);
2795 pci_write_config(dev, BGE_PCI_MISC_CTL,
2796 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2797 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2798 sc->bge_pci_miscctl, 4);
2800 /* Disable fastboot on controllers that support it. */
2801 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2802 BGE_IS_5755_PLUS(sc)) {
2804 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2805 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2809 * Write the magic number to SRAM at offset 0xB50.
2810 * When firmware finishes its initialization it will
2811 * write ~BGE_SRAM_FW_MB_MAGIC to the same location.
2813 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
2815 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2817 /* XXX: Broadcom Linux driver. */
2818 if (sc->bge_flags & BGE_FLAG_PCIE) {
2819 /* Force PCI-E 1.0a mode */
2820 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
2821 CSR_READ_4(sc, BGE_PCIE_PHY_TSTCTL) ==
2822 (BGE_PCIE_PHY_TSTCTL_PSCRAM |
2823 BGE_PCIE_PHY_TSTCTL_PCIE10)) {
2824 CSR_WRITE_4(sc, BGE_PCIE_PHY_TSTCTL,
2825 BGE_PCIE_PHY_TSTCTL_PSCRAM);
2827 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2828 /* Prevent PCIE link training during global reset */
2829 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2834 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2835 uint32_t status, ctrl;
2837 status = CSR_READ_4(sc, BGE_VCPU_STATUS);
2838 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2839 status | BGE_VCPU_STATUS_DRV_RESET);
2840 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2841 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2842 ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2846 * Set GPHY Power Down Override to leave GPHY
2847 * powered up in D0 uninitialized.
2849 if (BGE_IS_5705_PLUS(sc) && (sc->bge_flags & BGE_FLAG_CPMU) == 0)
2850 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
2852 /* Issue global reset */
2853 write_op(sc, BGE_MISC_CFG, reset);
2855 if (sc->bge_flags & BGE_FLAG_PCIE)
2860 /* XXX: Broadcom Linux driver. */
2861 if (sc->bge_flags & BGE_FLAG_PCIE) {
2864 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2867 DELAY(500000); /* wait for link training to complete */
2868 v = pci_read_config(dev, 0xc4, 4);
2869 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2872 devctl = pci_read_config(dev,
2873 sc->bge_pciecap + PCIER_DEVCTRL, 2);
2875 /* Disable no snoop and disable relaxed ordering. */
2876 devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP);
2878 /* Old PCI-E chips only support 128 bytes Max PayLoad Size. */
2879 if ((sc->bge_flags & BGE_FLAG_CPMU) == 0) {
2880 devctl &= ~PCIEM_DEVCTL_MAX_PAYLOAD_MASK;
2881 devctl |= PCIEM_DEVCTL_MAX_PAYLOAD_128;
2884 pci_write_config(dev, sc->bge_pciecap + PCIER_DEVCTRL,
2887 /* Clear error status. */
2888 pci_write_config(dev, sc->bge_pciecap + PCIER_DEVSTS,
2889 PCIEM_DEVSTS_CORR_ERR |
2890 PCIEM_DEVSTS_NFATAL_ERR |
2891 PCIEM_DEVSTS_FATAL_ERR |
2892 PCIEM_DEVSTS_UNSUPP_REQ, 2);
2895 /* Reset some of the PCI state that got zapped by reset */
2896 pci_write_config(dev, BGE_PCI_MISC_CTL,
2897 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2898 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2899 sc->bge_pci_miscctl, 4);
2900 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE;
2901 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 &&
2902 (sc->bge_flags & BGE_FLAG_PCIX))
2903 val |= BGE_PCISTATE_RETRY_SAME_DMA;
2904 if (sc->bge_mfw_flags & BGE_MFW_ON_APE) {
2905 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
2906 BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
2907 BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
2909 pci_write_config(dev, BGE_PCI_PCISTATE, val, 4);
2910 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2911 pci_write_config(dev, BGE_PCI_CMD, command, 4);
2914 * Disable PCI-X relaxed ordering to ensure status block update
2915 * comes first then packet buffer DMA. Otherwise driver may
2916 * read stale status block.
2918 if (sc->bge_flags & BGE_FLAG_PCIX) {
2921 devctl = pci_read_config(dev,
2922 sc->bge_pcixcap + PCIXR_COMMAND, 2);
2923 devctl &= ~PCIXM_COMMAND_ERO;
2924 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
2925 devctl &= ~PCIXM_COMMAND_MAX_READ;
2926 devctl |= PCIXM_COMMAND_MAX_READ_2048;
2927 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2928 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
2929 PCIXM_COMMAND_MAX_READ);
2930 devctl |= PCIXM_COMMAND_MAX_READ_2048;
2932 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
2937 * Enable memory arbiter and re-enable MSI if necessary.
2939 if (BGE_IS_5714_FAMILY(sc)) {
2942 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) {
2944 * Resetting BCM5714 family will clear MSI
2945 * enable bit; restore it after resetting.
2947 PCI_SETBIT(sc->bge_dev, sc->bge_msicap + PCIR_MSI_CTRL,
2948 PCIM_MSICTRL_MSI_ENABLE, 2);
2949 BGE_SETBIT(sc, BGE_MSI_MODE, BGE_MSIMODE_ENABLE);
2951 val = CSR_READ_4(sc, BGE_MARB_MODE);
2952 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2954 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2957 /* Fix up byte swapping. */
2958 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2959 BGE_MODECTL_BYTESWAP_DATA);
2961 val = CSR_READ_4(sc, BGE_MAC_MODE);
2962 val = (val & ~mac_mode_mask) | mac_mode;
2963 CSR_WRITE_4(sc, BGE_MAC_MODE, val);
2966 bge_ape_unlock(sc, BGE_APE_LOCK_GRC);
2968 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2969 for (i = 0; i < BGE_TIMEOUT; i++) {
2970 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2971 if (val & BGE_VCPU_STATUS_INIT_DONE)
2975 if (i == BGE_TIMEOUT) {
2976 if_printf(&sc->arpcom.ac_if, "reset timed out\n");
2982 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
2986 * Poll until we see the 1's complement of the magic number.
2987 * This indicates that the firmware initialization
2990 for (i = 0; i < BGE_FIRMWARE_TIMEOUT; i++) {
2991 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB);
2992 if (val == ~BGE_SRAM_FW_MB_MAGIC)
2996 if (i == BGE_FIRMWARE_TIMEOUT) {
2997 if_printf(&sc->arpcom.ac_if, "firmware handshake "
2998 "timed out, found 0x%08x\n", val);
3003 * The 5704 in TBI mode apparently needs some special
3004 * adjustment to insure the SERDES drive level is set
3007 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
3008 (sc->bge_flags & BGE_FLAG_TBI)) {
3011 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
3012 serdescfg = (serdescfg & ~0xFFF) | 0x880;
3013 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
3016 /* XXX: Broadcom Linux driver. */
3017 if ((sc->bge_flags & BGE_FLAG_PCIE) &&
3018 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
3019 sc->bge_asicrev != BGE_ASICREV_BCM5785) {
3022 /* Enable Data FIFO protection. */
3023 v = CSR_READ_4(sc, BGE_PCIE_TLDLPL_PORT);
3024 CSR_WRITE_4(sc, BGE_PCIE_TLDLPL_PORT, v | (1 << 25));
3031 * Frame reception handling. This is called if there's a frame
3032 * on the receive return list.
3034 * Note: we have to be able to handle two possibilities here:
3035 * 1) the frame is from the jumbo recieve ring
3036 * 2) the frame is from the standard receive ring
3040 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int count)
3043 int stdcnt = 0, jumbocnt = 0;
3045 ifp = &sc->arpcom.ac_if;
3047 while (sc->bge_rx_saved_considx != rx_prod && count != 0) {
3048 struct bge_rx_bd *cur_rx;
3050 struct mbuf *m = NULL;
3051 uint16_t vlan_tag = 0;
3057 &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
3059 rxidx = cur_rx->bge_idx;
3060 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
3063 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
3065 vlan_tag = cur_rx->bge_vlan_tag;
3068 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
3069 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
3072 if (rxidx != sc->bge_jumbo) {
3073 IFNET_STAT_INC(ifp, ierrors, 1);
3074 if_printf(ifp, "sw jumbo index(%d) "
3075 "and hw jumbo index(%d) mismatch, drop!\n",
3076 sc->bge_jumbo, rxidx);
3077 bge_setup_rxdesc_jumbo(sc, rxidx);
3081 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx].bge_mbuf;
3082 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3083 IFNET_STAT_INC(ifp, ierrors, 1);
3084 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
3087 if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 0)) {
3088 IFNET_STAT_INC(ifp, ierrors, 1);
3089 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
3095 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
3098 if (rxidx != sc->bge_std) {
3099 IFNET_STAT_INC(ifp, ierrors, 1);
3100 if_printf(ifp, "sw std index(%d) "
3101 "and hw std index(%d) mismatch, drop!\n",
3102 sc->bge_std, rxidx);
3103 bge_setup_rxdesc_std(sc, rxidx);
3108 m = sc->bge_cdata.bge_rx_std_chain[rxidx].bge_mbuf;
3109 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
3110 IFNET_STAT_INC(ifp, ierrors, 1);
3111 bge_setup_rxdesc_std(sc, sc->bge_std);
3115 if (bge_newbuf_std(sc, sc->bge_std, 0)) {
3116 IFNET_STAT_INC(ifp, ierrors, 1);
3117 bge_setup_rxdesc_std(sc, sc->bge_std);
3121 if (sc->bge_rx_wreg > 0 && stdcnt >= sc->bge_rx_wreg) {
3122 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO,
3130 IFNET_STAT_INC(ifp, ipackets, 1);
3131 #if !defined(__i386__) && !defined(__x86_64__)
3133 * The x86 allows unaligned accesses, but for other
3134 * platforms we must make sure the payload is aligned.
3136 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
3137 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
3139 m->m_data += ETHER_ALIGN;
3142 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
3143 m->m_pkthdr.rcvif = ifp;
3145 if (ifp->if_capenable & IFCAP_RXCSUM) {
3146 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
3147 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3148 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
3149 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3151 if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) &&
3152 m->m_pkthdr.len >= BGE_MIN_FRAMELEN) {
3153 m->m_pkthdr.csum_data =
3154 cur_rx->bge_tcp_udp_csum;
3155 m->m_pkthdr.csum_flags |=
3156 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
3161 * If we received a packet with a vlan tag, pass it
3162 * to vlan_input() instead of ether_input().
3165 m->m_flags |= M_VLANTAG;
3166 m->m_pkthdr.ether_vlantag = vlan_tag;
3168 ifp->if_input(ifp, m, NULL, -1);
3171 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
3173 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
3175 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
3179 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
3183 ifp = &sc->arpcom.ac_if;
3186 * Go through our tx ring and free mbufs for those
3187 * frames that have been sent.
3189 while (sc->bge_tx_saved_considx != tx_cons) {
3192 idx = sc->bge_tx_saved_considx;
3193 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
3194 IFNET_STAT_INC(ifp, opackets, 1);
3195 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
3196 sc->bge_cdata.bge_tx_dmamap[idx]);
3197 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
3198 sc->bge_cdata.bge_tx_chain[idx] = NULL;
3201 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
3205 if ((BGE_TX_RING_CNT - sc->bge_txcnt) >=
3206 (sc->bge_txrsvd + sc->bge_txspare))
3207 ifq_clr_oactive(&ifp->if_snd);
3209 if (sc->bge_txcnt == 0)
3212 if (!ifq_is_empty(&ifp->if_snd))
3216 #ifdef IFPOLL_ENABLE
3219 bge_npoll_compat(struct ifnet *ifp, void *arg __unused, int cycles)
3221 struct bge_softc *sc = ifp->if_softc;
3222 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
3223 uint16_t rx_prod, tx_cons;
3225 ASSERT_SERIALIZED(ifp->if_serializer);
3227 if (sc->bge_npoll.ifpc_stcount-- == 0) {
3228 sc->bge_npoll.ifpc_stcount = sc->bge_npoll.ifpc_stfrac;
3230 * Process link state changes.
3235 if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
3236 sc->bge_status_tag = sblk->bge_status_tag;
3238 * Use a load fence to ensure that status_tag
3239 * is saved before rx_prod and tx_cons.
3244 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
3245 if (sc->bge_rx_saved_considx != rx_prod)
3246 bge_rxeof(sc, rx_prod, cycles);
3248 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
3249 if (sc->bge_tx_saved_considx != tx_cons)
3250 bge_txeof(sc, tx_cons);
3252 if (sc->bge_flags & BGE_FLAG_STATUS_TAG)
3253 bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24);
3255 if (sc->bge_coal_chg)
3256 bge_coal_change(sc);
3260 bge_npoll(struct ifnet *ifp, struct ifpoll_info *info)
3262 struct bge_softc *sc = ifp->if_softc;
3264 ASSERT_SERIALIZED(ifp->if_serializer);
3267 int cpuid = sc->bge_npoll.ifpc_cpuid;
3269 info->ifpi_rx[cpuid].poll_func = bge_npoll_compat;
3270 info->ifpi_rx[cpuid].arg = NULL;
3271 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
3273 if (ifp->if_flags & IFF_RUNNING)
3274 bge_disable_intr(sc);
3275 ifq_set_cpuid(&ifp->if_snd, cpuid);
3277 if (ifp->if_flags & IFF_RUNNING)
3278 bge_enable_intr(sc);
3279 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->bge_irq));
3283 #endif /* IFPOLL_ENABLE */
3286 bge_intr_crippled(void *xsc)
3288 struct bge_softc *sc = xsc;
3289 struct ifnet *ifp = &sc->arpcom.ac_if;
3294 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't
3295 * disable interrupts by writing nonzero like we used to, since with
3296 * our current organization this just gives complications and
3297 * pessimizations for re-enabling interrupts. We used to have races
3298 * instead of the necessary complications. Disabling interrupts
3299 * would just reduce the chance of a status update while we are
3300 * running (by switching to the interrupt-mode coalescence
3301 * parameters), but this chance is already very low so it is more
3302 * efficient to get another interrupt than prevent it.
3304 * We do the ack first to ensure another interrupt if there is a
3305 * status update after the ack. We don't check for the status
3306 * changing later because it is more efficient to get another
3307 * interrupt than prevent it, not quite as above (not checking is
3308 * a smaller optimization than not toggling the interrupt enable,
3309 * since checking doesn't involve PCI accesses and toggling require
3310 * the status check). So toggling would probably be a pessimization
3311 * even with MSI. It would only be needed for using a task queue.
3313 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
3316 * Process link state changes.
3320 if (ifp->if_flags & IFF_RUNNING) {
3321 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
3322 uint16_t rx_prod, tx_cons;
3324 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
3325 if (sc->bge_rx_saved_considx != rx_prod)
3326 bge_rxeof(sc, rx_prod, -1);
3328 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
3329 if (sc->bge_tx_saved_considx != tx_cons)
3330 bge_txeof(sc, tx_cons);
3333 if (sc->bge_coal_chg)
3334 bge_coal_change(sc);
3338 bge_intr_legacy(void *xsc)
3340 struct bge_softc *sc = xsc;
3341 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
3343 if (sc->bge_status_tag == sblk->bge_status_tag) {
3346 val = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4);
3347 if (val & BGE_PCISTAT_INTR_NOTACT)
3353 * Interrupt will have to be disabled if tagged status
3354 * is used, else interrupt will always be asserted on
3355 * certain chips (at least on BCM5750 AX/BX).
3357 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3365 struct bge_softc *sc = xsc;
3367 /* Disable interrupt first */
3368 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
3373 bge_msi_oneshot(void *xsc)
3379 bge_intr(struct bge_softc *sc)
3381 struct ifnet *ifp = &sc->arpcom.ac_if;
3382 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
3383 uint16_t rx_prod, tx_cons;
3386 sc->bge_status_tag = sblk->bge_status_tag;
3388 * Use a load fence to ensure that status_tag is saved
3389 * before rx_prod, tx_cons and status.
3393 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
3394 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
3395 status = sblk->bge_status;
3397 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bge_link_evt)
3400 if (ifp->if_flags & IFF_RUNNING) {
3401 if (sc->bge_rx_saved_considx != rx_prod)
3402 bge_rxeof(sc, rx_prod, -1);
3404 if (sc->bge_tx_saved_considx != tx_cons)
3405 bge_txeof(sc, tx_cons);
3408 bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24);
3410 if (sc->bge_coal_chg)
3411 bge_coal_change(sc);
3417 struct bge_softc *sc = xsc;
3418 struct ifnet *ifp = &sc->arpcom.ac_if;
3420 lwkt_serialize_enter(ifp->if_serializer);
3422 if (BGE_IS_5705_PLUS(sc))
3423 bge_stats_update_regs(sc);
3425 bge_stats_update(sc);
3427 if (sc->bge_flags & BGE_FLAG_TBI) {
3429 * Since in TBI mode auto-polling can't be used we should poll
3430 * link status manually. Here we register pending link event
3431 * and trigger interrupt.
3434 if (BGE_IS_CRIPPLED(sc))
3435 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3437 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3438 } else if (!sc->bge_link) {
3439 mii_tick(device_get_softc(sc->bge_miibus));
3442 bge_asf_driver_up(sc);
3444 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
3446 lwkt_serialize_exit(ifp->if_serializer);
3450 bge_stats_update_regs(struct bge_softc *sc)
3452 struct ifnet *ifp = &sc->arpcom.ac_if;
3453 struct bge_mac_stats_regs stats;
3457 s = (uint32_t *)&stats;
3458 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
3459 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
3463 IFNET_STAT_SET(ifp, collisions,
3464 (stats.dot3StatsSingleCollisionFrames +
3465 stats.dot3StatsMultipleCollisionFrames +
3466 stats.dot3StatsExcessiveCollisions +
3467 stats.dot3StatsLateCollisions));
3471 bge_stats_update(struct bge_softc *sc)
3473 struct ifnet *ifp = &sc->arpcom.ac_if;
3476 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
3478 #define READ_STAT(sc, stats, stat) \
3479 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
3481 IFNET_STAT_SET(ifp, collisions,
3482 (READ_STAT(sc, stats,
3483 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
3484 READ_STAT(sc, stats,
3485 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
3486 READ_STAT(sc, stats,
3487 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
3488 READ_STAT(sc, stats,
3489 txstats.dot3StatsLateCollisions.bge_addr_lo)));
3494 IFNET_STAT_SET(ifp, collisions,
3495 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
3496 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
3497 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
3498 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions));
3503 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
3504 * pointers to descriptors.
3507 bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx,
3510 struct bge_tx_bd *d = NULL, *last_d;
3511 uint16_t csum_flags = 0, mss = 0;
3512 bus_dma_segment_t segs[BGE_NSEG_NEW];
3514 int error, maxsegs, nsegs, idx, i;
3515 struct mbuf *m_head = *m_head0, *m_new;
3517 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3518 error = bge_setup_tso(sc, m_head0, &mss, &csum_flags);
3522 } else if (m_head->m_pkthdr.csum_flags & BGE_CSUM_FEATURES) {
3523 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3524 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
3525 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
3526 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
3527 if (m_head->m_flags & M_LASTFRAG)
3528 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
3529 else if (m_head->m_flags & M_FRAG)
3530 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
3534 map = sc->bge_cdata.bge_tx_dmamap[idx];
3536 maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - sc->bge_txrsvd;
3537 KASSERT(maxsegs >= sc->bge_txspare,
3538 ("not enough segments %d", maxsegs));
3540 if (maxsegs > BGE_NSEG_NEW)
3541 maxsegs = BGE_NSEG_NEW;
3544 * Pad outbound frame to BGE_MIN_FRAMELEN for an unusual reason.
3545 * The bge hardware will pad out Tx runts to BGE_MIN_FRAMELEN,
3546 * but when such padded frames employ the bge IP/TCP checksum
3547 * offload, the hardware checksum assist gives incorrect results
3548 * (possibly from incorporating its own padding into the UDP/TCP
3549 * checksum; who knows). If we pad such runts with zeros, the
3550 * onboard checksum comes out correct.
3552 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
3553 m_head->m_pkthdr.len < BGE_MIN_FRAMELEN) {
3554 error = m_devpad(m_head, BGE_MIN_FRAMELEN);
3559 if ((sc->bge_flags & BGE_FLAG_SHORTDMA) && m_head->m_next != NULL) {
3560 m_new = bge_defrag_shortdma(m_head);
3561 if (m_new == NULL) {
3565 *m_head0 = m_head = m_new;
3567 if ((m_head->m_pkthdr.csum_flags & CSUM_TSO) == 0 &&
3568 sc->bge_force_defrag && (sc->bge_flags & BGE_FLAG_PCIE) &&
3569 m_head->m_next != NULL) {
3571 * Forcefully defragment mbuf chain to overcome hardware
3572 * limitation which only support a single outstanding
3573 * DMA read operation. If it fails, keep moving on using
3574 * the original mbuf chain.
3576 m_new = m_defrag(m_head, M_NOWAIT);
3578 *m_head0 = m_head = m_new;
3581 error = bus_dmamap_load_mbuf_defrag(sc->bge_cdata.bge_tx_mtag, map,
3582 m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3585 *segs_used += nsegs;
3588 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
3590 for (i = 0; ; i++) {
3591 d = &sc->bge_ldata.bge_tx_ring[idx];
3593 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
3594 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
3595 d->bge_len = segs[i].ds_len;
3596 d->bge_flags = csum_flags;
3601 BGE_INC(idx, BGE_TX_RING_CNT);
3605 /* Set vlan tag to the first segment of the packet. */
3606 d = &sc->bge_ldata.bge_tx_ring[*txidx];
3607 if (m_head->m_flags & M_VLANTAG) {
3608 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
3609 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
3611 d->bge_vlan_tag = 0;
3614 /* Mark the last segment as end of packet... */
3615 last_d->bge_flags |= BGE_TXBDFLAG_END;
3618 * Insure that the map for this transmission is placed at
3619 * the array index of the last descriptor in this chain.
3621 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
3622 sc->bge_cdata.bge_tx_dmamap[idx] = map;
3623 sc->bge_cdata.bge_tx_chain[idx] = m_head;
3624 sc->bge_txcnt += nsegs;
3626 BGE_INC(idx, BGE_TX_RING_CNT);
3637 bge_xmit(struct bge_softc *sc, uint32_t prodidx)
3640 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3641 /* 5700 b2 errata */
3642 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
3643 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3647 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
3648 * to the mbuf data regions directly in the transmit descriptors.
3651 bge_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
3653 struct bge_softc *sc = ifp->if_softc;
3654 struct mbuf *m_head = NULL;
3658 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
3660 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
3663 prodidx = sc->bge_tx_prodidx;
3665 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
3666 m_head = ifq_dequeue(&ifp->if_snd);
3672 * The code inside the if() block is never reached since we
3673 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
3674 * requests to checksum TCP/UDP in a fragmented packet.
3677 * safety overkill. If this is a fragmented packet chain
3678 * with delayed TCP/UDP checksums, then only encapsulate
3679 * it if we have enough descriptors to handle the entire
3681 * (paranoia -- may not actually be needed)
3683 if ((m_head->m_flags & M_FIRSTFRAG) &&
3684 (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
3685 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3686 m_head->m_pkthdr.csum_data + sc->bge_txrsvd) {
3687 ifq_set_oactive(&ifp->if_snd);
3688 ifq_prepend(&ifp->if_snd, m_head);
3694 * Sanity check: avoid coming within bge_txrsvd
3695 * descriptors of the end of the ring. Also make
3696 * sure there are bge_txspare descriptors for
3697 * jumbo buffers' defragmentation.
3699 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
3700 (sc->bge_txrsvd + sc->bge_txspare)) {
3701 ifq_set_oactive(&ifp->if_snd);
3702 ifq_prepend(&ifp->if_snd, m_head);
3707 * Pack the data into the transmit ring. If we
3708 * don't have room, set the OACTIVE flag and wait
3709 * for the NIC to drain the ring.
3711 if (bge_encap(sc, &m_head, &prodidx, &nsegs)) {
3712 ifq_set_oactive(&ifp->if_snd);
3713 IFNET_STAT_INC(ifp, oerrors, 1);
3717 if (nsegs >= sc->bge_tx_wreg) {
3718 bge_xmit(sc, prodidx);
3722 ETHER_BPF_MTAP(ifp, m_head);
3725 * Set a timeout in case the chip goes out to lunch.
3731 bge_xmit(sc, prodidx);
3732 sc->bge_tx_prodidx = prodidx;
3738 struct bge_softc *sc = xsc;
3739 struct ifnet *ifp = &sc->arpcom.ac_if;
3743 ASSERT_SERIALIZED(ifp->if_serializer);
3745 /* Cancel pending I/O and flush buffers. */
3749 bge_sig_pre_reset(sc, BGE_RESET_START);
3751 bge_sig_legacy(sc, BGE_RESET_START);
3752 bge_sig_post_reset(sc, BGE_RESET_START);
3757 * Init the various state machines, ring
3758 * control blocks and firmware.
3760 if (bge_blockinit(sc)) {
3761 if_printf(ifp, "initialization failure\n");
3767 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3768 ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
3770 /* Load our MAC address. */
3771 m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
3772 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3773 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3775 /* Enable or disable promiscuous mode as needed. */
3778 /* Program multicast filter. */
3782 if (bge_init_rx_ring_std(sc)) {
3783 if_printf(ifp, "RX ring initialization failed\n");
3789 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
3790 * memory to insure that the chip has in fact read the first
3791 * entry of the ring.
3793 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
3795 for (i = 0; i < 10; i++) {
3797 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
3798 if (v == (MCLBYTES - ETHER_ALIGN))
3802 if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
3805 /* Init jumbo RX ring. */
3806 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3807 if (bge_init_rx_ring_jumbo(sc)) {
3808 if_printf(ifp, "Jumbo RX ring initialization failed\n");
3814 /* Init our RX return ring index */
3815 sc->bge_rx_saved_considx = 0;
3818 bge_init_tx_ring(sc);
3820 /* Enable TX MAC state machine lockup fix. */
3821 mode = CSR_READ_4(sc, BGE_TX_MODE);
3822 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
3823 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
3824 /* Turn on transmitter */
3825 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
3828 /* Turn on receiver */
3829 mode = CSR_READ_4(sc, BGE_RX_MODE);
3830 if (BGE_IS_5755_PLUS(sc))
3831 mode |= BGE_RXMODE_IPV6_ENABLE;
3832 CSR_WRITE_4(sc, BGE_RX_MODE, mode | BGE_RXMODE_ENABLE);
3836 * Set the number of good frames to receive after RX MBUF
3837 * Low Watermark has been reached. After the RX MAC receives
3838 * this number of frames, it will drop subsequent incoming
3839 * frames until the MBUF High Watermark is reached.
3841 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
3843 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) {
3845 if_printf(ifp, "MSI_MODE: %#x\n",
3846 CSR_READ_4(sc, BGE_MSI_MODE));
3851 * Linux driver turns it on for all chips supporting MSI?!
3853 if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) {
3856 * According to 5722-PG101-R,
3857 * BGE_PCIE_TRANSACT_ONESHOT_MSI applies only to
3860 BGE_SETBIT(sc, BGE_PCIE_TRANSACT,
3861 BGE_PCIE_TRANSACT_ONESHOT_MSI);
3865 /* Tell firmware we're alive. */
3866 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3868 /* Enable host interrupts if polling(4) is not enabled. */
3869 PCI_SETBIT(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4);
3870 #ifdef IFPOLL_ENABLE
3871 if (ifp->if_flags & IFF_NPOLLING)
3872 bge_disable_intr(sc);
3875 bge_enable_intr(sc);
3877 ifp->if_flags |= IFF_RUNNING;
3878 ifq_clr_oactive(&ifp->if_snd);
3880 bge_ifmedia_upd(ifp);
3882 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
3886 * Set media options.
3889 bge_ifmedia_upd(struct ifnet *ifp)
3891 struct bge_softc *sc = ifp->if_softc;
3893 /* If this is a 1000baseX NIC, enable the TBI port. */
3894 if (sc->bge_flags & BGE_FLAG_TBI) {
3895 struct ifmedia *ifm = &sc->bge_ifmedia;
3897 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3900 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3903 * The BCM5704 ASIC appears to have a special
3904 * mechanism for programming the autoneg
3905 * advertisement registers in TBI mode.
3907 if (!bge_fake_autoneg &&
3908 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3911 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
3912 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
3913 sgdig |= BGE_SGDIGCFG_AUTO |
3914 BGE_SGDIGCFG_PAUSE_CAP |
3915 BGE_SGDIGCFG_ASYM_PAUSE;
3916 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
3917 sgdig | BGE_SGDIGCFG_SEND);
3919 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
3923 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3924 BGE_CLRBIT(sc, BGE_MAC_MODE,
3925 BGE_MACMODE_HALF_DUPLEX);
3927 BGE_SETBIT(sc, BGE_MAC_MODE,
3928 BGE_MACMODE_HALF_DUPLEX);
3936 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3940 if (mii->mii_instance) {
3941 struct mii_softc *miisc;
3943 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3944 mii_phy_reset(miisc);
3949 * Force an interrupt so that we will call bge_link_upd
3950 * if needed and clear any pending link state attention.
3951 * Without this we are not getting any further interrupts
3952 * for link state changes and thus will not UP the link and
3953 * not be able to send in bge_start. The only way to get
3954 * things working was to receive a packet and get an RX
3957 * bge_tick should help for fiber cards and we might not
3958 * need to do this here if BGE_FLAG_TBI is set but as
3959 * we poll for fiber anyway it should not harm.
3961 if (BGE_IS_CRIPPLED(sc))
3962 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3964 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3970 * Report current media status.
3973 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3975 struct bge_softc *sc = ifp->if_softc;
3977 if ((ifp->if_flags & IFF_RUNNING) == 0)
3980 if (sc->bge_flags & BGE_FLAG_TBI) {
3981 ifmr->ifm_status = IFM_AVALID;
3982 ifmr->ifm_active = IFM_ETHER;
3983 if (CSR_READ_4(sc, BGE_MAC_STS) &
3984 BGE_MACSTAT_TBI_PCS_SYNCHED) {
3985 ifmr->ifm_status |= IFM_ACTIVE;
3987 ifmr->ifm_active |= IFM_NONE;
3991 ifmr->ifm_active |= IFM_1000_SX;
3992 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3993 ifmr->ifm_active |= IFM_HDX;
3995 ifmr->ifm_active |= IFM_FDX;
3997 struct mii_data *mii = device_get_softc(sc->bge_miibus);
4000 ifmr->ifm_active = mii->mii_media_active;
4001 ifmr->ifm_status = mii->mii_media_status;
4006 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
4008 struct bge_softc *sc = ifp->if_softc;
4009 struct ifreq *ifr = (struct ifreq *)data;
4010 int mask, error = 0;
4012 ASSERT_SERIALIZED(ifp->if_serializer);
4016 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
4017 (BGE_IS_JUMBO_CAPABLE(sc) &&
4018 ifr->ifr_mtu > BGE_JUMBO_MTU)) {
4020 } else if (ifp->if_mtu != ifr->ifr_mtu) {
4021 ifp->if_mtu = ifr->ifr_mtu;
4022 if (ifp->if_flags & IFF_RUNNING)
4027 if (ifp->if_flags & IFF_UP) {
4028 if (ifp->if_flags & IFF_RUNNING) {
4029 mask = ifp->if_flags ^ sc->bge_if_flags;
4032 * If only the state of the PROMISC flag
4033 * changed, then just use the 'set promisc
4034 * mode' command instead of reinitializing
4035 * the entire NIC. Doing a full re-init
4036 * means reloading the firmware and waiting
4037 * for it to start up, which may take a
4038 * second or two. Similarly for ALLMULTI.
4040 if (mask & IFF_PROMISC)
4042 if (mask & IFF_ALLMULTI)
4047 } else if (ifp->if_flags & IFF_RUNNING) {
4050 sc->bge_if_flags = ifp->if_flags;
4054 if (ifp->if_flags & IFF_RUNNING)
4059 if (sc->bge_flags & BGE_FLAG_TBI) {
4060 error = ifmedia_ioctl(ifp, ifr,
4061 &sc->bge_ifmedia, command);
4063 struct mii_data *mii;
4065 mii = device_get_softc(sc->bge_miibus);
4066 error = ifmedia_ioctl(ifp, ifr,
4067 &mii->mii_media, command);
4071 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
4072 if (mask & IFCAP_HWCSUM) {
4073 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
4074 if (ifp->if_capenable & IFCAP_TXCSUM)
4075 ifp->if_hwassist |= BGE_CSUM_FEATURES;
4077 ifp->if_hwassist &= ~BGE_CSUM_FEATURES;
4079 if (mask & IFCAP_TSO) {
4080 ifp->if_capenable ^= IFCAP_TSO;
4081 if (ifp->if_capenable & IFCAP_TSO)
4082 ifp->if_hwassist |= CSUM_TSO;
4084 ifp->if_hwassist &= ~CSUM_TSO;
4088 error = ether_ioctl(ifp, command, data);
4095 bge_watchdog(struct ifnet *ifp)
4097 struct bge_softc *sc = ifp->if_softc;
4099 if_printf(ifp, "watchdog timeout -- resetting\n");
4103 IFNET_STAT_INC(ifp, oerrors, 1);
4105 if (!ifq_is_empty(&ifp->if_snd))
4110 * Stop the adapter and free any mbufs allocated to the
4114 bge_stop(struct bge_softc *sc)
4116 struct ifnet *ifp = &sc->arpcom.ac_if;
4118 ASSERT_SERIALIZED(ifp->if_serializer);
4120 callout_stop(&sc->bge_stat_timer);
4122 /* Disable host interrupts. */
4123 bge_disable_intr(sc);
4126 * Tell firmware we're shutting down.
4129 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
4132 * Disable all of the receiver blocks
4134 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
4135 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
4136 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
4137 if (BGE_IS_5700_FAMILY(sc))
4138 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
4139 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
4140 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
4141 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
4144 * Disable all of the transmit blocks
4146 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
4147 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
4148 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
4149 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
4150 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
4151 if (BGE_IS_5700_FAMILY(sc))
4152 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
4153 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
4156 * Shut down all of the memory managers and related
4159 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
4160 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
4161 if (BGE_IS_5700_FAMILY(sc))
4162 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
4163 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
4164 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
4165 if (!BGE_IS_5705_PLUS(sc)) {
4166 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
4167 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4171 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
4172 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
4175 * Keep the ASF firmware running if up.
4177 if (sc->bge_asf_mode & ASF_STACKUP)
4178 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4180 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
4182 /* Free the RX lists. */
4183 bge_free_rx_ring_std(sc);
4185 /* Free jumbo RX list. */
4186 if (BGE_IS_JUMBO_CAPABLE(sc))
4187 bge_free_rx_ring_jumbo(sc);
4189 /* Free TX buffers. */
4190 bge_free_tx_ring(sc);
4192 sc->bge_status_tag = 0;
4194 sc->bge_coal_chg = 0;
4196 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
4198 ifp->if_flags &= ~IFF_RUNNING;
4199 ifq_clr_oactive(&ifp->if_snd);
4204 * Stop all chip I/O so that the kernel's probe routines don't
4205 * get confused by errant DMAs when rebooting.
4208 bge_shutdown(device_t dev)
4210 struct bge_softc *sc = device_get_softc(dev);
4211 struct ifnet *ifp = &sc->arpcom.ac_if;
4213 lwkt_serialize_enter(ifp->if_serializer);
4215 lwkt_serialize_exit(ifp->if_serializer);
4219 bge_suspend(device_t dev)
4221 struct bge_softc *sc = device_get_softc(dev);
4222 struct ifnet *ifp = &sc->arpcom.ac_if;
4224 lwkt_serialize_enter(ifp->if_serializer);
4226 lwkt_serialize_exit(ifp->if_serializer);
4232 bge_resume(device_t dev)
4234 struct bge_softc *sc = device_get_softc(dev);
4235 struct ifnet *ifp = &sc->arpcom.ac_if;
4237 lwkt_serialize_enter(ifp->if_serializer);
4239 if (ifp->if_flags & IFF_UP) {
4242 if (!ifq_is_empty(&ifp->if_snd))
4246 lwkt_serialize_exit(ifp->if_serializer);
4252 bge_setpromisc(struct bge_softc *sc)
4254 struct ifnet *ifp = &sc->arpcom.ac_if;
4256 if (ifp->if_flags & IFF_PROMISC)
4257 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
4259 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
4263 bge_dma_free(struct bge_softc *sc)
4267 /* Destroy RX mbuf DMA stuffs. */
4268 if (sc->bge_cdata.bge_rx_mtag != NULL) {
4269 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
4270 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
4271 sc->bge_cdata.bge_rx_std_dmamap[i]);
4273 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
4274 sc->bge_cdata.bge_rx_tmpmap);
4275 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
4278 /* Destroy TX mbuf DMA stuffs. */
4279 if (sc->bge_cdata.bge_tx_mtag != NULL) {
4280 for (i = 0; i < BGE_TX_RING_CNT; i++) {
4281 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
4282 sc->bge_cdata.bge_tx_dmamap[i]);
4284 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
4287 /* Destroy standard RX ring */
4288 bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag,
4289 sc->bge_cdata.bge_rx_std_ring_map,
4290 sc->bge_ldata.bge_rx_std_ring);
4292 if (BGE_IS_JUMBO_CAPABLE(sc))
4293 bge_free_jumbo_mem(sc);
4295 /* Destroy RX return ring */
4296 bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag,
4297 sc->bge_cdata.bge_rx_return_ring_map,
4298 sc->bge_ldata.bge_rx_return_ring);
4300 /* Destroy TX ring */
4301 bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag,
4302 sc->bge_cdata.bge_tx_ring_map,
4303 sc->bge_ldata.bge_tx_ring);
4305 /* Destroy status block */
4306 bge_dma_block_free(sc->bge_cdata.bge_status_tag,
4307 sc->bge_cdata.bge_status_map,
4308 sc->bge_ldata.bge_status_block);
4310 /* Destroy statistics block */
4311 bge_dma_block_free(sc->bge_cdata.bge_stats_tag,
4312 sc->bge_cdata.bge_stats_map,
4313 sc->bge_ldata.bge_stats);
4315 /* Destroy the parent tag */
4316 if (sc->bge_cdata.bge_parent_tag != NULL)
4317 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
4321 bge_dma_alloc(struct bge_softc *sc)
4323 struct ifnet *ifp = &sc->arpcom.ac_if;
4328 lowaddr = BUS_SPACE_MAXADDR;
4329 if (sc->bge_flags & BGE_FLAG_MAXADDR_40BIT)
4330 lowaddr = BGE_DMA_MAXADDR_40BIT;
4333 * Allocate the parent bus DMA tag appropriate for PCI.
4335 * All of the NetExtreme/NetLink controllers have 4GB boundary
4337 * Whenever an address crosses a multiple of the 4GB boundary
4338 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
4339 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
4340 * state machine will lockup and cause the device to hang.
4342 error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G,
4343 lowaddr, BUS_SPACE_MAXADDR,
4345 BUS_SPACE_MAXSIZE_32BIT, 0,
4346 BUS_SPACE_MAXSIZE_32BIT,
4347 0, &sc->bge_cdata.bge_parent_tag);
4349 if_printf(ifp, "could not allocate parent dma tag\n");
4354 * Create DMA tag and maps for RX mbufs.
4356 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
4357 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
4358 NULL, NULL, MCLBYTES, 1, MCLBYTES,
4359 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
4360 &sc->bge_cdata.bge_rx_mtag);
4362 if_printf(ifp, "could not allocate RX mbuf dma tag\n");
4366 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
4367 BUS_DMA_WAITOK, &sc->bge_cdata.bge_rx_tmpmap);
4369 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
4370 sc->bge_cdata.bge_rx_mtag = NULL;
4374 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
4375 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
4377 &sc->bge_cdata.bge_rx_std_dmamap[i]);
4381 for (j = 0; j < i; ++j) {
4382 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
4383 sc->bge_cdata.bge_rx_std_dmamap[j]);
4385 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
4386 sc->bge_cdata.bge_rx_mtag = NULL;
4388 if_printf(ifp, "could not create DMA map for RX\n");
4394 * Create DMA tag and maps for TX mbufs.
4396 if (sc->bge_flags & BGE_FLAG_TSO)
4397 txmaxsz = IP_MAXPACKET + sizeof(struct ether_vlan_header);
4399 txmaxsz = BGE_JUMBO_FRAMELEN;
4400 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
4401 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
4403 txmaxsz, BGE_NSEG_NEW, PAGE_SIZE,
4404 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
4406 &sc->bge_cdata.bge_tx_mtag);
4408 if_printf(ifp, "could not allocate TX mbuf dma tag\n");
4412 for (i = 0; i < BGE_TX_RING_CNT; i++) {
4413 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag,
4414 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
4415 &sc->bge_cdata.bge_tx_dmamap[i]);
4419 for (j = 0; j < i; ++j) {
4420 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
4421 sc->bge_cdata.bge_tx_dmamap[j]);
4423 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
4424 sc->bge_cdata.bge_tx_mtag = NULL;
4426 if_printf(ifp, "could not create DMA map for TX\n");
4432 * Create DMA stuffs for standard RX ring.
4434 error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
4435 &sc->bge_cdata.bge_rx_std_ring_tag,
4436 &sc->bge_cdata.bge_rx_std_ring_map,
4437 (void *)&sc->bge_ldata.bge_rx_std_ring,
4438 &sc->bge_ldata.bge_rx_std_ring_paddr);
4440 if_printf(ifp, "could not create std RX ring\n");
4445 * Create jumbo buffer pool.
4447 if (BGE_IS_JUMBO_CAPABLE(sc)) {
4448 error = bge_alloc_jumbo_mem(sc);
4450 if_printf(ifp, "could not create jumbo buffer pool\n");
4456 * Create DMA stuffs for RX return ring.
4458 error = bge_dma_block_alloc(sc,
4459 BGE_RX_RTN_RING_SZ(sc->bge_return_ring_cnt),
4460 &sc->bge_cdata.bge_rx_return_ring_tag,
4461 &sc->bge_cdata.bge_rx_return_ring_map,
4462 (void *)&sc->bge_ldata.bge_rx_return_ring,
4463 &sc->bge_ldata.bge_rx_return_ring_paddr);
4465 if_printf(ifp, "could not create RX ret ring\n");
4470 * Create DMA stuffs for TX ring.
4472 error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ,
4473 &sc->bge_cdata.bge_tx_ring_tag,
4474 &sc->bge_cdata.bge_tx_ring_map,
4475 (void *)&sc->bge_ldata.bge_tx_ring,
4476 &sc->bge_ldata.bge_tx_ring_paddr);
4478 if_printf(ifp, "could not create TX ring\n");
4483 * Create DMA stuffs for status block.
4485 error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
4486 &sc->bge_cdata.bge_status_tag,
4487 &sc->bge_cdata.bge_status_map,
4488 (void *)&sc->bge_ldata.bge_status_block,
4489 &sc->bge_ldata.bge_status_block_paddr);
4491 if_printf(ifp, "could not create status block\n");
4496 * Create DMA stuffs for statistics block.
4498 error = bge_dma_block_alloc(sc, BGE_STATS_SZ,
4499 &sc->bge_cdata.bge_stats_tag,
4500 &sc->bge_cdata.bge_stats_map,
4501 (void *)&sc->bge_ldata.bge_stats,
4502 &sc->bge_ldata.bge_stats_paddr);
4504 if_printf(ifp, "could not create stats block\n");
4511 bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
4512 bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
4517 error = bus_dmamem_coherent(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0,
4518 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
4519 size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
4523 *tag = dmem.dmem_tag;
4524 *map = dmem.dmem_map;
4525 *addr = dmem.dmem_addr;
4526 *paddr = dmem.dmem_busaddr;
4532 bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
4535 bus_dmamap_unload(tag, map);
4536 bus_dmamem_free(tag, addr, map);
4537 bus_dma_tag_destroy(tag);
4542 * Grrr. The link status word in the status block does
4543 * not work correctly on the BCM5700 rev AX and BX chips,
4544 * according to all available information. Hence, we have
4545 * to enable MII interrupts in order to properly obtain
4546 * async link changes. Unfortunately, this also means that
4547 * we have to read the MAC status register to detect link
4548 * changes, thereby adding an additional register access to
4549 * the interrupt handler.
4551 * XXX: perhaps link state detection procedure used for
4552 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
4555 bge_bcm5700_link_upd(struct bge_softc *sc, uint32_t status __unused)
4557 struct ifnet *ifp = &sc->arpcom.ac_if;
4558 struct mii_data *mii = device_get_softc(sc->bge_miibus);
4562 if (!sc->bge_link &&
4563 (mii->mii_media_status & IFM_ACTIVE) &&
4564 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4567 if_printf(ifp, "link UP\n");
4568 } else if (sc->bge_link &&
4569 (!(mii->mii_media_status & IFM_ACTIVE) ||
4570 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4573 if_printf(ifp, "link DOWN\n");
4576 /* Clear the interrupt. */
4577 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT);
4578 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
4579 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, BRGPHY_INTRS);
4583 bge_tbi_link_upd(struct bge_softc *sc, uint32_t status)
4585 struct ifnet *ifp = &sc->arpcom.ac_if;
4587 #define PCS_ENCODE_ERR (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
4590 * Sometimes PCS encoding errors are detected in
4591 * TBI mode (on fiber NICs), and for some reason
4592 * the chip will signal them as link changes.
4593 * If we get a link change event, but the 'PCS
4594 * encoding error' bit in the MAC status register
4595 * is set, don't bother doing a link check.
4596 * This avoids spurious "gigabit link up" messages
4597 * that sometimes appear on fiber NICs during
4598 * periods of heavy traffic.
4600 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
4601 if (!sc->bge_link) {
4603 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4604 BGE_CLRBIT(sc, BGE_MAC_MODE,
4605 BGE_MACMODE_TBI_SEND_CFGS);
4608 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
4611 if_printf(ifp, "link UP\n");
4613 ifp->if_link_state = LINK_STATE_UP;
4614 if_link_state_change(ifp);
4616 } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
4621 if_printf(ifp, "link DOWN\n");
4623 ifp->if_link_state = LINK_STATE_DOWN;
4624 if_link_state_change(ifp);
4628 #undef PCS_ENCODE_ERR
4630 /* Clear the attention. */
4631 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4632 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4633 BGE_MACSTAT_LINK_CHANGED);
4637 bge_copper_link_upd(struct bge_softc *sc, uint32_t status __unused)
4639 struct ifnet *ifp = &sc->arpcom.ac_if;
4640 struct mii_data *mii = device_get_softc(sc->bge_miibus);
4643 bge_miibus_statchg(sc->bge_dev);
4647 if_printf(ifp, "link UP\n");
4649 if_printf(ifp, "link DOWN\n");
4652 /* Clear the attention. */
4653 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4654 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4655 BGE_MACSTAT_LINK_CHANGED);
4659 bge_autopoll_link_upd(struct bge_softc *sc, uint32_t status __unused)
4661 struct ifnet *ifp = &sc->arpcom.ac_if;
4662 struct mii_data *mii = device_get_softc(sc->bge_miibus);
4666 if (!sc->bge_link &&
4667 (mii->mii_media_status & IFM_ACTIVE) &&
4668 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
4671 if_printf(ifp, "link UP\n");
4672 } else if (sc->bge_link &&
4673 (!(mii->mii_media_status & IFM_ACTIVE) ||
4674 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
4677 if_printf(ifp, "link DOWN\n");
4680 /* Clear the attention. */
4681 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4682 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
4683 BGE_MACSTAT_LINK_CHANGED);
4687 bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
4689 struct bge_softc *sc = arg1;
4691 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4692 &sc->bge_rx_coal_ticks,
4693 BGE_RX_COAL_TICKS_MIN, BGE_RX_COAL_TICKS_MAX,
4694 BGE_RX_COAL_TICKS_CHG);
4698 bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
4700 struct bge_softc *sc = arg1;
4702 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4703 &sc->bge_tx_coal_ticks,
4704 BGE_TX_COAL_TICKS_MIN, BGE_TX_COAL_TICKS_MAX,
4705 BGE_TX_COAL_TICKS_CHG);
4709 bge_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS)
4711 struct bge_softc *sc = arg1;
4713 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4714 &sc->bge_rx_coal_bds,
4715 BGE_RX_COAL_BDS_MIN, BGE_RX_COAL_BDS_MAX,
4716 BGE_RX_COAL_BDS_CHG);
4720 bge_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS)
4722 struct bge_softc *sc = arg1;
4724 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4725 &sc->bge_tx_coal_bds,
4726 BGE_TX_COAL_BDS_MIN, BGE_TX_COAL_BDS_MAX,
4727 BGE_TX_COAL_BDS_CHG);
4731 bge_sysctl_rx_coal_ticks_int(SYSCTL_HANDLER_ARGS)
4733 struct bge_softc *sc = arg1;
4735 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4736 &sc->bge_rx_coal_ticks_int,
4737 BGE_RX_COAL_TICKS_MIN, BGE_RX_COAL_TICKS_MAX,
4738 BGE_RX_COAL_TICKS_INT_CHG);
4742 bge_sysctl_tx_coal_ticks_int(SYSCTL_HANDLER_ARGS)
4744 struct bge_softc *sc = arg1;
4746 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4747 &sc->bge_tx_coal_ticks_int,
4748 BGE_TX_COAL_TICKS_MIN, BGE_TX_COAL_TICKS_MAX,
4749 BGE_TX_COAL_TICKS_INT_CHG);
4753 bge_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS)
4755 struct bge_softc *sc = arg1;
4757 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4758 &sc->bge_rx_coal_bds_int,
4759 BGE_RX_COAL_BDS_MIN, BGE_RX_COAL_BDS_MAX,
4760 BGE_RX_COAL_BDS_INT_CHG);
4764 bge_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS)
4766 struct bge_softc *sc = arg1;
4768 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
4769 &sc->bge_tx_coal_bds_int,
4770 BGE_TX_COAL_BDS_MIN, BGE_TX_COAL_BDS_MAX,
4771 BGE_TX_COAL_BDS_INT_CHG);
4775 bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
4776 int coal_min, int coal_max, uint32_t coal_chg_mask)
4778 struct bge_softc *sc = arg1;
4779 struct ifnet *ifp = &sc->arpcom.ac_if;
4782 lwkt_serialize_enter(ifp->if_serializer);
4785 error = sysctl_handle_int(oidp, &v, 0, req);
4786 if (!error && req->newptr != NULL) {
4787 if (v < coal_min || v > coal_max) {
4791 sc->bge_coal_chg |= coal_chg_mask;
4795 lwkt_serialize_exit(ifp->if_serializer);
4800 bge_coal_change(struct bge_softc *sc)
4802 struct ifnet *ifp = &sc->arpcom.ac_if;
4804 ASSERT_SERIALIZED(ifp->if_serializer);
4806 if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_CHG) {
4807 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
4808 sc->bge_rx_coal_ticks);
4810 CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
4813 if_printf(ifp, "rx_coal_ticks -> %u\n",
4814 sc->bge_rx_coal_ticks);
4818 if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_CHG) {
4819 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
4820 sc->bge_tx_coal_ticks);
4822 CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
4825 if_printf(ifp, "tx_coal_ticks -> %u\n",
4826 sc->bge_tx_coal_ticks);
4830 if (sc->bge_coal_chg & BGE_RX_COAL_BDS_CHG) {
4831 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
4832 sc->bge_rx_coal_bds);
4834 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
4837 if_printf(ifp, "rx_coal_bds -> %u\n",
4838 sc->bge_rx_coal_bds);
4842 if (sc->bge_coal_chg & BGE_TX_COAL_BDS_CHG) {
4843 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
4844 sc->bge_tx_coal_bds);
4846 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
4849 if_printf(ifp, "tx_max_coal_bds -> %u\n",
4850 sc->bge_tx_coal_bds);
4854 if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_INT_CHG) {
4855 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT,
4856 sc->bge_rx_coal_ticks_int);
4858 CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS_INT);
4861 if_printf(ifp, "rx_coal_ticks_int -> %u\n",
4862 sc->bge_rx_coal_ticks_int);
4866 if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_INT_CHG) {
4867 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT,
4868 sc->bge_tx_coal_ticks_int);
4870 CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS_INT);
4873 if_printf(ifp, "tx_coal_ticks_int -> %u\n",
4874 sc->bge_tx_coal_ticks_int);
4878 if (sc->bge_coal_chg & BGE_RX_COAL_BDS_INT_CHG) {
4879 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT,
4880 sc->bge_rx_coal_bds_int);
4882 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT);
4885 if_printf(ifp, "rx_coal_bds_int -> %u\n",
4886 sc->bge_rx_coal_bds_int);
4890 if (sc->bge_coal_chg & BGE_TX_COAL_BDS_INT_CHG) {
4891 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT,
4892 sc->bge_tx_coal_bds_int);
4894 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT);
4897 if_printf(ifp, "tx_coal_bds_int -> %u\n",
4898 sc->bge_tx_coal_bds_int);
4902 sc->bge_coal_chg = 0;
4906 bge_enable_intr(struct bge_softc *sc)
4908 struct ifnet *ifp = &sc->arpcom.ac_if;
4910 lwkt_serialize_handler_enable(ifp->if_serializer);
4915 bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24);
4916 if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) {
4917 /* XXX Linux driver */
4918 bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24);
4922 * Unmask the interrupt when we stop polling.
4924 PCI_CLRBIT(sc->bge_dev, BGE_PCI_MISC_CTL,
4925 BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
4928 * Trigger another interrupt, since above writing
4929 * to interrupt mailbox0 may acknowledge pending
4932 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4936 bge_disable_intr(struct bge_softc *sc)
4938 struct ifnet *ifp = &sc->arpcom.ac_if;
4941 * Mask the interrupt when we start polling.
4943 PCI_SETBIT(sc->bge_dev, BGE_PCI_MISC_CTL,
4944 BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
4947 * Acknowledge possible asserted interrupt.
4949 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4951 sc->bge_npoll.ifpc_stcount = 0;
4953 lwkt_serialize_handler_disable(ifp->if_serializer);
4957 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
4962 mac_addr = bge_readmem_ind(sc, 0x0c14);
4963 if ((mac_addr >> 16) == 0x484b) {
4964 ether_addr[0] = (uint8_t)(mac_addr >> 8);
4965 ether_addr[1] = (uint8_t)mac_addr;
4966 mac_addr = bge_readmem_ind(sc, 0x0c18);
4967 ether_addr[2] = (uint8_t)(mac_addr >> 24);
4968 ether_addr[3] = (uint8_t)(mac_addr >> 16);
4969 ether_addr[4] = (uint8_t)(mac_addr >> 8);
4970 ether_addr[5] = (uint8_t)mac_addr;
4977 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
4979 int mac_offset = BGE_EE_MAC_OFFSET;
4981 if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
4982 mac_offset = BGE_EE_MAC_OFFSET_5906;
4984 return bge_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN);
4988 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
4990 if (sc->bge_flags & BGE_FLAG_NO_EEPROM)
4993 return bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
4998 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
5000 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
5001 /* NOTE: Order is critical */
5003 bge_get_eaddr_nvram,
5004 bge_get_eaddr_eeprom,
5007 const bge_eaddr_fcn_t *func;
5009 for (func = bge_eaddr_funcs; *func != NULL; ++func) {
5010 if ((*func)(sc, eaddr) == 0)
5013 return (*func == NULL ? ENXIO : 0);
5017 * NOTE: 'm' is not freed upon failure
5020 bge_defrag_shortdma(struct mbuf *m)
5026 * If device receive two back-to-back send BDs with less than
5027 * or equal to 8 total bytes then the device may hang. The two
5028 * back-to-back send BDs must in the same frame for this failure
5029 * to occur. Scan mbuf chains and see whether two back-to-back
5030 * send BDs are there. If this is the case, allocate new mbuf
5031 * and copy the frame to workaround the silicon bug.
5033 for (n = m, found = 0; n != NULL; n = n->m_next) {
5044 n = m_defrag(m, M_NOWAIT);
5051 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit)
5055 BGE_CLRBIT(sc, reg, bit);
5056 for (i = 0; i < BGE_TIMEOUT; i++) {
5057 if ((CSR_READ_4(sc, reg) & bit) == 0)
5064 bge_link_poll(struct bge_softc *sc)
5068 status = CSR_READ_4(sc, BGE_MAC_STS);
5069 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
5070 sc->bge_link_evt = 0;
5071 sc->bge_link_upd(sc, status);
5076 bge_enable_msi(struct bge_softc *sc)
5080 msi_mode = CSR_READ_4(sc, BGE_MSI_MODE);
5081 msi_mode |= BGE_MSIMODE_ENABLE;
5082 if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) {
5084 * According to all of the datasheets that are publicly
5085 * available, bit 5 of the MSI_MODE is defined to be
5086 * "MSI FIFO Underrun Attn" for BCM5755+ and BCM5906, on
5087 * which "oneshot MSI" is enabled. However, it is always
5088 * safe to clear it here.
5090 msi_mode &= ~BGE_MSIMODE_ONESHOT_DISABLE;
5092 CSR_WRITE_4(sc, BGE_MSI_MODE, msi_mode);
5096 bge_setup_tso(struct bge_softc *sc, struct mbuf **mp,
5097 uint16_t *mss0, uint16_t *flags0)
5102 int thoff, iphlen, hoff, hlen;
5103 uint16_t flags, mss;
5106 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
5108 hoff = m->m_pkthdr.csum_lhlen;
5109 iphlen = m->m_pkthdr.csum_iphlen;
5110 thoff = m->m_pkthdr.csum_thlen;
5112 KASSERT(hoff > 0, ("invalid ether header len"));
5113 KASSERT(iphlen > 0, ("invalid ip header len"));
5114 KASSERT(thoff > 0, ("invalid tcp header len"));
5116 if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
5117 m = m_pullup(m, hoff + iphlen + thoff);
5124 ip = mtodoff(m, struct ip *, hoff);
5125 th = mtodoff(m, struct tcphdr *, hoff + iphlen);
5127 mss = m->m_pkthdr.tso_segsz;
5128 flags = BGE_TXBDFLAG_CPU_PRE_DMA | BGE_TXBDFLAG_CPU_POST_DMA;
5130 ip->ip_len = htons(mss + iphlen + thoff);
5133 hlen = (iphlen + thoff) >> 2;
5134 mss |= (hlen << 11);
5143 bge_stop_fw(struct bge_softc *sc)
5147 if (sc->bge_asf_mode) {
5148 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE);
5149 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
5150 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT);
5152 for (i = 0; i < 100; i++ ) {
5153 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &
5154 BGE_RX_CPU_DRV_EVENT))
5162 bge_sig_pre_reset(struct bge_softc *sc, int type)
5165 * Some chips don't like this so only do this if ASF is enabled
5167 if (sc->bge_asf_mode)
5168 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
5170 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
5172 case BGE_RESET_START:
5173 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
5174 BGE_FW_DRV_STATE_START);
5176 case BGE_RESET_SHUTDOWN:
5177 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
5178 BGE_FW_DRV_STATE_UNLOAD);
5180 case BGE_RESET_SUSPEND:
5181 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
5182 BGE_FW_DRV_STATE_SUSPEND);
5187 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND)
5188 bge_ape_driver_state_change(sc, type);
5192 bge_sig_legacy(struct bge_softc *sc, int type)
5194 if (sc->bge_asf_mode) {
5196 case BGE_RESET_START:
5197 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
5198 BGE_FW_DRV_STATE_START);
5200 case BGE_RESET_SHUTDOWN:
5201 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
5202 BGE_FW_DRV_STATE_UNLOAD);
5209 bge_sig_post_reset(struct bge_softc *sc, int type)
5211 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
5213 case BGE_RESET_START:
5214 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
5215 BGE_FW_DRV_STATE_START_DONE);
5218 case BGE_RESET_SHUTDOWN:
5219 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
5220 BGE_FW_DRV_STATE_UNLOAD_DONE);
5224 if (type == BGE_RESET_SHUTDOWN)
5225 bge_ape_driver_state_change(sc, type);
5229 bge_asf_driver_up(struct bge_softc *sc)
5231 if (sc->bge_asf_mode & ASF_STACKUP) {
5232 /* Send ASF heartbeat aprox. every 2s */
5233 if (sc->bge_asf_count)
5234 sc->bge_asf_count --;
5236 sc->bge_asf_count = 2;
5237 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB,
5238 BGE_FW_CMD_DRV_ALIVE);
5239 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4);
5240 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB,
5241 BGE_FW_HB_TIMEOUT_SEC);
5242 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
5243 CSR_READ_4(sc, BGE_RX_CPU_EVENT) |
5244 BGE_RX_CPU_DRV_EVENT);
5250 * Clear all stale locks and select the lock for this driver instance.
5253 bge_ape_lock_init(struct bge_softc *sc)
5255 uint32_t bit, regbase;
5258 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
5259 regbase = BGE_APE_LOCK_GRANT;
5261 regbase = BGE_APE_PER_LOCK_GRANT;
5263 /* Clear any stale locks. */
5264 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) {
5266 case BGE_APE_LOCK_PHY0:
5267 case BGE_APE_LOCK_PHY1:
5268 case BGE_APE_LOCK_PHY2:
5269 case BGE_APE_LOCK_PHY3:
5270 bit = BGE_APE_LOCK_GRANT_DRIVER0;
5273 if (sc->bge_func_addr == 0)
5274 bit = BGE_APE_LOCK_GRANT_DRIVER0;
5276 bit = (1 << sc->bge_func_addr);
5278 APE_WRITE_4(sc, regbase + 4 * i, bit);
5281 /* Select the PHY lock based on the device's function number. */
5282 switch (sc->bge_func_addr) {
5284 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0;
5287 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1;
5290 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2;
5293 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3;
5296 device_printf(sc->bge_dev,
5297 "PHY lock not supported on this function\n");
5302 * Check for APE firmware, set flags, and print version info.
5305 bge_ape_read_fw_ver(struct bge_softc *sc)
5308 uint32_t apedata, features;
5310 /* Check for a valid APE signature in shared memory. */
5311 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG);
5312 if (apedata != BGE_APE_SEG_SIG_MAGIC) {
5313 device_printf(sc->bge_dev, "no APE signature\n");
5314 sc->bge_mfw_flags &= ~BGE_MFW_ON_APE;
5318 /* Check if APE firmware is running. */
5319 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS);
5320 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) {
5321 device_printf(sc->bge_dev, "APE signature found "
5322 "but FW status not ready! 0x%08x\n", apedata);
5326 sc->bge_mfw_flags |= BGE_MFW_ON_APE;
5328 /* Fetch the APE firwmare type and version. */
5329 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION);
5330 features = APE_READ_4(sc, BGE_APE_FW_FEATURES);
5331 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) {
5332 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI;
5334 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) {
5335 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH;
5340 /* Print the APE firmware version. */
5341 device_printf(sc->bge_dev, "APE FW version: %s v%d.%d.%d.%d\n",
5343 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT,
5344 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT,
5345 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT,
5346 (apedata & BGE_APE_FW_VERSION_BLDMSK));
5350 bge_ape_lock(struct bge_softc *sc, int locknum)
5352 uint32_t bit, gnt, req, status;
5355 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
5358 /* Lock request/grant registers have different bases. */
5359 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) {
5360 req = BGE_APE_LOCK_REQ;
5361 gnt = BGE_APE_LOCK_GRANT;
5363 req = BGE_APE_PER_LOCK_REQ;
5364 gnt = BGE_APE_PER_LOCK_GRANT;
5370 case BGE_APE_LOCK_GPIO:
5371 /* Lock required when using GPIO. */
5372 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
5374 if (sc->bge_func_addr == 0)
5375 bit = BGE_APE_LOCK_REQ_DRIVER0;
5377 bit = (1 << sc->bge_func_addr);
5379 case BGE_APE_LOCK_GRC:
5380 /* Lock required to reset the device. */
5381 if (sc->bge_func_addr == 0)
5382 bit = BGE_APE_LOCK_REQ_DRIVER0;
5384 bit = (1 << sc->bge_func_addr);
5386 case BGE_APE_LOCK_MEM:
5387 /* Lock required when accessing certain APE memory. */
5388 if (sc->bge_func_addr == 0)
5389 bit = BGE_APE_LOCK_REQ_DRIVER0;
5391 bit = (1 << sc->bge_func_addr);
5393 case BGE_APE_LOCK_PHY0:
5394 case BGE_APE_LOCK_PHY1:
5395 case BGE_APE_LOCK_PHY2:
5396 case BGE_APE_LOCK_PHY3:
5397 /* Lock required when accessing PHYs. */
5398 bit = BGE_APE_LOCK_REQ_DRIVER0;
5404 /* Request a lock. */
5405 APE_WRITE_4(sc, req + off, bit);
5407 /* Wait up to 1 second to acquire lock. */
5408 for (i = 0; i < 20000; i++) {
5409 status = APE_READ_4(sc, gnt + off);
5415 /* Handle any errors. */
5416 if (status != bit) {
5417 device_printf(sc->bge_dev, "APE lock %d request failed! "
5418 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n",
5419 locknum, req + off, bit & 0xFFFF, gnt + off,
5421 /* Revoke the lock request. */
5422 APE_WRITE_4(sc, gnt + off, bit);
5430 bge_ape_unlock(struct bge_softc *sc, int locknum)
5435 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
5438 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
5439 gnt = BGE_APE_LOCK_GRANT;
5441 gnt = BGE_APE_PER_LOCK_GRANT;
5446 case BGE_APE_LOCK_GPIO:
5447 if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
5449 if (sc->bge_func_addr == 0)
5450 bit = BGE_APE_LOCK_GRANT_DRIVER0;
5452 bit = (1 << sc->bge_func_addr);
5454 case BGE_APE_LOCK_GRC:
5455 if (sc->bge_func_addr == 0)
5456 bit = BGE_APE_LOCK_GRANT_DRIVER0;
5458 bit = (1 << sc->bge_func_addr);
5460 case BGE_APE_LOCK_MEM:
5461 if (sc->bge_func_addr == 0)
5462 bit = BGE_APE_LOCK_GRANT_DRIVER0;
5464 bit = (1 << sc->bge_func_addr);
5466 case BGE_APE_LOCK_PHY0:
5467 case BGE_APE_LOCK_PHY1:
5468 case BGE_APE_LOCK_PHY2:
5469 case BGE_APE_LOCK_PHY3:
5470 bit = BGE_APE_LOCK_GRANT_DRIVER0;
5476 APE_WRITE_4(sc, gnt + off, bit);
5480 * Send an event to the APE firmware.
5483 bge_ape_send_event(struct bge_softc *sc, uint32_t event)
5488 /* NCSI does not support APE events. */
5489 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
5492 /* Wait up to 1ms for APE to service previous event. */
5493 for (i = 10; i > 0; i--) {
5494 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0)
5496 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS);
5497 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) {
5498 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event |
5499 BGE_APE_EVENT_STATUS_EVENT_PENDING);
5500 bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
5501 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1);
5504 bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
5508 device_printf(sc->bge_dev, "APE event 0x%08x send timed out\n",
5513 bge_ape_driver_state_change(struct bge_softc *sc, int kind)
5515 uint32_t apedata, event;
5517 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
5521 case BGE_RESET_START:
5522 /* If this is the first load, clear the load counter. */
5523 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG);
5524 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC)
5525 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0);
5527 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT);
5528 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata);
5530 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG,
5531 BGE_APE_HOST_SEG_SIG_MAGIC);
5532 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN,
5533 BGE_APE_HOST_SEG_LEN_MAGIC);
5535 /* Add some version info if bge(4) supports it. */
5536 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID,
5537 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0));
5538 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR,
5539 BGE_APE_HOST_BEHAV_NO_PHYLOCK);
5540 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS,
5541 BGE_APE_HOST_HEARTBEAT_INT_DISABLE);
5542 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
5543 BGE_APE_HOST_DRVR_STATE_START);
5544 event = BGE_APE_EVENT_STATUS_STATE_START;
5546 case BGE_RESET_SHUTDOWN:
5547 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
5548 BGE_APE_HOST_DRVR_STATE_UNLOAD);
5549 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD;
5551 case BGE_RESET_SUSPEND:
5552 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND;
5558 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT |
5559 BGE_APE_EVENT_STATUS_STATE_CHNGE);