2 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 #include <sys/param.h>
36 #include <sys/bitops.h>
37 #include <sys/endian.h>
38 #include <sys/kernel.h>
40 #include <sys/interrupt.h>
41 #include <sys/malloc.h>
44 #include <sys/serialize.h>
45 #include <sys/socket.h>
46 #include <sys/sockio.h>
47 #include <sys/sysctl.h>
49 #include <net/ethernet.h>
52 #include <net/if_arp.h>
53 #include <net/if_dl.h>
54 #include <net/if_media.h>
55 #include <net/ifq_var.h>
57 #include <netproto/802_11/ieee80211_radiotap.h>
58 #include <netproto/802_11/ieee80211_var.h>
59 #include <netproto/802_11/wlan_ratectl/onoe/ieee80211_onoe_param.h>
61 #include <bus/pci/pcireg.h>
62 #include <bus/pci/pcivar.h>
65 #include <dev/netif/bwi/if_bwireg.h>
66 #include <dev/netif/bwi/if_bwivar.h>
67 #include <dev/netif/bwi/bwimac.h>
68 #include <dev/netif/bwi/bwirf.h>
70 struct bwi_clock_freq {
75 struct bwi_myaddr_bssid {
76 uint8_t myaddr[IEEE80211_ADDR_LEN];
77 uint8_t bssid[IEEE80211_ADDR_LEN];
80 static int bwi_probe(device_t);
81 static int bwi_attach(device_t);
82 static int bwi_detach(device_t);
83 static int bwi_shutdown(device_t);
85 static void bwi_init(void *);
86 static int bwi_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
87 static void bwi_start(struct ifnet *, struct ifaltq_subque *);
88 static void bwi_watchdog(struct ifnet *);
89 static int bwi_newstate(struct ieee80211com *, enum ieee80211_state, int);
90 static void bwi_updateslot(struct ifnet *);
91 static int bwi_media_change(struct ifnet *);
92 static void *bwi_ratectl_attach(struct ieee80211com *, u_int);
94 static void bwi_next_scan(void *);
95 static void bwi_calibrate(void *);
97 static void bwi_newstate_begin(struct bwi_softc *, enum ieee80211_state);
98 static void bwi_init_statechg(struct bwi_softc *, int);
99 static int bwi_stop(struct bwi_softc *, int);
100 static int bwi_newbuf(struct bwi_softc *, int, int);
101 static int bwi_encap(struct bwi_softc *, int, struct mbuf *,
102 struct ieee80211_node **, int);
104 static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t,
105 bus_addr_t, int, int);
106 static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t);
108 static int bwi_init_tx_ring32(struct bwi_softc *, int);
109 static int bwi_init_rx_ring32(struct bwi_softc *);
110 static int bwi_init_txstats32(struct bwi_softc *);
111 static void bwi_free_tx_ring32(struct bwi_softc *, int);
112 static void bwi_free_rx_ring32(struct bwi_softc *);
113 static void bwi_free_txstats32(struct bwi_softc *);
114 static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int);
115 static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *,
116 int, bus_addr_t, int);
117 static int bwi_rxeof32(struct bwi_softc *);
118 static void bwi_start_tx32(struct bwi_softc *, uint32_t, int);
119 static void bwi_txeof_status32(struct bwi_softc *);
121 static int bwi_init_tx_ring64(struct bwi_softc *, int);
122 static int bwi_init_rx_ring64(struct bwi_softc *);
123 static int bwi_init_txstats64(struct bwi_softc *);
124 static void bwi_free_tx_ring64(struct bwi_softc *, int);
125 static void bwi_free_rx_ring64(struct bwi_softc *);
126 static void bwi_free_txstats64(struct bwi_softc *);
127 static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int);
128 static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *,
129 int, bus_addr_t, int);
130 static int bwi_rxeof64(struct bwi_softc *);
131 static void bwi_start_tx64(struct bwi_softc *, uint32_t, int);
132 static void bwi_txeof_status64(struct bwi_softc *);
134 static void bwi_intr(void *);
135 static int bwi_rxeof(struct bwi_softc *, int);
136 static void _bwi_txeof(struct bwi_softc *, uint16_t, int, int);
137 static void bwi_txeof(struct bwi_softc *);
138 static void bwi_txeof_status(struct bwi_softc *, int);
139 static void bwi_enable_intrs(struct bwi_softc *, uint32_t);
140 static void bwi_disable_intrs(struct bwi_softc *, uint32_t);
141 static int bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *);
142 static void bwi_rx_radiotap(struct bwi_softc *, struct mbuf *,
143 struct bwi_rxbuf_hdr *, const void *, int, int);
145 static int bwi_dma_alloc(struct bwi_softc *);
146 static void bwi_dma_free(struct bwi_softc *);
147 static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t,
148 struct bwi_ring_data *, bus_size_t,
150 static int bwi_dma_mbuf_create(struct bwi_softc *);
151 static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int);
152 static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t);
153 static void bwi_dma_txstats_free(struct bwi_softc *);
154 static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int);
155 static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int,
158 static void bwi_power_on(struct bwi_softc *, int);
159 static int bwi_power_off(struct bwi_softc *, int);
160 static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode);
161 static int bwi_set_clock_delay(struct bwi_softc *);
162 static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *);
163 static int bwi_get_pwron_delay(struct bwi_softc *sc);
164 static void bwi_set_addr_filter(struct bwi_softc *, uint16_t,
166 static void bwi_set_bssid(struct bwi_softc *, const uint8_t *);
167 static int bwi_set_chan(struct bwi_softc *, struct ieee80211_channel *);
169 static void bwi_get_card_flags(struct bwi_softc *);
170 static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *);
172 static int bwi_bus_attach(struct bwi_softc *);
173 static int bwi_bbp_attach(struct bwi_softc *);
174 static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode);
175 static void bwi_bbp_power_off(struct bwi_softc *);
177 static const char *bwi_regwin_name(const struct bwi_regwin *);
178 static uint32_t bwi_regwin_disable_bits(struct bwi_softc *);
179 static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *);
180 static int bwi_regwin_select(struct bwi_softc *, int);
182 static void bwi_led_attach(struct bwi_softc *);
183 static void bwi_led_newstate(struct bwi_softc *, enum ieee80211_state);
184 static void bwi_led_event(struct bwi_softc *, int);
185 static void bwi_led_blink_start(struct bwi_softc *, int, int);
186 static void bwi_led_blink_next(void *);
187 static void bwi_led_blink_end(void *);
189 static const struct bwi_dev {
194 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4301,
195 "Broadcom BCM4301 802.11 Wireless Lan" },
197 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4307,
198 "Broadcom BCM4307 802.11 Wireless Lan" },
200 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4311,
201 "Broadcom BCM4311 802.11 Wireless Lan" },
203 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4312,
204 "Broadcom BCM4312 802.11 Wireless Lan" },
206 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4306_1,
207 "Broadcom BCM4306 802.11 Wireless Lan" },
209 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4306_2,
210 "Broadcom BCM4306 802.11 Wireless Lan" },
212 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4306_3,
213 "Broadcom BCM4306 802.11 Wireless Lan" },
215 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4309,
216 "Broadcom BCM4309 802.11 Wireless Lan" },
218 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4318,
219 "Broadcom BCM4318 802.11 Wireless Lan" },
221 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4319,
222 "Broadcom BCM4319 802.11 Wireless Lan" }
225 static device_method_t bwi_methods[] = {
226 DEVMETHOD(device_probe, bwi_probe),
227 DEVMETHOD(device_attach, bwi_attach),
228 DEVMETHOD(device_detach, bwi_detach),
229 DEVMETHOD(device_shutdown, bwi_shutdown),
231 DEVMETHOD(device_suspend, bwi_suspend),
232 DEVMETHOD(device_resume, bwi_resume),
237 static driver_t bwi_driver = {
240 sizeof(struct bwi_softc)
243 static devclass_t bwi_devclass;
245 DRIVER_MODULE(bwi, pci, bwi_driver, bwi_devclass, NULL, NULL);
246 DRIVER_MODULE(bwi, cardbus, bwi_driver, bwi_devclass, NULL, NULL);
248 MODULE_DEPEND(bwi, wlan, 1, 1, 1);
249 MODULE_DEPEND(bwi, wlan_ratectl_onoe, 1, 1, 1);
251 MODULE_DEPEND(bwi, wlan_ratectl_amrr, 1, 1, 1);
253 MODULE_DEPEND(bwi, pci, 1, 1, 1);
254 MODULE_DEPEND(bwi, cardbus, 1, 1, 1);
256 static const struct {
260 } bwi_bbpid_map[] = {
261 { 0x4301, 0x4301, 0x4301 },
262 { 0x4305, 0x4307, 0x4307 },
263 { 0x4403, 0x4403, 0x4402 },
264 { 0x4610, 0x4615, 0x4610 },
265 { 0x4710, 0x4715, 0x4710 },
266 { 0x4720, 0x4725, 0x4309 }
269 static const struct {
272 } bwi_regwin_count[] = {
285 #define CLKSRC(src) \
286 [BWI_CLKSRC_ ## src] = { \
287 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \
288 .freq_max = BWI_CLKSRC_ ##src## _FMAX \
291 static const struct {
294 } bwi_clkfreq[BWI_CLKSRC_MAX] = {
302 #define VENDOR_LED_ACT(vendor) \
304 .vid = PCI_VENDOR_##vendor, \
305 .led_act = { BWI_VENDOR_LED_ACT_##vendor } \
308 static const struct {
310 uint8_t led_act[BWI_LED_MAX];
311 } bwi_vendor_led_act[] = {
312 VENDOR_LED_ACT(COMPAQ),
313 VENDOR_LED_ACT(LINKSYS)
316 static const uint8_t bwi_default_led_act[BWI_LED_MAX] =
317 { BWI_VENDOR_LED_ACT_DEFAULT };
319 #undef VENDOR_LED_ACT
321 static const struct {
324 } bwi_led_duration[109] = {
341 #ifdef BWI_DEBUG_VERBOSE
342 static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER;
344 static uint32_t bwi_debug;
346 TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug);
347 #endif /* BWI_DEBUG */
349 static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN];
351 static const struct ieee80211_rateset bwi_rateset_11b =
352 { 4, { 2, 4, 11, 22 } };
353 static const struct ieee80211_rateset bwi_rateset_11g =
354 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } };
357 bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs)
359 return CSR_READ_2(sc, ofs + BWI_SPROM_START);
363 bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array,
364 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len,
367 struct bwi_desc32 *desc = &desc_array[desc_idx];
368 uint32_t ctrl, addr, addr_hi, addr_lo;
370 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK);
371 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK);
373 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) |
374 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK);
376 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) |
377 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK);
378 if (desc_idx == ndesc - 1)
379 ctrl |= BWI_DESC32_C_EOR;
382 ctrl |= BWI_DESC32_C_FRAME_START |
383 BWI_DESC32_C_FRAME_END |
387 desc->addr = htole32(addr);
388 desc->ctrl = htole32(ctrl);
391 /* XXX does not belong here */
393 bwi_rate2plcp(uint8_t rate)
395 rate &= IEEE80211_RATE_VAL;
400 case 11: return 0x37;
401 case 22: return 0x6e;
402 case 44: return 0xdc;
411 case 108: return 0xc;
414 panic("unsupported rate %u", rate);
418 /* XXX does not belong here */
419 #define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0)
420 #define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5)
423 bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate)
427 plcp = __SHIFTIN(bwi_rate2plcp(rate), IEEE80211_OFDM_PLCP_RATE_MASK) |
428 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK);
429 *plcp0 = htole32(plcp);
432 /* XXX does not belong here */
433 struct ieee80211_ds_plcp_hdr {
440 #define IEEE80211_DS_PLCP_SERVICE_LOCKED 0x04
441 #define IEEE80211_DS_PLCL_SERVICE_PBCC 0x08
442 #define IEEE80211_DS_PLCP_SERVICE_LENEXT5 0x20
443 #define IEEE80211_DS_PLCP_SERVICE_LENEXT6 0x40
444 #define IEEE80211_DS_PLCP_SERVICE_LENEXT7 0x80
447 bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len,
450 int len, service, pkt_bitlen;
452 pkt_bitlen = pkt_len * NBBY;
453 len = howmany(pkt_bitlen * 2, rate);
455 service = IEEE80211_DS_PLCP_SERVICE_LOCKED;
456 if (rate == (11 * 2)) {
460 * PLCP service field needs to be adjusted,
461 * if TX rate is 11Mbytes/s
463 pkt_bitlen1 = len * 11;
464 if (pkt_bitlen1 - pkt_bitlen >= NBBY)
465 service |= IEEE80211_DS_PLCP_SERVICE_LENEXT7;
468 plcp->i_signal = bwi_rate2plcp(rate);
469 plcp->i_service = service;
470 plcp->i_length = htole16(len);
471 /* NOTE: do NOT touch i_crc */
475 bwi_plcp_header(void *plcp, int pkt_len, uint8_t rate)
477 enum ieee80211_modtype modtype;
480 * Assume caller has zeroed 'plcp'
483 modtype = ieee80211_rate2modtype(rate);
484 if (modtype == IEEE80211_MODTYPE_OFDM)
485 bwi_ofdm_plcp_header(plcp, pkt_len, rate);
486 else if (modtype == IEEE80211_MODTYPE_DS)
487 bwi_ds_plcp_header(plcp, pkt_len, rate);
489 panic("unsupport modulation type %u", modtype);
492 static __inline uint8_t
493 bwi_ofdm_plcp2rate(const uint32_t *plcp0)
498 plcp = le32toh(*plcp0);
499 plcp_rate = __SHIFTOUT(plcp, IEEE80211_OFDM_PLCP_RATE_MASK);
500 return ieee80211_plcp2rate(plcp_rate, 1);
503 static __inline uint8_t
504 bwi_ds_plcp2rate(const struct ieee80211_ds_plcp_hdr *hdr)
506 return ieee80211_plcp2rate(hdr->i_signal, 0);
510 bwi_probe(device_t dev)
512 const struct bwi_dev *b;
515 did = pci_get_device(dev);
516 vid = pci_get_vendor(dev);
518 for (b = bwi_devices; b->desc != NULL; ++b) {
519 if (b->did == did && b->vid == vid) {
520 device_set_desc(dev, b->desc);
528 bwi_attach(device_t dev)
530 struct bwi_softc *sc = device_get_softc(dev);
531 struct ieee80211com *ic = &sc->sc_ic;
532 struct ifnet *ifp = &ic->ic_if;
535 struct sysctl_ctx_list *ctx;
536 struct sysctl_oid_list *tree;
537 char ethstr[ETHER_ADDRSTRLEN + 1];
540 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
544 * Initialize sysctl variables
546 sc->sc_fw_version = BWI_FW_VERSION3;
547 sc->sc_dwell_time = 200;
548 sc->sc_led_idle = (2350 * hz) / 1000;
549 sc->sc_led_blink = 1;
550 sc->sc_txpwr_calib = 1;
552 sc->sc_debug = bwi_debug;
555 callout_init(&sc->sc_scan_ch);
556 callout_init(&sc->sc_calib_ch);
559 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
562 /* XXX Save more PCIR */
563 irq = pci_read_config(dev, PCIR_INTLINE, 4);
564 mem = pci_read_config(dev, BWI_PCIR_BAR, 4);
566 device_printf(dev, "chip is in D%d power mode "
567 "-- setting to D0\n", pci_get_powerstate(dev));
569 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
571 pci_write_config(dev, PCIR_INTLINE, irq, 4);
572 pci_write_config(dev, BWI_PCIR_BAR, mem, 4);
574 #endif /* !BURN_BRIDGE */
576 pci_enable_busmaster(dev);
578 /* Get more PCI information */
579 sc->sc_pci_revid = pci_get_revid(dev);
580 sc->sc_pci_subvid = pci_get_subvendor(dev);
581 sc->sc_pci_subdid = pci_get_subdevice(dev);
586 sc->sc_mem_rid = BWI_PCIR_BAR;
587 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
588 &sc->sc_mem_rid, RF_ACTIVE);
589 if (sc->sc_mem_res == NULL) {
590 device_printf(dev, "can't allocate IO memory\n");
593 sc->sc_mem_bt = rman_get_bustag(sc->sc_mem_res);
594 sc->sc_mem_bh = rman_get_bushandle(sc->sc_mem_res);
600 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
602 RF_SHAREABLE | RF_ACTIVE);
603 if (sc->sc_irq_res == NULL) {
604 device_printf(dev, "can't allocate irq\n");
612 ctx = device_get_sysctl_ctx(sc->bge_dev);
613 tree = device_get_sysctl_tree(sc->bge_dev);
615 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
616 "dwell_time", CTLFLAG_RW, &sc->sc_dwell_time, 0,
617 "Channel dwell time during scan (msec)");
618 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
619 "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0,
621 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
622 "led_idle", CTLFLAG_RW, &sc->sc_led_idle, 0,
623 "# ticks before LED enters idle state");
624 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
625 "led_blink", CTLFLAG_RW, &sc->sc_led_blink, 0,
626 "Allow LED to blink");
627 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
628 "txpwr_calib", CTLFLAG_RW, &sc->sc_txpwr_calib, 0,
629 "Enable software TX power calibration");
631 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
632 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags");
637 error = bwi_bbp_attach(sc);
641 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
645 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) {
646 error = bwi_set_clock_delay(sc);
650 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST);
654 error = bwi_get_pwron_delay(sc);
659 error = bwi_bus_attach(sc);
663 bwi_get_card_flags(sc);
667 for (i = 0; i < sc->sc_nmac; ++i) {
668 struct bwi_regwin *old;
670 mac = &sc->sc_mac[i];
671 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old);
675 error = bwi_mac_lateattach(mac);
679 error = bwi_regwin_switch(sc, old, NULL);
685 * XXX First MAC is known to exist
688 mac = &sc->sc_mac[0];
691 bwi_bbp_power_off(sc);
693 error = bwi_dma_alloc(sc);
698 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
699 ifp->if_init = bwi_init;
700 ifp->if_ioctl = bwi_ioctl;
701 ifp->if_start = bwi_start;
702 ifp->if_watchdog = bwi_watchdog;
703 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
705 ifq_set_ready(&ifp->if_snd);
709 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO),
710 BWI_SPROM_CARD_INFO_LOCALE);
711 DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale);
714 * Setup ratesets, phytype, channels and get MAC address
716 if (phy->phy_mode == IEEE80211_MODE_11B ||
717 phy->phy_mode == IEEE80211_MODE_11G) {
720 ic->ic_sup_rates[IEEE80211_MODE_11B] = bwi_rateset_11b;
722 if (phy->phy_mode == IEEE80211_MODE_11B) {
723 chan_flags = IEEE80211_CHAN_B;
724 ic->ic_phytype = IEEE80211_T_DS;
726 chan_flags = IEEE80211_CHAN_CCK |
727 IEEE80211_CHAN_OFDM |
730 ic->ic_phytype = IEEE80211_T_OFDM;
731 ic->ic_sup_rates[IEEE80211_MODE_11G] =
735 /* XXX depend on locale */
736 for (i = 1; i <= 14; ++i) {
737 ic->ic_channels[i].ic_freq =
738 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ);
739 ic->ic_channels[i].ic_flags = chan_flags;
742 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, ic->ic_myaddr);
743 if (IEEE80211_IS_MULTICAST(ic->ic_myaddr)) {
744 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, ic->ic_myaddr);
745 if (IEEE80211_IS_MULTICAST(ic->ic_myaddr)) {
746 device_printf(dev, "invalid MAC address: "
747 "%s\n", kether_ntoa(ic->ic_myaddr, ethstr));
750 } else if (phy->phy_mode == IEEE80211_MODE_11A) {
755 panic("unknown phymode %d", phy->phy_mode);
758 ic->ic_caps = IEEE80211_C_SHSLOT |
759 IEEE80211_C_SHPREAMBLE |
762 ic->ic_state = IEEE80211_S_INIT;
763 ic->ic_opmode = IEEE80211_M_STA;
765 IEEE80211_ONOE_PARAM_SETUP(&sc->sc_onoe_param);
766 ic->ic_ratectl.rc_st_ratectl_cap = IEEE80211_RATECTL_CAP_ONOE;
767 ic->ic_ratectl.rc_st_ratectl = IEEE80211_RATECTL_ONOE;
768 ic->ic_ratectl.rc_st_attach = bwi_ratectl_attach;
770 ic->ic_updateslot = bwi_updateslot;
772 ieee80211_ifattach(ic);
774 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr);
775 ic->ic_flags_ext |= IEEE80211_FEXT_SWBMISS;
777 sc->sc_newstate = ic->ic_newstate;
778 ic->ic_newstate = bwi_newstate;
780 ieee80211_media_init(ic, bwi_media_change, ieee80211_media_status);
785 bpfattach_dlt(ifp, DLT_IEEE802_11_RADIO,
786 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th),
789 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(uint32_t));
790 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len);
791 sc->sc_tx_th.wt_ihdr.it_present = htole32(BWI_TX_RADIOTAP_PRESENT);
793 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(uint32_t));
794 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len);
795 sc->sc_rx_th.wr_ihdr.it_present = htole32(BWI_RX_RADIOTAP_PRESENT);
797 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->sc_irq_res));
799 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, bwi_intr, sc,
800 &sc->sc_irq_handle, ifp->if_serializer);
802 device_printf(dev, "can't setup intr\n");
804 ieee80211_ifdetach(ic);
809 ieee80211_announce(ic);
818 bwi_detach(device_t dev)
820 struct bwi_softc *sc = device_get_softc(dev);
822 if (device_is_attached(dev)) {
823 struct ifnet *ifp = &sc->sc_ic.ic_if;
826 lwkt_serialize_enter(ifp->if_serializer);
828 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle);
829 lwkt_serialize_exit(ifp->if_serializer);
832 ieee80211_ifdetach(&sc->sc_ic);
834 for (i = 0; i < sc->sc_nmac; ++i)
835 bwi_mac_detach(&sc->sc_mac[i]);
838 if (sc->sc_irq_res != NULL) {
839 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
843 if (sc->sc_mem_res != NULL) {
844 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
854 bwi_shutdown(device_t dev)
856 struct bwi_softc *sc = device_get_softc(dev);
857 struct ifnet *ifp = &sc->sc_ic.ic_if;
859 lwkt_serialize_enter(ifp->if_serializer);
861 lwkt_serialize_exit(ifp->if_serializer);
866 bwi_power_on(struct bwi_softc *sc, int with_pll)
868 uint32_t gpio_in, gpio_out, gpio_en;
871 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4);
872 if (gpio_in & BWI_PCIM_GPIO_PWR_ON)
875 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
876 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
878 gpio_out |= BWI_PCIM_GPIO_PWR_ON;
879 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
881 /* Turn off PLL first */
882 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
883 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
886 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
887 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
892 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF;
893 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
898 /* Clear "Signaled Target Abort" */
899 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2);
900 status &= ~PCIM_STATUS_STABORT;
901 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2);
905 bwi_power_off(struct bwi_softc *sc, int with_pll)
907 uint32_t gpio_out, gpio_en;
909 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */
910 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
911 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
913 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON;
914 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
916 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
917 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
920 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
921 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
926 bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw,
927 struct bwi_regwin **old_rw)
934 if (!BWI_REGWIN_EXIST(rw))
937 if (sc->sc_cur_regwin != rw) {
938 error = bwi_regwin_select(sc, rw->rw_id);
940 if_printf(&sc->sc_ic.ic_if, "can't select regwin %d\n",
947 *old_rw = sc->sc_cur_regwin;
948 sc->sc_cur_regwin = rw;
953 bwi_regwin_select(struct bwi_softc *sc, int id)
955 uint32_t win = BWI_PCIM_REGWIN(id);
959 for (i = 0; i < RETRY_MAX; ++i) {
960 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4);
961 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win)
971 bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev)
975 val = CSR_READ_4(sc, BWI_ID_HI);
976 *type = BWI_ID_HI_REGWIN_TYPE(val);
977 *rev = BWI_ID_HI_REGWIN_REV(val);
979 DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, "
980 "vendor 0x%04x\n", *type, *rev,
981 __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK));
985 bwi_bbp_attach(struct bwi_softc *sc)
987 uint16_t bbp_id, rw_type;
990 int error, nregwin, i;
993 * Get 0th regwin information
994 * NOTE: 0th regwin should exist
996 error = bwi_regwin_select(sc, 0);
998 device_printf(sc->sc_dev, "can't select regwin 0\n");
1001 bwi_regwin_info(sc, &rw_type, &rw_rev);
1008 if (rw_type == BWI_REGWIN_T_COM) {
1009 info = CSR_READ_4(sc, BWI_INFO);
1010 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK);
1012 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev);
1014 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY);
1016 uint16_t did = pci_get_device(sc->sc_dev);
1017 uint8_t revid = pci_get_revid(sc->sc_dev);
1019 for (i = 0; i < NELEM(bwi_bbpid_map); ++i) {
1020 if (did >= bwi_bbpid_map[i].did_min &&
1021 did <= bwi_bbpid_map[i].did_max) {
1022 bbp_id = bwi_bbpid_map[i].bbp_id;
1027 device_printf(sc->sc_dev, "no BBP id for device id "
1032 info = __SHIFTIN(revid, BWI_INFO_BBPREV_MASK) |
1033 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK);
1037 * Find out number of regwins
1040 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) {
1041 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK);
1043 for (i = 0; i < NELEM(bwi_regwin_count); ++i) {
1044 if (bwi_regwin_count[i].bbp_id == bbp_id) {
1045 nregwin = bwi_regwin_count[i].nregwin;
1050 device_printf(sc->sc_dev, "no number of win for "
1051 "BBP id 0x%04x\n", bbp_id);
1056 /* Record BBP id/rev for later using */
1057 sc->sc_bbp_id = bbp_id;
1058 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK);
1059 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK);
1060 device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n",
1061 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg);
1063 DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n",
1064 nregwin, sc->sc_cap);
1067 * Create rest of the regwins
1070 /* Don't re-create common regwin, if it is already created */
1071 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0;
1073 for (; i < nregwin; ++i) {
1075 * Get regwin information
1077 error = bwi_regwin_select(sc, i);
1079 device_printf(sc->sc_dev,
1080 "can't select regwin %d\n", i);
1083 bwi_regwin_info(sc, &rw_type, &rw_rev);
1087 * 1) Bus (PCI/PCIE) regwin
1089 * Ignore rest types of regwin
1091 if (rw_type == BWI_REGWIN_T_BUSPCI ||
1092 rw_type == BWI_REGWIN_T_BUSPCIE) {
1093 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
1094 device_printf(sc->sc_dev,
1095 "bus regwin already exists\n");
1097 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i,
1100 } else if (rw_type == BWI_REGWIN_T_MAC) {
1101 /* XXX ignore return value */
1102 bwi_mac_attach(sc, i, rw_rev);
1106 /* At least one MAC shold exist */
1107 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) {
1108 device_printf(sc->sc_dev, "no MAC was found\n");
1111 KKASSERT(sc->sc_nmac > 0);
1113 /* Bus regwin must exist */
1114 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
1115 device_printf(sc->sc_dev, "no bus regwin was found\n");
1119 /* Start with first MAC */
1120 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL);
1128 bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac)
1130 struct bwi_regwin *old, *bus;
1134 bus = &sc->sc_bus_regwin;
1135 KKASSERT(sc->sc_cur_regwin == &mac->mac_regwin);
1138 * Tell bus to generate requested interrupts
1140 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) {
1142 * NOTE: Read BWI_FLAGS from MAC regwin
1144 val = CSR_READ_4(sc, BWI_FLAGS);
1146 error = bwi_regwin_switch(sc, bus, &old);
1150 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK));
1154 mac_mask = 1 << mac->mac_id;
1156 error = bwi_regwin_switch(sc, bus, &old);
1160 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4);
1161 val |= mac_mask << 8;
1162 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4);
1165 if (sc->sc_flags & BWI_F_BUS_INITED)
1168 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) {
1170 * Enable prefetch and burst
1172 CSR_SETBITS_4(sc, BWI_BUS_CONFIG,
1173 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST);
1175 if (bus->rw_rev < 5) {
1176 struct bwi_regwin *com = &sc->sc_com_regwin;
1179 * Configure timeouts for bus operation
1183 * Set service timeout and request timeout
1185 CSR_SETBITS_4(sc, BWI_CONF_LO,
1186 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) |
1187 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK));
1190 * If there is common regwin, we switch to that regwin
1191 * and switch back to bus regwin once we have done.
1193 if (BWI_REGWIN_EXIST(com)) {
1194 error = bwi_regwin_switch(sc, com, NULL);
1199 /* Let bus know what we have changed */
1200 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC);
1201 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */
1202 CSR_WRITE_4(sc, BWI_BUS_DATA, 0);
1203 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */
1205 if (BWI_REGWIN_EXIST(com)) {
1206 error = bwi_regwin_switch(sc, bus, NULL);
1210 } else if (bus->rw_rev >= 11) {
1212 * Enable memory read multiple
1214 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM);
1220 sc->sc_flags |= BWI_F_BUS_INITED;
1222 return bwi_regwin_switch(sc, old, NULL);
1226 bwi_get_card_flags(struct bwi_softc *sc)
1228 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS);
1229 if (sc->sc_card_flags == 0xffff)
1230 sc->sc_card_flags = 0;
1232 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE &&
1233 sc->sc_pci_subdid == 0x4e && /* XXX */
1234 sc->sc_pci_revid > 0x40)
1235 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9;
1237 DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags);
1241 bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr)
1245 for (i = 0; i < 3; ++i) {
1246 *((uint16_t *)eaddr + i) =
1247 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i));
1252 bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq)
1254 struct bwi_regwin *com;
1259 bzero(freq, sizeof(*freq));
1260 com = &sc->sc_com_regwin;
1262 KKASSERT(BWI_REGWIN_EXIST(com));
1263 KKASSERT(sc->sc_cur_regwin == com);
1264 KKASSERT(sc->sc_cap & BWI_CAP_CLKMODE);
1267 * Calculate clock frequency
1271 if (com->rw_rev < 6) {
1272 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
1273 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) {
1274 src = BWI_CLKSRC_PCI;
1277 src = BWI_CLKSRC_CS_OSC;
1280 } else if (com->rw_rev < 10) {
1281 val = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1283 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC);
1284 if (src == BWI_CLKSRC_LP_OSC) {
1287 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2;
1289 /* Unknown source */
1290 if (src >= BWI_CLKSRC_MAX)
1291 src = BWI_CLKSRC_CS_OSC;
1294 val = CSR_READ_4(sc, BWI_CLOCK_INFO);
1296 src = BWI_CLKSRC_CS_OSC;
1297 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2;
1300 KKASSERT(src >= 0 && src < BWI_CLKSRC_MAX);
1303 DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n",
1304 src == BWI_CLKSRC_PCI ? "PCI" :
1305 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC"));
1307 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div;
1308 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div;
1310 DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n",
1311 freq->clkfreq_min, freq->clkfreq_max);
1315 bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
1317 struct bwi_regwin *old, *com;
1318 uint32_t clk_ctrl, clk_src;
1319 int error, pwr_off = 0;
1321 com = &sc->sc_com_regwin;
1322 if (!BWI_REGWIN_EXIST(com))
1325 if (com->rw_rev >= 10 || com->rw_rev < 6)
1329 * For common regwin whose rev is [6, 10), the chip
1330 * must be capable to change clock mode.
1332 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
1335 error = bwi_regwin_switch(sc, com, &old);
1339 if (clk_mode == BWI_CLOCK_MODE_FAST)
1340 bwi_power_on(sc, 0); /* Don't turn on PLL */
1342 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1343 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC);
1346 case BWI_CLOCK_MODE_FAST:
1347 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW;
1348 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL;
1350 case BWI_CLOCK_MODE_SLOW:
1351 clk_ctrl |= BWI_CLOCK_CTRL_SLOW;
1353 case BWI_CLOCK_MODE_DYN:
1354 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW |
1355 BWI_CLOCK_CTRL_IGNPLL |
1356 BWI_CLOCK_CTRL_NODYN);
1357 if (clk_src != BWI_CLKSRC_CS_OSC) {
1358 clk_ctrl |= BWI_CLOCK_CTRL_NODYN;
1363 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl);
1366 bwi_power_off(sc, 0); /* Leave PLL as it is */
1368 return bwi_regwin_switch(sc, old, NULL);
1372 bwi_set_clock_delay(struct bwi_softc *sc)
1374 struct bwi_regwin *old, *com;
1377 com = &sc->sc_com_regwin;
1378 if (!BWI_REGWIN_EXIST(com))
1381 error = bwi_regwin_switch(sc, com, &old);
1385 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) {
1386 if (sc->sc_bbp_rev == 0)
1387 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0);
1388 else if (sc->sc_bbp_rev == 1)
1389 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1);
1392 if (sc->sc_cap & BWI_CAP_CLKMODE) {
1393 if (com->rw_rev >= 10) {
1394 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000);
1396 struct bwi_clock_freq freq;
1398 bwi_get_clock_freq(sc, &freq);
1399 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY,
1400 howmany(freq.clkfreq_max * 150, 1000000));
1401 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY,
1402 howmany(freq.clkfreq_max * 15, 1000000));
1406 return bwi_regwin_switch(sc, old, NULL);
1412 bwi_init_statechg(xsc, 1);
1416 bwi_init_statechg(struct bwi_softc *sc, int statechg)
1418 struct ieee80211com *ic = &sc->sc_ic;
1419 struct ifnet *ifp = &ic->ic_if;
1420 struct bwi_mac *mac;
1423 ASSERT_SERIALIZED(ifp->if_serializer);
1425 error = bwi_stop(sc, statechg);
1427 if_printf(ifp, "can't stop\n");
1431 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
1435 mac = &sc->sc_mac[0];
1436 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL);
1440 error = bwi_mac_init(mac);
1444 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN);
1446 bcopy(IF_LLADDR(ifp), ic->ic_myaddr, sizeof(ic->ic_myaddr));
1448 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */
1449 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, ic->ic_myaddr);
1451 bwi_mac_reset_hwkeys(mac);
1453 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) {
1458 * Drain any possible pending TX status
1460 for (i = 0; i < NRETRY; ++i) {
1461 if ((CSR_READ_4(sc, BWI_TXSTATUS0) &
1462 BWI_TXSTATUS0_VALID) == 0)
1464 CSR_READ_4(sc, BWI_TXSTATUS1);
1467 if_printf(ifp, "can't drain TX status\n");
1471 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G)
1472 bwi_mac_updateslot(mac, 1);
1475 error = bwi_mac_start(mac);
1480 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1482 ifp->if_flags |= IFF_RUNNING;
1483 ifq_clr_oactive(&ifp->if_snd);
1486 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
1487 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)
1488 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
1490 ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
1493 ieee80211_new_state(ic, ic->ic_state, -1);
1503 bwi_ioctl(struct ifnet *ifp, u_long cmd, caddr_t req, struct ucred *cr)
1505 struct bwi_softc *sc = ifp->if_softc;
1508 ASSERT_SERIALIZED(ifp->if_serializer);
1512 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
1513 (IFF_UP | IFF_RUNNING)) {
1514 struct bwi_mac *mac;
1517 KKASSERT(sc->sc_cur_regwin->rw_type ==
1519 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1521 if ((ifp->if_flags & IFF_PROMISC) &&
1522 (sc->sc_flags & BWI_F_PROMISC) == 0) {
1524 sc->sc_flags |= BWI_F_PROMISC;
1525 } else if ((ifp->if_flags & IFF_PROMISC) == 0 &&
1526 (sc->sc_flags & BWI_F_PROMISC)) {
1528 sc->sc_flags &= ~BWI_F_PROMISC;
1532 bwi_mac_set_promisc(mac, promisc);
1535 if (ifp->if_flags & IFF_UP) {
1536 if ((ifp->if_flags & IFF_RUNNING) == 0)
1539 if (ifp->if_flags & IFF_RUNNING)
1544 error = ieee80211_ioctl(&sc->sc_ic, cmd, req, cr);
1548 if (error == ENETRESET) {
1549 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
1550 (IFF_UP | IFF_RUNNING))
1558 bwi_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1560 struct bwi_softc *sc = ifp->if_softc;
1561 struct ieee80211com *ic = &sc->sc_ic;
1562 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
1565 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
1566 ASSERT_SERIALIZED(ifp->if_serializer);
1568 if (ifq_is_oactive(&ifp->if_snd) || (ifp->if_flags & IFF_RUNNING) == 0)
1574 while (tbd->tbd_buf[idx].tb_mbuf == NULL) {
1575 struct ieee80211_frame *wh;
1576 struct ieee80211_node *ni;
1580 if (!IF_QEMPTY(&ic->ic_mgtq)) {
1581 IF_DEQUEUE(&ic->ic_mgtq, m);
1583 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
1584 m->m_pkthdr.rcvif = NULL;
1587 } else if (!ifq_is_empty(&ifp->if_snd)) {
1588 struct ether_header *eh;
1590 if (ic->ic_state != IEEE80211_S_RUN) {
1591 ifq_purge(&ifp->if_snd);
1595 m = ifq_dequeue(&ifp->if_snd);
1599 if (m->m_len < sizeof(*eh)) {
1600 m = m_pullup(m, sizeof(*eh));
1602 IFNET_STAT_INC(ifp, oerrors, 1);
1606 eh = mtod(m, struct ether_header *);
1608 ni = ieee80211_find_txnode(ic, eh->ether_dhost);
1611 IFNET_STAT_INC(ifp, oerrors, 1);
1619 m = ieee80211_encap(ic, m, ni);
1621 ieee80211_free_node(ni);
1622 IFNET_STAT_INC(ifp, oerrors, 1);
1629 if (ic->ic_rawbpf != NULL)
1630 bpf_mtap(ic->ic_rawbpf, m);
1632 wh = mtod(m, struct ieee80211_frame *);
1633 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
1634 if (ieee80211_crypto_encap(ic, ni, m) == NULL) {
1635 ieee80211_free_node(ni);
1637 IFNET_STAT_INC(ifp, oerrors, 1);
1641 wh = NULL; /* Catch any invalid use */
1643 if (bwi_encap(sc, idx, m, &ni, mgt_pkt) != 0) {
1644 /* 'm' is freed in bwi_encap() if we reach here */
1646 ieee80211_free_node(ni);
1647 IFNET_STAT_INC(ifp, oerrors, 1);
1653 idx = (idx + 1) % BWI_TX_NDESC;
1655 if (tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC) {
1656 ifq_set_oactive(&ifp->if_snd);
1663 sc->sc_tx_timer = 5;
1668 bwi_watchdog(struct ifnet *ifp)
1670 struct bwi_softc *sc = ifp->if_softc;
1672 ASSERT_SERIALIZED(ifp->if_serializer);
1676 if ((ifp->if_flags & IFF_RUNNING) == 0)
1679 if (sc->sc_tx_timer) {
1680 if (--sc->sc_tx_timer == 0) {
1681 if_printf(ifp, "watchdog timeout\n");
1682 IFNET_STAT_INC(ifp, oerrors, 1);
1688 ieee80211_watchdog(&sc->sc_ic);
1692 bwi_stop(struct bwi_softc *sc, int state_chg)
1694 struct ieee80211com *ic = &sc->sc_ic;
1695 struct ifnet *ifp = &ic->ic_if;
1696 struct bwi_mac *mac;
1697 int i, error, pwr_off = 0;
1699 ASSERT_SERIALIZED(ifp->if_serializer);
1702 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
1704 bwi_newstate_begin(sc, IEEE80211_S_INIT);
1706 if (ifp->if_flags & IFF_RUNNING) {
1707 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
1708 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1710 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1711 CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1715 for (i = 0; i < sc->sc_nmac; ++i) {
1716 struct bwi_regwin *old_rw;
1718 mac = &sc->sc_mac[i];
1719 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0)
1722 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw);
1726 bwi_mac_shutdown(mac);
1729 bwi_regwin_switch(sc, old_rw, NULL);
1733 bwi_bbp_power_off(sc);
1735 sc->sc_tx_timer = 0;
1737 ifp->if_flags &= ~IFF_RUNNING;
1738 ifq_clr_oactive(&ifp->if_snd);
1745 struct bwi_softc *sc = xsc;
1746 struct bwi_mac *mac;
1747 struct ifnet *ifp = &sc->sc_ic.ic_if;
1748 uint32_t intr_status;
1749 uint32_t txrx_intr_status[BWI_TXRX_NRING];
1750 int i, txrx_error, tx = 0, rx_data = -1;
1752 ASSERT_SERIALIZED(ifp->if_serializer);
1754 if ((ifp->if_flags & IFF_RUNNING) == 0)
1758 * Get interrupt status
1760 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);
1761 if (intr_status == 0xffffffff) /* Not for us */
1764 DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status);
1766 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1767 if (intr_status == 0) /* Nothing is interesting */
1770 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
1771 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1774 DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr");
1775 for (i = 0; i < BWI_TXRX_NRING; ++i) {
1778 if (BWI_TXRX_IS_RX(i))
1779 mask = BWI_TXRX_RX_INTRS;
1781 mask = BWI_TXRX_TX_INTRS;
1783 txrx_intr_status[i] =
1784 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask;
1786 _DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x",
1787 i, txrx_intr_status[i]);
1789 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) {
1790 if_printf(ifp, "intr fatal TX/RX (%d) error 0x%08x\n",
1791 i, txrx_intr_status[i]);
1795 _DPRINTF(sc, BWI_DBG_INTR, "%s\n", "");
1798 * Acknowledge interrupt
1800 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status);
1802 for (i = 0; i < BWI_TXRX_NRING; ++i)
1803 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]);
1805 /* Disable all interrupts */
1806 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1808 if (intr_status & BWI_INTR_PHY_TXERR) {
1809 if (mac->mac_flags & BWI_MAC_F_PHYE_RESET) {
1810 if_printf(ifp, "intr PHY TX error\n");
1811 /* XXX to netisr0? */
1812 bwi_init_statechg(sc, 0);
1818 /* TODO: reset device */
1821 if (intr_status & BWI_INTR_TBTT)
1822 bwi_mac_config_ps(mac);
1824 if (intr_status & BWI_INTR_EO_ATIM)
1825 if_printf(ifp, "EO_ATIM\n");
1827 if (intr_status & BWI_INTR_PMQ) {
1829 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0)
1832 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2);
1835 if (intr_status & BWI_INTR_NOISE)
1836 if_printf(ifp, "intr noise\n");
1838 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX)
1839 rx_data = sc->sc_rxeof(sc);
1841 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) {
1842 sc->sc_txeof_status(sc);
1846 if (intr_status & BWI_INTR_TX_DONE) {
1851 /* Re-enable interrupts */
1852 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1854 if (sc->sc_blink_led != NULL && sc->sc_led_blink) {
1855 int evt = BWI_LED_EVENT_NONE;
1857 if (tx && rx_data > 0) {
1858 if (sc->sc_rx_rate > sc->sc_tx_rate)
1859 evt = BWI_LED_EVENT_RX;
1861 evt = BWI_LED_EVENT_TX;
1863 evt = BWI_LED_EVENT_TX;
1864 } else if (rx_data > 0) {
1865 evt = BWI_LED_EVENT_RX;
1866 } else if (rx_data == 0) {
1867 evt = BWI_LED_EVENT_POLL;
1870 if (evt != BWI_LED_EVENT_NONE)
1871 bwi_led_event(sc, evt);
1876 bwi_newstate_begin(struct bwi_softc *sc, enum ieee80211_state nstate)
1878 callout_stop(&sc->sc_scan_ch);
1879 callout_stop(&sc->sc_calib_ch);
1881 ieee80211_ratectl_newstate(&sc->sc_ic, nstate);
1882 bwi_led_newstate(sc, nstate);
1884 if (nstate == IEEE80211_S_INIT)
1885 sc->sc_txpwrcb_type = BWI_TXPWR_INIT;
1889 bwi_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
1891 struct bwi_softc *sc = ic->ic_if.if_softc;
1892 struct ifnet *ifp = &ic->ic_if;
1895 ASSERT_SERIALIZED(ifp->if_serializer);
1897 bwi_newstate_begin(sc, nstate);
1899 if (nstate == IEEE80211_S_INIT)
1902 error = bwi_set_chan(sc, ic->ic_curchan);
1904 if_printf(ifp, "can't set channel to %u\n",
1905 ieee80211_chan2ieee(ic, ic->ic_curchan));
1909 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
1911 } else if (nstate == IEEE80211_S_RUN) {
1912 struct bwi_mac *mac;
1914 bwi_set_bssid(sc, ic->ic_bss->ni_bssid);
1916 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
1917 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1919 /* Initial TX power calibration */
1920 bwi_mac_calibrate_txpower(mac, BWI_TXPWR_INIT);
1922 sc->sc_txpwrcb_type = BWI_TXPWR_FORCE;
1924 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB;
1927 bwi_set_bssid(sc, bwi_zero_addr);
1931 error = sc->sc_newstate(ic, nstate, arg);
1933 if (nstate == IEEE80211_S_SCAN) {
1934 callout_reset(&sc->sc_scan_ch,
1935 (sc->sc_dwell_time * hz) / 1000,
1937 } else if (nstate == IEEE80211_S_RUN) {
1938 callout_reset(&sc->sc_calib_ch, hz, bwi_calibrate, sc);
1944 bwi_media_change(struct ifnet *ifp)
1948 ASSERT_SERIALIZED(ifp->if_serializer);
1950 error = ieee80211_media_change(ifp);
1951 if (error != ENETRESET)
1954 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING))
1955 bwi_init(ifp->if_softc);
1960 bwi_dma_alloc(struct bwi_softc *sc)
1962 int error, i, has_txstats;
1963 bus_addr_t lowaddr = 0;
1964 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0;
1965 uint32_t txrx_ctrl_step = 0;
1968 for (i = 0; i < sc->sc_nmac; ++i) {
1969 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) {
1975 switch (sc->sc_bus_space) {
1976 case BWI_BUS_SPACE_30BIT:
1977 case BWI_BUS_SPACE_32BIT:
1978 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT)
1979 lowaddr = BWI_BUS_SPACE_MAXADDR;
1981 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1982 desc_sz = sizeof(struct bwi_desc32);
1983 txrx_ctrl_step = 0x20;
1985 sc->sc_init_tx_ring = bwi_init_tx_ring32;
1986 sc->sc_free_tx_ring = bwi_free_tx_ring32;
1987 sc->sc_init_rx_ring = bwi_init_rx_ring32;
1988 sc->sc_free_rx_ring = bwi_free_rx_ring32;
1989 sc->sc_setup_rxdesc = bwi_setup_rx_desc32;
1990 sc->sc_setup_txdesc = bwi_setup_tx_desc32;
1991 sc->sc_rxeof = bwi_rxeof32;
1992 sc->sc_start_tx = bwi_start_tx32;
1994 sc->sc_init_txstats = bwi_init_txstats32;
1995 sc->sc_free_txstats = bwi_free_txstats32;
1996 sc->sc_txeof_status = bwi_txeof_status32;
2000 case BWI_BUS_SPACE_64BIT:
2001 lowaddr = BUS_SPACE_MAXADDR; /* XXX */
2002 desc_sz = sizeof(struct bwi_desc64);
2003 txrx_ctrl_step = 0x40;
2005 sc->sc_init_tx_ring = bwi_init_tx_ring64;
2006 sc->sc_free_tx_ring = bwi_free_tx_ring64;
2007 sc->sc_init_rx_ring = bwi_init_rx_ring64;
2008 sc->sc_free_rx_ring = bwi_free_rx_ring64;
2009 sc->sc_setup_rxdesc = bwi_setup_rx_desc64;
2010 sc->sc_setup_txdesc = bwi_setup_tx_desc64;
2011 sc->sc_rxeof = bwi_rxeof64;
2012 sc->sc_start_tx = bwi_start_tx64;
2014 sc->sc_init_txstats = bwi_init_txstats64;
2015 sc->sc_free_txstats = bwi_free_txstats64;
2016 sc->sc_txeof_status = bwi_txeof_status64;
2021 KKASSERT(lowaddr != 0);
2022 KKASSERT(desc_sz != 0);
2023 KKASSERT(txrx_ctrl_step != 0);
2025 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN);
2026 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN);
2029 * Create top level DMA tag
2031 error = bus_dma_tag_create(NULL, BWI_ALIGN, 0,
2032 lowaddr, BUS_SPACE_MAXADDR,
2035 BUS_SPACE_UNRESTRICTED,
2036 BUS_SPACE_MAXSIZE_32BIT,
2037 0, &sc->sc_parent_dtag);
2039 device_printf(sc->sc_dev, "can't create parent DMA tag\n");
2043 #define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step)
2046 * Create TX ring DMA stuffs
2048 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_RING_ALIGN, 0,
2049 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2051 tx_ring_sz, 1, BUS_SPACE_MAXSIZE_32BIT,
2052 0, &sc->sc_txring_dtag);
2054 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n");
2058 for (i = 0; i < BWI_TX_NRING; ++i) {
2059 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag,
2060 &sc->sc_tx_rdata[i], tx_ring_sz,
2063 device_printf(sc->sc_dev, "%dth TX ring "
2064 "DMA alloc failed\n", i);
2070 * Create RX ring DMA stuffs
2072 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_RING_ALIGN, 0,
2073 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2075 rx_ring_sz, 1, BUS_SPACE_MAXSIZE_32BIT,
2076 0, &sc->sc_rxring_dtag);
2078 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n");
2082 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata,
2083 rx_ring_sz, TXRX_CTRL(0));
2085 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n");
2090 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz);
2092 device_printf(sc->sc_dev,
2093 "TX stats DMA alloc failed\n");
2100 return bwi_dma_mbuf_create(sc);
2104 bwi_dma_free(struct bwi_softc *sc)
2106 if (sc->sc_txring_dtag != NULL) {
2109 for (i = 0; i < BWI_TX_NRING; ++i) {
2110 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i];
2112 if (rd->rdata_desc != NULL) {
2113 bus_dmamap_unload(sc->sc_txring_dtag,
2115 bus_dmamem_free(sc->sc_txring_dtag,
2120 bus_dma_tag_destroy(sc->sc_txring_dtag);
2123 if (sc->sc_rxring_dtag != NULL) {
2124 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2126 if (rd->rdata_desc != NULL) {
2127 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap);
2128 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc,
2131 bus_dma_tag_destroy(sc->sc_rxring_dtag);
2134 bwi_dma_txstats_free(sc);
2135 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1);
2137 if (sc->sc_parent_dtag != NULL)
2138 bus_dma_tag_destroy(sc->sc_parent_dtag);
2142 bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag,
2143 struct bwi_ring_data *rd, bus_size_t size,
2148 error = bus_dmamem_alloc(dtag, &rd->rdata_desc,
2149 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2152 device_printf(sc->sc_dev, "can't allocate DMA mem\n");
2156 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size,
2157 bwi_dma_ring_addr, &rd->rdata_paddr,
2160 device_printf(sc->sc_dev, "can't load DMA mem\n");
2161 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap);
2162 rd->rdata_desc = NULL;
2166 rd->rdata_txrx_ctrl = txrx_ctrl;
2171 bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base,
2174 struct bwi_txstats_data *st;
2175 bus_size_t dma_size;
2178 st = kmalloc(sizeof(*st), M_DEVBUF, M_WAITOK | M_ZERO);
2179 sc->sc_txstats = st;
2182 * Create TX stats descriptor DMA stuffs
2184 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN);
2186 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_RING_ALIGN, 0,
2187 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2189 dma_size, 1, BUS_SPACE_MAXSIZE_32BIT,
2190 0, &st->stats_ring_dtag);
2192 device_printf(sc->sc_dev, "can't create txstats ring "
2197 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring,
2198 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2199 &st->stats_ring_dmap);
2201 device_printf(sc->sc_dev, "can't allocate txstats ring "
2203 bus_dma_tag_destroy(st->stats_ring_dtag);
2204 st->stats_ring_dtag = NULL;
2208 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap,
2209 st->stats_ring, dma_size,
2210 bwi_dma_ring_addr, &st->stats_ring_paddr,
2213 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n");
2214 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2215 st->stats_ring_dmap);
2216 bus_dma_tag_destroy(st->stats_ring_dtag);
2217 st->stats_ring_dtag = NULL;
2222 * Create TX stats DMA stuffs
2224 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC,
2227 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_ALIGN, 0,
2228 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2230 dma_size, 1, BUS_SPACE_MAXSIZE_32BIT,
2231 0, &st->stats_dtag);
2233 device_printf(sc->sc_dev, "can't create txstats DMA tag\n");
2237 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats,
2238 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2241 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n");
2242 bus_dma_tag_destroy(st->stats_dtag);
2243 st->stats_dtag = NULL;
2247 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats,
2248 dma_size, bwi_dma_ring_addr, &st->stats_paddr,
2251 device_printf(sc->sc_dev, "can't load txstats DMA mem\n");
2252 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2253 bus_dma_tag_destroy(st->stats_dtag);
2254 st->stats_dtag = NULL;
2258 st->stats_ctrl_base = ctrl_base;
2263 bwi_dma_txstats_free(struct bwi_softc *sc)
2265 struct bwi_txstats_data *st;
2267 if (sc->sc_txstats == NULL)
2269 st = sc->sc_txstats;
2271 if (st->stats_ring_dtag != NULL) {
2272 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap);
2273 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2274 st->stats_ring_dmap);
2275 bus_dma_tag_destroy(st->stats_ring_dtag);
2278 if (st->stats_dtag != NULL) {
2279 bus_dmamap_unload(st->stats_dtag, st->stats_dmap);
2280 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2281 bus_dma_tag_destroy(st->stats_dtag);
2284 kfree(st, M_DEVBUF);
2288 bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
2290 KASSERT(nseg == 1, ("too many segments"));
2291 *((bus_addr_t *)arg) = seg->ds_addr;
2295 bwi_dma_mbuf_create(struct bwi_softc *sc)
2297 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2298 int i, j, k, ntx, error;
2301 * Create TX/RX mbuf DMA tag
2303 error = bus_dma_tag_create(sc->sc_parent_dtag, 1, 0,
2304 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2305 NULL, NULL, MCLBYTES, 1,
2306 BUS_SPACE_MAXSIZE_32BIT,
2307 0, &sc->sc_buf_dtag);
2309 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n");
2316 * Create TX mbuf DMA map
2318 for (i = 0; i < BWI_TX_NRING; ++i) {
2319 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2321 for (j = 0; j < BWI_TX_NDESC; ++j) {
2322 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2323 &tbd->tbd_buf[j].tb_dmap);
2325 device_printf(sc->sc_dev, "can't create "
2326 "%dth tbd, %dth DMA map\n", i, j);
2329 for (k = 0; k < j; ++k) {
2330 bus_dmamap_destroy(sc->sc_buf_dtag,
2331 tbd->tbd_buf[k].tb_dmap);
2340 * Create RX mbuf DMA map and a spare DMA map
2342 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2343 &rbd->rbd_tmp_dmap);
2345 device_printf(sc->sc_dev,
2346 "can't create spare RX buf DMA map\n");
2350 for (j = 0; j < BWI_RX_NDESC; ++j) {
2351 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2352 &rbd->rbd_buf[j].rb_dmap);
2354 device_printf(sc->sc_dev, "can't create %dth "
2355 "RX buf DMA map\n", j);
2357 for (k = 0; k < j; ++k) {
2358 bus_dmamap_destroy(sc->sc_buf_dtag,
2359 rbd->rbd_buf[j].rb_dmap);
2361 bus_dmamap_destroy(sc->sc_buf_dtag,
2369 bwi_dma_mbuf_destroy(sc, ntx, 0);
2374 bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx)
2378 if (sc->sc_buf_dtag == NULL)
2381 for (i = 0; i < ntx; ++i) {
2382 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2384 for (j = 0; j < BWI_TX_NDESC; ++j) {
2385 struct bwi_txbuf *tb = &tbd->tbd_buf[j];
2387 if (tb->tb_mbuf != NULL) {
2388 bus_dmamap_unload(sc->sc_buf_dtag,
2390 m_freem(tb->tb_mbuf);
2392 if (tb->tb_ni != NULL)
2393 ieee80211_free_node(tb->tb_ni);
2394 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap);
2399 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2401 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap);
2402 for (j = 0; j < BWI_RX_NDESC; ++j) {
2403 struct bwi_rxbuf *rb = &rbd->rbd_buf[j];
2405 if (rb->rb_mbuf != NULL) {
2406 bus_dmamap_unload(sc->sc_buf_dtag,
2408 m_freem(rb->rb_mbuf);
2410 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap);
2414 bus_dma_tag_destroy(sc->sc_buf_dtag);
2415 sc->sc_buf_dtag = NULL;
2419 bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs)
2421 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs);
2425 bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs)
2427 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs);
2431 bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx)
2433 struct bwi_ring_data *rd;
2434 struct bwi_txbuf_data *tbd;
2435 uint32_t val, addr_hi, addr_lo;
2437 KKASSERT(ring_idx < BWI_TX_NRING);
2438 rd = &sc->sc_tx_rdata[ring_idx];
2439 tbd = &sc->sc_tx_bdata[ring_idx];
2444 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC);
2445 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
2446 BUS_DMASYNC_PREWRITE);
2448 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2449 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2451 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2452 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2453 BWI_TXRX32_RINGINFO_FUNC_MASK);
2454 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val);
2456 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2457 BWI_TXRX32_CTRL_ENABLE;
2458 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val);
2464 bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base,
2465 bus_addr_t paddr, int hdr_size, int ndesc)
2467 uint32_t val, addr_hi, addr_lo;
2469 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2470 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2472 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2473 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2474 BWI_TXRX32_RINGINFO_FUNC_MASK);
2475 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val);
2477 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) |
2478 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2479 BWI_TXRX32_CTRL_ENABLE;
2480 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val);
2482 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
2483 (ndesc - 1) * sizeof(struct bwi_desc32));
2487 bwi_init_rx_ring32(struct bwi_softc *sc)
2489 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2492 sc->sc_rx_bdata.rbd_idx = 0;
2494 for (i = 0; i < BWI_RX_NDESC; ++i) {
2495 error = bwi_newbuf(sc, i, 1);
2497 if_printf(&sc->sc_ic.ic_if,
2498 "can't allocate %dth RX buffer\n", i);
2502 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2503 BUS_DMASYNC_PREWRITE);
2505 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr,
2506 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC);
2511 bwi_init_txstats32(struct bwi_softc *sc)
2513 struct bwi_txstats_data *st = sc->sc_txstats;
2514 bus_addr_t stats_paddr;
2517 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats));
2518 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE);
2522 stats_paddr = st->stats_paddr;
2523 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) {
2524 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i,
2525 stats_paddr, sizeof(struct bwi_txstats), 0);
2526 stats_paddr += sizeof(struct bwi_txstats);
2528 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap,
2529 BUS_DMASYNC_PREWRITE);
2531 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base,
2532 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC);
2537 bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2540 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2542 KKASSERT(buf_idx < BWI_RX_NDESC);
2543 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx,
2548 bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd,
2549 int buf_idx, bus_addr_t paddr, int buf_len)
2551 KKASSERT(buf_idx < BWI_TX_NDESC);
2552 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx,
2557 bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx)
2564 bwi_init_rx_ring64(struct bwi_softc *sc)
2571 bwi_init_txstats64(struct bwi_softc *sc)
2578 bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2585 bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd,
2586 int buf_idx, bus_addr_t paddr, int buf_len)
2592 bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg,
2593 bus_size_t mapsz __unused, int error)
2596 KASSERT(nseg == 1, ("too many segments(%d)", nseg));
2597 *((bus_addr_t *)arg) = seg->ds_addr;
2602 bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init)
2604 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2605 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx];
2606 struct bwi_rxbuf_hdr *hdr;
2612 KKASSERT(buf_idx < BWI_RX_NDESC);
2614 m = m_getcl(init ? M_WAITOK : M_NOWAIT, MT_DATA, M_PKTHDR);
2619 * If the NIC is up and running, we need to:
2620 * - Clear RX buffer's header.
2621 * - Restore RX descriptor settings.
2628 m->m_len = m->m_pkthdr.len = MCLBYTES;
2631 * Try to load RX buf into temporary DMA map
2633 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m,
2634 bwi_dma_buf_addr, &paddr,
2635 init ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT);
2640 * See the comment above
2649 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap);
2651 rxbuf->rb_paddr = paddr;
2654 * Swap RX buf's DMA map with the loaded temporary one
2656 map = rxbuf->rb_dmap;
2657 rxbuf->rb_dmap = rbd->rbd_tmp_dmap;
2658 rbd->rbd_tmp_dmap = map;
2662 * Clear RX buf header
2664 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *);
2665 bzero(hdr, sizeof(*hdr));
2666 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE);
2669 * Setup RX buf descriptor
2671 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr,
2672 rxbuf->rb_mbuf->m_len - sizeof(*hdr));
2677 bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs,
2678 const uint8_t *addr)
2682 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL,
2683 BWI_ADDR_FILTER_CTRL_SET | addr_ofs);
2685 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) {
2688 addr_val = (uint16_t)addr[i * 2] |
2689 (((uint16_t)addr[(i * 2) + 1]) << 8);
2690 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val);
2695 bwi_set_chan(struct bwi_softc *sc, struct ieee80211_channel *c)
2697 struct ieee80211com *ic = &sc->sc_ic;
2699 struct ifnet *ifp = &ic->ic_if;
2701 struct bwi_mac *mac;
2705 ASSERT_SERIALIZED(ifp->if_serializer);
2707 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
2708 mac = (struct bwi_mac *)sc->sc_cur_regwin;
2710 chan = ieee80211_chan2ieee(ic, c);
2712 bwi_rf_set_chan(mac, chan, 0);
2715 * Setup radio tap channel freq and flags
2717 if (IEEE80211_IS_CHAN_G(c))
2718 flags = IEEE80211_CHAN_G;
2720 flags = IEEE80211_CHAN_B;
2722 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq =
2723 htole16(c->ic_freq);
2724 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags =
2731 bwi_next_scan(void *xsc)
2733 struct bwi_softc *sc = xsc;
2734 struct ieee80211com *ic = &sc->sc_ic;
2735 struct ifnet *ifp = &ic->ic_if;
2737 lwkt_serialize_enter(ifp->if_serializer);
2739 if (ic->ic_state == IEEE80211_S_SCAN)
2740 ieee80211_next_scan(ic);
2742 lwkt_serialize_exit(ifp->if_serializer);
2746 bwi_rxeof(struct bwi_softc *sc, int end_idx)
2748 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2749 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2750 struct ieee80211com *ic = &sc->sc_ic;
2751 struct ifnet *ifp = &ic->ic_if;
2752 int idx, rx_data = 0;
2755 while (idx != end_idx) {
2756 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx];
2757 struct bwi_rxbuf_hdr *hdr;
2758 struct ieee80211_frame_min *wh;
2759 struct ieee80211_node *ni;
2763 int buflen, wh_ofs, hdr_extra, rssi, type, rate;
2766 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap,
2767 BUS_DMASYNC_POSTREAD);
2769 if (bwi_newbuf(sc, idx, 0)) {
2770 IFNET_STAT_INC(ifp, ierrors, 1);
2774 hdr = mtod(m, struct bwi_rxbuf_hdr *);
2775 flags2 = le16toh(hdr->rxh_flags2);
2778 if (flags2 & BWI_RXH_F2_TYPE2FRAME)
2780 wh_ofs = hdr_extra + 6; /* XXX magic number */
2782 buflen = le16toh(hdr->rxh_buflen);
2783 if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) {
2784 if_printf(ifp, "short frame %d, hdr_extra %d\n",
2786 IFNET_STAT_INC(ifp, ierrors, 1);
2791 plcp = ((const uint8_t *)(hdr + 1) + hdr_extra);
2792 rssi = bwi_calc_rssi(sc, hdr);
2794 m->m_pkthdr.rcvif = ifp;
2795 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr);
2796 m_adj(m, sizeof(*hdr) + wh_ofs);
2798 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM)
2799 rate = bwi_ofdm_plcp2rate(plcp);
2801 rate = bwi_ds_plcp2rate(plcp);
2804 if (sc->sc_drvbpf != NULL)
2805 bwi_rx_radiotap(sc, m, hdr, plcp, rate, rssi);
2807 m_adj(m, -IEEE80211_CRC_LEN);
2809 wh = mtod(m, struct ieee80211_frame_min *);
2810 ni = ieee80211_find_rxnode(ic, wh);
2812 type = ieee80211_input(ic, m, ni, rssi - BWI_NOISE_FLOOR,
2813 le16toh(hdr->rxh_tsf));
2814 ieee80211_free_node(ni);
2816 if (type == IEEE80211_FC0_TYPE_DATA) {
2818 sc->sc_rx_rate = rate;
2821 idx = (idx + 1) % BWI_RX_NDESC;
2825 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2826 BUS_DMASYNC_PREWRITE);
2831 bwi_rxeof32(struct bwi_softc *sc)
2833 uint32_t val, rx_ctrl;
2834 int end_idx, rx_data;
2836 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl;
2838 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2839 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
2840 sizeof(struct bwi_desc32);
2842 rx_data = bwi_rxeof(sc, end_idx);
2844 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX,
2845 end_idx * sizeof(struct bwi_desc32));
2851 bwi_rxeof64(struct bwi_softc *sc)
2858 bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl)
2862 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0);
2866 for (i = 0; i < NRETRY; ++i) {
2869 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2870 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) ==
2871 BWI_RX32_STATUS_STATE_DISABLED)
2877 if_printf(&sc->sc_ic.ic_if, "reset rx ring timedout\n");
2881 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0);
2885 bwi_free_txstats32(struct bwi_softc *sc)
2887 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base);
2891 bwi_free_rx_ring32(struct bwi_softc *sc)
2893 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2894 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2897 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl);
2899 for (i = 0; i < BWI_RX_NDESC; ++i) {
2900 struct bwi_rxbuf *rb = &rbd->rbd_buf[i];
2902 if (rb->rb_mbuf != NULL) {
2903 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap);
2904 m_freem(rb->rb_mbuf);
2911 bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx)
2913 struct bwi_ring_data *rd;
2914 struct bwi_txbuf_data *tbd;
2915 struct ifnet *ifp = &sc->sc_ic.ic_if;
2916 uint32_t state, val;
2919 KKASSERT(ring_idx < BWI_TX_NRING);
2920 rd = &sc->sc_tx_rdata[ring_idx];
2921 tbd = &sc->sc_tx_bdata[ring_idx];
2925 for (i = 0; i < NRETRY; ++i) {
2926 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2927 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2928 if (state == BWI_TX32_STATUS_STATE_DISABLED ||
2929 state == BWI_TX32_STATUS_STATE_IDLE ||
2930 state == BWI_TX32_STATUS_STATE_STOPPED)
2936 if_printf(ifp, "wait for TX ring(%d) stable timed out\n",
2940 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0);
2941 for (i = 0; i < NRETRY; ++i) {
2942 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2943 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2944 if (state == BWI_TX32_STATUS_STATE_DISABLED)
2950 if_printf(ifp, "reset TX ring (%d) timed out\n", ring_idx);
2956 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0);
2958 for (i = 0; i < BWI_TX_NDESC; ++i) {
2959 struct bwi_txbuf *tb = &tbd->tbd_buf[i];
2961 if (tb->tb_mbuf != NULL) {
2962 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
2963 m_freem(tb->tb_mbuf);
2966 if (tb->tb_ni != NULL) {
2967 ieee80211_free_node(tb->tb_ni);
2974 bwi_free_txstats64(struct bwi_softc *sc)
2980 bwi_free_rx_ring64(struct bwi_softc *sc)
2986 bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx)
2992 bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m,
2993 struct ieee80211_node **ni0, int mgt_pkt)
2995 struct ieee80211com *ic = &sc->sc_ic;
2996 struct ieee80211_node *ni = *ni0;
2997 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING];
2998 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
2999 struct bwi_txbuf *tb = &tbd->tbd_buf[idx];
3000 struct bwi_mac *mac;
3001 struct bwi_txbuf_hdr *hdr;
3002 struct ieee80211_frame *wh;
3003 uint8_t rate, rate_fb;
3007 int pkt_len, error, mcast_pkt = 0;
3013 KKASSERT(ni != NULL);
3014 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3015 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3017 wh = mtod(m, struct ieee80211_frame *);
3019 /* Get 802.11 frame len before prepending TX header */
3020 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN;
3025 bzero(tb->tb_rateidx, sizeof(tb->tb_rateidx));
3027 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) {
3030 rate = IEEE80211_RS_RATE(&ni->ni_rates,
3033 if (ic->ic_fixed_rate >= 1)
3034 idx = ic->ic_fixed_rate - 1;
3037 rate_fb = IEEE80211_RS_RATE(&ni->ni_rates, idx);
3039 tb->tb_rateidx_cnt = ieee80211_ratectl_findrate(ni,
3040 m->m_pkthdr.len, tb->tb_rateidx, BWI_NTXRATE);
3042 rate = IEEE80211_RS_RATE(&ni->ni_rates,
3044 if (tb->tb_rateidx_cnt == BWI_NTXRATE) {
3045 rate_fb = IEEE80211_RS_RATE(&ni->ni_rates,
3050 tb->tb_buflen = m->m_pkthdr.len;
3053 /* Fixed at 1Mbits/s for mgt frames */
3054 rate = rate_fb = (1 * 2);
3057 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
3058 rate = rate_fb = ic->ic_mcast_rate;
3062 if (rate == 0 || rate_fb == 0) {
3063 /* XXX this should not happen */
3064 if_printf(&ic->ic_if, "invalid rate %u or fallback rate %u",
3066 rate = rate_fb = (1 * 2); /* Force 1Mbits/s */
3068 sc->sc_tx_rate = rate;
3073 if (sc->sc_drvbpf != NULL) {
3074 sc->sc_tx_th.wt_flags = 0;
3075 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED)
3076 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3077 if (ieee80211_rate2modtype(rate) == IEEE80211_MODTYPE_DS &&
3078 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
3080 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3082 sc->sc_tx_th.wt_rate = rate;
3084 bpf_ptap(sc->sc_drvbpf, m, &sc->sc_tx_th, sc->sc_tx_th_len);
3088 * Setup the embedded TX header
3090 M_PREPEND(m, sizeof(*hdr), M_NOWAIT);
3092 if_printf(&ic->ic_if, "prepend TX header failed\n");
3095 hdr = mtod(m, struct bwi_txbuf_hdr *);
3097 bzero(hdr, sizeof(*hdr));
3099 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc));
3100 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1));
3106 ack_rate = ieee80211_ack_rate(ni, rate_fb);
3107 dur = ieee80211_txtime(ni,
3108 sizeof(struct ieee80211_frame_ack) + IEEE80211_CRC_LEN,
3109 ack_rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE);
3111 hdr->txh_fb_duration = htole16(dur);
3114 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) |
3115 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK);
3117 bwi_plcp_header(hdr->txh_plcp, pkt_len, rate);
3118 bwi_plcp_header(hdr->txh_fb_plcp, pkt_len, rate_fb);
3120 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,
3121 BWI_TXH_PHY_C_ANTMODE_MASK);
3122 if (ieee80211_rate2modtype(rate) == IEEE80211_MODTYPE_OFDM)
3123 phy_ctrl |= BWI_TXH_PHY_C_OFDM;
3124 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1))
3125 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE;
3127 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG;
3128 if (!IEEE80211_IS_MULTICAST(wh->i_addr1))
3129 mac_ctrl |= BWI_TXH_MAC_C_ACK;
3130 if (ieee80211_rate2modtype(rate_fb) == IEEE80211_MODTYPE_OFDM)
3131 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM;
3133 hdr->txh_mac_ctrl = htole32(mac_ctrl);
3134 hdr->txh_phy_ctrl = htole16(phy_ctrl);
3136 /* Catch any further usage */
3141 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3142 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
3143 if (error && error != EFBIG) {
3144 if_printf(&ic->ic_if, "can't load TX buffer (1) %d\n", error);
3148 if (error) { /* error == EFBIG */
3151 m_new = m_defrag(m, M_NOWAIT);
3152 if (m_new == NULL) {
3153 if_printf(&ic->ic_if, "can't defrag TX buffer\n");
3160 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3161 bwi_dma_buf_addr, &paddr,
3164 if_printf(&ic->ic_if, "can't load TX buffer (2) %d\n",
3171 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE);
3173 if (mgt_pkt || mcast_pkt) {
3174 /* Don't involve mcast/mgt packets into TX rate control */
3175 ieee80211_free_node(ni);
3182 p = mtod(m, const uint8_t *);
3183 for (i = 0; i < m->m_pkthdr.len; ++i) {
3184 if (i != 0 && i % 8 == 0)
3186 kprintf("%02x ", p[i]);
3191 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n",
3192 idx, pkt_len, m->m_pkthdr.len);
3194 /* Setup TX descriptor */
3195 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len);
3196 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
3197 BUS_DMASYNC_PREWRITE);
3200 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx);
3209 bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3211 idx = (idx + 1) % BWI_TX_NDESC;
3212 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX,
3213 idx * sizeof(struct bwi_desc32));
3217 bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3223 bwi_txeof_status32(struct bwi_softc *sc)
3225 struct ifnet *ifp = &sc->sc_ic.ic_if;
3226 uint32_t val, ctrl_base;
3229 ctrl_base = sc->sc_txstats->stats_ctrl_base;
3231 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS);
3232 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
3233 sizeof(struct bwi_desc32);
3235 bwi_txeof_status(sc, end_idx);
3237 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
3238 end_idx * sizeof(struct bwi_desc32));
3240 if (!ifq_is_oactive(&ifp->if_snd))
3245 bwi_txeof_status64(struct bwi_softc *sc)
3251 _bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt)
3253 struct ifnet *ifp = &sc->sc_ic.ic_if;
3254 struct bwi_txbuf_data *tbd;
3255 struct bwi_txbuf *tb;
3256 int ring_idx, buf_idx;
3259 if_printf(ifp, "zero tx id\n");
3263 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK);
3264 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK);
3266 KKASSERT(ring_idx == BWI_TX_DATA_RING);
3267 KKASSERT(buf_idx < BWI_TX_NDESC);
3269 tbd = &sc->sc_tx_bdata[ring_idx];
3270 KKASSERT(tbd->tbd_used > 0);
3273 tb = &tbd->tbd_buf[buf_idx];
3275 DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, "
3276 "acked %d, data_txcnt %d, ni %p\n",
3277 buf_idx, acked, data_txcnt, tb->tb_ni);
3279 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
3280 m_freem(tb->tb_mbuf);
3283 if (tb->tb_ni != NULL) {
3284 struct ieee80211_ratectl_res res[BWI_NTXRATE];
3287 if (data_txcnt <= BWI_SHRETRY_FB || tb->tb_rateidx_cnt == 1) {
3289 res[0].rc_res_rateidx = tb->tb_rateidx[0];
3290 res[0].rc_res_tries = data_txcnt;
3292 res_len = BWI_NTXRATE;
3293 res[0].rc_res_rateidx = tb->tb_rateidx[0];
3294 res[0].rc_res_tries = BWI_SHRETRY_FB;
3295 res[1].rc_res_rateidx = tb->tb_rateidx[1];
3296 res[1].rc_res_tries = data_txcnt - BWI_SHRETRY_FB;
3300 IFNET_STAT_INC(ifp, opackets, 1);
3301 retry = data_txcnt > 0 ? data_txcnt - 1 : 0;
3303 IFNET_STAT_INC(ifp, oerrors, 1);
3307 ieee80211_ratectl_tx_complete(tb->tb_ni, tb->tb_buflen,
3308 res, res_len, retry, 0, !acked);
3310 ieee80211_free_node(tb->tb_ni);
3313 /* XXX mgt packet error */
3314 IFNET_STAT_INC(ifp, opackets, 1);
3317 if (tbd->tbd_used == 0)
3318 sc->sc_tx_timer = 0;
3320 ifq_clr_oactive(&ifp->if_snd);
3324 bwi_txeof_status(struct bwi_softc *sc, int end_idx)
3326 struct bwi_txstats_data *st = sc->sc_txstats;
3329 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD);
3331 idx = st->stats_idx;
3332 while (idx != end_idx) {
3333 const struct bwi_txstats *stats = &st->stats[idx];
3335 if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) {
3338 data_txcnt = __SHIFTOUT(stats->txs_txcnt,
3339 BWI_TXS_TXCNT_DATA);
3340 _bwi_txeof(sc, le16toh(stats->txs_id),
3341 stats->txs_flags & BWI_TXS_F_ACKED,
3344 idx = (idx + 1) % BWI_TXSTATS_NDESC;
3346 st->stats_idx = idx;
3350 bwi_txeof(struct bwi_softc *sc)
3352 struct ifnet *ifp = &sc->sc_ic.ic_if;
3355 uint32_t tx_status0, tx_status1;
3359 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0);
3360 if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0)
3362 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1);
3364 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK);
3365 data_txcnt = __SHIFTOUT(tx_status0,
3366 BWI_TXSTATUS0_DATA_TXCNT_MASK);
3368 if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING))
3371 _bwi_txeof(sc, tx_id, tx_status0 & BWI_TXSTATUS0_ACKED,
3375 if (!ifq_is_oactive(&ifp->if_snd))
3380 bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
3382 bwi_power_on(sc, 1);
3383 return bwi_set_clock_mode(sc, clk_mode);
3387 bwi_bbp_power_off(struct bwi_softc *sc)
3389 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW);
3390 bwi_power_off(sc, 1);
3394 bwi_get_pwron_delay(struct bwi_softc *sc)
3396 struct bwi_regwin *com, *old;
3397 struct bwi_clock_freq freq;
3401 com = &sc->sc_com_regwin;
3402 KKASSERT(BWI_REGWIN_EXIST(com));
3404 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
3407 error = bwi_regwin_switch(sc, com, &old);
3411 bwi_get_clock_freq(sc, &freq);
3413 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY);
3414 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min);
3415 DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay);
3417 return bwi_regwin_switch(sc, old, NULL);
3421 bwi_bus_attach(struct bwi_softc *sc)
3423 struct bwi_regwin *bus, *old;
3426 bus = &sc->sc_bus_regwin;
3428 error = bwi_regwin_switch(sc, bus, &old);
3432 if (!bwi_regwin_is_enabled(sc, bus))
3433 bwi_regwin_enable(sc, bus, 0);
3435 /* Disable interripts */
3436 CSR_WRITE_4(sc, BWI_INTRVEC, 0);
3438 return bwi_regwin_switch(sc, old, NULL);
3442 bwi_regwin_name(const struct bwi_regwin *rw)
3444 switch (rw->rw_type) {
3445 case BWI_REGWIN_T_COM:
3447 case BWI_REGWIN_T_BUSPCI:
3449 case BWI_REGWIN_T_MAC:
3451 case BWI_REGWIN_T_BUSPCIE:
3454 panic("unknown regwin type 0x%04x", rw->rw_type);
3459 bwi_regwin_disable_bits(struct bwi_softc *sc)
3463 /* XXX cache this */
3464 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK);
3465 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC,
3466 "bus rev %u\n", busrev);
3468 if (busrev == BWI_BUSREV_0)
3469 return BWI_STATE_LO_DISABLE1;
3470 else if (busrev == BWI_BUSREV_1)
3471 return BWI_STATE_LO_DISABLE2;
3473 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2);
3477 bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw)
3479 uint32_t val, disable_bits;
3481 disable_bits = bwi_regwin_disable_bits(sc);
3482 val = CSR_READ_4(sc, BWI_STATE_LO);
3484 if ((val & (BWI_STATE_LO_CLOCK |
3485 BWI_STATE_LO_RESET |
3486 disable_bits)) == BWI_STATE_LO_CLOCK) {
3487 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n",
3488 bwi_regwin_name(rw));
3491 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n",
3492 bwi_regwin_name(rw));
3498 bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3500 uint32_t state_lo, disable_bits;
3503 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3506 * If current regwin is in 'reset' state, it was already disabled.
3508 if (state_lo & BWI_STATE_LO_RESET) {
3509 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT,
3510 "%s was already disabled\n", bwi_regwin_name(rw));
3514 disable_bits = bwi_regwin_disable_bits(sc);
3517 * Disable normal clock
3519 state_lo = BWI_STATE_LO_CLOCK | disable_bits;
3520 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3523 * Wait until normal clock is disabled
3526 for (i = 0; i < NRETRY; ++i) {
3527 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3528 if (state_lo & disable_bits)
3533 device_printf(sc->sc_dev, "%s disable clock timeout\n",
3534 bwi_regwin_name(rw));
3537 for (i = 0; i < NRETRY; ++i) {
3540 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3541 if ((state_hi & BWI_STATE_HI_BUSY) == 0)
3546 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n",
3547 bwi_regwin_name(rw));
3552 * Reset and disable regwin with gated clock
3554 state_lo = BWI_STATE_LO_RESET | disable_bits |
3555 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK |
3556 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3557 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3559 /* Flush pending bus write */
3560 CSR_READ_4(sc, BWI_STATE_LO);
3563 /* Reset and disable regwin */
3564 state_lo = BWI_STATE_LO_RESET | disable_bits |
3565 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3566 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3568 /* Flush pending bus write */
3569 CSR_READ_4(sc, BWI_STATE_LO);
3574 bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3576 uint32_t state_lo, state_hi, imstate;
3578 bwi_regwin_disable(sc, rw, flags);
3580 /* Reset regwin with gated clock */
3581 state_lo = BWI_STATE_LO_RESET |
3582 BWI_STATE_LO_CLOCK |
3583 BWI_STATE_LO_GATED_CLOCK |
3584 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3585 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3587 /* Flush pending bus write */
3588 CSR_READ_4(sc, BWI_STATE_LO);
3591 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3592 if (state_hi & BWI_STATE_HI_SERROR)
3593 CSR_WRITE_4(sc, BWI_STATE_HI, 0);
3595 imstate = CSR_READ_4(sc, BWI_IMSTATE);
3596 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) {
3597 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT);
3598 CSR_WRITE_4(sc, BWI_IMSTATE, imstate);
3601 /* Enable regwin with gated clock */
3602 state_lo = BWI_STATE_LO_CLOCK |
3603 BWI_STATE_LO_GATED_CLOCK |
3604 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3605 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3607 /* Flush pending bus write */
3608 CSR_READ_4(sc, BWI_STATE_LO);
3611 /* Enable regwin with normal clock */
3612 state_lo = BWI_STATE_LO_CLOCK |
3613 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3614 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3616 /* Flush pending bus write */
3617 CSR_READ_4(sc, BWI_STATE_LO);
3622 bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid)
3624 struct ieee80211com *ic = &sc->sc_ic;
3625 struct bwi_mac *mac;
3626 struct bwi_myaddr_bssid buf;
3631 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3632 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3634 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid);
3636 bcopy(ic->ic_myaddr, buf.myaddr, sizeof(buf.myaddr));
3637 bcopy(bssid, buf.bssid, sizeof(buf.bssid));
3639 n = sizeof(buf) / sizeof(val);
3640 p = (const uint8_t *)&buf;
3641 for (i = 0; i < n; ++i) {
3645 for (j = 0; j < sizeof(val); ++j)
3646 val |= ((uint32_t)(*p++)) << (j * 8);
3648 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val);
3653 bwi_updateslot(struct ifnet *ifp)
3655 struct bwi_softc *sc = ifp->if_softc;
3656 struct ieee80211com *ic = &sc->sc_ic;
3657 struct bwi_mac *mac;
3659 if ((ifp->if_flags & IFF_RUNNING) == 0)
3662 ASSERT_SERIALIZED(ifp->if_serializer);
3664 DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__);
3666 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3667 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3669 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT));
3673 bwi_calibrate(void *xsc)
3675 struct bwi_softc *sc = xsc;
3676 struct ieee80211com *ic = &sc->sc_ic;
3677 struct ifnet *ifp = &ic->ic_if;
3679 lwkt_serialize_enter(ifp->if_serializer);
3681 if (ic->ic_state == IEEE80211_S_RUN) {
3682 struct bwi_mac *mac;
3684 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3685 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3687 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
3688 bwi_mac_calibrate_txpower(mac, sc->sc_txpwrcb_type);
3689 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB;
3692 /* XXX 15 seconds */
3693 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc);
3696 lwkt_serialize_exit(ifp->if_serializer);
3700 bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr)
3702 struct bwi_mac *mac;
3704 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3705 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3707 return bwi_rf_calc_rssi(mac, hdr);
3711 bwi_rx_radiotap(struct bwi_softc *sc, struct mbuf *m,
3712 struct bwi_rxbuf_hdr *hdr, const void *plcp,
3715 const struct ieee80211_frame_min *wh;
3717 KKASSERT(sc->sc_drvbpf != NULL);
3719 sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS;
3720 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_SHPREAMBLE)
3721 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3723 wh = mtod(m, const struct ieee80211_frame_min *);
3724 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED)
3725 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP;
3727 sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian convertion */
3728 sc->sc_rx_th.wr_rate = rate;
3729 sc->sc_rx_th.wr_antsignal = rssi;
3730 sc->sc_rx_th.wr_antnoise = BWI_NOISE_FLOOR;
3732 bpf_ptap(sc->sc_drvbpf, m, &sc->sc_rx_th, sc->sc_rx_th_len);
3736 bwi_led_attach(struct bwi_softc *sc)
3738 const uint8_t *led_act = NULL;
3739 uint16_t gpio, val[BWI_LED_MAX];
3742 for (i = 0; i < NELEM(bwi_vendor_led_act); ++i) {
3743 if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) {
3744 led_act = bwi_vendor_led_act[i].led_act;
3748 if (led_act == NULL)
3749 led_act = bwi_default_led_act;
3751 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01);
3752 val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0);
3753 val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1);
3755 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23);
3756 val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2);
3757 val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3);
3759 for (i = 0; i < BWI_LED_MAX; ++i) {
3760 struct bwi_led *led = &sc->sc_leds[i];
3762 if (val[i] == 0xff) {
3763 led->l_act = led_act[i];
3765 if (val[i] & BWI_LED_ACT_LOW)
3766 led->l_flags |= BWI_LED_F_ACTLOW;
3767 led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK);
3769 led->l_mask = (1 << i);
3771 if (led->l_act == BWI_LED_ACT_BLINK_SLOW ||
3772 led->l_act == BWI_LED_ACT_BLINK_POLL ||
3773 led->l_act == BWI_LED_ACT_BLINK) {
3774 led->l_flags |= BWI_LED_F_BLINK;
3775 if (led->l_act == BWI_LED_ACT_BLINK_POLL)
3776 led->l_flags |= BWI_LED_F_POLLABLE;
3777 else if (led->l_act == BWI_LED_ACT_BLINK_SLOW)
3778 led->l_flags |= BWI_LED_F_SLOW;
3780 if (sc->sc_blink_led == NULL) {
3781 sc->sc_blink_led = led;
3782 if (led->l_flags & BWI_LED_F_SLOW)
3783 BWI_LED_SLOWDOWN(sc->sc_led_idle);
3787 DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH,
3788 "%dth led, act %d, lowact %d\n", i,
3789 led->l_act, led->l_flags & BWI_LED_F_ACTLOW);
3791 callout_init(&sc->sc_led_blink_ch);
3794 static __inline uint16_t
3795 bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on)
3797 if (led->l_flags & BWI_LED_F_ACTLOW)
3802 val &= ~led->l_mask;
3807 bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate)
3809 struct ieee80211com *ic = &sc->sc_ic;
3813 if (nstate == IEEE80211_S_INIT) {
3814 callout_stop(&sc->sc_led_blink_ch);
3815 sc->sc_led_blinking = 0;
3818 if ((ic->ic_if.if_flags & IFF_RUNNING) == 0)
3821 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3822 for (i = 0; i < BWI_LED_MAX; ++i) {
3823 struct bwi_led *led = &sc->sc_leds[i];
3826 if (led->l_act == BWI_LED_ACT_UNKN ||
3827 led->l_act == BWI_LED_ACT_NULL)
3830 if ((led->l_flags & BWI_LED_F_BLINK) &&
3831 nstate != IEEE80211_S_INIT)
3834 switch (led->l_act) {
3835 case BWI_LED_ACT_ON: /* Always on */
3838 case BWI_LED_ACT_OFF: /* Always off */
3839 case BWI_LED_ACT_5GHZ: /* TODO: 11A */
3845 case IEEE80211_S_INIT:
3848 case IEEE80211_S_RUN:
3849 if (led->l_act == BWI_LED_ACT_11G &&
3850 ic->ic_curmode != IEEE80211_MODE_11G)
3854 if (led->l_act == BWI_LED_ACT_ASSOC)
3861 val = bwi_led_onoff(led, val, on);
3863 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3867 bwi_led_event(struct bwi_softc *sc, int event)
3869 struct bwi_led *led = sc->sc_blink_led;
3872 if (event == BWI_LED_EVENT_POLL) {
3873 if ((led->l_flags & BWI_LED_F_POLLABLE) == 0)
3875 if (ticks - sc->sc_led_ticks < sc->sc_led_idle)
3879 sc->sc_led_ticks = ticks;
3880 if (sc->sc_led_blinking)
3884 case BWI_LED_EVENT_RX:
3885 rate = sc->sc_rx_rate;
3887 case BWI_LED_EVENT_TX:
3888 rate = sc->sc_tx_rate;
3890 case BWI_LED_EVENT_POLL:
3894 panic("unknown LED event %d", event);
3897 bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur,
3898 bwi_led_duration[rate].off_dur);
3902 bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur)
3904 struct bwi_led *led = sc->sc_blink_led;
3907 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3908 val = bwi_led_onoff(led, val, 1);
3909 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3911 if (led->l_flags & BWI_LED_F_SLOW) {
3912 BWI_LED_SLOWDOWN(on_dur);
3913 BWI_LED_SLOWDOWN(off_dur);
3916 sc->sc_led_blinking = 1;
3917 sc->sc_led_blink_offdur = off_dur;
3919 callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc);
3923 bwi_led_blink_next(void *xsc)
3925 struct bwi_softc *sc = xsc;
3928 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3929 val = bwi_led_onoff(sc->sc_blink_led, val, 0);
3930 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3932 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur,
3933 bwi_led_blink_end, sc);
3937 bwi_led_blink_end(void *xsc)
3939 struct bwi_softc *sc = xsc;
3941 sc->sc_led_blinking = 0;
3945 bwi_ratectl_attach(struct ieee80211com *ic, u_int rc)
3947 struct bwi_softc *sc = ic->ic_if.if_softc;
3950 case IEEE80211_RATECTL_ONOE:
3951 return &sc->sc_onoe_param;
3952 case IEEE80211_RATECTL_NONE:
3953 /* This could only happen during detaching */
3956 panic("unknown rate control algo %u", rc);