sys/dev/netif/ath/ath/if_ath_rx_edma.c

   1 /*-
   2  * Copyright (c) 2012 Adrian Chadd <adrian@FreeBSD.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer,
  10  *    without modification.
  11  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  12  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
  13  *    redistribution must be conditioned upon including a substantially
  14  *    similar Disclaimer requirement for further binary redistribution.
  15  *
  16  * NO WARRANTY
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
  20  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
  21  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
  22  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  23  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  24  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
  25  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  26  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  27  * THE POSSIBILITY OF SUCH DAMAGES.
  28  */
  29
  30 #include <sys/cdefs.h>
  31
  32 /*
  33  * Driver for the Atheros Wireless LAN controller.
  34  *
  35  * This software is derived from work of Atsushi Onoe; his contribution
  36  * is greatly appreciated.
  37  */
  38
  39 #include "opt_inet.h"
  40 #include "opt_ath.h"
  41 /*
  42  * This is needed for register operations which are performed
  43  * by the driver - eg, calls to ath_hal_gettsf32().
  44  *
  45  * It's also required for any AH_DEBUG checks in here, eg the
  46  * module dependencies.
  47  */
  48 #include "opt_ah.h"
  49 #include "opt_wlan.h"
  50
  51 #include <sys/param.h>
  52 #include <sys/systm.h>
  53 #include <sys/sysctl.h>
  54 #include <sys/mbuf.h>
  55 #include <sys/malloc.h>
  56 #include <sys/lock.h>
  57 #include <sys/mutex.h>
  58 #include <sys/kernel.h>
  59 #include <sys/socket.h>
  60 #include <sys/sockio.h>
  61 #include <sys/errno.h>
  62 #include <sys/callout.h>
  63 #include <sys/bus.h>
  64 #include <sys/endian.h>
  65 #include <sys/kthread.h>
  66 #include <sys/taskqueue.h>
  67 #include <sys/priv.h>
  68 #include <sys/module.h>
  69 #include <sys/ktr.h>
  70
  71 #include <net/if.h>
  72 #include <net/if_var.h>
  73 #include <net/if_dl.h>
  74 #include <net/if_media.h>
  75 #include <net/if_types.h>
  76 #include <net/if_arp.h>
  77 #include <net/ethernet.h>
  78 #include <net/if_llc.h>
  79 #include <net/ifq_var.h>
  80
  81 #include <netproto/802_11/ieee80211_var.h>
  82 #include <netproto/802_11/ieee80211_regdomain.h>
  83 #ifdef IEEE80211_SUPPORT_SUPERG
  84 #include <netproto/802_11/ieee80211_superg.h>
  85 #endif
  86 #ifdef IEEE80211_SUPPORT_TDMA
  87 #include <netproto/802_11/ieee80211_tdma.h>
  88 #endif
  89
  90 #include <net/bpf.h>
  91
  92 #ifdef INET
  93 #include <netinet/in.h>
  94 #include <netinet/if_ether.h>
  95 #endif
  96
  97 #include <dev/netif/ath/ath/if_athvar.h>
  98 #include <dev/netif/ath/ath_hal/ah_devid.h>             /* XXX for softled */
  99 #include <dev/netif/ath/ath_hal/ah_diagcodes.h>
 100
 101 #include <dev/netif/ath/ath/if_ath_debug.h>
 102 #include <dev/netif/ath/ath/if_ath_misc.h>
 103 #include <dev/netif/ath/ath/if_ath_tsf.h>
 104 #include <dev/netif/ath/ath/if_ath_tx.h>
 105 #include <dev/netif/ath/ath/if_ath_sysctl.h>
 106 #include <dev/netif/ath/ath/if_ath_led.h>
 107 #include <dev/netif/ath/ath/if_ath_keycache.h>
 108 #include <dev/netif/ath/ath/if_ath_rx.h>
 109 #include <dev/netif/ath/ath/if_ath_beacon.h>
 110 #include <dev/netif/ath/ath/if_athdfs.h>
 111
 112 #ifdef ATH_TX99_DIAG
 113 #include <dev/netif/ath/ath_tx99/ath_tx99.h>
 114 #endif
 115
 116 #include <dev/netif/ath/ath/if_ath_rx_edma.h>
 117
 118 #ifdef  ATH_DEBUG_ALQ
 119 #include <dev/netif/ath/ath/if_ath_alq.h>
 120 #endif
 121
 122 /*
 123  * some general macros
 124   */
 125 #define INCR(_l, _sz)           (_l) ++; (_l) &= ((_sz) - 1)
 126 #define DECR(_l, _sz)           (_l) --; (_l) &= ((_sz) - 1)
 127
 128 MALLOC_DECLARE(M_ATHDEV);
 129
 130 /*
 131  * XXX TODO:
 132  *
 133  * + Make sure the FIFO is correctly flushed and reinitialised
 134  *   through a reset;
 135  * + Verify multi-descriptor frames work!
 136  * + There's a "memory use after free" which needs to be tracked down
 137  *   and fixed ASAP.  I've seen this in the legacy path too, so it
 138  *   may be a generic RX path issue.
 139  */
 140
 141 /*
 142  * XXX shuffle the function orders so these pre-declarations aren't
 143  * required!
 144  */
 145 static  int ath_edma_rxfifo_alloc(struct ath_softc *sc, HAL_RX_QUEUE qtype,
 146             int nbufs);
 147 static  int ath_edma_rxfifo_flush(struct ath_softc *sc, HAL_RX_QUEUE qtype);
 148 static  void ath_edma_rxbuf_free(struct ath_softc *sc, struct ath_buf *bf);
 149 static  void ath_edma_recv_proc_queue(struct ath_softc *sc,
 150             HAL_RX_QUEUE qtype, int dosched);
 151 static  int ath_edma_recv_proc_deferred_queue(struct ath_softc *sc,
 152             HAL_RX_QUEUE qtype, int dosched);
 153
 154 static void
 155 ath_edma_stoprecv(struct ath_softc *sc, int dodelay)
 156 {
 157         struct ath_hal *ah = sc->sc_ah;
 158
 159         ATH_RX_LOCK(sc);
 160         ath_hal_stoppcurecv(ah);
 161         ath_hal_setrxfilter(ah, 0);
 162         ath_hal_stopdmarecv(ah);
 163
 164         DELAY(3000);
 165
 166         /* Flush RX pending for each queue */
 167         /* XXX should generic-ify this */
 168         if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending) {
 169                 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending);
 170                 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL;
 171         }
 172
 173         if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending) {
 174                 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending);
 175                 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL;
 176         }
 177         ATH_RX_UNLOCK(sc);
 178 }
 179
 180 /*
 181  * Re-initialise the FIFO given the current buffer contents.
 182  * Specifically, walk from head -> tail, pushing the FIFO contents
 183  * back into the FIFO.
 184  */
 185 static void
 186 ath_edma_reinit_fifo(struct ath_softc *sc, HAL_RX_QUEUE qtype)
 187 {
 188         struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
 189         struct ath_buf *bf;
 190         int i, j;
 191
 192         ATH_RX_LOCK_ASSERT(sc);
 193
 194         i = re->m_fifo_head;
 195         for (j = 0; j < re->m_fifo_depth; j++) {
 196                 bf = re->m_fifo[i];
 197                 DPRINTF(sc, ATH_DEBUG_EDMA_RX,
 198                     "%s: Q%d: pos=%i, addr=0x%jx\n",
 199                     __func__,
 200                     qtype,
 201                     i,
 202                     (uintmax_t)bf->bf_daddr);
 203                 ath_hal_putrxbuf(sc->sc_ah, bf->bf_daddr, qtype);
 204                 INCR(i, re->m_fifolen);
 205         }
 206
 207         /* Ensure this worked out right */
 208         if (i != re->m_fifo_tail) {
 209                 device_printf(sc->sc_dev, "%s: i (%d) != tail! (%d)\n",
 210                     __func__,
 211                     i,
 212                     re->m_fifo_tail);
 213         }
 214 }
 215
 216 /*
 217  * Start receive.
 218  *
 219  * XXX TODO: this needs to reallocate the FIFO entries when a reset
 220  * occurs, in case the FIFO is filled up and no new descriptors get
 221  * thrown into the FIFO.
 222  */
 223 static int
 224 ath_edma_startrecv(struct ath_softc *sc)
 225 {
 226         struct ath_hal *ah = sc->sc_ah;
 227
 228         ATH_RX_LOCK(sc);
 229
 230         /* Enable RX FIFO */
 231         ath_hal_rxena(ah);
 232
 233         /*
 234          * Entries should only be written out if the
 235          * FIFO is empty.
 236          *
 237          * XXX This isn't correct. I should be looking
 238          * at the value of AR_RXDP_SIZE (0x0070) to determine
 239          * how many entries are in here.
 240          *
 241          * A warm reset will clear the registers but not the FIFO.
 242          *
 243          * And I believe this is actually the address of the last
 244          * handled buffer rather than the current FIFO pointer.
 245          * So if no frames have been (yet) seen, we'll reinit the
 246          * FIFO.
 247          *
 248          * I'll chase that up at some point.
 249          */
 250         if (ath_hal_getrxbuf(sc->sc_ah, HAL_RX_QUEUE_HP) == 0) {
 251                 DPRINTF(sc, ATH_DEBUG_EDMA_RX,
 252                     "%s: Re-initing HP FIFO\n", __func__);
 253                 ath_edma_reinit_fifo(sc, HAL_RX_QUEUE_HP);
 254         }
 255         if (ath_hal_getrxbuf(sc->sc_ah, HAL_RX_QUEUE_LP) == 0) {
 256                 DPRINTF(sc, ATH_DEBUG_EDMA_RX,
 257                     "%s: Re-initing LP FIFO\n", __func__);
 258                 ath_edma_reinit_fifo(sc, HAL_RX_QUEUE_LP);
 259         }
 260
 261         /* Add up to m_fifolen entries in each queue */
 262         /*
 263          * These must occur after the above write so the FIFO buffers
 264          * are pushed/tracked in the same order as the hardware will
 265          * process them.
 266          */
 267         ath_edma_rxfifo_alloc(sc, HAL_RX_QUEUE_HP,
 268             sc->sc_rxedma[HAL_RX_QUEUE_HP].m_fifolen);
 269
 270         ath_edma_rxfifo_alloc(sc, HAL_RX_QUEUE_LP,
 271             sc->sc_rxedma[HAL_RX_QUEUE_LP].m_fifolen);
 272
 273         ath_mode_init(sc);
 274         ath_hal_startpcurecv(ah);
 275
 276         ATH_RX_UNLOCK(sc);
 277
 278         return (0);
 279 }
 280
 281 static void
 282 ath_edma_recv_sched_queue(struct ath_softc *sc, HAL_RX_QUEUE qtype,
 283     int dosched)
 284 {
 285         ath_power_set_power_state(sc, HAL_PM_AWAKE);
 286         ath_edma_recv_proc_queue(sc, qtype, dosched);
 287         ath_power_restore_power_state(sc);
 288
 289         taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
 290 }
 291
 292 static void
 293 ath_edma_recv_sched(struct ath_softc *sc, int dosched)
 294 {
 295         ath_power_set_power_state(sc, HAL_PM_AWAKE);
 296         ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_HP, dosched);
 297         ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_LP, dosched);
 298         ath_power_restore_power_state(sc);
 299
 300         taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
 301 }
 302
 303 static void
 304 ath_edma_recv_flush(struct ath_softc *sc)
 305 {
 306
 307         DPRINTF(sc, ATH_DEBUG_RECV, "%s: called\n", __func__);
 308
 309         ATH_PCU_LOCK(sc);
 310         sc->sc_rxproc_cnt++;
 311         ATH_PCU_UNLOCK(sc);
 312
 313         ath_power_set_power_state(sc, HAL_PM_AWAKE);
 314
 315         /*
 316          * Flush any active frames from FIFO -> deferred list
 317          */
 318         ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_HP, 0);
 319         ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_LP, 0);
 320
 321         /*
 322          * Process what's in the deferred queue
 323          */
 324         /*
 325          * XXX: If we read the tsf/channoise here and then pass it in,
 326          * we could restore the power state before processing
 327          * the deferred queue.
 328          */
 329         ath_edma_recv_proc_deferred_queue(sc, HAL_RX_QUEUE_HP, 0);
 330         ath_edma_recv_proc_deferred_queue(sc, HAL_RX_QUEUE_LP, 0);
 331
 332         ath_power_restore_power_state(sc);
 333
 334         ATH_PCU_LOCK(sc);
 335         sc->sc_rxproc_cnt--;
 336         ATH_PCU_UNLOCK(sc);
 337 }
 338
 339 /*
 340  * Process frames from the current queue into the deferred queue.
 341  */
 342 static void
 343 ath_edma_recv_proc_queue(struct ath_softc *sc, HAL_RX_QUEUE qtype,
 344     int dosched)
 345 {
 346         struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
 347         struct ath_rx_status *rs;
 348         struct ath_desc *ds;
 349         struct ath_buf *bf;
 350         struct mbuf *m;
 351         struct ath_hal *ah = sc->sc_ah;
 352         uint64_t tsf;
 353         uint16_t nf;
 354         int npkts = 0;
 355
 356         tsf = ath_hal_gettsf64(ah);
 357         nf = ath_hal_getchannoise(ah, sc->sc_curchan);
 358         sc->sc_stats.ast_rx_noise = nf;
 359
 360         ATH_RX_LOCK(sc);
 361
 362         do {
 363                 bf = re->m_fifo[re->m_fifo_head];
 364                 /* This shouldn't occur! */
 365                 if (bf == NULL) {
 366                         device_printf(sc->sc_dev, "%s: Q%d: NULL bf?\n",
 367                             __func__,
 368                             qtype);
 369                         break;
 370                 }
 371                 m = bf->bf_m;
 372                 ds = bf->bf_desc;
 373
 374                 /*
 375                  * Sync descriptor memory - this also syncs the buffer for us.
 376                  * EDMA descriptors are in cached memory.
 377                  */
 378                 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
 379                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 380                 rs = &bf->bf_status.ds_rxstat;
 381                 bf->bf_rxstatus = ath_hal_rxprocdesc(ah, ds, bf->bf_daddr,
 382                     NULL, rs);
 383 #ifdef  ATH_DEBUG
 384                 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
 385                         ath_printrxbuf(sc, bf, 0, bf->bf_rxstatus == HAL_OK);
 386 #endif /* ATH_DEBUG */
 387 #ifdef  ATH_DEBUG_ALQ
 388                 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS))
 389                         if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS,
 390                             sc->sc_rx_statuslen, (char *) ds);
 391 #endif /* ATH_DEBUG */
 392                 if (bf->bf_rxstatus == HAL_EINPROGRESS) {
 393                         DPRINTF(sc, ATH_DEBUG_EDMA_RX,
 394                             "%s: Q%d: still in-prog!\n", __func__, qtype);
 395                         break;
 396                 }
 397
 398                 /*
 399                  * Completed descriptor.
 400                  */
 401                 DPRINTF(sc, ATH_DEBUG_EDMA_RX,
 402                     "%s: Q%d: completed!\n", __func__, qtype);
 403                 npkts++;
 404
 405                 /*
 406                  * We've been synced already, so unmap.
 407                  */
 408                 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
 409
 410                 /*
 411                  * Remove the FIFO entry and place it on the completion
 412                  * queue.
 413                  */
 414                 re->m_fifo[re->m_fifo_head] = NULL;
 415                 TAILQ_INSERT_TAIL(&sc->sc_rx_rxlist[qtype], bf, bf_list);
 416
 417                 /* Bump the descriptor FIFO stats */
 418                 INCR(re->m_fifo_head, re->m_fifolen);
 419                 re->m_fifo_depth--;
 420                 /* XXX check it doesn't fall below 0 */
 421         } while (re->m_fifo_depth > 0);
 422
 423         /* Append some more fresh frames to the FIFO */
 424         if (dosched)
 425                 ath_edma_rxfifo_alloc(sc, qtype, re->m_fifolen);
 426
 427         ATH_RX_UNLOCK(sc);
 428
 429         /* rx signal state monitoring */
 430         ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan);
 431
 432         ATH_KTR(sc, ATH_KTR_INTERRUPTS, 1,
 433             "ath edma rx proc: npkts=%d\n",
 434             npkts);
 435
 436         /* Handle resched and kickpcu appropriately */
 437         ATH_PCU_LOCK(sc);
 438         if (dosched && sc->sc_kickpcu) {
 439                 ATH_KTR(sc, ATH_KTR_ERROR, 0,
 440                     "ath_edma_recv_proc_queue(): kickpcu");
 441                 if (npkts > 0)
 442                         device_printf(sc->sc_dev,
 443                             "%s: handled npkts %d\n",
 444                             __func__, npkts);
 445
 446                 /*
 447                  * XXX TODO: what should occur here? Just re-poke and
 448                  * re-enable the RX FIFO?
 449                  */
 450                 sc->sc_kickpcu = 0;
 451         }
 452         ATH_PCU_UNLOCK(sc);
 453
 454         return;
 455 }
 456
 457 /*
 458  * Flush the deferred queue.
 459  *
 460  * This destructively flushes the deferred queue - it doesn't
 461  * call the wireless stack on each mbuf.
 462  */
 463 static void
 464 ath_edma_flush_deferred_queue(struct ath_softc *sc)
 465 {
 466         struct ath_buf *bf;
 467
 468         ATH_RX_LOCK_ASSERT(sc);
 469
 470         /* Free in one set, inside the lock */
 471         while ((bf = TAILQ_FIRST(&sc->sc_rx_rxlist[HAL_RX_QUEUE_LP])) != NULL) {
 472                 TAILQ_REMOVE(&sc->sc_rx_rxlist[HAL_RX_QUEUE_LP], bf, bf_list);
 473                 ath_edma_rxbuf_free(sc, bf);
 474         }
 475         while ((bf = TAILQ_FIRST(&sc->sc_rx_rxlist[HAL_RX_QUEUE_HP])) != NULL) {
 476                 TAILQ_REMOVE(&sc->sc_rx_rxlist[HAL_RX_QUEUE_HP], bf, bf_list);
 477                 ath_edma_rxbuf_free(sc, bf);
 478         }
 479 }
 480
 481 static int
 482 ath_edma_recv_proc_deferred_queue(struct ath_softc *sc, HAL_RX_QUEUE qtype,
 483     int dosched)
 484 {
 485         int ngood = 0;
 486         uint64_t tsf;
 487         struct ath_buf *bf;
 488         struct ath_buf *next;
 489         struct ath_rx_status *rs;
 490         int16_t nf;
 491         ath_bufhead rxlist;
 492         struct mbuf *m;
 493
 494         TAILQ_INIT(&rxlist);
 495
 496         nf = ath_hal_getchannoise(sc->sc_ah, sc->sc_curchan);
 497         /*
 498          * XXX TODO: the NF/TSF should be stamped on the bufs themselves,
 499          * otherwise we may end up adding in the wrong values if this
 500          * is delayed too far..
 501          */
 502         tsf = ath_hal_gettsf64(sc->sc_ah);
 503
 504         /* Copy the list over */
 505         ATH_RX_LOCK(sc);
 506         TAILQ_CONCAT(&rxlist, &sc->sc_rx_rxlist[qtype], bf_list);
 507         ATH_RX_UNLOCK(sc);
 508
 509         /* Handle the completed descriptors */
 510         TAILQ_FOREACH_MUTABLE(bf, &rxlist, bf_list, next) {
 511                 /*
 512                  * Skip the RX descriptor status - start at the data offset
 513                  */
 514                 m_adj(bf->bf_m, sc->sc_rx_statuslen);
 515
 516                 /* Handle the frame */
 517
 518                 rs = &bf->bf_status.ds_rxstat;
 519                 m = bf->bf_m;
 520                 bf->bf_m = NULL;
 521                 if (ath_rx_pkt(sc, rs, bf->bf_rxstatus, tsf, nf, qtype, bf, m))
 522                         ngood++;
 523         }
 524
 525         if (ngood) {
 526                 sc->sc_lastrx = tsf;
 527         }
 528
 529         ATH_KTR(sc, ATH_KTR_INTERRUPTS, 1,
 530             "ath edma rx deferred proc: ngood=%d\n",
 531             ngood);
 532
 533         /* Free in one set, inside the lock */
 534         ATH_RX_LOCK(sc);
 535
 536         while ((bf = TAILQ_FIRST(&rxlist)) != NULL) {
 537                 /* Free the buffer/mbuf */
 538                 TAILQ_REMOVE(&rxlist, bf, bf_list);
 539                 ath_edma_rxbuf_free(sc, bf);
 540         }
 541         ATH_RX_UNLOCK(sc);
 542
 543         return (ngood);
 544 }
 545
 546 static void
 547 ath_edma_recv_tasklet(void *arg, int npending)
 548 {
 549         struct ath_softc *sc = (struct ath_softc *) arg;
 550         struct ifnet *ifp = sc->sc_ifp;
 551 #ifdef  IEEE80211_SUPPORT_SUPERG
 552         struct ieee80211com *ic = ifp->if_l2com;
 553 #endif
 554
 555         DPRINTF(sc, ATH_DEBUG_EDMA_RX, "%s: called; npending=%d\n",
 556             __func__,
 557             npending);
 558
 559         wlan_serialize_enter();
 560         ATH_PCU_LOCK(sc);
 561         if (sc->sc_inreset_cnt > 0) {
 562                 device_printf(sc->sc_dev, "%s: sc_inreset_cnt > 0; skipping\n",
 563                     __func__);
 564                 ATH_PCU_UNLOCK(sc);
 565                 wlan_serialize_exit();
 566                 return;
 567         }
 568         sc->sc_rxproc_cnt++;
 569         ATH_PCU_UNLOCK(sc);
 570
 571         ath_power_set_power_state(sc, HAL_PM_AWAKE);
 572
 573         ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_HP, 1);
 574         ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_LP, 1);
 575
 576         ath_edma_recv_proc_deferred_queue(sc, HAL_RX_QUEUE_HP, 1);
 577         ath_edma_recv_proc_deferred_queue(sc, HAL_RX_QUEUE_LP, 1);
 578
 579         /*
 580          * XXX: If we read the tsf/channoise here and then pass it in,
 581          * we could restore the power state before processing
 582          * the deferred queue.
 583          */
 584         ath_power_restore_power_state(sc);
 585
 586         /* XXX inside IF_LOCK ? */
 587         if (!ifq_is_oactive(&ifp->if_snd)) {
 588 #ifdef  IEEE80211_SUPPORT_SUPERG
 589                 ieee80211_ff_age_all(ic, 100);
 590 #endif
 591                 if (!ifq_is_empty(&ifp->if_snd))
 592                         ath_tx_kick(sc);
 593         }
 594         if (ath_dfs_tasklet_needed(sc, sc->sc_curchan))
 595                 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask);
 596
 597         ATH_PCU_LOCK(sc);
 598         sc->sc_rxproc_cnt--;
 599         ATH_PCU_UNLOCK(sc);
 600         wlan_serialize_exit();
 601 }
 602
 603 /*
 604  * Allocate an RX mbuf for the given ath_buf and initialise
 605  * it for EDMA.
 606  *
 607  * + Allocate a 4KB mbuf;
 608  * + Setup the DMA map for the given buffer;
 609  * + Return that.
 610  */
 611 static int
 612 ath_edma_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf)
 613 {
 614
 615         struct mbuf *m;
 616         int error;
 617         int len;
 618
 619         ATH_RX_LOCK_ASSERT(sc);
 620
 621         m = m_getjcl(MB_DONTWAIT, MT_DATA, M_PKTHDR, sc->sc_edma_bufsize);
 622 /*      m = m_getcl(MB_WAIT, MT_DATA, M_PKTHDR);*/
 623 /*      m = m_getm(NULL, sc->sc_edma_bufsize, MB_WAIT, MT_DATA);*/
 624         if (! m)
 625                 return (ENOBUFS);               /* XXX ?*/
 626
 627         /* XXX warn/enforce alignment */
 628
 629         len = m->m_ext.ext_size;
 630 #if 0
 631         device_printf(sc->sc_dev, "%s: called: m=%p, size=%d, mtod=%p\n",
 632             __func__,
 633             m,
 634             len,
 635             mtod(m, char *));
 636 #endif
 637
 638         m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
 639
 640         /*
 641          * Populate ath_buf fields.
 642          */
 643         bf->bf_desc = mtod(m, struct ath_desc *);
 644         bf->bf_lastds = bf->bf_desc;    /* XXX only really for TX? */
 645         bf->bf_m = m;
 646
 647         /*
 648          * Zero the descriptor and ensure it makes it out to the
 649          * bounce buffer if one is required.
 650          *
 651          * XXX PREWRITE will copy the whole buffer; we only needed it
 652          * to sync the first 32 DWORDS.  Oh well.
 653          */
 654         memset(bf->bf_desc, '\0', sc->sc_rx_statuslen);
 655
 656         /*
 657          * Create DMA mapping.
 658          */
 659         error = bus_dmamap_load_mbuf_segment(sc->sc_dmat,
 660             bf->bf_dmamap, m, bf->bf_segs, 1, &bf->bf_nseg, BUS_DMA_NOWAIT);
 661
 662         if (error != 0) {
 663                 device_printf(sc->sc_dev, "%s: failed; error=%d\n",
 664                     __func__,
 665                     error);
 666                 m_freem(m);
 667                 return (error);
 668         }
 669
 670         /*
 671          * Set daddr to the physical mapping page.
 672          */
 673         bf->bf_daddr = bf->bf_segs[0].ds_addr;
 674
 675         /*
 676          * Prepare for the upcoming read.
 677          *
 678          * We need to both sync some data into the buffer (the zero'ed
 679          * descriptor payload) and also prepare for the read that's going
 680          * to occur.
 681          */
 682         bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
 683             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 684
 685         /* Finish! */
 686         return (0);
 687 }
 688
 689 /*
 690  * Allocate a RX buffer.
 691  */
 692 static struct ath_buf *
 693 ath_edma_rxbuf_alloc(struct ath_softc *sc)
 694 {
 695         struct ath_buf *bf;
 696         int error;
 697
 698         ATH_RX_LOCK_ASSERT(sc);
 699
 700         /* Allocate buffer */
 701         bf = TAILQ_FIRST(&sc->sc_rxbuf);
 702         /* XXX shouldn't happen upon startup? */
 703         if (bf == NULL) {
 704                 device_printf(sc->sc_dev, "%s: nothing on rxbuf?!\n",
 705                     __func__);
 706                 return (NULL);
 707         }
 708
 709         /* Remove it from the free list */
 710         TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list);
 711
 712         /* Assign RX mbuf to it */
 713         error = ath_edma_rxbuf_init(sc, bf);
 714         if (error != 0) {
 715                 device_printf(sc->sc_dev,
 716                     "%s: bf=%p, rxbuf alloc failed! error=%d\n",
 717                     __func__,
 718                     bf,
 719                     error);
 720                 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
 721                 return (NULL);
 722         }
 723
 724         return (bf);
 725 }
 726
 727 static void
 728 ath_edma_rxbuf_free(struct ath_softc *sc, struct ath_buf *bf)
 729 {
 730
 731         ATH_RX_LOCK_ASSERT(sc);
 732
 733         /*
 734          * Only unload the frame if we haven't consumed
 735          * the mbuf via ath_rx_pkt().
 736          */
 737         if (bf->bf_m) {
 738                 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
 739                 m_freem(bf->bf_m);
 740                 bf->bf_m = NULL;
 741         }
 742
 743         /* XXX lock? */
 744         TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
 745 }
 746
 747 /*
 748  * Allocate up to 'n' entries and push them onto the hardware FIFO.
 749  *
 750  * Return how many entries were successfully pushed onto the
 751  * FIFO.
 752  */
 753 static int
 754 ath_edma_rxfifo_alloc(struct ath_softc *sc, HAL_RX_QUEUE qtype, int nbufs)
 755 {
 756         struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
 757         struct ath_buf *bf;
 758         int i;
 759
 760         ATH_RX_LOCK_ASSERT(sc);
 761
 762         /*
 763          * Allocate buffers until the FIFO is full or nbufs is reached.
 764          */
 765         for (i = 0; i < nbufs && re->m_fifo_depth < re->m_fifolen; i++) {
 766                 /* Ensure the FIFO is already blank, complain loudly! */
 767                 if (re->m_fifo[re->m_fifo_tail] != NULL) {
 768                         device_printf(sc->sc_dev,
 769                             "%s: Q%d: fifo[%d] != NULL (%p)\n",
 770                             __func__,
 771                             qtype,
 772                             re->m_fifo_tail,
 773                             re->m_fifo[re->m_fifo_tail]);
 774
 775                         /* Free the slot */
 776                         ath_edma_rxbuf_free(sc, re->m_fifo[re->m_fifo_tail]);
 777                         re->m_fifo_depth--;
 778                         /* XXX check it's not < 0 */
 779                         re->m_fifo[re->m_fifo_tail] = NULL;
 780                 }
 781
 782                 bf = ath_edma_rxbuf_alloc(sc);
 783                 /* XXX should ensure the FIFO is not NULL? */
 784                 if (bf == NULL) {
 785                         device_printf(sc->sc_dev,
 786                             "%s: Q%d: alloc failed: i=%d, nbufs=%d?\n",
 787                             __func__,
 788                             qtype,
 789                             i,
 790                             nbufs);
 791                         break;
 792                 }
 793
 794                 re->m_fifo[re->m_fifo_tail] = bf;
 795
 796                 /* Write to the RX FIFO */
 797                 DPRINTF(sc, ATH_DEBUG_EDMA_RX,
 798                     "%s: Q%d: putrxbuf=%p (0x%jx)\n",
 799                     __func__,
 800                     qtype,
 801                     bf->bf_desc,
 802                     (uintmax_t) bf->bf_daddr);
 803                 ath_hal_putrxbuf(sc->sc_ah, bf->bf_daddr, qtype);
 804
 805                 re->m_fifo_depth++;
 806                 INCR(re->m_fifo_tail, re->m_fifolen);
 807         }
 808
 809         /*
 810          * Return how many were allocated.
 811          */
 812         DPRINTF(sc, ATH_DEBUG_EDMA_RX, "%s: Q%d: nbufs=%d, nalloced=%d\n",
 813             __func__,
 814             qtype,
 815             nbufs,
 816             i);
 817         return (i);
 818 }
 819
 820 static int
 821 ath_edma_rxfifo_flush(struct ath_softc *sc, HAL_RX_QUEUE qtype)
 822 {
 823         struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
 824         int i;
 825
 826         ATH_RX_LOCK_ASSERT(sc);
 827
 828         for (i = 0; i < re->m_fifolen; i++) {
 829                 if (re->m_fifo[i] != NULL) {
 830 #ifdef  ATH_DEBUG
 831                         struct ath_buf *bf = re->m_fifo[i];
 832
 833                         if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
 834                                 ath_printrxbuf(sc, bf, 0, HAL_OK);
 835 #endif
 836                         ath_edma_rxbuf_free(sc, re->m_fifo[i]);
 837                         re->m_fifo[i] = NULL;
 838                         re->m_fifo_depth--;
 839                 }
 840         }
 841
 842         if (re->m_rxpending != NULL) {
 843                 m_freem(re->m_rxpending);
 844                 re->m_rxpending = NULL;
 845         }
 846         re->m_fifo_head = re->m_fifo_tail = re->m_fifo_depth = 0;
 847
 848         return (0);
 849 }
 850
 851 /*
 852  * Setup the initial RX FIFO structure.
 853  */
 854 static int
 855 ath_edma_setup_rxfifo(struct ath_softc *sc, HAL_RX_QUEUE qtype)
 856 {
 857         struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
 858
 859         ATH_RX_LOCK_ASSERT(sc);
 860
 861         if (! ath_hal_getrxfifodepth(sc->sc_ah, qtype, &re->m_fifolen)) {
 862                 device_printf(sc->sc_dev, "%s: qtype=%d, failed\n",
 863                     __func__,
 864                     qtype);
 865                 return (-EINVAL);
 866         }
 867         device_printf(sc->sc_dev, "%s: type=%d, FIFO depth = %d entries\n",
 868             __func__,
 869             qtype,
 870             re->m_fifolen);
 871
 872         /* Allocate ath_buf FIFO array, pre-zero'ed */
 873         re->m_fifo = kmalloc(sizeof(struct ath_buf *) * re->m_fifolen,
 874             M_ATHDEV,
 875             M_INTWAIT | M_ZERO);
 876         if (re->m_fifo == NULL) {
 877                 device_printf(sc->sc_dev, "%s: malloc failed\n",
 878                     __func__);
 879                 return (-ENOMEM);
 880         }
 881
 882         /*
 883          * Set initial "empty" state.
 884          */
 885         re->m_rxpending = NULL;
 886         re->m_fifo_head = re->m_fifo_tail = re->m_fifo_depth = 0;
 887
 888         return (0);
 889 }
 890
 891 static int
 892 ath_edma_rxfifo_free(struct ath_softc *sc, HAL_RX_QUEUE qtype)
 893 {
 894         struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
 895
 896         device_printf(sc->sc_dev, "%s: called; qtype=%d\n",
 897             __func__,
 898             qtype);
 899
 900         kfree(re->m_fifo, M_ATHDEV);
 901
 902         return (0);
 903 }
 904
 905 static int
 906 ath_edma_dma_rxsetup(struct ath_softc *sc)
 907 {
 908         int error;
 909
 910         /*
 911          * Create RX DMA tag and buffers.
 912          */
 913         error = ath_descdma_setup_rx_edma(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
 914             "rx", ath_rxbuf, sc->sc_rx_statuslen);
 915         if (error != 0)
 916                 return error;
 917
 918         ATH_RX_LOCK(sc);
 919         (void) ath_edma_setup_rxfifo(sc, HAL_RX_QUEUE_HP);
 920         (void) ath_edma_setup_rxfifo(sc, HAL_RX_QUEUE_LP);
 921         ATH_RX_UNLOCK(sc);
 922
 923         return (0);
 924 }
 925
 926 static int
 927 ath_edma_dma_rxteardown(struct ath_softc *sc)
 928 {
 929
 930         ATH_RX_LOCK(sc);
 931         ath_edma_flush_deferred_queue(sc);
 932         ath_edma_rxfifo_flush(sc, HAL_RX_QUEUE_HP);
 933         ath_edma_rxfifo_free(sc, HAL_RX_QUEUE_HP);
 934
 935         ath_edma_rxfifo_flush(sc, HAL_RX_QUEUE_LP);
 936         ath_edma_rxfifo_free(sc, HAL_RX_QUEUE_LP);
 937         ATH_RX_UNLOCK(sc);
 938
 939         /* Free RX ath_buf */
 940         /* Free RX DMA tag */
 941         if (sc->sc_rxdma.dd_desc_len != 0)
 942                 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
 943
 944         return (0);
 945 }
 946
 947 void
 948 ath_recv_setup_edma(struct ath_softc *sc)
 949 {
 950
 951         /* Set buffer size to 4k */
 952         sc->sc_edma_bufsize = 4096;
 953
 954         /* Fetch EDMA field and buffer sizes */
 955         (void) ath_hal_getrxstatuslen(sc->sc_ah, &sc->sc_rx_statuslen);
 956
 957         /* Configure the hardware with the RX buffer size */
 958         (void) ath_hal_setrxbufsize(sc->sc_ah, sc->sc_edma_bufsize -
 959             sc->sc_rx_statuslen);
 960
 961         device_printf(sc->sc_dev, "RX status length: %d\n",
 962             sc->sc_rx_statuslen);
 963         device_printf(sc->sc_dev, "RX buffer size: %d\n",
 964             sc->sc_edma_bufsize);
 965
 966         sc->sc_rx.recv_stop = ath_edma_stoprecv;
 967         sc->sc_rx.recv_start = ath_edma_startrecv;
 968         sc->sc_rx.recv_flush = ath_edma_recv_flush;
 969         sc->sc_rx.recv_tasklet = ath_edma_recv_tasklet;
 970         sc->sc_rx.recv_rxbuf_init = ath_edma_rxbuf_init;
 971
 972         sc->sc_rx.recv_setup = ath_edma_dma_rxsetup;
 973         sc->sc_rx.recv_teardown = ath_edma_dma_rxteardown;
 974
 975         sc->sc_rx.recv_sched = ath_edma_recv_sched;
 976         sc->sc_rx.recv_sched_queue = ath_edma_recv_sched_queue;
 977 }