sys/dev/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include "i915_drv.h"
  29 #include "intel_drv.h"
  30 #include <linux/module.h>
  31 #include <machine/clock.h>
  32 #include <drm/i915_powerwell.h>
  33
  34 /**
  35  * RC6 is a special power stage which allows the GPU to enter an very
  36  * low-voltage mode when idle, using down to 0V while at this stage.  This
  37  * stage is entered automatically when the GPU is idle when RC6 support is
  38  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  39  *
  40  * There are different RC6 modes available in Intel GPU, which differentiate
  41  * among each other with the latency required to enter and leave RC6 and
  42  * voltage consumed by the GPU in different states.
  43  *
  44  * The combination of the following flags define which states GPU is allowed
  45  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  46  * RC6pp is deepest RC6. Their support by hardware varies according to the
  47  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  48  * which brings the most power savings; deeper states save more power, but
  49  * require higher latency to switch to and wake up.
  50  */
  51 #define INTEL_RC6_ENABLE                        (1<<0)
  52 #define INTEL_RC6p_ENABLE                       (1<<1)
  53 #define INTEL_RC6pp_ENABLE                      (1<<2)
  54
  55 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
  56  * framebuffer contents in-memory, aiming at reducing the required bandwidth
  57  * during in-memory transfers and, therefore, reduce the power packet.
  58  *
  59  * The benefits of FBC are mostly visible with solid backgrounds and
  60  * variation-less patterns.
  61  *
  62  * FBC-related functionality can be enabled by the means of the
  63  * i915.i915_enable_fbc parameter
  64  */
  65
  66 static void i8xx_disable_fbc(struct drm_device *dev)
  67 {
  68         struct drm_i915_private *dev_priv = dev->dev_private;
  69         u32 fbc_ctl;
  70
  71         /* Disable compression */
  72         fbc_ctl = I915_READ(FBC_CONTROL);
  73         if ((fbc_ctl & FBC_CTL_EN) == 0)
  74                 return;
  75
  76         fbc_ctl &= ~FBC_CTL_EN;
  77         I915_WRITE(FBC_CONTROL, fbc_ctl);
  78
  79         /* Wait for compressing bit to clear */
  80         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  81                 DRM_DEBUG_KMS("FBC idle timed out\n");
  82                 return;
  83         }
  84
  85         DRM_DEBUG_KMS("disabled FBC\n");
  86 }
  87
  88 static void i8xx_enable_fbc(struct drm_crtc *crtc)
  89 {
  90         struct drm_device *dev = crtc->dev;
  91         struct drm_i915_private *dev_priv = dev->dev_private;
  92         struct drm_framebuffer *fb = crtc->primary->fb;
  93         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  94         struct drm_i915_gem_object *obj = intel_fb->obj;
  95         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  96         int cfb_pitch;
  97         int i;
  98         u32 fbc_ctl;
  99
 100         cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
 101         if (fb->pitches[0] < cfb_pitch)
 102                 cfb_pitch = fb->pitches[0];
 103
 104         /* FBC_CTL wants 32B or 64B units */
 105         if (IS_GEN2(dev))
 106                 cfb_pitch = (cfb_pitch / 32) - 1;
 107         else
 108                 cfb_pitch = (cfb_pitch / 64) - 1;
 109
 110         /* Clear old tags */
 111         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
 112                 I915_WRITE(FBC_TAG + (i * 4), 0);
 113
 114         if (IS_GEN4(dev)) {
 115                 u32 fbc_ctl2;
 116
 117                 /* Set it up... */
 118                 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 119                 fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane);
 120                 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 121                 I915_WRITE(FBC_FENCE_OFF, crtc->y);
 122         }
 123
 124         /* enable it... */
 125         fbc_ctl = I915_READ(FBC_CONTROL);
 126         fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
 127         fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
 128         if (IS_I945GM(dev))
 129                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 130         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 131         fbc_ctl |= obj->fence_reg;
 132         I915_WRITE(FBC_CONTROL, fbc_ctl);
 133
 134         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
 135                       cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
 136 }
 137
 138 static bool i8xx_fbc_enabled(struct drm_device *dev)
 139 {
 140         struct drm_i915_private *dev_priv = dev->dev_private;
 141
 142         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 143 }
 144
 145 static void g4x_enable_fbc(struct drm_crtc *crtc)
 146 {
 147         struct drm_device *dev = crtc->dev;
 148         struct drm_i915_private *dev_priv = dev->dev_private;
 149         struct drm_framebuffer *fb = crtc->primary->fb;
 150         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 151         struct drm_i915_gem_object *obj = intel_fb->obj;
 152         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 153         u32 dpfc_ctl;
 154
 155         dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN;
 156         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 157                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 158         else
 159                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 160         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
 161
 162         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
 163
 164         /* enable it... */
 165         I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 166
 167         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 168 }
 169
 170 static void g4x_disable_fbc(struct drm_device *dev)
 171 {
 172         struct drm_i915_private *dev_priv = dev->dev_private;
 173         u32 dpfc_ctl;
 174
 175         /* Disable compression */
 176         dpfc_ctl = I915_READ(DPFC_CONTROL);
 177         if (dpfc_ctl & DPFC_CTL_EN) {
 178                 dpfc_ctl &= ~DPFC_CTL_EN;
 179                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 180
 181                 DRM_DEBUG_KMS("disabled FBC\n");
 182         }
 183 }
 184
 185 static bool g4x_fbc_enabled(struct drm_device *dev)
 186 {
 187         struct drm_i915_private *dev_priv = dev->dev_private;
 188
 189         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 190 }
 191
 192 static void sandybridge_blit_fbc_update(struct drm_device *dev)
 193 {
 194         struct drm_i915_private *dev_priv = dev->dev_private;
 195         u32 blt_ecoskpd;
 196
 197         /* Make sure blitter notifies FBC of writes */
 198
 199         /* Blitter is part of Media powerwell on VLV. No impact of
 200          * his param in other platforms for now */
 201         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
 202
 203         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
 204         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
 205                 GEN6_BLITTER_LOCK_SHIFT;
 206         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 207         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
 208         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 209         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
 210                          GEN6_BLITTER_LOCK_SHIFT);
 211         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 212         POSTING_READ(GEN6_BLITTER_ECOSKPD);
 213
 214         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
 215 }
 216
 217 static void ironlake_enable_fbc(struct drm_crtc *crtc)
 218 {
 219         struct drm_device *dev = crtc->dev;
 220         struct drm_i915_private *dev_priv = dev->dev_private;
 221         struct drm_framebuffer *fb = crtc->primary->fb;
 222         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 223         struct drm_i915_gem_object *obj = intel_fb->obj;
 224         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 225         u32 dpfc_ctl;
 226
 227         dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane);
 228         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 229                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 230         else
 231                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 232         dpfc_ctl |= DPFC_CTL_FENCE_EN;
 233         if (IS_GEN5(dev))
 234                 dpfc_ctl |= obj->fence_reg;
 235
 236         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
 237         I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
 238         /* enable it... */
 239         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 240
 241         if (IS_GEN6(dev)) {
 242                 I915_WRITE(SNB_DPFC_CTL_SA,
 243                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 244                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 245                 sandybridge_blit_fbc_update(dev);
 246         }
 247
 248         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 249 }
 250
 251 static void ironlake_disable_fbc(struct drm_device *dev)
 252 {
 253         struct drm_i915_private *dev_priv = dev->dev_private;
 254         u32 dpfc_ctl;
 255
 256         /* Disable compression */
 257         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 258         if (dpfc_ctl & DPFC_CTL_EN) {
 259                 dpfc_ctl &= ~DPFC_CTL_EN;
 260                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 261
 262                 DRM_DEBUG_KMS("disabled FBC\n");
 263         }
 264 }
 265
 266 static bool ironlake_fbc_enabled(struct drm_device *dev)
 267 {
 268         struct drm_i915_private *dev_priv = dev->dev_private;
 269
 270         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 271 }
 272
 273 static void gen7_enable_fbc(struct drm_crtc *crtc)
 274 {
 275         struct drm_device *dev = crtc->dev;
 276         struct drm_i915_private *dev_priv = dev->dev_private;
 277         struct drm_framebuffer *fb = crtc->primary->fb;
 278         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 279         struct drm_i915_gem_object *obj = intel_fb->obj;
 280         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 281         u32 dpfc_ctl;
 282
 283         dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane);
 284         if (drm_format_plane_cpp(fb->pixel_format, 0) == 2)
 285                 dpfc_ctl |= DPFC_CTL_LIMIT_2X;
 286         else
 287                 dpfc_ctl |= DPFC_CTL_LIMIT_1X;
 288         dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
 289
 290         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 291
 292         if (IS_IVYBRIDGE(dev)) {
 293                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 294                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
 295                            I915_READ(ILK_DISPLAY_CHICKEN1) |
 296                            ILK_FBCQ_DIS);
 297         } else {
 298                 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
 299                 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe),
 300                            I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) |
 301                            HSW_FBCQ_DIS);
 302         }
 303
 304         I915_WRITE(SNB_DPFC_CTL_SA,
 305                    SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 306         I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 307
 308         sandybridge_blit_fbc_update(dev);
 309
 310         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 311 }
 312
 313 bool intel_fbc_enabled(struct drm_device *dev)
 314 {
 315         struct drm_i915_private *dev_priv = dev->dev_private;
 316
 317         if (!dev_priv->display.fbc_enabled)
 318                 return false;
 319
 320         return dev_priv->display.fbc_enabled(dev);
 321 }
 322
 323 static void intel_fbc_work_fn(struct work_struct *__work)
 324 {
 325         struct intel_fbc_work *work =
 326                 container_of(to_delayed_work(__work),
 327                              struct intel_fbc_work, work);
 328         struct drm_device *dev = work->crtc->dev;
 329         struct drm_i915_private *dev_priv = dev->dev_private;
 330
 331         mutex_lock(&dev->struct_mutex);
 332         if (work == dev_priv->fbc.fbc_work) {
 333                 /* Double check that we haven't switched fb without cancelling
 334                  * the prior work.
 335                  */
 336                 if (work->crtc->primary->fb == work->fb) {
 337                         dev_priv->display.enable_fbc(work->crtc);
 338
 339                         dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
 340                         dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id;
 341                         dev_priv->fbc.y = work->crtc->y;
 342                 }
 343
 344                 dev_priv->fbc.fbc_work = NULL;
 345         }
 346         mutex_unlock(&dev->struct_mutex);
 347
 348         kfree(work);
 349 }
 350
 351 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
 352 {
 353         if (dev_priv->fbc.fbc_work == NULL)
 354                 return;
 355
 356         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
 357
 358         /* Synchronisation is provided by struct_mutex and checking of
 359          * dev_priv->fbc.fbc_work, so we can perform the cancellation
 360          * entirely asynchronously.
 361          */
 362         if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
 363                 /* tasklet was killed before being run, clean up */
 364                 kfree(dev_priv->fbc.fbc_work);
 365
 366         /* Mark the work as no longer wanted so that if it does
 367          * wake-up (because the work was already running and waiting
 368          * for our mutex), it will discover that is no longer
 369          * necessary to run.
 370          */
 371         dev_priv->fbc.fbc_work = NULL;
 372 }
 373
 374 static void intel_enable_fbc(struct drm_crtc *crtc)
 375 {
 376         struct intel_fbc_work *work;
 377         struct drm_device *dev = crtc->dev;
 378         struct drm_i915_private *dev_priv = dev->dev_private;
 379
 380         if (!dev_priv->display.enable_fbc)
 381                 return;
 382
 383         intel_cancel_fbc_work(dev_priv);
 384
 385         work = kzalloc(sizeof(*work), GFP_KERNEL);
 386         if (work == NULL) {
 387                 DRM_ERROR("Failed to allocate FBC work structure\n");
 388                 dev_priv->display.enable_fbc(crtc);
 389                 return;
 390         }
 391
 392         work->crtc = crtc;
 393         work->fb = crtc->primary->fb;
 394         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
 395
 396         dev_priv->fbc.fbc_work = work;
 397
 398         /* Delay the actual enabling to let pageflipping cease and the
 399          * display to settle before starting the compression. Note that
 400          * this delay also serves a second purpose: it allows for a
 401          * vblank to pass after disabling the FBC before we attempt
 402          * to modify the control registers.
 403          *
 404          * A more complicated solution would involve tracking vblanks
 405          * following the termination of the page-flipping sequence
 406          * and indeed performing the enable as a co-routine and not
 407          * waiting synchronously upon the vblank.
 408          *
 409          * WaFbcWaitForVBlankBeforeEnable:ilk,snb
 410          */
 411         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
 412 }
 413
 414 void intel_disable_fbc(struct drm_device *dev)
 415 {
 416         struct drm_i915_private *dev_priv = dev->dev_private;
 417
 418         intel_cancel_fbc_work(dev_priv);
 419
 420         if (!dev_priv->display.disable_fbc)
 421                 return;
 422
 423         dev_priv->display.disable_fbc(dev);
 424         dev_priv->fbc.plane = -1;
 425 }
 426
 427 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
 428                               enum no_fbc_reason reason)
 429 {
 430         if (dev_priv->fbc.no_fbc_reason == reason)
 431                 return false;
 432
 433         dev_priv->fbc.no_fbc_reason = reason;
 434         return true;
 435 }
 436
 437 /**
 438  * intel_update_fbc - enable/disable FBC as needed
 439  * @dev: the drm_device
 440  *
 441  * Set up the framebuffer compression hardware at mode set time.  We
 442  * enable it if possible:
 443  *   - plane A only (on pre-965)
 444  *   - no pixel mulitply/line duplication
 445  *   - no alpha buffer discard
 446  *   - no dual wide
 447  *   - framebuffer <= max_hdisplay in width, max_vdisplay in height
 448  *
 449  * We can't assume that any compression will take place (worst case),
 450  * so the compressed buffer has to be the same size as the uncompressed
 451  * one.  It also must reside (along with the line length buffer) in
 452  * stolen memory.
 453  *
 454  * We need to enable/disable FBC on a global basis.
 455  */
 456 void intel_update_fbc(struct drm_device *dev)
 457 {
 458         struct drm_i915_private *dev_priv = dev->dev_private;
 459         struct drm_crtc *crtc = NULL, *tmp_crtc;
 460         struct intel_crtc *intel_crtc;
 461         struct drm_framebuffer *fb;
 462         struct intel_framebuffer *intel_fb;
 463         struct drm_i915_gem_object *obj;
 464         const struct drm_display_mode *adjusted_mode;
 465         unsigned int max_width, max_height;
 466
 467         if (!HAS_FBC(dev)) {
 468                 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
 469                 return;
 470         }
 471
 472         if (!i915.powersave) {
 473                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 474                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 475                 return;
 476         }
 477
 478         /*
 479          * If FBC is already on, we just have to verify that we can
 480          * keep it that way...
 481          * Need to disable if:
 482          *   - more than one pipe is active
 483          *   - changing FBC params (stride, fence, mode)
 484          *   - new fb is too large to fit in compressed buffer
 485          *   - going to an unsupported config (interlace, pixel multiply, etc.)
 486          */
 487         for_each_crtc(dev, tmp_crtc) {
 488                 if (intel_crtc_active(tmp_crtc) &&
 489                     to_intel_crtc(tmp_crtc)->primary_enabled) {
 490                         if (crtc) {
 491                                 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
 492                                         DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
 493                                 goto out_disable;
 494                         }
 495                         crtc = tmp_crtc;
 496                 }
 497         }
 498
 499         if (!crtc || crtc->primary->fb == NULL) {
 500                 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
 501                         DRM_DEBUG_KMS("no output, disabling\n");
 502                 goto out_disable;
 503         }
 504
 505         intel_crtc = to_intel_crtc(crtc);
 506         fb = crtc->primary->fb;
 507         intel_fb = to_intel_framebuffer(fb);
 508         obj = intel_fb->obj;
 509         adjusted_mode = &intel_crtc->config.adjusted_mode;
 510
 511         if (i915.enable_fbc < 0) {
 512                 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
 513                         DRM_DEBUG_KMS("disabled per chip default\n");
 514                 goto out_disable;
 515         }
 516         if (!i915.enable_fbc) {
 517                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 518                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 519                 goto out_disable;
 520         }
 521         if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
 522             (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
 523                 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
 524                         DRM_DEBUG_KMS("mode incompatible with compression, "
 525                                       "disabling\n");
 526                 goto out_disable;
 527         }
 528
 529         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 530                 max_width = 4096;
 531                 max_height = 2048;
 532         } else {
 533                 max_width = 2048;
 534                 max_height = 1536;
 535         }
 536         if (intel_crtc->config.pipe_src_w > max_width ||
 537             intel_crtc->config.pipe_src_h > max_height) {
 538                 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
 539                         DRM_DEBUG_KMS("mode too large for compression, disabling\n");
 540                 goto out_disable;
 541         }
 542         if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) &&
 543             intel_crtc->plane != PLANE_A) {
 544                 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
 545                         DRM_DEBUG_KMS("plane not A, disabling compression\n");
 546                 goto out_disable;
 547         }
 548
 549         /* The use of a CPU fence is mandatory in order to detect writes
 550          * by the CPU to the scanout and trigger updates to the FBC.
 551          */
 552         if (obj->tiling_mode != I915_TILING_X ||
 553             obj->fence_reg == I915_FENCE_REG_NONE) {
 554                 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
 555                         DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
 556                 goto out_disable;
 557         }
 558
 559         /* If the kernel debugger is active, always disable compression */
 560 #ifdef DDB
 561         if (in_dbg_master())
 562                 goto out_disable;
 563 #endif
 564
 565         if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
 566                 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
 567                         DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
 568                 goto out_disable;
 569         }
 570
 571         /* If the scanout has not changed, don't modify the FBC settings.
 572          * Note that we make the fundamental assumption that the fb->obj
 573          * cannot be unpinned (and have its GTT offset and fence revoked)
 574          * without first being decoupled from the scanout and FBC disabled.
 575          */
 576         if (dev_priv->fbc.plane == intel_crtc->plane &&
 577             dev_priv->fbc.fb_id == fb->base.id &&
 578             dev_priv->fbc.y == crtc->y)
 579                 return;
 580
 581         if (intel_fbc_enabled(dev)) {
 582                 /* We update FBC along two paths, after changing fb/crtc
 583                  * configuration (modeswitching) and after page-flipping
 584                  * finishes. For the latter, we know that not only did
 585                  * we disable the FBC at the start of the page-flip
 586                  * sequence, but also more than one vblank has passed.
 587                  *
 588                  * For the former case of modeswitching, it is possible
 589                  * to switch between two FBC valid configurations
 590                  * instantaneously so we do need to disable the FBC
 591                  * before we can modify its control registers. We also
 592                  * have to wait for the next vblank for that to take
 593                  * effect. However, since we delay enabling FBC we can
 594                  * assume that a vblank has passed since disabling and
 595                  * that we can safely alter the registers in the deferred
 596                  * callback.
 597                  *
 598                  * In the scenario that we go from a valid to invalid
 599                  * and then back to valid FBC configuration we have
 600                  * no strict enforcement that a vblank occurred since
 601                  * disabling the FBC. However, along all current pipe
 602                  * disabling paths we do need to wait for a vblank at
 603                  * some point. And we wait before enabling FBC anyway.
 604                  */
 605                 DRM_DEBUG_KMS("disabling active FBC for update\n");
 606                 intel_disable_fbc(dev);
 607         }
 608
 609         intel_enable_fbc(crtc);
 610         dev_priv->fbc.no_fbc_reason = FBC_OK;
 611         return;
 612
 613 out_disable:
 614         /* Multiple disables should be harmless */
 615         if (intel_fbc_enabled(dev)) {
 616                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
 617                 intel_disable_fbc(dev);
 618         }
 619         i915_gem_stolen_cleanup_compression(dev);
 620 }
 621
 622 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 623 {
 624         struct drm_i915_private *dev_priv = dev->dev_private;
 625         u32 tmp;
 626
 627         tmp = I915_READ(CLKCFG);
 628
 629         switch (tmp & CLKCFG_FSB_MASK) {
 630         case CLKCFG_FSB_533:
 631                 dev_priv->fsb_freq = 533; /* 133*4 */
 632                 break;
 633         case CLKCFG_FSB_800:
 634                 dev_priv->fsb_freq = 800; /* 200*4 */
 635                 break;
 636         case CLKCFG_FSB_667:
 637                 dev_priv->fsb_freq =  667; /* 167*4 */
 638                 break;
 639         case CLKCFG_FSB_400:
 640                 dev_priv->fsb_freq = 400; /* 100*4 */
 641                 break;
 642         }
 643
 644         switch (tmp & CLKCFG_MEM_MASK) {
 645         case CLKCFG_MEM_533:
 646                 dev_priv->mem_freq = 533;
 647                 break;
 648         case CLKCFG_MEM_667:
 649                 dev_priv->mem_freq = 667;
 650                 break;
 651         case CLKCFG_MEM_800:
 652                 dev_priv->mem_freq = 800;
 653                 break;
 654         }
 655
 656         /* detect pineview DDR3 setting */
 657         tmp = I915_READ(CSHRDDR3CTL);
 658         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 659 }
 660
 661 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 662 {
 663         struct drm_i915_private *dev_priv = dev->dev_private;
 664         u16 ddrpll, csipll;
 665
 666         ddrpll = I915_READ16(DDRMPLL1);
 667         csipll = I915_READ16(CSIPLL0);
 668
 669         switch (ddrpll & 0xff) {
 670         case 0xc:
 671                 dev_priv->mem_freq = 800;
 672                 break;
 673         case 0x10:
 674                 dev_priv->mem_freq = 1066;
 675                 break;
 676         case 0x14:
 677                 dev_priv->mem_freq = 1333;
 678                 break;
 679         case 0x18:
 680                 dev_priv->mem_freq = 1600;
 681                 break;
 682         default:
 683                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 684                                  ddrpll & 0xff);
 685                 dev_priv->mem_freq = 0;
 686                 break;
 687         }
 688
 689         dev_priv->ips.r_t = dev_priv->mem_freq;
 690
 691         switch (csipll & 0x3ff) {
 692         case 0x00c:
 693                 dev_priv->fsb_freq = 3200;
 694                 break;
 695         case 0x00e:
 696                 dev_priv->fsb_freq = 3733;
 697                 break;
 698         case 0x010:
 699                 dev_priv->fsb_freq = 4266;
 700                 break;
 701         case 0x012:
 702                 dev_priv->fsb_freq = 4800;
 703                 break;
 704         case 0x014:
 705                 dev_priv->fsb_freq = 5333;
 706                 break;
 707         case 0x016:
 708                 dev_priv->fsb_freq = 5866;
 709                 break;
 710         case 0x018:
 711                 dev_priv->fsb_freq = 6400;
 712                 break;
 713         default:
 714                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 715                                  csipll & 0x3ff);
 716                 dev_priv->fsb_freq = 0;
 717                 break;
 718         }
 719
 720         if (dev_priv->fsb_freq == 3200) {
 721                 dev_priv->ips.c_m = 0;
 722         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 723                 dev_priv->ips.c_m = 1;
 724         } else {
 725                 dev_priv->ips.c_m = 2;
 726         }
 727 }
 728
 729 static const struct cxsr_latency cxsr_latency_table[] = {
 730         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 731         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 732         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 733         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 734         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 735
 736         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 737         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 738         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 739         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 740         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 741
 742         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 743         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 744         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 745         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 746         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 747
 748         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 749         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 750         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 751         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 752         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 753
 754         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 755         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 756         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 757         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 758         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 759
 760         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 761         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 762         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 763         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 764         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 765 };
 766
 767 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 768                                                          int is_ddr3,
 769                                                          int fsb,
 770                                                          int mem)
 771 {
 772         const struct cxsr_latency *latency;
 773         int i;
 774
 775         if (fsb == 0 || mem == 0)
 776                 return NULL;
 777
 778         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 779                 latency = &cxsr_latency_table[i];
 780                 if (is_desktop == latency->is_desktop &&
 781                     is_ddr3 == latency->is_ddr3 &&
 782                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 783                         return latency;
 784         }
 785
 786         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 787
 788         return NULL;
 789 }
 790
 791 static void pineview_disable_cxsr(struct drm_device *dev)
 792 {
 793         struct drm_i915_private *dev_priv = dev->dev_private;
 794
 795         /* deactivate cxsr */
 796         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
 797 }
 798
 799 /*
 800  * Latency for FIFO fetches is dependent on several factors:
 801  *   - memory configuration (speed, channels)
 802  *   - chipset
 803  *   - current MCH state
 804  * It can be fairly high in some situations, so here we assume a fairly
 805  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 806  * set this value too high, the FIFO will fetch frequently to stay full)
 807  * and power consumption (set it too low to save power and we might see
 808  * FIFO underruns and display "flicker").
 809  *
 810  * A value of 5us seems to be a good balance; safe for very low end
 811  * platforms but not overly aggressive on lower latency configs.
 812  */
 813 static const int latency_ns = 5000;
 814
 815 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 816 {
 817         struct drm_i915_private *dev_priv = dev->dev_private;
 818         uint32_t dsparb = I915_READ(DSPARB);
 819         int size;
 820
 821         size = dsparb & 0x7f;
 822         if (plane)
 823                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 824
 825         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 826                       plane ? "B" : "A", size);
 827
 828         return size;
 829 }
 830
 831 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 832 {
 833         struct drm_i915_private *dev_priv = dev->dev_private;
 834         uint32_t dsparb = I915_READ(DSPARB);
 835         int size;
 836
 837         size = dsparb & 0x1ff;
 838         if (plane)
 839                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 840         size >>= 1; /* Convert to cachelines */
 841
 842         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 843                       plane ? "B" : "A", size);
 844
 845         return size;
 846 }
 847
 848 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 849 {
 850         struct drm_i915_private *dev_priv = dev->dev_private;
 851         uint32_t dsparb = I915_READ(DSPARB);
 852         int size;
 853
 854         size = dsparb & 0x7f;
 855         size >>= 2; /* Convert to cachelines */
 856
 857         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 858                       plane ? "B" : "A",
 859                       size);
 860
 861         return size;
 862 }
 863
 864 /* Pineview has different values for various configs */
 865 static const struct intel_watermark_params pineview_display_wm = {
 866         PINEVIEW_DISPLAY_FIFO,
 867         PINEVIEW_MAX_WM,
 868         PINEVIEW_DFT_WM,
 869         PINEVIEW_GUARD_WM,
 870         PINEVIEW_FIFO_LINE_SIZE
 871 };
 872 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 873         PINEVIEW_DISPLAY_FIFO,
 874         PINEVIEW_MAX_WM,
 875         PINEVIEW_DFT_HPLLOFF_WM,
 876         PINEVIEW_GUARD_WM,
 877         PINEVIEW_FIFO_LINE_SIZE
 878 };
 879 static const struct intel_watermark_params pineview_cursor_wm = {
 880         PINEVIEW_CURSOR_FIFO,
 881         PINEVIEW_CURSOR_MAX_WM,
 882         PINEVIEW_CURSOR_DFT_WM,
 883         PINEVIEW_CURSOR_GUARD_WM,
 884         PINEVIEW_FIFO_LINE_SIZE,
 885 };
 886 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 887         PINEVIEW_CURSOR_FIFO,
 888         PINEVIEW_CURSOR_MAX_WM,
 889         PINEVIEW_CURSOR_DFT_WM,
 890         PINEVIEW_CURSOR_GUARD_WM,
 891         PINEVIEW_FIFO_LINE_SIZE
 892 };
 893 static const struct intel_watermark_params g4x_wm_info = {
 894         G4X_FIFO_SIZE,
 895         G4X_MAX_WM,
 896         G4X_MAX_WM,
 897         2,
 898         G4X_FIFO_LINE_SIZE,
 899 };
 900 static const struct intel_watermark_params g4x_cursor_wm_info = {
 901         I965_CURSOR_FIFO,
 902         I965_CURSOR_MAX_WM,
 903         I965_CURSOR_DFT_WM,
 904         2,
 905         G4X_FIFO_LINE_SIZE,
 906 };
 907 static const struct intel_watermark_params valleyview_wm_info = {
 908         VALLEYVIEW_FIFO_SIZE,
 909         VALLEYVIEW_MAX_WM,
 910         VALLEYVIEW_MAX_WM,
 911         2,
 912         G4X_FIFO_LINE_SIZE,
 913 };
 914 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 915         I965_CURSOR_FIFO,
 916         VALLEYVIEW_CURSOR_MAX_WM,
 917         I965_CURSOR_DFT_WM,
 918         2,
 919         G4X_FIFO_LINE_SIZE,
 920 };
 921 static const struct intel_watermark_params i965_cursor_wm_info = {
 922         I965_CURSOR_FIFO,
 923         I965_CURSOR_MAX_WM,
 924         I965_CURSOR_DFT_WM,
 925         2,
 926         I915_FIFO_LINE_SIZE,
 927 };
 928 static const struct intel_watermark_params i945_wm_info = {
 929         I945_FIFO_SIZE,
 930         I915_MAX_WM,
 931         1,
 932         2,
 933         I915_FIFO_LINE_SIZE
 934 };
 935 static const struct intel_watermark_params i915_wm_info = {
 936         I915_FIFO_SIZE,
 937         I915_MAX_WM,
 938         1,
 939         2,
 940         I915_FIFO_LINE_SIZE
 941 };
 942 static const struct intel_watermark_params i830_wm_info = {
 943         I855GM_FIFO_SIZE,
 944         I915_MAX_WM,
 945         1,
 946         2,
 947         I830_FIFO_LINE_SIZE
 948 };
 949 static const struct intel_watermark_params i845_wm_info = {
 950         I830_FIFO_SIZE,
 951         I915_MAX_WM,
 952         1,
 953         2,
 954         I830_FIFO_LINE_SIZE
 955 };
 956
 957 /**
 958  * intel_calculate_wm - calculate watermark level
 959  * @clock_in_khz: pixel clock
 960  * @wm: chip FIFO params
 961  * @pixel_size: display pixel size
 962  * @latency_ns: memory latency for the platform
 963  *
 964  * Calculate the watermark level (the level at which the display plane will
 965  * start fetching from memory again).  Each chip has a different display
 966  * FIFO size and allocation, so the caller needs to figure that out and pass
 967  * in the correct intel_watermark_params structure.
 968  *
 969  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 970  * on the pixel size.  When it reaches the watermark level, it'll start
 971  * fetching FIFO line sized based chunks from memory until the FIFO fills
 972  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 973  * will occur, and a display engine hang could result.
 974  */
 975 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 976                                         const struct intel_watermark_params *wm,
 977                                         int fifo_size,
 978                                         int pixel_size,
 979                                         unsigned long latency_ns)
 980 {
 981         long entries_required, wm_size;
 982
 983         /*
 984          * Note: we need to make sure we don't overflow for various clock &
 985          * latency values.
 986          * clocks go from a few thousand to several hundred thousand.
 987          * latency is usually a few thousand
 988          */
 989         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
 990                 1000;
 991         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 992
 993         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 994
 995         wm_size = fifo_size - (entries_required + wm->guard_size);
 996
 997         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 998
 999         /* Don't promote wm_size to unsigned... */
1000         if (wm_size > (long)wm->max_wm)
1001                 wm_size = wm->max_wm;
1002         if (wm_size <= 0)
1003                 wm_size = wm->default_wm;
1004         return wm_size;
1005 }
1006
1007 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1008 {
1009         struct drm_crtc *crtc, *enabled = NULL;
1010
1011         for_each_crtc(dev, crtc) {
1012                 if (intel_crtc_active(crtc)) {
1013                         if (enabled)
1014                                 return NULL;
1015                         enabled = crtc;
1016                 }
1017         }
1018
1019         return enabled;
1020 }
1021
1022 static void pineview_update_wm(struct drm_crtc *unused_crtc)
1023 {
1024         struct drm_device *dev = unused_crtc->dev;
1025         struct drm_i915_private *dev_priv = dev->dev_private;
1026         struct drm_crtc *crtc;
1027         const struct cxsr_latency *latency;
1028         u32 reg;
1029         unsigned long wm;
1030
1031         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1032                                          dev_priv->fsb_freq, dev_priv->mem_freq);
1033         if (!latency) {
1034                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1035                 pineview_disable_cxsr(dev);
1036                 return;
1037         }
1038
1039         crtc = single_enabled_crtc(dev);
1040         if (crtc) {
1041                 const struct drm_display_mode *adjusted_mode;
1042                 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1043                 int clock;
1044
1045                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1046                 clock = adjusted_mode->crtc_clock;
1047
1048                 /* Display SR */
1049                 wm = intel_calculate_wm(clock, &pineview_display_wm,
1050                                         pineview_display_wm.fifo_size,
1051                                         pixel_size, latency->display_sr);
1052                 reg = I915_READ(DSPFW1);
1053                 reg &= ~DSPFW_SR_MASK;
1054                 reg |= wm << DSPFW_SR_SHIFT;
1055                 I915_WRITE(DSPFW1, reg);
1056                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1057
1058                 /* cursor SR */
1059                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1060                                         pineview_display_wm.fifo_size,
1061                                         pixel_size, latency->cursor_sr);
1062                 reg = I915_READ(DSPFW3);
1063                 reg &= ~DSPFW_CURSOR_SR_MASK;
1064                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1065                 I915_WRITE(DSPFW3, reg);
1066
1067                 /* Display HPLL off SR */
1068                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1069                                         pineview_display_hplloff_wm.fifo_size,
1070                                         pixel_size, latency->display_hpll_disable);
1071                 reg = I915_READ(DSPFW3);
1072                 reg &= ~DSPFW_HPLL_SR_MASK;
1073                 reg |= wm & DSPFW_HPLL_SR_MASK;
1074                 I915_WRITE(DSPFW3, reg);
1075
1076                 /* cursor HPLL off SR */
1077                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1078                                         pineview_display_hplloff_wm.fifo_size,
1079                                         pixel_size, latency->cursor_hpll_disable);
1080                 reg = I915_READ(DSPFW3);
1081                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1082                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1083                 I915_WRITE(DSPFW3, reg);
1084                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1085
1086                 /* activate cxsr */
1087                 I915_WRITE(DSPFW3,
1088                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1089                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1090         } else {
1091                 pineview_disable_cxsr(dev);
1092                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1093         }
1094 }
1095
1096 static bool g4x_compute_wm0(struct drm_device *dev,
1097                             int plane,
1098                             const struct intel_watermark_params *display,
1099                             int display_latency_ns,
1100                             const struct intel_watermark_params *cursor,
1101                             int cursor_latency_ns,
1102                             int *plane_wm,
1103                             int *cursor_wm)
1104 {
1105         struct drm_crtc *crtc;
1106         const struct drm_display_mode *adjusted_mode;
1107         int htotal, hdisplay, clock, pixel_size;
1108         int line_time_us, line_count;
1109         int entries, tlb_miss;
1110
1111         crtc = intel_get_crtc_for_plane(dev, plane);
1112         if (!intel_crtc_active(crtc)) {
1113                 *cursor_wm = cursor->guard_size;
1114                 *plane_wm = display->guard_size;
1115                 return false;
1116         }
1117
1118         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1119         clock = adjusted_mode->crtc_clock;
1120         htotal = adjusted_mode->crtc_htotal;
1121         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1122         pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1123
1124         /* Use the small buffer method to calculate plane watermark */
1125         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1126         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1127         if (tlb_miss > 0)
1128                 entries += tlb_miss;
1129         entries = DIV_ROUND_UP(entries, display->cacheline_size);
1130         *plane_wm = entries + display->guard_size;
1131         if (*plane_wm > (int)display->max_wm)
1132                 *plane_wm = display->max_wm;
1133
1134         /* Use the large buffer method to calculate cursor watermark */
1135         line_time_us = max(htotal * 1000 / clock, 1);
1136         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1137         entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size;
1138         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1139         if (tlb_miss > 0)
1140                 entries += tlb_miss;
1141         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1142         *cursor_wm = entries + cursor->guard_size;
1143         if (*cursor_wm > (int)cursor->max_wm)
1144                 *cursor_wm = (int)cursor->max_wm;
1145
1146         return true;
1147 }
1148
1149 /*
1150  * Check the wm result.
1151  *
1152  * If any calculated watermark values is larger than the maximum value that
1153  * can be programmed into the associated watermark register, that watermark
1154  * must be disabled.
1155  */
1156 static bool g4x_check_srwm(struct drm_device *dev,
1157                            int display_wm, int cursor_wm,
1158                            const struct intel_watermark_params *display,
1159                            const struct intel_watermark_params *cursor)
1160 {
1161         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1162                       display_wm, cursor_wm);
1163
1164         if (display_wm > display->max_wm) {
1165                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1166                               display_wm, display->max_wm);
1167                 return false;
1168         }
1169
1170         if (cursor_wm > cursor->max_wm) {
1171                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1172                               cursor_wm, cursor->max_wm);
1173                 return false;
1174         }
1175
1176         if (!(display_wm || cursor_wm)) {
1177                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1178                 return false;
1179         }
1180
1181         return true;
1182 }
1183
1184 static bool g4x_compute_srwm(struct drm_device *dev,
1185                              int plane,
1186                              int latency_ns,
1187                              const struct intel_watermark_params *display,
1188                              const struct intel_watermark_params *cursor,
1189                              int *display_wm, int *cursor_wm)
1190 {
1191         struct drm_crtc *crtc;
1192         const struct drm_display_mode *adjusted_mode;
1193         int hdisplay, htotal, pixel_size, clock;
1194         unsigned long line_time_us;
1195         int line_count, line_size;
1196         int small, large;
1197         int entries;
1198
1199         if (!latency_ns) {
1200                 *display_wm = *cursor_wm = 0;
1201                 return false;
1202         }
1203
1204         crtc = intel_get_crtc_for_plane(dev, plane);
1205         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1206         clock = adjusted_mode->crtc_clock;
1207         htotal = adjusted_mode->crtc_htotal;
1208         hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1209         pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1210
1211         line_time_us = max(htotal * 1000 / clock, 1);
1212         line_count = (latency_ns / line_time_us + 1000) / 1000;
1213         line_size = hdisplay * pixel_size;
1214
1215         /* Use the minimum of the small and large buffer method for primary */
1216         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1217         large = line_count * line_size;
1218
1219         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1220         *display_wm = entries + display->guard_size;
1221
1222         /* calculate the self-refresh watermark for display cursor */
1223         entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width;
1224         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1225         *cursor_wm = entries + cursor->guard_size;
1226
1227         return g4x_check_srwm(dev,
1228                               *display_wm, *cursor_wm,
1229                               display, cursor);
1230 }
1231
1232 static bool vlv_compute_drain_latency(struct drm_device *dev,
1233                                      int plane,
1234                                      int *plane_prec_mult,
1235                                      int *plane_dl,
1236                                      int *cursor_prec_mult,
1237                                      int *cursor_dl)
1238 {
1239         struct drm_crtc *crtc;
1240         int clock, pixel_size;
1241         int entries;
1242
1243         crtc = intel_get_crtc_for_plane(dev, plane);
1244         if (!intel_crtc_active(crtc))
1245                 return false;
1246
1247         clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
1248         pixel_size = crtc->primary->fb->bits_per_pixel / 8;     /* BPP */
1249
1250         entries = (clock / 1000) * pixel_size;
1251         *plane_prec_mult = (entries > 256) ?
1252                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1253         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1254                                                      pixel_size);
1255
1256         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
1257         *cursor_prec_mult = (entries > 256) ?
1258                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1259         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1260
1261         return true;
1262 }
1263
1264 /*
1265  * Update drain latency registers of memory arbiter
1266  *
1267  * Valleyview SoC has a new memory arbiter and needs drain latency registers
1268  * to be programmed. Each plane has a drain latency multiplier and a drain
1269  * latency value.
1270  */
1271
1272 static void vlv_update_drain_latency(struct drm_device *dev)
1273 {
1274         struct drm_i915_private *dev_priv = dev->dev_private;
1275         int planea_prec, planea_dl, planeb_prec, planeb_dl;
1276         int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1277         int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1278                                                         either 16 or 32 */
1279
1280         /* For plane A, Cursor A */
1281         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1282                                       &cursor_prec_mult, &cursora_dl)) {
1283                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1284                         DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1285                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1286                         DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1287
1288                 I915_WRITE(VLV_DDL1, cursora_prec |
1289                                 (cursora_dl << DDL_CURSORA_SHIFT) |
1290                                 planea_prec | planea_dl);
1291         }
1292
1293         /* For plane B, Cursor B */
1294         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1295                                       &cursor_prec_mult, &cursorb_dl)) {
1296                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1297                         DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1298                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1299                         DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1300
1301                 I915_WRITE(VLV_DDL2, cursorb_prec |
1302                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
1303                                 planeb_prec | planeb_dl);
1304         }
1305 }
1306
1307 #define single_plane_enabled(mask) is_power_of_2(mask)
1308
1309 static void valleyview_update_wm(struct drm_crtc *crtc)
1310 {
1311         struct drm_device *dev = crtc->dev;
1312         static const int sr_latency_ns = 12000;
1313         struct drm_i915_private *dev_priv = dev->dev_private;
1314         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1315         int plane_sr, cursor_sr;
1316         int ignore_plane_sr, ignore_cursor_sr;
1317         unsigned int enabled = 0;
1318
1319         vlv_update_drain_latency(dev);
1320
1321         if (g4x_compute_wm0(dev, PIPE_A,
1322                             &valleyview_wm_info, latency_ns,
1323                             &valleyview_cursor_wm_info, latency_ns,
1324                             &planea_wm, &cursora_wm))
1325                 enabled |= 1 << PIPE_A;
1326
1327         if (g4x_compute_wm0(dev, PIPE_B,
1328                             &valleyview_wm_info, latency_ns,
1329                             &valleyview_cursor_wm_info, latency_ns,
1330                             &planeb_wm, &cursorb_wm))
1331                 enabled |= 1 << PIPE_B;
1332
1333         if (single_plane_enabled(enabled) &&
1334             g4x_compute_srwm(dev, ffs(enabled) - 1,
1335                              sr_latency_ns,
1336                              &valleyview_wm_info,
1337                              &valleyview_cursor_wm_info,
1338                              &plane_sr, &ignore_cursor_sr) &&
1339             g4x_compute_srwm(dev, ffs(enabled) - 1,
1340                              2*sr_latency_ns,
1341                              &valleyview_wm_info,
1342                              &valleyview_cursor_wm_info,
1343                              &ignore_plane_sr, &cursor_sr)) {
1344                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1345         } else {
1346                 I915_WRITE(FW_BLC_SELF_VLV,
1347                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1348                 plane_sr = cursor_sr = 0;
1349         }
1350
1351         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1352                       planea_wm, cursora_wm,
1353                       planeb_wm, cursorb_wm,
1354                       plane_sr, cursor_sr);
1355
1356         I915_WRITE(DSPFW1,
1357                    (plane_sr << DSPFW_SR_SHIFT) |
1358                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1359                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1360                    planea_wm);
1361         I915_WRITE(DSPFW2,
1362                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1363                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1364         I915_WRITE(DSPFW3,
1365                    (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1366                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1367 }
1368
1369 static void g4x_update_wm(struct drm_crtc *crtc)
1370 {
1371         struct drm_device *dev = crtc->dev;
1372         static const int sr_latency_ns = 12000;
1373         struct drm_i915_private *dev_priv = dev->dev_private;
1374         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1375         int plane_sr, cursor_sr;
1376         unsigned int enabled = 0;
1377
1378         if (g4x_compute_wm0(dev, PIPE_A,
1379                             &g4x_wm_info, latency_ns,
1380                             &g4x_cursor_wm_info, latency_ns,
1381                             &planea_wm, &cursora_wm))
1382                 enabled |= 1 << PIPE_A;
1383
1384         if (g4x_compute_wm0(dev, PIPE_B,
1385                             &g4x_wm_info, latency_ns,
1386                             &g4x_cursor_wm_info, latency_ns,
1387                             &planeb_wm, &cursorb_wm))
1388                 enabled |= 1 << PIPE_B;
1389
1390         if (single_plane_enabled(enabled) &&
1391             g4x_compute_srwm(dev, ffs(enabled) - 1,
1392                              sr_latency_ns,
1393                              &g4x_wm_info,
1394                              &g4x_cursor_wm_info,
1395                              &plane_sr, &cursor_sr)) {
1396                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1397         } else {
1398                 I915_WRITE(FW_BLC_SELF,
1399                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1400                 plane_sr = cursor_sr = 0;
1401         }
1402
1403         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1404                       planea_wm, cursora_wm,
1405                       planeb_wm, cursorb_wm,
1406                       plane_sr, cursor_sr);
1407
1408         I915_WRITE(DSPFW1,
1409                    (plane_sr << DSPFW_SR_SHIFT) |
1410                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1411                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1412                    planea_wm);
1413         I915_WRITE(DSPFW2,
1414                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1415                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1416         /* HPLL off in SR has some issues on G4x... disable it */
1417         I915_WRITE(DSPFW3,
1418                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1419                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1420 }
1421
1422 static void i965_update_wm(struct drm_crtc *unused_crtc)
1423 {
1424         struct drm_device *dev = unused_crtc->dev;
1425         struct drm_i915_private *dev_priv = dev->dev_private;
1426         struct drm_crtc *crtc;
1427         int srwm = 1;
1428         int cursor_sr = 16;
1429
1430         /* Calc sr entries for one plane configs */
1431         crtc = single_enabled_crtc(dev);
1432         if (crtc) {
1433                 /* self-refresh has much higher latency */
1434                 static const int sr_latency_ns = 12000;
1435                 const struct drm_display_mode *adjusted_mode =
1436                         &to_intel_crtc(crtc)->config.adjusted_mode;
1437                 int clock = adjusted_mode->crtc_clock;
1438                 int htotal = adjusted_mode->crtc_htotal;
1439                 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1440                 int pixel_size = crtc->primary->fb->bits_per_pixel / 8;
1441                 unsigned long line_time_us;
1442                 int entries;
1443
1444                 line_time_us = max(htotal * 1000 / clock, 1);
1445
1446                 /* Use ns/us then divide to preserve precision */
1447                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1448                         pixel_size * hdisplay;
1449                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1450                 srwm = I965_FIFO_SIZE - entries;
1451                 if (srwm < 0)
1452                         srwm = 1;
1453                 srwm &= 0x1ff;
1454                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1455                               entries, srwm);
1456
1457                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1458                         pixel_size * to_intel_crtc(crtc)->cursor_width;
1459                 entries = DIV_ROUND_UP(entries,
1460                                           i965_cursor_wm_info.cacheline_size);
1461                 cursor_sr = i965_cursor_wm_info.fifo_size -
1462                         (entries + i965_cursor_wm_info.guard_size);
1463
1464                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1465                         cursor_sr = i965_cursor_wm_info.max_wm;
1466
1467                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1468                               "cursor %d\n", srwm, cursor_sr);
1469
1470                 if (IS_CRESTLINE(dev))
1471                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1472         } else {
1473                 /* Turn off self refresh if both pipes are enabled */
1474                 if (IS_CRESTLINE(dev))
1475                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1476                                    & ~FW_BLC_SELF_EN);
1477         }
1478
1479         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1480                       srwm);
1481
1482         /* 965 has limitations... */
1483         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1484                    (8 << 16) | (8 << 8) | (8 << 0));
1485         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1486         /* update cursor SR watermark */
1487         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1488 }
1489
1490 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1491 {
1492         struct drm_device *dev = unused_crtc->dev;
1493         struct drm_i915_private *dev_priv = dev->dev_private;
1494         const struct intel_watermark_params *wm_info;
1495         uint32_t fwater_lo;
1496         uint32_t fwater_hi;
1497         int cwm, srwm = 1;
1498         int fifo_size;
1499         int planea_wm, planeb_wm;
1500         struct drm_crtc *crtc, *enabled = NULL;
1501
1502         if (IS_I945GM(dev))
1503                 wm_info = &i945_wm_info;
1504         else if (!IS_GEN2(dev))
1505                 wm_info = &i915_wm_info;
1506         else
1507                 wm_info = &i830_wm_info;
1508
1509         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1510         crtc = intel_get_crtc_for_plane(dev, 0);
1511         if (intel_crtc_active(crtc)) {
1512                 const struct drm_display_mode *adjusted_mode;
1513                 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1514                 if (IS_GEN2(dev))
1515                         cpp = 4;
1516
1517                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1518                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1519                                                wm_info, fifo_size, cpp,
1520                                                latency_ns);
1521                 enabled = crtc;
1522         } else
1523                 planea_wm = fifo_size - wm_info->guard_size;
1524
1525         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1526         crtc = intel_get_crtc_for_plane(dev, 1);
1527         if (intel_crtc_active(crtc)) {
1528                 const struct drm_display_mode *adjusted_mode;
1529                 int cpp = crtc->primary->fb->bits_per_pixel / 8;
1530                 if (IS_GEN2(dev))
1531                         cpp = 4;
1532
1533                 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1534                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1535                                                wm_info, fifo_size, cpp,
1536                                                latency_ns);
1537                 if (enabled == NULL)
1538                         enabled = crtc;
1539                 else
1540                         enabled = NULL;
1541         } else
1542                 planeb_wm = fifo_size - wm_info->guard_size;
1543
1544         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1545
1546         if (IS_I915GM(dev) && enabled) {
1547                 struct intel_framebuffer *fb;
1548
1549                 fb = to_intel_framebuffer(enabled->primary->fb);
1550
1551                 /* self-refresh seems busted with untiled */
1552                 if (fb->obj->tiling_mode == I915_TILING_NONE)
1553                         enabled = NULL;
1554         }
1555
1556         /*
1557          * Overlay gets an aggressive default since video jitter is bad.
1558          */
1559         cwm = 2;
1560
1561         /* Play safe and disable self-refresh before adjusting watermarks. */
1562         if (IS_I945G(dev) || IS_I945GM(dev))
1563                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1564         else if (IS_I915GM(dev))
1565                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_SELF_EN));
1566
1567         /* Calc sr entries for one plane configs */
1568         if (HAS_FW_BLC(dev) && enabled) {
1569                 /* self-refresh has much higher latency */
1570                 static const int sr_latency_ns = 6000;
1571                 const struct drm_display_mode *adjusted_mode =
1572                         &to_intel_crtc(enabled)->config.adjusted_mode;
1573                 int clock = adjusted_mode->crtc_clock;
1574                 int htotal = adjusted_mode->crtc_htotal;
1575                 int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w;
1576                 int pixel_size = enabled->primary->fb->bits_per_pixel / 8;
1577                 unsigned long line_time_us;
1578                 int entries;
1579
1580                 line_time_us = max(htotal * 1000 / clock, 1);
1581
1582                 /* Use ns/us then divide to preserve precision */
1583                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1584                         pixel_size * hdisplay;
1585                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1586                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1587                 srwm = wm_info->fifo_size - entries;
1588                 if (srwm < 0)
1589                         srwm = 1;
1590
1591                 if (IS_I945G(dev) || IS_I945GM(dev))
1592                         I915_WRITE(FW_BLC_SELF,
1593                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1594                 else if (IS_I915GM(dev))
1595                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1596         }
1597
1598         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1599                       planea_wm, planeb_wm, cwm, srwm);
1600
1601         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1602         fwater_hi = (cwm & 0x1f);
1603
1604         /* Set request length to 8 cachelines per fetch */
1605         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1606         fwater_hi = fwater_hi | (1 << 8);
1607
1608         I915_WRITE(FW_BLC, fwater_lo);
1609         I915_WRITE(FW_BLC2, fwater_hi);
1610
1611         if (HAS_FW_BLC(dev)) {
1612                 if (enabled) {
1613                         if (IS_I945G(dev) || IS_I945GM(dev))
1614                                 I915_WRITE(FW_BLC_SELF,
1615                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1616                         else if (IS_I915GM(dev))
1617                                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_SELF_EN));
1618                         DRM_DEBUG_KMS("memory self refresh enabled\n");
1619                 } else
1620                         DRM_DEBUG_KMS("memory self refresh disabled\n");
1621         }
1622 }
1623
1624 static void i845_update_wm(struct drm_crtc *unused_crtc)
1625 {
1626         struct drm_device *dev = unused_crtc->dev;
1627         struct drm_i915_private *dev_priv = dev->dev_private;
1628         struct drm_crtc *crtc;
1629         const struct drm_display_mode *adjusted_mode;
1630         uint32_t fwater_lo;
1631         int planea_wm;
1632
1633         crtc = single_enabled_crtc(dev);
1634         if (crtc == NULL)
1635                 return;
1636
1637         adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1638         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1639                                        &i845_wm_info,
1640                                        dev_priv->display.get_fifo_size(dev, 0),
1641                                        4, latency_ns);
1642         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1643         fwater_lo |= (3<<8) | planea_wm;
1644
1645         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1646
1647         I915_WRITE(FW_BLC, fwater_lo);
1648 }
1649
1650 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
1651                                     struct drm_crtc *crtc)
1652 {
1653         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1654         uint32_t pixel_rate;
1655
1656         pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
1657
1658         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1659          * adjust the pixel_rate here. */
1660
1661         if (intel_crtc->config.pch_pfit.enabled) {
1662                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1663                 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
1664
1665                 pipe_w = intel_crtc->config.pipe_src_w;
1666                 pipe_h = intel_crtc->config.pipe_src_h;
1667                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1668                 pfit_h = pfit_size & 0xFFFF;
1669                 if (pipe_w < pfit_w)
1670                         pipe_w = pfit_w;
1671                 if (pipe_h < pfit_h)
1672                         pipe_h = pfit_h;
1673
1674                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1675                                      pfit_w * pfit_h);
1676         }
1677
1678         return pixel_rate;
1679 }
1680
1681 /* latency must be in 0.1us units. */
1682 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1683                                uint32_t latency)
1684 {
1685         uint64_t ret;
1686
1687         if (WARN(latency == 0, "Latency value missing\n"))
1688                 return UINT_MAX;
1689
1690         ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1691         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1692
1693         return ret;
1694 }
1695
1696 /* latency must be in 0.1us units. */
1697 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1698                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1699                                uint32_t latency)
1700 {
1701         uint32_t ret;
1702
1703         if (WARN(latency == 0, "Latency value missing\n"))
1704                 return UINT_MAX;
1705
1706         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1707         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1708         ret = DIV_ROUND_UP(ret, 64) + 2;
1709         return ret;
1710 }
1711
1712 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1713                            uint8_t bytes_per_pixel)
1714 {
1715         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1716 }
1717
1718 struct ilk_pipe_wm_parameters {
1719         bool active;
1720         uint32_t pipe_htotal;
1721         uint32_t pixel_rate;
1722         struct intel_plane_wm_parameters pri;
1723         struct intel_plane_wm_parameters spr;
1724         struct intel_plane_wm_parameters cur;
1725 };
1726
1727 struct ilk_wm_maximums {
1728         uint16_t pri;
1729         uint16_t spr;
1730         uint16_t cur;
1731         uint16_t fbc;
1732 };
1733
1734 /* used in computing the new watermarks state */
1735 struct intel_wm_config {
1736         unsigned int num_pipes_active;
1737         bool sprites_enabled;
1738         bool sprites_scaled;
1739 };
1740
1741 /*
1742  * For both WM_PIPE and WM_LP.
1743  * mem_value must be in 0.1us units.
1744  */
1745 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
1746                                    uint32_t mem_value,
1747                                    bool is_lp)
1748 {
1749         uint32_t method1, method2;
1750
1751         if (!params->active || !params->pri.enabled)
1752                 return 0;
1753
1754         method1 = ilk_wm_method1(params->pixel_rate,
1755                                  params->pri.bytes_per_pixel,
1756                                  mem_value);
1757
1758         if (!is_lp)
1759                 return method1;
1760
1761         method2 = ilk_wm_method2(params->pixel_rate,
1762                                  params->pipe_htotal,
1763                                  params->pri.horiz_pixels,
1764                                  params->pri.bytes_per_pixel,
1765                                  mem_value);
1766
1767         return min(method1, method2);
1768 }
1769
1770 /*
1771  * For both WM_PIPE and WM_LP.
1772  * mem_value must be in 0.1us units.
1773  */
1774 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
1775                                    uint32_t mem_value)
1776 {
1777         uint32_t method1, method2;
1778
1779         if (!params->active || !params->spr.enabled)
1780                 return 0;
1781
1782         method1 = ilk_wm_method1(params->pixel_rate,
1783                                  params->spr.bytes_per_pixel,
1784                                  mem_value);
1785         method2 = ilk_wm_method2(params->pixel_rate,
1786                                  params->pipe_htotal,
1787                                  params->spr.horiz_pixels,
1788                                  params->spr.bytes_per_pixel,
1789                                  mem_value);
1790         return min(method1, method2);
1791 }
1792
1793 /*
1794  * For both WM_PIPE and WM_LP.
1795  * mem_value must be in 0.1us units.
1796  */
1797 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
1798                                    uint32_t mem_value)
1799 {
1800         if (!params->active || !params->cur.enabled)
1801                 return 0;
1802
1803         return ilk_wm_method2(params->pixel_rate,
1804                               params->pipe_htotal,
1805                               params->cur.horiz_pixels,
1806                               params->cur.bytes_per_pixel,
1807                               mem_value);
1808 }
1809
1810 /* Only for WM_LP. */
1811 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1812                                    uint32_t pri_val)
1813 {
1814         if (!params->active || !params->pri.enabled)
1815                 return 0;
1816
1817         return ilk_wm_fbc(pri_val,
1818                           params->pri.horiz_pixels,
1819                           params->pri.bytes_per_pixel);
1820 }
1821
1822 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1823 {
1824         if (INTEL_INFO(dev)->gen >= 8)
1825                 return 3072;
1826         else if (INTEL_INFO(dev)->gen >= 7)
1827                 return 768;
1828         else
1829                 return 512;
1830 }
1831
1832 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1833                                          int level, bool is_sprite)
1834 {
1835         if (INTEL_INFO(dev)->gen >= 8)
1836                 /* BDW primary/sprite plane watermarks */
1837                 return level == 0 ? 255 : 2047;
1838         else if (INTEL_INFO(dev)->gen >= 7)
1839                 /* IVB/HSW primary/sprite plane watermarks */
1840                 return level == 0 ? 127 : 1023;
1841         else if (!is_sprite)
1842                 /* ILK/SNB primary plane watermarks */
1843                 return level == 0 ? 127 : 511;
1844         else
1845                 /* ILK/SNB sprite plane watermarks */
1846                 return level == 0 ? 63 : 255;
1847 }
1848
1849 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1850                                           int level)
1851 {
1852         if (INTEL_INFO(dev)->gen >= 7)
1853                 return level == 0 ? 63 : 255;
1854         else
1855                 return level == 0 ? 31 : 63;
1856 }
1857
1858 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1859 {
1860         if (INTEL_INFO(dev)->gen >= 8)
1861                 return 31;
1862         else
1863                 return 15;
1864 }
1865
1866 /* Calculate the maximum primary/sprite plane watermark */
1867 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1868                                      int level,
1869                                      const struct intel_wm_config *config,
1870                                      enum intel_ddb_partitioning ddb_partitioning,
1871                                      bool is_sprite)
1872 {
1873         unsigned int fifo_size = ilk_display_fifo_size(dev);
1874
1875         /* if sprites aren't enabled, sprites get nothing */
1876         if (is_sprite && !config->sprites_enabled)
1877                 return 0;
1878
1879         /* HSW allows LP1+ watermarks even with multiple pipes */
1880         if (level == 0 || config->num_pipes_active > 1) {
1881                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1882
1883                 /*
1884                  * For some reason the non self refresh
1885                  * FIFO size is only half of the self
1886                  * refresh FIFO size on ILK/SNB.
1887                  */
1888                 if (INTEL_INFO(dev)->gen <= 6)
1889                         fifo_size /= 2;
1890         }
1891
1892         if (config->sprites_enabled) {
1893                 /* level 0 is always calculated with 1:1 split */
1894                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1895                         if (is_sprite)
1896                                 fifo_size *= 5;
1897                         fifo_size /= 6;
1898                 } else {
1899                         fifo_size /= 2;
1900                 }
1901         }
1902
1903         /* clamp to max that the registers can hold */
1904         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1905 }
1906
1907 /* Calculate the maximum cursor plane watermark */
1908 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1909                                       int level,
1910                                       const struct intel_wm_config *config)
1911 {
1912         /* HSW LP1+ watermarks w/ multiple pipes */
1913         if (level > 0 && config->num_pipes_active > 1)
1914                 return 64;
1915
1916         /* otherwise just report max that registers can hold */
1917         return ilk_cursor_wm_reg_max(dev, level);
1918 }
1919
1920 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1921                                     int level,
1922                                     const struct intel_wm_config *config,
1923                                     enum intel_ddb_partitioning ddb_partitioning,
1924                                     struct ilk_wm_maximums *max)
1925 {
1926         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1927         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1928         max->cur = ilk_cursor_wm_max(dev, level, config);
1929         max->fbc = ilk_fbc_wm_reg_max(dev);
1930 }
1931
1932 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1933                                         int level,
1934                                         struct ilk_wm_maximums *max)
1935 {
1936         max->pri = ilk_plane_wm_reg_max(dev, level, false);
1937         max->spr = ilk_plane_wm_reg_max(dev, level, true);
1938         max->cur = ilk_cursor_wm_reg_max(dev, level);
1939         max->fbc = ilk_fbc_wm_reg_max(dev);
1940 }
1941
1942 static bool ilk_validate_wm_level(int level,
1943                                   const struct ilk_wm_maximums *max,
1944                                   struct intel_wm_level *result)
1945 {
1946         bool ret;
1947
1948         /* already determined to be invalid? */
1949         if (!result->enable)
1950                 return false;
1951
1952         result->enable = result->pri_val <= max->pri &&
1953                          result->spr_val <= max->spr &&
1954                          result->cur_val <= max->cur;
1955
1956         ret = result->enable;
1957
1958         /*
1959          * HACK until we can pre-compute everything,
1960          * and thus fail gracefully if LP0 watermarks
1961          * are exceeded...
1962          */
1963         if (level == 0 && !result->enable) {
1964                 if (result->pri_val > max->pri)
1965                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1966                                       level, result->pri_val, max->pri);
1967                 if (result->spr_val > max->spr)
1968                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1969                                       level, result->spr_val, max->spr);
1970                 if (result->cur_val > max->cur)
1971                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1972                                       level, result->cur_val, max->cur);
1973
1974                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1975                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1976                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1977                 result->enable = true;
1978         }
1979
1980         return ret;
1981 }
1982
1983 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1984                                  int level,
1985                                  const struct ilk_pipe_wm_parameters *p,
1986                                  struct intel_wm_level *result)
1987 {
1988         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1989         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1990         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1991
1992         /* WM1+ latency values stored in 0.5us units */
1993         if (level > 0) {
1994                 pri_latency *= 5;
1995                 spr_latency *= 5;
1996                 cur_latency *= 5;
1997         }
1998
1999         result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2000         result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2001         result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2002         result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2003         result->enable = true;
2004 }
2005
2006 static uint32_t
2007 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2008 {
2009         struct drm_i915_private *dev_priv = dev->dev_private;
2010         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2011         struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2012         u32 linetime, ips_linetime;
2013
2014         if (!intel_crtc_active(crtc))
2015                 return 0;
2016
2017         /* The WM are computed with base on how long it takes to fill a single
2018          * row at the given clock rate, multiplied by 8.
2019          * */
2020         linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2021                                      mode->crtc_clock);
2022         ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2023                                          intel_ddi_get_cdclk_freq(dev_priv));
2024
2025         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2026                PIPE_WM_LINETIME_TIME(linetime);
2027 }
2028
2029 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2030 {
2031         struct drm_i915_private *dev_priv = dev->dev_private;
2032
2033         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2034                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2035
2036                 wm[0] = (sskpd >> 56) & 0xFF;
2037                 if (wm[0] == 0)
2038                         wm[0] = sskpd & 0xF;
2039                 wm[1] = (sskpd >> 4) & 0xFF;
2040                 wm[2] = (sskpd >> 12) & 0xFF;
2041                 wm[3] = (sskpd >> 20) & 0x1FF;
2042                 wm[4] = (sskpd >> 32) & 0x1FF;
2043         } else if (INTEL_INFO(dev)->gen >= 6) {
2044                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2045
2046                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2047                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2048                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2049                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2050         } else if (INTEL_INFO(dev)->gen >= 5) {
2051                 uint32_t mltr = I915_READ(MLTR_ILK);
2052
2053                 /* ILK primary LP0 latency is 700 ns */
2054                 wm[0] = 7;
2055                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2056                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2057         }
2058 }
2059
2060 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2061 {
2062         /* ILK sprite LP0 latency is 1300 ns */
2063         if (INTEL_INFO(dev)->gen == 5)
2064                 wm[0] = 13;
2065 }
2066
2067 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2068 {
2069         /* ILK cursor LP0 latency is 1300 ns */
2070         if (INTEL_INFO(dev)->gen == 5)
2071                 wm[0] = 13;
2072
2073         /* WaDoubleCursorLP3Latency:ivb */
2074         if (IS_IVYBRIDGE(dev))
2075                 wm[3] *= 2;
2076 }
2077
2078 int ilk_wm_max_level(const struct drm_device *dev)
2079 {
2080         /* how many WM levels are we expecting */
2081         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2082                 return 4;
2083         else if (INTEL_INFO(dev)->gen >= 6)
2084                 return 3;
2085         else
2086                 return 2;
2087 }
2088
2089 static void intel_print_wm_latency(struct drm_device *dev,
2090                                    const char *name,
2091                                    const uint16_t wm[5])
2092 {
2093         int level, max_level = ilk_wm_max_level(dev);
2094
2095         for (level = 0; level <= max_level; level++) {
2096                 unsigned int latency = wm[level];
2097
2098                 if (latency == 0) {
2099                         DRM_ERROR("%s WM%d latency not provided\n",
2100                                   name, level);
2101                         continue;
2102                 }
2103
2104                 /* WM1+ latency values in 0.5us units */
2105                 if (level > 0)
2106                         latency *= 5;
2107
2108                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2109                               name, level, wm[level],
2110                               latency / 10, latency % 10);
2111         }
2112 }
2113
2114 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2115                                     uint16_t wm[5], uint16_t min)
2116 {
2117         int level, max_level = ilk_wm_max_level(dev_priv->dev);
2118
2119         if (wm[0] >= min)
2120                 return false;
2121
2122         wm[0] = max(wm[0], min);
2123         for (level = 1; level <= max_level; level++)
2124                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2125
2126         return true;
2127 }
2128
2129 static void snb_wm_latency_quirk(struct drm_device *dev)
2130 {
2131         struct drm_i915_private *dev_priv = dev->dev_private;
2132         bool changed;
2133
2134         /*
2135          * The BIOS provided WM memory latency values are often
2136          * inadequate for high resolution displays. Adjust them.
2137          */
2138         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2139                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2140                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2141
2142         if (!changed)
2143                 return;
2144
2145         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2146         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2147         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2148         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2149 }
2150
2151 static void ilk_setup_wm_latency(struct drm_device *dev)
2152 {
2153         struct drm_i915_private *dev_priv = dev->dev_private;
2154
2155         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2156
2157         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2158                sizeof(dev_priv->wm.pri_latency));
2159         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2160                sizeof(dev_priv->wm.pri_latency));
2161
2162         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2163         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2164
2165         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2166         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2167         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2168
2169         if (IS_GEN6(dev))
2170                 snb_wm_latency_quirk(dev);
2171 }
2172
2173 static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2174                                       struct ilk_pipe_wm_parameters *p)
2175 {
2176         struct drm_device *dev = crtc->dev;
2177         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2178         enum i915_pipe pipe = intel_crtc->pipe;
2179         struct drm_plane *plane;
2180
2181         if (!intel_crtc_active(crtc))
2182                 return;
2183
2184         p->active = true;
2185         p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal;
2186         p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2187         p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8;
2188         p->cur.bytes_per_pixel = 4;
2189         p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
2190         p->cur.horiz_pixels = intel_crtc->cursor_width;
2191         /* TODO: for now, assume primary and cursor planes are always enabled. */
2192         p->pri.enabled = true;
2193         p->cur.enabled = true;
2194
2195         drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
2196                 struct intel_plane *intel_plane = to_intel_plane(plane);
2197
2198                 if (intel_plane->pipe == pipe) {
2199                         p->spr = intel_plane->wm;
2200                         break;
2201                 }
2202         }
2203 }
2204
2205 static void ilk_compute_wm_config(struct drm_device *dev,
2206                                   struct intel_wm_config *config)
2207 {
2208         struct intel_crtc *intel_crtc;
2209
2210         /* Compute the currently _active_ config */
2211         for_each_intel_crtc(dev, intel_crtc) {
2212                 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
2213
2214                 if (!wm->pipe_enabled)
2215                         continue;
2216
2217                 config->sprites_enabled |= wm->sprites_enabled;
2218                 config->sprites_scaled |= wm->sprites_scaled;
2219                 config->num_pipes_active++;
2220         }
2221 }
2222
2223 /* Compute new watermarks for the pipe */
2224 static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2225                                   const struct ilk_pipe_wm_parameters *params,
2226                                   struct intel_pipe_wm *pipe_wm)
2227 {
2228         struct drm_device *dev = crtc->dev;
2229         const struct drm_i915_private *dev_priv = dev->dev_private;
2230         int level, max_level = ilk_wm_max_level(dev);
2231         /* LP0 watermark maximums depend on this pipe alone */
2232         struct intel_wm_config config = {
2233                 .num_pipes_active = 1,
2234                 .sprites_enabled = params->spr.enabled,
2235                 .sprites_scaled = params->spr.scaled,
2236         };
2237         struct ilk_wm_maximums max;
2238
2239         pipe_wm->pipe_enabled = params->active;
2240         pipe_wm->sprites_enabled = params->spr.enabled;
2241         pipe_wm->sprites_scaled = params->spr.scaled;
2242
2243         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2244         if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2245                 max_level = 1;
2246
2247         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2248         if (params->spr.scaled)
2249                 max_level = 0;
2250
2251         ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
2252
2253         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2254                 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2255
2256         /* LP0 watermarks always use 1/2 DDB partitioning */
2257         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2258
2259         /* At least LP0 must be valid */
2260         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2261                 return false;
2262
2263         ilk_compute_wm_reg_maximums(dev, 1, &max);
2264
2265         for (level = 1; level <= max_level; level++) {
2266                 struct intel_wm_level wm = {};
2267
2268                 ilk_compute_wm_level(dev_priv, level, params, &wm);
2269
2270                 /*
2271                  * Disable any watermark level that exceeds the
2272                  * register maximums since such watermarks are
2273                  * always invalid.
2274                  */
2275                 if (!ilk_validate_wm_level(level, &max, &wm))
2276                         break;
2277
2278                 pipe_wm->wm[level] = wm;
2279         }
2280
2281         return true;
2282 }
2283
2284 /*
2285  * Merge the watermarks from all active pipes for a specific level.
2286  */
2287 static void ilk_merge_wm_level(struct drm_device *dev,
2288                                int level,
2289                                struct intel_wm_level *ret_wm)
2290 {
2291         struct intel_crtc *intel_crtc;
2292
2293         ret_wm->enable = true;
2294
2295         for_each_intel_crtc(dev, intel_crtc) {
2296                 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2297                 const struct intel_wm_level *wm = &active->wm[level];
2298
2299                 if (!active->pipe_enabled)
2300                         continue;
2301
2302                 /*
2303                  * The watermark values may have been used in the past,
2304                  * so we must maintain them in the registers for some
2305                  * time even if the level is now disabled.
2306                  */
2307                 if (!wm->enable)
2308                         ret_wm->enable = false;
2309
2310                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2311                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2312                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2313                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2314         }
2315 }
2316
2317 /*
2318  * Merge all low power watermarks for all active pipes.
2319  */
2320 static void ilk_wm_merge(struct drm_device *dev,
2321                          const struct intel_wm_config *config,
2322                          const struct ilk_wm_maximums *max,
2323                          struct intel_pipe_wm *merged)
2324 {
2325         int level, max_level = ilk_wm_max_level(dev);
2326         int last_enabled_level = max_level;
2327
2328         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2329         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2330             config->num_pipes_active > 1)
2331                 return;
2332
2333         /* ILK: FBC WM must be disabled always */
2334         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2335
2336         /* merge each WM1+ level */
2337         for (level = 1; level <= max_level; level++) {
2338                 struct intel_wm_level *wm = &merged->wm[level];
2339
2340                 ilk_merge_wm_level(dev, level, wm);
2341
2342                 if (level > last_enabled_level)
2343                         wm->enable = false;
2344                 else if (!ilk_validate_wm_level(level, max, wm))
2345                         /* make sure all following levels get disabled */
2346                         last_enabled_level = level - 1;
2347
2348                 /*
2349                  * The spec says it is preferred to disable
2350                  * FBC WMs instead of disabling a WM level.
2351                  */
2352                 if (wm->fbc_val > max->fbc) {
2353                         if (wm->enable)
2354                                 merged->fbc_wm_enabled = false;
2355                         wm->fbc_val = 0;
2356                 }
2357         }
2358
2359         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2360         /*
2361          * FIXME this is racy. FBC might get enabled later.
2362          * What we should check here is whether FBC can be
2363          * enabled sometime later.
2364          */
2365         if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2366                 for (level = 2; level <= max_level; level++) {
2367                         struct intel_wm_level *wm = &merged->wm[level];
2368
2369                         wm->enable = false;
2370                 }
2371         }
2372 }
2373
2374 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2375 {
2376         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2377         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2378 }
2379
2380 /* The value we need to program into the WM_LPx latency field */
2381 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2382 {
2383         struct drm_i915_private *dev_priv = dev->dev_private;
2384
2385         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2386                 return 2 * level;
2387         else
2388                 return dev_priv->wm.pri_latency[level];
2389 }
2390
2391 static void ilk_compute_wm_results(struct drm_device *dev,
2392                                    const struct intel_pipe_wm *merged,
2393                                    enum intel_ddb_partitioning partitioning,
2394                                    struct ilk_wm_values *results)
2395 {
2396         struct intel_crtc *intel_crtc;
2397         int level, wm_lp;
2398
2399         results->enable_fbc_wm = merged->fbc_wm_enabled;
2400         results->partitioning = partitioning;
2401
2402         /* LP1+ register values */
2403         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2404                 const struct intel_wm_level *r;
2405
2406                 level = ilk_wm_lp_to_level(wm_lp, merged);
2407
2408                 r = &merged->wm[level];
2409
2410                 /*
2411                  * Maintain the watermark values even if the level is
2412                  * disabled. Doing otherwise could cause underruns.
2413                  */
2414                 results->wm_lp[wm_lp - 1] =
2415                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2416                         (r->pri_val << WM1_LP_SR_SHIFT) |
2417                         r->cur_val;
2418
2419                 if (r->enable)
2420                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2421
2422                 if (INTEL_INFO(dev)->gen >= 8)
2423                         results->wm_lp[wm_lp - 1] |=
2424                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2425                 else
2426                         results->wm_lp[wm_lp - 1] |=
2427                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2428
2429                 /*
2430                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2431                  * level is disabled. Doing otherwise could cause underruns.
2432                  */
2433                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2434                         WARN_ON(wm_lp != 1);
2435                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2436                 } else
2437                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2438         }
2439
2440         /* LP0 register values */
2441         for_each_intel_crtc(dev, intel_crtc) {
2442                 enum i915_pipe pipe = intel_crtc->pipe;
2443                 const struct intel_wm_level *r =
2444                         &intel_crtc->wm.active.wm[0];
2445
2446                 if (WARN_ON(!r->enable))
2447                         continue;
2448
2449                 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
2450
2451                 results->wm_pipe[pipe] =
2452                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2453                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2454                         r->cur_val;
2455         }
2456 }
2457
2458 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2459  * case both are at the same level. Prefer r1 in case they're the same. */
2460 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2461                                                   struct intel_pipe_wm *r1,
2462                                                   struct intel_pipe_wm *r2)
2463 {
2464         int level, max_level = ilk_wm_max_level(dev);
2465         int level1 = 0, level2 = 0;
2466
2467         for (level = 1; level <= max_level; level++) {
2468                 if (r1->wm[level].enable)
2469                         level1 = level;
2470                 if (r2->wm[level].enable)
2471                         level2 = level;
2472         }
2473
2474         if (level1 == level2) {
2475                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2476                         return r2;
2477                 else
2478                         return r1;
2479         } else if (level1 > level2) {
2480                 return r1;
2481         } else {
2482                 return r2;
2483         }
2484 }
2485
2486 /* dirty bits used to track which watermarks need changes */
2487 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2488 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2489 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2490 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2491 #define WM_DIRTY_FBC (1 << 24)
2492 #define WM_DIRTY_DDB (1 << 25)
2493
2494 static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2495                                          const struct ilk_wm_values *old,
2496                                          const struct ilk_wm_values *new)
2497 {
2498         unsigned int dirty = 0;
2499         enum i915_pipe pipe;
2500         int wm_lp;
2501
2502         for_each_pipe(pipe) {
2503                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2504                         dirty |= WM_DIRTY_LINETIME(pipe);
2505                         /* Must disable LP1+ watermarks too */
2506                         dirty |= WM_DIRTY_LP_ALL;
2507                 }
2508
2509                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2510                         dirty |= WM_DIRTY_PIPE(pipe);
2511                         /* Must disable LP1+ watermarks too */
2512                         dirty |= WM_DIRTY_LP_ALL;
2513                 }
2514         }
2515
2516         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2517                 dirty |= WM_DIRTY_FBC;
2518                 /* Must disable LP1+ watermarks too */
2519                 dirty |= WM_DIRTY_LP_ALL;
2520         }
2521
2522         if (old->partitioning != new->partitioning) {
2523                 dirty |= WM_DIRTY_DDB;
2524                 /* Must disable LP1+ watermarks too */
2525                 dirty |= WM_DIRTY_LP_ALL;
2526         }
2527
2528         /* LP1+ watermarks already deemed dirty, no need to continue */
2529         if (dirty & WM_DIRTY_LP_ALL)
2530                 return dirty;
2531
2532         /* Find the lowest numbered LP1+ watermark in need of an update... */
2533         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2534                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2535                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2536                         break;
2537         }
2538
2539         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2540         for (; wm_lp <= 3; wm_lp++)
2541                 dirty |= WM_DIRTY_LP(wm_lp);
2542
2543         return dirty;
2544 }
2545
2546 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2547                                unsigned int dirty)
2548 {
2549         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2550         bool changed = false;
2551
2552         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2553                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2554                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2555                 changed = true;
2556         }
2557         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2558                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2559                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2560                 changed = true;
2561         }
2562         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2563                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2564                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2565                 changed = true;
2566         }
2567
2568         /*
2569          * Don't touch WM1S_LP_EN here.
2570          * Doing so could cause underruns.
2571          */
2572
2573         return changed;
2574 }
2575
2576 /*
2577  * The spec says we shouldn't write when we don't need, because every write
2578  * causes WMs to be re-evaluated, expending some power.
2579  */
2580 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2581                                 struct ilk_wm_values *results)
2582 {
2583         struct drm_device *dev = dev_priv->dev;
2584         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2585         unsigned int dirty;
2586         uint32_t val;
2587
2588         dirty = ilk_compute_wm_dirty(dev, previous, results);
2589         if (!dirty)
2590                 return;
2591
2592         _ilk_disable_lp_wm(dev_priv, dirty);
2593
2594         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2595                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2596         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2597                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2598         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2599                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2600
2601         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2602                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2603         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2604                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2605         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2606                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2607
2608         if (dirty & WM_DIRTY_DDB) {
2609                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2610                         val = I915_READ(WM_MISC);
2611                         if (results->partitioning == INTEL_DDB_PART_1_2)
2612                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2613                         else
2614                                 val |= WM_MISC_DATA_PARTITION_5_6;
2615                         I915_WRITE(WM_MISC, val);
2616                 } else {
2617                         val = I915_READ(DISP_ARB_CTL2);
2618                         if (results->partitioning == INTEL_DDB_PART_1_2)
2619                                 val &= ~DISP_DATA_PARTITION_5_6;
2620                         else
2621                                 val |= DISP_DATA_PARTITION_5_6;
2622                         I915_WRITE(DISP_ARB_CTL2, val);
2623                 }
2624         }
2625
2626         if (dirty & WM_DIRTY_FBC) {
2627                 val = I915_READ(DISP_ARB_CTL);
2628                 if (results->enable_fbc_wm)
2629                         val &= ~DISP_FBC_WM_DIS;
2630                 else
2631                         val |= DISP_FBC_WM_DIS;
2632                 I915_WRITE(DISP_ARB_CTL, val);
2633         }
2634
2635         if (dirty & WM_DIRTY_LP(1) &&
2636             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2637                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2638
2639         if (INTEL_INFO(dev)->gen >= 7) {
2640                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2641                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2642                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2643                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2644         }
2645
2646         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2647                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2648         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2649                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2650         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2651                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2652
2653         dev_priv->wm.hw = *results;
2654 }
2655
2656 static bool ilk_disable_lp_wm(struct drm_device *dev)
2657 {
2658         struct drm_i915_private *dev_priv = dev->dev_private;
2659
2660         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2661 }
2662
2663 static void ilk_update_wm(struct drm_crtc *crtc)
2664 {
2665         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2666         struct drm_device *dev = crtc->dev;
2667         struct drm_i915_private *dev_priv = dev->dev_private;
2668         struct ilk_wm_maximums max;
2669         struct ilk_pipe_wm_parameters params = {};
2670         struct ilk_wm_values results = {};
2671         enum intel_ddb_partitioning partitioning;
2672         struct intel_pipe_wm pipe_wm = {};
2673         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
2674         struct intel_wm_config config = {};
2675
2676         ilk_compute_wm_parameters(crtc, &params);
2677
2678         intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2679
2680         if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2681                 return;
2682
2683         intel_crtc->wm.active = pipe_wm;
2684
2685         ilk_compute_wm_config(dev, &config);
2686
2687         ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
2688         ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
2689
2690         /* 5/6 split only in single pipe config on IVB+ */
2691         if (INTEL_INFO(dev)->gen >= 7 &&
2692             config.num_pipes_active == 1 && config.sprites_enabled) {
2693                 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
2694                 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
2695
2696                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
2697         } else {
2698                 best_lp_wm = &lp_wm_1_2;
2699         }
2700
2701         partitioning = (best_lp_wm == &lp_wm_1_2) ?
2702                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2703
2704         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2705
2706         ilk_write_wm_values(dev_priv, &results);
2707 }
2708
2709 static void ilk_update_sprite_wm(struct drm_plane *plane,
2710                                      struct drm_crtc *crtc,
2711                                      uint32_t sprite_width, int pixel_size,
2712                                      bool enabled, bool scaled)
2713 {
2714         struct drm_device *dev = plane->dev;
2715         struct intel_plane *intel_plane = to_intel_plane(plane);
2716
2717         intel_plane->wm.enabled = enabled;
2718         intel_plane->wm.scaled = scaled;
2719         intel_plane->wm.horiz_pixels = sprite_width;
2720         intel_plane->wm.bytes_per_pixel = pixel_size;
2721
2722         /*
2723          * IVB workaround: must disable low power watermarks for at least
2724          * one frame before enabling scaling.  LP watermarks can be re-enabled
2725          * when scaling is disabled.
2726          *
2727          * WaCxSRDisabledForSpriteScaling:ivb
2728          */
2729         if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
2730                 intel_wait_for_vblank(dev, intel_plane->pipe);
2731
2732         ilk_update_wm(crtc);
2733 }
2734
2735 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
2736 {
2737         struct drm_device *dev = crtc->dev;
2738         struct drm_i915_private *dev_priv = dev->dev_private;
2739         struct ilk_wm_values *hw = &dev_priv->wm.hw;
2740         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2741         struct intel_pipe_wm *active = &intel_crtc->wm.active;
2742         enum i915_pipe pipe = intel_crtc->pipe;
2743         static const unsigned int wm0_pipe_reg[] = {
2744                 [PIPE_A] = WM0_PIPEA_ILK,
2745                 [PIPE_B] = WM0_PIPEB_ILK,
2746                 [PIPE_C] = WM0_PIPEC_IVB,
2747         };
2748
2749         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
2750         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2751                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
2752
2753         active->pipe_enabled = intel_crtc_active(crtc);
2754
2755         if (active->pipe_enabled) {
2756                 u32 tmp = hw->wm_pipe[pipe];
2757
2758                 /*
2759                  * For active pipes LP0 watermark is marked as
2760                  * enabled, and LP1+ watermaks as disabled since
2761                  * we can't really reverse compute them in case
2762                  * multiple pipes are active.
2763                  */
2764                 active->wm[0].enable = true;
2765                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
2766                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
2767                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
2768                 active->linetime = hw->wm_linetime[pipe];
2769         } else {
2770                 int level, max_level = ilk_wm_max_level(dev);
2771
2772                 /*
2773                  * For inactive pipes, all watermark levels
2774                  * should be marked as enabled but zeroed,
2775                  * which is what we'd compute them to.
2776                  */
2777                 for (level = 0; level <= max_level; level++)
2778                         active->wm[level].enable = true;
2779         }
2780 }
2781
2782 void ilk_wm_get_hw_state(struct drm_device *dev)
2783 {
2784         struct drm_i915_private *dev_priv = dev->dev_private;
2785         struct ilk_wm_values *hw = &dev_priv->wm.hw;
2786         struct drm_crtc *crtc;
2787
2788         for_each_crtc(dev, crtc)
2789                 ilk_pipe_wm_get_hw_state(crtc);
2790
2791         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
2792         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
2793         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
2794
2795         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2796         if (INTEL_INFO(dev)->gen >= 7) {
2797                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2798                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2799         }
2800
2801         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2802                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2803                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2804         else if (IS_IVYBRIDGE(dev))
2805                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
2806                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2807
2808         hw->enable_fbc_wm =
2809                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2810 }
2811
2812 /**
2813  * intel_update_watermarks - update FIFO watermark values based on current modes
2814  *
2815  * Calculate watermark values for the various WM regs based on current mode
2816  * and plane configuration.
2817  *
2818  * There are several cases to deal with here:
2819  *   - normal (i.e. non-self-refresh)
2820  *   - self-refresh (SR) mode
2821  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2822  *   - lines are small relative to FIFO size (buffer can hold more than 2
2823  *     lines), so need to account for TLB latency
2824  *
2825  *   The normal calculation is:
2826  *     watermark = dotclock * bytes per pixel * latency
2827  *   where latency is platform & configuration dependent (we assume pessimal
2828  *   values here).
2829  *
2830  *   The SR calculation is:
2831  *     watermark = (trunc(latency/line time)+1) * surface width *
2832  *       bytes per pixel
2833  *   where
2834  *     line time = htotal / dotclock
2835  *     surface width = hdisplay for normal plane and 64 for cursor
2836  *   and latency is assumed to be high, as above.
2837  *
2838  * The final value programmed to the register should always be rounded up,
2839  * and include an extra 2 entries to account for clock crossings.
2840  *
2841  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2842  * to set the non-SR watermarks to 8.
2843  */
2844 void intel_update_watermarks(struct drm_crtc *crtc)
2845 {
2846         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2847
2848         if (dev_priv->display.update_wm)
2849                 dev_priv->display.update_wm(crtc);
2850 }
2851
2852 void intel_update_sprite_watermarks(struct drm_plane *plane,
2853                                     struct drm_crtc *crtc,
2854                                     uint32_t sprite_width, int pixel_size,
2855                                     bool enabled, bool scaled)
2856 {
2857         struct drm_i915_private *dev_priv = plane->dev->dev_private;
2858
2859         if (dev_priv->display.update_sprite_wm)
2860                 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
2861                                                    pixel_size, enabled, scaled);
2862 }
2863
2864 static struct drm_i915_gem_object *
2865 intel_alloc_context_page(struct drm_device *dev)
2866 {
2867         struct drm_i915_gem_object *ctx;
2868         int ret;
2869
2870         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2871
2872         ctx = i915_gem_alloc_object(dev, 4096);
2873         if (!ctx) {
2874                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2875                 return NULL;
2876         }
2877
2878         ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0);
2879         if (ret) {
2880                 DRM_ERROR("failed to pin power context: %d\n", ret);
2881                 goto err_unref;
2882         }
2883
2884         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2885         if (ret) {
2886                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2887                 goto err_unpin;
2888         }
2889
2890         return ctx;
2891
2892 err_unpin:
2893         i915_gem_object_ggtt_unpin(ctx);
2894 err_unref:
2895         drm_gem_object_unreference(&ctx->base);
2896         return NULL;
2897 }
2898
2899 /**
2900  * Lock protecting IPS related data structures
2901  */
2902 struct lock mchdev_lock;
2903 LOCK_SYSINIT(mchdev, &mchdev_lock, "mchdev", LK_CANRECURSE);
2904
2905 /* Global for IPS driver to get at the current i915 device. Protected by
2906  * mchdev_lock. */
2907 static struct drm_i915_private *i915_mch_dev;
2908
2909 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2910 {
2911         struct drm_i915_private *dev_priv = dev->dev_private;
2912         u16 rgvswctl;
2913
2914         assert_spin_locked(&mchdev_lock);
2915
2916         rgvswctl = I915_READ16(MEMSWCTL);
2917         if (rgvswctl & MEMCTL_CMD_STS) {
2918                 DRM_DEBUG("gpu busy, RCS change rejected\n");
2919                 return false; /* still busy with another command */
2920         }
2921
2922         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2923                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2924         I915_WRITE16(MEMSWCTL, rgvswctl);
2925         POSTING_READ16(MEMSWCTL);
2926
2927         rgvswctl |= MEMCTL_CMD_STS;
2928         I915_WRITE16(MEMSWCTL, rgvswctl);
2929
2930         return true;
2931 }
2932
2933 static void ironlake_enable_drps(struct drm_device *dev)
2934 {
2935         struct drm_i915_private *dev_priv = dev->dev_private;
2936         u32 rgvmodectl = I915_READ(MEMMODECTL);
2937         u8 fmax, fmin, fstart, vstart;
2938
2939         lockmgr(&mchdev_lock, LK_EXCLUSIVE);
2940
2941         /* Enable temp reporting */
2942         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2943         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2944
2945         /* 100ms RC evaluation intervals */
2946         I915_WRITE(RCUPEI, 100000);
2947         I915_WRITE(RCDNEI, 100000);
2948
2949         /* Set max/min thresholds to 90ms and 80ms respectively */
2950         I915_WRITE(RCBMAXAVG, 90000);
2951         I915_WRITE(RCBMINAVG, 80000);
2952
2953         I915_WRITE(MEMIHYST, 1);
2954
2955         /* Set up min, max, and cur for interrupt handling */
2956         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2957         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2958         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2959                 MEMMODE_FSTART_SHIFT;
2960
2961         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2962                 PXVFREQ_PX_SHIFT;
2963
2964         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2965         dev_priv->ips.fstart = fstart;
2966
2967         dev_priv->ips.max_delay = fstart;
2968         dev_priv->ips.min_delay = fmin;
2969         dev_priv->ips.cur_delay = fstart;
2970
2971         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2972                          fmax, fmin, fstart);
2973
2974         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2975
2976         /*
2977          * Interrupts will be enabled in ironlake_irq_postinstall
2978          */
2979
2980         I915_WRITE(VIDSTART, vstart);
2981         POSTING_READ(VIDSTART);
2982
2983         rgvmodectl |= MEMMODE_SWMODE_EN;
2984         I915_WRITE(MEMMODECTL, rgvmodectl);
2985
2986         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2987                 DRM_ERROR("stuck trying to change perf mode\n");
2988         mdelay(1);
2989
2990         ironlake_set_drps(dev, fstart);
2991
2992         dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2993                 I915_READ(0x112e0);
2994         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2995         dev_priv->ips.last_count2 = I915_READ(0x112f4);
2996         getrawmonotonic(&dev_priv->ips.last_time2);
2997
2998         lockmgr(&mchdev_lock, LK_RELEASE);
2999 }
3000
3001 static void ironlake_disable_drps(struct drm_device *dev)
3002 {
3003         struct drm_i915_private *dev_priv = dev->dev_private;
3004         u16 rgvswctl;
3005
3006         lockmgr(&mchdev_lock, LK_EXCLUSIVE);
3007
3008         rgvswctl = I915_READ16(MEMSWCTL);
3009
3010         /* Ack interrupts, disable EFC interrupt */
3011         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3012         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3013         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3014         I915_WRITE(DEIIR, DE_PCU_EVENT);
3015         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3016
3017         /* Go back to the starting frequency */
3018         ironlake_set_drps(dev, dev_priv->ips.fstart);
3019         mdelay(1);
3020         rgvswctl |= MEMCTL_CMD_STS;
3021         I915_WRITE(MEMSWCTL, rgvswctl);
3022         mdelay(1);
3023
3024         lockmgr(&mchdev_lock, LK_RELEASE);
3025 }
3026
3027 /* There's a funny hw issue where the hw returns all 0 when reading from
3028  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3029  * ourselves, instead of doing a rmw cycle (which might result in us clearing
3030  * all limits and the gpu stuck at whatever frequency it is at atm).
3031  */
3032 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
3033 {
3034         u32 limits;
3035
3036         /* Only set the down limit when we've reached the lowest level to avoid
3037          * getting more interrupts, otherwise leave this clear. This prevents a
3038          * race in the hw when coming out of rc6: There's a tiny window where
3039          * the hw runs at the minimal clock before selecting the desired
3040          * frequency, if the down threshold expires in that window we will not
3041          * receive a down interrupt. */
3042         limits = dev_priv->rps.max_freq_softlimit << 24;
3043         if (val <= dev_priv->rps.min_freq_softlimit)
3044                 limits |= dev_priv->rps.min_freq_softlimit << 16;
3045
3046         return limits;
3047 }
3048
3049 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3050 {
3051         int new_power;
3052
3053         new_power = dev_priv->rps.power;
3054         switch (dev_priv->rps.power) {
3055         case LOW_POWER:
3056                 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
3057                         new_power = BETWEEN;
3058                 break;
3059
3060         case BETWEEN:
3061                 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
3062                         new_power = LOW_POWER;
3063                 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
3064                         new_power = HIGH_POWER;
3065                 break;
3066
3067         case HIGH_POWER:
3068                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
3069                         new_power = BETWEEN;
3070                 break;
3071         }
3072         /* Max/min bins are special */
3073         if (val == dev_priv->rps.min_freq_softlimit)
3074                 new_power = LOW_POWER;
3075         if (val == dev_priv->rps.max_freq_softlimit)
3076                 new_power = HIGH_POWER;
3077         if (new_power == dev_priv->rps.power)
3078                 return;
3079
3080         /* Note the units here are not exactly 1us, but 1280ns. */
3081         switch (new_power) {
3082         case LOW_POWER:
3083                 /* Upclock if more than 95% busy over 16ms */
3084                 I915_WRITE(GEN6_RP_UP_EI, 12500);
3085                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3086
3087                 /* Downclock if less than 85% busy over 32ms */
3088                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3089                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3090
3091                 I915_WRITE(GEN6_RP_CONTROL,
3092                            GEN6_RP_MEDIA_TURBO |
3093                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3094                            GEN6_RP_MEDIA_IS_GFX |
3095                            GEN6_RP_ENABLE |
3096                            GEN6_RP_UP_BUSY_AVG |
3097                            GEN6_RP_DOWN_IDLE_AVG);
3098                 break;
3099
3100         case BETWEEN:
3101                 /* Upclock if more than 90% busy over 13ms */
3102                 I915_WRITE(GEN6_RP_UP_EI, 10250);
3103                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3104
3105                 /* Downclock if less than 75% busy over 32ms */
3106                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3107                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3108
3109                 I915_WRITE(GEN6_RP_CONTROL,
3110                            GEN6_RP_MEDIA_TURBO |
3111                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3112                            GEN6_RP_MEDIA_IS_GFX |
3113                            GEN6_RP_ENABLE |
3114                            GEN6_RP_UP_BUSY_AVG |
3115                            GEN6_RP_DOWN_IDLE_AVG);
3116                 break;
3117
3118         case HIGH_POWER:
3119                 /* Upclock if more than 85% busy over 10ms */
3120                 I915_WRITE(GEN6_RP_UP_EI, 8000);
3121                 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3122
3123                 /* Downclock if less than 60% busy over 32ms */
3124                 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3125                 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3126
3127                 I915_WRITE(GEN6_RP_CONTROL,
3128                            GEN6_RP_MEDIA_TURBO |
3129                            GEN6_RP_MEDIA_HW_NORMAL_MODE |
3130                            GEN6_RP_MEDIA_IS_GFX |
3131                            GEN6_RP_ENABLE |
3132                            GEN6_RP_UP_BUSY_AVG |
3133                            GEN6_RP_DOWN_IDLE_AVG);
3134                 break;
3135         }
3136
3137         dev_priv->rps.power = new_power;
3138         dev_priv->rps.last_adj = 0;
3139 }
3140
3141 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
3142 {
3143         u32 mask = 0;
3144
3145         if (val > dev_priv->rps.min_freq_softlimit)
3146                 mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
3147         if (val < dev_priv->rps.max_freq_softlimit)
3148                 mask |= GEN6_PM_RP_UP_THRESHOLD;
3149
3150         /* IVB and SNB hard hangs on looping batchbuffer
3151          * if GEN6_PM_UP_EI_EXPIRED is masked.
3152          */
3153         if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev))
3154                 mask |= GEN6_PM_RP_UP_EI_EXPIRED;
3155
3156         if (IS_GEN8(dev_priv->dev))
3157                 mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
3158
3159         return ~mask;
3160 }
3161
3162 /* gen6_set_rps is called to update the frequency request, but should also be
3163  * called when the range (min_delay and max_delay) is modified so that we can
3164  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
3165 void gen6_set_rps(struct drm_device *dev, u8 val)
3166 {
3167         struct drm_i915_private *dev_priv = dev->dev_private;
3168
3169         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3170         WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3171         WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3172
3173         /* min/max delay may still have been modified so be sure to
3174          * write the limits value.
3175          */
3176         if (val != dev_priv->rps.cur_freq) {
3177                 gen6_set_rps_thresholds(dev_priv, val);
3178
3179                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3180                         I915_WRITE(GEN6_RPNSWREQ,
3181                                    HSW_FREQUENCY(val));
3182                 else
3183                         I915_WRITE(GEN6_RPNSWREQ,
3184                                    GEN6_FREQUENCY(val) |
3185                                    GEN6_OFFSET(0) |
3186                                    GEN6_AGGRESSIVE_TURBO);
3187         }
3188
3189         /* Make sure we continue to get interrupts
3190          * until we hit the minimum or maximum frequencies.
3191          */
3192         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val));
3193         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3194
3195         POSTING_READ(GEN6_RPNSWREQ);
3196
3197         dev_priv->rps.cur_freq = val;
3198         trace_intel_gpu_freq_change(val * 50);
3199 }
3200
3201 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3202  *
3203  * * If Gfx is Idle, then
3204  * 1. Mask Turbo interrupts
3205  * 2. Bring up Gfx clock
3206  * 3. Change the freq to Rpn and wait till P-Unit updates freq
3207  * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3208  * 5. Unmask Turbo interrupts
3209 */
3210 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
3211 {
3212         int revision;
3213
3214         struct drm_device *dev = dev_priv->dev;
3215
3216         /* Latest VLV doesn't need to force the gfx clock */
3217         revision = pci_read_config(dev->dev, PCIR_REVID, 1);
3218         if (revision >= 0xd) {
3219                 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3220                 return;
3221         }
3222
3223         /*
3224          * When we are idle.  Drop to min voltage state.
3225          */
3226
3227         if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit)
3228                 return;
3229
3230         /* Mask turbo interrupt so that they will not come in between */
3231         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3232
3233         vlv_force_gfx_clock(dev_priv, true);
3234
3235         dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit;
3236
3237         vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ,
3238                                         dev_priv->rps.min_freq_softlimit);
3239
3240         if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS))
3241                                 & GENFREQSTATUS) == 0, 5))
3242                 DRM_ERROR("timed out waiting for Punit\n");
3243
3244         vlv_force_gfx_clock(dev_priv, false);
3245
3246         I915_WRITE(GEN6_PMINTRMSK,
3247                    gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
3248 }
3249
3250 void gen6_rps_idle(struct drm_i915_private *dev_priv)
3251 {
3252         struct drm_device *dev = dev_priv->dev;
3253
3254         mutex_lock(&dev_priv->rps.hw_lock);
3255         if (dev_priv->rps.enabled) {
3256                 if (IS_VALLEYVIEW(dev))
3257                         vlv_set_rps_idle(dev_priv);
3258                 else
3259                         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3260                 dev_priv->rps.last_adj = 0;
3261         }
3262         mutex_unlock(&dev_priv->rps.hw_lock);
3263 }
3264
3265 void gen6_rps_boost(struct drm_i915_private *dev_priv)
3266 {
3267         struct drm_device *dev = dev_priv->dev;
3268
3269         mutex_lock(&dev_priv->rps.hw_lock);
3270         if (dev_priv->rps.enabled) {
3271                 if (IS_VALLEYVIEW(dev))
3272                         valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3273                 else
3274                         gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit);
3275                 dev_priv->rps.last_adj = 0;
3276         }
3277         mutex_unlock(&dev_priv->rps.hw_lock);
3278 }
3279
3280 void valleyview_set_rps(struct drm_device *dev, u8 val)
3281 {
3282         struct drm_i915_private *dev_priv = dev->dev_private;
3283
3284         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3285         WARN_ON(val > dev_priv->rps.max_freq_softlimit);
3286         WARN_ON(val < dev_priv->rps.min_freq_softlimit);
3287
3288         DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3289                          vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3290                          dev_priv->rps.cur_freq,
3291                          vlv_gpu_freq(dev_priv, val), val);
3292
3293         if (val != dev_priv->rps.cur_freq)
3294                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3295
3296         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
3297
3298         dev_priv->rps.cur_freq = val;
3299         trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3300 }
3301
3302 static void gen8_disable_rps_interrupts(struct drm_device *dev)
3303 {
3304         struct drm_i915_private *dev_priv = dev->dev_private;
3305
3306         I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP);
3307         I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
3308                                    ~dev_priv->pm_rps_events);
3309         /* Complete PM interrupt masking here doesn't race with the rps work
3310          * item again unmasking PM interrupts because that is using a different
3311          * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
3312          * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
3313          * gen8_enable_rps will clean up. */
3314
3315         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
3316         dev_priv->rps.pm_iir = 0;
3317         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
3318
3319         I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3320 }
3321
3322 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3323 {
3324         struct drm_i915_private *dev_priv = dev->dev_private;
3325
3326         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3327         I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) &
3328                                 ~dev_priv->pm_rps_events);
3329         /* Complete PM interrupt masking here doesn't race with the rps work
3330          * item again unmasking PM interrupts because that is using a different
3331          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3332          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3333
3334         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
3335         dev_priv->rps.pm_iir = 0;
3336         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
3337
3338         I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3339 }
3340
3341 static void gen6_disable_rps(struct drm_device *dev)
3342 {
3343         struct drm_i915_private *dev_priv = dev->dev_private;
3344
3345         I915_WRITE(GEN6_RC_CONTROL, 0);
3346         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3347
3348         if (IS_BROADWELL(dev))
3349                 gen8_disable_rps_interrupts(dev);
3350         else
3351                 gen6_disable_rps_interrupts(dev);
3352 }
3353
3354 static void valleyview_disable_rps(struct drm_device *dev)
3355 {
3356         struct drm_i915_private *dev_priv = dev->dev_private;
3357
3358         I915_WRITE(GEN6_RC_CONTROL, 0);
3359
3360         gen6_disable_rps_interrupts(dev);
3361 }
3362
3363 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3364 {
3365         if (IS_VALLEYVIEW(dev)) {
3366                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
3367                         mode = GEN6_RC_CTL_RC6_ENABLE;
3368                 else
3369                         mode = 0;
3370         }
3371         DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3372                  (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3373                  (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3374                  (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3375 }
3376
3377 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
3378 {
3379         /* No RC6 before Ironlake */
3380         if (INTEL_INFO(dev)->gen < 5)
3381                 return 0;
3382
3383         /* RC6 is only on Ironlake mobile not on desktop */
3384         if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
3385                 return 0;
3386
3387         /* Respect the kernel parameter if it is set */
3388         if (enable_rc6 >= 0) {
3389                 int mask;
3390
3391                 if (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
3392                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
3393                                INTEL_RC6pp_ENABLE;
3394                 else
3395                         mask = INTEL_RC6_ENABLE;
3396
3397                 if ((enable_rc6 & mask) != enable_rc6)
3398                         DRM_INFO("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3399                                  enable_rc6 & mask, enable_rc6, mask);
3400
3401                 return enable_rc6 & mask;
3402         }
3403
3404         /* Disable RC6 on Ironlake */
3405         if (INTEL_INFO(dev)->gen == 5)
3406                 return 0;
3407
3408         if (IS_IVYBRIDGE(dev))
3409                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3410
3411         return INTEL_RC6_ENABLE;
3412 }
3413
3414 int intel_enable_rc6(const struct drm_device *dev)
3415 {
3416         return i915.enable_rc6;
3417 }
3418
3419 static void gen8_enable_rps_interrupts(struct drm_device *dev)
3420 {
3421         struct drm_i915_private *dev_priv = dev->dev_private;
3422
3423         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
3424         WARN_ON(dev_priv->rps.pm_iir);
3425         bdw_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3426         I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events);
3427         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
3428 }
3429
3430 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3431 {
3432         struct drm_i915_private *dev_priv = dev->dev_private;
3433
3434         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
3435         WARN_ON(dev_priv->rps.pm_iir);
3436         snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
3437         I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events);
3438         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
3439 }
3440
3441 static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap)
3442 {
3443         /* All of these values are in units of 50MHz */
3444         dev_priv->rps.cur_freq          = 0;
3445         /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3446         dev_priv->rps.rp1_freq          = (rp_state_cap >>  8) & 0xff;
3447         dev_priv->rps.rp0_freq          = (rp_state_cap >>  0) & 0xff;
3448         dev_priv->rps.min_freq          = (rp_state_cap >> 16) & 0xff;
3449         /* XXX: only BYT has a special efficient freq */
3450         dev_priv->rps.efficient_freq    = dev_priv->rps.rp1_freq;
3451         /* hw_max = RP0 until we check for overclocking */
3452         dev_priv->rps.max_freq          = dev_priv->rps.rp0_freq;
3453
3454         /* Preserve min/max settings in case of re-init */
3455         if (dev_priv->rps.max_freq_softlimit == 0)
3456                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3457
3458         if (dev_priv->rps.min_freq_softlimit == 0)
3459                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3460 }
3461
3462 static void gen8_enable_rps(struct drm_device *dev)
3463 {
3464         struct drm_i915_private *dev_priv = dev->dev_private;
3465         struct intel_engine_cs *ring;
3466         uint32_t rc6_mask = 0, rp_state_cap;
3467         int unused;
3468
3469         /* 1a: Software RC state - RC0 */
3470         I915_WRITE(GEN6_RC_STATE, 0);
3471
3472         /* 1c & 1d: Get forcewake during program sequence. Although the driver
3473          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3474         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3475
3476         /* 2a: Disable RC states. */
3477         I915_WRITE(GEN6_RC_CONTROL, 0);
3478
3479         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3480         parse_rp_state_cap(dev_priv, rp_state_cap);
3481
3482         /* 2b: Program RC6 thresholds.*/
3483         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
3484         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
3485         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3486         for_each_ring(ring, dev_priv, unused)
3487                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3488         I915_WRITE(GEN6_RC_SLEEP, 0);
3489         I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
3490
3491         /* 3: Enable RC6 */
3492         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3493                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3494         intel_print_rc6_info(dev, rc6_mask);
3495         I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3496                                     GEN6_RC_CTL_EI_MODE(1) |
3497                                     rc6_mask);
3498
3499         /* 4 Program defaults and thresholds for RPS*/
3500         I915_WRITE(GEN6_RPNSWREQ,
3501                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3502         I915_WRITE(GEN6_RC_VIDEO_FREQ,
3503                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
3504         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3505         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
3506
3507         /* Docs recommend 900MHz, and 300 MHz respectively */
3508         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3509                    dev_priv->rps.max_freq_softlimit << 24 |
3510                    dev_priv->rps.min_freq_softlimit << 16);
3511
3512         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
3513         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3514         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
3515         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
3516
3517         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3518
3519         /* 5: Enable RPS */
3520         I915_WRITE(GEN6_RP_CONTROL,
3521                    GEN6_RP_MEDIA_TURBO |
3522                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
3523                    GEN6_RP_MEDIA_IS_GFX |
3524                    GEN6_RP_ENABLE |
3525                    GEN6_RP_UP_BUSY_AVG |
3526                    GEN6_RP_DOWN_IDLE_AVG);
3527
3528         /* 6: Ring frequency + overclocking (our driver does this later */
3529
3530         gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8);
3531
3532         gen8_enable_rps_interrupts(dev);
3533
3534         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3535 }
3536
3537 static void gen6_enable_rps(struct drm_device *dev)
3538 {
3539         struct drm_i915_private *dev_priv = dev->dev_private;
3540         struct intel_engine_cs *ring;
3541         u32 rp_state_cap;
3542         u32 gt_perf_status;
3543         u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
3544         u32 gtfifodbg;
3545         int rc6_mode;
3546         int i, ret;
3547
3548         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3549
3550         /* Here begins a magic sequence of register writes to enable
3551          * auto-downclocking.
3552          *
3553          * Perhaps there might be some value in exposing these to
3554          * userspace...
3555          */
3556         I915_WRITE(GEN6_RC_STATE, 0);
3557
3558         /* Clear the DBG now so we don't confuse earlier errors */
3559         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3560                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3561                 I915_WRITE(GTFIFODBG, gtfifodbg);
3562         }
3563
3564         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3565
3566         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3567         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3568
3569         parse_rp_state_cap(dev_priv, rp_state_cap);
3570
3571         /* disable the counters and set deterministic thresholds */
3572         I915_WRITE(GEN6_RC_CONTROL, 0);
3573
3574         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3575         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3576         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3577         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3578         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3579
3580         for_each_ring(ring, dev_priv, i)
3581                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3582
3583         I915_WRITE(GEN6_RC_SLEEP, 0);
3584         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3585         if (IS_IVYBRIDGE(dev))
3586                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3587         else
3588                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3589         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3590         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3591
3592         /* Check if we are enabling RC6 */
3593         rc6_mode = intel_enable_rc6(dev_priv->dev);
3594         if (rc6_mode & INTEL_RC6_ENABLE)
3595                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3596
3597         /* We don't use those on Haswell */
3598         if (!IS_HASWELL(dev)) {
3599                 if (rc6_mode & INTEL_RC6p_ENABLE)
3600                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3601
3602                 if (rc6_mode & INTEL_RC6pp_ENABLE)
3603                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3604         }
3605
3606         intel_print_rc6_info(dev, rc6_mask);
3607
3608         I915_WRITE(GEN6_RC_CONTROL,
3609                    rc6_mask |
3610                    GEN6_RC_CTL_EI_MODE(1) |
3611                    GEN6_RC_CTL_HW_ENABLE);
3612
3613         /* Power down if completely idle for over 50ms */
3614         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
3615         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3616
3617         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3618         if (ret)
3619                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3620
3621         ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3622         if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3623                 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3624                                  (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
3625                                  (pcu_mbox & 0xff) * 50);
3626                 dev_priv->rps.max_freq = pcu_mbox & 0xff;
3627         }
3628
3629         dev_priv->rps.power = HIGH_POWER; /* force a reset */
3630         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
3631
3632         gen6_enable_rps_interrupts(dev);
3633
3634         rc6vids = 0;
3635         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3636         if (IS_GEN6(dev) && ret) {
3637                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3638         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3639                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3640                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3641                 rc6vids &= 0xffff00;
3642                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3643                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3644                 if (ret)
3645                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3646         }
3647
3648         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3649 }
3650
3651 static void __gen6_update_ring_freq(struct drm_device *dev)
3652 {
3653         struct drm_i915_private *dev_priv = dev->dev_private;
3654         int min_freq = 15;
3655         unsigned int gpu_freq;
3656         unsigned int max_ia_freq, min_ring_freq;
3657         int scaling_factor = 180;
3658
3659         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3660
3661 #if 0
3662         policy = cpufreq_cpu_get(0);
3663         if (policy) {
3664                 max_ia_freq = policy->cpuinfo.max_freq;
3665                 cpufreq_cpu_put(policy);
3666         } else {
3667                 /*
3668                  * Default to measured freq if none found, PCU will ensure we
3669                  * don't go over
3670                  */
3671                 max_ia_freq = tsc_khz;
3672         }
3673 #else
3674         max_ia_freq = tsc_frequency / 1000;
3675 #endif
3676
3677         /* Convert from kHz to MHz */
3678         max_ia_freq /= 1000;
3679
3680         min_ring_freq = I915_READ(DCLK) & 0xf;
3681         /* convert DDR frequency from units of 266.6MHz to bandwidth */
3682         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3683
3684         /*
3685          * For each potential GPU frequency, load a ring frequency we'd like
3686          * to use for memory access.  We do this by specifying the IA frequency
3687          * the PCU should use as a reference to determine the ring frequency.
3688          */
3689         for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
3690              gpu_freq--) {
3691                 int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
3692                 unsigned int ia_freq = 0, ring_freq = 0;
3693
3694                 if (INTEL_INFO(dev)->gen >= 8) {
3695                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
3696                         ring_freq = max(min_ring_freq, gpu_freq);
3697                 } else if (IS_HASWELL(dev)) {
3698                         ring_freq = mult_frac(gpu_freq, 5, 4);
3699                         ring_freq = max(min_ring_freq, ring_freq);
3700                         /* leave ia_freq as the default, chosen by cpufreq */
3701                 } else {
3702                         /* On older processors, there is no separate ring
3703                          * clock domain, so in order to boost the bandwidth
3704                          * of the ring, we need to upclock the CPU (ia_freq).
3705                          *
3706                          * For GPU frequencies less than 750MHz,
3707                          * just use the lowest ring freq.
3708                          */
3709                         if (gpu_freq < min_freq)
3710                                 ia_freq = 800;
3711                         else
3712                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3713                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3714                 }
3715
3716                 sandybridge_pcode_write(dev_priv,
3717                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3718                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3719                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3720                                         gpu_freq);
3721         }
3722 }
3723
3724 void gen6_update_ring_freq(struct drm_device *dev)
3725 {
3726         struct drm_i915_private *dev_priv = dev->dev_private;
3727
3728         if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
3729                 return;
3730
3731         mutex_lock(&dev_priv->rps.hw_lock);
3732         __gen6_update_ring_freq(dev);
3733         mutex_unlock(&dev_priv->rps.hw_lock);
3734 }
3735
3736 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3737 {
3738         u32 val, rp0;
3739
3740         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3741
3742         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3743         /* Clamp to max */
3744         rp0 = min_t(u32, rp0, 0xea);
3745
3746         return rp0;
3747 }
3748
3749 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3750 {
3751         u32 val, rpe;
3752
3753         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
3754         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
3755         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
3756         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3757
3758         return rpe;
3759 }
3760
3761 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3762 {
3763         return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
3764 }
3765
3766 /* Check that the pctx buffer wasn't move under us. */
3767 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
3768 {
3769         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
3770
3771         /* DragonFly - if EDID fails vlv_pctx can wind up NULL */
3772         if (WARN_ON(!dev_priv->vlv_pctx))
3773                 return;
3774
3775         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
3776                              dev_priv->vlv_pctx->stolen->start);
3777 }
3778
3779 static void valleyview_setup_pctx(struct drm_device *dev)
3780 {
3781         struct drm_i915_private *dev_priv = dev->dev_private;
3782         struct drm_i915_gem_object *pctx;
3783         unsigned long pctx_paddr;
3784         u32 pcbr;
3785         int pctx_size = 24*1024;
3786
3787         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3788
3789         pcbr = I915_READ(VLV_PCBR);
3790         if (pcbr) {
3791                 /* BIOS set it up already, grab the pre-alloc'd space */
3792                 int pcbr_offset;
3793
3794                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3795                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3796                                                                       pcbr_offset,
3797                                                                       I915_GTT_OFFSET_NONE,
3798                                                                       pctx_size);
3799                 goto out;
3800         }
3801
3802         /*
3803          * From the Gunit register HAS:
3804          * The Gfx driver is expected to program this register and ensure
3805          * proper allocation within Gfx stolen memory.  For example, this
3806          * register should be programmed such than the PCBR range does not
3807          * overlap with other ranges, such as the frame buffer, protected
3808          * memory, or any other relevant ranges.
3809          */
3810         pctx = i915_gem_object_create_stolen(dev, pctx_size);
3811         if (!pctx) {
3812                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3813                 return;
3814         }
3815
3816         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3817         I915_WRITE(VLV_PCBR, pctx_paddr);
3818
3819 out:
3820         dev_priv->vlv_pctx = pctx;
3821 }
3822
3823 static void valleyview_cleanup_pctx(struct drm_device *dev)
3824 {
3825         struct drm_i915_private *dev_priv = dev->dev_private;
3826
3827         if (WARN_ON(!dev_priv->vlv_pctx))
3828                 return;
3829
3830         drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3831         dev_priv->vlv_pctx = NULL;
3832 }
3833
3834 static void valleyview_init_gt_powersave(struct drm_device *dev)
3835 {
3836         struct drm_i915_private *dev_priv = dev->dev_private;
3837
3838         valleyview_setup_pctx(dev);
3839
3840         mutex_lock(&dev_priv->rps.hw_lock);
3841
3842         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
3843         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
3844         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3845                          vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq),
3846                          dev_priv->rps.max_freq);
3847
3848         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
3849         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3850                          vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3851                          dev_priv->rps.efficient_freq);
3852
3853         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
3854         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3855                          vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq),
3856                          dev_priv->rps.min_freq);
3857
3858         /* Preserve min/max settings in case of re-init */
3859         if (dev_priv->rps.max_freq_softlimit == 0)
3860                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
3861
3862         if (dev_priv->rps.min_freq_softlimit == 0)
3863                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
3864
3865         mutex_unlock(&dev_priv->rps.hw_lock);
3866 }
3867
3868 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
3869 {
3870         valleyview_cleanup_pctx(dev);
3871 }
3872
3873 static void valleyview_enable_rps(struct drm_device *dev)
3874 {
3875         struct drm_i915_private *dev_priv = dev->dev_private;
3876         struct intel_engine_cs *ring;
3877         u32 gtfifodbg, val, rc6_mode = 0;
3878         int i;
3879
3880         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3881
3882         valleyview_check_pctx(dev_priv);
3883
3884         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3885                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
3886                                  gtfifodbg);
3887                 I915_WRITE(GTFIFODBG, gtfifodbg);
3888         }
3889
3890         /* If VLV, Forcewake all wells, else re-direct to regular path */
3891         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3892
3893         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3894         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3895         I915_WRITE(GEN6_RP_UP_EI, 66000);
3896         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3897
3898         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3899
3900         I915_WRITE(GEN6_RP_CONTROL,
3901                    GEN6_RP_MEDIA_TURBO |
3902                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
3903                    GEN6_RP_MEDIA_IS_GFX |
3904                    GEN6_RP_ENABLE |
3905                    GEN6_RP_UP_BUSY_AVG |
3906                    GEN6_RP_DOWN_IDLE_CONT);
3907
3908         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3909         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3910         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3911
3912         for_each_ring(ring, dev_priv, i)
3913                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3914
3915         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
3916
3917         /* allows RC6 residency counter to work */
3918         I915_WRITE(VLV_COUNTER_CONTROL,
3919                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
3920                                       VLV_MEDIA_RC6_COUNT_EN |
3921                                       VLV_RENDER_RC6_COUNT_EN));
3922         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3923                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
3924
3925         intel_print_rc6_info(dev, rc6_mode);
3926
3927         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
3928
3929         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
3930
3931         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3932         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3933
3934         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
3935         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
3936                          vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
3937                          dev_priv->rps.cur_freq);
3938
3939         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
3940                          vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
3941                          dev_priv->rps.efficient_freq);
3942
3943         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
3944
3945         gen6_enable_rps_interrupts(dev);
3946
3947         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3948 }
3949
3950 void ironlake_teardown_rc6(struct drm_device *dev)
3951 {
3952         struct drm_i915_private *dev_priv = dev->dev_private;
3953
3954         if (dev_priv->ips.renderctx) {
3955                 i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx);
3956                 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3957                 dev_priv->ips.renderctx = NULL;
3958         }
3959
3960         if (dev_priv->ips.pwrctx) {
3961                 i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx);
3962                 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3963                 dev_priv->ips.pwrctx = NULL;
3964         }
3965 }
3966
3967 static void ironlake_disable_rc6(struct drm_device *dev)
3968 {
3969         struct drm_i915_private *dev_priv = dev->dev_private;
3970
3971         if (I915_READ(PWRCTXA)) {
3972                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3973                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3974                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3975                          50);
3976
3977                 I915_WRITE(PWRCTXA, 0);
3978                 POSTING_READ(PWRCTXA);
3979
3980                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3981                 POSTING_READ(RSTDBYCTL);
3982         }
3983 }
3984
3985 static int ironlake_setup_rc6(struct drm_device *dev)
3986 {
3987         struct drm_i915_private *dev_priv = dev->dev_private;
3988
3989         if (dev_priv->ips.renderctx == NULL)
3990                 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3991         if (!dev_priv->ips.renderctx)
3992                 return -ENOMEM;
3993
3994         if (dev_priv->ips.pwrctx == NULL)
3995                 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3996         if (!dev_priv->ips.pwrctx) {
3997                 ironlake_teardown_rc6(dev);
3998                 return -ENOMEM;
3999         }
4000
4001         return 0;
4002 }
4003
4004 static void ironlake_enable_rc6(struct drm_device *dev)
4005 {
4006         struct drm_i915_private *dev_priv = dev->dev_private;
4007         struct intel_engine_cs *ring = &dev_priv->ring[RCS];
4008         bool was_interruptible;
4009         int ret;
4010
4011         /* rc6 disabled by default due to repeated reports of hanging during
4012          * boot and resume.
4013          */
4014         if (!intel_enable_rc6(dev))
4015                 return;
4016
4017         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4018
4019         ret = ironlake_setup_rc6(dev);
4020         if (ret)
4021                 return;
4022
4023         was_interruptible = dev_priv->mm.interruptible;
4024         dev_priv->mm.interruptible = false;
4025
4026         /*
4027          * GPU can automatically power down the render unit if given a page
4028          * to save state.
4029          */
4030         ret = intel_ring_begin(ring, 6);
4031         if (ret) {
4032                 ironlake_teardown_rc6(dev);
4033                 dev_priv->mm.interruptible = was_interruptible;
4034                 return;
4035         }
4036
4037         intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4038         intel_ring_emit(ring, MI_SET_CONTEXT);
4039         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
4040                         MI_MM_SPACE_GTT |
4041                         MI_SAVE_EXT_STATE_EN |
4042                         MI_RESTORE_EXT_STATE_EN |
4043                         MI_RESTORE_INHIBIT);
4044         intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4045         intel_ring_emit(ring, MI_NOOP);
4046         intel_ring_emit(ring, MI_FLUSH);
4047         intel_ring_advance(ring);
4048
4049         /*
4050          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4051          * does an implicit flush, combined with MI_FLUSH above, it should be
4052          * safe to assume that renderctx is valid
4053          */
4054         ret = intel_ring_idle(ring);
4055         dev_priv->mm.interruptible = was_interruptible;
4056         if (ret) {
4057                 DRM_ERROR("failed to enable ironlake power savings\n");
4058                 ironlake_teardown_rc6(dev);
4059                 return;
4060         }
4061
4062         I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
4063         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4064
4065         intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE);
4066 }
4067
4068 static unsigned long intel_pxfreq(u32 vidfreq)
4069 {
4070         unsigned long freq;
4071         int div = (vidfreq & 0x3f0000) >> 16;
4072         int post = (vidfreq & 0x3000) >> 12;
4073         int pre = (vidfreq & 0x7);
4074
4075         if (!pre)
4076                 return 0;
4077
4078         freq = ((div * 133333) / ((1<<post) * pre));
4079
4080         return freq;
4081 }
4082
4083 static const struct cparams {
4084         u16 i;
4085         u16 t;
4086         u16 m;
4087         u16 c;
4088 } cparams[] = {
4089         { 1, 1333, 301, 28664 },
4090         { 1, 1066, 294, 24460 },
4091         { 1, 800, 294, 25192 },
4092         { 0, 1333, 276, 27605 },
4093         { 0, 1066, 276, 27605 },
4094         { 0, 800, 231, 23784 },
4095 };
4096
4097 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
4098 {
4099         u64 total_count, diff, ret;
4100         u32 count1, count2, count3, m = 0, c = 0;
4101         unsigned long now = jiffies_to_msecs(jiffies), diff1;
4102         int i;
4103
4104         assert_spin_locked(&mchdev_lock);
4105
4106         diff1 = now - dev_priv->ips.last_time1;
4107
4108         /* Prevent division-by-zero if we are asking too fast.
4109          * Also, we don't get interesting results if we are polling
4110          * faster than once in 10ms, so just return the saved value
4111          * in such cases.
4112          */
4113         if (diff1 <= 10)
4114                 return dev_priv->ips.chipset_power;
4115
4116         count1 = I915_READ(DMIEC);
4117         count2 = I915_READ(DDREC);
4118         count3 = I915_READ(CSIEC);
4119
4120         total_count = count1 + count2 + count3;
4121
4122         /* FIXME: handle per-counter overflow */
4123         if (total_count < dev_priv->ips.last_count1) {
4124                 diff = ~0UL - dev_priv->ips.last_count1;
4125                 diff += total_count;
4126         } else {
4127                 diff = total_count - dev_priv->ips.last_count1;
4128         }
4129
4130         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
4131                 if (cparams[i].i == dev_priv->ips.c_m &&
4132                     cparams[i].t == dev_priv->ips.r_t) {
4133                         m = cparams[i].m;
4134                         c = cparams[i].c;
4135                         break;
4136                 }
4137         }
4138
4139         diff = div_u64(diff, diff1);
4140         ret = ((m * diff) + c);
4141         ret = div_u64(ret, 10);
4142
4143         dev_priv->ips.last_count1 = total_count;
4144         dev_priv->ips.last_time1 = now;
4145
4146         dev_priv->ips.chipset_power = ret;
4147
4148         return ret;
4149 }
4150
4151 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4152 {
4153         struct drm_device *dev = dev_priv->dev;
4154         unsigned long val;
4155
4156         if (INTEL_INFO(dev)->gen != 5)
4157                 return 0;
4158
4159         lockmgr(&mchdev_lock, LK_EXCLUSIVE);
4160
4161         val = __i915_chipset_val(dev_priv);
4162
4163         lockmgr(&mchdev_lock, LK_RELEASE);
4164
4165         return val;
4166 }
4167
4168 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4169 {
4170         unsigned long m, x, b;
4171         u32 tsfs;
4172
4173         tsfs = I915_READ(TSFS);
4174
4175         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4176         x = I915_READ8(TR1);
4177
4178         b = tsfs & TSFS_INTR_MASK;
4179
4180         return ((m * x) / 127) - b;
4181 }
4182
4183 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4184 {
4185         struct drm_device *dev = dev_priv->dev;
4186         static const struct v_table {
4187                 u16 vd; /* in .1 mil */
4188                 u16 vm; /* in .1 mil */
4189         } v_table[] = {
4190                 { 0, 0, },
4191                 { 375, 0, },
4192                 { 500, 0, },
4193                 { 625, 0, },
4194                 { 750, 0, },
4195                 { 875, 0, },
4196                 { 1000, 0, },
4197                 { 1125, 0, },
4198                 { 4125, 3000, },
4199                 { 4125, 3000, },
4200                 { 4125, 3000, },
4201                 { 4125, 3000, },
4202                 { 4125, 3000, },
4203                 { 4125, 3000, },
4204                 { 4125, 3000, },
4205                 { 4125, 3000, },
4206                 { 4125, 3000, },
4207                 { 4125, 3000, },
4208                 { 4125, 3000, },
4209                 { 4125, 3000, },
4210                 { 4125, 3000, },
4211                 { 4125, 3000, },
4212                 { 4125, 3000, },
4213                 { 4125, 3000, },
4214                 { 4125, 3000, },
4215                 { 4125, 3000, },
4216                 { 4125, 3000, },
4217                 { 4125, 3000, },
4218                 { 4125, 3000, },
4219                 { 4125, 3000, },
4220                 { 4125, 3000, },
4221                 { 4125, 3000, },
4222                 { 4250, 3125, },
4223                 { 4375, 3250, },
4224                 { 4500, 3375, },
4225                 { 4625, 3500, },
4226                 { 4750, 3625, },
4227                 { 4875, 3750, },
4228                 { 5000, 3875, },
4229                 { 5125, 4000, },
4230                 { 5250, 4125, },
4231                 { 5375, 4250, },
4232                 { 5500, 4375, },
4233                 { 5625, 4500, },
4234                 { 5750, 4625, },
4235                 { 5875, 4750, },
4236                 { 6000, 4875, },
4237                 { 6125, 5000, },
4238                 { 6250, 5125, },
4239                 { 6375, 5250, },
4240                 { 6500, 5375, },
4241                 { 6625, 5500, },
4242                 { 6750, 5625, },
4243                 { 6875, 5750, },
4244                 { 7000, 5875, },
4245                 { 7125, 6000, },
4246                 { 7250, 6125, },
4247                 { 7375, 6250, },
4248                 { 7500, 6375, },
4249                 { 7625, 6500, },
4250                 { 7750, 6625, },
4251                 { 7875, 6750, },
4252                 { 8000, 6875, },
4253                 { 8125, 7000, },
4254                 { 8250, 7125, },
4255                 { 8375, 7250, },
4256                 { 8500, 7375, },
4257                 { 8625, 7500, },
4258                 { 8750, 7625, },
4259                 { 8875, 7750, },
4260                 { 9000, 7875, },
4261                 { 9125, 8000, },
4262                 { 9250, 8125, },
4263                 { 9375, 8250, },
4264                 { 9500, 8375, },
4265                 { 9625, 8500, },
4266                 { 9750, 8625, },
4267                 { 9875, 8750, },
4268                 { 10000, 8875, },
4269                 { 10125, 9000, },
4270                 { 10250, 9125, },
4271                 { 10375, 9250, },
4272                 { 10500, 9375, },
4273                 { 10625, 9500, },
4274                 { 10750, 9625, },
4275                 { 10875, 9750, },
4276                 { 11000, 9875, },
4277                 { 11125, 10000, },
4278                 { 11250, 10125, },
4279                 { 11375, 10250, },
4280                 { 11500, 10375, },
4281                 { 11625, 10500, },
4282                 { 11750, 10625, },
4283                 { 11875, 10750, },
4284                 { 12000, 10875, },
4285                 { 12125, 11000, },
4286                 { 12250, 11125, },
4287                 { 12375, 11250, },
4288                 { 12500, 11375, },
4289                 { 12625, 11500, },
4290                 { 12750, 11625, },
4291                 { 12875, 11750, },
4292                 { 13000, 11875, },
4293                 { 13125, 12000, },
4294                 { 13250, 12125, },
4295                 { 13375, 12250, },
4296                 { 13500, 12375, },
4297                 { 13625, 12500, },
4298                 { 13750, 12625, },
4299                 { 13875, 12750, },
4300                 { 14000, 12875, },
4301                 { 14125, 13000, },
4302                 { 14250, 13125, },
4303                 { 14375, 13250, },
4304                 { 14500, 13375, },
4305                 { 14625, 13500, },
4306                 { 14750, 13625, },
4307                 { 14875, 13750, },
4308                 { 15000, 13875, },
4309                 { 15125, 14000, },
4310                 { 15250, 14125, },
4311                 { 15375, 14250, },
4312                 { 15500, 14375, },
4313                 { 15625, 14500, },
4314                 { 15750, 14625, },
4315                 { 15875, 14750, },
4316                 { 16000, 14875, },
4317                 { 16125, 15000, },
4318         };
4319         if (INTEL_INFO(dev)->is_mobile)
4320                 return v_table[pxvid].vm;
4321         else
4322                 return v_table[pxvid].vd;
4323 }
4324
4325 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4326 {
4327         struct timespec now, diff1;
4328         u64 diff;
4329         unsigned long diffms;
4330         u32 count;
4331
4332         assert_spin_locked(&mchdev_lock);
4333
4334         getrawmonotonic(&now);
4335         diff1 = timespec_sub(now, dev_priv->ips.last_time2);
4336
4337         /* Don't divide by 0 */
4338         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4339         if (!diffms)
4340                 return;
4341
4342         count = I915_READ(GFXEC);
4343
4344         if (count < dev_priv->ips.last_count2) {
4345                 diff = ~0UL - dev_priv->ips.last_count2;
4346                 diff += count;
4347         } else {
4348                 diff = count - dev_priv->ips.last_count2;
4349         }
4350
4351         dev_priv->ips.last_count2 = count;
4352         dev_priv->ips.last_time2 = now;
4353
4354         /* More magic constants... */
4355         diff = diff * 1181;
4356         diff = div_u64(diff, diffms * 10);
4357         dev_priv->ips.gfx_power = diff;
4358 }
4359
4360 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4361 {
4362         struct drm_device *dev = dev_priv->dev;
4363
4364         if (INTEL_INFO(dev)->gen != 5)
4365                 return;
4366
4367         lockmgr(&mchdev_lock, LK_EXCLUSIVE);
4368
4369         __i915_update_gfx_val(dev_priv);
4370
4371         lockmgr(&mchdev_lock, LK_RELEASE);
4372 }
4373
4374 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4375 {
4376         unsigned long t, corr, state1, corr2, state2;
4377         u32 pxvid, ext_v;
4378
4379         assert_spin_locked(&mchdev_lock);
4380
4381         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
4382         pxvid = (pxvid >> 24) & 0x7f;
4383         ext_v = pvid_to_extvid(dev_priv, pxvid);
4384
4385         state1 = ext_v;
4386
4387         t = i915_mch_val(dev_priv);
4388
4389         /* Revel in the empirically derived constants */
4390
4391         /* Correction factor in 1/100000 units */
4392         if (t > 80)
4393                 corr = ((t * 2349) + 135940);
4394         else if (t >= 50)
4395                 corr = ((t * 964) + 29317);
4396         else /* < 50 */
4397                 corr = ((t * 301) + 1004);
4398
4399         corr = corr * ((150142 * state1) / 10000 - 78642);
4400         corr /= 100000;
4401         corr2 = (corr * dev_priv->ips.corr);
4402
4403         state2 = (corr2 * state1) / 10000;
4404         state2 /= 100; /* convert to mW */
4405
4406         __i915_update_gfx_val(dev_priv);
4407
4408         return dev_priv->ips.gfx_power + state2;
4409 }
4410
4411 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4412 {
4413         struct drm_device *dev = dev_priv->dev;
4414         unsigned long val;
4415
4416         if (INTEL_INFO(dev)->gen != 5)
4417                 return 0;
4418
4419         lockmgr(&mchdev_lock, LK_EXCLUSIVE);
4420
4421         val = __i915_gfx_val(dev_priv);
4422
4423         lockmgr(&mchdev_lock, LK_RELEASE);
4424
4425         return val;
4426 }
4427
4428 /**
4429  * i915_read_mch_val - return value for IPS use
4430  *
4431  * Calculate and return a value for the IPS driver to use when deciding whether
4432  * we have thermal and power headroom to increase CPU or GPU power budget.
4433  */
4434 unsigned long i915_read_mch_val(void)
4435 {
4436         struct drm_i915_private *dev_priv;
4437         unsigned long chipset_val, graphics_val, ret = 0;
4438
4439         lockmgr(&mchdev_lock, LK_EXCLUSIVE);
4440         if (!i915_mch_dev)
4441                 goto out_unlock;
4442         dev_priv = i915_mch_dev;
4443
4444         chipset_val = __i915_chipset_val(dev_priv);
4445         graphics_val = __i915_gfx_val(dev_priv);
4446
4447         ret = chipset_val + graphics_val;
4448
4449 out_unlock:
4450         lockmgr(&mchdev_lock, LK_RELEASE);
4451
4452         return ret;
4453 }
4454
4455 /**
4456  * i915_gpu_raise - raise GPU frequency limit
4457  *
4458  * Raise the limit; IPS indicates we have thermal headroom.
4459  */
4460 bool i915_gpu_raise(void)
4461 {
4462         struct drm_i915_private *dev_priv;
4463         bool ret = true;
4464
4465         lockmgr(&mchdev_lock, LK_EXCLUSIVE);
4466         if (!i915_mch_dev) {
4467                 ret = false;
4468                 goto out_unlock;
4469         }
4470         dev_priv = i915_mch_dev;
4471
4472         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4473                 dev_priv->ips.max_delay--;
4474
4475 out_unlock:
4476         lockmgr(&mchdev_lock, LK_RELEASE);
4477
4478         return ret;
4479 }
4480
4481 /**
4482  * i915_gpu_lower - lower GPU frequency limit
4483  *
4484  * IPS indicates we're close to a thermal limit, so throttle back the GPU
4485  * frequency maximum.
4486  */
4487 bool i915_gpu_lower(void)
4488 {
4489         struct drm_i915_private *dev_priv;
4490         bool ret = true;
4491
4492         lockmgr(&mchdev_lock, LK_EXCLUSIVE);
4493         if (!i915_mch_dev) {
4494                 ret = false;
4495                 goto out_unlock;
4496         }
4497         dev_priv = i915_mch_dev;
4498
4499         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4500                 dev_priv->ips.max_delay++;
4501
4502 out_unlock:
4503         lockmgr(&mchdev_lock, LK_RELEASE);
4504
4505         return ret;
4506 }
4507
4508 /**
4509  * i915_gpu_busy - indicate GPU business to IPS
4510  *
4511  * Tell the IPS driver whether or not the GPU is busy.
4512  */
4513 bool i915_gpu_busy(void)
4514 {
4515         struct drm_i915_private *dev_priv;
4516         struct intel_engine_cs *ring;
4517         bool ret = false;
4518         int i;
4519
4520         lockmgr(&mchdev_lock, LK_EXCLUSIVE);
4521         if (!i915_mch_dev)
4522                 goto out_unlock;
4523         dev_priv = i915_mch_dev;
4524
4525         for_each_ring(ring, dev_priv, i)
4526                 ret |= !list_empty(&ring->request_list);
4527
4528 out_unlock:
4529         lockmgr(&mchdev_lock, LK_RELEASE);
4530
4531         return ret;
4532 }
4533
4534 /**
4535  * i915_gpu_turbo_disable - disable graphics turbo
4536  *
4537  * Disable graphics turbo by resetting the max frequency and setting the
4538  * current frequency to the default.
4539  */
4540 bool i915_gpu_turbo_disable(void)
4541 {
4542         struct drm_i915_private *dev_priv;
4543         bool ret = true;
4544
4545         lockmgr(&mchdev_lock, LK_EXCLUSIVE);
4546         if (!i915_mch_dev) {
4547                 ret = false;
4548                 goto out_unlock;
4549         }
4550         dev_priv = i915_mch_dev;
4551
4552         dev_priv->ips.max_delay = dev_priv->ips.fstart;
4553
4554         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4555                 ret = false;
4556
4557 out_unlock:
4558         lockmgr(&mchdev_lock, LK_RELEASE);
4559
4560         return ret;
4561 }
4562
4563 #if 0
4564 /**
4565  * Tells the intel_ips driver that the i915 driver is now loaded, if
4566  * IPS got loaded first.
4567  *
4568  * This awkward dance is so that neither module has to depend on the
4569  * other in order for IPS to do the appropriate communication of
4570  * GPU turbo limits to i915.
4571  */
4572 static void
4573 ips_ping_for_i915_load(void)
4574 {
4575         void (*link)(void);
4576
4577         link = symbol_get(ips_link_to_i915_driver);
4578         if (link) {
4579                 link();
4580                 symbol_put(ips_link_to_i915_driver);
4581         }
4582 }
4583 #endif
4584
4585 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4586 {
4587         /* We only register the i915 ips part with intel-ips once everything is
4588          * set up, to avoid intel-ips sneaking in and reading bogus values. */
4589         lockmgr(&mchdev_lock, LK_EXCLUSIVE);
4590         i915_mch_dev = dev_priv;
4591         lockmgr(&mchdev_lock, LK_RELEASE);
4592 }
4593
4594 void intel_gpu_ips_teardown(void)
4595 {
4596         lockmgr(&mchdev_lock, LK_EXCLUSIVE);
4597         i915_mch_dev = NULL;
4598         lockmgr(&mchdev_lock, LK_RELEASE);
4599 }
4600
4601 static void intel_init_emon(struct drm_device *dev)
4602 {
4603         struct drm_i915_private *dev_priv = dev->dev_private;
4604         u32 lcfuse;
4605         u8 pxw[16];
4606         int i;
4607
4608         /* Disable to program */
4609         I915_WRITE(ECR, 0);
4610         POSTING_READ(ECR);
4611
4612         /* Program energy weights for various events */
4613         I915_WRITE(SDEW, 0x15040d00);
4614         I915_WRITE(CSIEW0, 0x007f0000);
4615         I915_WRITE(CSIEW1, 0x1e220004);
4616         I915_WRITE(CSIEW2, 0x04000004);
4617
4618         for (i = 0; i < 5; i++)
4619                 I915_WRITE(PEW + (i * 4), 0);
4620         for (i = 0; i < 3; i++)
4621                 I915_WRITE(DEW + (i * 4), 0);
4622
4623         /* Program P-state weights to account for frequency power adjustment */
4624         for (i = 0; i < 16; i++) {
4625                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4626                 unsigned long freq = intel_pxfreq(pxvidfreq);
4627                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4628                         PXVFREQ_PX_SHIFT;
4629                 unsigned long val;
4630
4631                 val = vid * vid;
4632                 val *= (freq / 1000);
4633                 val *= 255;
4634                 val /= (127*127*900);
4635                 if (val > 0xff)
4636                         DRM_ERROR("bad pxval: %ld\n", val);
4637                 pxw[i] = val;
4638         }
4639         /* Render standby states get 0 weight */
4640         pxw[14] = 0;
4641         pxw[15] = 0;
4642
4643         for (i = 0; i < 4; i++) {
4644                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4645                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4646                 I915_WRITE(PXW + (i * 4), val);
4647         }
4648
4649         /* Adjust magic regs to magic values (more experimental results) */
4650         I915_WRITE(OGW0, 0);
4651         I915_WRITE(OGW1, 0);
4652         I915_WRITE(EG0, 0x00007f00);
4653         I915_WRITE(EG1, 0x0000000e);
4654         I915_WRITE(EG2, 0x000e0000);
4655         I915_WRITE(EG3, 0x68000300);
4656         I915_WRITE(EG4, 0x42000000);
4657         I915_WRITE(EG5, 0x00140031);
4658         I915_WRITE(EG6, 0);
4659         I915_WRITE(EG7, 0);
4660
4661         for (i = 0; i < 8; i++)
4662                 I915_WRITE(PXWL + (i * 4), 0);
4663
4664         /* Enable PMON + select events */
4665         I915_WRITE(ECR, 0x80000019);
4666
4667         lcfuse = I915_READ(LCFUSE02);
4668
4669         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4670 }
4671
4672 void intel_init_gt_powersave(struct drm_device *dev)
4673 {
4674         i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
4675
4676         if (IS_VALLEYVIEW(dev))
4677                 valleyview_init_gt_powersave(dev);
4678 }
4679
4680 void intel_cleanup_gt_powersave(struct drm_device *dev)
4681 {
4682         if (IS_VALLEYVIEW(dev))
4683                 valleyview_cleanup_gt_powersave(dev);
4684 }
4685
4686 void intel_disable_gt_powersave(struct drm_device *dev)
4687 {
4688         struct drm_i915_private *dev_priv = dev->dev_private;
4689
4690         /* Interrupts should be disabled already to avoid re-arming. */
4691         WARN_ON(dev->irq_enabled);
4692
4693         if (IS_IRONLAKE_M(dev)) {
4694                 ironlake_disable_drps(dev);
4695                 ironlake_disable_rc6(dev);
4696         } else if (IS_GEN6(dev) || IS_GEN7(dev) || IS_BROADWELL(dev)) {
4697                 if (cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work))
4698                         intel_runtime_pm_put(dev_priv);
4699
4700                 cancel_work_sync(&dev_priv->rps.work);
4701                 mutex_lock(&dev_priv->rps.hw_lock);
4702                 if (IS_VALLEYVIEW(dev))
4703                         valleyview_disable_rps(dev);
4704                 else
4705                         gen6_disable_rps(dev);
4706                 dev_priv->rps.enabled = false;
4707                 mutex_unlock(&dev_priv->rps.hw_lock);
4708         }
4709 }
4710
4711 static void intel_gen6_powersave_work(struct work_struct *work)
4712 {
4713         struct drm_i915_private *dev_priv =
4714                 container_of(work, struct drm_i915_private,
4715                              rps.delayed_resume_work.work);
4716         struct drm_device *dev = dev_priv->dev;
4717
4718         mutex_lock(&dev_priv->rps.hw_lock);
4719
4720         if (IS_VALLEYVIEW(dev)) {
4721                 valleyview_enable_rps(dev);
4722         } else if (IS_BROADWELL(dev)) {
4723                 gen8_enable_rps(dev);
4724                 __gen6_update_ring_freq(dev);
4725         } else {
4726                 gen6_enable_rps(dev);
4727                 __gen6_update_ring_freq(dev);
4728         }
4729         dev_priv->rps.enabled = true;
4730         mutex_unlock(&dev_priv->rps.hw_lock);
4731
4732         intel_runtime_pm_put(dev_priv);
4733 }
4734
4735 void intel_enable_gt_powersave(struct drm_device *dev)
4736 {
4737         struct drm_i915_private *dev_priv = dev->dev_private;
4738
4739         if (IS_IRONLAKE_M(dev)) {
4740                 mutex_lock(&dev->struct_mutex);
4741                 ironlake_enable_drps(dev);
4742                 ironlake_enable_rc6(dev);
4743                 intel_init_emon(dev);
4744                 mutex_unlock(&dev->struct_mutex);
4745         } else if (IS_GEN6(dev) || IS_GEN7(dev) || IS_BROADWELL(dev)) {
4746                 /*
4747                  * PCU communication is slow and this doesn't need to be
4748                  * done at any specific time, so do this out of our fast path
4749                  * to make resume and init faster.
4750                  *
4751                  * We depend on the HW RC6 power context save/restore
4752                  * mechanism when entering D3 through runtime PM suspend. So
4753                  * disable RPM until RPS/RC6 is properly setup. We can only
4754                  * get here via the driver load/system resume/runtime resume
4755                  * paths, so the _noresume version is enough (and in case of
4756                  * runtime resume it's necessary).
4757                  */
4758                 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4759                                            round_jiffies_up_relative(HZ)))
4760                         intel_runtime_pm_get_noresume(dev_priv);
4761         }
4762 }
4763
4764 void intel_reset_gt_powersave(struct drm_device *dev)
4765 {
4766         struct drm_i915_private *dev_priv = dev->dev_private;
4767
4768         dev_priv->rps.enabled = false;
4769         intel_enable_gt_powersave(dev);
4770 }
4771
4772 static void ibx_init_clock_gating(struct drm_device *dev)
4773 {
4774         struct drm_i915_private *dev_priv = dev->dev_private;
4775
4776         /*
4777          * On Ibex Peak and Cougar Point, we need to disable clock
4778          * gating for the panel power sequencer or it will fail to
4779          * start up when no ports are active.
4780          */
4781         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4782 }
4783
4784 static void g4x_disable_trickle_feed(struct drm_device *dev)
4785 {
4786         struct drm_i915_private *dev_priv = dev->dev_private;
4787         int pipe;
4788
4789         for_each_pipe(pipe) {
4790                 I915_WRITE(DSPCNTR(pipe),
4791                            I915_READ(DSPCNTR(pipe)) |
4792                            DISPPLANE_TRICKLE_FEED_DISABLE);
4793                 intel_flush_primary_plane(dev_priv, pipe);
4794         }
4795 }
4796
4797 static void ilk_init_lp_watermarks(struct drm_device *dev)
4798 {
4799         struct drm_i915_private *dev_priv = dev->dev_private;
4800
4801         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
4802         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
4803         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
4804
4805         /*
4806          * Don't touch WM1S_LP_EN here.
4807          * Doing so could cause underruns.
4808          */
4809 }
4810
4811 static void ironlake_init_clock_gating(struct drm_device *dev)
4812 {
4813         struct drm_i915_private *dev_priv = dev->dev_private;
4814         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4815
4816         /*
4817          * Required for FBC
4818          * WaFbcDisableDpfcClockGating:ilk
4819          */
4820         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4821                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4822                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
4823
4824         I915_WRITE(PCH_3DCGDIS0,
4825                    MARIUNIT_CLOCK_GATE_DISABLE |
4826                    SVSMUNIT_CLOCK_GATE_DISABLE);
4827         I915_WRITE(PCH_3DCGDIS1,
4828                    VFMUNIT_CLOCK_GATE_DISABLE);
4829
4830         /*
4831          * According to the spec the following bits should be set in
4832          * order to enable memory self-refresh
4833          * The bit 22/21 of 0x42004
4834          * The bit 5 of 0x42020
4835          * The bit 15 of 0x45000
4836          */
4837         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4838                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
4839                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4840         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
4841         I915_WRITE(DISP_ARB_CTL,
4842                    (I915_READ(DISP_ARB_CTL) |
4843                     DISP_FBC_WM_DIS));
4844
4845         ilk_init_lp_watermarks(dev);
4846
4847         /*
4848          * Based on the document from hardware guys the following bits
4849          * should be set unconditionally in order to enable FBC.
4850          * The bit 22 of 0x42000
4851          * The bit 22 of 0x42004
4852          * The bit 7,8,9 of 0x42020.
4853          */
4854         if (IS_IRONLAKE_M(dev)) {
4855                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
4856                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4857                            I915_READ(ILK_DISPLAY_CHICKEN1) |
4858                            ILK_FBCQ_DIS);
4859                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4860                            I915_READ(ILK_DISPLAY_CHICKEN2) |
4861                            ILK_DPARB_GATE);
4862         }
4863
4864         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4865
4866         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4867                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4868                    ILK_ELPIN_409_SELECT);
4869         I915_WRITE(_3D_CHICKEN2,
4870                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4871                    _3D_CHICKEN2_WM_READ_PIPELINED);
4872
4873         /* WaDisableRenderCachePipelinedFlush:ilk */
4874         I915_WRITE(CACHE_MODE_0,
4875                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4876
4877         /* WaDisable_RenderCache_OperationalFlush:ilk */
4878         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
4879
4880         g4x_disable_trickle_feed(dev);
4881
4882         ibx_init_clock_gating(dev);
4883 }
4884
4885 static void cpt_init_clock_gating(struct drm_device *dev)
4886 {
4887         struct drm_i915_private *dev_priv = dev->dev_private;
4888         int pipe;
4889         uint32_t val;
4890
4891         /*
4892          * On Ibex Peak and Cougar Point, we need to disable clock
4893          * gating for the panel power sequencer or it will fail to
4894          * start up when no ports are active.
4895          */
4896         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
4897                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
4898                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
4899         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4900                    DPLS_EDP_PPS_FIX_DIS);
4901         /* The below fixes the weird display corruption, a few pixels shifted
4902          * downward, on (only) LVDS of some HP laptops with IVY.
4903          */
4904         for_each_pipe(pipe) {
4905                 val = I915_READ(TRANS_CHICKEN2(pipe));
4906                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4907                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4908                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
4909                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4910                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4911                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4912                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
4913                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4914         }
4915         /* WADP0ClockGatingDisable */
4916         for_each_pipe(pipe) {
4917                 I915_WRITE(TRANS_CHICKEN1(pipe),
4918                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4919         }
4920 }
4921
4922 static void gen6_check_mch_setup(struct drm_device *dev)
4923 {
4924         struct drm_i915_private *dev_priv = dev->dev_private;
4925         uint32_t tmp;
4926
4927         tmp = I915_READ(MCH_SSKPD);
4928         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4929                 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4930                 DRM_INFO("This can cause pipe underruns and display issues.\n");
4931                 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4932         }
4933 }
4934
4935 static void gen6_init_clock_gating(struct drm_device *dev)
4936 {
4937         struct drm_i915_private *dev_priv = dev->dev_private;
4938         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4939
4940         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4941
4942         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4943                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4944                    ILK_ELPIN_409_SELECT);
4945
4946         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4947         I915_WRITE(_3D_CHICKEN,
4948                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4949
4950         /* WaSetupGtModeTdRowDispatch:snb */
4951         if (IS_SNB_GT1(dev))
4952                 I915_WRITE(GEN6_GT_MODE,
4953                            _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4954
4955         /* WaDisable_RenderCache_OperationalFlush:snb */
4956         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
4957
4958         /*
4959          * BSpec recoomends 8x4 when MSAA is used,
4960          * however in practice 16x4 seems fastest.
4961          *
4962          * Note that PS/WM thread counts depend on the WIZ hashing
4963          * disable bit, which we don't touch here, but it's good
4964          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
4965          */
4966         I915_WRITE(GEN6_GT_MODE,
4967                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
4968
4969         ilk_init_lp_watermarks(dev);
4970
4971         I915_WRITE(CACHE_MODE_0,
4972                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
4973
4974         I915_WRITE(GEN6_UCGCTL1,
4975                    I915_READ(GEN6_UCGCTL1) |
4976                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4977                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4978
4979         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4980          * gating disable must be set.  Failure to set it results in
4981          * flickering pixels due to Z write ordering failures after
4982          * some amount of runtime in the Mesa "fire" demo, and Unigine
4983          * Sanctuary and Tropics, and apparently anything else with
4984          * alpha test or pixel discard.
4985          *
4986          * According to the spec, bit 11 (RCCUNIT) must also be set,
4987          * but we didn't debug actual testcases to find it out.
4988          *
4989          * WaDisableRCCUnitClockGating:snb
4990          * WaDisableRCPBUnitClockGating:snb
4991          */
4992         I915_WRITE(GEN6_UCGCTL2,
4993                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4994                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4995
4996         /* WaStripsFansDisableFastClipPerformanceFix:snb */
4997         I915_WRITE(_3D_CHICKEN3,
4998                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
4999
5000         /*
5001          * Bspec says:
5002          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
5003          * 3DSTATE_SF number of SF output attributes is more than 16."
5004          */
5005         I915_WRITE(_3D_CHICKEN3,
5006                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
5007
5008         /*
5009          * According to the spec the following bits should be
5010          * set in order to enable memory self-refresh and fbc:
5011          * The bit21 and bit22 of 0x42000
5012          * The bit21 and bit22 of 0x42004
5013          * The bit5 and bit7 of 0x42020
5014          * The bit14 of 0x70180
5015          * The bit14 of 0x71180
5016          *
5017          * WaFbcAsynchFlipDisableFbcQueue:snb
5018          */
5019         I915_WRITE(ILK_DISPLAY_CHICKEN1,
5020                    I915_READ(ILK_DISPLAY_CHICKEN1) |
5021                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5022         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5023                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5024                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
5025         I915_WRITE(ILK_DSPCLK_GATE_D,
5026                    I915_READ(ILK_DSPCLK_GATE_D) |
5027                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
5028                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
5029
5030         g4x_disable_trickle_feed(dev);
5031
5032         cpt_init_clock_gating(dev);
5033
5034         gen6_check_mch_setup(dev);
5035 }
5036
5037 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5038 {
5039         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5040
5041         /*
5042          * WaVSThreadDispatchOverride:ivb,vlv
5043          *
5044          * This actually overrides the dispatch
5045          * mode for all thread types.
5046          */
5047         reg &= ~GEN7_FF_SCHED_MASK;
5048         reg |= GEN7_FF_TS_SCHED_HW;
5049         reg |= GEN7_FF_VS_SCHED_HW;
5050         reg |= GEN7_FF_DS_SCHED_HW;
5051
5052         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5053 }
5054
5055 static void lpt_init_clock_gating(struct drm_device *dev)
5056 {
5057         struct drm_i915_private *dev_priv = dev->dev_private;
5058
5059         /*
5060          * TODO: this bit should only be enabled when really needed, then
5061          * disabled when not needed anymore in order to save power.
5062          */
5063         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5064                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5065                            I915_READ(SOUTH_DSPCLK_GATE_D) |
5066                            PCH_LP_PARTITION_LEVEL_DISABLE);
5067
5068         /* WADPOClockGatingDisable:hsw */
5069         I915_WRITE(_TRANSA_CHICKEN1,
5070                    I915_READ(_TRANSA_CHICKEN1) |
5071                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5072 }
5073
5074 static void lpt_suspend_hw(struct drm_device *dev)
5075 {
5076         struct drm_i915_private *dev_priv = dev->dev_private;
5077
5078         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5079                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5080
5081                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5082                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5083         }
5084 }
5085
5086 static void gen8_init_clock_gating(struct drm_device *dev)
5087 {
5088         struct drm_i915_private *dev_priv = dev->dev_private;
5089         enum i915_pipe pipe;
5090
5091         I915_WRITE(WM3_LP_ILK, 0);
5092         I915_WRITE(WM2_LP_ILK, 0);
5093         I915_WRITE(WM1_LP_ILK, 0);
5094
5095         /* FIXME(BDW): Check all the w/a, some might only apply to
5096          * pre-production hw. */
5097
5098         /* WaDisablePartialInstShootdown:bdw */
5099         I915_WRITE(GEN8_ROW_CHICKEN,
5100                    _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
5101
5102         /* WaDisableThreadStallDopClockGating:bdw */
5103         /* FIXME: Unclear whether we really need this on production bdw. */
5104         I915_WRITE(GEN8_ROW_CHICKEN,
5105                    _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
5106
5107         /*
5108          * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
5109          * pre-production hardware
5110          */
5111         I915_WRITE(HALF_SLICE_CHICKEN3,
5112                    _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS));
5113         I915_WRITE(HALF_SLICE_CHICKEN3,
5114                    _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
5115         I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5116
5117         I915_WRITE(_3D_CHICKEN3,
5118                    _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
5119
5120         I915_WRITE(COMMON_SLICE_CHICKEN2,
5121                    _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE));
5122
5123         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5124                    _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
5125
5126         /* WaDisableDopClockGating:bdw May not be needed for production */
5127         I915_WRITE(GEN7_ROW_CHICKEN2,
5128                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5129
5130         /* WaSwitchSolVfFArbitrationPriority:bdw */
5131         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5132
5133         /* WaPsrDPAMaskVBlankInSRD:bdw */
5134         I915_WRITE(CHICKEN_PAR1_1,
5135                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
5136
5137         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
5138         for_each_pipe(pipe) {
5139                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
5140                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
5141                            BDW_DPRS_MASK_VBLANK_SRD);
5142         }
5143
5144         /* Use Force Non-Coherent whenever executing a 3D context. This is a
5145          * workaround for for a possible hang in the unlikely event a TLB
5146          * invalidation occurs during a PSD flush.
5147          */
5148         I915_WRITE(HDC_CHICKEN0,
5149                    I915_READ(HDC_CHICKEN0) |
5150                    _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
5151
5152         /* WaVSRefCountFullforceMissDisable:bdw */
5153         /* WaDSRefCountFullforceMissDisable:bdw */
5154         I915_WRITE(GEN7_FF_THREAD_MODE,
5155                    I915_READ(GEN7_FF_THREAD_MODE) &
5156                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5157
5158         /*
5159          * BSpec recommends 8x4 when MSAA is used,
5160          * however in practice 16x4 seems fastest.
5161          *
5162          * Note that PS/WM thread counts depend on the WIZ hashing
5163          * disable bit, which we don't touch here, but it's good
5164          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5165          */
5166         I915_WRITE(GEN7_GT_MODE,
5167                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5168
5169         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5170                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
5171
5172         /* WaDisableSDEUnitClockGating:bdw */
5173         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5174                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5175
5176         /* Wa4x4STCOptimizationDisable:bdw */
5177         I915_WRITE(CACHE_MODE_1,
5178                    _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
5179 }
5180
5181 static void haswell_init_clock_gating(struct drm_device *dev)
5182 {
5183         struct drm_i915_private *dev_priv = dev->dev_private;
5184
5185         ilk_init_lp_watermarks(dev);
5186
5187         /* L3 caching of data atomics doesn't work -- disable it. */
5188         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5189         I915_WRITE(HSW_ROW_CHICKEN3,
5190                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5191
5192         /* This is required by WaCatErrorRejectionIssue:hsw */
5193         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5194                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5195                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5196
5197         /* WaVSRefCountFullforceMissDisable:hsw */
5198         I915_WRITE(GEN7_FF_THREAD_MODE,
5199                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
5200
5201         /* WaDisable_RenderCache_OperationalFlush:hsw */
5202         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5203
5204         /* enable HiZ Raw Stall Optimization */
5205         I915_WRITE(CACHE_MODE_0_GEN7,
5206                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5207
5208         /* WaDisable4x2SubspanOptimization:hsw */
5209         I915_WRITE(CACHE_MODE_1,
5210                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5211
5212         /*
5213          * BSpec recommends 8x4 when MSAA is used,
5214          * however in practice 16x4 seems fastest.
5215          *
5216          * Note that PS/WM thread counts depend on the WIZ hashing
5217          * disable bit, which we don't touch here, but it's good
5218          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5219          */
5220         I915_WRITE(GEN7_GT_MODE,
5221                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5222
5223         /* WaSwitchSolVfFArbitrationPriority:hsw */
5224         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5225
5226         /* WaRsPkgCStateDisplayPMReq:hsw */
5227         I915_WRITE(CHICKEN_PAR1_1,
5228                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
5229
5230         lpt_init_clock_gating(dev);
5231 }
5232
5233 static void ivybridge_init_clock_gating(struct drm_device *dev)
5234 {
5235         struct drm_i915_private *dev_priv = dev->dev_private;
5236         uint32_t snpcr;
5237
5238         ilk_init_lp_watermarks(dev);
5239
5240         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
5241
5242         /* WaDisableEarlyCull:ivb */
5243         I915_WRITE(_3D_CHICKEN3,
5244                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5245
5246         /* WaDisableBackToBackFlipFix:ivb */
5247         I915_WRITE(IVB_CHICKEN3,
5248                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5249                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
5250
5251         /* WaDisablePSDDualDispatchEnable:ivb */
5252         if (IS_IVB_GT1(dev))
5253                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5254                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5255
5256         /* WaDisable_RenderCache_OperationalFlush:ivb */
5257         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5258
5259         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5260         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5261                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5262
5263         /* WaApplyL3ControlAndL3ChickenMode:ivb */
5264         I915_WRITE(GEN7_L3CNTLREG1,
5265                         GEN7_WA_FOR_GEN7_L3_CONTROL);
5266         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5267                    GEN7_WA_L3_CHICKEN_MODE);
5268         if (IS_IVB_GT1(dev))
5269                 I915_WRITE(GEN7_ROW_CHICKEN2,
5270                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5271         else {
5272                 /* must write both registers */
5273                 I915_WRITE(GEN7_ROW_CHICKEN2,
5274                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5275                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5276                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5277         }
5278
5279         /* WaForceL3Serialization:ivb */
5280         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5281                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5282
5283         /*
5284          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5285          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5286          */
5287         I915_WRITE(GEN6_UCGCTL2,
5288                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5289
5290         /* This is required by WaCatErrorRejectionIssue:ivb */
5291         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5292                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5293                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5294
5295         g4x_disable_trickle_feed(dev);
5296
5297         gen7_setup_fixed_func_scheduler(dev_priv);
5298
5299         if (0) { /* causes HiZ corruption on ivb:gt1 */
5300                 /* enable HiZ Raw Stall Optimization */
5301                 I915_WRITE(CACHE_MODE_0_GEN7,
5302                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
5303         }
5304
5305         /* WaDisable4x2SubspanOptimization:ivb */
5306         I915_WRITE(CACHE_MODE_1,
5307                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5308
5309         /*
5310          * BSpec recommends 8x4 when MSAA is used,
5311          * however in practice 16x4 seems fastest.
5312          *
5313          * Note that PS/WM thread counts depend on the WIZ hashing
5314          * disable bit, which we don't touch here, but it's good
5315          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5316          */
5317         I915_WRITE(GEN7_GT_MODE,
5318                    GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
5319
5320         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5321         snpcr &= ~GEN6_MBC_SNPCR_MASK;
5322         snpcr |= GEN6_MBC_SNPCR_MED;
5323         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5324
5325         if (!HAS_PCH_NOP(dev))
5326                 cpt_init_clock_gating(dev);
5327
5328         gen6_check_mch_setup(dev);
5329 }
5330
5331 static void valleyview_init_clock_gating(struct drm_device *dev)
5332 {
5333         struct drm_i915_private *dev_priv = dev->dev_private;
5334         u32 val;
5335
5336         mutex_lock(&dev_priv->rps.hw_lock);
5337         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5338         mutex_unlock(&dev_priv->rps.hw_lock);
5339         switch ((val >> 6) & 3) {
5340         case 0:
5341         case 1:
5342                 dev_priv->mem_freq = 800;
5343                 break;
5344         case 2:
5345                 dev_priv->mem_freq = 1066;
5346                 break;
5347         case 3:
5348                 dev_priv->mem_freq = 1333;
5349                 break;
5350         }
5351         DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
5352
5353         dev_priv->vlv_cdclk_freq = valleyview_cur_cdclk(dev_priv);
5354         DRM_DEBUG_DRIVER("Current CD clock rate: %d MHz",
5355                          dev_priv->vlv_cdclk_freq);
5356
5357         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5358
5359         /* WaDisableEarlyCull:vlv */
5360         I915_WRITE(_3D_CHICKEN3,
5361                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5362
5363         /* WaDisableBackToBackFlipFix:vlv */
5364         I915_WRITE(IVB_CHICKEN3,
5365                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5366                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
5367
5368         /* WaPsdDispatchEnable:vlv */
5369         /* WaDisablePSDDualDispatchEnable:vlv */
5370         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5371                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5372                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5373
5374         /* WaDisable_RenderCache_OperationalFlush:vlv */
5375         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5376
5377         /* WaForceL3Serialization:vlv */
5378         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5379                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5380
5381         /* WaDisableDopClockGating:vlv */
5382         I915_WRITE(GEN7_ROW_CHICKEN2,
5383                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5384
5385         /* This is required by WaCatErrorRejectionIssue:vlv */
5386         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5387                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5388                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5389
5390         gen7_setup_fixed_func_scheduler(dev_priv);
5391
5392         /*
5393          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5394          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5395          */
5396         I915_WRITE(GEN6_UCGCTL2,
5397                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5398
5399         /* WaDisableL3Bank2xClockGate:vlv
5400          * Disabling L3 clock gating- MMIO 940c[25] = 1
5401          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
5402         I915_WRITE(GEN7_UCGCTL4,
5403                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5404
5405         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5406
5407         /*
5408          * BSpec says this must be set, even though
5409          * WaDisable4x2SubspanOptimization isn't listed for VLV.
5410          */
5411         I915_WRITE(CACHE_MODE_1,
5412                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5413
5414         /*
5415          * WaIncreaseL3CreditsForVLVB0:vlv
5416          * This is the hardware default actually.
5417          */
5418         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
5419
5420         /*
5421          * WaDisableVLVClockGating_VBIIssue:vlv
5422          * Disable clock gating on th GCFG unit to prevent a delay
5423          * in the reporting of vblank events.
5424          */
5425         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
5426 }
5427
5428 static void cherryview_init_clock_gating(struct drm_device *dev)
5429 {
5430         struct drm_i915_private *dev_priv = dev->dev_private;
5431
5432         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5433
5434         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5435
5436         /* WaDisablePartialInstShootdown:chv */
5437         I915_WRITE(GEN8_ROW_CHICKEN,
5438                    _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
5439
5440         /* WaDisableThreadStallDopClockGating:chv */
5441         I915_WRITE(GEN8_ROW_CHICKEN,
5442                    _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
5443
5444         /* WaVSRefCountFullforceMissDisable:chv */
5445         /* WaDSRefCountFullforceMissDisable:chv */
5446         I915_WRITE(GEN7_FF_THREAD_MODE,
5447                    I915_READ(GEN7_FF_THREAD_MODE) &
5448                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
5449
5450         /* WaDisableSemaphoreAndSyncFlipWait:chv */
5451         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5452                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
5453
5454         /* WaDisableCSUnitClockGating:chv */
5455         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5456                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5457
5458         /* WaDisableSDEUnitClockGating:chv */
5459         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
5460                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5461
5462         /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
5463         I915_WRITE(HALF_SLICE_CHICKEN3,
5464                    _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
5465
5466         /* WaDisableGunitClockGating:chv (pre-production hw) */
5467         I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) |
5468                    GINT_DIS);
5469
5470         /* WaDisableFfDopClockGating:chv (pre-production hw) */
5471         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
5472                    _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE));
5473
5474         /* WaDisableDopClockGating:chv (pre-production hw) */
5475         I915_WRITE(GEN7_ROW_CHICKEN2,
5476                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5477         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
5478                    GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
5479 }
5480
5481 static void g4x_init_clock_gating(struct drm_device *dev)
5482 {
5483         struct drm_i915_private *dev_priv = dev->dev_private;
5484         uint32_t dspclk_gate;
5485
5486         I915_WRITE(RENCLK_GATE_D1, 0);
5487         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5488                    GS_UNIT_CLOCK_GATE_DISABLE |
5489                    CL_UNIT_CLOCK_GATE_DISABLE);
5490         I915_WRITE(RAMCLK_GATE_D, 0);
5491         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5492                 OVRUNIT_CLOCK_GATE_DISABLE |
5493                 OVCUNIT_CLOCK_GATE_DISABLE;
5494         if (IS_GM45(dev))
5495                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5496         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5497
5498         /* WaDisableRenderCachePipelinedFlush */
5499         I915_WRITE(CACHE_MODE_0,
5500                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5501
5502         /* WaDisable_RenderCache_OperationalFlush:g4x */
5503         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5504
5505         g4x_disable_trickle_feed(dev);
5506 }
5507
5508 static void crestline_init_clock_gating(struct drm_device *dev)
5509 {
5510         struct drm_i915_private *dev_priv = dev->dev_private;
5511
5512         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5513         I915_WRITE(RENCLK_GATE_D2, 0);
5514         I915_WRITE(DSPCLK_GATE_D, 0);
5515         I915_WRITE(RAMCLK_GATE_D, 0);
5516         I915_WRITE16(DEUC, 0);
5517         I915_WRITE(MI_ARB_STATE,
5518                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5519
5520         /* WaDisable_RenderCache_OperationalFlush:gen4 */
5521         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5522 }
5523
5524 static void broadwater_init_clock_gating(struct drm_device *dev)
5525 {
5526         struct drm_i915_private *dev_priv = dev->dev_private;
5527
5528         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5529                    I965_RCC_CLOCK_GATE_DISABLE |
5530                    I965_RCPB_CLOCK_GATE_DISABLE |
5531                    I965_ISC_CLOCK_GATE_DISABLE |
5532                    I965_FBC_CLOCK_GATE_DISABLE);
5533         I915_WRITE(RENCLK_GATE_D2, 0);
5534         I915_WRITE(MI_ARB_STATE,
5535                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5536
5537         /* WaDisable_RenderCache_OperationalFlush:gen4 */
5538         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5539 }
5540
5541 static void gen3_init_clock_gating(struct drm_device *dev)
5542 {
5543         struct drm_i915_private *dev_priv = dev->dev_private;
5544         u32 dstate = I915_READ(D_STATE);
5545
5546         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5547                 DSTATE_DOT_CLOCK_GATING;
5548         I915_WRITE(D_STATE, dstate);
5549
5550         if (IS_PINEVIEW(dev))
5551                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
5552
5553         /* IIR "flip pending" means done if this bit is set */
5554         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
5555
5556         /* interrupts should cause a wake up from C3 */
5557         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
5558
5559         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
5560         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
5561 }
5562
5563 static void i85x_init_clock_gating(struct drm_device *dev)
5564 {
5565         struct drm_i915_private *dev_priv = dev->dev_private;
5566
5567         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5568
5569         /* interrupts should cause a wake up from C3 */
5570         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
5571                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
5572 }
5573
5574 static void i830_init_clock_gating(struct drm_device *dev)
5575 {
5576         struct drm_i915_private *dev_priv = dev->dev_private;
5577
5578         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5579 }
5580
5581 void intel_init_clock_gating(struct drm_device *dev)
5582 {
5583         struct drm_i915_private *dev_priv = dev->dev_private;
5584
5585         dev_priv->display.init_clock_gating(dev);
5586 }
5587
5588 void intel_suspend_hw(struct drm_device *dev)
5589 {
5590         if (HAS_PCH_LPT(dev))
5591                 lpt_suspend_hw(dev);
5592 }
5593
5594 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
5595         for (i = 0;                                                     \
5596              i < (power_domains)->power_well_count &&                   \
5597                  ((power_well) = &(power_domains)->power_wells[i]);     \
5598              i++)                                                       \
5599                 if ((power_well)->domains & (domain_mask))
5600
5601 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5602         for (i = (power_domains)->power_well_count - 1;                  \
5603              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5604              i--)                                                        \
5605                 if ((power_well)->domains & (domain_mask))
5606
5607 /**
5608  * We should only use the power well if we explicitly asked the hardware to
5609  * enable it, so check if it's enabled and also check if we've requested it to
5610  * be enabled.
5611  */
5612 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
5613                                    struct i915_power_well *power_well)
5614 {
5615         return I915_READ(HSW_PWR_WELL_DRIVER) ==
5616                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5617 }
5618
5619 bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv,
5620                                           enum intel_display_power_domain domain)
5621 {
5622         struct i915_power_domains *power_domains;
5623         struct i915_power_well *power_well;
5624         bool is_enabled;
5625         int i;
5626
5627         if (dev_priv->pm.suspended)
5628                 return false;
5629
5630         power_domains = &dev_priv->power_domains;
5631
5632         is_enabled = true;
5633
5634         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5635                 if (power_well->always_on)
5636                         continue;
5637
5638                 if (!power_well->hw_enabled) {
5639                         is_enabled = false;
5640                         break;
5641                 }
5642         }
5643
5644         return is_enabled;
5645 }
5646
5647 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
5648                                  enum intel_display_power_domain domain)
5649 {
5650         struct i915_power_domains *power_domains;
5651         bool ret;
5652
5653         power_domains = &dev_priv->power_domains;
5654
5655         mutex_lock(&power_domains->lock);
5656         ret = intel_display_power_enabled_unlocked(dev_priv, domain);
5657         mutex_unlock(&power_domains->lock);
5658
5659         return ret;
5660 }
5661
5662 /*
5663  * Starting with Haswell, we have a "Power Down Well" that can be turned off
5664  * when not needed anymore. We have 4 registers that can request the power well
5665  * to be enabled, and it will only be disabled if none of the registers is
5666  * requesting it to be enabled.
5667  */
5668 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
5669 {
5670         struct drm_device *dev = dev_priv->dev;
5671
5672         /*
5673          * After we re-enable the power well, if we touch VGA register 0x3d5
5674          * we'll get unclaimed register interrupts. This stops after we write
5675          * anything to the VGA MSR register. The vgacon module uses this
5676          * register all the time, so if we unbind our driver and, as a
5677          * consequence, bind vgacon, we'll get stuck in an infinite loop at
5678          * console_unlock(). So make here we touch the VGA MSR register, making
5679          * sure vgacon can keep working normally without triggering interrupts
5680          * and error messages.
5681          */
5682 #if 0
5683         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
5684         outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
5685         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
5686 #else
5687         outb(VGA_MSR_WRITE, inb(VGA_MSR_READ));
5688 #endif
5689
5690         if (IS_BROADWELL(dev)) {
5691                 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
5692                 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5693                            dev_priv->de_irq_mask[PIPE_B]);
5694                 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5695                            ~dev_priv->de_irq_mask[PIPE_B] |
5696                            GEN8_PIPE_VBLANK);
5697                 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5698                            dev_priv->de_irq_mask[PIPE_C]);
5699                 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5700                            ~dev_priv->de_irq_mask[PIPE_C] |
5701                            GEN8_PIPE_VBLANK);
5702                 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5703                 lockmgr(&dev_priv->irq_lock, LK_RELEASE);
5704         }
5705 }
5706
5707 static void reset_vblank_counter(struct drm_device *dev, enum i915_pipe pipe)
5708 {
5709         assert_spin_locked(&dev->vbl_lock);
5710
5711         dev->vblank[pipe].last = 0;
5712 }
5713
5714 static void hsw_power_well_post_disable(struct drm_i915_private *dev_priv)
5715 {
5716         struct drm_device *dev = dev_priv->dev;
5717         enum i915_pipe pipe;
5718
5719         /*
5720          * After this, the registers on the pipes that are part of the power
5721          * well will become zero, so we have to adjust our counters according to
5722          * that.
5723          *
5724          * FIXME: Should we do this in general in drm_vblank_post_modeset?
5725          */
5726         lockmgr(&dev->vbl_lock, LK_EXCLUSIVE);
5727         for_each_pipe(pipe)
5728                 if (pipe != PIPE_A)
5729                         reset_vblank_counter(dev, pipe);
5730         lockmgr(&dev->vbl_lock, LK_RELEASE);
5731 }
5732
5733 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
5734                                struct i915_power_well *power_well, bool enable)
5735 {
5736         bool is_enabled, enable_requested;
5737         uint32_t tmp;
5738
5739         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5740         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5741         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
5742
5743         if (enable) {
5744                 if (!enable_requested)
5745                         I915_WRITE(HSW_PWR_WELL_DRIVER,
5746                                    HSW_PWR_WELL_ENABLE_REQUEST);
5747
5748                 if (!is_enabled) {
5749                         DRM_DEBUG_KMS("Enabling power well\n");
5750                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5751                                       HSW_PWR_WELL_STATE_ENABLED), 20))
5752                                 DRM_ERROR("Timeout enabling power well\n");
5753                 }
5754
5755                 hsw_power_well_post_enable(dev_priv);
5756         } else {
5757                 if (enable_requested) {
5758                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5759                         POSTING_READ(HSW_PWR_WELL_DRIVER);
5760                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
5761
5762                         hsw_power_well_post_disable(dev_priv);
5763                 }
5764         }
5765 }
5766
5767 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
5768                                    struct i915_power_well *power_well)
5769 {
5770         hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
5771
5772         /*
5773          * We're taking over the BIOS, so clear any requests made by it since
5774          * the driver is in charge now.
5775          */
5776         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5777                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5778 }
5779
5780 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
5781                                   struct i915_power_well *power_well)
5782 {
5783         hsw_set_power_well(dev_priv, power_well, true);
5784 }
5785
5786 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
5787                                    struct i915_power_well *power_well)
5788 {
5789         hsw_set_power_well(dev_priv, power_well, false);
5790 }
5791
5792 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
5793                                            struct i915_power_well *power_well)
5794 {
5795 }
5796
5797 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
5798                                              struct i915_power_well *power_well)
5799 {
5800         return true;
5801 }
5802
5803 void __vlv_set_power_well(struct drm_i915_private *dev_priv,
5804                           enum punit_power_well power_well_id, bool enable)
5805 {
5806         struct drm_device *dev = dev_priv->dev;
5807         u32 mask;
5808         u32 state;
5809         u32 ctrl;
5810         enum i915_pipe pipe;
5811
5812         if (power_well_id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
5813                 if (enable) {
5814                         /*
5815                          * Enable the CRI clock source so we can get at the
5816                          * display and the reference clock for VGA
5817                          * hotplug / manual detection.
5818                          */
5819                         I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
5820                                    DPLL_REFA_CLK_ENABLE_VLV |
5821                                    DPLL_INTEGRATED_CRI_CLK_VLV);
5822                         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
5823                 } else {
5824                         for_each_pipe(pipe)
5825                                 assert_pll_disabled(dev_priv, pipe);
5826                         /* Assert common reset */
5827                         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) &
5828                                    ~DPIO_CMNRST);
5829                 }
5830         }
5831
5832         mask = PUNIT_PWRGT_MASK(power_well_id);
5833         state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
5834                          PUNIT_PWRGT_PWR_GATE(power_well_id);
5835
5836         mutex_lock(&dev_priv->rps.hw_lock);
5837
5838 #define COND \
5839         ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
5840
5841         if (COND)
5842                 goto out;
5843
5844         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
5845         ctrl &= ~mask;
5846         ctrl |= state;
5847         vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
5848
5849         if (wait_for(COND, 100))
5850                 DRM_ERROR("timout setting power well state %08x (%08x)\n",
5851                           state,
5852                           vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
5853
5854 #undef COND
5855
5856 out:
5857         mutex_unlock(&dev_priv->rps.hw_lock);
5858
5859         /*
5860          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
5861          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
5862          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
5863          *   b. The other bits such as sfr settings / modesel may all
5864          *      be set to 0.
5865          *
5866          * This should only be done on init and resume from S3 with
5867          * both PLLs disabled, or we risk losing DPIO and PLL
5868          * synchronization.
5869          */
5870         if (power_well_id == PUNIT_POWER_WELL_DPIO_CMN_BC && enable)
5871                 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
5872 }
5873
5874 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
5875                                struct i915_power_well *power_well, bool enable)
5876 {
5877         enum punit_power_well power_well_id = power_well->data;
5878
5879         __vlv_set_power_well(dev_priv, power_well_id, enable);
5880 }
5881
5882 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
5883                                    struct i915_power_well *power_well)
5884 {
5885         vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
5886 }
5887
5888 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
5889                                   struct i915_power_well *power_well)
5890 {
5891         vlv_set_power_well(dev_priv, power_well, true);
5892 }
5893
5894 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
5895                                    struct i915_power_well *power_well)
5896 {
5897         vlv_set_power_well(dev_priv, power_well, false);
5898 }
5899
5900 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
5901                                    struct i915_power_well *power_well)
5902 {
5903         int power_well_id = power_well->data;
5904         bool enabled = false;
5905         u32 mask;
5906         u32 state;
5907         u32 ctrl;
5908
5909         mask = PUNIT_PWRGT_MASK(power_well_id);
5910         ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
5911
5912         mutex_lock(&dev_priv->rps.hw_lock);
5913
5914         state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
5915         /*
5916          * We only ever set the power-on and power-gate states, anything
5917          * else is unexpected.
5918          */
5919         WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
5920                 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
5921         if (state == ctrl)
5922                 enabled = true;
5923
5924         /*
5925          * A transient state at this point would mean some unexpected party
5926          * is poking at the power controls too.
5927          */
5928         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
5929         WARN_ON(ctrl != state);
5930
5931         mutex_unlock(&dev_priv->rps.hw_lock);
5932
5933         return enabled;
5934 }
5935
5936 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
5937                                           struct i915_power_well *power_well)
5938 {
5939         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
5940
5941         vlv_set_power_well(dev_priv, power_well, true);
5942
5943         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
5944         valleyview_enable_display_irqs(dev_priv);
5945         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
5946
5947         /*
5948          * During driver initialization/resume we can avoid restoring the
5949          * part of the HW/SW state that will be inited anyway explicitly.
5950          */
5951         if (dev_priv->power_domains.initializing)
5952                 return;
5953
5954         intel_hpd_init(dev_priv->dev);
5955
5956         i915_redisable_vga_power_on(dev_priv->dev);
5957 }
5958
5959 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
5960                                            struct i915_power_well *power_well)
5961 {
5962         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
5963
5964         lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE);
5965         valleyview_disable_display_irqs(dev_priv);
5966         lockmgr(&dev_priv->irq_lock, LK_RELEASE);
5967
5968         vlv_set_power_well(dev_priv, power_well, false);
5969 }
5970
5971 static void check_power_well_state(struct drm_i915_private *dev_priv,
5972                                    struct i915_power_well *power_well)
5973 {
5974         bool enabled = power_well->ops->is_enabled(dev_priv, power_well);
5975
5976         if (power_well->always_on || !i915.disable_power_well) {
5977                 if (!enabled)
5978                         goto mismatch;
5979
5980                 return;
5981         }
5982
5983         if (enabled != (power_well->count > 0))
5984                 goto mismatch;
5985
5986         return;
5987
5988 mismatch:
5989         WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
5990                   power_well->name, power_well->always_on, enabled,
5991                   power_well->count, i915.disable_power_well);
5992 }
5993
5994 void intel_display_power_get(struct drm_i915_private *dev_priv,
5995                              enum intel_display_power_domain domain)
5996 {
5997         struct i915_power_domains *power_domains;
5998         struct i915_power_well *power_well;
5999         int i;
6000
6001         intel_runtime_pm_get(dev_priv);
6002
6003         power_domains = &dev_priv->power_domains;
6004
6005         mutex_lock(&power_domains->lock);
6006
6007         for_each_power_well(i, power_well, BIT(domain), power_domains) {
6008                 if (!power_well->count++) {
6009                         DRM_DEBUG_KMS("enabling %s\n", power_well->name);
6010                         power_well->ops->enable(dev_priv, power_well);
6011                         power_well->hw_enabled = true;
6012                 }
6013
6014                 check_power_well_state(dev_priv, power_well);
6015         }
6016
6017         power_domains->domain_use_count[domain]++;
6018
6019         mutex_unlock(&power_domains->lock);
6020 }
6021
6022 void intel_display_power_put(struct drm_i915_private *dev_priv,
6023                              enum intel_display_power_domain domain)
6024 {
6025         struct i915_power_domains *power_domains;
6026         struct i915_power_well *power_well;
6027         int i;
6028
6029         power_domains = &dev_priv->power_domains;
6030
6031         mutex_lock(&power_domains->lock);
6032
6033         WARN_ON(!power_domains->domain_use_count[domain]);
6034         power_domains->domain_use_count[domain]--;
6035
6036         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
6037                 WARN_ON(!power_well->count);
6038
6039                 if (!--power_well->count && i915.disable_power_well) {
6040                         DRM_DEBUG_KMS("disabling %s\n", power_well->name);
6041                         power_well->hw_enabled = false;
6042                         power_well->ops->disable(dev_priv, power_well);
6043                 }
6044
6045                 check_power_well_state(dev_priv, power_well);
6046         }
6047
6048         mutex_unlock(&power_domains->lock);
6049
6050         intel_runtime_pm_put(dev_priv);
6051 }
6052
6053 static struct i915_power_domains *hsw_pwr;
6054
6055 /* Display audio driver power well request */
6056 int i915_request_power_well(void)
6057 {
6058         struct drm_i915_private *dev_priv;
6059
6060         if (!hsw_pwr)
6061                 return -ENODEV;
6062
6063         dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6064                                 power_domains);
6065         intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
6066         return 0;
6067 }
6068
6069 /* Display audio driver power well release */
6070 int i915_release_power_well(void)
6071 {
6072         struct drm_i915_private *dev_priv;
6073
6074         if (!hsw_pwr)
6075                 return -ENODEV;
6076
6077         dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6078                                 power_domains);
6079         intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
6080         return 0;
6081 }
6082
6083 /*
6084  * Private interface for the audio driver to get CDCLK in kHz.
6085  *
6086  * Caller must request power well using i915_request_power_well() prior to
6087  * making the call.
6088  */
6089 int i915_get_cdclk_freq(void)
6090 {
6091         struct drm_i915_private *dev_priv;
6092
6093         if (!hsw_pwr)
6094                 return -ENODEV;
6095
6096         dev_priv = container_of(hsw_pwr, struct drm_i915_private,
6097                                 power_domains);
6098
6099         return intel_ddi_get_cdclk_freq(dev_priv);
6100 }
6101 EXPORT_SYMBOL_GPL(i915_get_cdclk_freq);
6102
6103
6104 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
6105
6106 #define HSW_ALWAYS_ON_POWER_DOMAINS (                   \
6107         BIT(POWER_DOMAIN_PIPE_A) |                      \
6108         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
6109         BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) |          \
6110         BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) |          \
6111         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |          \
6112         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |          \
6113         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |          \
6114         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |          \
6115         BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) |          \
6116         BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) |          \
6117         BIT(POWER_DOMAIN_PORT_CRT) |                    \
6118         BIT(POWER_DOMAIN_INIT))
6119 #define HSW_DISPLAY_POWER_DOMAINS (                             \
6120         (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) |    \
6121         BIT(POWER_DOMAIN_INIT))
6122
6123 #define BDW_ALWAYS_ON_POWER_DOMAINS (                   \
6124         HSW_ALWAYS_ON_POWER_DOMAINS |                   \
6125         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
6126 #define BDW_DISPLAY_POWER_DOMAINS (                             \
6127         (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) |    \
6128         BIT(POWER_DOMAIN_INIT))
6129
6130 #define VLV_ALWAYS_ON_POWER_DOMAINS     BIT(POWER_DOMAIN_INIT)
6131 #define VLV_DISPLAY_POWER_DOMAINS       POWER_DOMAIN_MASK
6132
6133 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (         \
6134         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
6135         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
6136         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
6137         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
6138         BIT(POWER_DOMAIN_PORT_CRT) |            \
6139         BIT(POWER_DOMAIN_INIT))
6140
6141 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (  \
6142         BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) |  \
6143         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
6144         BIT(POWER_DOMAIN_INIT))
6145
6146 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (  \
6147         BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) |  \
6148         BIT(POWER_DOMAIN_INIT))
6149
6150 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (  \
6151         BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) |  \
6152         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
6153         BIT(POWER_DOMAIN_INIT))
6154
6155 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (  \
6156         BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) |  \
6157         BIT(POWER_DOMAIN_INIT))
6158
6159 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
6160         .sync_hw = i9xx_always_on_power_well_noop,
6161         .enable = i9xx_always_on_power_well_noop,
6162         .disable = i9xx_always_on_power_well_noop,
6163         .is_enabled = i9xx_always_on_power_well_enabled,
6164 };
6165
6166 static struct i915_power_well i9xx_always_on_power_well[] = {
6167         {
6168                 .name = "always-on",
6169                 .always_on = 1,
6170                 .domains = POWER_DOMAIN_MASK,
6171                 .ops = &i9xx_always_on_power_well_ops,
6172         },
6173 };
6174
6175 static const struct i915_power_well_ops hsw_power_well_ops = {
6176         .sync_hw = hsw_power_well_sync_hw,
6177         .enable = hsw_power_well_enable,
6178         .disable = hsw_power_well_disable,
6179         .is_enabled = hsw_power_well_enabled,
6180 };
6181
6182 static struct i915_power_well hsw_power_wells[] = {
6183         {
6184                 .name = "always-on",
6185                 .always_on = 1,
6186                 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
6187                 .ops = &i9xx_always_on_power_well_ops,
6188         },
6189         {
6190                 .name = "display",
6191                 .domains = HSW_DISPLAY_POWER_DOMAINS,
6192                 .ops = &hsw_power_well_ops,
6193         },
6194 };
6195
6196 static struct i915_power_well bdw_power_wells[] = {
6197         {
6198                 .name = "always-on",
6199                 .always_on = 1,
6200                 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
6201                 .ops = &i9xx_always_on_power_well_ops,
6202         },
6203         {
6204                 .name = "display",
6205                 .domains = BDW_DISPLAY_POWER_DOMAINS,
6206                 .ops = &hsw_power_well_ops,
6207         },
6208 };
6209
6210 static const struct i915_power_well_ops vlv_display_power_well_ops = {
6211         .sync_hw = vlv_power_well_sync_hw,
6212         .enable = vlv_display_power_well_enable,
6213         .disable = vlv_display_power_well_disable,
6214         .is_enabled = vlv_power_well_enabled,
6215 };
6216
6217 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
6218         .sync_hw = vlv_power_well_sync_hw,
6219         .enable = vlv_power_well_enable,
6220         .disable = vlv_power_well_disable,
6221         .is_enabled = vlv_power_well_enabled,
6222 };
6223
6224 static struct i915_power_well vlv_power_wells[] = {
6225         {
6226                 .name = "always-on",
6227                 .always_on = 1,
6228                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
6229                 .ops = &i9xx_always_on_power_well_ops,
6230         },
6231         {
6232                 .name = "display",
6233                 .domains = VLV_DISPLAY_POWER_DOMAINS,
6234                 .data = PUNIT_POWER_WELL_DISP2D,
6235                 .ops = &vlv_display_power_well_ops,
6236         },
6237         {
6238                 .name = "dpio-tx-b-01",
6239                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6240                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6241                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6242                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6243                 .ops = &vlv_dpio_power_well_ops,
6244                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
6245         },
6246         {
6247                 .name = "dpio-tx-b-23",
6248                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6249                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6250                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6251                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6252                 .ops = &vlv_dpio_power_well_ops,
6253                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
6254         },
6255         {
6256                 .name = "dpio-tx-c-01",
6257                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6258                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6259                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6260                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6261                 .ops = &vlv_dpio_power_well_ops,
6262                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
6263         },
6264         {
6265                 .name = "dpio-tx-c-23",
6266                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
6267                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
6268                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
6269                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
6270                 .ops = &vlv_dpio_power_well_ops,
6271                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
6272         },
6273         {
6274                 .name = "dpio-common",
6275                 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
6276                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
6277                 .ops = &vlv_dpio_power_well_ops,
6278         },
6279 };
6280
6281 #define set_power_wells(power_domains, __power_wells) ({                \
6282         (power_domains)->power_wells = (__power_wells);                 \
6283         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
6284 })
6285
6286 int intel_power_domains_init(struct drm_i915_private *dev_priv)
6287 {
6288         struct i915_power_domains *power_domains = &dev_priv->power_domains;
6289
6290         lockinit(&power_domains->lock, "i915pl", 0, LK_CANRECURSE);
6291
6292         /*
6293          * The enabling order will be from lower to higher indexed wells,
6294          * the disabling order is reversed.
6295          */
6296         if (IS_HASWELL(dev_priv->dev)) {
6297                 set_power_wells(power_domains, hsw_power_wells);
6298                 hsw_pwr = power_domains;
6299         } else if (IS_BROADWELL(dev_priv->dev)) {
6300                 set_power_wells(power_domains, bdw_power_wells);
6301                 hsw_pwr = power_domains;
6302         } else if (IS_VALLEYVIEW(dev_priv->dev)) {
6303                 set_power_wells(power_domains, vlv_power_wells);
6304         } else {
6305                 set_power_wells(power_domains, i9xx_always_on_power_well);
6306         }
6307
6308         return 0;
6309 }
6310
6311 void intel_power_domains_remove(struct drm_i915_private *dev_priv)
6312 {
6313         hsw_pwr = NULL;
6314 }
6315
6316 static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
6317 {
6318         struct i915_power_domains *power_domains = &dev_priv->power_domains;
6319         struct i915_power_well *power_well;
6320         int i;
6321
6322         mutex_lock(&power_domains->lock);
6323         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
6324                 power_well->ops->sync_hw(dev_priv, power_well);
6325                 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
6326                                                                      power_well);
6327         }
6328         mutex_unlock(&power_domains->lock);
6329 }
6330
6331 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv)
6332 {
6333         struct i915_power_domains *power_domains = &dev_priv->power_domains;
6334
6335         power_domains->initializing = true;
6336         /* For now, we need the power well to be always enabled. */
6337         intel_display_set_init_power(dev_priv, true);
6338         intel_power_domains_resume(dev_priv);
6339         power_domains->initializing = false;
6340 }
6341
6342 void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
6343 {
6344         intel_runtime_pm_get(dev_priv);
6345 }
6346
6347 void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
6348 {
6349         intel_runtime_pm_put(dev_priv);
6350 }
6351
6352 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
6353 {
6354 #if 0
6355         struct drm_device *dev = dev_priv->dev;
6356         struct device *device = &dev->pdev->dev;
6357
6358         if (!HAS_RUNTIME_PM(dev))
6359                 return;
6360
6361         pm_runtime_get_sync(device);
6362         WARN(dev_priv->pm.suspended, "Device still suspended.\n");
6363 #endif
6364 }
6365
6366 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
6367 {
6368         struct drm_device *dev = dev_priv->dev;
6369 #if 0
6370         struct device *device = &dev->pdev->dev;
6371 #endif
6372
6373         if (!HAS_RUNTIME_PM(dev))
6374                 return;
6375
6376         WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
6377 #if 0
6378         pm_runtime_get_noresume(device);
6379 #endif
6380 }
6381
6382 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
6383 {
6384 #if 0
6385         struct drm_device *dev = dev_priv->dev;
6386         struct device *device = &dev->pdev->dev;
6387
6388         if (!HAS_RUNTIME_PM(dev))
6389                 return;
6390
6391         pm_runtime_mark_last_busy(device);
6392         pm_runtime_put_autosuspend(device);
6393 #endif
6394 }
6395
6396 void intel_init_runtime_pm(struct drm_i915_private *dev_priv)
6397 {
6398         struct drm_device *dev = dev_priv->dev;
6399 #if 0
6400         struct device *device = &dev->pdev->dev;
6401 #endif
6402
6403         if (!HAS_RUNTIME_PM(dev))
6404                 return;
6405
6406 #if 0
6407         pm_runtime_set_active(device);
6408
6409         /*
6410          * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6411          * requirement.
6412          */
6413         if (!intel_enable_rc6(dev)) {
6414                 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6415                 return;
6416         }
6417
6418         pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
6419         pm_runtime_mark_last_busy(device);
6420         pm_runtime_use_autosuspend(device);
6421
6422         pm_runtime_put_autosuspend(device);
6423 #endif
6424 }
6425
6426 void intel_fini_runtime_pm(struct drm_i915_private *dev_priv)
6427 {
6428 #if 0
6429         struct drm_device *dev = dev_priv->dev;
6430         struct device *device = &dev->pdev->dev;
6431
6432         if (!HAS_RUNTIME_PM(dev))
6433                 return;
6434
6435         if (!intel_enable_rc6(dev))
6436                 return;
6437
6438         /* Make sure we're not suspended first. */
6439         pm_runtime_get_sync(device);
6440         pm_runtime_disable(device);
6441 #endif
6442 }
6443
6444 /* Set up chip specific power management-related functions */
6445 void intel_init_pm(struct drm_device *dev)
6446 {
6447         struct drm_i915_private *dev_priv = dev->dev_private;
6448
6449         if (HAS_FBC(dev)) {
6450                 if (INTEL_INFO(dev)->gen >= 7) {
6451                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6452                         dev_priv->display.enable_fbc = gen7_enable_fbc;
6453                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
6454                 } else if (INTEL_INFO(dev)->gen >= 5) {
6455                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6456                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
6457                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
6458                 } else if (IS_GM45(dev)) {
6459                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6460                         dev_priv->display.enable_fbc = g4x_enable_fbc;
6461                         dev_priv->display.disable_fbc = g4x_disable_fbc;
6462                 } else {
6463                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6464                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
6465                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
6466
6467                         /* This value was pulled out of someone's hat */
6468                         I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
6469                 }
6470         }
6471
6472         /* For cxsr */
6473         if (IS_PINEVIEW(dev))
6474                 i915_pineview_get_mem_freq(dev);
6475         else if (IS_GEN5(dev))
6476                 i915_ironlake_get_mem_freq(dev);
6477
6478         /* For FIFO watermark updates */
6479         if (HAS_PCH_SPLIT(dev)) {
6480                 ilk_setup_wm_latency(dev);
6481
6482                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6483                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6484                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6485                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6486                         dev_priv->display.update_wm = ilk_update_wm;
6487                         dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6488                 } else {
6489                         DRM_DEBUG_KMS("Failed to read display plane latency. "
6490                                       "Disable CxSR\n");
6491                 }
6492
6493                 if (IS_GEN5(dev))
6494                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
6495                 else if (IS_GEN6(dev))
6496                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
6497                 else if (IS_IVYBRIDGE(dev))
6498                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6499                 else if (IS_HASWELL(dev))
6500                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
6501                 else if (INTEL_INFO(dev)->gen == 8)
6502                         dev_priv->display.init_clock_gating = gen8_init_clock_gating;
6503         } else if (IS_CHERRYVIEW(dev)) {
6504                 dev_priv->display.update_wm = valleyview_update_wm;
6505                 dev_priv->display.init_clock_gating =
6506                         cherryview_init_clock_gating;
6507         } else if (IS_VALLEYVIEW(dev)) {
6508                 dev_priv->display.update_wm = valleyview_update_wm;
6509                 dev_priv->display.init_clock_gating =
6510                         valleyview_init_clock_gating;
6511         } else if (IS_PINEVIEW(dev)) {
6512                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6513                                             dev_priv->is_ddr3,
6514                                             dev_priv->fsb_freq,
6515                                             dev_priv->mem_freq)) {
6516                         DRM_INFO("failed to find known CxSR latency "
6517                                  "(found ddr%s fsb freq %d, mem freq %d), "
6518                                  "disabling CxSR\n",
6519                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
6520                                  dev_priv->fsb_freq, dev_priv->mem_freq);
6521                         /* Disable CxSR and never update its watermark again */
6522                         pineview_disable_cxsr(dev);
6523                         dev_priv->display.update_wm = NULL;
6524                 } else
6525                         dev_priv->display.update_wm = pineview_update_wm;
6526                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6527         } else if (IS_G4X(dev)) {
6528                 dev_priv->display.update_wm = g4x_update_wm;
6529                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6530         } else if (IS_GEN4(dev)) {
6531                 dev_priv->display.update_wm = i965_update_wm;
6532                 if (IS_CRESTLINE(dev))
6533                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6534                 else if (IS_BROADWATER(dev))
6535                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6536         } else if (IS_GEN3(dev)) {
6537                 dev_priv->display.update_wm = i9xx_update_wm;
6538                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6539                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6540         } else if (IS_GEN2(dev)) {
6541                 if (INTEL_INFO(dev)->num_pipes == 1) {
6542                         dev_priv->display.update_wm = i845_update_wm;
6543                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
6544                 } else {
6545                         dev_priv->display.update_wm = i9xx_update_wm;
6546                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
6547                 }
6548
6549                 if (IS_I85X(dev) || IS_I865G(dev))
6550                         dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6551                 else
6552                         dev_priv->display.init_clock_gating = i830_init_clock_gating;
6553         } else {
6554                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
6555         }
6556 }
6557
6558 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
6559 {
6560         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6561
6562         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6563                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6564                 return -EAGAIN;
6565         }
6566
6567         I915_WRITE(GEN6_PCODE_DATA, *val);
6568         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6569
6570         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6571                      500)) {
6572                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6573                 return -ETIMEDOUT;
6574         }
6575
6576         *val = I915_READ(GEN6_PCODE_DATA);
6577         I915_WRITE(GEN6_PCODE_DATA, 0);
6578
6579         return 0;
6580 }
6581
6582 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
6583 {
6584         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6585
6586         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6587                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6588                 return -EAGAIN;
6589         }
6590
6591         I915_WRITE(GEN6_PCODE_DATA, val);
6592         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6593
6594         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6595                      500)) {
6596                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6597                 return -ETIMEDOUT;
6598         }
6599
6600         I915_WRITE(GEN6_PCODE_DATA, 0);
6601
6602         return 0;
6603 }
6604
6605 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
6606 {
6607         int div;
6608
6609         /* 4 x czclk */
6610         switch (dev_priv->mem_freq) {
6611         case 800:
6612                 div = 10;
6613                 break;
6614         case 1066:
6615                 div = 12;
6616                 break;
6617         case 1333:
6618                 div = 16;
6619                 break;
6620         default:
6621                 return -1;
6622         }
6623
6624         return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
6625 }
6626
6627 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
6628 {
6629         int mul;
6630
6631         /* 4 x czclk */
6632         switch (dev_priv->mem_freq) {
6633         case 800:
6634                 mul = 10;
6635                 break;
6636         case 1066:
6637                 mul = 12;
6638                 break;
6639         case 1333:
6640                 mul = 16;
6641                 break;
6642         default:
6643                 return -1;
6644         }
6645
6646         return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
6647 }
6648
6649 void intel_pm_setup(struct drm_device *dev)
6650 {
6651         struct drm_i915_private *dev_priv = dev->dev_private;
6652
6653         lockinit(&dev_priv->rps.hw_lock, "i915 rps.hw_lock", 0, LK_CANRECURSE);
6654
6655         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6656                           intel_gen6_powersave_work);
6657
6658         dev_priv->pm.suspended = false;
6659         dev_priv->pm.irqs_disabled = false;
6660 }