1 @c Copyright 1996-2013 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
8 @chapter ARM Dependent Features
12 @node Machine Dependencies
13 @chapter ARM Dependent Features
19 * ARM Options:: Options
21 * ARM Floating Point:: Floating Point
22 * ARM Directives:: ARM Machine Directives
23 * ARM Opcodes:: Opcodes
24 * ARM Mapping Symbols:: Mapping Symbols
25 * ARM Unwinding Tutorial:: Unwinding
30 @cindex ARM options (none)
31 @cindex options for ARM (none)
35 @cindex @code{-mcpu=} command line option, ARM
36 @item -mcpu=@var{processor}[+@var{extension}@dots{}]
37 This option specifies the target processor. The assembler will issue an
38 error message if an attempt is made to assemble an instruction which
39 will not execute on the target processor. The following processor names are
84 @code{fa526} (Faraday FA526 processor),
85 @code{fa626} (Faraday FA626 processor),
104 @code{fa606te} (Faraday FA606TE processor),
105 @code{fa616te} (Faraday FA616TE processor),
106 @code{fa626te} (Faraday FA626TE processor),
107 @code{fmp626} (Faraday FMP626 processor),
108 @code{fa726te} (Faraday FA726TE processor),
130 @code{cortex-m0plus},
131 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
132 @code{i80200} (Intel XScale processor)
133 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
136 The special name @code{all} may be used to allow the
137 assembler to accept instructions valid for any ARM processor.
139 In addition to the basic instruction set, the assembler can be told to
140 accept various extension mnemonics that extend the processor using the
141 co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
142 is equivalent to specifying @code{-mcpu=ep9312}.
144 Multiple extensions may be specified, separated by a @code{+}. The
145 extensions should be specified in ascending alphabetical order.
147 Some extensions may be restricted to particular architectures; this is
148 documented in the list of extensions below.
150 Extension mnemonics may also be removed from those the assembler accepts.
151 This is done be prepending @code{no} to the option that adds the extension.
152 Extensions that are removed should be listed after all extensions which have
153 been added, again in ascending alphabetical order. For example,
154 @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
157 The following extensions are currently supported:
158 @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
159 @code{fp} (Floating Point Extensions for v8-A architecture),
160 @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
164 @code{mp} (Multiprocessing Extensions for v7-A and v7-R architectures),
165 @code{os} (Operating System for v6M architecture),
166 @code{sec} (Security Extensions for v6K and v7-A architectures),
167 @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
168 @code{virt} (Virtualization Extensions for v7-A architecture, implies
173 @cindex @code{-march=} command line option, ARM
174 @item -march=@var{architecture}[+@var{extension}@dots{}]
175 This option specifies the target architecture. The assembler will issue
176 an error message if an attempt is made to assemble an instruction which
177 will not execute on the target architecture. The following architecture
178 names are recognized:
211 If both @code{-mcpu} and
212 @code{-march} are specified, the assembler will use
213 the setting for @code{-mcpu}.
215 The architecture option can be extended with the same instruction set
216 extension options as the @code{-mcpu} option.
218 @cindex @code{-mfpu=} command line option, ARM
219 @item -mfpu=@var{floating-point-format}
221 This option specifies the floating point format to assemble for. The
222 assembler will issue an error message if an attempt is made to assemble
223 an instruction which will not execute on the target floating point unit.
224 The following format options are recognized:
244 @code{vfpv3-d16-fp16},
257 @code{neon-fp-armv8},
259 @code{crypto-neon-fp-armv8}.
261 In addition to determining which instructions are assembled, this option
262 also affects the way in which the @code{.double} assembler directive behaves
263 when assembling little-endian code.
265 The default is dependent on the processor selected. For Architecture 5 or
266 later, the default is to assembler for VFP instructions; for earlier
267 architectures the default is to assemble for FPA instructions.
269 @cindex @code{-mthumb} command line option, ARM
271 This option specifies that the assembler should start assembling Thumb
272 instructions; that is, it should behave as though the file starts with a
273 @code{.code 16} directive.
275 @cindex @code{-mthumb-interwork} command line option, ARM
276 @item -mthumb-interwork
277 This option specifies that the output generated by the assembler should
278 be marked as supporting interworking.
280 @cindex @code{-mimplicit-it} command line option, ARM
281 @item -mimplicit-it=never
282 @itemx -mimplicit-it=always
283 @itemx -mimplicit-it=arm
284 @itemx -mimplicit-it=thumb
285 The @code{-mimplicit-it} option controls the behavior of the assembler when
286 conditional instructions are not enclosed in IT blocks.
287 There are four possible behaviors.
288 If @code{never} is specified, such constructs cause a warning in ARM
289 code and an error in Thumb-2 code.
290 If @code{always} is specified, such constructs are accepted in both
291 ARM and Thumb-2 code, where the IT instruction is added implicitly.
292 If @code{arm} is specified, such constructs are accepted in ARM code
293 and cause an error in Thumb-2 code.
294 If @code{thumb} is specified, such constructs cause a warning in ARM
295 code and are accepted in Thumb-2 code. If you omit this option, the
296 behavior is equivalent to @code{-mimplicit-it=arm}.
298 @cindex @code{-mapcs-26} command line option, ARM
299 @cindex @code{-mapcs-32} command line option, ARM
302 These options specify that the output generated by the assembler should
303 be marked as supporting the indicated version of the Arm Procedure.
306 @cindex @code{-matpcs} command line option, ARM
308 This option specifies that the output generated by the assembler should
309 be marked as supporting the Arm/Thumb Procedure Calling Standard. If
310 enabled this option will cause the assembler to create an empty
311 debugging section in the object file called .arm.atpcs. Debuggers can
312 use this to determine the ABI being used by.
314 @cindex @code{-mapcs-float} command line option, ARM
316 This indicates the floating point variant of the APCS should be
317 used. In this variant floating point arguments are passed in FP
318 registers rather than integer registers.
320 @cindex @code{-mapcs-reentrant} command line option, ARM
321 @item -mapcs-reentrant
322 This indicates that the reentrant variant of the APCS should be used.
323 This variant supports position independent code.
325 @cindex @code{-mfloat-abi=} command line option, ARM
326 @item -mfloat-abi=@var{abi}
327 This option specifies that the output generated by the assembler should be
328 marked as using specified floating point ABI.
329 The following values are recognized:
335 @cindex @code{-eabi=} command line option, ARM
336 @item -meabi=@var{ver}
337 This option specifies which EABI version the produced object files should
339 The following values are recognized:
345 @cindex @code{-EB} command line option, ARM
347 This option specifies that the output generated by the assembler should
348 be marked as being encoded for a big-endian processor.
350 @cindex @code{-EL} command line option, ARM
352 This option specifies that the output generated by the assembler should
353 be marked as being encoded for a little-endian processor.
355 @cindex @code{-k} command line option, ARM
356 @cindex PIC code generation for ARM
358 This option specifies that the output of the assembler should be marked
359 as position-independent code (PIC).
361 @cindex @code{--fix-v4bx} command line option, ARM
363 Allow @code{BX} instructions in ARMv4 code. This is intended for use with
364 the linker option of the same name.
366 @cindex @code{-mwarn-deprecated} command line option, ARM
367 @item -mwarn-deprecated
368 @itemx -mno-warn-deprecated
369 Enable or disable warnings about using deprecated options or
370 features. The default is to warn.
378 * ARM-Instruction-Set:: Instruction Set
379 * ARM-Chars:: Special Characters
380 * ARM-Regs:: Register Names
381 * ARM-Relocations:: Relocations
382 * ARM-Neon-Alignment:: NEON Alignment Specifiers
385 @node ARM-Instruction-Set
386 @subsection Instruction Set Syntax
387 Two slightly different syntaxes are support for ARM and THUMB
388 instructions. The default, @code{divided}, uses the old style where
389 ARM and THUMB instructions had their own, separate syntaxes. The new,
390 @code{unified} syntax, which can be selected via the @code{.syntax}
391 directive, and has the following main features:
395 Immediate operands do not require a @code{#} prefix.
398 The @code{IT} instruction may appear, and if it does it is validated
399 against subsequent conditional affixes. In ARM mode it does not
400 generate machine code, in THUMB mode it does.
403 For ARM instructions the conditional affixes always appear at the end
404 of the instruction. For THUMB instructions conditional affixes can be
405 used, but only inside the scope of an @code{IT} instruction.
408 All of the instructions new to the V6T2 architecture (and later) are
409 available. (Only a few such instructions can be written in the
410 @code{divided} syntax).
413 The @code{.N} and @code{.W} suffixes are recognized and honored.
416 All instructions set the flags if and only if they have an @code{s}
421 @subsection Special Characters
423 @cindex line comment character, ARM
424 @cindex ARM line comment character
425 The presence of a @samp{@@} anywhere on a line indicates the start of
426 a comment that extends to the end of that line.
428 If a @samp{#} appears as the first character of a line then the whole
429 line is treated as a comment, but in this case the line could also be
430 a logical line number directive (@pxref{Comments}) or a preprocessor
431 control command (@pxref{Preprocessing}).
433 @cindex line separator, ARM
434 @cindex statement separator, ARM
435 @cindex ARM line separator
436 The @samp{;} character can be used instead of a newline to separate
439 @cindex immediate character, ARM
440 @cindex ARM immediate character
441 Either @samp{#} or @samp{$} can be used to indicate immediate operands.
443 @cindex identifiers, ARM
444 @cindex ARM identifiers
445 *TODO* Explain about /data modifier on symbols.
448 @subsection Register Names
450 @cindex ARM register names
451 @cindex register names, ARM
452 *TODO* Explain about ARM register naming, and the predefined names.
454 @node ARM-Relocations
455 @subsection ARM relocation generation
457 @cindex data relocations, ARM
458 @cindex ARM data relocations
459 Specific data relocations can be generated by putting the relocation name
460 in parentheses after the symbol name. For example:
466 This will generate an @samp{R_ARM_TARGET1} relocation against the symbol
468 The following relocations are supported:
484 For compatibility with older toolchains the assembler also accepts
485 @code{(PLT)} after branch targets. On legacy targets this will
486 generate the deprecated @samp{R_ARM_PLT32} relocation. On EABI
487 targets it will encode either the @samp{R_ARM_CALL} or
488 @samp{R_ARM_JUMP24} relocation, as appropriate.
490 @cindex MOVW and MOVT relocations, ARM
491 Relocations for @samp{MOVW} and @samp{MOVT} instructions can be generated
492 by prefixing the value with @samp{#:lower16:} and @samp{#:upper16}
493 respectively. For example to load the 32-bit address of foo into r0:
496 MOVW r0, #:lower16:foo
497 MOVT r0, #:upper16:foo
500 @node ARM-Neon-Alignment
501 @subsection NEON Alignment Specifiers
503 @cindex alignment for NEON instructions
504 Some NEON load/store instructions allow an optional address
506 The ARM documentation specifies that this is indicated by
507 @samp{@@ @var{align}}. However GAS already interprets
508 the @samp{@@} character as a "line comment" start,
509 so @samp{: @var{align}} is used instead. For example:
512 vld1.8 @{q0@}, [r0, :128]
515 @node ARM Floating Point
516 @section Floating Point
518 @cindex floating point, ARM (@sc{ieee})
519 @cindex ARM floating point (@sc{ieee})
520 The ARM family uses @sc{ieee} floating-point numbers.
523 @section ARM Machine Directives
525 @cindex machine directives, ARM
526 @cindex ARM machine directives
529 @c AAAAAAAAAAAAAAAAAAAAAAAAA
531 @cindex @code{.2byte} directive, ARM
532 @cindex @code{.4byte} directive, ARM
533 @cindex @code{.8byte} directive, ARM
534 @item .2byte @var{expression} [, @var{expression}]*
535 @itemx .4byte @var{expression} [, @var{expression}]*
536 @itemx .8byte @var{expression} [, @var{expression}]*
537 These directives write 2, 4 or 8 byte values to the output section.
539 @cindex @code{.align} directive, ARM
540 @item .align @var{expression} [, @var{expression}]
541 This is the generic @var{.align} directive. For the ARM however if the
542 first argument is zero (ie no alignment is needed) the assembler will
543 behave as if the argument had been 2 (ie pad to the next four byte
544 boundary). This is for compatibility with ARM's own assembler.
546 @cindex @code{.arch} directive, ARM
547 @item .arch @var{name}
548 Select the target architecture. Valid values for @var{name} are the same as
549 for the @option{-march} commandline option.
551 Specifying @code{.arch} clears any previously selected architecture
554 @cindex @code{.arch_extension} directive, ARM
555 @item .arch_extension @var{name}
556 Add or remove an architecture extension to the target architecture. Valid
557 values for @var{name} are the same as those accepted as architectural
558 extensions by the @option{-mcpu} commandline option.
560 @code{.arch_extension} may be used multiple times to add or remove extensions
561 incrementally to the architecture being compiled for.
563 @cindex @code{.arm} directive, ARM
565 This performs the same action as @var{.code 32}.
568 @cindex @code{.pad} directive, ARM
569 @item .pad #@var{count}
570 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
571 A positive value indicates the function prologue allocated stack space by
572 decrementing the stack pointer.
574 @c BBBBBBBBBBBBBBBBBBBBBBBBBB
576 @cindex @code{.bss} directive, ARM
578 This directive switches to the @code{.bss} section.
580 @c CCCCCCCCCCCCCCCCCCCCCCCCCC
582 @cindex @code{.cantunwind} directive, ARM
584 Prevents unwinding through the current function. No personality routine
585 or exception table data is required or permitted.
587 @cindex @code{.code} directive, ARM
588 @item .code @code{[16|32]}
589 This directive selects the instruction set being generated. The value 16
590 selects Thumb, with the value 32 selecting ARM.
592 @cindex @code{.cpu} directive, ARM
593 @item .cpu @var{name}
594 Select the target processor. Valid values for @var{name} are the same as
595 for the @option{-mcpu} commandline option.
597 Specifying @code{.cpu} clears any previously selected architecture
600 @c DDDDDDDDDDDDDDDDDDDDDDDDDD
602 @cindex @code{.dn} and @code{.qn} directives, ARM
603 @item @var{name} .dn @var{register name} [@var{.type}] [[@var{index}]]
604 @itemx @var{name} .qn @var{register name} [@var{.type}] [[@var{index}]]
606 The @code{dn} and @code{qn} directives are used to create typed
607 and/or indexed register aliases for use in Advanced SIMD Extension
608 (Neon) instructions. The former should be used to create aliases
609 of double-precision registers, and the latter to create aliases of
610 quad-precision registers.
612 If these directives are used to create typed aliases, those aliases can
613 be used in Neon instructions instead of writing types after the mnemonic
614 or after each operand. For example:
623 This is equivalent to writing the following:
629 Aliases created using @code{dn} or @code{qn} can be destroyed using
632 @c EEEEEEEEEEEEEEEEEEEEEEEEEE
634 @cindex @code{.eabi_attribute} directive, ARM
635 @item .eabi_attribute @var{tag}, @var{value}
636 Set the EABI object attribute @var{tag} to @var{value}.
638 The @var{tag} is either an attribute number, or one of the following:
639 @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch},
640 @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use},
641 @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch},
642 @code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config},
643 @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data},
644 @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use},
645 @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding},
646 @code{Tag_ABI_FP_denormal}, @code{Tag_ABI_FP_exceptions},
647 @code{Tag_ABI_FP_user_exceptions}, @code{Tag_ABI_FP_number_model},
648 @code{Tag_ABI_align_needed}, @code{Tag_ABI_align_preserved},
649 @code{Tag_ABI_enum_size}, @code{Tag_ABI_HardFP_use},
650 @code{Tag_ABI_VFP_args}, @code{Tag_ABI_WMMX_args},
651 @code{Tag_ABI_optimization_goals}, @code{Tag_ABI_FP_optimization_goals},
652 @code{Tag_compatibility}, @code{Tag_CPU_unaligned_access},
653 @code{Tag_FP_HP_extension}, @code{Tag_ABI_FP_16bit_format},
654 @code{Tag_MPextension_use}, @code{Tag_DIV_use},
655 @code{Tag_nodefaults}, @code{Tag_also_compatible_with},
656 @code{Tag_conformance}, @code{Tag_T2EE_use},
657 @code{Tag_Virtualization_use}
659 The @var{value} is either a @code{number}, @code{"string"}, or
660 @code{number, "string"} depending on the tag.
662 Note - the following legacy values are also accepted by @var{tag}:
663 @code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
664 @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
666 @cindex @code{.even} directive, ARM
668 This directive aligns to an even-numbered address.
670 @cindex @code{.extend} directive, ARM
671 @cindex @code{.ldouble} directive, ARM
672 @item .extend @var{expression} [, @var{expression}]*
673 @itemx .ldouble @var{expression} [, @var{expression}]*
674 These directives write 12byte long double floating-point values to the
675 output section. These are not compatible with current ARM processors
678 @c FFFFFFFFFFFFFFFFFFFFFFFFFF
681 @cindex @code{.fnend} directive, ARM
683 Marks the end of a function with an unwind table entry. The unwind index
684 table entry is created when this directive is processed.
686 If no personality routine has been specified then standard personality
687 routine 0 or 1 will be used, depending on the number of unwind opcodes
691 @cindex @code{.fnstart} directive, ARM
693 Marks the start of a function with an unwind table entry.
695 @cindex @code{.force_thumb} directive, ARM
697 This directive forces the selection of Thumb instructions, even if the
698 target processor does not support those instructions
700 @cindex @code{.fpu} directive, ARM
701 @item .fpu @var{name}
702 Select the floating-point unit to assemble for. Valid values for @var{name}
703 are the same as for the @option{-mfpu} commandline option.
705 @c GGGGGGGGGGGGGGGGGGGGGGGGGG
706 @c HHHHHHHHHHHHHHHHHHHHHHHHHH
708 @cindex @code{.handlerdata} directive, ARM
710 Marks the end of the current function, and the start of the exception table
711 entry for that function. Anything between this directive and the
712 @code{.fnend} directive will be added to the exception table entry.
714 Must be preceded by a @code{.personality} or @code{.personalityindex}
717 @c IIIIIIIIIIIIIIIIIIIIIIIIII
719 @cindex @code{.inst} directive, ARM
720 @item .inst @var{opcode} [ , @dots{} ]
721 @itemx .inst.n @var{opcode} [ , @dots{} ]
722 @itemx .inst.w @var{opcode} [ , @dots{} ]
723 Generates the instruction corresponding to the numerical value @var{opcode}.
724 @code{.inst.n} and @code{.inst.w} allow the Thumb instruction size to be
725 specified explicitly, overriding the normal encoding rules.
727 @c JJJJJJJJJJJJJJJJJJJJJJJJJJ
728 @c KKKKKKKKKKKKKKKKKKKKKKKKKK
729 @c LLLLLLLLLLLLLLLLLLLLLLLLLL
731 @item .ldouble @var{expression} [, @var{expression}]*
734 @cindex @code{.ltorg} directive, ARM
736 This directive causes the current contents of the literal pool to be
737 dumped into the current section (which is assumed to be the .text
738 section) at the current location (aligned to a word boundary).
739 @code{GAS} maintains a separate literal pool for each section and each
740 sub-section. The @code{.ltorg} directive will only affect the literal
741 pool of the current section and sub-section. At the end of assembly
742 all remaining, un-empty literal pools will automatically be dumped.
744 Note - older versions of @code{GAS} would dump the current literal
745 pool any time a section change occurred. This is no longer done, since
746 it prevents accurate control of the placement of literal pools.
748 @c MMMMMMMMMMMMMMMMMMMMMMMMMM
750 @cindex @code{.movsp} directive, ARM
751 @item .movsp @var{reg} [, #@var{offset}]
752 Tell the unwinder that @var{reg} contains an offset from the current
753 stack pointer. If @var{offset} is not specified then it is assumed to be
756 @c NNNNNNNNNNNNNNNNNNNNNNNNNN
757 @c OOOOOOOOOOOOOOOOOOOOOOOOOO
759 @cindex @code{.object_arch} directive, ARM
760 @item .object_arch @var{name}
761 Override the architecture recorded in the EABI object attribute section.
762 Valid values for @var{name} are the same as for the @code{.arch} directive.
763 Typically this is useful when code uses runtime detection of CPU features.
765 @c PPPPPPPPPPPPPPPPPPPPPPPPPP
767 @cindex @code{.packed} directive, ARM
768 @item .packed @var{expression} [, @var{expression}]*
769 This directive writes 12-byte packed floating-point values to the
770 output section. These are not compatible with current ARM processors
773 @cindex @code{.pad} directive, ARM
774 @item .pad #@var{count}
775 Generate unwinder annotations for a stack adjustment of @var{count} bytes.
776 A positive value indicates the function prologue allocated stack space by
777 decrementing the stack pointer.
779 @cindex @code{.personality} directive, ARM
780 @item .personality @var{name}
781 Sets the personality routine for the current function to @var{name}.
783 @cindex @code{.personalityindex} directive, ARM
784 @item .personalityindex @var{index}
785 Sets the personality routine for the current function to the EABI standard
786 routine number @var{index}
788 @cindex @code{.pool} directive, ARM
790 This is a synonym for .ltorg.
792 @c QQQQQQQQQQQQQQQQQQQQQQQQQQ
793 @c RRRRRRRRRRRRRRRRRRRRRRRRRR
795 @cindex @code{.req} directive, ARM
796 @item @var{name} .req @var{register name}
797 This creates an alias for @var{register name} called @var{name}. For
804 @c SSSSSSSSSSSSSSSSSSSSSSSSSS
807 @cindex @code{.save} directive, ARM
808 @item .save @var{reglist}
809 Generate unwinder annotations to restore the registers in @var{reglist}.
810 The format of @var{reglist} is the same as the corresponding store-multiple
814 @exdent @emph{core registers}
815 .save @{r4, r5, r6, lr@}
816 stmfd sp!, @{r4, r5, r6, lr@}
817 @exdent @emph{FPA registers}
820 @exdent @emph{VFP registers}
821 .save @{d8, d9, d10@}
822 fstmdx sp!, @{d8, d9, d10@}
823 @exdent @emph{iWMMXt registers}
825 wstrd wr11, [sp, #-8]!
826 wstrd wr10, [sp, #-8]!
829 wstrd wr11, [sp, #-8]!
831 wstrd wr10, [sp, #-8]!
835 @cindex @code{.setfp} directive, ARM
836 @item .setfp @var{fpreg}, @var{spreg} [, #@var{offset}]
837 Make all unwinder annotations relative to a frame pointer. Without this
838 the unwinder will use offsets from the stack pointer.
840 The syntax of this directive is the same as the @code{add} or @code{mov}
841 instruction used to set the frame pointer. @var{spreg} must be either
842 @code{sp} or mentioned in a previous @code{.movsp} directive.
852 @cindex @code{.secrel32} directive, ARM
853 @item .secrel32 @var{expression} [, @var{expression}]*
854 This directive emits relocations that evaluate to the section-relative
855 offset of each expression's symbol. This directive is only supported
858 @cindex @code{.syntax} directive, ARM
859 @item .syntax [@code{unified} | @code{divided}]
860 This directive sets the Instruction Set Syntax as described in the
861 @ref{ARM-Instruction-Set} section.
863 @c TTTTTTTTTTTTTTTTTTTTTTTTTT
865 @cindex @code{.thumb} directive, ARM
867 This performs the same action as @var{.code 16}.
869 @cindex @code{.thumb_func} directive, ARM
871 This directive specifies that the following symbol is the name of a
872 Thumb encoded function. This information is necessary in order to allow
873 the assembler and linker to generate correct code for interworking
874 between Arm and Thumb instructions and should be used even if
875 interworking is not going to be performed. The presence of this
876 directive also implies @code{.thumb}
878 This directive is not neccessary when generating EABI objects. On these
879 targets the encoding is implicit when generating Thumb code.
881 @cindex @code{.thumb_set} directive, ARM
883 This performs the equivalent of a @code{.set} directive in that it
884 creates a symbol which is an alias for another symbol (possibly not yet
885 defined). This directive also has the added property in that it marks
886 the aliased symbol as being a thumb function entry point, in the same
887 way that the @code{.thumb_func} directive does.
889 @cindex @code{.tlsdescseq} directive, ARM
890 @item .tlsdescseq @var{tls-variable}
891 This directive is used to annotate parts of an inlined TLS descriptor
892 trampoline. Normally the trampoline is provided by the linker, and
893 this directive is not needed.
895 @c UUUUUUUUUUUUUUUUUUUUUUUUUU
897 @cindex @code{.unreq} directive, ARM
898 @item .unreq @var{alias-name}
899 This undefines a register alias which was previously defined using the
900 @code{req}, @code{dn} or @code{qn} directives. For example:
907 An error occurs if the name is undefined. Note - this pseudo op can
908 be used to delete builtin in register name aliases (eg 'r0'). This
909 should only be done if it is really necessary.
911 @cindex @code{.unwind_raw} directive, ARM
912 @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
913 Insert one of more arbitary unwind opcode bytes, which are known to adjust
914 the stack pointer by @var{offset} bytes.
916 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
919 @c VVVVVVVVVVVVVVVVVVVVVVVVVV
921 @cindex @code{.vsave} directive, ARM
922 @item .vsave @var{vfp-reglist}
923 Generate unwinder annotations to restore the VFP registers in @var{vfp-reglist}
924 using FLDMD. Also works for VFPv3 registers
925 that are to be restored using VLDM.
926 The format of @var{vfp-reglist} is the same as the corresponding store-multiple
930 @exdent @emph{VFP registers}
931 .vsave @{d8, d9, d10@}
932 fstmdd sp!, @{d8, d9, d10@}
933 @exdent @emph{VFPv3 registers}
934 .vsave @{d15, d16, d17@}
935 vstm sp!, @{d15, d16, d17@}
938 Since FLDMX and FSTMX are now deprecated, this directive should be
939 used in favour of @code{.save} for saving VFP registers for ARMv6 and above.
941 @c WWWWWWWWWWWWWWWWWWWWWWWWWW
942 @c XXXXXXXXXXXXXXXXXXXXXXXXXX
943 @c YYYYYYYYYYYYYYYYYYYYYYYYYY
944 @c ZZZZZZZZZZZZZZZZZZZZZZZZZZ
952 @cindex opcodes for ARM
953 @code{@value{AS}} implements all the standard ARM opcodes. It also
954 implements several pseudo opcodes, including several synthetic load
959 @cindex @code{NOP} pseudo op, ARM
965 This pseudo op will always evaluate to a legal ARM instruction that does
966 nothing. Currently it will evaluate to MOV r0, r0.
968 @cindex @code{LDR reg,=<label>} pseudo op, ARM
971 ldr <register> , = <expression>
974 If expression evaluates to a numeric constant then a MOV or MVN
975 instruction will be used in place of the LDR instruction, if the
976 constant can be generated by either of these instructions. Otherwise
977 the constant will be placed into the nearest literal pool (if it not
978 already there) and a PC relative LDR instruction will be generated.
980 @cindex @code{ADR reg,<label>} pseudo op, ARM
983 adr <register> <label>
986 This instruction will load the address of @var{label} into the indicated
987 register. The instruction will evaluate to a PC relative ADD or SUB
988 instruction depending upon where the label is located. If the label is
989 out of range, or if it is not defined in the same file (and section) as
990 the ADR instruction, then an error will be generated. This instruction
991 will not make use of the literal pool.
993 @cindex @code{ADRL reg,<label>} pseudo op, ARM
996 adrl <register> <label>
999 This instruction will load the address of @var{label} into the indicated
1000 register. The instruction will evaluate to one or two PC relative ADD
1001 or SUB instructions depending upon where the label is located. If a
1002 second instruction is not needed a NOP instruction will be generated in
1003 its place, so that this instruction is always 8 bytes long.
1005 If the label is out of range, or if it is not defined in the same file
1006 (and section) as the ADRL instruction, then an error will be generated.
1007 This instruction will not make use of the literal pool.
1011 For information on the ARM or Thumb instruction sets, see @cite{ARM
1012 Software Development Toolkit Reference Manual}, Advanced RISC Machines
1015 @node ARM Mapping Symbols
1016 @section Mapping Symbols
1018 The ARM ELF specification requires that special symbols be inserted
1019 into object files to mark certain features:
1025 At the start of a region of code containing ARM instructions.
1029 At the start of a region of code containing THUMB instructions.
1033 At the start of a region of data.
1037 The assembler will automatically insert these symbols for you - there
1038 is no need to code them yourself. Support for tagging symbols ($b,
1039 $f, $p and $m) which is also mentioned in the current ARM ELF
1040 specification is not implemented. This is because they have been
1041 dropped from the new EABI and so tools cannot rely upon their
1044 @node ARM Unwinding Tutorial
1047 The ABI for the ARM Architecture specifies a standard format for
1048 exception unwind information. This information is used when an
1049 exception is thrown to determine where control should be transferred.
1050 In particular, the unwind information is used to determine which
1051 function called the function that threw the exception, and which
1052 function called that one, and so forth. This information is also used
1053 to restore the values of callee-saved registers in the function
1054 catching the exception.
1056 If you are writing functions in assembly code, and those functions
1057 call other functions that throw exceptions, you must use assembly
1058 pseudo ops to ensure that appropriate exception unwind information is
1059 generated. Otherwise, if one of the functions called by your assembly
1060 code throws an exception, the run-time library will be unable to
1061 unwind the stack through your assembly code and your program will not
1064 To illustrate the use of these pseudo ops, we will examine the code
1065 that G++ generates for the following C++ input:
1068 void callee (int *);
1079 This example does not show how to throw or catch an exception from
1080 assembly code. That is a much more complex operation and should
1081 always be done in a high-level language, such as C++, that directly
1082 supports exceptions.
1084 The code generated by one particular version of G++ when compiling the
1091 @ Function supports interworking.
1092 @ args = 0, pretend = 0, frame = 8
1093 @ frame_needed = 1, uses_anonymous_args = 0
1115 Of course, the sequence of instructions varies based on the options
1116 you pass to GCC and on the version of GCC in use. The exact
1117 instructions are not important since we are focusing on the pseudo ops
1118 that are used to generate unwind information.
1120 An important assumption made by the unwinder is that the stack frame
1121 does not change during the body of the function. In particular, since
1122 we assume that the assembly code does not itself throw an exception,
1123 the only point where an exception can be thrown is from a call, such
1124 as the @code{bl} instruction above. At each call site, the same saved
1125 registers (including @code{lr}, which indicates the return address)
1126 must be located in the same locations relative to the frame pointer.
1128 The @code{.fnstart} (@pxref{arm_fnstart,,.fnstart pseudo op}) pseudo
1129 op appears immediately before the first instruction of the function
1130 while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
1131 op appears immediately after the last instruction of the function.
1132 These pseudo ops specify the range of the function.
1134 Only the order of the other pseudos ops (e.g., @code{.setfp} or
1135 @code{.pad}) matters; their exact locations are irrelevant. In the
1136 example above, the compiler emits the pseudo ops with particular
1137 instructions. That makes it easier to understand the code, but it is
1138 not required for correctness. It would work just as well to emit all
1139 of the pseudo ops other than @code{.fnend} in the same order, but
1140 immediately after @code{.fnstart}.
1142 The @code{.save} (@pxref{arm_save,,.save pseudo op}) pseudo op
1143 indicates registers that have been saved to the stack so that they can
1144 be restored before the function returns. The argument to the
1145 @code{.save} pseudo op is a list of registers to save. If a register
1146 is ``callee-saved'' (as specified by the ABI) and is modified by the
1147 function you are writing, then your code must save the value before it
1148 is modified and restore the original value before the function
1149 returns. If an exception is thrown, the run-time library restores the
1150 values of these registers from their locations on the stack before
1151 returning control to the exception handler. (Of course, if an
1152 exception is not thrown, the function that contains the @code{.save}
1153 pseudo op restores these registers in the function epilogue, as is
1154 done with the @code{ldmfd} instruction above.)
1156 You do not have to save callee-saved registers at the very beginning
1157 of the function and you do not need to use the @code{.save} pseudo op
1158 immediately following the point at which the registers are saved.
1159 However, if you modify a callee-saved register, you must save it on
1160 the stack before modifying it and before calling any functions which
1161 might throw an exception. And, you must use the @code{.save} pseudo
1162 op to indicate that you have done so.
1164 The @code{.pad} (@pxref{arm_pad,,.pad}) pseudo op indicates a
1165 modification of the stack pointer that does not save any registers.
1166 The argument is the number of bytes (in decimal) that are subtracted
1167 from the stack pointer. (On ARM CPUs, the stack grows downwards, so
1168 subtracting from the stack pointer increases the size of the stack.)
1170 The @code{.setfp} (@pxref{arm_setfp,,.setfp pseudo op}) pseudo op
1171 indicates the register that contains the frame pointer. The first
1172 argument is the register that is set, which is typically @code{fp}.
1173 The second argument indicates the register from which the frame
1174 pointer takes its value. The third argument, if present, is the value
1175 (in decimal) added to the register specified by the second argument to
1176 compute the value of the frame pointer. You should not modify the
1177 frame pointer in the body of the function.
1179 If you do not use a frame pointer, then you should not use the
1180 @code{.setfp} pseudo op. If you do not use a frame pointer, then you
1181 should avoid modifying the stack pointer outside of the function
1182 prologue. Otherwise, the run-time library will be unable to find
1183 saved registers when it is unwinding the stack.
1185 The pseudo ops described above are sufficient for writing assembly
1186 code that calls functions which may throw exceptions. If you need to
1187 know more about the object-file format used to represent unwind
1188 information, you may consult the @cite{Exception Handling ABI for the
1189 ARM Architecture} available from @uref{http://infocenter.arm.com}.
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