c696eeae106295bbb8d97c6acbef3c222310e607
[dragonfly.git] / sys / dev / drm / i915 / i915_dma.c
1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2  */
3 /*
4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5  * All Rights Reserved.
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a
8  * copy of this software and associated documentation files (the
9  * "Software"), to deal in the Software without restriction, including
10  * without limitation the rights to use, copy, modify, merge, publish,
11  * distribute, sub license, and/or sell copies of the Software, and to
12  * permit persons to whom the Software is furnished to do so, subject to
13  * the following conditions:
14  *
15  * The above copyright notice and this permission notice (including the
16  * next paragraph) shall be included in all copies or substantial portions
17  * of the Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26  *
27  */
28
29 #include <drm/drmP.h>
30 #include <drm/i915_drm.h>
31 #include "i915_drv.h"
32 #include "intel_drv.h"
33 #include "intel_ringbuffer.h"
34 #include <linux/workqueue.h>
35
36 extern struct drm_i915_private *i915_mch_dev;
37
38 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
39
40 #define BEGIN_LP_RING(n) \
41         intel_ring_begin(LP_RING(dev_priv), (n))
42
43 #define OUT_RING(x) \
44         intel_ring_emit(LP_RING(dev_priv), x)
45
46 #define ADVANCE_LP_RING() \
47         intel_ring_advance(LP_RING(dev_priv))
48
49 /**
50  * Lock test for when it's just for synchronization of ring access.
51  *
52  * In that case, we don't need to do it when GEM is initialized as nobody else
53  * has access to the ring.
54  */
55 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do {                      \
56         if (LP_RING(dev->dev_private)->obj == NULL)                     \
57                 LOCK_TEST_WITH_RETURN(dev, file);                       \
58 } while (0)
59
60 static inline u32
61 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
62 {
63         if (I915_NEED_GFX_HWS(dev_priv->dev))
64                 return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
65         else
66                 return intel_read_status_page(LP_RING(dev_priv), reg);
67 }
68
69 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
70 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
71 #define I915_BREADCRUMB_INDEX           0x21
72
73 void i915_update_dri1_breadcrumb(struct drm_device *dev)
74 {
75         /*
76          * The dri breadcrumb update races against the drm master disappearing.
77          * Instead of trying to fix this (this is by far not the only ums issue)
78          * just don't do the update in kms mode.
79          */
80         if (drm_core_check_feature(dev, DRIVER_MODESET))
81                 return;
82
83         /* XXX: don't do it at all actually */
84         return;
85 }
86
87 static void i915_write_hws_pga(struct drm_device *dev)
88 {
89         drm_i915_private_t *dev_priv = dev->dev_private;
90         u32 addr;
91
92         addr = dev_priv->status_page_dmah->busaddr;
93         if (INTEL_INFO(dev)->gen >= 4)
94                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
95         I915_WRITE(HWS_PGA, addr);
96 }
97
98 /**
99  * Frees the hardware status page, whether it's a physical address or a virtual
100  * address set up by the X Server.
101  */
102 static void i915_free_hws(struct drm_device *dev)
103 {
104         drm_i915_private_t *dev_priv = dev->dev_private;
105         struct intel_ring_buffer *ring = LP_RING(dev_priv);
106
107         if (dev_priv->status_page_dmah) {
108                 drm_pci_free(dev, dev_priv->status_page_dmah);
109                 dev_priv->status_page_dmah = NULL;
110         }
111
112         if (ring->status_page.gfx_addr) {
113                 ring->status_page.gfx_addr = 0;
114 #if 0   /* We don't care about dri1 */
115                 iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
116 #endif
117         }
118
119         /* Need to rewrite hardware status page */
120         I915_WRITE(HWS_PGA, 0x1ffff000);
121 }
122
123 void i915_kernel_lost_context(struct drm_device * dev)
124 {
125         drm_i915_private_t *dev_priv = dev->dev_private;
126         struct intel_ring_buffer *ring = LP_RING(dev_priv);
127
128         /*
129          * We should never lose context on the ring with modesetting
130          * as we don't expose it to userspace
131          */
132         if (drm_core_check_feature(dev, DRIVER_MODESET))
133                 return;
134
135         ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
136         ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
137         ring->space = ring->head - (ring->tail + I915_RING_FREE_SPACE);
138         if (ring->space < 0)
139                 ring->space += ring->size;
140
141 #if 1
142         KIB_NOTYET();
143 #else
144         if (!dev->primary->master)
145                 return;
146 #endif
147
148         if (ring->head == ring->tail && dev_priv->sarea_priv)
149                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
150 }
151
152 static int i915_dma_cleanup(struct drm_device * dev)
153 {
154         drm_i915_private_t *dev_priv = dev->dev_private;
155         int i;
156
157
158         /* Make sure interrupts are disabled here because the uninstall ioctl
159          * may not have been called from userspace and after dev_private
160          * is freed, it's too late.
161          */
162         if (dev->irq_enabled)
163                 drm_irq_uninstall(dev);
164
165         mutex_lock(&dev->struct_mutex);
166         for (i = 0; i < I915_NUM_RINGS; i++)
167                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
168         mutex_unlock(&dev->struct_mutex);
169
170         /* Clear the HWS virtual address at teardown */
171         if (I915_NEED_GFX_HWS(dev))
172                 i915_free_hws(dev);
173
174         return 0;
175 }
176
177 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
178 {
179         drm_i915_private_t *dev_priv = dev->dev_private;
180         int ret;
181
182         dev_priv->sarea = drm_getsarea(dev);
183         if (!dev_priv->sarea) {
184                 DRM_ERROR("can not find sarea!\n");
185                 i915_dma_cleanup(dev);
186                 return -EINVAL;
187         }
188
189         dev_priv->sarea_priv = (drm_i915_sarea_t *)
190             ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
191
192         if (init->ring_size != 0) {
193                 if (LP_RING(dev_priv)->obj != NULL) {
194                         i915_dma_cleanup(dev);
195                         DRM_ERROR("Client tried to initialize ringbuffer in "
196                                   "GEM mode\n");
197                         return -EINVAL;
198                 }
199
200                 ret = intel_render_ring_init_dri(dev,
201                                                  init->ring_start,
202                                                  init->ring_size);
203                 if (ret) {
204                         i915_dma_cleanup(dev);
205                         return ret;
206                 }
207         }
208
209         dev_priv->dri1.cpp = init->cpp;
210         dev_priv->dri1.back_offset = init->back_offset;
211         dev_priv->dri1.front_offset = init->front_offset;
212         dev_priv->dri1.current_page = 0;
213         dev_priv->sarea_priv->pf_current_page = 0;
214
215
216         /* Allow hardware batchbuffers unless told otherwise.
217          */
218         dev_priv->dri1.allow_batchbuffer = 1;
219
220         return 0;
221 }
222
223 static int i915_dma_resume(struct drm_device * dev)
224 {
225         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
226         struct intel_ring_buffer *ring = LP_RING(dev_priv);
227
228         DRM_DEBUG_DRIVER("%s\n", __func__);
229
230         if (ring->virtual_start == NULL) {
231                 DRM_ERROR("can not ioremap virtual address for"
232                           " ring buffer\n");
233                 return -ENOMEM;
234         }
235
236         /* Program Hardware Status Page */
237         if (!ring->status_page.page_addr) {
238                 DRM_ERROR("Can not find hardware status page\n");
239                 return -EINVAL;
240         }
241         DRM_DEBUG_DRIVER("hw status page @ %p\n",
242                                 ring->status_page.page_addr);
243         if (ring->status_page.gfx_addr != 0)
244                 intel_ring_setup_status_page(ring);
245         else
246                 i915_write_hws_pga(dev);
247
248         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
249
250         return 0;
251 }
252
253 static int i915_dma_init(struct drm_device *dev, void *data,
254                          struct drm_file *file_priv)
255 {
256         drm_i915_init_t *init = data;
257         int retcode = 0;
258
259         if (drm_core_check_feature(dev, DRIVER_MODESET))
260                 return -ENODEV;
261
262         switch (init->func) {
263         case I915_INIT_DMA:
264                 retcode = i915_initialize(dev, init);
265                 break;
266         case I915_CLEANUP_DMA:
267                 retcode = i915_dma_cleanup(dev);
268                 break;
269         case I915_RESUME_DMA:
270                 retcode = i915_dma_resume(dev);
271                 break;
272         default:
273                 retcode = -EINVAL;
274                 break;
275         }
276
277         return retcode;
278 }
279
280 /* Implement basically the same security restrictions as hardware does
281  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
282  *
283  * Most of the calculations below involve calculating the size of a
284  * particular instruction.  It's important to get the size right as
285  * that tells us where the next instruction to check is.  Any illegal
286  * instruction detected will be given a size of zero, which is a
287  * signal to abort the rest of the buffer.
288  */
289 static int validate_cmd(int cmd)
290 {
291         switch (((cmd >> 29) & 0x7)) {
292         case 0x0:
293                 switch ((cmd >> 23) & 0x3f) {
294                 case 0x0:
295                         return 1;       /* MI_NOOP */
296                 case 0x4:
297                         return 1;       /* MI_FLUSH */
298                 default:
299                         return 0;       /* disallow everything else */
300                 }
301                 break;
302         case 0x1:
303                 return 0;       /* reserved */
304         case 0x2:
305                 return (cmd & 0xff) + 2;        /* 2d commands */
306         case 0x3:
307                 if (((cmd >> 24) & 0x1f) <= 0x18)
308                         return 1;
309
310                 switch ((cmd >> 24) & 0x1f) {
311                 case 0x1c:
312                         return 1;
313                 case 0x1d:
314                         switch ((cmd >> 16) & 0xff) {
315                         case 0x3:
316                                 return (cmd & 0x1f) + 2;
317                         case 0x4:
318                                 return (cmd & 0xf) + 2;
319                         default:
320                                 return (cmd & 0xffff) + 2;
321                         }
322                 case 0x1e:
323                         if (cmd & (1 << 23))
324                                 return (cmd & 0xffff) + 1;
325                         else
326                                 return 1;
327                 case 0x1f:
328                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
329                                 return (cmd & 0x1ffff) + 2;
330                         else if (cmd & (1 << 17))       /* indirect random */
331                                 if ((cmd & 0xffff) == 0)
332                                         return 0;       /* unknown length, too hard */
333                                 else
334                                         return (((cmd & 0xffff) + 1) / 2) + 1;
335                         else
336                                 return 2;       /* indirect sequential */
337                 default:
338                         return 0;
339                 }
340         default:
341                 return 0;
342         }
343
344         return 0;
345 }
346
347 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
348 {
349         drm_i915_private_t *dev_priv = dev->dev_private;
350         int i, ret;
351
352         if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
353                 return -EINVAL;
354
355         for (i = 0; i < dwords;) {
356                 int sz = validate_cmd(buffer[i]);
357                 if (sz == 0 || i + sz > dwords)
358                         return -EINVAL;
359                 i += sz;
360         }
361
362         ret = BEGIN_LP_RING((dwords+1)&~1);
363         if (ret)
364                 return ret;
365
366         for (i = 0; i < dwords; i++)
367                 OUT_RING(buffer[i]);
368         if (dwords & 1)
369                 OUT_RING(0);
370
371         ADVANCE_LP_RING();
372
373         return 0;
374 }
375
376 int
377 i915_emit_box(struct drm_device *dev,
378               struct drm_clip_rect *box,
379               int DR1, int DR4)
380 {
381         struct drm_i915_private *dev_priv = dev->dev_private;
382         int ret;
383
384         if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
385             box->y2 <= 0 || box->x2 <= 0) {
386                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
387                           box->x1, box->y1, box->x2, box->y2);
388                 return -EINVAL;
389         }
390
391         if (INTEL_INFO(dev)->gen >= 4) {
392                 ret = BEGIN_LP_RING(4);
393                 if (ret)
394                         return ret;
395
396                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
397                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
398                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
399                 OUT_RING(DR4);
400         } else {
401                 ret = BEGIN_LP_RING(6);
402                 if (ret)
403                         return ret;
404
405                 OUT_RING(GFX_OP_DRAWRECT_INFO);
406                 OUT_RING(DR1);
407                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
408                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
409                 OUT_RING(DR4);
410                 OUT_RING(0);
411         }
412         ADVANCE_LP_RING();
413
414         return 0;
415 }
416
417 /* XXX: Emitting the counter should really be moved to part of the IRQ
418  * emit. For now, do it in both places:
419  */
420
421 static void i915_emit_breadcrumb(struct drm_device *dev)
422 {
423         drm_i915_private_t *dev_priv = dev->dev_private;
424
425         dev_priv->dri1.counter++;
426         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
427                 dev_priv->dri1.counter = 0;
428         if (dev_priv->sarea_priv)
429                 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
430
431         if (BEGIN_LP_RING(4) == 0) {
432                 OUT_RING(MI_STORE_DWORD_INDEX);
433                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
434                 OUT_RING(dev_priv->dri1.counter);
435                 OUT_RING(0);
436                 ADVANCE_LP_RING();
437         }
438 }
439
440 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
441                                    drm_i915_cmdbuffer_t *cmd,
442                                    struct drm_clip_rect *cliprects,
443                                    void *cmdbuf)
444 {
445         int nbox = cmd->num_cliprects;
446         int i = 0, count, ret;
447
448         if (cmd->sz & 0x3) {
449                 DRM_ERROR("alignment");
450                 return -EINVAL;
451         }
452
453         i915_kernel_lost_context(dev);
454
455         count = nbox ? nbox : 1;
456
457         for (i = 0; i < count; i++) {
458                 if (i < nbox) {
459                         ret = i915_emit_box(dev, &cliprects[i],
460                                             cmd->DR1, cmd->DR4);
461                         if (ret)
462                                 return ret;
463                 }
464
465                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
466                 if (ret)
467                         return ret;
468         }
469
470         i915_emit_breadcrumb(dev);
471         return 0;
472 }
473
474 static int i915_dispatch_batchbuffer(struct drm_device * dev,
475                                      drm_i915_batchbuffer_t * batch,
476                                      struct drm_clip_rect *cliprects)
477 {
478         struct drm_i915_private *dev_priv = dev->dev_private;
479         int nbox = batch->num_cliprects;
480         int i, count, ret;
481
482         if ((batch->start | batch->used) & 0x7) {
483                 DRM_ERROR("alignment");
484                 return -EINVAL;
485         }
486
487         i915_kernel_lost_context(dev);
488
489         count = nbox ? nbox : 1;
490         for (i = 0; i < count; i++) {
491                 if (i < nbox) {
492                         ret = i915_emit_box(dev, &cliprects[i],
493                                             batch->DR1, batch->DR4);
494                         if (ret)
495                                 return ret;
496                 }
497
498                 if (!IS_I830(dev) && !IS_845G(dev)) {
499                         ret = BEGIN_LP_RING(2);
500                         if (ret)
501                                 return ret;
502
503                         if (INTEL_INFO(dev)->gen >= 4) {
504                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
505                                 OUT_RING(batch->start);
506                         } else {
507                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
508                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
509                         }
510                 } else {
511                         ret = BEGIN_LP_RING(4);
512                         if (ret)
513                                 return ret;
514
515                         OUT_RING(MI_BATCH_BUFFER);
516                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
517                         OUT_RING(batch->start + batch->used - 4);
518                         OUT_RING(0);
519                 }
520                 ADVANCE_LP_RING();
521         }
522
523
524         if (IS_G4X(dev) || IS_GEN5(dev)) {
525                 if (BEGIN_LP_RING(2) == 0) {
526                         OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
527                         OUT_RING(MI_NOOP);
528                         ADVANCE_LP_RING();
529                 }
530         }
531
532         i915_emit_breadcrumb(dev);
533         return 0;
534 }
535
536 static int i915_dispatch_flip(struct drm_device * dev)
537 {
538         drm_i915_private_t *dev_priv = dev->dev_private;
539         int ret;
540
541         if (!dev_priv->sarea_priv)
542                 return -EINVAL;
543
544         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
545                           __func__,
546                          dev_priv->dri1.current_page,
547                          dev_priv->sarea_priv->pf_current_page);
548
549         i915_kernel_lost_context(dev);
550
551         ret = BEGIN_LP_RING(10);
552         if (ret)
553                 return ret;
554
555         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
556         OUT_RING(0);
557
558         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
559         OUT_RING(0);
560         if (dev_priv->dri1.current_page == 0) {
561                 OUT_RING(dev_priv->dri1.back_offset);
562                 dev_priv->dri1.current_page = 1;
563         } else {
564                 OUT_RING(dev_priv->dri1.front_offset);
565                 dev_priv->dri1.current_page = 0;
566         }
567         OUT_RING(0);
568
569         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
570         OUT_RING(0);
571
572         ADVANCE_LP_RING();
573
574         dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
575
576         if (BEGIN_LP_RING(4) == 0) {
577                 OUT_RING(MI_STORE_DWORD_INDEX);
578                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
579                 OUT_RING(dev_priv->dri1.counter);
580                 OUT_RING(0);
581                 ADVANCE_LP_RING();
582         }
583
584         dev_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
585         return 0;
586 }
587
588 static int i915_quiescent(struct drm_device *dev)
589 {
590         i915_kernel_lost_context(dev);
591         return intel_ring_idle(LP_RING(dev->dev_private));
592 }
593
594 static int i915_flush_ioctl(struct drm_device *dev, void *data,
595                             struct drm_file *file_priv)
596 {
597         int ret;
598
599         if (drm_core_check_feature(dev, DRIVER_MODESET))
600                 return -ENODEV;
601
602         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
603
604         mutex_lock(&dev->struct_mutex);
605         ret = i915_quiescent(dev);
606         mutex_unlock(&dev->struct_mutex);
607
608         return ret;
609 }
610
611 static int i915_batchbuffer(struct drm_device *dev, void *data,
612                             struct drm_file *file_priv)
613 {
614         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
615         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
616         drm_i915_batchbuffer_t *batch = data;
617         int ret;
618         struct drm_clip_rect *cliprects = NULL;
619
620         if (drm_core_check_feature(dev, DRIVER_MODESET))
621                 return -ENODEV;
622
623         if (!dev_priv->dri1.allow_batchbuffer) {
624                 DRM_ERROR("Batchbuffer ioctl disabled\n");
625                 return -EINVAL;
626         }
627
628         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
629                         batch->start, batch->used, batch->num_cliprects);
630
631         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
632
633         if (batch->num_cliprects < 0)
634                 return -EINVAL;
635
636         if (batch->num_cliprects) {
637                 cliprects = kmalloc(batch->num_cliprects *
638                                     sizeof(struct drm_clip_rect), M_DRM,
639                                     M_WAITOK | M_ZERO);
640                 if (cliprects == NULL)
641                         return -ENOMEM;
642
643                 ret = copy_from_user(cliprects, batch->cliprects,
644                                      batch->num_cliprects *
645                                      sizeof(struct drm_clip_rect));
646                 if (ret != 0) {
647                         ret = -EFAULT;
648                         goto fail_free;
649                 }
650         }
651
652         mutex_lock(&dev->struct_mutex);
653         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
654         mutex_unlock(&dev->struct_mutex);
655
656         if (sarea_priv)
657                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
658
659 fail_free:
660         kfree(cliprects, M_DRM);
661         return ret;
662 }
663
664 static int i915_cmdbuffer(struct drm_device *dev, void *data,
665                           struct drm_file *file_priv)
666 {
667         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
668         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
669         drm_i915_cmdbuffer_t *cmdbuf = data;
670         struct drm_clip_rect *cliprects = NULL;
671         void *batch_data;
672         int ret;
673
674         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
675                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
676
677         if (drm_core_check_feature(dev, DRIVER_MODESET))
678                 return -ENODEV;
679
680         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
681
682         if (cmdbuf->num_cliprects < 0)
683                 return -EINVAL;
684
685         batch_data = kmalloc(cmdbuf->sz, M_DRM, M_WAITOK);
686         if (batch_data == NULL)
687                 return -ENOMEM;
688
689         ret = -copyin(cmdbuf->buf, batch_data, cmdbuf->sz);
690         if (ret != 0) {
691                 ret = -EFAULT;
692                 goto fail_batch_free;
693         }
694
695         if (cmdbuf->num_cliprects) {
696                 cliprects = kmalloc(cmdbuf->num_cliprects *
697                                     sizeof(struct drm_clip_rect), M_DRM,
698                                     M_WAITOK | M_ZERO);
699                 if (cliprects == NULL) {
700                         ret = -ENOMEM;
701                         goto fail_batch_free;
702                 }
703
704                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
705                                      cmdbuf->num_cliprects *
706                                      sizeof(struct drm_clip_rect));
707                 if (ret != 0) {
708                         ret = -EFAULT;
709                         goto fail_clip_free;
710                 }
711         }
712
713         mutex_lock(&dev->struct_mutex);
714         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
715         mutex_unlock(&dev->struct_mutex);
716         if (ret) {
717                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
718                 goto fail_clip_free;
719         }
720
721         if (sarea_priv)
722                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
723
724 fail_clip_free:
725         drm_free(cliprects, M_DRM);
726 fail_batch_free:
727         drm_free(batch_data, M_DRM);
728         return ret;
729 }
730
731 static int i915_emit_irq(struct drm_device * dev)
732 {
733         drm_i915_private_t *dev_priv = dev->dev_private;
734 #if 0
735         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
736 #endif
737
738         i915_kernel_lost_context(dev);
739
740         DRM_DEBUG_DRIVER("\n");
741
742         dev_priv->dri1.counter++;
743         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
744                 dev_priv->dri1.counter = 1;
745         if (dev_priv->sarea_priv)
746                 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
747
748         if (BEGIN_LP_RING(4) == 0) {
749                 OUT_RING(MI_STORE_DWORD_INDEX);
750                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
751                 OUT_RING(dev_priv->dri1.counter);
752                 OUT_RING(MI_USER_INTERRUPT);
753                 ADVANCE_LP_RING();
754         }
755
756         return dev_priv->dri1.counter;
757 }
758
759 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
760 {
761         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
762 #if 0
763         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
764 #endif
765         int ret = 0;
766         struct intel_ring_buffer *ring = LP_RING(dev_priv);
767
768         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
769                   READ_BREADCRUMB(dev_priv));
770
771 #if 0
772         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
773                 if (master_priv->sarea_priv)
774                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
775                 return 0;
776         }
777
778         if (master_priv->sarea_priv)
779                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
780 #else
781         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
782                 if (dev_priv->sarea_priv) {
783                         dev_priv->sarea_priv->last_dispatch =
784                                 READ_BREADCRUMB(dev_priv);
785                 }
786                 return 0;
787         }
788
789         if (dev_priv->sarea_priv)
790                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
791 #endif
792
793         if (ring->irq_get(ring)) {
794                 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
795                             READ_BREADCRUMB(dev_priv) >= irq_nr);
796                 ring->irq_put(ring);
797         } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
798                 ret = -EBUSY;
799
800         if (ret == -EBUSY) {
801                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
802                           READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
803         }
804
805         return ret;
806 }
807
808 /* Needs the lock as it touches the ring.
809  */
810 static int i915_irq_emit(struct drm_device *dev, void *data,
811                          struct drm_file *file_priv)
812 {
813         drm_i915_private_t *dev_priv = dev->dev_private;
814         drm_i915_irq_emit_t *emit = data;
815         int result;
816
817         if (drm_core_check_feature(dev, DRIVER_MODESET))
818                 return -ENODEV;
819
820         if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
821                 DRM_ERROR("called with no initialization\n");
822                 return -EINVAL;
823         }
824
825         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
826
827         mutex_lock(&dev->struct_mutex);
828         result = i915_emit_irq(dev);
829         mutex_unlock(&dev->struct_mutex);
830
831         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
832                 DRM_ERROR("copy_to_user\n");
833                 return -EFAULT;
834         }
835
836         return 0;
837 }
838
839 /* Doesn't need the hardware lock.
840  */
841 static int i915_irq_wait(struct drm_device *dev, void *data,
842                          struct drm_file *file_priv)
843 {
844         drm_i915_private_t *dev_priv = dev->dev_private;
845         drm_i915_irq_wait_t *irqwait = data;
846
847         if (drm_core_check_feature(dev, DRIVER_MODESET))
848                 return -ENODEV;
849
850         if (!dev_priv) {
851                 DRM_ERROR("called with no initialization\n");
852                 return -EINVAL;
853         }
854
855         return i915_wait_irq(dev, irqwait->irq_seq);
856 }
857
858 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
859                          struct drm_file *file_priv)
860 {
861         drm_i915_private_t *dev_priv = dev->dev_private;
862         drm_i915_vblank_pipe_t *pipe = data;
863
864         if (drm_core_check_feature(dev, DRIVER_MODESET))
865                 return -ENODEV;
866
867         if (!dev_priv) {
868                 DRM_ERROR("called with no initialization\n");
869                 return -EINVAL;
870         }
871
872         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
873
874         return 0;
875 }
876
877 /**
878  * Schedule buffer swap at given vertical blank.
879  */
880 static int i915_vblank_swap(struct drm_device *dev, void *data,
881                      struct drm_file *file_priv)
882 {
883         /* The delayed swap mechanism was fundamentally racy, and has been
884          * removed.  The model was that the client requested a delayed flip/swap
885          * from the kernel, then waited for vblank before continuing to perform
886          * rendering.  The problem was that the kernel might wake the client
887          * up before it dispatched the vblank swap (since the lock has to be
888          * held while touching the ringbuffer), in which case the client would
889          * clear and start the next frame before the swap occurred, and
890          * flicker would occur in addition to likely missing the vblank.
891          *
892          * In the absence of this ioctl, userland falls back to a correct path
893          * of waiting for a vblank, then dispatching the swap on its own.
894          * Context switching to userland and back is plenty fast enough for
895          * meeting the requirements of vblank swapping.
896          */
897         return -EINVAL;
898 }
899
900 static int i915_flip_bufs(struct drm_device *dev, void *data,
901                           struct drm_file *file_priv)
902 {
903         int ret;
904
905         if (drm_core_check_feature(dev, DRIVER_MODESET))
906                 return -ENODEV;
907
908         DRM_DEBUG_DRIVER("%s\n", __func__);
909
910         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
911
912         mutex_lock(&dev->struct_mutex);
913         ret = i915_dispatch_flip(dev);
914         mutex_unlock(&dev->struct_mutex);
915
916         return ret;
917 }
918
919 static int i915_getparam(struct drm_device *dev, void *data,
920                          struct drm_file *file_priv)
921 {
922         drm_i915_private_t *dev_priv = dev->dev_private;
923         drm_i915_getparam_t *param = data;
924         int value;
925
926         if (!dev_priv) {
927                 DRM_ERROR("called with no initialization\n");
928                 return -EINVAL;
929         }
930
931         switch (param->param) {
932         case I915_PARAM_IRQ_ACTIVE:
933                 value = dev->irq_enabled ? 1 : 0;
934                 break;
935         case I915_PARAM_ALLOW_BATCHBUFFER:
936                 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
937                 break;
938         case I915_PARAM_LAST_DISPATCH:
939                 value = READ_BREADCRUMB(dev_priv);
940                 break;
941         case I915_PARAM_CHIPSET_ID:
942                 value = dev->pci_device;
943                 break;
944         case I915_PARAM_HAS_GEM:
945                 value = 1;
946                 break;
947         case I915_PARAM_NUM_FENCES_AVAIL:
948                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
949                 break;
950         case I915_PARAM_HAS_OVERLAY:
951                 value = dev_priv->overlay ? 1 : 0;
952                 break;
953         case I915_PARAM_HAS_PAGEFLIPPING:
954                 value = 1;
955                 break;
956         case I915_PARAM_HAS_EXECBUF2:
957                 /* depends on GEM */
958                 value = 1;
959                 break;
960         case I915_PARAM_HAS_BSD:
961                 value = intel_ring_initialized(&dev_priv->ring[VCS]);
962                 break;
963         case I915_PARAM_HAS_BLT:
964                 value = intel_ring_initialized(&dev_priv->ring[BCS]);
965                 break;
966         case I915_PARAM_HAS_RELAXED_FENCING:
967                 value = 1;
968                 break;
969         case I915_PARAM_HAS_COHERENT_RINGS:
970                 value = 1;
971                 break;
972         case I915_PARAM_HAS_EXEC_CONSTANTS:
973                 value = INTEL_INFO(dev)->gen >= 4;
974                 break;
975         case I915_PARAM_HAS_RELAXED_DELTA:
976                 value = 1;
977                 break;
978         case I915_PARAM_HAS_GEN7_SOL_RESET:
979                 value = 1;
980                 break;
981         case I915_PARAM_HAS_LLC:
982                 value = HAS_LLC(dev);
983                 break;
984         case I915_PARAM_HAS_ALIASING_PPGTT:
985                 value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
986                 break;
987         case I915_PARAM_HAS_WAIT_TIMEOUT:
988                 value = 1;
989                 break;
990         case I915_PARAM_HAS_SEMAPHORES:
991                 value = i915_semaphore_is_enabled(dev);
992                 break;
993         case I915_PARAM_HAS_PINNED_BATCHES:
994                 value = 1;
995                 break;
996         case I915_PARAM_HAS_EXEC_NO_RELOC:
997                 value = 1;
998                 break;
999         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
1000                 value = 1;
1001                 break;
1002         default:
1003                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
1004                                  param->param);
1005                 return -EINVAL;
1006         }
1007
1008         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
1009                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
1010                 return -EFAULT;
1011         }
1012
1013         return 0;
1014 }
1015
1016 static int i915_setparam(struct drm_device *dev, void *data,
1017                          struct drm_file *file_priv)
1018 {
1019         drm_i915_private_t *dev_priv = dev->dev_private;
1020         drm_i915_setparam_t *param = data;
1021
1022         if (!dev_priv) {
1023                 DRM_ERROR("called with no initialization\n");
1024                 return -EINVAL;
1025         }
1026
1027         switch (param->param) {
1028         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1029                 break;
1030         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1031                 break;
1032         case I915_SETPARAM_ALLOW_BATCHBUFFER:
1033                 dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
1034                 break;
1035         case I915_SETPARAM_NUM_USED_FENCES:
1036                 if (param->value > dev_priv->num_fence_regs ||
1037                     param->value < 0)
1038                         return -EINVAL;
1039                 /* Userspace can use first N regs */
1040                 dev_priv->fence_reg_start = param->value;
1041                 break;
1042         default:
1043                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
1044                                         param->param);
1045                 return -EINVAL;
1046         }
1047
1048         return 0;
1049 }
1050
1051 static int i915_set_status_page(struct drm_device *dev, void *data,
1052                                 struct drm_file *file_priv)
1053 {
1054 #if 0   /* We don't care about dri1 */
1055         drm_i915_private_t *dev_priv = dev->dev_private;
1056         drm_i915_hws_addr_t *hws = data;
1057         struct intel_ring_buffer *ring;
1058
1059         if (drm_core_check_feature(dev, DRIVER_MODESET))
1060                 return -ENODEV;
1061
1062         if (!I915_NEED_GFX_HWS(dev))
1063                 return -EINVAL;
1064
1065         if (!dev_priv) {
1066                 DRM_ERROR("called with no initialization\n");
1067                 return -EINVAL;
1068         }
1069
1070         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1071                 WARN(1, "tried to set status page when mode setting active\n");
1072                 return 0;
1073         }
1074
1075         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
1076
1077         ring = LP_RING(dev_priv);
1078         ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
1079
1080         dev_priv->dri1.gfx_hws_cpu_addr =
1081                 ioremap_wc(dev_priv->gtt.mappable_base + hws->addr, 4096);
1082         if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
1083                 i915_dma_cleanup(dev);
1084                 ring->status_page.gfx_addr = 0;
1085                 DRM_ERROR("can not ioremap virtual address for"
1086                                 " G33 hw status page\n");
1087                 return -ENOMEM;
1088         }
1089
1090         memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
1091         I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
1092
1093         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
1094                          ring->status_page.gfx_addr);
1095         DRM_DEBUG_DRIVER("load hws at %p\n",
1096                          ring->status_page.page_addr);
1097         return 0;
1098 #endif
1099         return -EINVAL;
1100 }
1101
1102 static int i915_get_bridge_dev(struct drm_device *dev)
1103 {
1104         struct drm_i915_private *dev_priv = dev->dev_private;
1105         static struct pci_dev i915_bridge_dev;
1106
1107         i915_bridge_dev.dev = pci_find_dbsf(0, 0, 0, 0);
1108         if (!i915_bridge_dev.dev) {
1109                 DRM_ERROR("bridge device not found\n");
1110                 return -1;
1111         }
1112
1113         dev_priv->bridge_dev = &i915_bridge_dev;
1114         return 0;
1115 }
1116
1117 #define MCHBAR_I915 0x44
1118 #define MCHBAR_I965 0x48
1119 #define MCHBAR_SIZE (4*4096)
1120
1121 #define DEVEN_REG 0x54
1122 #define   DEVEN_MCHBAR_EN (1 << 28)
1123
1124 /* Allocate space for the MCH regs if needed, return nonzero on error */
1125 static int
1126 intel_alloc_mchbar_resource(struct drm_device *dev)
1127 {
1128         drm_i915_private_t *dev_priv = dev->dev_private;
1129         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1130         device_t vga;
1131         u32 temp_lo, temp_hi = 0;
1132         u64 mchbar_addr;
1133
1134         if (INTEL_INFO(dev)->gen >= 4)
1135                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1136         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1137         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1138
1139         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1140 #ifdef CONFIG_PNP
1141         if (mchbar_addr &&
1142             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1143                 return 0;
1144 #endif
1145
1146         /* Get some space for it */
1147         vga = device_get_parent(dev->dev);
1148         dev_priv->mch_res_rid = 0x100;
1149         dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
1150             dev->dev, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
1151             MCHBAR_SIZE, RF_ACTIVE | RF_SHAREABLE, -1);
1152         if (dev_priv->mch_res == NULL) {
1153                 DRM_ERROR("failed mchbar resource alloc\n");
1154                 return (-ENOMEM);
1155         }
1156
1157         if (INTEL_INFO(dev)->gen >= 4)
1158                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
1159                                        upper_32_bits(rman_get_start(dev_priv->mch_res)));
1160
1161         pci_write_config_dword(dev_priv->bridge_dev, reg,
1162                                lower_32_bits(rman_get_start(dev_priv->mch_res)));
1163         return 0;
1164 }
1165
1166 /* Setup MCHBAR if possible, return true if we should disable it again */
1167 static void
1168 intel_setup_mchbar(struct drm_device *dev)
1169 {
1170         drm_i915_private_t *dev_priv = dev->dev_private;
1171         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1172         u32 temp;
1173         bool enabled;
1174
1175         dev_priv->mchbar_need_disable = false;
1176
1177         if (IS_I915G(dev) || IS_I915GM(dev)) {
1178                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1179                 enabled = (temp & DEVEN_MCHBAR_EN) != 0;
1180         } else {
1181                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1182                 enabled = temp & 1;
1183         }
1184
1185         /* If it's already enabled, don't have to do anything */
1186         if (enabled)
1187                 return;
1188
1189         if (intel_alloc_mchbar_resource(dev))
1190                 return;
1191
1192         dev_priv->mchbar_need_disable = true;
1193
1194         /* Space is allocated or reserved, so enable it. */
1195         if (IS_I915G(dev) || IS_I915GM(dev)) {
1196                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1197                                        temp | DEVEN_MCHBAR_EN);
1198         } else {
1199                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1200                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1201         }
1202 }
1203
1204 static void
1205 intel_teardown_mchbar(struct drm_device *dev)
1206 {
1207         drm_i915_private_t *dev_priv = dev->dev_private;
1208         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1209         device_t vga;
1210         u32 temp;
1211
1212         if (dev_priv->mchbar_need_disable) {
1213                 if (IS_I915G(dev) || IS_I915GM(dev)) {
1214                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1215                         temp &= ~DEVEN_MCHBAR_EN;
1216                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1217                 } else {
1218                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1219                         temp &= ~1;
1220                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1221                 }
1222         }
1223
1224         if (dev_priv->mch_res != NULL) {
1225                 vga = device_get_parent(dev->dev);
1226                 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev->dev,
1227                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1228                 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev->dev,
1229                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1230                 dev_priv->mch_res = NULL;
1231         }
1232 }
1233
1234 static int i915_load_modeset_init(struct drm_device *dev)
1235 {
1236         struct drm_i915_private *dev_priv = dev->dev_private;
1237         int ret;
1238
1239         ret = intel_parse_bios(dev);
1240         if (ret)
1241                 DRM_INFO("failed to find VBIOS tables\n");
1242
1243 #if 0
1244         /* If we have > 1 VGA cards, then we need to arbitrate access
1245          * to the common VGA resources.
1246          *
1247          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1248          * then we do not take part in VGA arbitration and the
1249          * vga_client_register() fails with -ENODEV.
1250          */
1251         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1252         if (ret && ret != -ENODEV)
1253                 goto out;
1254
1255         intel_register_dsm_handler();
1256
1257         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops);
1258         if (ret)
1259                 goto cleanup_vga_client;
1260
1261         /* Initialise stolen first so that we may reserve preallocated
1262          * objects for the BIOS to KMS transition.
1263          */
1264         ret = i915_gem_init_stolen(dev);
1265         if (ret)
1266                 goto cleanup_vga_switcheroo;
1267 #endif
1268
1269         ret = drm_irq_install(dev);
1270         if (ret)
1271                 goto cleanup_gem_stolen;
1272
1273         /* Important: The output setup functions called by modeset_init need
1274          * working irqs for e.g. gmbus and dp aux transfers. */
1275         intel_modeset_init(dev);
1276
1277         ret = i915_gem_init(dev);
1278         if (ret)
1279                 goto cleanup_irq;
1280
1281 #if 0
1282         INIT_WORK(&dev_priv->console_resume_work, intel_console_resume);
1283 #endif
1284
1285         intel_modeset_gem_init(dev);
1286
1287         /* Always safe in the mode setting case. */
1288         /* FIXME: do pre/post-mode set stuff in core KMS code */
1289         dev->vblank_disable_allowed = 1;
1290
1291         ret = intel_fbdev_init(dev);
1292         if (ret)
1293                 goto cleanup_gem;
1294
1295         /* Only enable hotplug handling once the fbdev is fully set up. */
1296         intel_hpd_init(dev);
1297
1298         /*
1299          * Some ports require correctly set-up hpd registers for detection to
1300          * work properly (leading to ghost connected connector status), e.g. VGA
1301          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1302          * irqs are fully enabled. Now we should scan for the initial config
1303          * only once hotplug handling is enabled, but due to screwed-up locking
1304          * around kms/fbdev init we can't protect the fdbev initial config
1305          * scanning against hotplug events. Hence do this first and ignore the
1306          * tiny window where we will loose hotplug notifactions.
1307          */
1308         intel_fbdev_initial_config(dev);
1309
1310         /* Only enable hotplug handling once the fbdev is fully set up. */
1311         dev_priv->enable_hotplug_processing = true;
1312
1313         drm_kms_helper_poll_init(dev);
1314
1315         /* We're off and running w/KMS */
1316         dev_priv->mm.suspended = 0;
1317
1318         return 0;
1319
1320 cleanup_gem:
1321         mutex_lock(&dev->struct_mutex);
1322         i915_gem_cleanup_ringbuffer(dev);
1323         mutex_unlock(&dev->struct_mutex);
1324         i915_gem_cleanup_aliasing_ppgtt(dev);
1325 cleanup_irq:
1326         drm_irq_uninstall(dev);
1327 cleanup_gem_stolen:
1328 #if 0
1329         i915_gem_cleanup_stolen(dev);
1330 cleanup_vga_switcheroo:
1331         vga_switcheroo_unregister_client(dev->pdev);
1332 cleanup_vga_client:
1333         vga_client_register(dev->pdev, NULL, NULL, NULL);
1334 out:
1335 #endif
1336         return ret;
1337 }
1338
1339 #if 0
1340 static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1341 {
1342         struct apertures_struct *ap;
1343         struct pci_dev *pdev = dev_priv->dev->pdev;
1344         bool primary;
1345
1346         ap = alloc_apertures(1);
1347         if (!ap)
1348                 return;
1349
1350         ap->ranges[0].base = dev_priv->gtt.mappable_base;
1351         ap->ranges[0].size = dev_priv->gtt.mappable_end - dev_priv->gtt.start;
1352
1353         primary =
1354                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1355
1356         remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
1357
1358         kfree(ap);
1359 }
1360 #endif
1361
1362 /**
1363  * i915_driver_load - setup chip and create an initial config
1364  * @dev: DRM device
1365  * @flags: startup flags
1366  *
1367  * The driver load routine has to do several things:
1368  *   - drive output discovery via intel_modeset_init()
1369  *   - initialize the memory manager
1370  *   - allocate initial config memory
1371  *   - setup the DRM framebuffer with the allocated memory
1372  */
1373 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1374 {
1375         struct drm_i915_private *dev_priv = dev->dev_private;
1376         unsigned long base, size;
1377         int ret = 0, mmio_bar;
1378         static struct pci_dev i915_pdev;
1379
1380         /* XXX: struct pci_dev */
1381         i915_pdev.dev = dev->dev;
1382         dev->pdev = &i915_pdev;
1383
1384         /* i915 has 4 more counters */
1385         dev->counters += 4;
1386         dev->types[6] = _DRM_STAT_IRQ;
1387         dev->types[7] = _DRM_STAT_PRIMARY;
1388         dev->types[8] = _DRM_STAT_SECONDARY;
1389         dev->types[9] = _DRM_STAT_DMA;
1390
1391         dev_priv = kmalloc(sizeof(drm_i915_private_t), M_DRM,
1392             M_ZERO | M_WAITOK);
1393         if (dev_priv == NULL)
1394                 return -ENOMEM;
1395
1396         dev->dev_private = (void *)dev_priv;
1397         dev_priv->dev = dev;
1398         dev_priv->info = i915_get_device_id(dev->pci_device);
1399
1400         if (i915_get_bridge_dev(dev)) {
1401                 ret = -EIO;
1402                 goto free_priv;
1403         }
1404
1405         ret = i915_gem_gtt_init(dev);
1406         if (ret)
1407                 goto put_bridge;
1408
1409 #if 0
1410         if (drm_core_check_feature(dev, DRIVER_MODESET))
1411                 i915_kick_out_firmware_fb(dev_priv);
1412
1413         pci_set_master(dev->pdev);
1414
1415         /* overlay on gen2 is broken and can't address above 1G */
1416         if (IS_GEN2(dev))
1417                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1418
1419         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1420          * using 32bit addressing, overwriting memory if HWS is located
1421          * above 4GB.
1422          *
1423          * The documentation also mentions an issue with undefined
1424          * behaviour if any general state is accessed within a page above 4GB,
1425          * which also needs to be handled carefully.
1426          */
1427         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1428                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1429 #endif
1430
1431         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1432         /* Before gen4, the registers and the GTT are behind different BARs.
1433          * However, from gen4 onwards, the registers and the GTT are shared
1434          * in the same BAR, so we want to restrict this ioremap from
1435          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1436          * the register BAR remains the same size for all the earlier
1437          * generations up to Ironlake.
1438          */
1439 #if 0
1440         if (info->gen < 5)
1441                 mmio_size = 512*1024;
1442         else
1443                 mmio_size = 2*1024*1024;
1444
1445         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1446         if (!dev_priv->regs) {
1447                 DRM_ERROR("failed to map registers\n");
1448                 ret = -EIO;
1449                 goto put_gmch;
1450         }
1451
1452         aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1453
1454         dev_priv->gtt.mappable =
1455                 io_mapping_create_wc(dev_priv->gtt.mappable_base,
1456                                      aperture_size);
1457         if (dev_priv->gtt.mappable == NULL) {
1458                 ret = -EIO;
1459                 goto out_rmmap;
1460         }
1461
1462         i915_mtrr_setup(dev_priv, dev_priv->gtt.mappable_base,
1463                         aperture_size);
1464 #endif
1465
1466         base = drm_get_resource_start(dev, mmio_bar);
1467         size = drm_get_resource_len(dev, mmio_bar);
1468
1469         ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
1470             _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
1471
1472         /* The i915 workqueue is primarily used for batched retirement of
1473          * requests (and thus managing bo) once the task has been completed
1474          * by the GPU. i915_gem_retire_requests() is called directly when we
1475          * need high-priority retirement, such as waiting for an explicit
1476          * bo.
1477          *
1478          * It is also used for periodic low-priority events, such as
1479          * idle-timers and recording error state.
1480          *
1481          * All tasks on the workqueue are expected to acquire the dev mutex
1482          * so there is no point in running more than one instance of the
1483          * workqueue at any time.  Use an ordered one.
1484          */
1485         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1486         if (dev_priv->wq == NULL) {
1487                 DRM_ERROR("Failed to create our workqueue.\n");
1488                 ret = -ENOMEM;
1489                 goto out_mtrrfree;
1490         }
1491
1492         /* This must be called before any calls to HAS_PCH_* */
1493         intel_detect_pch(dev);
1494
1495         intel_irq_init(dev);
1496         intel_gt_init(dev);
1497
1498         /* Try to make sure MCHBAR is enabled before poking at it */
1499         intel_setup_mchbar(dev);
1500         intel_setup_gmbus(dev);
1501         intel_opregion_setup(dev);
1502
1503         intel_setup_bios(dev);
1504
1505         i915_gem_load(dev);
1506
1507         /* On the 945G/GM, the chipset reports the MSI capability on the
1508          * integrated graphics even though the support isn't actually there
1509          * according to the published specs.  It doesn't appear to function
1510          * correctly in testing on 945G.
1511          * This may be a side effect of MSI having been made available for PEG
1512          * and the registers being closely associated.
1513          *
1514          * According to chipset errata, on the 965GM, MSI interrupts may
1515          * be lost or delayed, but we use them anyways to avoid
1516          * stuck interrupts on some machines.
1517          */
1518 #if 0
1519         if (!IS_I945G(dev) && !IS_I945GM(dev))
1520                 pci_enable_msi(dev->pdev);
1521 #endif
1522
1523         lockinit(&dev_priv->irq_lock, "userirq", 0, LK_CANRECURSE);
1524         lockinit(&dev_priv->gpu_error.lock, "915err", 0, LK_CANRECURSE);
1525         spin_init(&dev_priv->rps.lock, "i915initrps");
1526         lockinit(&dev_priv->dpio_lock, "i915dpio", 0, LK_CANRECURSE);
1527
1528         lockinit(&dev_priv->rps.hw_lock, "i915 rps.hw_lock", 0, LK_CANRECURSE);
1529         lockinit(&dev_priv->modeset_restore_lock, "i915mrl", 0, LK_CANRECURSE);
1530
1531         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1532                 dev_priv->num_pipe = 3;
1533         else if (IS_MOBILE(dev) || !IS_GEN2(dev))
1534                 dev_priv->num_pipe = 2;
1535         else
1536                 dev_priv->num_pipe = 1;
1537
1538         ret = drm_vblank_init(dev, dev_priv->num_pipe);
1539         if (ret)
1540                 goto out_gem_unload;
1541
1542         /* Start out suspended */
1543         dev_priv->mm.suspended = 1;
1544
1545         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1546                 ret = i915_load_modeset_init(dev);
1547                 if (ret < 0) {
1548                         DRM_ERROR("failed to init modeset\n");
1549                         goto out_gem_unload;
1550                 }
1551         }
1552
1553 #if 0
1554         i915_setup_sysfs(dev);
1555 #endif
1556
1557         /* Must be done after probing outputs */
1558         intel_opregion_init(dev);
1559 #if 0
1560         acpi_video_register();
1561 #endif
1562
1563         if (IS_GEN5(dev))
1564                 intel_gpu_ips_init(dev_priv);
1565
1566         return 0;
1567
1568 out_gem_unload:
1569
1570         intel_teardown_gmbus(dev);
1571         intel_teardown_mchbar(dev);
1572         destroy_workqueue(dev_priv->wq);
1573 out_mtrrfree:
1574 put_bridge:
1575 free_priv:
1576         kfree(dev_priv, M_DRM);
1577         return ret;
1578 }
1579
1580 int i915_driver_unload(struct drm_device *dev)
1581 {
1582         struct drm_i915_private *dev_priv = dev->dev_private;
1583         int ret;
1584
1585         intel_gpu_ips_teardown();
1586
1587 #if 0
1588         i915_teardown_sysfs(dev);
1589
1590         if (dev_priv->mm.inactive_shrinker.shrink)
1591                 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
1592 #endif
1593
1594         mutex_lock(&dev->struct_mutex);
1595         ret = i915_gpu_idle(dev);
1596         if (ret)
1597                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1598         i915_gem_retire_requests(dev);
1599         mutex_unlock(&dev->struct_mutex);
1600
1601         /* Cancel the retire work handler, which should be idle now. */
1602         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
1603
1604 #if 0
1605         io_mapping_free(dev_priv->gtt.mappable);
1606         if (dev_priv->mm.gtt_mtrr >= 0) {
1607                 mtrr_del(dev_priv->mm.gtt_mtrr,
1608                          dev_priv->gtt.mappable_base,
1609                          dev_priv->mm.gtt->gtt_mappable_entries * PAGE_SIZE);
1610                 dev_priv->mm.gtt_mtrr = -1;
1611         }
1612
1613         acpi_video_unregister();
1614 #endif
1615
1616         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1617                 intel_fbdev_fini(dev);
1618                 intel_modeset_cleanup(dev);
1619 #if 0
1620                 cancel_work_sync(&dev_priv->console_resume_work);
1621 #endif
1622
1623                 /*
1624                  * free the memory space allocated for the child device
1625                  * config parsed from VBT
1626                  */
1627                 if (dev_priv->child_dev && dev_priv->child_dev_num) {
1628                         kfree(dev_priv->child_dev, M_DRM);
1629                         dev_priv->child_dev = NULL;
1630                         dev_priv->child_dev_num = 0;
1631                 }
1632
1633         }
1634
1635         /* Free error state after interrupts are fully disabled. */
1636         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1637         cancel_work_sync(&dev_priv->gpu_error.work);
1638         i915_destroy_error_state(dev);
1639
1640         intel_opregion_fini(dev);
1641
1642         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1643                 /* Flush any outstanding unpin_work. */
1644                 flush_workqueue(dev_priv->wq);
1645
1646                 mutex_lock(&dev->struct_mutex);
1647                 i915_gem_free_all_phys_object(dev);
1648                 i915_gem_cleanup_ringbuffer(dev);
1649                 i915_gem_context_fini(dev);
1650                 mutex_unlock(&dev->struct_mutex);
1651                 i915_gem_cleanup_aliasing_ppgtt(dev);
1652 #if 0
1653                 i915_gem_cleanup_stolen(dev);
1654 #endif
1655
1656                 if (!I915_NEED_GFX_HWS(dev))
1657                         i915_free_hws(dev);
1658         }
1659
1660 #if 0
1661         if (dev_priv->regs != NULL)
1662                 pci_iounmap(dev->pdev, dev_priv->regs);
1663 #endif
1664
1665         intel_teardown_gmbus(dev);
1666         intel_teardown_mchbar(dev);
1667
1668         bus_generic_detach(dev->dev);
1669         drm_rmmap(dev, dev_priv->mmio_map);
1670         intel_teardown_gmbus(dev);
1671
1672         destroy_workqueue(dev_priv->wq);
1673         pm_qos_remove_request(&dev_priv->pm_qos);
1674
1675         pci_dev_put(dev_priv->bridge_dev);
1676         drm_free(dev->dev_private, M_DRM);
1677
1678         return 0;
1679 }
1680
1681 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1682 {
1683         struct drm_i915_file_private *file_priv;
1684
1685         DRM_DEBUG_DRIVER("\n");
1686         file_priv = kmalloc(sizeof(*file_priv), M_DRM, M_WAITOK | M_ZERO);
1687         if (!file_priv)
1688                 return -ENOMEM;
1689
1690         file->driver_priv = file_priv;
1691
1692         spin_init(&file_priv->mm.lock, "i915_priv");
1693         INIT_LIST_HEAD(&file_priv->mm.request_list);
1694
1695         idr_init(&file_priv->context_idr);
1696
1697         return 0;
1698 }
1699
1700 /**
1701  * i915_driver_lastclose - clean up after all DRM clients have exited
1702  * @dev: DRM device
1703  *
1704  * Take care of cleaning up after all DRM clients have exited.  In the
1705  * mode setting case, we want to restore the kernel's initial mode (just
1706  * in case the last client left us in a bad state).
1707  *
1708  * Additionally, in the non-mode setting case, we'll tear down the GTT
1709  * and DMA structures, since the kernel won't be using them, and clea
1710  * up any GEM state.
1711  */
1712 void i915_driver_lastclose(struct drm_device * dev)
1713 {
1714         drm_i915_private_t *dev_priv = dev->dev_private;
1715
1716         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
1717 #if 1
1718                 KIB_NOTYET();
1719 #else
1720                 drm_fb_helper_restore();
1721                 vga_switcheroo_process_delayed_switch();
1722 #endif
1723                 return;
1724         }
1725         i915_gem_lastclose(dev);
1726         i915_dma_cleanup(dev);
1727 }
1728
1729 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1730 {
1731         i915_gem_context_close(dev, file_priv);
1732         i915_gem_release(dev, file_priv);
1733 }
1734
1735 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1736 {
1737         struct drm_i915_file_private *file_priv = file->driver_priv;
1738
1739         kfree(file_priv, M_DRM);
1740 }
1741
1742 struct drm_ioctl_desc i915_ioctls[] = {
1743         DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1744         DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1745         DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
1746         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1747         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1748         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1749         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
1750         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1751         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1752         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1753         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1754         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1755         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1756         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1757         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH),
1758         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1759         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1760         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1761         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1762         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
1763         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1764         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1765         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1766         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED),
1767         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED),
1768         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
1769         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1770         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1771         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
1772         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1773         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1774         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
1775         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1776         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1777         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1778         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
1779         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
1780         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1781         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1782         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1783         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1784         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1785         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1786         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1787         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED),
1788         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED),
1789         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED),
1790         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED),
1791 };
1792
1793 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1794
1795 /*
1796  * This is really ugly: Because old userspace abused the linux agp interface to
1797  * manage the gtt, we need to claim that all intel devices are agp.  For
1798  * otherwise the drm core refuses to initialize the agp support code.
1799  */
1800 int i915_driver_device_is_agp(struct drm_device * dev)
1801 {
1802         return 1;
1803 }