1 /* radeon_state.c -- State support for Radeon -*- linux-c -*- */
3 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 * Gareth Hughes <gareth@valinux.com>
27 * Kevin E. Martin <martin@valinux.com>
29 * ------------------------ This file is DEPRECATED! -------------------------
31 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_state.c 254885 2013-08-25 19:37:15Z dumbbell $
35 #include <drm/drm_buffer.h>
36 #include <uapi_drm/radeon_drm.h>
37 #include "radeon_drv.h"
39 /* ================================================================
40 * Helper functions for client state checking and fixup
43 static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t *
45 struct drm_file * file_priv,
49 u32 fb_end = dev_priv->fb_location + dev_priv->fb_size - 1;
50 struct drm_radeon_driver_file_fields *radeon_priv;
52 /* Hrm ... the story of the offset ... So this function converts
53 * the various ideas of what userland clients might have for an
54 * offset in the card address space into an offset into the card
55 * address space :) So with a sane client, it should just keep
56 * the value intact and just do some boundary checking. However,
57 * not all clients are sane. Some older clients pass us 0 based
58 * offsets relative to the start of the framebuffer and some may
59 * assume the AGP aperture it appended to the framebuffer, so we
60 * try to detect those cases and fix them up.
62 * Note: It might be a good idea here to make sure the offset lands
63 * in some "allowed" area to protect things like the PCIE GART...
66 /* First, the best case, the offset already lands in either the
67 * framebuffer or the GART mapped space
69 if (radeon_check_offset(dev_priv, off))
72 /* Ok, that didn't happen... now check if we have a zero based
73 * offset that fits in the framebuffer + gart space, apply the
74 * magic offset we get from SETPARAM or calculated from fb_location
76 if (off < (dev_priv->fb_size + dev_priv->gart_size)) {
77 radeon_priv = file_priv->driver_priv;
78 off += radeon_priv->radeon_fb_delta;
81 /* Finally, assume we aimed at a GART offset if beyond the fb */
83 off = off - fb_end - 1 + dev_priv->gart_vm_start;
85 /* Now recheck and fail if out of bounds */
86 if (radeon_check_offset(dev_priv, off)) {
87 DRM_DEBUG("offset fixed up to 0x%x\n", (unsigned int)off);
94 static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
96 struct drm_file *file_priv,
97 int id, struct drm_buffer *buf)
102 case RADEON_EMIT_PP_MISC:
103 data = drm_buffer_pointer_to_dword(buf,
104 (RADEON_RB3D_DEPTHOFFSET - RADEON_PP_MISC) / 4);
106 if (radeon_check_and_fixup_offset(dev_priv, file_priv, data)) {
107 DRM_ERROR("Invalid depth buffer offset\n");
110 dev_priv->have_z_offset = 1;
113 case RADEON_EMIT_PP_CNTL:
114 data = drm_buffer_pointer_to_dword(buf,
115 (RADEON_RB3D_COLOROFFSET - RADEON_PP_CNTL) / 4);
117 if (radeon_check_and_fixup_offset(dev_priv, file_priv, data)) {
118 DRM_ERROR("Invalid colour buffer offset\n");
123 case R200_EMIT_PP_TXOFFSET_0:
124 case R200_EMIT_PP_TXOFFSET_1:
125 case R200_EMIT_PP_TXOFFSET_2:
126 case R200_EMIT_PP_TXOFFSET_3:
127 case R200_EMIT_PP_TXOFFSET_4:
128 case R200_EMIT_PP_TXOFFSET_5:
129 data = drm_buffer_pointer_to_dword(buf, 0);
130 if (radeon_check_and_fixup_offset(dev_priv, file_priv, data)) {
131 DRM_ERROR("Invalid R200 texture offset\n");
136 case RADEON_EMIT_PP_TXFILTER_0:
137 case RADEON_EMIT_PP_TXFILTER_1:
138 case RADEON_EMIT_PP_TXFILTER_2:
139 data = drm_buffer_pointer_to_dword(buf,
140 (RADEON_PP_TXOFFSET_0 - RADEON_PP_TXFILTER_0) / 4);
141 if (radeon_check_and_fixup_offset(dev_priv, file_priv, data)) {
142 DRM_ERROR("Invalid R100 texture offset\n");
147 case R200_EMIT_PP_CUBIC_OFFSETS_0:
148 case R200_EMIT_PP_CUBIC_OFFSETS_1:
149 case R200_EMIT_PP_CUBIC_OFFSETS_2:
150 case R200_EMIT_PP_CUBIC_OFFSETS_3:
151 case R200_EMIT_PP_CUBIC_OFFSETS_4:
152 case R200_EMIT_PP_CUBIC_OFFSETS_5:{
154 for (i = 0; i < 5; i++) {
155 data = drm_buffer_pointer_to_dword(buf, i);
156 if (radeon_check_and_fixup_offset(dev_priv,
160 ("Invalid R200 cubic texture offset\n");
167 case RADEON_EMIT_PP_CUBIC_OFFSETS_T0:
168 case RADEON_EMIT_PP_CUBIC_OFFSETS_T1:
169 case RADEON_EMIT_PP_CUBIC_OFFSETS_T2:{
171 for (i = 0; i < 5; i++) {
172 data = drm_buffer_pointer_to_dword(buf, i);
173 if (radeon_check_and_fixup_offset(dev_priv,
177 ("Invalid R100 cubic texture offset\n");
184 case R200_EMIT_VAP_CTL:{
187 OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0);
192 case RADEON_EMIT_RB3D_COLORPITCH:
193 case RADEON_EMIT_RE_LINE_PATTERN:
194 case RADEON_EMIT_SE_LINE_WIDTH:
195 case RADEON_EMIT_PP_LUM_MATRIX:
196 case RADEON_EMIT_PP_ROT_MATRIX_0:
197 case RADEON_EMIT_RB3D_STENCILREFMASK:
198 case RADEON_EMIT_SE_VPORT_XSCALE:
199 case RADEON_EMIT_SE_CNTL:
200 case RADEON_EMIT_SE_CNTL_STATUS:
201 case RADEON_EMIT_RE_MISC:
202 case RADEON_EMIT_PP_BORDER_COLOR_0:
203 case RADEON_EMIT_PP_BORDER_COLOR_1:
204 case RADEON_EMIT_PP_BORDER_COLOR_2:
205 case RADEON_EMIT_SE_ZBIAS_FACTOR:
206 case RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT:
207 case RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED:
208 case R200_EMIT_PP_TXCBLEND_0:
209 case R200_EMIT_PP_TXCBLEND_1:
210 case R200_EMIT_PP_TXCBLEND_2:
211 case R200_EMIT_PP_TXCBLEND_3:
212 case R200_EMIT_PP_TXCBLEND_4:
213 case R200_EMIT_PP_TXCBLEND_5:
214 case R200_EMIT_PP_TXCBLEND_6:
215 case R200_EMIT_PP_TXCBLEND_7:
216 case R200_EMIT_TCL_LIGHT_MODEL_CTL_0:
217 case R200_EMIT_TFACTOR_0:
218 case R200_EMIT_VTX_FMT_0:
219 case R200_EMIT_MATRIX_SELECT_0:
220 case R200_EMIT_TEX_PROC_CTL_2:
221 case R200_EMIT_TCL_UCP_VERT_BLEND_CTL:
222 case R200_EMIT_PP_TXFILTER_0:
223 case R200_EMIT_PP_TXFILTER_1:
224 case R200_EMIT_PP_TXFILTER_2:
225 case R200_EMIT_PP_TXFILTER_3:
226 case R200_EMIT_PP_TXFILTER_4:
227 case R200_EMIT_PP_TXFILTER_5:
228 case R200_EMIT_VTE_CNTL:
229 case R200_EMIT_OUTPUT_VTX_COMP_SEL:
230 case R200_EMIT_PP_TAM_DEBUG3:
231 case R200_EMIT_PP_CNTL_X:
232 case R200_EMIT_RB3D_DEPTHXY_OFFSET:
233 case R200_EMIT_RE_AUX_SCISSOR_CNTL:
234 case R200_EMIT_RE_SCISSOR_TL_0:
235 case R200_EMIT_RE_SCISSOR_TL_1:
236 case R200_EMIT_RE_SCISSOR_TL_2:
237 case R200_EMIT_SE_VAP_CNTL_STATUS:
238 case R200_EMIT_SE_VTX_STATE_CNTL:
239 case R200_EMIT_RE_POINTSIZE:
240 case R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0:
241 case R200_EMIT_PP_CUBIC_FACES_0:
242 case R200_EMIT_PP_CUBIC_FACES_1:
243 case R200_EMIT_PP_CUBIC_FACES_2:
244 case R200_EMIT_PP_CUBIC_FACES_3:
245 case R200_EMIT_PP_CUBIC_FACES_4:
246 case R200_EMIT_PP_CUBIC_FACES_5:
247 case RADEON_EMIT_PP_TEX_SIZE_0:
248 case RADEON_EMIT_PP_TEX_SIZE_1:
249 case RADEON_EMIT_PP_TEX_SIZE_2:
250 case R200_EMIT_RB3D_BLENDCOLOR:
251 case R200_EMIT_TCL_POINT_SPRITE_CNTL:
252 case RADEON_EMIT_PP_CUBIC_FACES_0:
253 case RADEON_EMIT_PP_CUBIC_FACES_1:
254 case RADEON_EMIT_PP_CUBIC_FACES_2:
255 case R200_EMIT_PP_TRI_PERF_CNTL:
256 case R200_EMIT_PP_AFS_0:
257 case R200_EMIT_PP_AFS_1:
258 case R200_EMIT_ATF_TFACTOR:
259 case R200_EMIT_PP_TXCTLALL_0:
260 case R200_EMIT_PP_TXCTLALL_1:
261 case R200_EMIT_PP_TXCTLALL_2:
262 case R200_EMIT_PP_TXCTLALL_3:
263 case R200_EMIT_PP_TXCTLALL_4:
264 case R200_EMIT_PP_TXCTLALL_5:
265 case R200_EMIT_VAP_PVS_CNTL:
266 /* These packets don't contain memory offsets */
270 DRM_ERROR("Unknown state packet ID %d\n", id);
277 static int radeon_check_and_fixup_packet3(drm_radeon_private_t *
279 struct drm_file *file_priv,
280 drm_radeon_kcmd_buffer_t *
284 u32 *cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 0);
288 count = ((*cmd & RADEON_CP_PACKET_COUNT_MASK) >> 16);
291 if ((*cmd & 0xc0000000) != RADEON_CP_PACKET3) {
292 DRM_ERROR("Not a type 3 packet\n");
296 if (4 * *cmdsz > drm_buffer_unprocessed(cmdbuf->buffer)) {
297 DRM_ERROR("Packet size larger than size of data provided\n");
301 switch (*cmd & 0xff00) {
302 /* XXX Are there old drivers needing other packets? */
304 case RADEON_3D_DRAW_IMMD:
305 case RADEON_3D_DRAW_VBUF:
306 case RADEON_3D_DRAW_INDX:
307 case RADEON_WAIT_FOR_IDLE:
309 case RADEON_3D_CLEAR_ZMASK:
310 /* case RADEON_CP_NEXT_CHAR:
311 case RADEON_CP_PLY_NEXTSCAN:
312 case RADEON_CP_SET_SCISSORS: */ /* probably safe but will never need them? */
313 /* these packets are safe */
316 case RADEON_CP_3D_DRAW_IMMD_2:
317 case RADEON_CP_3D_DRAW_VBUF_2:
318 case RADEON_CP_3D_DRAW_INDX_2:
319 case RADEON_3D_CLEAR_HIZ:
320 /* safe but r200 only */
321 if (dev_priv->microcode_version != UCODE_R200) {
322 DRM_ERROR("Invalid 3d packet for r100-class chip\n");
327 case RADEON_3D_LOAD_VBPNTR:
329 if (count > 18) { /* 12 arrays max */
330 DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n",
335 /* carefully check packet contents */
336 cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 1);
338 narrays = *cmd & ~0xc000;
341 while ((k < narrays) && (i < (count + 2))) {
342 i++; /* skip attribute field */
343 cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, i);
344 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
347 ("Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.\n",
355 /* have one more to process, they come in pairs */
356 cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, i);
358 if (radeon_check_and_fixup_offset(dev_priv,
362 ("Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.\n",
369 /* do the counts match what we expect ? */
370 if ((k != narrays) || (i != (count + 2))) {
372 ("Malformed 3D_LOAD_VBPNTR packet (k=%d i=%d narrays=%d count+1=%d).\n",
373 k, i, narrays, count + 1);
378 case RADEON_3D_RNDR_GEN_INDX_PRIM:
379 if (dev_priv->microcode_version != UCODE_R100) {
380 DRM_ERROR("Invalid 3d packet for r200-class chip\n");
384 cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 1);
385 if (radeon_check_and_fixup_offset(dev_priv, file_priv, cmd)) {
386 DRM_ERROR("Invalid rndr_gen_indx offset\n");
391 case RADEON_CP_INDX_BUFFER:
392 if (dev_priv->microcode_version != UCODE_R200) {
393 DRM_ERROR("Invalid 3d packet for r100-class chip\n");
397 cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 1);
398 if ((*cmd & 0x8000ffff) != 0x80000810) {
399 DRM_ERROR("Invalid indx_buffer reg address %08X\n", *cmd);
402 cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 2);
403 if (radeon_check_and_fixup_offset(dev_priv, file_priv, cmd)) {
404 DRM_ERROR("Invalid indx_buffer offset is %08X\n", *cmd);
409 case RADEON_CNTL_HOSTDATA_BLT:
410 case RADEON_CNTL_PAINT_MULTI:
411 case RADEON_CNTL_BITBLT_MULTI:
412 /* MSB of opcode: next DWORD GUI_CNTL */
413 cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 1);
414 if (*cmd & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL
415 | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
416 u32 *cmd2 = drm_buffer_pointer_to_dword(cmdbuf->buffer, 2);
417 offset = *cmd2 << 10;
418 if (radeon_check_and_fixup_offset
419 (dev_priv, file_priv, &offset)) {
420 DRM_ERROR("Invalid first packet offset\n");
423 *cmd2 = (*cmd2 & 0xffc00000) | offset >> 10;
426 if ((*cmd & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) &&
427 (*cmd & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
428 u32 *cmd3 = drm_buffer_pointer_to_dword(cmdbuf->buffer, 3);
429 offset = *cmd3 << 10;
430 if (radeon_check_and_fixup_offset
431 (dev_priv, file_priv, &offset)) {
432 DRM_ERROR("Invalid second packet offset\n");
435 *cmd3 = (*cmd3 & 0xffc00000) | offset >> 10;
440 DRM_ERROR("Invalid packet type %x\n", *cmd & 0xff00);
447 /* ================================================================
448 * CP hardware state programming functions
451 static void radeon_emit_clip_rect(drm_radeon_private_t * dev_priv,
452 struct drm_clip_rect * box)
456 DRM_DEBUG(" box: x1=%d y1=%d x2=%d y2=%d\n",
457 box->x1, box->y1, box->x2, box->y2);
460 OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0));
461 OUT_RING((box->y1 << 16) | box->x1);
462 OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
463 OUT_RING(((box->y2 - 1) << 16) | (box->x2 - 1));
469 static int radeon_emit_state(drm_radeon_private_t * dev_priv,
470 struct drm_file *file_priv,
471 drm_radeon_context_regs_t * ctx,
472 drm_radeon_texture_regs_t * tex,
476 DRM_DEBUG("dirty=0x%08x\n", dirty);
478 if (dirty & RADEON_UPLOAD_CONTEXT) {
479 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
480 &ctx->rb3d_depthoffset)) {
481 DRM_ERROR("Invalid depth buffer offset\n");
485 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
486 &ctx->rb3d_coloroffset)) {
487 DRM_ERROR("Invalid depth buffer offset\n");
492 OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6));
493 OUT_RING(ctx->pp_misc);
494 OUT_RING(ctx->pp_fog_color);
495 OUT_RING(ctx->re_solid_color);
496 OUT_RING(ctx->rb3d_blendcntl);
497 OUT_RING(ctx->rb3d_depthoffset);
498 OUT_RING(ctx->rb3d_depthpitch);
499 OUT_RING(ctx->rb3d_zstencilcntl);
500 OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 2));
501 OUT_RING(ctx->pp_cntl);
502 OUT_RING(ctx->rb3d_cntl);
503 OUT_RING(ctx->rb3d_coloroffset);
504 OUT_RING(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
505 OUT_RING(ctx->rb3d_colorpitch);
509 if (dirty & RADEON_UPLOAD_VERTFMT) {
511 OUT_RING(CP_PACKET0(RADEON_SE_COORD_FMT, 0));
512 OUT_RING(ctx->se_coord_fmt);
516 if (dirty & RADEON_UPLOAD_LINE) {
518 OUT_RING(CP_PACKET0(RADEON_RE_LINE_PATTERN, 1));
519 OUT_RING(ctx->re_line_pattern);
520 OUT_RING(ctx->re_line_state);
521 OUT_RING(CP_PACKET0(RADEON_SE_LINE_WIDTH, 0));
522 OUT_RING(ctx->se_line_width);
526 if (dirty & RADEON_UPLOAD_BUMPMAP) {
528 OUT_RING(CP_PACKET0(RADEON_PP_LUM_MATRIX, 0));
529 OUT_RING(ctx->pp_lum_matrix);
530 OUT_RING(CP_PACKET0(RADEON_PP_ROT_MATRIX_0, 1));
531 OUT_RING(ctx->pp_rot_matrix_0);
532 OUT_RING(ctx->pp_rot_matrix_1);
536 if (dirty & RADEON_UPLOAD_MASKS) {
538 OUT_RING(CP_PACKET0(RADEON_RB3D_STENCILREFMASK, 2));
539 OUT_RING(ctx->rb3d_stencilrefmask);
540 OUT_RING(ctx->rb3d_ropcntl);
541 OUT_RING(ctx->rb3d_planemask);
545 if (dirty & RADEON_UPLOAD_VIEWPORT) {
547 OUT_RING(CP_PACKET0(RADEON_SE_VPORT_XSCALE, 5));
548 OUT_RING(ctx->se_vport_xscale);
549 OUT_RING(ctx->se_vport_xoffset);
550 OUT_RING(ctx->se_vport_yscale);
551 OUT_RING(ctx->se_vport_yoffset);
552 OUT_RING(ctx->se_vport_zscale);
553 OUT_RING(ctx->se_vport_zoffset);
557 if (dirty & RADEON_UPLOAD_SETUP) {
559 OUT_RING(CP_PACKET0(RADEON_SE_CNTL, 0));
560 OUT_RING(ctx->se_cntl);
561 OUT_RING(CP_PACKET0(RADEON_SE_CNTL_STATUS, 0));
562 OUT_RING(ctx->se_cntl_status);
566 if (dirty & RADEON_UPLOAD_MISC) {
568 OUT_RING(CP_PACKET0(RADEON_RE_MISC, 0));
569 OUT_RING(ctx->re_misc);
573 if (dirty & RADEON_UPLOAD_TEX0) {
574 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
575 &tex[0].pp_txoffset)) {
576 DRM_ERROR("Invalid texture offset for unit 0\n");
581 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_0, 5));
582 OUT_RING(tex[0].pp_txfilter);
583 OUT_RING(tex[0].pp_txformat);
584 OUT_RING(tex[0].pp_txoffset);
585 OUT_RING(tex[0].pp_txcblend);
586 OUT_RING(tex[0].pp_txablend);
587 OUT_RING(tex[0].pp_tfactor);
588 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_0, 0));
589 OUT_RING(tex[0].pp_border_color);
593 if (dirty & RADEON_UPLOAD_TEX1) {
594 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
595 &tex[1].pp_txoffset)) {
596 DRM_ERROR("Invalid texture offset for unit 1\n");
601 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_1, 5));
602 OUT_RING(tex[1].pp_txfilter);
603 OUT_RING(tex[1].pp_txformat);
604 OUT_RING(tex[1].pp_txoffset);
605 OUT_RING(tex[1].pp_txcblend);
606 OUT_RING(tex[1].pp_txablend);
607 OUT_RING(tex[1].pp_tfactor);
608 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_1, 0));
609 OUT_RING(tex[1].pp_border_color);
613 if (dirty & RADEON_UPLOAD_TEX2) {
614 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
615 &tex[2].pp_txoffset)) {
616 DRM_ERROR("Invalid texture offset for unit 2\n");
621 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_2, 5));
622 OUT_RING(tex[2].pp_txfilter);
623 OUT_RING(tex[2].pp_txformat);
624 OUT_RING(tex[2].pp_txoffset);
625 OUT_RING(tex[2].pp_txcblend);
626 OUT_RING(tex[2].pp_txablend);
627 OUT_RING(tex[2].pp_tfactor);
628 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_2, 0));
629 OUT_RING(tex[2].pp_border_color);
638 static int radeon_emit_state2(drm_radeon_private_t * dev_priv,
639 struct drm_file *file_priv,
640 drm_radeon_state_t * state)
644 if (state->dirty & RADEON_UPLOAD_ZBIAS) {
646 OUT_RING(CP_PACKET0(RADEON_SE_ZBIAS_FACTOR, 1));
647 OUT_RING(state->context2.se_zbias_factor);
648 OUT_RING(state->context2.se_zbias_constant);
652 return radeon_emit_state(dev_priv, file_priv, &state->context,
653 state->tex, state->dirty);
656 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
657 * 1.3 cmdbuffers allow all previous state to be updated as well as
658 * the tcl scalar and vector areas.
664 } packet[RADEON_MAX_STATE_PACKETS] = {
665 {RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
666 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
667 {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
668 {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
669 {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
670 {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
671 {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
672 {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
673 {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
674 {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
675 {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
676 {RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
677 {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
678 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
679 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
680 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
681 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
682 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
683 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
684 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
685 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
686 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
687 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
688 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
689 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
690 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
691 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
692 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
693 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
694 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
695 {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
696 {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
697 {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
698 {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
699 {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
700 {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
701 {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
702 {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
703 {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
704 {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
705 {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
706 {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
707 {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
708 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
709 {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
710 {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
711 {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
712 {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
713 {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
714 {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
715 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1,
716 "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
717 {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
718 {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
719 {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
720 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
721 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
722 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
723 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
724 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
725 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
726 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
727 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
728 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
729 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
730 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
731 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
732 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
733 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
734 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
735 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
736 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
737 {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
738 {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
739 {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
740 {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
741 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
742 {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
743 {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
744 {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
745 {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
746 {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
747 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
748 {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
749 {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
750 {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
751 {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
752 {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
753 {R200_PP_AFS_0, 32, "R200_PP_AFS_0"}, /* 85 */
754 {R200_PP_AFS_1, 32, "R200_PP_AFS_1"},
755 {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
756 {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
757 {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
758 {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
759 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
760 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
761 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
762 {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
765 /* ================================================================
766 * Performance monitoring functions
769 static void radeon_clear_box(drm_radeon_private_t * dev_priv,
770 struct drm_radeon_master_private *master_priv,
771 int x, int y, int w, int h, int r, int g, int b)
776 x += master_priv->sarea_priv->boxes[0].x1;
777 y += master_priv->sarea_priv->boxes[0].y1;
779 switch (dev_priv->color_fmt) {
780 case RADEON_COLOR_FORMAT_RGB565:
781 color = (((r & 0xf8) << 8) |
782 ((g & 0xfc) << 3) | ((b & 0xf8) >> 3));
784 case RADEON_COLOR_FORMAT_ARGB8888:
786 color = (((0xff) << 24) | (r << 16) | (g << 8) | b);
791 RADEON_WAIT_UNTIL_3D_IDLE();
792 OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0));
793 OUT_RING(0xffffffff);
798 OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4));
799 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
800 RADEON_GMC_BRUSH_SOLID_COLOR |
801 (dev_priv->color_fmt << 8) |
802 RADEON_GMC_SRC_DATATYPE_COLOR |
803 RADEON_ROP3_P | RADEON_GMC_CLR_CMP_CNTL_DIS);
805 if (master_priv->sarea_priv->pfCurrentPage == 1) {
806 OUT_RING(dev_priv->front_pitch_offset);
808 OUT_RING(dev_priv->back_pitch_offset);
813 OUT_RING((x << 16) | y);
814 OUT_RING((w << 16) | h);
819 static void radeon_cp_performance_boxes(drm_radeon_private_t *dev_priv, struct drm_radeon_master_private *master_priv)
821 /* Collapse various things into a wait flag -- trying to
822 * guess if userspase slept -- better just to have them tell us.
824 if (dev_priv->stats.last_frame_reads > 1 ||
825 dev_priv->stats.last_clear_reads > dev_priv->stats.clears) {
826 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
829 if (dev_priv->stats.freelist_loops) {
830 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
833 /* Purple box for page flipping
835 if (dev_priv->stats.boxes & RADEON_BOX_FLIP)
836 radeon_clear_box(dev_priv, master_priv, 4, 4, 8, 8, 255, 0, 255);
838 /* Red box if we have to wait for idle at any point
840 if (dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE)
841 radeon_clear_box(dev_priv, master_priv, 16, 4, 8, 8, 255, 0, 0);
843 /* Blue box: lost context?
846 /* Yellow box for texture swaps
848 if (dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD)
849 radeon_clear_box(dev_priv, master_priv, 40, 4, 8, 8, 255, 255, 0);
851 /* Green box if hardware never idles (as far as we can tell)
853 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE))
854 radeon_clear_box(dev_priv, master_priv, 64, 4, 8, 8, 0, 255, 0);
856 /* Draw bars indicating number of buffers allocated
857 * (not a great measure, easily confused)
859 if (dev_priv->stats.requested_bufs) {
860 if (dev_priv->stats.requested_bufs > 100)
861 dev_priv->stats.requested_bufs = 100;
863 radeon_clear_box(dev_priv, master_priv, 4, 16,
864 dev_priv->stats.requested_bufs, 4,
868 memset(&dev_priv->stats, 0, sizeof(dev_priv->stats));
872 /* ================================================================
873 * CP command dispatch functions
876 static void radeon_cp_dispatch_clear(struct drm_device * dev,
877 struct drm_master *master,
878 drm_radeon_clear_t * clear,
879 drm_radeon_clear_rect_t * depth_boxes)
881 drm_radeon_private_t *dev_priv = dev->dev_private;
882 struct drm_radeon_master_private *master_priv = master->driver_priv;
883 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
884 drm_radeon_depth_clear_t *depth_clear = &dev_priv->depth_clear;
885 int nbox = sarea_priv->nbox;
886 struct drm_clip_rect *pbox = sarea_priv->boxes;
887 unsigned int flags = clear->flags;
888 u32 rb3d_cntl = 0, rb3d_stencilrefmask = 0;
891 DRM_DEBUG("flags = 0x%x\n", flags);
893 dev_priv->stats.clears++;
895 if (sarea_priv->pfCurrentPage == 1) {
896 unsigned int tmp = flags;
898 flags &= ~(RADEON_FRONT | RADEON_BACK);
899 if (tmp & RADEON_FRONT)
900 flags |= RADEON_BACK;
901 if (tmp & RADEON_BACK)
902 flags |= RADEON_FRONT;
904 if (flags & (RADEON_DEPTH|RADEON_STENCIL)) {
905 if (!dev_priv->have_z_offset) {
906 printk_once(KERN_ERR "radeon: illegal depth clear request. Buggy mesa detected - please update.\n");
907 flags &= ~(RADEON_DEPTH | RADEON_STENCIL);
911 if (flags & (RADEON_FRONT | RADEON_BACK)) {
915 /* Ensure the 3D stream is idle before doing a
916 * 2D fill to clear the front or back buffer.
918 RADEON_WAIT_UNTIL_3D_IDLE();
920 OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0));
921 OUT_RING(clear->color_mask);
925 /* Make sure we restore the 3D state next time.
927 sarea_priv->ctx_owner = 0;
929 for (i = 0; i < nbox; i++) {
932 int w = pbox[i].x2 - x;
933 int h = pbox[i].y2 - y;
935 DRM_DEBUG("%d,%d-%d,%d flags 0x%x\n",
938 if (flags & RADEON_FRONT) {
942 (RADEON_CNTL_PAINT_MULTI, 4));
943 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
944 RADEON_GMC_BRUSH_SOLID_COLOR |
947 RADEON_GMC_SRC_DATATYPE_COLOR |
949 RADEON_GMC_CLR_CMP_CNTL_DIS);
951 OUT_RING(dev_priv->front_pitch_offset);
952 OUT_RING(clear->clear_color);
954 OUT_RING((x << 16) | y);
955 OUT_RING((w << 16) | h);
960 if (flags & RADEON_BACK) {
964 (RADEON_CNTL_PAINT_MULTI, 4));
965 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
966 RADEON_GMC_BRUSH_SOLID_COLOR |
969 RADEON_GMC_SRC_DATATYPE_COLOR |
971 RADEON_GMC_CLR_CMP_CNTL_DIS);
973 OUT_RING(dev_priv->back_pitch_offset);
974 OUT_RING(clear->clear_color);
976 OUT_RING((x << 16) | y);
977 OUT_RING((w << 16) | h);
985 /* no docs available, based on reverse engineering by Stephane Marchesin */
986 if ((flags & (RADEON_DEPTH | RADEON_STENCIL))
987 && (flags & RADEON_CLEAR_FASTZ)) {
990 int depthpixperline =
991 dev_priv->depth_fmt ==
992 RADEON_DEPTH_FORMAT_16BIT_INT_Z ? (dev_priv->depth_pitch /
998 u32 tempRB3D_DEPTHCLEARVALUE = clear->clear_depth |
999 ((clear->depth_mask & 0xff) << 24);
1001 /* Make sure we restore the 3D state next time.
1002 * we haven't touched any "normal" state - still need this?
1004 sarea_priv->ctx_owner = 0;
1006 if ((dev_priv->flags & RADEON_HAS_HIERZ)
1007 && (flags & RADEON_USE_HIERZ)) {
1008 /* FIXME : reverse engineer that for Rx00 cards */
1009 /* FIXME : the mask supposedly contains low-res z values. So can't set
1010 just to the max (0xff? or actually 0x3fff?), need to take z clear
1011 value into account? */
1012 /* pattern seems to work for r100, though get slight
1013 rendering errors with glxgears. If hierz is not enabled for r100,
1014 only 4 bits which indicate clear (15,16,31,32, all zero) matter, the
1015 other ones are ignored, and the same clear mask can be used. That's
1016 very different behaviour than R200 which needs different clear mask
1017 and different number of tiles to clear if hierz is enabled or not !?!
1019 clearmask = (0xff << 22) | (0xff << 6) | 0x003f003f;
1021 /* clear mask : chooses the clearing pattern.
1022 rv250: could be used to clear only parts of macrotiles
1023 (but that would get really complicated...)?
1024 bit 0 and 1 (either or both of them ?!?!) are used to
1025 not clear tile (or maybe one of the bits indicates if the tile is
1026 compressed or not), bit 2 and 3 to not clear tile 1,...,.
1027 Pattern is as follows:
1028 | 0,1 | 4,5 | 8,9 |12,13|16,17|20,21|24,25|28,29|
1029 bits -------------------------------------------------
1030 | 2,3 | 6,7 |10,11|14,15|18,19|22,23|26,27|30,31|
1031 rv100: clearmask covers 2x8 4x1 tiles, but one clear still
1032 covers 256 pixels ?!?
1038 RADEON_WAIT_UNTIL_2D_IDLE();
1039 OUT_RING_REG(RADEON_RB3D_DEPTHCLEARVALUE,
1040 tempRB3D_DEPTHCLEARVALUE);
1041 /* what offset is this exactly ? */
1042 OUT_RING_REG(RADEON_RB3D_ZMASKOFFSET, 0);
1043 /* need ctlstat, otherwise get some strange black flickering */
1044 OUT_RING_REG(RADEON_RB3D_ZCACHE_CTLSTAT,
1045 RADEON_RB3D_ZC_FLUSH_ALL);
1048 for (i = 0; i < nbox; i++) {
1049 int tileoffset, nrtilesx, nrtilesy, j;
1050 /* it looks like r200 needs rv-style clears, at least if hierz is not enabled? */
1051 if ((dev_priv->flags & RADEON_HAS_HIERZ)
1052 && !(dev_priv->microcode_version == UCODE_R200)) {
1053 /* FIXME : figure this out for r200 (when hierz is enabled). Or
1054 maybe r200 actually doesn't need to put the low-res z value into
1055 the tile cache like r100, but just needs to clear the hi-level z-buffer?
1056 Works for R100, both with hierz and without.
1057 R100 seems to operate on 2x1 8x8 tiles, but...
1058 odd: offset/nrtiles need to be 64 pix (4 block) aligned? Potentially
1059 problematic with resolutions which are not 64 pix aligned? */
1061 ((pbox[i].y1 >> 3) * depthpixperline +
1064 ((pbox[i].x2 & ~63) -
1065 (pbox[i].x1 & ~63)) >> 4;
1067 (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3);
1068 for (j = 0; j <= nrtilesy; j++) {
1071 (RADEON_3D_CLEAR_ZMASK, 2));
1073 OUT_RING(tileoffset * 8);
1074 /* the number of tiles to clear */
1075 OUT_RING(nrtilesx + 4);
1076 /* clear mask : chooses the clearing pattern. */
1077 OUT_RING(clearmask);
1079 tileoffset += depthpixperline >> 6;
1081 } else if (dev_priv->microcode_version == UCODE_R200) {
1082 /* works for rv250. */
1083 /* find first macro tile (8x2 4x4 z-pixels on rv250) */
1085 ((pbox[i].y1 >> 3) * depthpixperline +
1088 (pbox[i].x2 >> 5) - (pbox[i].x1 >> 5);
1090 (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3);
1091 for (j = 0; j <= nrtilesy; j++) {
1094 (RADEON_3D_CLEAR_ZMASK, 2));
1096 /* judging by the first tile offset needed, could possibly
1097 directly address/clear 4x4 tiles instead of 8x2 * 4x4
1098 macro tiles, though would still need clear mask for
1099 right/bottom if truly 4x4 granularity is desired ? */
1100 OUT_RING(tileoffset * 16);
1101 /* the number of tiles to clear */
1102 OUT_RING(nrtilesx + 1);
1103 /* clear mask : chooses the clearing pattern. */
1104 OUT_RING(clearmask);
1106 tileoffset += depthpixperline >> 5;
1108 } else { /* rv 100 */
1109 /* rv100 might not need 64 pix alignment, who knows */
1110 /* offsets are, hmm, weird */
1112 ((pbox[i].y1 >> 4) * depthpixperline +
1115 ((pbox[i].x2 & ~63) -
1116 (pbox[i].x1 & ~63)) >> 4;
1118 (pbox[i].y2 >> 4) - (pbox[i].y1 >> 4);
1119 for (j = 0; j <= nrtilesy; j++) {
1122 (RADEON_3D_CLEAR_ZMASK, 2));
1123 OUT_RING(tileoffset * 128);
1124 /* the number of tiles to clear */
1125 OUT_RING(nrtilesx + 4);
1126 /* clear mask : chooses the clearing pattern. */
1127 OUT_RING(clearmask);
1129 tileoffset += depthpixperline >> 6;
1134 /* TODO don't always clear all hi-level z tiles */
1135 if ((dev_priv->flags & RADEON_HAS_HIERZ)
1136 && (dev_priv->microcode_version == UCODE_R200)
1137 && (flags & RADEON_USE_HIERZ))
1138 /* r100 and cards without hierarchical z-buffer have no high-level z-buffer */
1139 /* FIXME : the mask supposedly contains low-res z values. So can't set
1140 just to the max (0xff? or actually 0x3fff?), need to take z clear
1141 value into account? */
1144 OUT_RING(CP_PACKET3(RADEON_3D_CLEAR_HIZ, 2));
1145 OUT_RING(0x0); /* First tile */
1147 OUT_RING((0xff << 22) | (0xff << 6) | 0x003f003f);
1152 /* We have to clear the depth and/or stencil buffers by
1153 * rendering a quad into just those buffers. Thus, we have to
1154 * make sure the 3D engine is configured correctly.
1156 else if ((dev_priv->microcode_version == UCODE_R200) &&
1157 (flags & (RADEON_DEPTH | RADEON_STENCIL))) {
1162 int tempRB3D_ZSTENCILCNTL;
1163 int tempRB3D_STENCILREFMASK;
1164 int tempRB3D_PLANEMASK;
1166 int tempSE_VTE_CNTL;
1167 int tempSE_VTX_FMT_0;
1168 int tempSE_VTX_FMT_1;
1169 int tempSE_VAP_CNTL;
1170 int tempRE_AUX_SCISSOR_CNTL;
1175 tempRB3D_CNTL = depth_clear->rb3d_cntl;
1177 tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl;
1178 tempRB3D_STENCILREFMASK = 0x0;
1180 tempSE_CNTL = depth_clear->se_cntl;
1184 tempSE_VAP_CNTL = ( /* SE_VAP_CNTL__FORCE_W_TO_ONE_MASK | */
1186 SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT));
1188 tempRB3D_PLANEMASK = 0x0;
1190 tempRE_AUX_SCISSOR_CNTL = 0x0;
1193 SE_VTE_CNTL__VTX_XY_FMT_MASK | SE_VTE_CNTL__VTX_Z_FMT_MASK;
1195 /* Vertex format (X, Y, Z, W) */
1197 SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK |
1198 SE_VTX_FMT_0__VTX_W0_PRESENT_MASK;
1199 tempSE_VTX_FMT_1 = 0x0;
1202 * Depth buffer specific enables
1204 if (flags & RADEON_DEPTH) {
1205 /* Enable depth buffer */
1206 tempRB3D_CNTL |= RADEON_Z_ENABLE;
1208 /* Disable depth buffer */
1209 tempRB3D_CNTL &= ~RADEON_Z_ENABLE;
1213 * Stencil buffer specific enables
1215 if (flags & RADEON_STENCIL) {
1216 tempRB3D_CNTL |= RADEON_STENCIL_ENABLE;
1217 tempRB3D_STENCILREFMASK = clear->depth_mask;
1219 tempRB3D_CNTL &= ~RADEON_STENCIL_ENABLE;
1220 tempRB3D_STENCILREFMASK = 0x00000000;
1223 if (flags & RADEON_USE_COMP_ZBUF) {
1224 tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE |
1225 RADEON_Z_DECOMPRESSION_ENABLE;
1227 if (flags & RADEON_USE_HIERZ) {
1228 tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE;
1232 RADEON_WAIT_UNTIL_2D_IDLE();
1234 OUT_RING_REG(RADEON_PP_CNTL, tempPP_CNTL);
1235 OUT_RING_REG(R200_RE_CNTL, tempRE_CNTL);
1236 OUT_RING_REG(RADEON_RB3D_CNTL, tempRB3D_CNTL);
1237 OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL);
1238 OUT_RING_REG(RADEON_RB3D_STENCILREFMASK,
1239 tempRB3D_STENCILREFMASK);
1240 OUT_RING_REG(RADEON_RB3D_PLANEMASK, tempRB3D_PLANEMASK);
1241 OUT_RING_REG(RADEON_SE_CNTL, tempSE_CNTL);
1242 OUT_RING_REG(R200_SE_VTE_CNTL, tempSE_VTE_CNTL);
1243 OUT_RING_REG(R200_SE_VTX_FMT_0, tempSE_VTX_FMT_0);
1244 OUT_RING_REG(R200_SE_VTX_FMT_1, tempSE_VTX_FMT_1);
1245 OUT_RING_REG(R200_SE_VAP_CNTL, tempSE_VAP_CNTL);
1246 OUT_RING_REG(R200_RE_AUX_SCISSOR_CNTL, tempRE_AUX_SCISSOR_CNTL);
1249 /* Make sure we restore the 3D state next time.
1251 sarea_priv->ctx_owner = 0;
1253 for (i = 0; i < nbox; i++) {
1255 /* Funny that this should be required --
1258 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1261 OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 12));
1262 OUT_RING((RADEON_PRIM_TYPE_RECT_LIST |
1263 RADEON_PRIM_WALK_RING |
1264 (3 << RADEON_NUM_VERTICES_SHIFT)));
1265 OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
1266 OUT_RING(depth_boxes[i].ui[CLEAR_Y1]);
1267 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1268 OUT_RING(0x3f800000);
1269 OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
1270 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
1271 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1272 OUT_RING(0x3f800000);
1273 OUT_RING(depth_boxes[i].ui[CLEAR_X2]);
1274 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
1275 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1276 OUT_RING(0x3f800000);
1279 } else if ((flags & (RADEON_DEPTH | RADEON_STENCIL))) {
1281 int tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl;
1283 rb3d_cntl = depth_clear->rb3d_cntl;
1285 if (flags & RADEON_DEPTH) {
1286 rb3d_cntl |= RADEON_Z_ENABLE;
1288 rb3d_cntl &= ~RADEON_Z_ENABLE;
1291 if (flags & RADEON_STENCIL) {
1292 rb3d_cntl |= RADEON_STENCIL_ENABLE;
1293 rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */
1295 rb3d_cntl &= ~RADEON_STENCIL_ENABLE;
1296 rb3d_stencilrefmask = 0x00000000;
1299 if (flags & RADEON_USE_COMP_ZBUF) {
1300 tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE |
1301 RADEON_Z_DECOMPRESSION_ENABLE;
1303 if (flags & RADEON_USE_HIERZ) {
1304 tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE;
1308 RADEON_WAIT_UNTIL_2D_IDLE();
1310 OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 1));
1311 OUT_RING(0x00000000);
1312 OUT_RING(rb3d_cntl);
1314 OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL);
1315 OUT_RING_REG(RADEON_RB3D_STENCILREFMASK, rb3d_stencilrefmask);
1316 OUT_RING_REG(RADEON_RB3D_PLANEMASK, 0x00000000);
1317 OUT_RING_REG(RADEON_SE_CNTL, depth_clear->se_cntl);
1320 /* Make sure we restore the 3D state next time.
1322 sarea_priv->ctx_owner = 0;
1324 for (i = 0; i < nbox; i++) {
1326 /* Funny that this should be required --
1329 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1333 OUT_RING(CP_PACKET3(RADEON_3D_DRAW_IMMD, 13));
1334 OUT_RING(RADEON_VTX_Z_PRESENT |
1335 RADEON_VTX_PKCOLOR_PRESENT);
1336 OUT_RING((RADEON_PRIM_TYPE_RECT_LIST |
1337 RADEON_PRIM_WALK_RING |
1338 RADEON_MAOS_ENABLE |
1339 RADEON_VTX_FMT_RADEON_MODE |
1340 (3 << RADEON_NUM_VERTICES_SHIFT)));
1342 OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
1343 OUT_RING(depth_boxes[i].ui[CLEAR_Y1]);
1344 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1347 OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
1348 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
1349 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1352 OUT_RING(depth_boxes[i].ui[CLEAR_X2]);
1353 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
1354 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1361 /* Increment the clear counter. The client-side 3D driver must
1362 * wait on this value before performing the clear ioctl. We
1363 * need this because the card's so damned fast...
1365 sarea_priv->last_clear++;
1369 RADEON_CLEAR_AGE(sarea_priv->last_clear);
1370 RADEON_WAIT_UNTIL_IDLE();
1375 static void radeon_cp_dispatch_swap(struct drm_device *dev, struct drm_master *master)
1377 drm_radeon_private_t *dev_priv = dev->dev_private;
1378 struct drm_radeon_master_private *master_priv = master->driver_priv;
1379 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
1380 int nbox = sarea_priv->nbox;
1381 struct drm_clip_rect *pbox = sarea_priv->boxes;
1386 /* Do some trivial performance monitoring...
1388 if (dev_priv->do_boxes)
1389 radeon_cp_performance_boxes(dev_priv, master_priv);
1391 /* Wait for the 3D stream to idle before dispatching the bitblt.
1392 * This will prevent data corruption between the two streams.
1396 RADEON_WAIT_UNTIL_3D_IDLE();
1400 for (i = 0; i < nbox; i++) {
1403 int w = pbox[i].x2 - x;
1404 int h = pbox[i].y2 - y;
1406 DRM_DEBUG("%d,%d-%d,%d\n", x, y, w, h);
1410 OUT_RING(CP_PACKET0(RADEON_DP_GUI_MASTER_CNTL, 0));
1411 OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
1412 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
1413 RADEON_GMC_BRUSH_NONE |
1414 (dev_priv->color_fmt << 8) |
1415 RADEON_GMC_SRC_DATATYPE_COLOR |
1417 RADEON_DP_SRC_SOURCE_MEMORY |
1418 RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
1420 /* Make this work even if front & back are flipped:
1422 OUT_RING(CP_PACKET0(RADEON_SRC_PITCH_OFFSET, 1));
1423 if (sarea_priv->pfCurrentPage == 0) {
1424 OUT_RING(dev_priv->back_pitch_offset);
1425 OUT_RING(dev_priv->front_pitch_offset);
1427 OUT_RING(dev_priv->front_pitch_offset);
1428 OUT_RING(dev_priv->back_pitch_offset);
1431 OUT_RING(CP_PACKET0(RADEON_SRC_X_Y, 2));
1432 OUT_RING((x << 16) | y);
1433 OUT_RING((x << 16) | y);
1434 OUT_RING((w << 16) | h);
1439 /* Increment the frame counter. The client-side 3D driver must
1440 * throttle the framerate by waiting for this value before
1441 * performing the swapbuffer ioctl.
1443 sarea_priv->last_frame++;
1447 RADEON_FRAME_AGE(sarea_priv->last_frame);
1448 RADEON_WAIT_UNTIL_2D_IDLE();
1453 void radeon_cp_dispatch_flip(struct drm_device *dev, struct drm_master *master)
1455 drm_radeon_private_t *dev_priv = dev->dev_private;
1456 struct drm_radeon_master_private *master_priv = master->driver_priv;
1457 struct drm_sarea *sarea = (struct drm_sarea *)master_priv->sarea->handle;
1458 int offset = (master_priv->sarea_priv->pfCurrentPage == 1)
1459 ? dev_priv->front_offset : dev_priv->back_offset;
1461 DRM_DEBUG("pfCurrentPage=%d\n",
1462 master_priv->sarea_priv->pfCurrentPage);
1464 /* Do some trivial performance monitoring...
1466 if (dev_priv->do_boxes) {
1467 dev_priv->stats.boxes |= RADEON_BOX_FLIP;
1468 radeon_cp_performance_boxes(dev_priv, master_priv);
1471 /* Update the frame offsets for both CRTCs
1475 RADEON_WAIT_UNTIL_3D_IDLE();
1476 OUT_RING_REG(RADEON_CRTC_OFFSET,
1477 ((sarea->frame.y * dev_priv->front_pitch +
1478 sarea->frame.x * (dev_priv->color_fmt - 2)) & ~7)
1480 OUT_RING_REG(RADEON_CRTC2_OFFSET, master_priv->sarea_priv->crtc2_base
1485 /* Increment the frame counter. The client-side 3D driver must
1486 * throttle the framerate by waiting for this value before
1487 * performing the swapbuffer ioctl.
1489 master_priv->sarea_priv->last_frame++;
1490 master_priv->sarea_priv->pfCurrentPage =
1491 1 - master_priv->sarea_priv->pfCurrentPage;
1495 RADEON_FRAME_AGE(master_priv->sarea_priv->last_frame);
1500 static int bad_prim_vertex_nr(int primitive, int nr)
1502 switch (primitive & RADEON_PRIM_TYPE_MASK) {
1503 case RADEON_PRIM_TYPE_NONE:
1504 case RADEON_PRIM_TYPE_POINT:
1506 case RADEON_PRIM_TYPE_LINE:
1507 return (nr & 1) || nr == 0;
1508 case RADEON_PRIM_TYPE_LINE_STRIP:
1510 case RADEON_PRIM_TYPE_TRI_LIST:
1511 case RADEON_PRIM_TYPE_3VRT_POINT_LIST:
1512 case RADEON_PRIM_TYPE_3VRT_LINE_LIST:
1513 case RADEON_PRIM_TYPE_RECT_LIST:
1514 return nr % 3 || nr == 0;
1515 case RADEON_PRIM_TYPE_TRI_FAN:
1516 case RADEON_PRIM_TYPE_TRI_STRIP:
1525 unsigned int finish;
1527 unsigned int numverts;
1528 unsigned int offset;
1529 unsigned int vc_format;
1530 } drm_radeon_tcl_prim_t;
1532 static void radeon_cp_dispatch_vertex(struct drm_device * dev,
1533 struct drm_file *file_priv,
1534 struct drm_buf * buf,
1535 drm_radeon_tcl_prim_t * prim)
1537 drm_radeon_private_t *dev_priv = dev->dev_private;
1538 struct drm_radeon_master_private *master_priv = file_priv->masterp->driver_priv;
1539 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
1540 int offset = dev_priv->gart_buffers_offset + buf->offset + prim->start;
1541 int numverts = (int)prim->numverts;
1542 int nbox = sarea_priv->nbox;
1546 DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d %d verts\n",
1548 prim->vc_format, prim->start, prim->finish, prim->numverts);
1550 if (bad_prim_vertex_nr(prim->prim, prim->numverts)) {
1551 DRM_ERROR("bad prim %x numverts %d\n",
1552 prim->prim, prim->numverts);
1557 /* Emit the next cliprect */
1559 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1562 /* Emit the vertex buffer rendering commands */
1565 OUT_RING(CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, 3));
1568 OUT_RING(prim->vc_format);
1569 OUT_RING(prim->prim | RADEON_PRIM_WALK_LIST |
1570 RADEON_COLOR_ORDER_RGBA |
1571 RADEON_VTX_FMT_RADEON_MODE |
1572 (numverts << RADEON_NUM_VERTICES_SHIFT));
1580 void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf)
1582 drm_radeon_private_t *dev_priv = dev->dev_private;
1583 struct drm_radeon_master_private *master_priv = master->driver_priv;
1584 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1587 buf_priv->age = ++master_priv->sarea_priv->last_dispatch;
1589 /* Emit the vertex buffer age */
1590 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1592 R600_DISPATCH_AGE(buf_priv->age);
1596 RADEON_DISPATCH_AGE(buf_priv->age);
1604 static void radeon_cp_dispatch_indirect(struct drm_device * dev,
1605 struct drm_buf * buf, int start, int end)
1607 drm_radeon_private_t *dev_priv = dev->dev_private;
1609 DRM_DEBUG("buf=%d s=0x%x e=0x%x\n", buf->idx, start, end);
1612 int offset = (dev_priv->gart_buffers_offset
1613 + buf->offset + start);
1614 int dwords = (end - start + 3) / sizeof(u32);
1616 /* Indirect buffer data must be an even number of
1617 * dwords, so if we've been given an odd number we must
1618 * pad the data with a Type-2 CP packet.
1622 ((char *)dev->agp_buffer_map->handle
1623 + buf->offset + start);
1624 data[dwords++] = RADEON_CP_PACKET2;
1627 /* Fire off the indirect buffer */
1630 OUT_RING(CP_PACKET0(RADEON_CP_IB_BASE, 1));
1638 static void radeon_cp_dispatch_indices(struct drm_device *dev,
1639 struct drm_master *master,
1640 struct drm_buf * elt_buf,
1641 drm_radeon_tcl_prim_t * prim)
1643 drm_radeon_private_t *dev_priv = dev->dev_private;
1644 struct drm_radeon_master_private *master_priv = master->driver_priv;
1645 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
1646 int offset = dev_priv->gart_buffers_offset + prim->offset;
1650 int start = prim->start + RADEON_INDEX_PRIM_OFFSET;
1651 int count = (prim->finish - start) / sizeof(u16);
1652 int nbox = sarea_priv->nbox;
1654 DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n",
1657 prim->start, prim->finish, prim->offset, prim->numverts);
1659 if (bad_prim_vertex_nr(prim->prim, count)) {
1660 DRM_ERROR("bad prim %x count %d\n", prim->prim, count);
1664 if (start >= prim->finish || (prim->start & 0x7)) {
1665 DRM_ERROR("buffer prim %d\n", prim->prim);
1669 dwords = (prim->finish - prim->start + 3) / sizeof(u32);
1671 data = (u32 *) ((char *)dev->agp_buffer_map->handle +
1672 elt_buf->offset + prim->start);
1674 data[0] = CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, dwords - 2);
1676 data[2] = prim->numverts;
1677 data[3] = prim->vc_format;
1678 data[4] = (prim->prim |
1679 RADEON_PRIM_WALK_IND |
1680 RADEON_COLOR_ORDER_RGBA |
1681 RADEON_VTX_FMT_RADEON_MODE |
1682 (count << RADEON_NUM_VERTICES_SHIFT));
1686 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1688 radeon_cp_dispatch_indirect(dev, elt_buf,
1689 prim->start, prim->finish);
1696 #define RADEON_MAX_TEXTURE_SIZE RADEON_BUFFER_SIZE
1698 static int radeon_cp_dispatch_texture(struct drm_device * dev,
1699 struct drm_file *file_priv,
1700 drm_radeon_texture_t * tex,
1701 drm_radeon_tex_image_t * image)
1703 drm_radeon_private_t *dev_priv = dev->dev_private;
1704 struct drm_buf *buf;
1707 const u8 __user *data;
1708 int size, dwords, tex_width, blit_width, spitch;
1711 u32 texpitch, microtile;
1712 u32 offset, byte_offset;
1715 if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex->offset)) {
1716 DRM_ERROR("Invalid destination offset\n");
1720 dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD;
1722 /* Flush the pixel cache. This ensures no pixel data gets mixed
1723 * up with the texture data from the host data blit, otherwise
1724 * part of the texture image may be corrupted.
1727 RADEON_FLUSH_CACHE();
1728 RADEON_WAIT_UNTIL_IDLE();
1731 /* The compiler won't optimize away a division by a variable,
1732 * even if the only legal values are powers of two. Thus, we'll
1733 * use a shift instead.
1735 switch (tex->format) {
1736 case RADEON_TXFORMAT_ARGB8888:
1737 case RADEON_TXFORMAT_RGBA8888:
1738 format = RADEON_COLOR_FORMAT_ARGB8888;
1739 tex_width = tex->width * 4;
1740 blit_width = image->width * 4;
1742 case RADEON_TXFORMAT_AI88:
1743 case RADEON_TXFORMAT_ARGB1555:
1744 case RADEON_TXFORMAT_RGB565:
1745 case RADEON_TXFORMAT_ARGB4444:
1746 case RADEON_TXFORMAT_VYUY422:
1747 case RADEON_TXFORMAT_YVYU422:
1748 format = RADEON_COLOR_FORMAT_RGB565;
1749 tex_width = tex->width * 2;
1750 blit_width = image->width * 2;
1752 case RADEON_TXFORMAT_I8:
1753 case RADEON_TXFORMAT_RGB332:
1754 format = RADEON_COLOR_FORMAT_CI8;
1755 tex_width = tex->width * 1;
1756 blit_width = image->width * 1;
1759 DRM_ERROR("invalid texture format %d\n", tex->format);
1762 spitch = blit_width >> 6;
1763 if (spitch == 0 && image->height > 1)
1766 texpitch = tex->pitch;
1767 if ((texpitch << 22) & RADEON_DST_TILE_MICRO) {
1769 if (tex_width < 64) {
1770 texpitch &= ~(RADEON_DST_TILE_MICRO >> 22);
1771 /* we got tiled coordinates, untile them */
1777 /* this might fail for zero-sized uploads - are those illegal? */
1778 if (!radeon_check_offset(dev_priv, tex->offset + image->height *
1780 DRM_ERROR("Invalid final destination offset\n");
1784 DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width);
1787 DRM_DEBUG("tex: ofs=0x%x p=%d f=%d x=%u y=%u w=%u h=%u\n",
1788 tex->offset >> 10, tex->pitch, tex->format,
1789 image->x, image->y, image->width, image->height);
1791 /* Make a copy of some parameters in case we have to
1792 * update them for a multi-pass texture blit.
1794 height = image->height;
1795 data = (const u8 __user *)image->data;
1797 size = height * blit_width;
1799 if (size > RADEON_MAX_TEXTURE_SIZE) {
1800 height = RADEON_MAX_TEXTURE_SIZE / blit_width;
1801 size = height * blit_width;
1802 } else if (size < 4 && size > 0) {
1804 } else if (size == 0) {
1808 buf = radeon_freelist_get(dev);
1810 radeon_do_cp_idle(dev_priv);
1811 buf = radeon_freelist_get(dev);
1814 DRM_DEBUG("EAGAIN\n");
1815 if (copy_to_user(tex->image, image, sizeof(*image)))
1820 /* Dispatch the indirect buffer.
1823 (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
1826 #define RADEON_COPY_MT(_buf, _data, _width) \
1828 if (copy_from_user(_buf, _data, (_width))) {\
1829 DRM_ERROR("EFAULT on pad, %d bytes\n", (_width)); \
1835 /* texture micro tiling in use, minimum texture width is thus 16 bytes.
1836 however, we cannot use blitter directly for texture width < 64 bytes,
1837 since minimum tex pitch is 64 bytes and we need this to match
1838 the texture width, otherwise the blitter will tile it wrong.
1839 Thus, tiling manually in this case. Additionally, need to special
1840 case tex height = 1, since our actual image will have height 2
1841 and we need to ensure we don't read beyond the texture size
1843 if (tex->height == 1) {
1844 if (tex_width >= 64 || tex_width <= 16) {
1845 RADEON_COPY_MT(buffer, data,
1846 (int)(tex_width * sizeof(u32)));
1847 } else if (tex_width == 32) {
1848 RADEON_COPY_MT(buffer, data, 16);
1849 RADEON_COPY_MT(buffer + 8,
1852 } else if (tex_width >= 64 || tex_width == 16) {
1853 RADEON_COPY_MT(buffer, data,
1854 (int)(dwords * sizeof(u32)));
1855 } else if (tex_width < 16) {
1856 for (i = 0; i < tex->height; i++) {
1857 RADEON_COPY_MT(buffer, data, tex_width);
1861 } else if (tex_width == 32) {
1862 /* TODO: make sure this works when not fitting in one buffer
1863 (i.e. 32bytes x 2048...) */
1864 for (i = 0; i < tex->height; i += 2) {
1865 RADEON_COPY_MT(buffer, data, 16);
1867 RADEON_COPY_MT(buffer + 8, data, 16);
1869 RADEON_COPY_MT(buffer + 4, data, 16);
1871 RADEON_COPY_MT(buffer + 12, data, 16);
1877 if (tex_width >= 32) {
1878 /* Texture image width is larger than the minimum, so we
1879 * can upload it directly.
1881 RADEON_COPY_MT(buffer, data,
1882 (int)(dwords * sizeof(u32)));
1884 /* Texture image width is less than the minimum, so we
1885 * need to pad out each image scanline to the minimum
1888 for (i = 0; i < tex->height; i++) {
1889 RADEON_COPY_MT(buffer, data, tex_width);
1896 #undef RADEON_COPY_MT
1897 byte_offset = (image->y & ~2047) * blit_width;
1898 buf->file_priv = file_priv;
1900 offset = dev_priv->gart_buffers_offset + buf->offset;
1902 OUT_RING(CP_PACKET3(RADEON_CNTL_BITBLT_MULTI, 5));
1903 OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
1904 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
1905 RADEON_GMC_BRUSH_NONE |
1907 RADEON_GMC_SRC_DATATYPE_COLOR |
1909 RADEON_DP_SRC_SOURCE_MEMORY |
1910 RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
1911 OUT_RING((spitch << 22) | (offset >> 10));
1912 OUT_RING((texpitch << 22) | ((tex->offset >> 10) + (byte_offset >> 10)));
1914 OUT_RING((image->x << 16) | (image->y % 2048));
1915 OUT_RING((image->width << 16) | height);
1916 RADEON_WAIT_UNTIL_2D_IDLE();
1920 radeon_cp_discard_buffer(dev, file_priv->masterp, buf);
1922 /* Update the input parameters for next time */
1924 image->height -= height;
1925 image->data = (const u8 __user *)image->data + size;
1926 } while (image->height > 0);
1928 /* Flush the pixel cache after the blit completes. This ensures
1929 * the texture data is written out to memory before rendering
1933 RADEON_FLUSH_CACHE();
1934 RADEON_WAIT_UNTIL_2D_IDLE();
1941 static void radeon_cp_dispatch_stipple(struct drm_device * dev, u32 * stipple)
1943 drm_radeon_private_t *dev_priv = dev->dev_private;
1950 OUT_RING(CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0));
1951 OUT_RING(0x00000000);
1953 OUT_RING(CP_PACKET0_TABLE(RADEON_RE_STIPPLE_DATA, 31));
1954 for (i = 0; i < 32; i++) {
1955 OUT_RING(stipple[i]);
1961 static void radeon_apply_surface_regs(int surf_index,
1962 drm_radeon_private_t *dev_priv)
1964 if (!dev_priv->mmio)
1967 radeon_do_cp_idle(dev_priv);
1969 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * surf_index,
1970 dev_priv->surfaces[surf_index].flags);
1971 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * surf_index,
1972 dev_priv->surfaces[surf_index].lower);
1973 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * surf_index,
1974 dev_priv->surfaces[surf_index].upper);
1977 /* Allocates a virtual surface
1978 * doesn't always allocate a real surface, will stretch an existing
1979 * surface when possible.
1981 * Note that refcount can be at most 2, since during a free refcount=3
1982 * might mean we have to allocate a new surface which might not always
1984 * For example : we allocate three contiguous surfaces ABC. If B is
1985 * freed, we suddenly need two surfaces to store A and C, which might
1986 * not always be available.
1988 static int alloc_surface(drm_radeon_surface_alloc_t *new,
1989 drm_radeon_private_t *dev_priv,
1990 struct drm_file *file_priv)
1992 struct radeon_virt_surface *s;
1994 int virt_surface_index;
1995 uint32_t new_upper, new_lower;
1997 new_lower = new->address;
1998 new_upper = new_lower + new->size - 1;
2001 if ((new_lower >= new_upper) || (new->flags == 0) || (new->size == 0) ||
2002 ((new_upper & RADEON_SURF_ADDRESS_FIXED_MASK) !=
2003 RADEON_SURF_ADDRESS_FIXED_MASK)
2004 || ((new_lower & RADEON_SURF_ADDRESS_FIXED_MASK) != 0))
2007 /* make sure there is no overlap with existing surfaces */
2008 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
2009 if ((dev_priv->surfaces[i].refcount != 0) &&
2010 (((new_lower >= dev_priv->surfaces[i].lower) &&
2011 (new_lower < dev_priv->surfaces[i].upper)) ||
2012 ((new_lower < dev_priv->surfaces[i].lower) &&
2013 (new_upper > dev_priv->surfaces[i].lower)))) {
2018 /* find a virtual surface */
2019 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++)
2020 if (dev_priv->virt_surfaces[i].file_priv == NULL)
2022 if (i == 2 * RADEON_MAX_SURFACES) {
2025 virt_surface_index = i;
2027 /* try to reuse an existing surface */
2028 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
2030 if ((dev_priv->surfaces[i].refcount == 1) &&
2031 (new->flags == dev_priv->surfaces[i].flags) &&
2032 (new_upper + 1 == dev_priv->surfaces[i].lower)) {
2033 s = &(dev_priv->virt_surfaces[virt_surface_index]);
2034 s->surface_index = i;
2035 s->lower = new_lower;
2036 s->upper = new_upper;
2037 s->flags = new->flags;
2038 s->file_priv = file_priv;
2039 dev_priv->surfaces[i].refcount++;
2040 dev_priv->surfaces[i].lower = s->lower;
2041 radeon_apply_surface_regs(s->surface_index, dev_priv);
2042 return virt_surface_index;
2046 if ((dev_priv->surfaces[i].refcount == 1) &&
2047 (new->flags == dev_priv->surfaces[i].flags) &&
2048 (new_lower == dev_priv->surfaces[i].upper + 1)) {
2049 s = &(dev_priv->virt_surfaces[virt_surface_index]);
2050 s->surface_index = i;
2051 s->lower = new_lower;
2052 s->upper = new_upper;
2053 s->flags = new->flags;
2054 s->file_priv = file_priv;
2055 dev_priv->surfaces[i].refcount++;
2056 dev_priv->surfaces[i].upper = s->upper;
2057 radeon_apply_surface_regs(s->surface_index, dev_priv);
2058 return virt_surface_index;
2062 /* okay, we need a new one */
2063 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
2064 if (dev_priv->surfaces[i].refcount == 0) {
2065 s = &(dev_priv->virt_surfaces[virt_surface_index]);
2066 s->surface_index = i;
2067 s->lower = new_lower;
2068 s->upper = new_upper;
2069 s->flags = new->flags;
2070 s->file_priv = file_priv;
2071 dev_priv->surfaces[i].refcount = 1;
2072 dev_priv->surfaces[i].lower = s->lower;
2073 dev_priv->surfaces[i].upper = s->upper;
2074 dev_priv->surfaces[i].flags = s->flags;
2075 radeon_apply_surface_regs(s->surface_index, dev_priv);
2076 return virt_surface_index;
2080 /* we didn't find anything */
2084 static int free_surface(struct drm_file *file_priv,
2085 drm_radeon_private_t * dev_priv,
2088 struct radeon_virt_surface *s;
2090 /* find the virtual surface */
2091 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) {
2092 s = &(dev_priv->virt_surfaces[i]);
2094 if ((lower == s->lower) && (file_priv == s->file_priv))
2096 if (dev_priv->surfaces[s->surface_index].
2098 dev_priv->surfaces[s->surface_index].
2101 if (dev_priv->surfaces[s->surface_index].
2103 dev_priv->surfaces[s->surface_index].
2106 dev_priv->surfaces[s->surface_index].refcount--;
2107 if (dev_priv->surfaces[s->surface_index].
2109 dev_priv->surfaces[s->surface_index].
2111 s->file_priv = NULL;
2112 radeon_apply_surface_regs(s->surface_index,
2121 static void radeon_surfaces_release(struct drm_file *file_priv,
2122 drm_radeon_private_t * dev_priv)
2125 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) {
2126 if (dev_priv->virt_surfaces[i].file_priv == file_priv)
2127 free_surface(file_priv, dev_priv,
2128 dev_priv->virt_surfaces[i].lower);
2132 /* ================================================================
2135 static int radeon_surface_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv)
2137 drm_radeon_private_t *dev_priv = dev->dev_private;
2138 drm_radeon_surface_alloc_t *alloc = data;
2140 if (alloc_surface(alloc, dev_priv, file_priv) == -1)
2146 static int radeon_surface_free(struct drm_device *dev, void *data, struct drm_file *file_priv)
2148 drm_radeon_private_t *dev_priv = dev->dev_private;
2149 drm_radeon_surface_free_t *memfree = data;
2151 if (free_surface(file_priv, dev_priv, memfree->address))
2157 static int radeon_cp_clear(struct drm_device *dev, void *data, struct drm_file *file_priv)
2159 drm_radeon_private_t *dev_priv = dev->dev_private;
2160 struct drm_radeon_master_private *master_priv = file_priv->masterp->driver_priv;
2161 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
2162 drm_radeon_clear_t *clear = data;
2163 drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
2166 LOCK_TEST_WITH_RETURN(dev, file_priv);
2168 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2170 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2171 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
2173 if (copy_from_user(&depth_boxes, clear->depth_boxes,
2174 sarea_priv->nbox * sizeof(depth_boxes[0])))
2177 radeon_cp_dispatch_clear(dev, file_priv->masterp, clear, depth_boxes);
2183 /* Not sure why this isn't set all the time:
2185 static int radeon_do_init_pageflip(struct drm_device *dev, struct drm_master *master)
2187 drm_radeon_private_t *dev_priv = dev->dev_private;
2188 struct drm_radeon_master_private *master_priv = master->driver_priv;
2194 RADEON_WAIT_UNTIL_3D_IDLE();
2195 OUT_RING(CP_PACKET0(RADEON_CRTC_OFFSET_CNTL, 0));
2196 OUT_RING(RADEON_READ(RADEON_CRTC_OFFSET_CNTL) |
2197 RADEON_CRTC_OFFSET_FLIP_CNTL);
2198 OUT_RING(CP_PACKET0(RADEON_CRTC2_OFFSET_CNTL, 0));
2199 OUT_RING(RADEON_READ(RADEON_CRTC2_OFFSET_CNTL) |
2200 RADEON_CRTC_OFFSET_FLIP_CNTL);
2203 dev_priv->page_flipping = 1;
2205 if (master_priv->sarea_priv->pfCurrentPage != 1)
2206 master_priv->sarea_priv->pfCurrentPage = 0;
2211 /* Swapping and flipping are different operations, need different ioctls.
2212 * They can & should be intermixed to support multiple 3d windows.
2214 static int radeon_cp_flip(struct drm_device *dev, void *data, struct drm_file *file_priv)
2216 drm_radeon_private_t *dev_priv = dev->dev_private;
2219 LOCK_TEST_WITH_RETURN(dev, file_priv);
2221 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2223 if (!dev_priv->page_flipping)
2224 radeon_do_init_pageflip(dev, file_priv->masterp);
2226 radeon_cp_dispatch_flip(dev, file_priv->masterp);
2232 static int radeon_cp_swap(struct drm_device *dev, void *data, struct drm_file *file_priv)
2234 drm_radeon_private_t *dev_priv = dev->dev_private;
2235 struct drm_radeon_master_private *master_priv = file_priv->masterp->driver_priv;
2236 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
2240 LOCK_TEST_WITH_RETURN(dev, file_priv);
2242 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2244 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2245 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
2247 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
2248 r600_cp_dispatch_swap(dev, file_priv);
2250 radeon_cp_dispatch_swap(dev, file_priv->masterp);
2251 sarea_priv->ctx_owner = 0;
2257 static int radeon_cp_vertex(struct drm_device *dev, void *data, struct drm_file *file_priv)
2259 drm_radeon_private_t *dev_priv = dev->dev_private;
2260 struct drm_radeon_master_private *master_priv = file_priv->masterp->driver_priv;
2261 drm_radeon_sarea_t *sarea_priv;
2262 struct drm_device_dma *dma = dev->dma;
2263 struct drm_buf *buf;
2264 drm_radeon_vertex_t *vertex = data;
2265 drm_radeon_tcl_prim_t prim;
2267 LOCK_TEST_WITH_RETURN(dev, file_priv);
2269 sarea_priv = master_priv->sarea_priv;
2271 DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n",
2272 DRM_CURRENTPID, vertex->idx, vertex->count, vertex->discard);
2274 if (vertex->idx < 0 || vertex->idx >= dma->buf_count) {
2275 DRM_ERROR("buffer index %d (of %d max)\n",
2276 vertex->idx, dma->buf_count - 1);
2279 if (vertex->prim < 0 || vertex->prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) {
2280 DRM_ERROR("buffer prim %d\n", vertex->prim);
2284 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2285 VB_AGE_TEST_WITH_RETURN(dev_priv);
2287 buf = dma->buflist[vertex->idx];
2289 if (buf->file_priv != file_priv) {
2290 DRM_ERROR("process %d using buffer owned by %p\n",
2291 DRM_CURRENTPID, buf->file_priv);
2295 DRM_ERROR("sending pending buffer %d\n", vertex->idx);
2299 /* Build up a prim_t record:
2301 if (vertex->count) {
2302 buf->used = vertex->count; /* not used? */
2304 if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
2305 if (radeon_emit_state(dev_priv, file_priv,
2306 &sarea_priv->context_state,
2307 sarea_priv->tex_state,
2308 sarea_priv->dirty)) {
2309 DRM_ERROR("radeon_emit_state failed\n");
2313 sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
2314 RADEON_UPLOAD_TEX1IMAGES |
2315 RADEON_UPLOAD_TEX2IMAGES |
2316 RADEON_REQUIRE_QUIESCENCE);
2320 prim.finish = vertex->count; /* unused */
2321 prim.prim = vertex->prim;
2322 prim.numverts = vertex->count;
2323 prim.vc_format = sarea_priv->vc_format;
2325 radeon_cp_dispatch_vertex(dev, file_priv, buf, &prim);
2328 if (vertex->discard) {
2329 radeon_cp_discard_buffer(dev, file_priv->masterp, buf);
2336 static int radeon_cp_indices(struct drm_device *dev, void *data, struct drm_file *file_priv)
2338 drm_radeon_private_t *dev_priv = dev->dev_private;
2339 struct drm_radeon_master_private *master_priv = file_priv->masterp->driver_priv;
2340 drm_radeon_sarea_t *sarea_priv;
2341 struct drm_device_dma *dma = dev->dma;
2342 struct drm_buf *buf;
2343 drm_radeon_indices_t *elts = data;
2344 drm_radeon_tcl_prim_t prim;
2347 LOCK_TEST_WITH_RETURN(dev, file_priv);
2349 sarea_priv = master_priv->sarea_priv;
2351 DRM_DEBUG("pid=%d index=%d start=%d end=%d discard=%d\n",
2352 DRM_CURRENTPID, elts->idx, elts->start, elts->end,
2355 if (elts->idx < 0 || elts->idx >= dma->buf_count) {
2356 DRM_ERROR("buffer index %d (of %d max)\n",
2357 elts->idx, dma->buf_count - 1);
2360 if (elts->prim < 0 || elts->prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) {
2361 DRM_ERROR("buffer prim %d\n", elts->prim);
2365 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2366 VB_AGE_TEST_WITH_RETURN(dev_priv);
2368 buf = dma->buflist[elts->idx];
2370 if (buf->file_priv != file_priv) {
2371 DRM_ERROR("process %d using buffer owned by %p\n",
2372 DRM_CURRENTPID, buf->file_priv);
2376 DRM_ERROR("sending pending buffer %d\n", elts->idx);
2380 count = (elts->end - elts->start) / sizeof(u16);
2381 elts->start -= RADEON_INDEX_PRIM_OFFSET;
2383 if (elts->start & 0x7) {
2384 DRM_ERROR("misaligned buffer 0x%x\n", elts->start);
2387 if (elts->start < buf->used) {
2388 DRM_ERROR("no header 0x%x - 0x%x\n", elts->start, buf->used);
2392 buf->used = elts->end;
2394 if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
2395 if (radeon_emit_state(dev_priv, file_priv,
2396 &sarea_priv->context_state,
2397 sarea_priv->tex_state,
2398 sarea_priv->dirty)) {
2399 DRM_ERROR("radeon_emit_state failed\n");
2403 sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
2404 RADEON_UPLOAD_TEX1IMAGES |
2405 RADEON_UPLOAD_TEX2IMAGES |
2406 RADEON_REQUIRE_QUIESCENCE);
2409 /* Build up a prim_t record:
2411 prim.start = elts->start;
2412 prim.finish = elts->end;
2413 prim.prim = elts->prim;
2414 prim.offset = 0; /* offset from start of dma buffers */
2415 prim.numverts = RADEON_MAX_VB_VERTS; /* duh */
2416 prim.vc_format = sarea_priv->vc_format;
2418 radeon_cp_dispatch_indices(dev, file_priv->masterp, buf, &prim);
2419 if (elts->discard) {
2420 radeon_cp_discard_buffer(dev, file_priv->masterp, buf);
2427 static int radeon_cp_texture(struct drm_device *dev, void *data, struct drm_file *file_priv)
2429 drm_radeon_private_t *dev_priv = dev->dev_private;
2430 drm_radeon_texture_t *tex = data;
2431 drm_radeon_tex_image_t image;
2434 LOCK_TEST_WITH_RETURN(dev, file_priv);
2436 if (tex->image == NULL) {
2437 DRM_ERROR("null texture image!\n");
2441 if (copy_from_user(&image,
2442 (drm_radeon_tex_image_t __user *) tex->image,
2446 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2447 VB_AGE_TEST_WITH_RETURN(dev_priv);
2449 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
2450 ret = r600_cp_dispatch_texture(dev, file_priv, tex, &image);
2452 ret = radeon_cp_dispatch_texture(dev, file_priv, tex, &image);
2457 static int radeon_cp_stipple(struct drm_device *dev, void *data, struct drm_file *file_priv)
2459 drm_radeon_private_t *dev_priv = dev->dev_private;
2460 drm_radeon_stipple_t *stipple = data;
2463 LOCK_TEST_WITH_RETURN(dev, file_priv);
2465 if (copy_from_user(&mask, stipple->mask, 32 * sizeof(u32)))
2468 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2470 radeon_cp_dispatch_stipple(dev, mask);
2476 static int radeon_cp_indirect(struct drm_device *dev, void *data, struct drm_file *file_priv)
2478 drm_radeon_private_t *dev_priv = dev->dev_private;
2479 struct drm_device_dma *dma = dev->dma;
2480 struct drm_buf *buf;
2481 drm_radeon_indirect_t *indirect = data;
2484 LOCK_TEST_WITH_RETURN(dev, file_priv);
2486 DRM_DEBUG("idx=%d s=%d e=%d d=%d\n",
2487 indirect->idx, indirect->start, indirect->end,
2490 if (indirect->idx < 0 || indirect->idx >= dma->buf_count) {
2491 DRM_ERROR("buffer index %d (of %d max)\n",
2492 indirect->idx, dma->buf_count - 1);
2496 buf = dma->buflist[indirect->idx];
2498 if (buf->file_priv != file_priv) {
2499 DRM_ERROR("process %d using buffer owned by %p\n",
2500 DRM_CURRENTPID, buf->file_priv);
2504 DRM_ERROR("sending pending buffer %d\n", indirect->idx);
2508 if (indirect->start < buf->used) {
2509 DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n",
2510 indirect->start, buf->used);
2514 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2515 VB_AGE_TEST_WITH_RETURN(dev_priv);
2517 buf->used = indirect->end;
2519 /* Dispatch the indirect buffer full of commands from the
2520 * X server. This is insecure and is thus only available to
2521 * privileged clients.
2523 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
2524 r600_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end);
2526 /* Wait for the 3D stream to idle before the indirect buffer
2527 * containing 2D acceleration commands is processed.
2530 RADEON_WAIT_UNTIL_3D_IDLE();
2532 radeon_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end);
2535 if (indirect->discard) {
2536 radeon_cp_discard_buffer(dev, file_priv->masterp, buf);
2543 static int radeon_cp_vertex2(struct drm_device *dev, void *data, struct drm_file *file_priv)
2545 drm_radeon_private_t *dev_priv = dev->dev_private;
2546 struct drm_radeon_master_private *master_priv = file_priv->masterp->driver_priv;
2547 drm_radeon_sarea_t *sarea_priv;
2548 struct drm_device_dma *dma = dev->dma;
2549 struct drm_buf *buf;
2550 drm_radeon_vertex2_t *vertex = data;
2552 unsigned char laststate;
2554 LOCK_TEST_WITH_RETURN(dev, file_priv);
2556 sarea_priv = master_priv->sarea_priv;
2558 DRM_DEBUG("pid=%d index=%d discard=%d\n",
2559 DRM_CURRENTPID, vertex->idx, vertex->discard);
2561 if (vertex->idx < 0 || vertex->idx >= dma->buf_count) {
2562 DRM_ERROR("buffer index %d (of %d max)\n",
2563 vertex->idx, dma->buf_count - 1);
2567 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2568 VB_AGE_TEST_WITH_RETURN(dev_priv);
2570 buf = dma->buflist[vertex->idx];
2572 if (buf->file_priv != file_priv) {
2573 DRM_ERROR("process %d using buffer owned by %p\n",
2574 DRM_CURRENTPID, buf->file_priv);
2579 DRM_ERROR("sending pending buffer %d\n", vertex->idx);
2583 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2586 for (laststate = 0xff, i = 0; i < vertex->nr_prims; i++) {
2587 drm_radeon_prim_t prim;
2588 drm_radeon_tcl_prim_t tclprim;
2590 if (copy_from_user(&prim, &vertex->prim[i], sizeof(prim)))
2593 if (prim.stateidx != laststate) {
2594 drm_radeon_state_t state;
2596 if (copy_from_user(&state,
2597 &vertex->state[prim.stateidx],
2601 if (radeon_emit_state2(dev_priv, file_priv, &state)) {
2602 DRM_ERROR("radeon_emit_state2 failed\n");
2606 laststate = prim.stateidx;
2609 tclprim.start = prim.start;
2610 tclprim.finish = prim.finish;
2611 tclprim.prim = prim.prim;
2612 tclprim.vc_format = prim.vc_format;
2614 if (prim.prim & RADEON_PRIM_WALK_IND) {
2615 tclprim.offset = prim.numverts * 64;
2616 tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */
2618 radeon_cp_dispatch_indices(dev, file_priv->masterp, buf, &tclprim);
2620 tclprim.numverts = prim.numverts;
2621 tclprim.offset = 0; /* not used */
2623 radeon_cp_dispatch_vertex(dev, file_priv, buf, &tclprim);
2626 if (sarea_priv->nbox == 1)
2627 sarea_priv->nbox = 0;
2630 if (vertex->discard) {
2631 radeon_cp_discard_buffer(dev, file_priv->masterp, buf);
2638 static int radeon_emit_packets(drm_radeon_private_t * dev_priv,
2639 struct drm_file *file_priv,
2640 drm_radeon_cmd_header_t header,
2641 drm_radeon_kcmd_buffer_t *cmdbuf)
2643 int id = (int)header.packet.packet_id;
2647 if (id >= RADEON_MAX_STATE_PACKETS)
2650 sz = packet[id].len;
2651 reg = packet[id].start;
2653 if (sz * sizeof(u32) > drm_buffer_unprocessed(cmdbuf->buffer)) {
2654 DRM_ERROR("Packet size provided larger than data provided\n");
2658 if (radeon_check_and_fixup_packets(dev_priv, file_priv, id,
2660 DRM_ERROR("Packet verification failed\n");
2665 OUT_RING(CP_PACKET0(reg, (sz - 1)));
2666 OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz);
2672 static __inline__ int radeon_emit_scalars(drm_radeon_private_t *dev_priv,
2673 drm_radeon_cmd_header_t header,
2674 drm_radeon_kcmd_buffer_t *cmdbuf)
2676 int sz = header.scalars.count;
2677 int start = header.scalars.offset;
2678 int stride = header.scalars.stride;
2682 OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0));
2683 OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
2684 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1));
2685 OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz);
2692 static __inline__ int radeon_emit_scalars2(drm_radeon_private_t *dev_priv,
2693 drm_radeon_cmd_header_t header,
2694 drm_radeon_kcmd_buffer_t *cmdbuf)
2696 int sz = header.scalars.count;
2697 int start = ((unsigned int)header.scalars.offset) + 0x100;
2698 int stride = header.scalars.stride;
2702 OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0));
2703 OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
2704 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1));
2705 OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz);
2710 static __inline__ int radeon_emit_vectors(drm_radeon_private_t *dev_priv,
2711 drm_radeon_cmd_header_t header,
2712 drm_radeon_kcmd_buffer_t *cmdbuf)
2714 int sz = header.vectors.count;
2715 int start = header.vectors.offset;
2716 int stride = header.vectors.stride;
2720 OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0);
2721 OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0));
2722 OUT_RING(start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT));
2723 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1)));
2724 OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz);
2730 static __inline__ int radeon_emit_veclinear(drm_radeon_private_t *dev_priv,
2731 drm_radeon_cmd_header_t header,
2732 drm_radeon_kcmd_buffer_t *cmdbuf)
2734 int sz = header.veclinear.count * 4;
2735 int start = header.veclinear.addr_lo | (header.veclinear.addr_hi << 8);
2740 if (sz * 4 > drm_buffer_unprocessed(cmdbuf->buffer))
2744 OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0);
2745 OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0));
2746 OUT_RING(start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT));
2747 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1)));
2748 OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz);
2754 static int radeon_emit_packet3(struct drm_device * dev,
2755 struct drm_file *file_priv,
2756 drm_radeon_kcmd_buffer_t *cmdbuf)
2758 drm_radeon_private_t *dev_priv = dev->dev_private;
2765 if ((ret = radeon_check_and_fixup_packet3(dev_priv, file_priv,
2767 DRM_ERROR("Packet verification failed\n");
2772 OUT_RING_DRM_BUFFER(cmdbuf->buffer, cmdsz);
2778 static int radeon_emit_packet3_cliprect(struct drm_device *dev,
2779 struct drm_file *file_priv,
2780 drm_radeon_kcmd_buffer_t *cmdbuf,
2783 drm_radeon_private_t *dev_priv = dev->dev_private;
2784 struct drm_clip_rect box;
2787 struct drm_clip_rect __user *boxes = cmdbuf->boxes;
2793 if ((ret = radeon_check_and_fixup_packet3(dev_priv, file_priv,
2795 DRM_ERROR("Packet verification failed\n");
2803 if (i < cmdbuf->nbox) {
2804 if (copy_from_user(&box, &boxes[i], sizeof(box)))
2806 /* FIXME The second and subsequent times round
2807 * this loop, send a WAIT_UNTIL_3D_IDLE before
2808 * calling emit_clip_rect(). This fixes a
2809 * lockup on fast machines when sending
2810 * several cliprects with a cmdbuf, as when
2811 * waving a 2D window over a 3D
2812 * window. Something in the commands from user
2813 * space seems to hang the card when they're
2814 * sent several times in a row. That would be
2815 * the correct place to fix it but this works
2816 * around it until I can figure that out - Tim
2820 RADEON_WAIT_UNTIL_3D_IDLE();
2823 radeon_emit_clip_rect(dev_priv, &box);
2827 OUT_RING_DRM_BUFFER(cmdbuf->buffer, cmdsz);
2830 } while (++i < cmdbuf->nbox);
2831 if (cmdbuf->nbox == 1)
2836 drm_buffer_advance(cmdbuf->buffer, cmdsz * 4);
2840 static int radeon_emit_wait(struct drm_device * dev, int flags)
2842 drm_radeon_private_t *dev_priv = dev->dev_private;
2845 DRM_DEBUG("%x\n", flags);
2847 case RADEON_WAIT_2D:
2849 RADEON_WAIT_UNTIL_2D_IDLE();
2852 case RADEON_WAIT_3D:
2854 RADEON_WAIT_UNTIL_3D_IDLE();
2857 case RADEON_WAIT_2D | RADEON_WAIT_3D:
2859 RADEON_WAIT_UNTIL_IDLE();
2869 static int radeon_cp_cmdbuf(struct drm_device *dev, void *data,
2870 struct drm_file *file_priv)
2872 drm_radeon_private_t *dev_priv = dev->dev_private;
2873 struct drm_device_dma *dma = dev->dma;
2874 struct drm_buf *buf = NULL;
2875 drm_radeon_cmd_header_t stack_header;
2877 drm_radeon_kcmd_buffer_t *cmdbuf = data;
2880 LOCK_TEST_WITH_RETURN(dev, file_priv);
2882 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2883 VB_AGE_TEST_WITH_RETURN(dev_priv);
2885 if (cmdbuf->bufsz > 64 * 1024 || cmdbuf->bufsz < 0) {
2889 /* Allocate an in-kernel area and copy in the cmdbuf. Do this to avoid
2890 * races between checking values and using those values in other code,
2891 * and simply to avoid a lot of function calls to copy in data.
2893 if (cmdbuf->bufsz != 0) {
2895 void __user *buffer = cmdbuf->buffer;
2896 rv = drm_buffer_alloc(&cmdbuf->buffer, cmdbuf->bufsz);
2899 rv = drm_buffer_copy_from_user(cmdbuf->buffer, buffer,
2902 drm_buffer_free(cmdbuf->buffer);
2908 orig_nbox = cmdbuf->nbox;
2910 if (dev_priv->microcode_version == UCODE_R300) {
2912 temp = r300_do_cp_cmdbuf(dev, file_priv, cmdbuf);
2914 drm_buffer_free(cmdbuf->buffer);
2919 /* microcode_version != r300 */
2920 while (drm_buffer_unprocessed(cmdbuf->buffer) >= sizeof(stack_header)) {
2922 drm_radeon_cmd_header_t *header;
2923 header = drm_buffer_read_object(cmdbuf->buffer,
2924 sizeof(stack_header), &stack_header);
2926 switch (header->header.cmd_type) {
2927 case RADEON_CMD_PACKET:
2928 DRM_DEBUG("RADEON_CMD_PACKET\n");
2929 if (radeon_emit_packets
2930 (dev_priv, file_priv, *header, cmdbuf)) {
2931 DRM_ERROR("radeon_emit_packets failed\n");
2936 case RADEON_CMD_SCALARS:
2937 DRM_DEBUG("RADEON_CMD_SCALARS\n");
2938 if (radeon_emit_scalars(dev_priv, *header, cmdbuf)) {
2939 DRM_ERROR("radeon_emit_scalars failed\n");
2944 case RADEON_CMD_VECTORS:
2945 DRM_DEBUG("RADEON_CMD_VECTORS\n");
2946 if (radeon_emit_vectors(dev_priv, *header, cmdbuf)) {
2947 DRM_ERROR("radeon_emit_vectors failed\n");
2952 case RADEON_CMD_DMA_DISCARD:
2953 DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n");
2954 idx = header->dma.buf_idx;
2955 if (idx < 0 || idx >= dma->buf_count) {
2956 DRM_ERROR("buffer index %d (of %d max)\n",
2957 idx, dma->buf_count - 1);
2961 buf = dma->buflist[idx];
2962 if (buf->file_priv != file_priv || buf->pending) {
2963 DRM_ERROR("bad buffer %p %p %d\n",
2964 buf->file_priv, file_priv,
2969 radeon_cp_discard_buffer(dev, file_priv->masterp, buf);
2972 case RADEON_CMD_PACKET3:
2973 DRM_DEBUG("RADEON_CMD_PACKET3\n");
2974 if (radeon_emit_packet3(dev, file_priv, cmdbuf)) {
2975 DRM_ERROR("radeon_emit_packet3 failed\n");
2980 case RADEON_CMD_PACKET3_CLIP:
2981 DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n");
2982 if (radeon_emit_packet3_cliprect
2983 (dev, file_priv, cmdbuf, orig_nbox)) {
2984 DRM_ERROR("radeon_emit_packet3_clip failed\n");
2989 case RADEON_CMD_SCALARS2:
2990 DRM_DEBUG("RADEON_CMD_SCALARS2\n");
2991 if (radeon_emit_scalars2(dev_priv, *header, cmdbuf)) {
2992 DRM_ERROR("radeon_emit_scalars2 failed\n");
2997 case RADEON_CMD_WAIT:
2998 DRM_DEBUG("RADEON_CMD_WAIT\n");
2999 if (radeon_emit_wait(dev, header->wait.flags)) {
3000 DRM_ERROR("radeon_emit_wait failed\n");
3004 case RADEON_CMD_VECLINEAR:
3005 DRM_DEBUG("RADEON_CMD_VECLINEAR\n");
3006 if (radeon_emit_veclinear(dev_priv, *header, cmdbuf)) {
3007 DRM_ERROR("radeon_emit_veclinear failed\n");
3013 DRM_ERROR("bad cmd_type %d at byte %d\n",
3014 header->header.cmd_type,
3015 cmdbuf->buffer->iterator);
3020 drm_buffer_free(cmdbuf->buffer);
3023 DRM_DEBUG("DONE\n");
3028 drm_buffer_free(cmdbuf->buffer);
3032 static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv)
3034 drm_radeon_private_t *dev_priv = dev->dev_private;
3035 drm_radeon_getparam_t *param = data;
3038 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
3040 switch (param->param) {
3041 case RADEON_PARAM_GART_BUFFER_OFFSET:
3042 value = dev_priv->gart_buffers_offset;
3044 case RADEON_PARAM_LAST_FRAME:
3045 dev_priv->stats.last_frame_reads++;
3046 value = GET_SCRATCH(dev_priv, 0);
3048 case RADEON_PARAM_LAST_DISPATCH:
3049 value = GET_SCRATCH(dev_priv, 1);
3051 case RADEON_PARAM_LAST_CLEAR:
3052 dev_priv->stats.last_clear_reads++;
3053 value = GET_SCRATCH(dev_priv, 2);
3055 case RADEON_PARAM_IRQ_NR:
3056 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
3061 case RADEON_PARAM_GART_BASE:
3062 value = dev_priv->gart_vm_start;
3064 case RADEON_PARAM_REGISTER_HANDLE:
3065 value = dev_priv->mmio->offset;
3067 case RADEON_PARAM_STATUS_HANDLE:
3068 value = dev_priv->ring_rptr_offset;
3072 * This ioctl() doesn't work on 64-bit platforms because hw_lock is a
3073 * pointer which can't fit into an int-sized variable. According to
3074 * Michel Dänzer, the ioctl() is only used on embedded platforms, so
3075 * not supporting it shouldn't be a problem. If the same functionality
3076 * is needed on 64-bit platforms, a new ioctl() would have to be added,
3077 * so backwards-compatibility for the embedded platforms can be
3078 * maintained. --davidm 4-Feb-2004.
3080 case RADEON_PARAM_SAREA_HANDLE:
3081 /* The lock is the first dword in the sarea. */
3082 /* no users of this parameter */
3085 case RADEON_PARAM_GART_TEX_HANDLE:
3086 value = dev_priv->gart_textures_offset;
3088 case RADEON_PARAM_SCRATCH_OFFSET:
3089 if (!dev_priv->writeback_works)
3091 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
3092 value = R600_SCRATCH_REG_OFFSET;
3094 value = RADEON_SCRATCH_REG_OFFSET;
3096 case RADEON_PARAM_CARD_TYPE:
3097 if (dev_priv->flags & RADEON_IS_PCIE)
3098 value = RADEON_CARD_PCIE;
3099 else if (dev_priv->flags & RADEON_IS_AGP)
3100 value = RADEON_CARD_AGP;
3102 value = RADEON_CARD_PCI;
3104 case RADEON_PARAM_VBLANK_CRTC:
3105 value = radeon_vblank_crtc_get(dev);
3107 case RADEON_PARAM_FB_LOCATION:
3108 value = radeon_read_fb_location(dev_priv);
3110 case RADEON_PARAM_NUM_GB_PIPES:
3111 value = dev_priv->num_gb_pipes;
3113 case RADEON_PARAM_NUM_Z_PIPES:
3114 value = dev_priv->num_z_pipes;
3117 DRM_DEBUG("Invalid parameter %d\n", param->param);
3121 if (copy_to_user(param->value, &value, sizeof(int))) {
3122 DRM_ERROR("copy_to_user\n");
3129 static int radeon_cp_setparam(struct drm_device *dev, void *data, struct drm_file *file_priv)
3131 drm_radeon_private_t *dev_priv = dev->dev_private;
3132 struct drm_radeon_master_private *master_priv = file_priv->masterp->driver_priv;
3133 drm_radeon_setparam_t *sp = data;
3134 struct drm_radeon_driver_file_fields *radeon_priv;
3136 switch (sp->param) {
3137 case RADEON_SETPARAM_FB_LOCATION:
3138 radeon_priv = file_priv->driver_priv;
3139 radeon_priv->radeon_fb_delta = dev_priv->fb_location -
3142 case RADEON_SETPARAM_SWITCH_TILING:
3143 if (sp->value == 0) {
3144 DRM_DEBUG("color tiling disabled\n");
3145 dev_priv->front_pitch_offset &= ~RADEON_DST_TILE_MACRO;
3146 dev_priv->back_pitch_offset &= ~RADEON_DST_TILE_MACRO;
3147 if (master_priv->sarea_priv)
3148 master_priv->sarea_priv->tiling_enabled = 0;
3149 } else if (sp->value == 1) {
3150 DRM_DEBUG("color tiling enabled\n");
3151 dev_priv->front_pitch_offset |= RADEON_DST_TILE_MACRO;
3152 dev_priv->back_pitch_offset |= RADEON_DST_TILE_MACRO;
3153 if (master_priv->sarea_priv)
3154 master_priv->sarea_priv->tiling_enabled = 1;
3157 case RADEON_SETPARAM_PCIGART_LOCATION:
3158 dev_priv->pcigart_offset = sp->value;
3159 dev_priv->pcigart_offset_set = 1;
3161 case RADEON_SETPARAM_NEW_MEMMAP:
3162 dev_priv->new_memmap = sp->value;
3164 case RADEON_SETPARAM_PCIGART_TABLE_SIZE:
3165 dev_priv->gart_info.table_size = sp->value;
3166 if (dev_priv->gart_info.table_size < RADEON_PCIGART_TABLE_SIZE)
3167 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
3169 case RADEON_SETPARAM_VBLANK_CRTC:
3170 return radeon_vblank_crtc_set(dev, sp->value);
3173 DRM_DEBUG("Invalid parameter %d\n", sp->param);
3180 /* When a client dies:
3181 * - Check for and clean up flipped page state
3182 * - Free any alloced GART memory.
3183 * - Free any alloced radeon surfaces.
3185 * DRM infrastructure takes care of reclaiming dma buffers.
3187 void radeon_driver_preclose(struct drm_device *dev, struct drm_file *file_priv)
3189 if (dev->dev_private) {
3190 drm_radeon_private_t *dev_priv = dev->dev_private;
3191 dev_priv->page_flipping = 0;
3192 radeon_mem_release(file_priv, dev_priv->gart_heap);
3193 radeon_mem_release(file_priv, dev_priv->fb_heap);
3194 radeon_surfaces_release(file_priv, dev_priv);
3198 void radeon_driver_lastclose(struct drm_device *dev)
3200 radeon_surfaces_release(PCIGART_FILE_PRIV, dev->dev_private);
3201 radeon_do_release(dev);
3204 int radeon_driver_open(struct drm_device *dev, struct drm_file *file_priv)
3206 drm_radeon_private_t *dev_priv = dev->dev_private;
3207 struct drm_radeon_driver_file_fields *radeon_priv;
3210 radeon_priv = kmalloc(sizeof(*radeon_priv), M_DRM, M_WAITOK);
3215 file_priv->driver_priv = radeon_priv;
3218 radeon_priv->radeon_fb_delta = dev_priv->fb_location;
3220 radeon_priv->radeon_fb_delta = 0;
3224 void radeon_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
3226 struct drm_radeon_driver_file_fields *radeon_priv =
3227 file_priv->driver_priv;
3232 struct drm_ioctl_desc radeon_ioctls[] = {
3233 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3234 DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3235 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3236 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3237 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle, DRM_AUTH),
3238 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume, DRM_AUTH),
3239 DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset, DRM_AUTH),
3240 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen, DRM_AUTH),
3241 DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap, DRM_AUTH),
3242 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear, DRM_AUTH),
3243 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex, DRM_AUTH),
3244 DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices, DRM_AUTH),
3245 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture, DRM_AUTH),
3246 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple, DRM_AUTH),
3247 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3248 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2, DRM_AUTH),
3249 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf, DRM_AUTH),
3250 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam, DRM_AUTH),
3251 DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip, DRM_AUTH),
3252 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc, DRM_AUTH),
3253 DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free, DRM_AUTH),
3254 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3255 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit, DRM_AUTH),
3256 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait, DRM_AUTH),
3257 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam, DRM_AUTH),
3258 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc, DRM_AUTH),
3259 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free, DRM_AUTH),
3260 DRM_IOCTL_DEF_DRV(RADEON_CS, r600_cs_legacy_ioctl, DRM_AUTH)
3263 int radeon_max_ioctl = ARRAY_SIZE(radeon_ioctls);