d15716e689cf53866e81471327cbf60ec19d91d2
[dragonfly.git] / sys / dev / drm / radeon / radeon_pm.c
1 /*
2  * Permission is hereby granted, free of charge, to any person obtaining a
3  * copy of this software and associated documentation files (the "Software"),
4  * to deal in the Software without restriction, including without limitation
5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6  * and/or sell copies of the Software, and to permit persons to whom the
7  * Software is furnished to do so, subject to the following conditions:
8  *
9  * The above copyright notice and this permission notice shall be included in
10  * all copies or substantial portions of the Software.
11  *
12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18  * OTHER DEALINGS IN THE SOFTWARE.
19  *
20  * Authors: Rafał Miłecki <zajec5@gmail.com>
21  *          Alex Deucher <alexdeucher@gmail.com>
22  *
23  * $FreeBSD: head/sys/dev/drm2/radeon/radeon_pm.c 254885 2013-08-25 19:37:15Z dumbbell $
24  */
25
26 #include <sys/power.h>
27 #include <drm/drmP.h>
28 #include "radeon.h"
29 #include "avivod.h"
30 #include "atom.h"
31
32 #define RADEON_IDLE_LOOP_MS 100
33 #define RADEON_RECLOCK_DELAY_MS 200
34 #define RADEON_WAIT_VBLANK_TIMEOUT 200
35
36 static const char *radeon_pm_state_type_name[5] = {
37         "",
38         "Powersave",
39         "Battery",
40         "Balanced",
41         "Performance",
42 };
43
44 #ifdef DUMBBELL_WIP
45 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
46 #endif /* DUMBBELL_WIP */
47 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
48 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
49 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
50 static void radeon_pm_update_profile(struct radeon_device *rdev);
51 static void radeon_pm_set_clocks(struct radeon_device *rdev);
52
53 int radeon_pm_get_type_index(struct radeon_device *rdev,
54                              enum radeon_pm_state_type ps_type,
55                              int instance)
56 {
57         int i;
58         int found_instance = -1;
59
60         for (i = 0; i < rdev->pm.num_power_states; i++) {
61                 if (rdev->pm.power_state[i].type == ps_type) {
62                         found_instance++;
63                         if (found_instance == instance)
64                                 return i;
65                 }
66         }
67         /* return default if no match */
68         return rdev->pm.default_power_state_index;
69 }
70
71 void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
72 {
73         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
74                 if (rdev->pm.profile == PM_PROFILE_AUTO) {
75                         lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE);
76                         radeon_pm_update_profile(rdev);
77                         radeon_pm_set_clocks(rdev);
78                         lockmgr(&rdev->pm.mutex, LK_RELEASE);
79                 }
80         }
81 }
82
83 static void radeon_pm_update_profile(struct radeon_device *rdev)
84 {
85         switch (rdev->pm.profile) {
86         case PM_PROFILE_DEFAULT:
87                 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
88                 break;
89         case PM_PROFILE_AUTO:
90                 if (power_profile_get_state() == POWER_PROFILE_PERFORMANCE) {
91                         if (rdev->pm.active_crtc_count > 1)
92                                 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
93                         else
94                                 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
95                 } else {
96                         if (rdev->pm.active_crtc_count > 1)
97                                 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
98                         else
99                                 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
100                 }
101                 break;
102         case PM_PROFILE_LOW:
103                 if (rdev->pm.active_crtc_count > 1)
104                         rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
105                 else
106                         rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
107                 break;
108         case PM_PROFILE_MID:
109                 if (rdev->pm.active_crtc_count > 1)
110                         rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
111                 else
112                         rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
113                 break;
114         case PM_PROFILE_HIGH:
115                 if (rdev->pm.active_crtc_count > 1)
116                         rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
117                 else
118                         rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
119                 break;
120         }
121
122         if (rdev->pm.active_crtc_count == 0) {
123                 rdev->pm.requested_power_state_index =
124                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
125                 rdev->pm.requested_clock_mode_index =
126                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
127         } else {
128                 rdev->pm.requested_power_state_index =
129                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
130                 rdev->pm.requested_clock_mode_index =
131                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
132         }
133 }
134
135 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
136 {
137         struct radeon_bo *bo, *n;
138
139         if (list_empty(&rdev->gem.objects))
140                 return;
141
142         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
143                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
144                         ttm_bo_unmap_virtual(&bo->tbo);
145         }
146 }
147
148 static void radeon_sync_with_vblank(struct radeon_device *rdev)
149 {
150         if (rdev->pm.active_crtcs) {
151                 rdev->pm.vblank_sync = false;
152 #ifdef DUMBBELL_WIP
153                 wait_event_timeout(
154                         rdev->irq.vblank_queue, rdev->pm.vblank_sync,
155                         msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
156 #endif /* DUMBBELL_WIP */
157         }
158 }
159
160 static void radeon_set_power_state(struct radeon_device *rdev)
161 {
162         u32 sclk, mclk;
163         bool misc_after = false;
164
165         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
166             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
167                 return;
168
169         if (radeon_gui_idle(rdev)) {
170                 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
171                         clock_info[rdev->pm.requested_clock_mode_index].sclk;
172                 if (sclk > rdev->pm.default_sclk)
173                         sclk = rdev->pm.default_sclk;
174
175                 /* starting with BTC, there is one state that is used for both
176                  * MH and SH.  Difference is that we always use the high clock index for
177                  * mclk and vddci.
178                  */
179                 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
180                     (rdev->family >= CHIP_BARTS) &&
181                     rdev->pm.active_crtc_count &&
182                     ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
183                      (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
184                         mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
185                                 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
186                 else
187                         mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
188                                 clock_info[rdev->pm.requested_clock_mode_index].mclk;
189
190                 if (mclk > rdev->pm.default_mclk)
191                         mclk = rdev->pm.default_mclk;
192
193                 /* upvolt before raising clocks, downvolt after lowering clocks */
194                 if (sclk < rdev->pm.current_sclk)
195                         misc_after = true;
196
197                 radeon_sync_with_vblank(rdev);
198
199                 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
200                         if (!radeon_pm_in_vbl(rdev))
201                                 return;
202                 }
203
204                 radeon_pm_prepare(rdev);
205
206                 if (!misc_after)
207                         /* voltage, pcie lanes, etc.*/
208                         radeon_pm_misc(rdev);
209
210                 /* set engine clock */
211                 if (sclk != rdev->pm.current_sclk) {
212                         radeon_pm_debug_check_in_vbl(rdev, false);
213                         radeon_set_engine_clock(rdev, sclk);
214                         radeon_pm_debug_check_in_vbl(rdev, true);
215                         rdev->pm.current_sclk = sclk;
216                         DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
217                 }
218
219                 /* set memory clock */
220                 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
221                         radeon_pm_debug_check_in_vbl(rdev, false);
222                         radeon_set_memory_clock(rdev, mclk);
223                         radeon_pm_debug_check_in_vbl(rdev, true);
224                         rdev->pm.current_mclk = mclk;
225                         DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
226                 }
227
228                 if (misc_after)
229                         /* voltage, pcie lanes, etc.*/
230                         radeon_pm_misc(rdev);
231
232                 radeon_pm_finish(rdev);
233
234                 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
235                 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
236         } else
237                 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
238 }
239
240 static void radeon_pm_set_clocks(struct radeon_device *rdev)
241 {
242         int i, r;
243
244         /* no need to take locks, etc. if nothing's going to change */
245         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
246             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
247                 return;
248
249         DRM_LOCK(rdev->ddev);
250         lockmgr(&rdev->pm.mclk_lock, LK_EXCLUSIVE); // down_write
251         lockmgr(&rdev->ring_lock, LK_EXCLUSIVE);
252
253         /* wait for the rings to drain */
254         for (i = 0; i < RADEON_NUM_RINGS; i++) {
255                 struct radeon_ring *ring = &rdev->ring[i];
256                 if (!ring->ready) {
257                         continue;
258                 }
259                 r = radeon_fence_wait_empty_locked(rdev, i);
260                 if (r) {
261                         /* needs a GPU reset dont reset here */
262                         lockmgr(&rdev->ring_lock, LK_RELEASE);
263                         lockmgr(&rdev->pm.mclk_lock, LK_RELEASE); // up_write
264                         DRM_UNLOCK(rdev->ddev);
265                         return;
266                 }
267         }
268
269         radeon_unmap_vram_bos(rdev);
270
271         if (rdev->irq.installed) {
272                 for (i = 0; i < rdev->num_crtc; i++) {
273                         if (rdev->pm.active_crtcs & (1 << i)) {
274                                 rdev->pm.req_vblank |= (1 << i);
275                                 drm_vblank_get(rdev->ddev, i);
276                         }
277                 }
278         }
279
280         radeon_set_power_state(rdev);
281
282         if (rdev->irq.installed) {
283                 for (i = 0; i < rdev->num_crtc; i++) {
284                         if (rdev->pm.req_vblank & (1 << i)) {
285                                 rdev->pm.req_vblank &= ~(1 << i);
286                                 drm_vblank_put(rdev->ddev, i);
287                         }
288                 }
289         }
290
291         /* update display watermarks based on new power state */
292         radeon_update_bandwidth_info(rdev);
293         if (rdev->pm.active_crtc_count)
294                 radeon_bandwidth_update(rdev);
295
296         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
297
298         lockmgr(&rdev->ring_lock, LK_RELEASE);
299         lockmgr(&rdev->pm.mclk_lock, LK_RELEASE); // up_write
300         DRM_UNLOCK(rdev->ddev);
301 }
302
303 static void radeon_pm_print_states(struct radeon_device *rdev)
304 {
305         int i, j;
306         struct radeon_power_state *power_state;
307         struct radeon_pm_clock_info *clock_info;
308
309         DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
310         for (i = 0; i < rdev->pm.num_power_states; i++) {
311                 power_state = &rdev->pm.power_state[i];
312                 DRM_DEBUG_DRIVER("State %d: %s\n", i,
313                         radeon_pm_state_type_name[power_state->type]);
314                 if (i == rdev->pm.default_power_state_index)
315                         DRM_DEBUG_DRIVER("\tDefault");
316                 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
317                         DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
318                 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
319                         DRM_DEBUG_DRIVER("\tSingle display only\n");
320                 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
321                 for (j = 0; j < power_state->num_clock_modes; j++) {
322                         clock_info = &(power_state->clock_info[j]);
323                         if (rdev->flags & RADEON_IS_IGP)
324                                 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
325                                                  j,
326                                                  clock_info->sclk * 10);
327                         else
328                                 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
329                                                  j,
330                                                  clock_info->sclk * 10,
331                                                  clock_info->mclk * 10,
332                                                  clock_info->voltage.voltage);
333                 }
334         }
335 }
336
337 #ifdef DUMBBELL_WIP
338 static ssize_t radeon_get_pm_profile(struct device *dev,
339                                      struct device_attribute *attr,
340                                      char *buf)
341 {
342         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
343         struct radeon_device *rdev = ddev->dev_private;
344         int cp = rdev->pm.profile;
345
346         return ksnprintf(buf, PAGE_SIZE, "%s\n",
347                         (cp == PM_PROFILE_AUTO) ? "auto" :
348                         (cp == PM_PROFILE_LOW) ? "low" :
349                         (cp == PM_PROFILE_MID) ? "mid" :
350                         (cp == PM_PROFILE_HIGH) ? "high" : "default");
351 }
352
353 static ssize_t radeon_set_pm_profile(struct device *dev,
354                                      struct device_attribute *attr,
355                                      const char *buf,
356                                      size_t count)
357 {
358         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
359         struct radeon_device *rdev = ddev->dev_private;
360
361         lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE);
362         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
363                 if (strncmp("default", buf, strlen("default")) == 0)
364                         rdev->pm.profile = PM_PROFILE_DEFAULT;
365                 else if (strncmp("auto", buf, strlen("auto")) == 0)
366                         rdev->pm.profile = PM_PROFILE_AUTO;
367                 else if (strncmp("low", buf, strlen("low")) == 0)
368                         rdev->pm.profile = PM_PROFILE_LOW;
369                 else if (strncmp("mid", buf, strlen("mid")) == 0)
370                         rdev->pm.profile = PM_PROFILE_MID;
371                 else if (strncmp("high", buf, strlen("high")) == 0)
372                         rdev->pm.profile = PM_PROFILE_HIGH;
373                 else {
374                         count = -EINVAL;
375                         goto fail;
376                 }
377                 radeon_pm_update_profile(rdev);
378                 radeon_pm_set_clocks(rdev);
379         } else
380                 count = -EINVAL;
381
382 fail:
383         lockmgr(&rdev->pm.mutex, LK_RELEASE);
384
385         return count;
386 }
387
388 static ssize_t radeon_get_pm_method(struct device *dev,
389                                     struct device_attribute *attr,
390                                     char *buf)
391 {
392         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
393         struct radeon_device *rdev = ddev->dev_private;
394         int pm = rdev->pm.pm_method;
395
396         return ksnprintf(buf, PAGE_SIZE, "%s\n",
397                         (pm == PM_METHOD_DYNPM) ? "dynpm" :
398                         (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
399 }
400
401 static ssize_t radeon_set_pm_method(struct device *dev,
402                                     struct device_attribute *attr,
403                                     const char *buf,
404                                     size_t count)
405 {
406         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
407         struct radeon_device *rdev = ddev->dev_private;
408
409         /* we don't support the legacy modes with dpm */
410         if (rdev->pm.pm_method == PM_METHOD_DPM) {
411                 count = -EINVAL;
412                 goto fail;
413         }
414
415         if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
416                 lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE);
417                 rdev->pm.pm_method = PM_METHOD_DYNPM;
418                 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
419                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
420                 lockmgr(&rdev->pm.mutex, LK_RELEASE);
421         } else if (strncmp("profile", buf, strlen("profile")) == 0) {
422                 lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE);
423                 /* disable dynpm */
424                 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
425                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
426                 rdev->pm.pm_method = PM_METHOD_PROFILE;
427                 lockmgr(&rdev->pm.mutex, LK_RELEASE);
428 #ifdef DUMBBELL_WIP
429                 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
430 #endif /* DUMBBELL_WIP */
431         } else {
432                 count = -EINVAL;
433                 goto fail;
434         }
435         radeon_pm_compute_clocks(rdev);
436 fail:
437         return count;
438 }
439
440 static ssize_t radeon_get_dpm_state(struct device *dev,
441                                     struct device_attribute *attr,
442                                     char *buf)
443 {
444         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
445         struct radeon_device *rdev = ddev->dev_private;
446         enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
447
448         return snprintf(buf, PAGE_SIZE, "%s\n",
449                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
450                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
451 }
452
453 static ssize_t radeon_set_dpm_state(struct device *dev,
454                                     struct device_attribute *attr,
455                                     const char *buf,
456                                     size_t count)
457 {
458         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
459         struct radeon_device *rdev = ddev->dev_private;
460
461         lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE);
462         if (strncmp("battery", buf, strlen("battery")) == 0)
463                 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
464         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
465                 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
466         else if (strncmp("performance", buf, strlen("performance")) == 0)
467                 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
468         else {
469                 lockmgr(&rdev->pm.mutex, LK_RELEASE);
470                 count = -EINVAL;
471                 goto fail;
472         }
473         lockmgr(&rdev->pm.mutex, LK_RELEASE);
474         radeon_pm_compute_clocks(rdev);
475 fail:
476         return count;
477 }
478
479 static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev,
480                                                        struct device_attribute *attr,
481                                                        char *buf)
482 {
483         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
484         struct radeon_device *rdev = ddev->dev_private;
485         enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
486
487         return snprintf(buf, PAGE_SIZE, "%s\n",
488                         (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" :
489                         (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
490 }
491
492 static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev,
493                                                        struct device_attribute *attr,
494                                                        const char *buf,
495                                                        size_t count)
496 {
497         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
498         struct radeon_device *rdev = ddev->dev_private;
499         enum radeon_dpm_forced_level level;
500         int ret = 0;
501
502         spin_lock(&rdev->pm.mutex);
503         if (strncmp("low", buf, strlen("low")) == 0) {
504                 level = RADEON_DPM_FORCED_LEVEL_LOW;
505         } else if (strncmp("high", buf, strlen("high")) == 0) {
506                 level = RADEON_DPM_FORCED_LEVEL_HIGH;
507         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
508                 level = RADEON_DPM_FORCED_LEVEL_AUTO;
509         } else {
510                 spin_unlock(&rdev->pm.mutex);
511                 count = -EINVAL;
512                 goto fail;
513         }
514         if (rdev->asic->dpm.force_performance_level) {
515                 ret = radeon_dpm_force_performance_level(rdev, level);
516                 if (ret)
517                         count = -EINVAL;
518         }
519         spin_unlock(&rdev->pm.mutex);
520 fail:
521         return count;
522 }
523
524 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
525 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
526 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
527 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
528                    radeon_get_dpm_forced_performance_level,
529                    radeon_set_dpm_forced_performance_level);
530
531 static ssize_t radeon_hwmon_show_temp(struct device *dev,
532                                       struct device_attribute *attr,
533                                       char *buf)
534 {
535         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
536         struct radeon_device *rdev = ddev->dev_private;
537         int temp;
538
539         if (rdev->asic->pm.get_temperature)
540                 temp = radeon_get_temperature(rdev);
541         else
542                 temp = 0;
543
544         return ksnprintf(buf, PAGE_SIZE, "%d\n", temp);
545 }
546
547 static ssize_t radeon_hwmon_show_name(struct device *dev,
548                                       struct device_attribute *attr,
549                                       char *buf)
550 {
551         return sprintf(buf, "radeon\n");
552 }
553
554 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
555 static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
556
557 static struct attribute *hwmon_attributes[] = {
558         &sensor_dev_attr_temp1_input.dev_attr.attr,
559         &sensor_dev_attr_name.dev_attr.attr,
560         NULL
561 };
562
563 static const struct attribute_group hwmon_attrgroup = {
564         .attrs = hwmon_attributes,
565 };
566 #endif /* DUMBBELL_WIP */
567
568 static int radeon_hwmon_init(struct radeon_device *rdev)
569 {
570         int err = 0;
571
572 #ifdef DUMBBELL_WIP
573         rdev->pm.int_hwmon_dev = NULL;
574 #endif /* DUMBBELL_WIP */
575
576         switch (rdev->pm.int_thermal_type) {
577         case THERMAL_TYPE_RV6XX:
578         case THERMAL_TYPE_RV770:
579         case THERMAL_TYPE_EVERGREEN:
580         case THERMAL_TYPE_NI:
581         case THERMAL_TYPE_SUMO:
582         case THERMAL_TYPE_SI:
583                 if (rdev->asic->pm.get_temperature == NULL)
584                         return err;
585 #ifdef DUMBBELL_WIP
586                 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
587                 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
588                         err = PTR_ERR(rdev->pm.int_hwmon_dev);
589                         dev_err(rdev->dev,
590                                 "Unable to register hwmon device: %d\n", err);
591                         break;
592                 }
593                 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
594                 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
595                                          &hwmon_attrgroup);
596                 if (err) {
597                         dev_err(rdev->dev,
598                                 "Unable to create hwmon sysfs file: %d\n", err);
599                         hwmon_device_unregister(rdev->dev);
600                 }
601 #endif /* DUMBBELL_WIP */
602                 break;
603         default:
604                 break;
605         }
606
607         return err;
608 }
609
610 static void radeon_hwmon_fini(struct radeon_device *rdev)
611 {
612 #ifdef DUMBBELL_WIP
613         if (rdev->pm.int_hwmon_dev) {
614                 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
615                 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
616         }
617 #endif /* DUMBBELL_WIP */
618 }
619
620 static void radeon_dpm_thermal_work_handler(void *arg, int pending)
621 {
622         struct radeon_device *rdev = arg;
623         /* switch to the thermal state */
624         enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
625
626         if (!rdev->pm.dpm_enabled)
627                 return;
628
629         if (rdev->asic->pm.get_temperature) {
630                 int temp = radeon_get_temperature(rdev);
631
632                 if (temp < rdev->pm.dpm.thermal.min_temp)
633                         /* switch back the user state */
634                         dpm_state = rdev->pm.dpm.user_state;
635         } else {
636                 if (rdev->pm.dpm.thermal.high_to_low)
637                         /* switch back the user state */
638                         dpm_state = rdev->pm.dpm.user_state;
639         }
640         radeon_dpm_enable_power_state(rdev, dpm_state);
641 }
642
643 static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
644                                                      enum radeon_pm_state_type dpm_state)
645 {
646         int i;
647         struct radeon_ps *ps;
648         u32 ui_class;
649         bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
650                 true : false;
651
652         /* check if the vblank period is too short to adjust the mclk */
653         if (single_display && rdev->asic->dpm.vblank_too_short) {
654                 if (radeon_dpm_vblank_too_short(rdev))
655                         single_display = false;
656         }
657
658         /* certain older asics have a separare 3D performance state,
659          * so try that first if the user selected performance
660          */
661         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
662                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
663         /* balanced states don't exist at the moment */
664         if (dpm_state == POWER_STATE_TYPE_BALANCED)
665                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
666
667 restart_search:
668         /* Pick the best power state based on current conditions */
669         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
670                 ps = &rdev->pm.dpm.ps[i];
671                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
672                 switch (dpm_state) {
673                 /* user states */
674                 case POWER_STATE_TYPE_BATTERY:
675                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
676                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
677                                         if (single_display)
678                                                 return ps;
679                                 } else
680                                         return ps;
681                         }
682                         break;
683                 case POWER_STATE_TYPE_BALANCED:
684                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
685                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
686                                         if (single_display)
687                                                 return ps;
688                                 } else
689                                         return ps;
690                         }
691                         break;
692                 case POWER_STATE_TYPE_PERFORMANCE:
693                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
694                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
695                                         if (single_display)
696                                                 return ps;
697                                 } else
698                                         return ps;
699                         }
700                         break;
701                 /* internal states */
702                 case POWER_STATE_TYPE_INTERNAL_UVD:
703                         return rdev->pm.dpm.uvd_ps;
704                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
705                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
706                                 return ps;
707                         break;
708                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
709                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
710                                 return ps;
711                         break;
712                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
713                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
714                                 return ps;
715                         break;
716                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
717                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
718                                 return ps;
719                         break;
720                 case POWER_STATE_TYPE_INTERNAL_BOOT:
721                         return rdev->pm.dpm.boot_ps;
722                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
723                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
724                                 return ps;
725                         break;
726                 case POWER_STATE_TYPE_INTERNAL_ACPI:
727                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
728                                 return ps;
729                         break;
730                 case POWER_STATE_TYPE_INTERNAL_ULV:
731                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
732                                 return ps;
733                         break;
734                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
735                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
736                                 return ps;
737                         break;
738                 default:
739                         break;
740                 }
741         }
742         /* use a fallback state if we didn't match */
743         switch (dpm_state) {
744         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
745         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
746         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
747         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
748                 return rdev->pm.dpm.uvd_ps;
749         case POWER_STATE_TYPE_INTERNAL_THERMAL:
750                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
751                 goto restart_search;
752         case POWER_STATE_TYPE_INTERNAL_ACPI:
753                 dpm_state = POWER_STATE_TYPE_BATTERY;
754                 goto restart_search;
755         case POWER_STATE_TYPE_BATTERY:
756         case POWER_STATE_TYPE_BALANCED:
757         case POWER_STATE_TYPE_INTERNAL_3DPERF:
758                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
759                 goto restart_search;
760         default:
761                 break;
762         }
763
764         return NULL;
765 }
766
767 static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
768 {
769         int i;
770         struct radeon_ps *ps;
771         enum radeon_pm_state_type dpm_state;
772         int ret;
773
774         /* if dpm init failed */
775         if (!rdev->pm.dpm_enabled)
776                 return;
777
778         if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
779                 /* add other state override checks here */
780                 if ((!rdev->pm.dpm.thermal_active) &&
781                     (!rdev->pm.dpm.uvd_active))
782                         rdev->pm.dpm.state = rdev->pm.dpm.user_state;
783         }
784         dpm_state = rdev->pm.dpm.state;
785
786         ps = radeon_dpm_pick_power_state(rdev, dpm_state);
787         if (ps)
788                 rdev->pm.dpm.requested_ps = ps;
789         else
790                 return;
791
792         /* no need to reprogram if nothing changed unless we are on BTC+ */
793         if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
794                 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
795                         /* for pre-BTC and APUs if the num crtcs changed but state is the same,
796                          * all we need to do is update the display configuration.
797                          */
798                         if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
799                                 /* update display watermarks based on new power state */
800                                 radeon_bandwidth_update(rdev);
801                                 /* update displays */
802                                 radeon_dpm_display_configuration_changed(rdev);
803                                 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
804                                 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
805                         }
806                         return;
807                 } else {
808                         /* for BTC+ if the num crtcs hasn't changed and state is the same,
809                          * nothing to do, if the num crtcs is > 1 and state is the same,
810                          * update display configuration.
811                          */
812                         if (rdev->pm.dpm.new_active_crtcs ==
813                             rdev->pm.dpm.current_active_crtcs) {
814                                 return;
815                         } else {
816                                 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
817                                     (rdev->pm.dpm.new_active_crtc_count > 1)) {
818                                         /* update display watermarks based on new power state */
819                                         radeon_bandwidth_update(rdev);
820                                         /* update displays */
821                                         radeon_dpm_display_configuration_changed(rdev);
822                                         rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
823                                         rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
824                                         return;
825                                 }
826                         }
827                 }
828         }
829
830         printk("switching from power state:\n");
831         radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
832         printk("switching to power state:\n");
833         radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
834
835         lockmgr(&rdev->ddev->struct_mutex, LK_EXCLUSIVE);
836         lockmgr(&rdev->pm.mclk_lock, LK_EXCLUSIVE); // down_write
837         lockmgr(&rdev->ring_lock, LK_EXCLUSIVE);
838
839         ret = radeon_dpm_pre_set_power_state(rdev);
840         if (ret)
841                 goto done;
842
843         /* update display watermarks based on new power state */
844         radeon_bandwidth_update(rdev);
845         /* update displays */
846         radeon_dpm_display_configuration_changed(rdev);
847
848         rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
849         rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
850
851         /* wait for the rings to drain */
852         for (i = 0; i < RADEON_NUM_RINGS; i++) {
853                 struct radeon_ring *ring = &rdev->ring[i];
854                 if (ring->ready)
855                         radeon_fence_wait_empty_locked(rdev, i);
856         }
857
858         /* program the new power state */
859         radeon_dpm_set_power_state(rdev);
860
861         /* update current power state */
862         rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
863
864         radeon_dpm_post_set_power_state(rdev);
865
866 done:
867         lockmgr(&rdev->ring_lock, LK_RELEASE);
868         lockmgr(&rdev->pm.mclk_lock, LK_RELEASE); // up_write
869         lockmgr(&rdev->ddev->struct_mutex, LK_RELEASE);
870 }
871
872 void radeon_dpm_enable_power_state(struct radeon_device *rdev,
873                                    enum radeon_pm_state_type dpm_state)
874 {
875         if (!rdev->pm.dpm_enabled)
876                 return;
877
878         lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE);
879         switch (dpm_state) {
880         case POWER_STATE_TYPE_INTERNAL_THERMAL:
881                 rdev->pm.dpm.thermal_active = true;
882                 break;
883         case POWER_STATE_TYPE_INTERNAL_UVD:
884         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
885         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
886         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
887         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
888                 rdev->pm.dpm.uvd_active = true;
889                 break;
890         default:
891                 rdev->pm.dpm.thermal_active = false;
892                 rdev->pm.dpm.uvd_active = false;
893                 break;
894         }
895         rdev->pm.dpm.state = dpm_state;
896         lockmgr(&rdev->pm.mutex, LK_RELEASE);
897         radeon_pm_compute_clocks(rdev);
898 }
899
900 static void radeon_pm_suspend_old(struct radeon_device *rdev)
901 {
902         lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE);
903         if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
904                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
905                         rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
906         }
907         lockmgr(&rdev->pm.mutex, LK_RELEASE);
908
909 #ifdef DUMBBELL_WIP
910         cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
911 #endif /* DUMBBELL_WIP */
912 }
913
914 static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
915 {
916         lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE);
917         /* disable dpm */
918         radeon_dpm_disable(rdev);
919         /* reset the power state */
920         rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
921         rdev->pm.dpm_enabled = false;
922         lockmgr(&rdev->pm.mutex, LK_RELEASE);
923 }
924
925 void radeon_pm_suspend(struct radeon_device *rdev)
926 {
927         if (rdev->pm.pm_method == PM_METHOD_DPM)
928                 radeon_pm_suspend_dpm(rdev);
929         else
930                 radeon_pm_suspend_old(rdev);
931 }
932
933 static void radeon_pm_resume_old(struct radeon_device *rdev)
934 {
935         /* set up the default clocks if the MC ucode is loaded */
936         if ((rdev->family >= CHIP_BARTS) &&
937             (rdev->family <= CHIP_HAINAN) &&
938             rdev->mc_fw) {
939                 if (rdev->pm.default_vddc)
940                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
941                                                 SET_VOLTAGE_TYPE_ASIC_VDDC);
942                 if (rdev->pm.default_vddci)
943                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
944                                                 SET_VOLTAGE_TYPE_ASIC_VDDCI);
945                 if (rdev->pm.default_sclk)
946                         radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
947                 if (rdev->pm.default_mclk)
948                         radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
949         }
950         /* asic init will reset the default power state */
951         lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE);
952         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
953         rdev->pm.current_clock_mode_index = 0;
954         rdev->pm.current_sclk = rdev->pm.default_sclk;
955         rdev->pm.current_mclk = rdev->pm.default_mclk;
956         rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
957         rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
958         if (rdev->pm.pm_method == PM_METHOD_DYNPM
959             && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
960                 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
961 #ifdef DUMBBELL_WIP
962                 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
963                                       msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
964 #endif /* DUMBBELL_WIP */
965         }
966         lockmgr(&rdev->pm.mutex, LK_RELEASE);
967         radeon_pm_compute_clocks(rdev);
968 }
969
970 static void radeon_pm_resume_dpm(struct radeon_device *rdev)
971 {
972         int ret;
973
974         /* asic init will reset to the boot state */
975         lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE);
976         rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
977         radeon_dpm_setup_asic(rdev);
978         ret = radeon_dpm_enable(rdev);
979         lockmgr(&rdev->pm.mutex, LK_RELEASE);
980         if (ret) {
981                 DRM_ERROR("radeon: dpm resume failed\n");
982                 if ((rdev->family >= CHIP_BARTS) &&
983                     (rdev->family <= CHIP_HAINAN) &&
984                     rdev->mc_fw) {
985                         if (rdev->pm.default_vddc)
986                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
987                                                         SET_VOLTAGE_TYPE_ASIC_VDDC);
988                         if (rdev->pm.default_vddci)
989                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
990                                                         SET_VOLTAGE_TYPE_ASIC_VDDCI);
991                         if (rdev->pm.default_sclk)
992                                 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
993                         if (rdev->pm.default_mclk)
994                                 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
995                 }
996         } else {
997                 rdev->pm.dpm_enabled = true;
998                 radeon_pm_compute_clocks(rdev);
999         }
1000 }
1001
1002 void radeon_pm_resume(struct radeon_device *rdev)
1003 {
1004         if (rdev->pm.pm_method == PM_METHOD_DPM)
1005                 radeon_pm_resume_dpm(rdev);
1006         else
1007                 radeon_pm_resume_old(rdev);
1008 }
1009
1010 static int radeon_pm_init_old(struct radeon_device *rdev)
1011 {
1012         int ret;
1013
1014         rdev->pm.profile = PM_PROFILE_DEFAULT;
1015         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1016         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1017         rdev->pm.dynpm_can_upclock = true;
1018         rdev->pm.dynpm_can_downclock = true;
1019         rdev->pm.default_sclk = rdev->clock.default_sclk;
1020         rdev->pm.default_mclk = rdev->clock.default_mclk;
1021         rdev->pm.current_sclk = rdev->clock.default_sclk;
1022         rdev->pm.current_mclk = rdev->clock.default_mclk;
1023         rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1024
1025         if (rdev->bios) {
1026                 if (rdev->is_atom_bios)
1027                         radeon_atombios_get_power_modes(rdev);
1028                 else
1029                         radeon_combios_get_power_modes(rdev);
1030                 radeon_pm_print_states(rdev);
1031                 radeon_pm_init_profile(rdev);
1032                 /* set up the default clocks if the MC ucode is loaded */
1033                 if ((rdev->family >= CHIP_BARTS) &&
1034                     (rdev->family <= CHIP_HAINAN) &&
1035                     rdev->mc_fw) {
1036                         if (rdev->pm.default_vddc)
1037                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1038                                                         SET_VOLTAGE_TYPE_ASIC_VDDC);
1039                         if (rdev->pm.default_vddci)
1040                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1041                                                         SET_VOLTAGE_TYPE_ASIC_VDDCI);
1042                         if (rdev->pm.default_sclk)
1043                                 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1044                         if (rdev->pm.default_mclk)
1045                                 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1046                 }
1047         }
1048
1049         /* set up the internal thermal sensor if applicable */
1050         ret = radeon_hwmon_init(rdev);
1051         if (ret)
1052                 return ret;
1053
1054 #ifdef DUMBBELL_WIP
1055         INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
1056 #endif /* DUMBBELL_WIP */
1057
1058         if (rdev->pm.num_power_states > 1) {
1059                 /* where's the best place to put these? */
1060 #ifdef DUMBBELL_WIP
1061                 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1062 #endif /* DUMBBELL_WIP */
1063                 if (ret)
1064                         DRM_ERROR("failed to create device file for power profile\n");
1065 #ifdef DUMBBELL_WIP
1066                 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1067 #endif /* DUMBBELL_WIP */
1068                 if (ret)
1069                         DRM_ERROR("failed to create device file for power method\n");
1070
1071                 if (radeon_debugfs_pm_init(rdev)) {
1072                         DRM_ERROR("Failed to register debugfs file for PM!\n");
1073                 }
1074
1075                 DRM_INFO("radeon: power management initialized\n");
1076         }
1077
1078         return 0;
1079 }
1080
1081 static void radeon_dpm_print_power_states(struct radeon_device *rdev)
1082 {
1083         int i;
1084
1085         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1086                 printk("== power state %d ==\n", i);
1087                 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1088         }
1089 }
1090
1091 static int radeon_pm_init_dpm(struct radeon_device *rdev)
1092 {
1093         int ret;
1094
1095         /* default to performance state */
1096         rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1097         rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
1098         rdev->pm.default_sclk = rdev->clock.default_sclk;
1099         rdev->pm.default_mclk = rdev->clock.default_mclk;
1100         rdev->pm.current_sclk = rdev->clock.default_sclk;
1101         rdev->pm.current_mclk = rdev->clock.default_mclk;
1102         rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1103
1104         if (rdev->bios && rdev->is_atom_bios)
1105                 radeon_atombios_get_power_modes(rdev);
1106         else
1107                 return -EINVAL;
1108
1109         /* set up the internal thermal sensor if applicable */
1110         ret = radeon_hwmon_init(rdev);
1111         if (ret)
1112                 return ret;
1113
1114         TASK_INIT(&rdev->pm.dpm.thermal.work, 0, radeon_dpm_thermal_work_handler, rdev);
1115         lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE);
1116         radeon_dpm_init(rdev);
1117         rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1118         radeon_dpm_print_power_states(rdev);
1119         radeon_dpm_setup_asic(rdev);
1120         ret = radeon_dpm_enable(rdev);
1121         lockmgr(&rdev->pm.mutex, LK_RELEASE);
1122         if (ret) {
1123                 rdev->pm.dpm_enabled = false;
1124                 if ((rdev->family >= CHIP_BARTS) &&
1125                     (rdev->family <= CHIP_HAINAN) &&
1126                     rdev->mc_fw) {
1127                         if (rdev->pm.default_vddc)
1128                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1129                                                         SET_VOLTAGE_TYPE_ASIC_VDDC);
1130                         if (rdev->pm.default_vddci)
1131                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1132                                                         SET_VOLTAGE_TYPE_ASIC_VDDCI);
1133                         if (rdev->pm.default_sclk)
1134                                 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1135                         if (rdev->pm.default_mclk)
1136                                 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1137                 }
1138                 DRM_ERROR("radeon: dpm initialization failed\n");
1139                 return ret;
1140         }
1141         rdev->pm.dpm_enabled = true;
1142         radeon_pm_compute_clocks(rdev);
1143
1144 #ifdef TODO_DEVICE_FILE
1145         if (rdev->pm.num_power_states > 1) {
1146                 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1147                 if (ret)
1148                         DRM_ERROR("failed to create device file for dpm state\n");
1149                 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1150                 if (ret)
1151                         DRM_ERROR("failed to create device file for dpm state\n");
1152                 /* XXX: these are noops for dpm but are here for backwards compat */
1153                 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1154                 if (ret)
1155                         DRM_ERROR("failed to create device file for power profile\n");
1156                 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1157                 if (ret)
1158                         DRM_ERROR("failed to create device file for power method\n");
1159
1160                 if (radeon_debugfs_pm_init(rdev)) {
1161                         DRM_ERROR("Failed to register debugfs file for dpm!\n");
1162                 }
1163
1164                 DRM_INFO("radeon: dpm initialized\n");
1165         }
1166 #endif
1167
1168         return 0;
1169 }
1170
1171 int radeon_pm_init(struct radeon_device *rdev)
1172 {
1173         /* enable dpm on rv6xx+ */
1174         switch (rdev->family) {
1175         case CHIP_RV610:
1176         case CHIP_RV630:
1177         case CHIP_RV620:
1178         case CHIP_RV635:
1179         case CHIP_RV670:
1180         case CHIP_RS780:
1181         case CHIP_RS880:
1182         case CHIP_RV770:
1183         case CHIP_RV730:
1184         case CHIP_RV710:
1185         case CHIP_RV740:
1186         case CHIP_CEDAR:
1187         case CHIP_REDWOOD:
1188         case CHIP_JUNIPER:
1189         case CHIP_CYPRESS:
1190         case CHIP_HEMLOCK:
1191         case CHIP_PALM:
1192         case CHIP_SUMO:
1193         case CHIP_SUMO2:
1194         case CHIP_BARTS:
1195         case CHIP_TURKS:
1196         case CHIP_CAICOS:
1197         case CHIP_CAYMAN:
1198         case CHIP_ARUBA:
1199         case CHIP_TAHITI:
1200         case CHIP_PITCAIRN:
1201         case CHIP_VERDE:
1202         case CHIP_OLAND:
1203         case CHIP_HAINAN:
1204                 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1205                 if (!rdev->rlc_fw)
1206                         rdev->pm.pm_method = PM_METHOD_PROFILE;
1207                 else if ((rdev->family >= CHIP_RV770) &&
1208                          (!(rdev->flags & RADEON_IS_IGP)) &&
1209                          (!rdev->smc_fw))
1210                         rdev->pm.pm_method = PM_METHOD_PROFILE;
1211                 else if (radeon_dpm == 1)
1212                         rdev->pm.pm_method = PM_METHOD_DPM;
1213                 else
1214                         rdev->pm.pm_method = PM_METHOD_PROFILE;
1215                 break;
1216         default:
1217                 /* default to profile method */
1218                 rdev->pm.pm_method = PM_METHOD_PROFILE;
1219                 break;
1220         }
1221
1222         if (rdev->pm.pm_method == PM_METHOD_DPM)
1223                 return radeon_pm_init_dpm(rdev);
1224         else
1225                 return radeon_pm_init_old(rdev);
1226 }
1227
1228 static void radeon_pm_fini_old(struct radeon_device *rdev)
1229 {
1230         if (rdev->pm.num_power_states > 1) {
1231                 DRM_UNLOCK(rdev->ddev); /* Work around LOR. */
1232                 lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE);
1233                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1234                         rdev->pm.profile = PM_PROFILE_DEFAULT;
1235                         radeon_pm_update_profile(rdev);
1236                         radeon_pm_set_clocks(rdev);
1237                 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1238                         /* reset default clocks */
1239                         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1240                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1241                         radeon_pm_set_clocks(rdev);
1242                 }
1243                 lockmgr(&rdev->pm.mutex, LK_RELEASE);
1244                 DRM_LOCK(rdev->ddev);
1245
1246 #ifdef DUMBBELL_WIP
1247                 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1248
1249                 device_remove_file(rdev->dev, &dev_attr_power_profile);
1250                 device_remove_file(rdev->dev, &dev_attr_power_method);
1251 #endif /* DUMBBELL_WIP */
1252         }
1253
1254         if (rdev->pm.power_state) {
1255                 int i;
1256                 for (i = 0; i < rdev->pm.num_power_states; ++i) {
1257                         drm_free(rdev->pm.power_state[i].clock_info,
1258                                  M_DRM);
1259                 }
1260                 drm_free(rdev->pm.power_state, M_DRM);
1261                 rdev->pm.power_state = NULL;
1262                 rdev->pm.num_power_states = 0;
1263         }
1264
1265         radeon_hwmon_fini(rdev);
1266 }
1267
1268 static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1269 {
1270         if (rdev->pm.num_power_states > 1) {
1271                 lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE);
1272                 radeon_dpm_disable(rdev);
1273                 lockmgr(&rdev->pm.mutex, LK_RELEASE);
1274
1275 #ifdef TODO_DEVICE_FILE
1276                 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
1277                 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1278                 /* XXX backwards compat */
1279                 device_remove_file(rdev->dev, &dev_attr_power_profile);
1280                 device_remove_file(rdev->dev, &dev_attr_power_method);
1281 #endif
1282         }
1283         radeon_dpm_fini(rdev);
1284
1285         if (rdev->pm.power_state)
1286                 kfree(rdev->pm.power_state);
1287
1288         radeon_hwmon_fini(rdev);
1289 }
1290
1291 void radeon_pm_fini(struct radeon_device *rdev)
1292 {
1293         if (rdev->pm.pm_method == PM_METHOD_DPM)
1294                 radeon_pm_fini_dpm(rdev);
1295         else
1296                 radeon_pm_fini_old(rdev);
1297 }
1298
1299 static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
1300 {
1301         struct drm_device *ddev = rdev->ddev;
1302         struct drm_crtc *crtc;
1303         struct radeon_crtc *radeon_crtc;
1304
1305         if (rdev->pm.num_power_states < 2)
1306                 return;
1307
1308         lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE);
1309
1310         rdev->pm.active_crtcs = 0;
1311         rdev->pm.active_crtc_count = 0;
1312         list_for_each_entry(crtc,
1313                 &ddev->mode_config.crtc_list, head) {
1314                 radeon_crtc = to_radeon_crtc(crtc);
1315                 if (radeon_crtc->enabled) {
1316                         rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
1317                         rdev->pm.active_crtc_count++;
1318                 }
1319         }
1320
1321         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1322                 radeon_pm_update_profile(rdev);
1323                 radeon_pm_set_clocks(rdev);
1324         } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1325                 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1326                         if (rdev->pm.active_crtc_count > 1) {
1327                                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1328 #ifdef DUMBBELL_WIP
1329                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1330 #endif /* DUMBBELL_WIP */
1331
1332                                         rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1333                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1334                                         radeon_pm_get_dynpm_state(rdev);
1335                                         radeon_pm_set_clocks(rdev);
1336
1337                                         DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
1338                                 }
1339                         } else if (rdev->pm.active_crtc_count == 1) {
1340                                 /* TODO: Increase clocks if needed for current mode */
1341
1342                                 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1343                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1344                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1345                                         radeon_pm_get_dynpm_state(rdev);
1346                                         radeon_pm_set_clocks(rdev);
1347
1348 #ifdef DUMBBELL_WIP
1349                                         schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1350                                                               msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1351 #endif /* DUMBBELL_WIP */
1352                                 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1353                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1354 #ifdef DUMBBELL_WIP
1355                                         schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1356                                                               msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1357 #endif /* DUMBBELL_WIP */
1358                                         DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
1359                                 }
1360                         } else { /* count == 0 */
1361                                 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1362 #ifdef DUMBBELL_WIP
1363                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1364 #endif /* DUMBBELL_WIP */
1365
1366                                         rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1367                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1368                                         radeon_pm_get_dynpm_state(rdev);
1369                                         radeon_pm_set_clocks(rdev);
1370                                 }
1371                         }
1372                 }
1373         }
1374
1375         lockmgr(&rdev->pm.mutex, LK_RELEASE);
1376 }
1377
1378 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1379 {
1380         struct drm_device *ddev = rdev->ddev;
1381         struct drm_crtc *crtc;
1382         struct radeon_crtc *radeon_crtc;
1383
1384         lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE);
1385
1386         /* update active crtc counts */
1387         rdev->pm.dpm.new_active_crtcs = 0;
1388         rdev->pm.dpm.new_active_crtc_count = 0;
1389         list_for_each_entry(crtc,
1390                 &ddev->mode_config.crtc_list, head) {
1391                 radeon_crtc = to_radeon_crtc(crtc);
1392                 if (crtc->enabled) {
1393                         rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1394                         rdev->pm.dpm.new_active_crtc_count++;
1395                 }
1396         }
1397
1398         /* update battery/ac status */
1399         if (power_profile_get_state() == POWER_PROFILE_PERFORMANCE)
1400                 rdev->pm.dpm.ac_power = true;
1401         else
1402                 rdev->pm.dpm.ac_power = false;
1403
1404         radeon_dpm_change_power_state_locked(rdev);
1405
1406         lockmgr(&rdev->pm.mutex, LK_RELEASE);
1407 }
1408
1409 void radeon_pm_compute_clocks(struct radeon_device *rdev)
1410 {
1411         if (rdev->pm.pm_method == PM_METHOD_DPM)
1412                 radeon_pm_compute_clocks_dpm(rdev);
1413         else
1414                 radeon_pm_compute_clocks_old(rdev);
1415 }
1416
1417 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
1418 {
1419         int  crtc, vpos, hpos, vbl_status;
1420         bool in_vbl = true;
1421
1422         /* Iterate over all active crtc's. All crtc's must be in vblank,
1423          * otherwise return in_vbl == false.
1424          */
1425         for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1426                 if (rdev->pm.active_crtcs & (1 << crtc)) {
1427                         vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos);
1428                         if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
1429                             !(vbl_status & DRM_SCANOUTPOS_INVBL))
1430                                 in_vbl = false;
1431                 }
1432         }
1433
1434         return in_vbl;
1435 }
1436
1437 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
1438 {
1439         u32 stat_crtc = 0;
1440         bool in_vbl = radeon_pm_in_vbl(rdev);
1441
1442         if (in_vbl == false)
1443                 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
1444                          finish ? "exit" : "entry");
1445         return in_vbl;
1446 }
1447
1448 #ifdef DUMBBELL_WIP
1449 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
1450 {
1451         struct radeon_device *rdev;
1452         int resched;
1453         rdev = container_of(work, struct radeon_device,
1454                                 pm.dynpm_idle_work.work);
1455
1456         resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1457         lockmgr(&rdev->pm.mutex, LK_EXCLUSIVE);
1458         if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1459                 int not_processed = 0;
1460                 int i;
1461
1462                 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1463                         struct radeon_ring *ring = &rdev->ring[i];
1464
1465                         if (ring->ready) {
1466                                 not_processed += radeon_fence_count_emitted(rdev, i);
1467                                 if (not_processed >= 3)
1468                                         break;
1469                         }
1470                 }
1471
1472                 if (not_processed >= 3) { /* should upclock */
1473                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1474                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1475                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1476                                    rdev->pm.dynpm_can_upclock) {
1477                                 rdev->pm.dynpm_planned_action =
1478                                         DYNPM_ACTION_UPCLOCK;
1479                                 rdev->pm.dynpm_action_timeout = jiffies +
1480                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1481                         }
1482                 } else if (not_processed == 0) { /* should downclock */
1483                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1484                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1485                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1486                                    rdev->pm.dynpm_can_downclock) {
1487                                 rdev->pm.dynpm_planned_action =
1488                                         DYNPM_ACTION_DOWNCLOCK;
1489                                 rdev->pm.dynpm_action_timeout = jiffies +
1490                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1491                         }
1492                 }
1493
1494                 /* Note, radeon_pm_set_clocks is called with static_switch set
1495                  * to false since we want to wait for vbl to avoid flicker.
1496                  */
1497                 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1498                     jiffies > rdev->pm.dynpm_action_timeout) {
1499                         radeon_pm_get_dynpm_state(rdev);
1500                         radeon_pm_set_clocks(rdev);
1501                 }
1502
1503                 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1504                                       msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1505         }
1506         lockmgr(&rdev->pm.mutex, LK_RELEASE);
1507         ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1508 }
1509 #endif /* DUMBBELL_WIP */
1510
1511 /*
1512  * Debugfs info
1513  */
1514 #if defined(CONFIG_DEBUG_FS)
1515
1516 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
1517 {
1518         struct drm_info_node *node = (struct drm_info_node *) m->private;
1519         struct drm_device *dev = node->minor->dev;
1520         struct radeon_device *rdev = dev->dev_private;
1521
1522         if (rdev->pm.dpm_enabled) {
1523                 spin_lock(&rdev->pm.mutex);
1524                 if (rdev->asic->dpm.debugfs_print_current_performance_level)
1525                         radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1526                 else
1527                         seq_printf(m, "Debugfs support not implemented for this asic\n");
1528                 spin_unlock(&rdev->pm.mutex);
1529         } else {
1530                 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1531                 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1532                 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1533                         seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1534                 else
1535                         seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1536                 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1537                 if (rdev->asic->pm.get_memory_clock)
1538                         seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1539                 if (rdev->pm.current_vddc)
1540                         seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1541                 if (rdev->asic->pm.get_pcie_lanes)
1542                         seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1543         }
1544
1545         return 0;
1546 }
1547
1548 static struct drm_info_list radeon_pm_info_list[] = {
1549         {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
1550 };
1551 #endif
1552
1553 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
1554 {
1555 #if defined(CONFIG_DEBUG_FS)
1556         return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
1557 #else
1558         return 0;
1559 #endif
1560 }