sys/dev/drm/i915/i915_gem.c

   1 /*-
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  * Copyright (c) 2011 The FreeBSD Foundation
  27  * All rights reserved.
  28  *
  29  * This software was developed by Konstantin Belousov under sponsorship from
  30  * the FreeBSD Foundation.
  31  *
  32  * Redistribution and use in source and binary forms, with or without
  33  * modification, are permitted provided that the following conditions
  34  * are met:
  35  * 1. Redistributions of source code must retain the above copyright
  36  *    notice, this list of conditions and the following disclaimer.
  37  * 2. Redistributions in binary form must reproduce the above copyright
  38  *    notice, this list of conditions and the following disclaimer in the
  39  *    documentation and/or other materials provided with the distribution.
  40  *
  41  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  42  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  43  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  44  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  45  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  46  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  47  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  48  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  49  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  50  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  51  * SUCH DAMAGE.
  52  *
  53  * $FreeBSD: head/sys/dev/drm2/i915/i915_gem.c 253497 2013-07-20 13:52:40Z kib $
  54  */
  55
  56 #include <sys/resourcevar.h>
  57 #include <sys/sfbuf.h>
  58
  59 #include <drm/drmP.h>
  60 #include <drm/i915_drm.h>
  61 #include "i915_drv.h"
  62 #include "intel_drv.h"
  63 #include "intel_ringbuffer.h"
  64
  65 static void i915_gem_object_flush_cpu_write_domain(
  66     struct drm_i915_gem_object *obj);
  67 static uint32_t i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size,
  68     int tiling_mode);
  69 static uint32_t i915_gem_get_gtt_alignment(struct drm_device *dev,
  70     uint32_t size, int tiling_mode);
  71 static int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
  72     unsigned alignment, bool map_and_fenceable);
  73 static int i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
  74     int flags);
  75 static void i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj);
  76 static int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj,
  77     bool write);
  78 static void i915_gem_object_set_to_full_cpu_read_domain(
  79     struct drm_i915_gem_object *obj);
  80 static int i915_gem_object_set_cpu_read_domain_range(
  81     struct drm_i915_gem_object *obj, uint64_t offset, uint64_t size);
  82 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj);
  83 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
  84 static int i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj);
  85 static bool i915_gem_object_is_inactive(struct drm_i915_gem_object *obj);
  86 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj);
  87 static vm_page_t i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex);
  88 static void i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
  89     uint32_t flush_domains);
  90 static void i915_gem_clear_fence_reg(struct drm_device *dev,
  91     struct drm_i915_fence_reg *reg);
  92 static void i915_gem_reset_fences(struct drm_device *dev);
  93 static void i915_gem_retire_task_handler(void *arg, int pending);
  94 static int i915_gem_phys_pwrite(struct drm_device *dev,
  95     struct drm_i915_gem_object *obj, uint64_t data_ptr, uint64_t offset,
  96     uint64_t size, struct drm_file *file_priv);
  97 static void i915_gem_lowmem(void *arg);
  98
  99 MALLOC_DEFINE(DRM_I915_GEM, "i915gem", "Allocations from i915 gem");
 100 long i915_gem_wired_pages_cnt;
 101
 102 static void
 103 i915_gem_info_add_obj(struct drm_i915_private *dev_priv, size_t size)
 104 {
 105
 106         dev_priv->mm.object_count++;
 107         dev_priv->mm.object_memory += size;
 108 }
 109
 110 static void
 111 i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, size_t size)
 112 {
 113
 114         dev_priv->mm.object_count--;
 115         dev_priv->mm.object_memory -= size;
 116 }
 117
 118 static int
 119 i915_gem_wait_for_error(struct drm_device *dev)
 120 {
 121         struct drm_i915_private *dev_priv = dev->dev_private;
 122         int ret;
 123
 124         if (!atomic_read(&dev_priv->mm.wedged))
 125                 return 0;
 126
 127         lockmgr(&dev_priv->error_completion_lock, LK_EXCLUSIVE);
 128         while (dev_priv->error_completion == 0) {
 129                 ret = -lksleep(&dev_priv->error_completion,
 130                     &dev_priv->error_completion_lock, PCATCH, "915wco", 0);
 131                 if (ret != 0) {
 132                         lockmgr(&dev_priv->error_completion_lock, LK_RELEASE);
 133                         return (ret);
 134                 }
 135         }
 136         lockmgr(&dev_priv->error_completion_lock, LK_RELEASE);
 137
 138         if (atomic_read(&dev_priv->mm.wedged)) {
 139                 /* GPU is hung, bump the completion count to account for
 140                  * the token we just consumed so that we never hit zero and
 141                  * end up waiting upon a subsequent completion event that
 142                  * will never happen.
 143                  */
 144                 lockmgr(&dev_priv->error_completion_lock, LK_EXCLUSIVE);
 145                 dev_priv->error_completion++;
 146                 lockmgr(&dev_priv->error_completion_lock, LK_RELEASE);
 147         }
 148         return 0;
 149 }
 150
 151 int
 152 i915_mutex_lock_interruptible(struct drm_device *dev)
 153 {
 154         struct drm_i915_private *dev_priv;
 155         int ret;
 156
 157         dev_priv = dev->dev_private;
 158         ret = i915_gem_wait_for_error(dev);
 159         if (ret != 0)
 160                 return (ret);
 161
 162         /*
 163          * interruptible shall it be. might indeed be if dev_lock is
 164          * changed to sx
 165          */
 166         ret = lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL);
 167         if (ret != 0)
 168                 return (-ret);
 169
 170         return (0);
 171 }
 172
 173
 174 static void
 175 i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
 176 {
 177         struct drm_device *dev;
 178         drm_i915_private_t *dev_priv;
 179         int ret;
 180
 181         dev = obj->base.dev;
 182         dev_priv = dev->dev_private;
 183
 184         ret = i915_gem_object_unbind(obj);
 185         if (ret == -ERESTART) {
 186                 list_move(&obj->mm_list, &dev_priv->mm.deferred_free_list);
 187                 return;
 188         }
 189
 190         drm_gem_free_mmap_offset(&obj->base);
 191         drm_gem_object_release(&obj->base);
 192         i915_gem_info_remove_obj(dev_priv, obj->base.size);
 193
 194         drm_free(obj->page_cpu_valid, DRM_I915_GEM);
 195         drm_free(obj->bit_17, DRM_I915_GEM);
 196         drm_free(obj, DRM_I915_GEM);
 197 }
 198
 199 void
 200 i915_gem_free_object(struct drm_gem_object *gem_obj)
 201 {
 202         struct drm_i915_gem_object *obj;
 203         struct drm_device *dev;
 204
 205         obj = to_intel_bo(gem_obj);
 206         dev = obj->base.dev;
 207
 208         while (obj->pin_count > 0)
 209                 i915_gem_object_unpin(obj);
 210
 211         if (obj->phys_obj != NULL)
 212                 i915_gem_detach_phys_object(dev, obj);
 213
 214         i915_gem_free_object_tail(obj);
 215 }
 216
 217 static void
 218 init_ring_lists(struct intel_ring_buffer *ring)
 219 {
 220
 221         INIT_LIST_HEAD(&ring->active_list);
 222         INIT_LIST_HEAD(&ring->request_list);
 223         INIT_LIST_HEAD(&ring->gpu_write_list);
 224 }
 225
 226 void
 227 i915_gem_load(struct drm_device *dev)
 228 {
 229         int i;
 230         drm_i915_private_t *dev_priv = dev->dev_private;
 231
 232         INIT_LIST_HEAD(&dev_priv->mm.active_list);
 233         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
 234         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
 235         INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
 236         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
 237         INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
 238         INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
 239         for (i = 0; i < I915_NUM_RINGS; i++)
 240                 init_ring_lists(&dev_priv->rings[i]);
 241         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
 242                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
 243         TIMEOUT_TASK_INIT(dev_priv->tq, &dev_priv->mm.retire_task, 0,
 244             i915_gem_retire_task_handler, dev_priv);
 245         dev_priv->error_completion = 0;
 246
 247         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
 248         if (IS_GEN3(dev)) {
 249                 I915_WRITE(MI_ARB_STATE,
 250                            _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
 251         }
 252
 253         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
 254
 255         /* Old X drivers will take 0-2 for front, back, depth buffers */
 256         if (!drm_core_check_feature(dev, DRIVER_MODESET))
 257                 dev_priv->fence_reg_start = 3;
 258
 259         if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
 260                 dev_priv->num_fence_regs = 16;
 261         else
 262                 dev_priv->num_fence_regs = 8;
 263
 264         /* Initialize fence registers to zero */
 265         i915_gem_reset_fences(dev);
 266
 267         i915_gem_detect_bit_6_swizzle(dev);
 268
 269         dev_priv->mm.interruptible = true;
 270
 271         dev_priv->mm.i915_lowmem = EVENTHANDLER_REGISTER(vm_lowmem,
 272             i915_gem_lowmem, dev, EVENTHANDLER_PRI_ANY);
 273 }
 274
 275 int
 276 i915_gem_do_init(struct drm_device *dev, unsigned long start,
 277     unsigned long mappable_end, unsigned long end)
 278 {
 279         drm_i915_private_t *dev_priv;
 280         unsigned long mappable;
 281         int error;
 282
 283         dev_priv = dev->dev_private;
 284         mappable = min(end, mappable_end) - start;
 285
 286         drm_mm_init(&dev_priv->mm.gtt_space, start, end - start);
 287
 288         dev_priv->mm.gtt_start = start;
 289         dev_priv->mm.gtt_mappable_end = mappable_end;
 290         dev_priv->mm.gtt_end = end;
 291         dev_priv->mm.gtt_total = end - start;
 292         dev_priv->mm.mappable_gtt_total = mappable;
 293
 294         /* Take over this portion of the GTT */
 295         intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
 296         device_printf(dev->dev,
 297             "taking over the fictitious range 0x%lx-0x%lx\n",
 298             dev->agp->base + start, dev->agp->base + start + mappable);
 299         error = -vm_phys_fictitious_reg_range(dev->agp->base + start,
 300             dev->agp->base + start + mappable, VM_MEMATTR_WRITE_COMBINING);
 301         return (error);
 302 }
 303
 304 int
 305 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 306     struct drm_file *file)
 307 {
 308         struct drm_i915_gem_init *args;
 309         drm_i915_private_t *dev_priv;
 310
 311         dev_priv = dev->dev_private;
 312         args = data;
 313
 314         if (args->gtt_start >= args->gtt_end ||
 315             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
 316                 return (-EINVAL);
 317
 318         /*
 319          * XXXKIB. The second-time initialization should be guarded
 320          * against.
 321          */
 322         lockmgr(&dev->dev_lock, LK_EXCLUSIVE|LK_RETRY|LK_CANRECURSE);
 323         i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end);
 324         lockmgr(&dev->dev_lock, LK_RELEASE);
 325
 326         return 0;
 327 }
 328
 329 int
 330 i915_gem_idle(struct drm_device *dev)
 331 {
 332         drm_i915_private_t *dev_priv;
 333         int ret;
 334
 335         dev_priv = dev->dev_private;
 336         if (dev_priv->mm.suspended)
 337                 return (0);
 338
 339         ret = i915_gpu_idle(dev, true);
 340         if (ret != 0)
 341                 return (ret);
 342
 343         /* Under UMS, be paranoid and evict. */
 344         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
 345                 ret = i915_gem_evict_inactive(dev, false);
 346                 if (ret != 0)
 347                         return ret;
 348         }
 349
 350         i915_gem_reset_fences(dev);
 351
 352         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
 353          * We need to replace this with a semaphore, or something.
 354          * And not confound mm.suspended!
 355          */
 356         dev_priv->mm.suspended = 1;
 357         callout_stop(&dev_priv->hangcheck_timer);
 358
 359         i915_kernel_lost_context(dev);
 360         i915_gem_cleanup_ringbuffer(dev);
 361
 362         /* Cancel the retire work handler, which should be idle now. */
 363         taskqueue_cancel_timeout(dev_priv->tq, &dev_priv->mm.retire_task, NULL);
 364         return (ret);
 365 }
 366
 367 void
 368 i915_gem_init_swizzling(struct drm_device *dev)
 369 {
 370         drm_i915_private_t *dev_priv;
 371
 372         dev_priv = dev->dev_private;
 373
 374         if (INTEL_INFO(dev)->gen < 5 ||
 375             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
 376                 return;
 377
 378         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
 379                                  DISP_TILE_SURFACE_SWIZZLING);
 380
 381         if (IS_GEN5(dev))
 382                 return;
 383
 384         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
 385         if (IS_GEN6(dev))
 386                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
 387         else
 388                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
 389 }
 390
 391 int
 392 i915_gem_init_hw(struct drm_device *dev)
 393 {
 394         drm_i915_private_t *dev_priv;
 395         int ret;
 396
 397         dev_priv = dev->dev_private;
 398
 399         i915_gem_init_swizzling(dev);
 400
 401         ret = intel_init_render_ring_buffer(dev);
 402         if (ret != 0)
 403                 return (ret);
 404
 405         if (HAS_BSD(dev)) {
 406                 ret = intel_init_bsd_ring_buffer(dev);
 407                 if (ret != 0)
 408                         goto cleanup_render_ring;
 409         }
 410
 411         if (HAS_BLT(dev)) {
 412                 ret = intel_init_blt_ring_buffer(dev);
 413                 if (ret != 0)
 414                         goto cleanup_bsd_ring;
 415         }
 416
 417         dev_priv->next_seqno = 1;
 418         i915_gem_init_ppgtt(dev);
 419         return (0);
 420
 421 cleanup_bsd_ring:
 422         intel_cleanup_ring_buffer(&dev_priv->rings[VCS]);
 423 cleanup_render_ring:
 424         intel_cleanup_ring_buffer(&dev_priv->rings[RCS]);
 425         return (ret);
 426 }
 427
 428 int
 429 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 430     struct drm_file *file)
 431 {
 432         struct drm_i915_private *dev_priv;
 433         struct drm_i915_gem_get_aperture *args;
 434         struct drm_i915_gem_object *obj;
 435         size_t pinned;
 436
 437         dev_priv = dev->dev_private;
 438         args = data;
 439
 440         if (!(dev->driver->driver_features & DRIVER_GEM))
 441                 return (-ENODEV);
 442
 443         pinned = 0;
 444         DRM_LOCK(dev);
 445         list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
 446                 pinned += obj->gtt_space->size;
 447         DRM_UNLOCK(dev);
 448
 449         args->aper_size = dev_priv->mm.gtt_total;
 450         args->aper_available_size = args->aper_size - pinned;
 451
 452         return (0);
 453 }
 454
 455 int
 456 i915_gem_object_pin(struct drm_i915_gem_object *obj, uint32_t alignment,
 457      bool map_and_fenceable)
 458 {
 459         struct drm_device *dev;
 460         struct drm_i915_private *dev_priv;
 461         int ret;
 462
 463         dev = obj->base.dev;
 464         dev_priv = dev->dev_private;
 465
 466         KASSERT(obj->pin_count != DRM_I915_GEM_OBJECT_MAX_PIN_COUNT,
 467             ("Max pin count"));
 468
 469         if (obj->gtt_space != NULL) {
 470                 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
 471                     (map_and_fenceable && !obj->map_and_fenceable)) {
 472                         DRM_DEBUG("bo is already pinned with incorrect alignment:"
 473                              " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
 474                              " obj->map_and_fenceable=%d\n",
 475                              obj->gtt_offset, alignment,
 476                              map_and_fenceable,
 477                              obj->map_and_fenceable);
 478                         ret = i915_gem_object_unbind(obj);
 479                         if (ret != 0)
 480                                 return (ret);
 481                 }
 482         }
 483
 484         if (obj->gtt_space == NULL) {
 485                 ret = i915_gem_object_bind_to_gtt(obj, alignment,
 486                     map_and_fenceable);
 487                 if (ret)
 488                         return (ret);
 489         }
 490
 491         if (obj->pin_count++ == 0 && !obj->active)
 492                 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
 493         obj->pin_mappable |= map_and_fenceable;
 494
 495 #if 1
 496         KIB_NOTYET();
 497 #else
 498         WARN_ON(i915_verify_lists(dev));
 499 #endif
 500         return (0);
 501 }
 502
 503 void
 504 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
 505 {
 506         struct drm_device *dev;
 507         drm_i915_private_t *dev_priv;
 508
 509         dev = obj->base.dev;
 510         dev_priv = dev->dev_private;
 511
 512 #if 1
 513         KIB_NOTYET();
 514 #else
 515         WARN_ON(i915_verify_lists(dev));
 516 #endif
 517
 518         KASSERT(obj->pin_count != 0, ("zero pin count"));
 519         KASSERT(obj->gtt_space != NULL, ("No gtt mapping"));
 520
 521         if (--obj->pin_count == 0) {
 522                 if (!obj->active)
 523                         list_move_tail(&obj->mm_list,
 524                             &dev_priv->mm.inactive_list);
 525                 obj->pin_mappable = false;
 526         }
 527 #if 1
 528         KIB_NOTYET();
 529 #else
 530         WARN_ON(i915_verify_lists(dev));
 531 #endif
 532 }
 533
 534 int
 535 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
 536     struct drm_file *file)
 537 {
 538         struct drm_i915_gem_pin *args;
 539         struct drm_i915_gem_object *obj;
 540         struct drm_gem_object *gobj;
 541         int ret;
 542
 543         args = data;
 544
 545         ret = i915_mutex_lock_interruptible(dev);
 546         if (ret != 0)
 547                 return ret;
 548
 549         gobj = drm_gem_object_lookup(dev, file, args->handle);
 550         if (gobj == NULL) {
 551                 ret = -ENOENT;
 552                 goto unlock;
 553         }
 554         obj = to_intel_bo(gobj);
 555
 556         if (obj->madv != I915_MADV_WILLNEED) {
 557                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
 558                 ret = -EINVAL;
 559                 goto out;
 560         }
 561
 562         if (obj->pin_filp != NULL && obj->pin_filp != file) {
 563                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
 564                     args->handle);
 565                 ret = -EINVAL;
 566                 goto out;
 567         }
 568
 569         obj->user_pin_count++;
 570         obj->pin_filp = file;
 571         if (obj->user_pin_count == 1) {
 572                 ret = i915_gem_object_pin(obj, args->alignment, true);
 573                 if (ret != 0)
 574                         goto out;
 575         }
 576
 577         /* XXX - flush the CPU caches for pinned objects
 578          * as the X server doesn't manage domains yet
 579          */
 580         i915_gem_object_flush_cpu_write_domain(obj);
 581         args->offset = obj->gtt_offset;
 582 out:
 583         drm_gem_object_unreference(&obj->base);
 584 unlock:
 585         DRM_UNLOCK(dev);
 586         return (ret);
 587 }
 588
 589 int
 590 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
 591     struct drm_file *file)
 592 {
 593         struct drm_i915_gem_pin *args;
 594         struct drm_i915_gem_object *obj;
 595         int ret;
 596
 597         args = data;
 598         ret = i915_mutex_lock_interruptible(dev);
 599         if (ret != 0)
 600                 return (ret);
 601
 602         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 603         if (&obj->base == NULL) {
 604                 ret = -ENOENT;
 605                 goto unlock;
 606         }
 607
 608         if (obj->pin_filp != file) {
 609                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
 610                     args->handle);
 611                 ret = -EINVAL;
 612                 goto out;
 613         }
 614         obj->user_pin_count--;
 615         if (obj->user_pin_count == 0) {
 616                 obj->pin_filp = NULL;
 617                 i915_gem_object_unpin(obj);
 618         }
 619
 620 out:
 621         drm_gem_object_unreference(&obj->base);
 622 unlock:
 623         DRM_UNLOCK(dev);
 624         return (ret);
 625 }
 626
 627 int
 628 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
 629     struct drm_file *file)
 630 {
 631         struct drm_i915_gem_busy *args;
 632         struct drm_i915_gem_object *obj;
 633         struct drm_i915_gem_request *request;
 634         int ret;
 635
 636         args = data;
 637
 638         ret = i915_mutex_lock_interruptible(dev);
 639         if (ret != 0)
 640                 return ret;
 641
 642         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 643         if (&obj->base == NULL) {
 644                 ret = -ENOENT;
 645                 goto unlock;
 646         }
 647
 648         args->busy = obj->active;
 649         if (args->busy) {
 650                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
 651                         ret = i915_gem_flush_ring(obj->ring,
 652                             0, obj->base.write_domain);
 653                 } else if (obj->ring->outstanding_lazy_request ==
 654                     obj->last_rendering_seqno) {
 655                         request = kmalloc(sizeof(*request), DRM_I915_GEM,
 656                             M_WAITOK | M_ZERO);
 657                         ret = i915_add_request(obj->ring, NULL, request);
 658                         if (ret != 0)
 659                                 drm_free(request, DRM_I915_GEM);
 660                 }
 661
 662                 i915_gem_retire_requests_ring(obj->ring);
 663                 args->busy = obj->active;
 664         }
 665
 666         drm_gem_object_unreference(&obj->base);
 667 unlock:
 668         DRM_UNLOCK(dev);
 669         return (ret);
 670 }
 671
 672 /* Throttle our rendering by waiting until the ring has completed our requests
 673  * emitted over 20 msec ago.
 674  *
 675  * Note that if we were to use the current jiffies each time around the loop,
 676  * we wouldn't escape the function with any frames outstanding if the time to
 677  * render a frame was over 20ms.
 678  *
 679  * This should get us reasonable parallelism between CPU and GPU but also
 680  * relatively low latency when blocking on a particular request to finish.
 681  */
 682 static int
 683 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
 684 {
 685         struct drm_i915_private *dev_priv = dev->dev_private;
 686         struct drm_i915_file_private *file_priv = file->driver_priv;
 687         unsigned long recent_enough = ticks - (20 * hz / 1000);
 688         struct drm_i915_gem_request *request;
 689         struct intel_ring_buffer *ring = NULL;
 690         u32 seqno = 0;
 691         int ret;
 692
 693         dev_priv = dev->dev_private;
 694         if (atomic_read(&dev_priv->mm.wedged))
 695                 return -EIO;
 696
 697         recent_enough = ticks - (20 * hz / 1000);
 698         ring = NULL;
 699         seqno = 0;
 700
 701         spin_lock(&file_priv->mm.lock);
 702         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
 703                 if (time_after_eq(request->emitted_jiffies, recent_enough))
 704                         break;
 705
 706                 ring = request->ring;
 707                 seqno = request->seqno;
 708         }
 709         spin_unlock(&file_priv->mm.lock);
 710
 711         if (seqno == 0)
 712                 return 0;
 713
 714         ret = 0;
 715         lockmgr(&ring->irq_lock, LK_EXCLUSIVE);
 716         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
 717                 if (ring->irq_get(ring)) {
 718                         while (ret == 0 &&
 719                             !(i915_seqno_passed(ring->get_seqno(ring), seqno) ||
 720                             atomic_read(&dev_priv->mm.wedged)))
 721                                 ret = -lksleep(ring, &ring->irq_lock, PCATCH,
 722                                     "915thr", 0);
 723                         ring->irq_put(ring);
 724                         if (ret == 0 && atomic_read(&dev_priv->mm.wedged))
 725                                 ret = -EIO;
 726                 } else if (_intel_wait_for(dev,
 727                     i915_seqno_passed(ring->get_seqno(ring), seqno) ||
 728                     atomic_read(&dev_priv->mm.wedged), 3000, 0, "915rtr")) {
 729                         ret = -EBUSY;
 730                 }
 731         }
 732         lockmgr(&ring->irq_lock, LK_RELEASE);
 733
 734         if (ret == 0)
 735                 taskqueue_enqueue_timeout(dev_priv->tq,
 736                     &dev_priv->mm.retire_task, 0);
 737
 738         return ret;
 739 }
 740
 741 int
 742 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
 743     struct drm_file *file_priv)
 744 {
 745
 746         return (i915_gem_ring_throttle(dev, file_priv));
 747 }
 748
 749 int
 750 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
 751                        struct drm_file *file_priv)
 752 {
 753         struct drm_i915_gem_madvise *args = data;
 754         struct drm_i915_gem_object *obj;
 755         int ret;
 756
 757         switch (args->madv) {
 758         case I915_MADV_DONTNEED:
 759         case I915_MADV_WILLNEED:
 760             break;
 761         default:
 762             return -EINVAL;
 763         }
 764
 765         ret = i915_mutex_lock_interruptible(dev);
 766         if (ret)
 767                 return ret;
 768
 769         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
 770         if (&obj->base == NULL) {
 771                 ret = -ENOENT;
 772                 goto unlock;
 773         }
 774
 775         if (obj->pin_count) {
 776                 ret = -EINVAL;
 777                 goto out;
 778         }
 779
 780         if (obj->madv != __I915_MADV_PURGED)
 781                 obj->madv = args->madv;
 782
 783         /* if the object is no longer attached, discard its backing storage */
 784         if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
 785                 i915_gem_object_truncate(obj);
 786
 787         args->retained = obj->madv != __I915_MADV_PURGED;
 788
 789 out:
 790         drm_gem_object_unreference(&obj->base);
 791 unlock:
 792         DRM_UNLOCK(dev);
 793         return ret;
 794 }
 795
 796 void
 797 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
 798 {
 799         drm_i915_private_t *dev_priv;
 800         int i;
 801
 802         dev_priv = dev->dev_private;
 803         for (i = 0; i < I915_NUM_RINGS; i++)
 804                 intel_cleanup_ring_buffer(&dev_priv->rings[i]);
 805 }
 806
 807 int
 808 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
 809                        struct drm_file *file_priv)
 810 {
 811         drm_i915_private_t *dev_priv = dev->dev_private;
 812         int ret;
 813
 814         if (drm_core_check_feature(dev, DRIVER_MODESET))
 815                 return 0;
 816
 817         if (atomic_read(&dev_priv->mm.wedged)) {
 818                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
 819                 atomic_set(&dev_priv->mm.wedged, 0);
 820         }
 821
 822         DRM_LOCK(dev);
 823         dev_priv->mm.suspended = 0;
 824
 825         ret = i915_gem_init_hw(dev);
 826         if (ret != 0) {
 827                 DRM_UNLOCK(dev);
 828                 return ret;
 829         }
 830
 831         KASSERT(list_empty(&dev_priv->mm.active_list), ("active list"));
 832         DRM_UNLOCK(dev);
 833
 834         ret = drm_irq_install(dev);
 835         if (ret)
 836                 goto cleanup_ringbuffer;
 837
 838         return 0;
 839
 840 cleanup_ringbuffer:
 841         DRM_LOCK(dev);
 842         i915_gem_cleanup_ringbuffer(dev);
 843         dev_priv->mm.suspended = 1;
 844         DRM_UNLOCK(dev);
 845
 846         return ret;
 847 }
 848
 849 int
 850 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
 851     struct drm_file *file_priv)
 852 {
 853
 854         if (drm_core_check_feature(dev, DRIVER_MODESET))
 855                 return 0;
 856
 857         drm_irq_uninstall(dev);
 858         return (i915_gem_idle(dev));
 859 }
 860
 861 int
 862 i915_gem_create(struct drm_file *file, struct drm_device *dev, uint64_t size,
 863     uint32_t *handle_p)
 864 {
 865         struct drm_i915_gem_object *obj;
 866         uint32_t handle;
 867         int ret;
 868
 869         size = roundup(size, PAGE_SIZE);
 870         if (size == 0)
 871                 return (-EINVAL);
 872
 873         obj = i915_gem_alloc_object(dev, size);
 874         if (obj == NULL)
 875                 return (-ENOMEM);
 876
 877         handle = 0;
 878         ret = drm_gem_handle_create(file, &obj->base, &handle);
 879         if (ret != 0) {
 880                 drm_gem_object_release(&obj->base);
 881                 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
 882                 drm_free(obj, DRM_I915_GEM);
 883                 return (-ret);
 884         }
 885
 886         /* drop reference from allocate - handle holds it now */
 887         drm_gem_object_unreference(&obj->base);
 888         *handle_p = handle;
 889         return (0);
 890 }
 891
 892 int
 893 i915_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
 894     struct drm_mode_create_dumb *args)
 895 {
 896
 897         /* have to work out size/pitch and return them */
 898         args->pitch = roundup2(args->width * ((args->bpp + 7) / 8), 64);
 899         args->size = args->pitch * args->height;
 900         return (i915_gem_create(file, dev, args->size, &args->handle));
 901 }
 902
 903 int
 904 i915_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
 905     uint32_t handle)
 906 {
 907
 908         return (drm_gem_handle_delete(file, handle));
 909 }
 910
 911 int
 912 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 913     struct drm_file *file)
 914 {
 915         struct drm_i915_gem_create *args = data;
 916
 917         return (i915_gem_create(file, dev, args->size, &args->handle));
 918 }
 919
 920 static inline void vm_page_reference(vm_page_t m)
 921 {
 922         vm_page_flag_set(m, PG_REFERENCED);
 923 }
 924
 925 static int
 926 i915_gem_swap_io(struct drm_device *dev, struct drm_i915_gem_object *obj,
 927     uint64_t data_ptr, uint64_t size, uint64_t offset, enum uio_rw rw,
 928     struct drm_file *file)
 929 {
 930         vm_object_t vm_obj;
 931         vm_page_t m;
 932         struct sf_buf *sf;
 933         vm_offset_t mkva;
 934         vm_pindex_t obj_pi;
 935         int cnt, do_bit17_swizzling, length, obj_po, ret, swizzled_po;
 936
 937         if (obj->gtt_offset != 0 && rw == UIO_READ)
 938                 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 939         else
 940                 do_bit17_swizzling = 0;
 941
 942         obj->dirty = 1;
 943         vm_obj = obj->base.vm_obj;
 944         ret = 0;
 945
 946         VM_OBJECT_LOCK(vm_obj);
 947         vm_object_pip_add(vm_obj, 1);
 948         while (size > 0) {
 949                 obj_pi = OFF_TO_IDX(offset);
 950                 obj_po = offset & PAGE_MASK;
 951
 952                 m = i915_gem_wire_page(vm_obj, obj_pi);
 953                 VM_OBJECT_UNLOCK(vm_obj);
 954
 955                 sf = sf_buf_alloc(m);
 956                 mkva = sf_buf_kva(sf);
 957                 length = min(size, PAGE_SIZE - obj_po);
 958                 while (length > 0) {
 959                         if (do_bit17_swizzling &&
 960                             (VM_PAGE_TO_PHYS(m) & (1 << 17)) != 0) {
 961                                 cnt = roundup2(obj_po + 1, 64);
 962                                 cnt = min(cnt - obj_po, length);
 963                                 swizzled_po = obj_po ^ 64;
 964                         } else {
 965                                 cnt = length;
 966                                 swizzled_po = obj_po;
 967                         }
 968                         if (rw == UIO_READ)
 969                                 ret = -copyout_nofault(
 970                                     (char *)mkva + swizzled_po,
 971                                     (void *)(uintptr_t)data_ptr, cnt);
 972                         else
 973                                 ret = -copyin_nofault(
 974                                     (void *)(uintptr_t)data_ptr,
 975                                     (char *)mkva + swizzled_po, cnt);
 976                         if (ret != 0)
 977                                 break;
 978                         data_ptr += cnt;
 979                         size -= cnt;
 980                         length -= cnt;
 981                         offset += cnt;
 982                         obj_po += cnt;
 983                 }
 984                 sf_buf_free(sf);
 985                 VM_OBJECT_LOCK(vm_obj);
 986                 if (rw == UIO_WRITE)
 987                         vm_page_dirty(m);
 988                 vm_page_reference(m);
 989                 vm_page_busy_wait(m, FALSE, "i915gem");
 990                 vm_page_unwire(m, 1);
 991                 vm_page_wakeup(m);
 992                 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
 993
 994                 if (ret != 0)
 995                         break;
 996         }
 997         vm_object_pip_wakeup(vm_obj);
 998         VM_OBJECT_UNLOCK(vm_obj);
 999
1000         return (ret);
1001 }
1002
1003 static int
1004 i915_gem_gtt_write(struct drm_device *dev, struct drm_i915_gem_object *obj,
1005     uint64_t data_ptr, uint64_t size, uint64_t offset, struct drm_file *file)
1006 {
1007         vm_offset_t mkva;
1008         int ret;
1009
1010         /*
1011          * Pass the unaligned physical address and size to pmap_mapdev_attr()
1012          * so it can properly calculate whether an extra page needs to be
1013          * mapped or not to cover the requested range.  The function will
1014          * add the page offset into the returned mkva for us.
1015          */
1016         mkva = (vm_offset_t)pmap_mapdev_attr(dev->agp->base + obj->gtt_offset +
1017             offset, size, PAT_WRITE_COMBINING);
1018         ret = -copyin_nofault((void *)(uintptr_t)data_ptr, (char *)mkva, size);
1019         pmap_unmapdev(mkva, size);
1020         return (ret);
1021 }
1022
1023 static int
1024 i915_gem_obj_io(struct drm_device *dev, uint32_t handle, uint64_t data_ptr,
1025     uint64_t size, uint64_t offset, enum uio_rw rw, struct drm_file *file)
1026 {
1027         struct drm_i915_gem_object *obj;
1028         vm_page_t *ma;
1029         vm_offset_t start, end;
1030         int npages, ret;
1031
1032         if (size == 0)
1033                 return (0);
1034         start = trunc_page(data_ptr);
1035         end = round_page(data_ptr + size);
1036         npages = howmany(end - start, PAGE_SIZE);
1037         ma = kmalloc(npages * sizeof(vm_page_t), DRM_I915_GEM, M_WAITOK |
1038             M_ZERO);
1039         npages = vm_fault_quick_hold_pages(&curproc->p_vmspace->vm_map,
1040             (vm_offset_t)data_ptr, size,
1041             (rw == UIO_READ ? VM_PROT_WRITE : 0 ) | VM_PROT_READ, ma, npages);
1042         if (npages == -1) {
1043                 ret = -EFAULT;
1044                 goto free_ma;
1045         }
1046
1047         ret = i915_mutex_lock_interruptible(dev);
1048         if (ret != 0)
1049                 goto unlocked;
1050
1051         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1052         if (&obj->base == NULL) {
1053                 ret = -ENOENT;
1054                 goto unlock;
1055         }
1056         if (offset > obj->base.size || size > obj->base.size - offset) {
1057                 ret = -EINVAL;
1058                 goto out;
1059         }
1060
1061         if (rw == UIO_READ) {
1062                 ret = i915_gem_object_set_cpu_read_domain_range(obj,
1063                     offset, size);
1064                 if (ret != 0)
1065                         goto out;
1066                 ret = i915_gem_swap_io(dev, obj, data_ptr, size, offset,
1067                     UIO_READ, file);
1068         } else {
1069                 if (obj->phys_obj) {
1070                         ret = i915_gem_phys_pwrite(dev, obj, data_ptr, offset,
1071                             size, file);
1072                 } else if (obj->gtt_space &&
1073                     obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1074                         ret = i915_gem_object_pin(obj, 0, true);
1075                         if (ret != 0)
1076                                 goto out;
1077                         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1078                         if (ret != 0)
1079                                 goto out_unpin;
1080                         ret = i915_gem_object_put_fence(obj);
1081                         if (ret != 0)
1082                                 goto out_unpin;
1083                         ret = i915_gem_gtt_write(dev, obj, data_ptr, size,
1084                             offset, file);
1085 out_unpin:
1086                         i915_gem_object_unpin(obj);
1087                 } else {
1088                         ret = i915_gem_object_set_to_cpu_domain(obj, true);
1089                         if (ret != 0)
1090                                 goto out;
1091                         ret = i915_gem_swap_io(dev, obj, data_ptr, size, offset,
1092                             UIO_WRITE, file);
1093                 }
1094         }
1095 out:
1096         drm_gem_object_unreference(&obj->base);
1097 unlock:
1098         DRM_UNLOCK(dev);
1099 unlocked:
1100         vm_page_unhold_pages(ma, npages);
1101 free_ma:
1102         drm_free(ma, DRM_I915_GEM);
1103         return (ret);
1104 }
1105
1106 int
1107 i915_gem_pread_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
1108 {
1109         struct drm_i915_gem_pread *args;
1110
1111         args = data;
1112         return (i915_gem_obj_io(dev, args->handle, args->data_ptr, args->size,
1113             args->offset, UIO_READ, file));
1114 }
1115
1116 int
1117 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
1118 {
1119         struct drm_i915_gem_pwrite *args;
1120
1121         args = data;
1122         return (i915_gem_obj_io(dev, args->handle, args->data_ptr, args->size,
1123             args->offset, UIO_WRITE, file));
1124 }
1125
1126 int
1127 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1128     struct drm_file *file)
1129 {
1130         struct drm_i915_gem_set_domain *args;
1131         struct drm_i915_gem_object *obj;
1132         uint32_t read_domains;
1133         uint32_t write_domain;
1134         int ret;
1135
1136         if ((dev->driver->driver_features & DRIVER_GEM) == 0)
1137                 return (-ENODEV);
1138
1139         args = data;
1140         read_domains = args->read_domains;
1141         write_domain = args->write_domain;
1142
1143         if ((write_domain & I915_GEM_GPU_DOMAINS) != 0 ||
1144             (read_domains & I915_GEM_GPU_DOMAINS) != 0 ||
1145             (write_domain != 0 && read_domains != write_domain))
1146                 return (-EINVAL);
1147
1148         ret = i915_mutex_lock_interruptible(dev);
1149         if (ret != 0)
1150                 return (ret);
1151
1152         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1153         if (&obj->base == NULL) {
1154                 ret = -ENOENT;
1155                 goto unlock;
1156         }
1157
1158         if ((read_domains & I915_GEM_DOMAIN_GTT) != 0) {
1159                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1160                 if (ret == -EINVAL)
1161                         ret = 0;
1162         } else
1163                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1164
1165         drm_gem_object_unreference(&obj->base);
1166 unlock:
1167         DRM_UNLOCK(dev);
1168         return (ret);
1169 }
1170
1171 int
1172 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1173     struct drm_file *file)
1174 {
1175         struct drm_i915_gem_sw_finish *args;
1176         struct drm_i915_gem_object *obj;
1177         int ret;
1178
1179         args = data;
1180         ret = 0;
1181         if ((dev->driver->driver_features & DRIVER_GEM) == 0)
1182                 return (ENODEV);
1183         ret = i915_mutex_lock_interruptible(dev);
1184         if (ret != 0)
1185                 return (ret);
1186         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1187         if (&obj->base == NULL) {
1188                 ret = -ENOENT;
1189                 goto unlock;
1190         }
1191         if (obj->pin_count != 0)
1192                 i915_gem_object_flush_cpu_write_domain(obj);
1193         drm_gem_object_unreference(&obj->base);
1194 unlock:
1195         DRM_UNLOCK(dev);
1196         return (ret);
1197 }
1198
1199 int
1200 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1201     struct drm_file *file)
1202 {
1203         struct drm_i915_gem_mmap *args;
1204         struct drm_gem_object *obj;
1205         struct proc *p;
1206         vm_map_t map;
1207         vm_offset_t addr;
1208         vm_size_t size;
1209         int error, rv;
1210
1211         args = data;
1212
1213         if ((dev->driver->driver_features & DRIVER_GEM) == 0)
1214                 return (-ENODEV);
1215
1216         obj = drm_gem_object_lookup(dev, file, args->handle);
1217         if (obj == NULL)
1218                 return (-ENOENT);
1219         error = 0;
1220         if (args->size == 0)
1221                 goto out;
1222         p = curproc;
1223         map = &p->p_vmspace->vm_map;
1224         size = round_page(args->size);
1225         PROC_LOCK(p);
1226         if (map->size + size > p->p_rlimit[RLIMIT_VMEM].rlim_cur) {
1227                 PROC_UNLOCK(p);
1228                 error = ENOMEM;
1229                 goto out;
1230         }
1231         PROC_UNLOCK(p);
1232
1233         addr = 0;
1234         vm_object_hold(obj->vm_obj);
1235         vm_object_reference_locked(obj->vm_obj);
1236         vm_object_drop(obj->vm_obj);
1237         DRM_UNLOCK(dev);
1238         rv = vm_map_find(map, obj->vm_obj, args->offset, &addr, args->size,
1239             PAGE_SIZE, /* align */
1240             TRUE, /* fitit */
1241             VM_MAPTYPE_NORMAL, /* maptype */
1242             VM_PROT_READ | VM_PROT_WRITE, /* prot */
1243             VM_PROT_READ | VM_PROT_WRITE, /* max */
1244             MAP_SHARED /* cow */);
1245         if (rv != KERN_SUCCESS) {
1246                 vm_object_deallocate(obj->vm_obj);
1247                 error = -vm_mmap_to_errno(rv);
1248         } else {
1249                 args->addr_ptr = (uint64_t)addr;
1250         }
1251         DRM_LOCK(dev);
1252 out:
1253         drm_gem_object_unreference(obj);
1254         return (error);
1255 }
1256
1257 static int
1258 i915_gem_pager_ctor(void *handle, vm_ooffset_t size, vm_prot_t prot,
1259     vm_ooffset_t foff, struct ucred *cred, u_short *color)
1260 {
1261
1262         *color = 0; /* XXXKIB */
1263         return (0);
1264 }
1265
1266 int i915_intr_pf;
1267
1268 static int
1269 i915_gem_pager_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot,
1270     vm_page_t *mres)
1271 {
1272         struct drm_gem_object *gem_obj;
1273         struct drm_i915_gem_object *obj;
1274         struct drm_device *dev;
1275         drm_i915_private_t *dev_priv;
1276         vm_page_t m, oldm;
1277         int cause, ret;
1278         bool write;
1279
1280         gem_obj = vm_obj->handle;
1281         obj = to_intel_bo(gem_obj);
1282         dev = obj->base.dev;
1283         dev_priv = dev->dev_private;
1284 #if 0
1285         write = (prot & VM_PROT_WRITE) != 0;
1286 #else
1287         write = true;
1288 #endif
1289         vm_object_pip_add(vm_obj, 1);
1290
1291         /*
1292          * Remove the placeholder page inserted by vm_fault() from the
1293          * object before dropping the object lock. If
1294          * i915_gem_release_mmap() is active in parallel on this gem
1295          * object, then it owns the drm device sx and might find the
1296          * placeholder already. Then, since the page is busy,
1297          * i915_gem_release_mmap() sleeps waiting for the busy state
1298          * of the page cleared. We will be not able to acquire drm
1299          * device lock until i915_gem_release_mmap() is able to make a
1300          * progress.
1301          */
1302         if (*mres != NULL) {
1303                 oldm = *mres;
1304                 vm_page_remove(oldm);
1305                 *mres = NULL;
1306         } else
1307                 oldm = NULL;
1308 retry:
1309         VM_OBJECT_UNLOCK(vm_obj);
1310 unlocked_vmobj:
1311         cause = ret = 0;
1312         m = NULL;
1313
1314         if (i915_intr_pf) {
1315                 ret = i915_mutex_lock_interruptible(dev);
1316                 if (ret != 0) {
1317                         cause = 10;
1318                         goto out;
1319                 }
1320         } else
1321                 DRM_LOCK(dev);
1322
1323         /*
1324          * Since the object lock was dropped, other thread might have
1325          * faulted on the same GTT address and instantiated the
1326          * mapping for the page.  Recheck.
1327          */
1328         VM_OBJECT_LOCK(vm_obj);
1329         m = vm_page_lookup(vm_obj, OFF_TO_IDX(offset));
1330         if (m != NULL) {
1331                 if ((m->flags & PG_BUSY) != 0) {
1332                         DRM_UNLOCK(dev);
1333 #if 0 /* XXX */
1334                         vm_page_sleep(m, "915pee");
1335 #endif
1336                         goto retry;
1337                 }
1338                 goto have_page;
1339         } else
1340                 VM_OBJECT_UNLOCK(vm_obj);
1341
1342         /* Now bind it into the GTT if needed */
1343         if (!obj->map_and_fenceable) {
1344                 ret = i915_gem_object_unbind(obj);
1345                 if (ret != 0) {
1346                         cause = 20;
1347                         goto unlock;
1348                 }
1349         }
1350         if (!obj->gtt_space) {
1351                 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
1352                 if (ret != 0) {
1353                         cause = 30;
1354                         goto unlock;
1355                 }
1356
1357                 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1358                 if (ret != 0) {
1359                         cause = 40;
1360                         goto unlock;
1361                 }
1362         }
1363
1364         if (obj->tiling_mode == I915_TILING_NONE)
1365                 ret = i915_gem_object_put_fence(obj);
1366         else
1367                 ret = i915_gem_object_get_fence(obj, NULL);
1368         if (ret != 0) {
1369                 cause = 50;
1370                 goto unlock;
1371         }
1372
1373         if (i915_gem_object_is_inactive(obj))
1374                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1375
1376         obj->fault_mappable = true;
1377         VM_OBJECT_LOCK(vm_obj);
1378         m = vm_phys_fictitious_to_vm_page(dev->agp->base + obj->gtt_offset +
1379             offset);
1380         if (m == NULL) {
1381                 cause = 60;
1382                 ret = -EFAULT;
1383                 goto unlock;
1384         }
1385         KASSERT((m->flags & PG_FICTITIOUS) != 0,
1386             ("not fictitious %p", m));
1387         KASSERT(m->wire_count == 1, ("wire_count not 1 %p", m));
1388
1389         if ((m->flags & PG_BUSY) != 0) {
1390                 DRM_UNLOCK(dev);
1391 #if 0 /* XXX */
1392                 vm_page_sleep(m, "915pbs");
1393 #endif
1394                 goto retry;
1395         }
1396         m->valid = VM_PAGE_BITS_ALL;
1397         vm_page_insert(m, vm_obj, OFF_TO_IDX(offset));
1398 have_page:
1399         *mres = m;
1400         vm_page_busy_try(m, false);
1401
1402         DRM_UNLOCK(dev);
1403         if (oldm != NULL) {
1404                 vm_page_free(oldm);
1405         }
1406         vm_object_pip_wakeup(vm_obj);
1407         return (VM_PAGER_OK);
1408
1409 unlock:
1410         DRM_UNLOCK(dev);
1411 out:
1412         KASSERT(ret != 0, ("i915_gem_pager_fault: wrong return"));
1413         if (ret == -EAGAIN || ret == -EIO || ret == -EINTR) {
1414                 goto unlocked_vmobj;
1415         }
1416         VM_OBJECT_LOCK(vm_obj);
1417         vm_object_pip_wakeup(vm_obj);
1418         return (VM_PAGER_ERROR);
1419 }
1420
1421 static void
1422 i915_gem_pager_dtor(void *handle)
1423 {
1424         struct drm_gem_object *obj;
1425         struct drm_device *dev;
1426
1427         obj = handle;
1428         dev = obj->dev;
1429
1430         DRM_LOCK(dev);
1431         drm_gem_free_mmap_offset(obj);
1432         i915_gem_release_mmap(to_intel_bo(obj));
1433         drm_gem_object_unreference(obj);
1434         DRM_UNLOCK(dev);
1435 }
1436
1437 struct cdev_pager_ops i915_gem_pager_ops = {
1438         .cdev_pg_fault  = i915_gem_pager_fault,
1439         .cdev_pg_ctor   = i915_gem_pager_ctor,
1440         .cdev_pg_dtor   = i915_gem_pager_dtor
1441 };
1442
1443 int
1444 i915_gem_mmap_gtt(struct drm_file *file, struct drm_device *dev,
1445     uint32_t handle, uint64_t *offset)
1446 {
1447         struct drm_i915_private *dev_priv;
1448         struct drm_i915_gem_object *obj;
1449         int ret;
1450
1451         if (!(dev->driver->driver_features & DRIVER_GEM))
1452                 return (-ENODEV);
1453
1454         dev_priv = dev->dev_private;
1455
1456         ret = i915_mutex_lock_interruptible(dev);
1457         if (ret != 0)
1458                 return (ret);
1459
1460         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1461         if (&obj->base == NULL) {
1462                 ret = -ENOENT;
1463                 goto unlock;
1464         }
1465
1466         if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1467                 ret = -E2BIG;
1468                 goto out;
1469         }
1470
1471         if (obj->madv != I915_MADV_WILLNEED) {
1472                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1473                 ret = -EINVAL;
1474                 goto out;
1475         }
1476
1477         ret = drm_gem_create_mmap_offset(&obj->base);
1478         if (ret != 0)
1479                 goto out;
1480
1481         *offset = DRM_GEM_MAPPING_OFF(obj->base.map_list.key) |
1482             DRM_GEM_MAPPING_KEY;
1483 out:
1484         drm_gem_object_unreference(&obj->base);
1485 unlock:
1486         DRM_UNLOCK(dev);
1487         return (ret);
1488 }
1489
1490 int
1491 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1492     struct drm_file *file)
1493 {
1494         struct drm_i915_private *dev_priv;
1495         struct drm_i915_gem_mmap_gtt *args;
1496
1497         dev_priv = dev->dev_private;
1498         args = data;
1499
1500         return (i915_gem_mmap_gtt(file, dev, args->handle, &args->offset));
1501 }
1502
1503 struct drm_i915_gem_object *
1504 i915_gem_alloc_object(struct drm_device *dev, size_t size)
1505 {
1506         struct drm_i915_private *dev_priv;
1507         struct drm_i915_gem_object *obj;
1508
1509         dev_priv = dev->dev_private;
1510
1511         obj = kmalloc(sizeof(*obj), DRM_I915_GEM, M_WAITOK | M_ZERO);
1512
1513         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
1514                 drm_free(obj, DRM_I915_GEM);
1515                 return (NULL);
1516         }
1517
1518         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1519         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
1520
1521         if (HAS_LLC(dev))
1522                 obj->cache_level = I915_CACHE_LLC;
1523         else
1524                 obj->cache_level = I915_CACHE_NONE;
1525         obj->base.driver_private = NULL;
1526         obj->fence_reg = I915_FENCE_REG_NONE;
1527         INIT_LIST_HEAD(&obj->mm_list);
1528         INIT_LIST_HEAD(&obj->gtt_list);
1529         INIT_LIST_HEAD(&obj->ring_list);
1530         INIT_LIST_HEAD(&obj->exec_list);
1531         INIT_LIST_HEAD(&obj->gpu_write_list);
1532         obj->madv = I915_MADV_WILLNEED;
1533         /* Avoid an unnecessary call to unbind on the first bind. */
1534         obj->map_and_fenceable = true;
1535
1536         i915_gem_info_add_obj(dev_priv, size);
1537
1538         return (obj);
1539 }
1540
1541 void
1542 i915_gem_clflush_object(struct drm_i915_gem_object *obj)
1543 {
1544
1545         /* If we don't have a page list set up, then we're not pinned
1546          * to GPU, and we can ignore the cache flush because it'll happen
1547          * again at bind time.
1548          */
1549         if (obj->pages == NULL)
1550                 return;
1551
1552         /* If the GPU is snooping the contents of the CPU cache,
1553          * we do not need to manually clear the CPU cache lines.  However,
1554          * the caches are only snooped when the render cache is
1555          * flushed/invalidated.  As we always have to emit invalidations
1556          * and flushes when moving into and out of the RENDER domain, correct
1557          * snooping behaviour occurs naturally as the result of our domain
1558          * tracking.
1559          */
1560         if (obj->cache_level != I915_CACHE_NONE)
1561                 return;
1562
1563         drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
1564 }
1565
1566 static void
1567 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
1568 {
1569         uint32_t old_write_domain;
1570
1571         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
1572                 return;
1573
1574         i915_gem_clflush_object(obj);
1575         intel_gtt_chipset_flush();
1576         old_write_domain = obj->base.write_domain;
1577         obj->base.write_domain = 0;
1578 }
1579
1580 static int
1581 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
1582 {
1583
1584         if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
1585                 return (0);
1586         return (i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain));
1587 }
1588
1589 static void
1590 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
1591 {
1592         uint32_t old_write_domain;
1593
1594         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
1595                 return;
1596
1597         cpu_sfence();
1598
1599         old_write_domain = obj->base.write_domain;
1600         obj->base.write_domain = 0;
1601 }
1602
1603 int
1604 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
1605 {
1606         uint32_t old_write_domain, old_read_domains;
1607         int ret;
1608
1609         if (obj->gtt_space == NULL)
1610                 return (-EINVAL);
1611
1612         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
1613                 return 0;
1614
1615         ret = i915_gem_object_flush_gpu_write_domain(obj);
1616         if (ret != 0)
1617                 return (ret);
1618
1619         if (obj->pending_gpu_write || write) {
1620                 ret = i915_gem_object_wait_rendering(obj);
1621                 if (ret != 0)
1622                         return (ret);
1623         }
1624
1625         i915_gem_object_flush_cpu_write_domain(obj);
1626
1627         old_write_domain = obj->base.write_domain;
1628         old_read_domains = obj->base.read_domains;
1629
1630         KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) == 0,
1631             ("In GTT write domain"));
1632         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
1633         if (write) {
1634                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
1635                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
1636                 obj->dirty = 1;
1637         }
1638
1639         return (0);
1640 }
1641
1642 int
1643 i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1644     enum i915_cache_level cache_level)
1645 {
1646         struct drm_device *dev;
1647         drm_i915_private_t *dev_priv;
1648         int ret;
1649
1650         if (obj->cache_level == cache_level)
1651                 return 0;
1652
1653         if (obj->pin_count) {
1654                 DRM_DEBUG("can not change the cache level of pinned objects\n");
1655                 return (-EBUSY);
1656         }
1657
1658         dev = obj->base.dev;
1659         dev_priv = dev->dev_private;
1660         if (obj->gtt_space) {
1661                 ret = i915_gem_object_finish_gpu(obj);
1662                 if (ret != 0)
1663                         return (ret);
1664
1665                 i915_gem_object_finish_gtt(obj);
1666
1667                 /* Before SandyBridge, you could not use tiling or fence
1668                  * registers with snooped memory, so relinquish any fences
1669                  * currently pointing to our region in the aperture.
1670                  */
1671                 if (INTEL_INFO(obj->base.dev)->gen < 6) {
1672                         ret = i915_gem_object_put_fence(obj);
1673                         if (ret != 0)
1674                                 return (ret);
1675                 }
1676
1677                 i915_gem_gtt_rebind_object(obj, cache_level);
1678                 if (obj->has_aliasing_ppgtt_mapping)
1679                         i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
1680                             obj, cache_level);
1681         }
1682
1683         if (cache_level == I915_CACHE_NONE) {
1684                 u32 old_read_domains, old_write_domain;
1685
1686                 /* If we're coming from LLC cached, then we haven't
1687                  * actually been tracking whether the data is in the
1688                  * CPU cache or not, since we only allow one bit set
1689                  * in obj->write_domain and have been skipping the clflushes.
1690                  * Just set it to the CPU cache for now.
1691                  */
1692                 KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) == 0,
1693                     ("obj %p in CPU write domain", obj));
1694                 KASSERT((obj->base.read_domains & ~I915_GEM_DOMAIN_CPU) == 0,
1695                     ("obj %p in CPU read domain", obj));
1696
1697                 old_read_domains = obj->base.read_domains;
1698                 old_write_domain = obj->base.write_domain;
1699
1700                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
1701                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1702
1703         }
1704
1705         obj->cache_level = cache_level;
1706         return (0);
1707 }
1708
1709 int
1710 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1711     u32 alignment, struct intel_ring_buffer *pipelined)
1712 {
1713         u32 old_read_domains, old_write_domain;
1714         int ret;
1715
1716         ret = i915_gem_object_flush_gpu_write_domain(obj);
1717         if (ret != 0)
1718                 return (ret);
1719
1720         if (pipelined != obj->ring) {
1721                 ret = i915_gem_object_wait_rendering(obj);
1722                 if (ret == -ERESTART || ret == -EINTR)
1723                         return (ret);
1724         }
1725
1726         ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
1727         if (ret != 0)
1728                 return (ret);
1729
1730         ret = i915_gem_object_pin(obj, alignment, true);
1731         if (ret != 0)
1732                 return (ret);
1733
1734         i915_gem_object_flush_cpu_write_domain(obj);
1735
1736         old_write_domain = obj->base.write_domain;
1737         old_read_domains = obj->base.read_domains;
1738
1739         KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) == 0,
1740             ("obj %p in GTT write domain", obj));
1741         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
1742
1743         return (0);
1744 }
1745
1746 int
1747 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
1748 {
1749         int ret;
1750
1751         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
1752                 return (0);
1753
1754         if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
1755                 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
1756                 if (ret != 0)
1757                         return (ret);
1758         }
1759
1760         ret = i915_gem_object_wait_rendering(obj);
1761         if (ret != 0)
1762                 return (ret);
1763
1764         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1765
1766         return (0);
1767 }
1768
1769 static int
1770 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
1771 {
1772         uint32_t old_write_domain, old_read_domains;
1773         int ret;
1774
1775         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
1776                 return 0;
1777
1778         ret = i915_gem_object_flush_gpu_write_domain(obj);
1779         if (ret != 0)
1780                 return (ret);
1781
1782         ret = i915_gem_object_wait_rendering(obj);
1783         if (ret != 0)
1784                 return (ret);
1785
1786         i915_gem_object_flush_gtt_write_domain(obj);
1787         i915_gem_object_set_to_full_cpu_read_domain(obj);
1788
1789         old_write_domain = obj->base.write_domain;
1790         old_read_domains = obj->base.read_domains;
1791
1792         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
1793                 i915_gem_clflush_object(obj);
1794                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
1795         }
1796
1797         KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) == 0,
1798             ("In cpu write domain"));
1799
1800         if (write) {
1801                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
1802                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1803         }
1804
1805         return (0);
1806 }
1807
1808 static void
1809 i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj)
1810 {
1811         int i;
1812
1813         if (obj->page_cpu_valid == NULL)
1814                 return;
1815
1816         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0) {
1817                 for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) {
1818                         if (obj->page_cpu_valid[i] != 0)
1819                                 continue;
1820                         drm_clflush_pages(obj->pages + i, 1);
1821                 }
1822         }
1823
1824         drm_free(obj->page_cpu_valid, DRM_I915_GEM);
1825         obj->page_cpu_valid = NULL;
1826 }
1827
1828 static int
1829 i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
1830     uint64_t offset, uint64_t size)
1831 {
1832         uint32_t old_read_domains;
1833         int i, ret;
1834
1835         if (offset == 0 && size == obj->base.size)
1836                 return (i915_gem_object_set_to_cpu_domain(obj, 0));
1837
1838         ret = i915_gem_object_flush_gpu_write_domain(obj);
1839         if (ret != 0)
1840                 return (ret);
1841         ret = i915_gem_object_wait_rendering(obj);
1842         if (ret != 0)
1843                 return (ret);
1844
1845         i915_gem_object_flush_gtt_write_domain(obj);
1846
1847         if (obj->page_cpu_valid == NULL &&
1848             (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0)
1849                 return (0);
1850
1851         if (obj->page_cpu_valid == NULL) {
1852                 obj->page_cpu_valid = kmalloc(obj->base.size / PAGE_SIZE,
1853                     DRM_I915_GEM, M_WAITOK | M_ZERO);
1854         } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
1855                 memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE);
1856
1857         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
1858              i++) {
1859                 if (obj->page_cpu_valid[i])
1860                         continue;
1861                 drm_clflush_pages(obj->pages + i, 1);
1862                 obj->page_cpu_valid[i] = 1;
1863         }
1864
1865         KASSERT((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) == 0,
1866             ("In gpu write domain"));
1867
1868         old_read_domains = obj->base.read_domains;
1869         obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
1870
1871         return (0);
1872 }
1873
1874 static uint32_t
1875 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1876 {
1877         uint32_t gtt_size;
1878
1879         if (INTEL_INFO(dev)->gen >= 4 ||
1880             tiling_mode == I915_TILING_NONE)
1881                 return (size);
1882
1883         /* Previous chips need a power-of-two fence region when tiling */
1884         if (INTEL_INFO(dev)->gen == 3)
1885                 gtt_size = 1024*1024;
1886         else
1887                 gtt_size = 512*1024;
1888
1889         while (gtt_size < size)
1890                 gtt_size <<= 1;
1891
1892         return (gtt_size);
1893 }
1894
1895 /**
1896  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1897  * @obj: object to check
1898  *
1899  * Return the required GTT alignment for an object, taking into account
1900  * potential fence register mapping.
1901  */
1902 static uint32_t
1903 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1904      int tiling_mode)
1905 {
1906
1907         /*
1908          * Minimum alignment is 4k (GTT page size), but might be greater
1909          * if a fence register is needed for the object.
1910          */
1911         if (INTEL_INFO(dev)->gen >= 4 ||
1912             tiling_mode == I915_TILING_NONE)
1913                 return (4096);
1914
1915         /*
1916          * Previous chips need to be aligned to the size of the smallest
1917          * fence register that can contain the object.
1918          */
1919         return (i915_gem_get_gtt_size(dev, size, tiling_mode));
1920 }
1921
1922 uint32_t
1923 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, uint32_t size,
1924     int tiling_mode)
1925 {
1926
1927         if (tiling_mode == I915_TILING_NONE)
1928                 return (4096);
1929
1930         /*
1931          * Minimum alignment is 4k (GTT page size) for sane hw.
1932          */
1933         if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev))
1934                 return (4096);
1935
1936         /*
1937          * Previous hardware however needs to be aligned to a power-of-two
1938          * tile height. The simplest method for determining this is to reuse
1939          * the power-of-tile object size.
1940          */
1941         return (i915_gem_get_gtt_size(dev, size, tiling_mode));
1942 }
1943
1944 static int
1945 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
1946     unsigned alignment, bool map_and_fenceable)
1947 {
1948         struct drm_device *dev;
1949         struct drm_i915_private *dev_priv;
1950         struct drm_mm_node *free_space;
1951         uint32_t size, fence_size, fence_alignment, unfenced_alignment;
1952         bool mappable, fenceable;
1953         int ret;
1954
1955         dev = obj->base.dev;
1956         dev_priv = dev->dev_private;
1957
1958         if (obj->madv != I915_MADV_WILLNEED) {
1959                 DRM_ERROR("Attempting to bind a purgeable object\n");
1960                 return (-EINVAL);
1961         }
1962
1963         fence_size = i915_gem_get_gtt_size(dev, obj->base.size,
1964             obj->tiling_mode);
1965         fence_alignment = i915_gem_get_gtt_alignment(dev, obj->base.size,
1966             obj->tiling_mode);
1967         unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(dev,
1968             obj->base.size, obj->tiling_mode);
1969         if (alignment == 0)
1970                 alignment = map_and_fenceable ? fence_alignment :
1971                     unfenced_alignment;
1972         if (map_and_fenceable && (alignment & (fence_alignment - 1)) != 0) {
1973                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
1974                 return (-EINVAL);
1975         }
1976
1977         size = map_and_fenceable ? fence_size : obj->base.size;
1978
1979         /* If the object is bigger than the entire aperture, reject it early
1980          * before evicting everything in a vain attempt to find space.
1981          */
1982         if (obj->base.size > (map_and_fenceable ?
1983             dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
1984                 DRM_ERROR(
1985 "Attempting to bind an object larger than the aperture\n");
1986                 return (-E2BIG);
1987         }
1988
1989  search_free:
1990         if (map_and_fenceable)
1991                 free_space = drm_mm_search_free_in_range(
1992                     &dev_priv->mm.gtt_space, size, alignment, 0,
1993                     dev_priv->mm.gtt_mappable_end, 0);
1994         else
1995                 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
1996                     size, alignment, 0);
1997         if (free_space != NULL) {
1998                 int color = 0;
1999                 if (map_and_fenceable)
2000                         obj->gtt_space = drm_mm_get_block_range_generic(
2001                             free_space, size, alignment, color, 0,
2002                             dev_priv->mm.gtt_mappable_end, 1);
2003                 else
2004                         obj->gtt_space = drm_mm_get_block_generic(free_space,
2005                             size, alignment, color, 1);
2006         }
2007         if (obj->gtt_space == NULL) {
2008                 ret = i915_gem_evict_something(dev, size, alignment,
2009                     map_and_fenceable);
2010                 if (ret != 0)
2011                         return (ret);
2012                 goto search_free;
2013         }
2014         ret = i915_gem_object_get_pages_gtt(obj, 0);
2015         if (ret != 0) {
2016                 drm_mm_put_block(obj->gtt_space);
2017                 obj->gtt_space = NULL;
2018                 /*
2019                  * i915_gem_object_get_pages_gtt() cannot return
2020                  * ENOMEM, since we use vm_page_grab(VM_ALLOC_RETRY)
2021                  * (which does not support operation without a flag
2022                  * anyway).
2023                  */
2024                 return (ret);
2025         }
2026
2027         ret = i915_gem_gtt_bind_object(obj);
2028         if (ret != 0) {
2029                 i915_gem_object_put_pages_gtt(obj);
2030                 drm_mm_put_block(obj->gtt_space);
2031                 obj->gtt_space = NULL;
2032                 if (i915_gem_evict_everything(dev, false))
2033                         return (ret);
2034                 goto search_free;
2035         }
2036
2037         list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
2038         list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2039
2040         KASSERT((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0,
2041             ("Object in gpu read domain"));
2042         KASSERT((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0,
2043             ("Object in gpu write domain"));
2044
2045         obj->gtt_offset = obj->gtt_space->start;
2046
2047         fenceable =
2048                 obj->gtt_space->size == fence_size &&
2049                 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
2050
2051         mappable =
2052                 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2053         obj->map_and_fenceable = mappable && fenceable;
2054
2055         return (0);
2056 }
2057
2058 static void
2059 i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2060 {
2061         u32 old_write_domain, old_read_domains;
2062
2063         /* Act a barrier for all accesses through the GTT */
2064         cpu_mfence();
2065
2066         /* Force a pagefault for domain tracking on next user access */
2067         i915_gem_release_mmap(obj);
2068
2069         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2070                 return;
2071
2072         old_read_domains = obj->base.read_domains;
2073         old_write_domain = obj->base.write_domain;
2074
2075         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2076         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2077
2078 }
2079
2080 int
2081 i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2082 {
2083         drm_i915_private_t *dev_priv;
2084         int ret;
2085
2086         dev_priv = obj->base.dev->dev_private;
2087         ret = 0;
2088         if (obj->gtt_space == NULL)
2089                 return (0);
2090         if (obj->pin_count != 0) {
2091                 DRM_ERROR("Attempting to unbind pinned buffer\n");
2092                 return (-EINVAL);
2093         }
2094
2095         ret = i915_gem_object_finish_gpu(obj);
2096         if (ret == -ERESTART || ret == -EINTR)
2097                 return (ret);
2098
2099         i915_gem_object_finish_gtt(obj);
2100
2101         if (ret == 0)
2102                 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2103         if (ret == -ERESTART || ret == -EINTR)
2104                 return (ret);
2105         if (ret != 0) {
2106                 i915_gem_clflush_object(obj);
2107                 obj->base.read_domains = obj->base.write_domain =
2108                     I915_GEM_DOMAIN_CPU;
2109         }
2110
2111         ret = i915_gem_object_put_fence(obj);
2112         if (ret == -ERESTART)
2113                 return (ret);
2114
2115         i915_gem_gtt_unbind_object(obj);
2116         if (obj->has_aliasing_ppgtt_mapping) {
2117                 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2118                 obj->has_aliasing_ppgtt_mapping = 0;
2119         }
2120         i915_gem_object_put_pages_gtt(obj);
2121
2122         list_del_init(&obj->gtt_list);
2123         list_del_init(&obj->mm_list);
2124         obj->map_and_fenceable = true;
2125
2126         drm_mm_put_block(obj->gtt_space);
2127         obj->gtt_space = NULL;
2128         obj->gtt_offset = 0;
2129
2130         if (i915_gem_object_is_purgeable(obj))
2131                 i915_gem_object_truncate(obj);
2132
2133         return (ret);
2134 }
2135
2136 static int
2137 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
2138     int flags)
2139 {
2140         struct drm_device *dev;
2141         vm_object_t vm_obj;
2142         vm_page_t m;
2143         int page_count, i, j;
2144
2145         dev = obj->base.dev;
2146         KASSERT(obj->pages == NULL, ("Obj already has pages"));
2147         page_count = obj->base.size / PAGE_SIZE;
2148         obj->pages = kmalloc(page_count * sizeof(vm_page_t), DRM_I915_GEM,
2149             M_WAITOK);
2150         vm_obj = obj->base.vm_obj;
2151         VM_OBJECT_LOCK(vm_obj);
2152         for (i = 0; i < page_count; i++) {
2153                 if ((obj->pages[i] = i915_gem_wire_page(vm_obj, i)) == NULL)
2154                         goto failed;
2155         }
2156         VM_OBJECT_UNLOCK(vm_obj);
2157         if (i915_gem_object_needs_bit17_swizzle(obj))
2158                 i915_gem_object_do_bit_17_swizzle(obj);
2159         return (0);
2160
2161 failed:
2162         for (j = 0; j < i; j++) {
2163                 m = obj->pages[j];
2164                 vm_page_busy_wait(m, FALSE, "i915gem");
2165                 vm_page_unwire(m, 0);
2166                 vm_page_wakeup(m);
2167                 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
2168         }
2169         VM_OBJECT_UNLOCK(vm_obj);
2170         drm_free(obj->pages, DRM_I915_GEM);
2171         obj->pages = NULL;
2172         return (-EIO);
2173 }
2174
2175 #define GEM_PARANOID_CHECK_GTT 0
2176 #if GEM_PARANOID_CHECK_GTT
2177 static void
2178 i915_gem_assert_pages_not_mapped(struct drm_device *dev, vm_page_t *ma,
2179     int page_count)
2180 {
2181         struct drm_i915_private *dev_priv;
2182         vm_paddr_t pa;
2183         unsigned long start, end;
2184         u_int i;
2185         int j;
2186
2187         dev_priv = dev->dev_private;
2188         start = OFF_TO_IDX(dev_priv->mm.gtt_start);
2189         end = OFF_TO_IDX(dev_priv->mm.gtt_end);
2190         for (i = start; i < end; i++) {
2191                 pa = intel_gtt_read_pte_paddr(i);
2192                 for (j = 0; j < page_count; j++) {
2193                         if (pa == VM_PAGE_TO_PHYS(ma[j])) {
2194                                 panic("Page %p in GTT pte index %d pte %x",
2195                                     ma[i], i, intel_gtt_read_pte(i));
2196                         }
2197                 }
2198         }
2199 }
2200 #endif
2201
2202 static void
2203 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
2204 {
2205         vm_page_t m;
2206         int page_count, i;
2207
2208         BUG_ON(obj->madv == __I915_MADV_PURGED);
2209
2210         if (obj->tiling_mode != I915_TILING_NONE)
2211                 i915_gem_object_save_bit_17_swizzle(obj);
2212         if (obj->madv == I915_MADV_DONTNEED)
2213                 obj->dirty = 0;
2214         page_count = obj->base.size / PAGE_SIZE;
2215         VM_OBJECT_LOCK(obj->base.vm_obj);
2216 #if GEM_PARANOID_CHECK_GTT
2217         i915_gem_assert_pages_not_mapped(obj->base.dev, obj->pages, page_count);
2218 #endif
2219         for (i = 0; i < page_count; i++) {
2220                 m = obj->pages[i];
2221                 if (obj->dirty)
2222                         vm_page_dirty(m);
2223                 if (obj->madv == I915_MADV_WILLNEED)
2224                         vm_page_reference(m);
2225                 vm_page_busy_wait(obj->pages[i], FALSE, "i915gem");
2226                 vm_page_unwire(obj->pages[i], 1);
2227                 vm_page_wakeup(obj->pages[i]);
2228                 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
2229         }
2230         VM_OBJECT_UNLOCK(obj->base.vm_obj);
2231         obj->dirty = 0;
2232         drm_free(obj->pages, DRM_I915_GEM);
2233         obj->pages = NULL;
2234 }
2235
2236 void
2237 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
2238 {
2239         vm_object_t devobj;
2240         vm_page_t m;
2241         int i, page_count;
2242
2243         if (!obj->fault_mappable)
2244                 return;
2245
2246         devobj = cdev_pager_lookup(obj);
2247         if (devobj != NULL) {
2248                 page_count = OFF_TO_IDX(obj->base.size);
2249
2250                 VM_OBJECT_LOCK(devobj);
2251                 for (i = 0; i < page_count; i++) {
2252                         m = vm_page_lookup_busy_wait(devobj, i, TRUE, "915unm");
2253                         if (m == NULL)
2254                                 continue;
2255                         cdev_pager_free_page(devobj, m);
2256                 }
2257                 VM_OBJECT_UNLOCK(devobj);
2258                 vm_object_deallocate(devobj);
2259         }
2260
2261         obj->fault_mappable = false;
2262 }
2263
2264 int
2265 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
2266 {
2267         int ret;
2268
2269         KASSERT((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0,
2270             ("In GPU write domain"));
2271
2272         if (obj->active) {
2273                 ret = i915_wait_request(obj->ring, obj->last_rendering_seqno,
2274                     true);
2275                 if (ret != 0)
2276                         return (ret);
2277         }
2278         return (0);
2279 }
2280
2281 void
2282 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2283     struct intel_ring_buffer *ring, uint32_t seqno)
2284 {
2285         struct drm_device *dev = obj->base.dev;
2286         struct drm_i915_private *dev_priv = dev->dev_private;
2287         struct drm_i915_fence_reg *reg;
2288
2289         obj->ring = ring;
2290         KASSERT(ring != NULL, ("NULL ring"));
2291
2292         /* Add a reference if we're newly entering the active list. */
2293         if (!obj->active) {
2294                 drm_gem_object_reference(&obj->base);
2295                 obj->active = 1;
2296         }
2297
2298         /* Move from whatever list we were on to the tail of execution. */
2299         list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
2300         list_move_tail(&obj->ring_list, &ring->active_list);
2301
2302         obj->last_rendering_seqno = seqno;
2303         if (obj->fenced_gpu_access) {
2304                 obj->last_fenced_seqno = seqno;
2305                 obj->last_fenced_ring = ring;
2306
2307                 /* Bump MRU to take account of the delayed flush */
2308                 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2309                         reg = &dev_priv->fence_regs[obj->fence_reg];
2310                         list_move_tail(&reg->lru_list,
2311                                        &dev_priv->mm.fence_list);
2312                 }
2313         }
2314 }
2315
2316 static void
2317 i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
2318 {
2319         list_del_init(&obj->ring_list);
2320         obj->last_rendering_seqno = 0;
2321         obj->last_fenced_seqno = 0;
2322 }
2323
2324 static void
2325 i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
2326 {
2327         struct drm_device *dev = obj->base.dev;
2328         drm_i915_private_t *dev_priv = dev->dev_private;
2329
2330         KASSERT(obj->active, ("Object not active"));
2331         list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
2332
2333         i915_gem_object_move_off_active(obj);
2334 }
2335
2336 static void
2337 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2338 {
2339         struct drm_device *dev = obj->base.dev;
2340         struct drm_i915_private *dev_priv = dev->dev_private;
2341
2342         if (obj->pin_count != 0)
2343                 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
2344         else
2345                 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2346
2347         KASSERT(list_empty(&obj->gpu_write_list), ("On gpu_write_list"));
2348         KASSERT(obj->active, ("Object not active"));
2349         obj->ring = NULL;
2350         obj->last_fenced_ring = NULL;
2351
2352         i915_gem_object_move_off_active(obj);
2353         obj->fenced_gpu_access = false;
2354
2355         obj->active = 0;
2356         obj->pending_gpu_write = false;
2357         drm_gem_object_unreference(&obj->base);
2358
2359 #if 1
2360         KIB_NOTYET();
2361 #else
2362         WARN_ON(i915_verify_lists(dev));
2363 #endif
2364 }
2365
2366 /* Immediately discard the backing storage */
2367 static void
2368 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2369 {
2370         vm_object_t vm_obj;
2371
2372         vm_obj = obj->base.vm_obj;
2373         VM_OBJECT_LOCK(vm_obj);
2374         vm_object_page_remove(vm_obj, 0, 0, false);
2375         VM_OBJECT_UNLOCK(vm_obj);
2376         obj->madv = __I915_MADV_PURGED;
2377 }
2378
2379 static inline int
2380 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
2381 {
2382
2383         return (obj->madv == I915_MADV_DONTNEED);
2384 }
2385
2386 static void
2387 i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
2388     uint32_t flush_domains)
2389 {
2390         struct drm_i915_gem_object *obj, *next;
2391         uint32_t old_write_domain;
2392
2393         list_for_each_entry_safe(obj, next, &ring->gpu_write_list,
2394             gpu_write_list) {
2395                 if (obj->base.write_domain & flush_domains) {
2396                         old_write_domain = obj->base.write_domain;
2397                         obj->base.write_domain = 0;
2398                         list_del_init(&obj->gpu_write_list);
2399                         i915_gem_object_move_to_active(obj, ring,
2400                             i915_gem_next_request_seqno(ring));
2401                 }
2402         }
2403 }
2404
2405 static int
2406 i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2407 {
2408         drm_i915_private_t *dev_priv;
2409
2410         dev_priv = obj->base.dev->dev_private;
2411         return (dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2412             obj->tiling_mode != I915_TILING_NONE);
2413 }
2414
2415 #define VM_OBJECT_LOCK_ASSERT_OWNED(object)
2416
2417 static vm_page_t
2418 i915_gem_wire_page(vm_object_t object, vm_pindex_t pindex)
2419 {
2420         vm_page_t m;
2421         int rv;
2422
2423         VM_OBJECT_LOCK_ASSERT_OWNED(object);
2424         m = vm_page_grab(object, pindex, VM_ALLOC_NORMAL | VM_ALLOC_RETRY);
2425         if (m->valid != VM_PAGE_BITS_ALL) {
2426                 if (vm_pager_has_page(object, pindex)) {
2427                         rv = vm_pager_get_page(object, &m, 1);
2428                         m = vm_page_lookup(object, pindex);
2429                         if (m == NULL)
2430                                 return (NULL);
2431                         if (rv != VM_PAGER_OK) {
2432                                 vm_page_free(m);
2433                                 return (NULL);
2434                         }
2435                 } else {
2436                         pmap_zero_page(VM_PAGE_TO_PHYS(m));
2437                         m->valid = VM_PAGE_BITS_ALL;
2438                         m->dirty = 0;
2439                 }
2440         }
2441         vm_page_wire(m);
2442         vm_page_wakeup(m);
2443         atomic_add_long(&i915_gem_wired_pages_cnt, 1);
2444         return (m);
2445 }
2446
2447 int
2448 i915_gem_flush_ring(struct intel_ring_buffer *ring, uint32_t invalidate_domains,
2449     uint32_t flush_domains)
2450 {
2451         int ret;
2452
2453         if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
2454                 return 0;
2455
2456         ret = ring->flush(ring, invalidate_domains, flush_domains);
2457         if (ret)
2458                 return ret;
2459
2460         if (flush_domains & I915_GEM_GPU_DOMAINS)
2461                 i915_gem_process_flushing_list(ring, flush_domains);
2462         return 0;
2463 }
2464
2465 static int
2466 i915_ring_idle(struct intel_ring_buffer *ring, bool do_retire)
2467 {
2468         int ret;
2469
2470         if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
2471                 return 0;
2472
2473         if (!list_empty(&ring->gpu_write_list)) {
2474                 ret = i915_gem_flush_ring(ring, I915_GEM_GPU_DOMAINS,
2475                     I915_GEM_GPU_DOMAINS);
2476                 if (ret != 0)
2477                         return ret;
2478         }
2479
2480         return (i915_wait_request(ring, i915_gem_next_request_seqno(ring),
2481             do_retire));
2482 }
2483
2484 int
2485 i915_gpu_idle(struct drm_device *dev, bool do_retire)
2486 {
2487         drm_i915_private_t *dev_priv = dev->dev_private;
2488         int ret, i;
2489
2490         /* Flush everything onto the inactive list. */
2491         for (i = 0; i < I915_NUM_RINGS; i++) {
2492                 ret = i915_ring_idle(&dev_priv->rings[i], do_retire);
2493                 if (ret)
2494                         return ret;
2495         }
2496
2497         return 0;
2498 }
2499
2500 int
2501 i915_wait_request(struct intel_ring_buffer *ring, uint32_t seqno, bool do_retire)
2502 {
2503         drm_i915_private_t *dev_priv;
2504         struct drm_i915_gem_request *request;
2505         uint32_t ier;
2506         int flags, ret;
2507         bool recovery_complete;
2508
2509         KASSERT(seqno != 0, ("Zero seqno"));
2510
2511         dev_priv = ring->dev->dev_private;
2512         ret = 0;
2513
2514         if (atomic_read(&dev_priv->mm.wedged) != 0) {
2515                 /* Give the error handler a chance to run. */
2516                 lockmgr(&dev_priv->error_completion_lock, LK_EXCLUSIVE);
2517                 recovery_complete = (&dev_priv->error_completion) > 0;
2518                 lockmgr(&dev_priv->error_completion_lock, LK_RELEASE);
2519                 return (recovery_complete ? -EIO : -EAGAIN);
2520         }
2521
2522         if (seqno == ring->outstanding_lazy_request) {
2523                 request = kmalloc(sizeof(*request), DRM_I915_GEM,
2524                     M_WAITOK | M_ZERO);
2525                 if (request == NULL)
2526                         return (-ENOMEM);
2527
2528                 ret = i915_add_request(ring, NULL, request);
2529                 if (ret != 0) {
2530                         drm_free(request, DRM_I915_GEM);
2531                         return (ret);
2532                 }
2533
2534                 seqno = request->seqno;
2535         }
2536
2537         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
2538                 if (HAS_PCH_SPLIT(ring->dev))
2539                         ier = I915_READ(DEIER) | I915_READ(GTIER);
2540                 else
2541                         ier = I915_READ(IER);
2542                 if (!ier) {
2543                         DRM_ERROR("something (likely vbetool) disabled "
2544                                   "interrupts, re-enabling\n");
2545                         ring->dev->driver->irq_preinstall(ring->dev);
2546                         ring->dev->driver->irq_postinstall(ring->dev);
2547                 }
2548
2549                 ring->waiting_seqno = seqno;
2550                 lockmgr(&ring->irq_lock, LK_EXCLUSIVE);
2551                 if (ring->irq_get(ring)) {
2552                         flags = dev_priv->mm.interruptible ? PCATCH : 0;
2553                         while (!i915_seqno_passed(ring->get_seqno(ring), seqno)
2554                             && !atomic_read(&dev_priv->mm.wedged) &&
2555                             ret == 0) {
2556                                 ret = -lksleep(ring, &ring->irq_lock, flags,
2557                                     "915gwr", 0);
2558                         }
2559                         ring->irq_put(ring);
2560                         lockmgr(&ring->irq_lock, LK_RELEASE);
2561                 } else {
2562                         lockmgr(&ring->irq_lock, LK_RELEASE);
2563                         if (_intel_wait_for(ring->dev,
2564                             i915_seqno_passed(ring->get_seqno(ring), seqno) ||
2565                             atomic_read(&dev_priv->mm.wedged), 3000,
2566                             0, "i915wrq") != 0)
2567                                 ret = -EBUSY;
2568                 }
2569                 ring->waiting_seqno = 0;
2570
2571         }
2572         if (atomic_read(&dev_priv->mm.wedged))
2573                 ret = -EAGAIN;
2574
2575         /* Directly dispatch request retiring.  While we have the work queue
2576          * to handle this, the waiter on a request often wants an associated
2577          * buffer to have made it to the inactive list, and we would need
2578          * a separate wait queue to handle that.
2579          */
2580         if (ret == 0 && do_retire)
2581                 i915_gem_retire_requests_ring(ring);
2582
2583         return (ret);
2584 }
2585
2586 static u32
2587 i915_gem_get_seqno(struct drm_device *dev)
2588 {
2589         drm_i915_private_t *dev_priv = dev->dev_private;
2590         u32 seqno = dev_priv->next_seqno;
2591
2592         /* reserve 0 for non-seqno */
2593         if (++dev_priv->next_seqno == 0)
2594                 dev_priv->next_seqno = 1;
2595
2596         return seqno;
2597 }
2598
2599 u32
2600 i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
2601 {
2602         if (ring->outstanding_lazy_request == 0)
2603                 ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev);
2604
2605         return ring->outstanding_lazy_request;
2606 }
2607
2608 int
2609 i915_add_request(struct intel_ring_buffer *ring, struct drm_file *file,
2610      struct drm_i915_gem_request *request)
2611 {
2612         drm_i915_private_t *dev_priv;
2613         struct drm_i915_file_private *file_priv;
2614         uint32_t seqno;
2615         u32 request_ring_position;
2616         int was_empty;
2617         int ret;
2618
2619         KASSERT(request != NULL, ("NULL request in add"));
2620         DRM_LOCK_ASSERT(ring->dev);
2621         dev_priv = ring->dev->dev_private;
2622
2623         seqno = i915_gem_next_request_seqno(ring);
2624         request_ring_position = intel_ring_get_tail(ring);
2625
2626         ret = ring->add_request(ring, &seqno);
2627         if (ret != 0)
2628             return ret;
2629
2630         request->seqno = seqno;
2631         request->ring = ring;
2632         request->tail = request_ring_position;
2633         request->emitted_jiffies = ticks;
2634         was_empty = list_empty(&ring->request_list);
2635         list_add_tail(&request->list, &ring->request_list);
2636
2637         if (file != NULL) {
2638                 file_priv = file->driver_priv;
2639
2640                 spin_lock(&file_priv->mm.lock);
2641                 request->file_priv = file_priv;
2642                 list_add_tail(&request->client_list,
2643                     &file_priv->mm.request_list);
2644                 spin_unlock(&file_priv->mm.lock);
2645         }
2646
2647         ring->outstanding_lazy_request = 0;
2648
2649         if (!dev_priv->mm.suspended) {
2650                 if (i915_enable_hangcheck) {
2651                         callout_reset(&dev_priv->hangcheck_timer,
2652                             DRM_I915_HANGCHECK_PERIOD, i915_hangcheck_elapsed, ring->dev);
2653                 }
2654                 if (was_empty)
2655                         taskqueue_enqueue_timeout(dev_priv->tq,
2656                             &dev_priv->mm.retire_task, hz);
2657         }
2658         return (0);
2659 }
2660
2661 static inline void
2662 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2663 {
2664         struct drm_i915_file_private *file_priv = request->file_priv;
2665
2666         if (!file_priv)
2667                 return;
2668
2669         DRM_LOCK_ASSERT(request->ring->dev);
2670
2671         spin_lock(&file_priv->mm.lock);
2672         if (request->file_priv != NULL) {
2673                 list_del(&request->client_list);
2674                 request->file_priv = NULL;
2675         }
2676         spin_unlock(&file_priv->mm.lock);
2677 }
2678
2679 void
2680 i915_gem_release(struct drm_device *dev, struct drm_file *file)
2681 {
2682         struct drm_i915_file_private *file_priv;
2683         struct drm_i915_gem_request *request;
2684
2685         file_priv = file->driver_priv;
2686
2687         /* Clean up our request list when the client is going away, so that
2688          * later retire_requests won't dereference our soon-to-be-gone
2689          * file_priv.
2690          */
2691         spin_lock(&file_priv->mm.lock);
2692         while (!list_empty(&file_priv->mm.request_list)) {
2693                 request = list_first_entry(&file_priv->mm.request_list,
2694                                            struct drm_i915_gem_request,
2695                                            client_list);
2696                 list_del(&request->client_list);
2697                 request->file_priv = NULL;
2698         }
2699         spin_unlock(&file_priv->mm.lock);
2700 }
2701
2702 static void
2703 i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
2704     struct intel_ring_buffer *ring)
2705 {
2706
2707         if (ring->dev != NULL)
2708                 DRM_LOCK_ASSERT(ring->dev);
2709
2710         while (!list_empty(&ring->request_list)) {
2711                 struct drm_i915_gem_request *request;
2712
2713                 request = list_first_entry(&ring->request_list,
2714                     struct drm_i915_gem_request, list);
2715
2716                 list_del(&request->list);
2717                 i915_gem_request_remove_from_client(request);
2718                 drm_free(request, DRM_I915_GEM);
2719         }
2720
2721         while (!list_empty(&ring->active_list)) {
2722                 struct drm_i915_gem_object *obj;
2723
2724                 obj = list_first_entry(&ring->active_list,
2725                     struct drm_i915_gem_object, ring_list);
2726
2727                 obj->base.write_domain = 0;
2728                 list_del_init(&obj->gpu_write_list);
2729                 i915_gem_object_move_to_inactive(obj);
2730         }
2731 }
2732
2733 static void
2734 i915_gem_reset_fences(struct drm_device *dev)
2735 {
2736         struct drm_i915_private *dev_priv = dev->dev_private;
2737         int i;
2738
2739         for (i = 0; i < dev_priv->num_fence_regs; i++) {
2740                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2741                 struct drm_i915_gem_object *obj = reg->obj;
2742
2743                 if (!obj)
2744                         continue;
2745
2746                 if (obj->tiling_mode)
2747                         i915_gem_release_mmap(obj);
2748
2749                 reg->obj->fence_reg = I915_FENCE_REG_NONE;
2750                 reg->obj->fenced_gpu_access = false;
2751                 reg->obj->last_fenced_seqno = 0;
2752                 reg->obj->last_fenced_ring = NULL;
2753                 i915_gem_clear_fence_reg(dev, reg);
2754         }
2755 }
2756
2757 void
2758 i915_gem_reset(struct drm_device *dev)
2759 {
2760         struct drm_i915_private *dev_priv = dev->dev_private;
2761         struct drm_i915_gem_object *obj;
2762         int i;
2763
2764         for (i = 0; i < I915_NUM_RINGS; i++)
2765                 i915_gem_reset_ring_lists(dev_priv, &dev_priv->rings[i]);
2766
2767         /* Remove anything from the flushing lists. The GPU cache is likely
2768          * to be lost on reset along with the data, so simply move the
2769          * lost bo to the inactive list.
2770          */
2771         while (!list_empty(&dev_priv->mm.flushing_list)) {
2772                 obj = list_first_entry(&dev_priv->mm.flushing_list,
2773                                       struct drm_i915_gem_object,
2774                                       mm_list);
2775
2776                 obj->base.write_domain = 0;
2777                 list_del_init(&obj->gpu_write_list);
2778                 i915_gem_object_move_to_inactive(obj);
2779         }
2780
2781         /* Move everything out of the GPU domains to ensure we do any
2782          * necessary invalidation upon reuse.
2783          */
2784         list_for_each_entry(obj, &dev_priv->mm.inactive_list, mm_list) {
2785                 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2786         }
2787
2788         /* The fence registers are invalidated so clear them out */
2789         i915_gem_reset_fences(dev);
2790 }
2791
2792 /**
2793  * This function clears the request list as sequence numbers are passed.
2794  */
2795 void
2796 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2797 {
2798         uint32_t seqno;
2799         int i;
2800
2801         if (list_empty(&ring->request_list))
2802                 return;
2803
2804         seqno = ring->get_seqno(ring);
2805         for (i = 0; i < DRM_ARRAY_SIZE(ring->sync_seqno); i++)
2806                 if (seqno >= ring->sync_seqno[i])
2807                         ring->sync_seqno[i] = 0;
2808
2809         while (!list_empty(&ring->request_list)) {
2810                 struct drm_i915_gem_request *request;
2811
2812                 request = list_first_entry(&ring->request_list,
2813                                            struct drm_i915_gem_request,
2814                                            list);
2815
2816                 if (!i915_seqno_passed(seqno, request->seqno))
2817                         break;
2818
2819                 ring->last_retired_head = request->tail;
2820
2821                 list_del(&request->list);
2822                 i915_gem_request_remove_from_client(request);
2823                 drm_free(request, DRM_I915_GEM);
2824         }
2825
2826         /* Move any buffers on the active list that are no longer referenced
2827          * by the ringbuffer to the flushing/inactive lists as appropriate.
2828          */
2829         while (!list_empty(&ring->active_list)) {
2830                 struct drm_i915_gem_object *obj;
2831
2832                 obj = list_first_entry(&ring->active_list,
2833                                       struct drm_i915_gem_object,
2834                                       ring_list);
2835
2836                 if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
2837                         break;
2838
2839                 if (obj->base.write_domain != 0)
2840                         i915_gem_object_move_to_flushing(obj);
2841                 else
2842                         i915_gem_object_move_to_inactive(obj);
2843         }
2844
2845         if (ring->trace_irq_seqno &&
2846             i915_seqno_passed(seqno, ring->trace_irq_seqno)) {
2847                 lockmgr(&ring->irq_lock, LK_EXCLUSIVE);
2848                 ring->irq_put(ring);
2849                 lockmgr(&ring->irq_lock, LK_RELEASE);
2850                 ring->trace_irq_seqno = 0;
2851         }
2852 }
2853
2854 void
2855 i915_gem_retire_requests(struct drm_device *dev)
2856 {
2857         drm_i915_private_t *dev_priv = dev->dev_private;
2858         struct drm_i915_gem_object *obj, *next;
2859         int i;
2860
2861         if (!list_empty(&dev_priv->mm.deferred_free_list)) {
2862                 list_for_each_entry_safe(obj, next,
2863                     &dev_priv->mm.deferred_free_list, mm_list)
2864                         i915_gem_free_object_tail(obj);
2865         }
2866
2867         for (i = 0; i < I915_NUM_RINGS; i++)
2868                 i915_gem_retire_requests_ring(&dev_priv->rings[i]);
2869 }
2870
2871 static int
2872 sandybridge_write_fence_reg(struct drm_i915_gem_object *obj,
2873     struct intel_ring_buffer *pipelined)
2874 {
2875         struct drm_device *dev = obj->base.dev;
2876         drm_i915_private_t *dev_priv = dev->dev_private;
2877         u32 size = obj->gtt_space->size;
2878         int regnum = obj->fence_reg;
2879         uint64_t val;
2880
2881         val = (uint64_t)((obj->gtt_offset + size - 4096) &
2882                          0xfffff000) << 32;
2883         val |= obj->gtt_offset & 0xfffff000;
2884         val |= (uint64_t)((obj->stride / 128) - 1) <<
2885                 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2886
2887         if (obj->tiling_mode == I915_TILING_Y)
2888                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2889         val |= I965_FENCE_REG_VALID;
2890
2891         if (pipelined) {
2892                 int ret = intel_ring_begin(pipelined, 6);
2893                 if (ret)
2894                         return ret;
2895
2896                 intel_ring_emit(pipelined, MI_NOOP);
2897                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2898                 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8);
2899                 intel_ring_emit(pipelined, (u32)val);
2900                 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4);
2901                 intel_ring_emit(pipelined, (u32)(val >> 32));
2902                 intel_ring_advance(pipelined);
2903         } else
2904                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val);
2905
2906         return 0;
2907 }
2908
2909 static int
2910 i965_write_fence_reg(struct drm_i915_gem_object *obj,
2911     struct intel_ring_buffer *pipelined)
2912 {
2913         struct drm_device *dev = obj->base.dev;
2914         drm_i915_private_t *dev_priv = dev->dev_private;
2915         u32 size = obj->gtt_space->size;
2916         int regnum = obj->fence_reg;
2917         uint64_t val;
2918
2919         val = (uint64_t)((obj->gtt_offset + size - 4096) &
2920                     0xfffff000) << 32;
2921         val |= obj->gtt_offset & 0xfffff000;
2922         val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2923         if (obj->tiling_mode == I915_TILING_Y)
2924                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2925         val |= I965_FENCE_REG_VALID;
2926
2927         if (pipelined) {
2928                 int ret = intel_ring_begin(pipelined, 6);
2929                 if (ret)
2930                         return ret;
2931
2932                 intel_ring_emit(pipelined, MI_NOOP);
2933                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2934                 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8);
2935                 intel_ring_emit(pipelined, (u32)val);
2936                 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4);
2937                 intel_ring_emit(pipelined, (u32)(val >> 32));
2938                 intel_ring_advance(pipelined);
2939         } else
2940                 I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val);
2941
2942         return 0;
2943 }
2944
2945 static int
2946 i915_write_fence_reg(struct drm_i915_gem_object *obj,
2947     struct intel_ring_buffer *pipelined)
2948 {
2949         struct drm_device *dev = obj->base.dev;
2950         drm_i915_private_t *dev_priv = dev->dev_private;
2951         u32 size = obj->gtt_space->size;
2952         u32 fence_reg, val, pitch_val;
2953         int tile_width;
2954
2955         if ((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2956             (size & -size) != size || (obj->gtt_offset & (size - 1))) {
2957                 kprintf(
2958 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2959                  obj->gtt_offset, obj->map_and_fenceable, size);
2960                 return -EINVAL;
2961         }
2962
2963         if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2964                 tile_width = 128;
2965         else
2966                 tile_width = 512;
2967
2968         /* Note: pitch better be a power of two tile widths */
2969         pitch_val = obj->stride / tile_width;
2970         pitch_val = ffs(pitch_val) - 1;
2971
2972         val = obj->gtt_offset;
2973         if (obj->tiling_mode == I915_TILING_Y)
2974                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2975         val |= I915_FENCE_SIZE_BITS(size);
2976         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2977         val |= I830_FENCE_REG_VALID;
2978
2979         fence_reg = obj->fence_reg;
2980         if (fence_reg < 8)
2981                 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
2982         else
2983                 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
2984
2985         if (pipelined) {
2986                 int ret = intel_ring_begin(pipelined, 4);
2987                 if (ret)
2988                         return ret;
2989
2990                 intel_ring_emit(pipelined, MI_NOOP);
2991                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2992                 intel_ring_emit(pipelined, fence_reg);
2993                 intel_ring_emit(pipelined, val);
2994                 intel_ring_advance(pipelined);
2995         } else
2996                 I915_WRITE(fence_reg, val);
2997
2998         return 0;
2999 }
3000
3001 static int
3002 i830_write_fence_reg(struct drm_i915_gem_object *obj,
3003     struct intel_ring_buffer *pipelined)
3004 {
3005         struct drm_device *dev = obj->base.dev;
3006         drm_i915_private_t *dev_priv = dev->dev_private;
3007         u32 size = obj->gtt_space->size;
3008         int regnum = obj->fence_reg;
3009         uint32_t val;
3010         uint32_t pitch_val;
3011
3012         if ((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
3013             (size & -size) != size || (obj->gtt_offset & (size - 1))) {
3014                 kprintf(
3015 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
3016                     obj->gtt_offset, size);
3017                 return -EINVAL;
3018         }
3019
3020         pitch_val = obj->stride / 128;
3021         pitch_val = ffs(pitch_val) - 1;
3022
3023         val = obj->gtt_offset;
3024         if (obj->tiling_mode == I915_TILING_Y)
3025                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3026         val |= I830_FENCE_SIZE_BITS(size);
3027         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3028         val |= I830_FENCE_REG_VALID;
3029
3030         if (pipelined) {
3031                 int ret = intel_ring_begin(pipelined, 4);
3032                 if (ret)
3033                         return ret;
3034
3035                 intel_ring_emit(pipelined, MI_NOOP);
3036                 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
3037                 intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4);
3038                 intel_ring_emit(pipelined, val);
3039                 intel_ring_advance(pipelined);
3040         } else
3041                 I915_WRITE(FENCE_REG_830_0 + regnum * 4, val);
3042
3043         return 0;
3044 }
3045
3046 static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno)
3047 {
3048         return i915_seqno_passed(ring->get_seqno(ring), seqno);
3049 }
3050
3051 static int
3052 i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
3053     struct intel_ring_buffer *pipelined)
3054 {
3055         int ret;
3056
3057         if (obj->fenced_gpu_access) {
3058                 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3059                         ret = i915_gem_flush_ring(obj->last_fenced_ring, 0,
3060                             obj->base.write_domain);
3061                         if (ret)
3062                                 return ret;
3063                 }
3064
3065                 obj->fenced_gpu_access = false;
3066         }
3067
3068         if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) {
3069                 if (!ring_passed_seqno(obj->last_fenced_ring,
3070                                        obj->last_fenced_seqno)) {
3071                         ret = i915_wait_request(obj->last_fenced_ring,
3072                                                 obj->last_fenced_seqno,
3073                                                 true);
3074                         if (ret)
3075                                 return ret;
3076                 }
3077
3078                 obj->last_fenced_seqno = 0;
3079                 obj->last_fenced_ring = NULL;
3080         }
3081
3082         /* Ensure that all CPU reads are completed before installing a fence
3083          * and all writes before removing the fence.
3084          */
3085         if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
3086                 cpu_mfence();
3087
3088         return 0;
3089 }
3090
3091 int
3092 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3093 {
3094         int ret;
3095
3096         if (obj->tiling_mode)
3097                 i915_gem_release_mmap(obj);
3098
3099         ret = i915_gem_object_flush_fence(obj, NULL);
3100         if (ret)
3101                 return ret;
3102
3103         if (obj->fence_reg != I915_FENCE_REG_NONE) {
3104                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3105
3106                 if (dev_priv->fence_regs[obj->fence_reg].pin_count != 0)
3107                         kprintf("%s: pin_count %d\n", __func__,
3108                             dev_priv->fence_regs[obj->fence_reg].pin_count);
3109                 i915_gem_clear_fence_reg(obj->base.dev,
3110                                          &dev_priv->fence_regs[obj->fence_reg]);
3111
3112                 obj->fence_reg = I915_FENCE_REG_NONE;
3113         }
3114
3115         return 0;
3116 }
3117
3118 static struct drm_i915_fence_reg *
3119 i915_find_fence_reg(struct drm_device *dev, struct intel_ring_buffer *pipelined)
3120 {
3121         struct drm_i915_private *dev_priv = dev->dev_private;
3122         struct drm_i915_fence_reg *reg, *first, *avail;
3123         int i;
3124
3125         /* First try to find a free reg */
3126         avail = NULL;
3127         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3128                 reg = &dev_priv->fence_regs[i];
3129                 if (!reg->obj)
3130                         return reg;
3131
3132                 if (!reg->pin_count)
3133                         avail = reg;
3134         }
3135
3136         if (avail == NULL)
3137                 return NULL;
3138
3139         /* None available, try to steal one or wait for a user to finish */
3140         avail = first = NULL;
3141         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3142                 if (reg->pin_count)
3143                         continue;
3144
3145                 if (first == NULL)
3146                         first = reg;
3147
3148                 if (!pipelined ||
3149                     !reg->obj->last_fenced_ring ||
3150                     reg->obj->last_fenced_ring == pipelined) {
3151                         avail = reg;
3152                         break;
3153                 }
3154         }
3155
3156         if (avail == NULL)
3157                 avail = first;
3158
3159         return avail;
3160 }
3161
3162 int
3163 i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
3164     struct intel_ring_buffer *pipelined)
3165 {
3166         struct drm_device *dev = obj->base.dev;
3167         struct drm_i915_private *dev_priv = dev->dev_private;
3168         struct drm_i915_fence_reg *reg;
3169         int ret;
3170
3171         pipelined = NULL;
3172         ret = 0;
3173
3174         if (obj->fence_reg != I915_FENCE_REG_NONE) {
3175                 reg = &dev_priv->fence_regs[obj->fence_reg];
3176                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
3177
3178                 if (obj->tiling_changed) {
3179                         ret = i915_gem_object_flush_fence(obj, pipelined);
3180                         if (ret)
3181                                 return ret;
3182
3183                         if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
3184                                 pipelined = NULL;
3185
3186                         if (pipelined) {
3187                                 reg->setup_seqno =
3188                                         i915_gem_next_request_seqno(pipelined);
3189                                 obj->last_fenced_seqno = reg->setup_seqno;
3190                                 obj->last_fenced_ring = pipelined;
3191                         }
3192
3193                         goto update;
3194                 }
3195
3196                 if (!pipelined) {
3197                         if (reg->setup_seqno) {
3198                                 if (!ring_passed_seqno(obj->last_fenced_ring,
3199                                     reg->setup_seqno)) {
3200                                         ret = i915_wait_request(
3201                                             obj->last_fenced_ring,
3202                                             reg->setup_seqno,
3203                                             true);
3204                                         if (ret)
3205                                                 return ret;
3206                                 }
3207
3208                                 reg->setup_seqno = 0;
3209                         }
3210                 } else if (obj->last_fenced_ring &&
3211                            obj->last_fenced_ring != pipelined) {
3212                         ret = i915_gem_object_flush_fence(obj, pipelined);
3213                         if (ret)
3214                                 return ret;
3215                 }
3216
3217                 if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
3218                         pipelined = NULL;
3219                 KASSERT(pipelined || reg->setup_seqno == 0, ("!pipelined"));
3220
3221                 if (obj->tiling_changed) {
3222                         if (pipelined) {
3223                                 reg->setup_seqno =
3224                                         i915_gem_next_request_seqno(pipelined);
3225                                 obj->last_fenced_seqno = reg->setup_seqno;
3226                                 obj->last_fenced_ring = pipelined;
3227                         }
3228                         goto update;
3229                 }
3230
3231                 return 0;
3232         }
3233
3234         reg = i915_find_fence_reg(dev, pipelined);
3235         if (reg == NULL)
3236                 return -EDEADLK;
3237
3238         ret = i915_gem_object_flush_fence(obj, pipelined);
3239         if (ret)
3240                 return ret;
3241
3242         if (reg->obj) {
3243                 struct drm_i915_gem_object *old = reg->obj;
3244
3245                 drm_gem_object_reference(&old->base);
3246
3247                 if (old->tiling_mode)
3248                         i915_gem_release_mmap(old);
3249
3250                 ret = i915_gem_object_flush_fence(old, pipelined);
3251                 if (ret) {
3252                         drm_gem_object_unreference(&old->base);
3253                         return ret;
3254                 }
3255
3256                 if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0)
3257                         pipelined = NULL;
3258
3259                 old->fence_reg = I915_FENCE_REG_NONE;
3260                 old->last_fenced_ring = pipelined;
3261                 old->last_fenced_seqno =
3262                         pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
3263
3264                 drm_gem_object_unreference(&old->base);
3265         } else if (obj->last_fenced_seqno == 0)
3266                 pipelined = NULL;
3267
3268         reg->obj = obj;
3269         list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
3270         obj->fence_reg = reg - dev_priv->fence_regs;
3271         obj->last_fenced_ring = pipelined;
3272
3273         reg->setup_seqno =
3274                 pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
3275         obj->last_fenced_seqno = reg->setup_seqno;
3276
3277 update:
3278         obj->tiling_changed = false;
3279         switch (INTEL_INFO(dev)->gen) {
3280         case 7:
3281         case 6:
3282                 ret = sandybridge_write_fence_reg(obj, pipelined);
3283                 break;
3284         case 5:
3285         case 4:
3286                 ret = i965_write_fence_reg(obj, pipelined);
3287                 break;
3288         case 3:
3289                 ret = i915_write_fence_reg(obj, pipelined);
3290                 break;
3291         case 2:
3292                 ret = i830_write_fence_reg(obj, pipelined);
3293                 break;
3294         }
3295
3296         return ret;
3297 }
3298
3299 static void
3300 i915_gem_clear_fence_reg(struct drm_device *dev, struct drm_i915_fence_reg *reg)
3301 {
3302         drm_i915_private_t *dev_priv = dev->dev_private;
3303         uint32_t fence_reg = reg - dev_priv->fence_regs;
3304
3305         switch (INTEL_INFO(dev)->gen) {
3306         case 7:
3307         case 6:
3308                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
3309                 break;
3310         case 5:
3311         case 4:
3312                 I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0);
3313                 break;
3314         case 3:
3315                 if (fence_reg >= 8)
3316                         fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
3317                 else
3318         case 2:
3319                         fence_reg = FENCE_REG_830_0 + fence_reg * 4;
3320
3321                 I915_WRITE(fence_reg, 0);
3322                 break;
3323         }
3324
3325         list_del_init(&reg->lru_list);
3326         reg->obj = NULL;
3327         reg->setup_seqno = 0;
3328         reg->pin_count = 0;
3329 }
3330
3331 int
3332 i915_gem_init_object(struct drm_gem_object *obj)
3333 {
3334
3335         kprintf("i915_gem_init_object called\n");
3336         return (0);
3337 }
3338
3339 static bool
3340 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
3341 {
3342
3343         return (obj->gtt_space && !obj->active && obj->pin_count == 0);
3344 }
3345
3346 static void
3347 i915_gem_retire_task_handler(void *arg, int pending)
3348 {
3349         drm_i915_private_t *dev_priv;
3350         struct drm_device *dev;
3351         bool idle;
3352         int i;
3353
3354         dev_priv = arg;
3355         dev = dev_priv->dev;
3356
3357         /* Come back later if the device is busy... */
3358         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_NOWAIT)) {
3359                 taskqueue_enqueue_timeout(dev_priv->tq,
3360                     &dev_priv->mm.retire_task, hz);
3361                 return;
3362         }
3363
3364         i915_gem_retire_requests(dev);
3365
3366         /* Send a periodic flush down the ring so we don't hold onto GEM
3367          * objects indefinitely.
3368          */
3369         idle = true;
3370         for (i = 0; i < I915_NUM_RINGS; i++) {
3371                 struct intel_ring_buffer *ring = &dev_priv->rings[i];
3372
3373                 if (!list_empty(&ring->gpu_write_list)) {
3374                         struct drm_i915_gem_request *request;
3375                         int ret;
3376
3377                         ret = i915_gem_flush_ring(ring,
3378                                                   0, I915_GEM_GPU_DOMAINS);
3379                         request = kmalloc(sizeof(*request), DRM_I915_GEM,
3380                             M_WAITOK | M_ZERO);
3381                         if (ret || request == NULL ||
3382                             i915_add_request(ring, NULL, request))
3383                                 drm_free(request, DRM_I915_GEM);
3384                 }
3385
3386                 idle &= list_empty(&ring->request_list);
3387         }
3388
3389         if (!dev_priv->mm.suspended && !idle)
3390                 taskqueue_enqueue_timeout(dev_priv->tq,
3391                     &dev_priv->mm.retire_task, hz);
3392
3393         DRM_UNLOCK(dev);
3394 }
3395
3396 void
3397 i915_gem_lastclose(struct drm_device *dev)
3398 {
3399         int ret;
3400
3401         if (drm_core_check_feature(dev, DRIVER_MODESET))
3402                 return;
3403
3404         ret = i915_gem_idle(dev);
3405         if (ret != 0)
3406                 DRM_ERROR("failed to idle hardware: %d\n", ret);
3407 }
3408
3409 static int
3410 i915_gem_init_phys_object(struct drm_device *dev, int id, int size, int align)
3411 {
3412         drm_i915_private_t *dev_priv;
3413         struct drm_i915_gem_phys_object *phys_obj;
3414         int ret;
3415
3416         dev_priv = dev->dev_private;
3417         if (dev_priv->mm.phys_objs[id - 1] != NULL || size == 0)
3418                 return (0);
3419
3420         phys_obj = kmalloc(sizeof(struct drm_i915_gem_phys_object), DRM_I915_GEM,
3421             M_WAITOK | M_ZERO);
3422
3423         phys_obj->id = id;
3424
3425         phys_obj->handle = drm_pci_alloc(dev, size, align, ~0);
3426         if (phys_obj->handle == NULL) {
3427                 ret = -ENOMEM;
3428                 goto free_obj;
3429         }
3430         pmap_change_attr((vm_offset_t)phys_obj->handle->vaddr,
3431             size / PAGE_SIZE, PAT_WRITE_COMBINING);
3432
3433         dev_priv->mm.phys_objs[id - 1] = phys_obj;
3434
3435         return (0);
3436
3437 free_obj:
3438         drm_free(phys_obj, DRM_I915_GEM);
3439         return (ret);
3440 }
3441
3442 static void
3443 i915_gem_free_phys_object(struct drm_device *dev, int id)
3444 {
3445         drm_i915_private_t *dev_priv;
3446         struct drm_i915_gem_phys_object *phys_obj;
3447
3448         dev_priv = dev->dev_private;
3449         if (dev_priv->mm.phys_objs[id - 1] == NULL)
3450                 return;
3451
3452         phys_obj = dev_priv->mm.phys_objs[id - 1];
3453         if (phys_obj->cur_obj != NULL)
3454                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3455
3456         drm_pci_free(dev, phys_obj->handle);
3457         drm_free(phys_obj, DRM_I915_GEM);
3458         dev_priv->mm.phys_objs[id - 1] = NULL;
3459 }
3460
3461 void
3462 i915_gem_free_all_phys_object(struct drm_device *dev)
3463 {
3464         int i;
3465
3466         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3467                 i915_gem_free_phys_object(dev, i);
3468 }
3469
3470 void
3471 i915_gem_detach_phys_object(struct drm_device *dev,
3472     struct drm_i915_gem_object *obj)
3473 {
3474         vm_page_t m;
3475         struct sf_buf *sf;
3476         char *vaddr, *dst;
3477         int i, page_count;
3478
3479         if (obj->phys_obj == NULL)
3480                 return;
3481         vaddr = obj->phys_obj->handle->vaddr;
3482
3483         page_count = obj->base.size / PAGE_SIZE;
3484         VM_OBJECT_LOCK(obj->base.vm_obj);
3485         for (i = 0; i < page_count; i++) {
3486                 m = i915_gem_wire_page(obj->base.vm_obj, i);
3487                 if (m == NULL)
3488                         continue; /* XXX */
3489
3490                 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3491                 sf = sf_buf_alloc(m);
3492                 if (sf != NULL) {
3493                         dst = (char *)sf_buf_kva(sf);
3494                         memcpy(dst, vaddr + IDX_TO_OFF(i), PAGE_SIZE);
3495                         sf_buf_free(sf);
3496                 }
3497                 drm_clflush_pages(&m, 1);
3498
3499                 VM_OBJECT_LOCK(obj->base.vm_obj);
3500                 vm_page_reference(m);
3501                 vm_page_dirty(m);
3502                 vm_page_busy_wait(m, FALSE, "i915gem");
3503                 vm_page_unwire(m, 0);
3504                 vm_page_wakeup(m);
3505                 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3506         }
3507         VM_OBJECT_UNLOCK(obj->base.vm_obj);
3508         intel_gtt_chipset_flush();
3509
3510         obj->phys_obj->cur_obj = NULL;
3511         obj->phys_obj = NULL;
3512 }
3513
3514 int
3515 i915_gem_attach_phys_object(struct drm_device *dev,
3516     struct drm_i915_gem_object *obj, int id, int align)
3517 {
3518         drm_i915_private_t *dev_priv;
3519         vm_page_t m;
3520         struct sf_buf *sf;
3521         char *dst, *src;
3522         int i, page_count, ret;
3523
3524         if (id > I915_MAX_PHYS_OBJECT)
3525                 return (-EINVAL);
3526
3527         if (obj->phys_obj != NULL) {
3528                 if (obj->phys_obj->id == id)
3529                         return (0);
3530                 i915_gem_detach_phys_object(dev, obj);
3531         }
3532
3533         dev_priv = dev->dev_private;
3534         if (dev_priv->mm.phys_objs[id - 1] == NULL) {
3535                 ret = i915_gem_init_phys_object(dev, id, obj->base.size, align);
3536                 if (ret != 0) {
3537                         DRM_ERROR("failed to init phys object %d size: %zu\n",
3538                                   id, obj->base.size);
3539                         return (ret);
3540                 }
3541         }
3542
3543         /* bind to the object */
3544         obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
3545         obj->phys_obj->cur_obj = obj;
3546
3547         page_count = obj->base.size / PAGE_SIZE;
3548
3549         VM_OBJECT_LOCK(obj->base.vm_obj);
3550         ret = 0;
3551         for (i = 0; i < page_count; i++) {
3552                 m = i915_gem_wire_page(obj->base.vm_obj, i);
3553                 if (m == NULL) {
3554                         ret = -EIO;
3555                         break;
3556                 }
3557                 VM_OBJECT_UNLOCK(obj->base.vm_obj);
3558                 sf = sf_buf_alloc(m);
3559                 src = (char *)sf_buf_kva(sf);
3560                 dst = (char *)obj->phys_obj->handle->vaddr + IDX_TO_OFF(i);
3561                 memcpy(dst, src, PAGE_SIZE);
3562                 sf_buf_free(sf);
3563
3564                 VM_OBJECT_LOCK(obj->base.vm_obj);
3565
3566                 vm_page_reference(m);
3567                 vm_page_busy_wait(m, FALSE, "i915gem");
3568                 vm_page_unwire(m, 0);
3569                 vm_page_wakeup(m);
3570                 atomic_add_long(&i915_gem_wired_pages_cnt, -1);
3571         }
3572         VM_OBJECT_UNLOCK(obj->base.vm_obj);
3573
3574         return (0);
3575 }
3576
3577 static int
3578 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_i915_gem_object *obj,
3579     uint64_t data_ptr, uint64_t offset, uint64_t size,
3580     struct drm_file *file_priv)
3581 {
3582         char *user_data, *vaddr;
3583         int ret;
3584
3585         vaddr = (char *)obj->phys_obj->handle->vaddr + offset;
3586         user_data = (char *)(uintptr_t)data_ptr;
3587
3588         if (copyin_nofault(user_data, vaddr, size) != 0) {
3589                 /* The physical object once assigned is fixed for the lifetime
3590                  * of the obj, so we can safely drop the lock and continue
3591                  * to access vaddr.
3592                  */
3593                 DRM_UNLOCK(dev);
3594                 ret = -copyin(user_data, vaddr, size);
3595                 DRM_LOCK(dev);
3596                 if (ret != 0)
3597                         return (ret);
3598         }
3599
3600         intel_gtt_chipset_flush();
3601         return (0);
3602 }
3603
3604 static int
3605 i915_gpu_is_active(struct drm_device *dev)
3606 {
3607         drm_i915_private_t *dev_priv;
3608
3609         dev_priv = dev->dev_private;
3610         return (!list_empty(&dev_priv->mm.flushing_list) ||
3611             !list_empty(&dev_priv->mm.active_list));
3612 }
3613
3614 static void
3615 i915_gem_lowmem(void *arg)
3616 {
3617         struct drm_device *dev;
3618         struct drm_i915_private *dev_priv;
3619         struct drm_i915_gem_object *obj, *next;
3620         int cnt, cnt_fail, cnt_total;
3621
3622         dev = arg;
3623         dev_priv = dev->dev_private;
3624
3625         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_NOWAIT))
3626                 return;
3627
3628 rescan:
3629         /* first scan for clean buffers */
3630         i915_gem_retire_requests(dev);
3631
3632         cnt_total = cnt_fail = cnt = 0;
3633
3634         list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
3635             mm_list) {
3636                 if (i915_gem_object_is_purgeable(obj)) {
3637                         if (i915_gem_object_unbind(obj) != 0)
3638                                 cnt_total++;
3639                 } else
3640                         cnt_total++;
3641         }
3642
3643         /* second pass, evict/count anything still on the inactive list */
3644         list_for_each_entry_safe(obj, next, &dev_priv->mm.inactive_list,
3645             mm_list) {
3646                 if (i915_gem_object_unbind(obj) == 0)
3647                         cnt++;
3648                 else
3649                         cnt_fail++;
3650         }
3651
3652         if (cnt_fail > cnt_total / 100 && i915_gpu_is_active(dev)) {
3653                 /*
3654                  * We are desperate for pages, so as a last resort, wait
3655                  * for the GPU to finish and discard whatever we can.
3656                  * This has a dramatic impact to reduce the number of
3657                  * OOM-killer events whilst running the GPU aggressively.
3658                  */
3659                 if (i915_gpu_idle(dev, true) == 0)
3660                         goto rescan;
3661         }
3662         DRM_UNLOCK(dev);
3663 }
3664
3665 void
3666 i915_gem_unload(struct drm_device *dev)
3667 {
3668         struct drm_i915_private *dev_priv;
3669
3670         dev_priv = dev->dev_private;
3671         EVENTHANDLER_DEREGISTER(vm_lowmem, dev_priv->mm.i915_lowmem);
3672 }