2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2004 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 #ifndef _ATH_AR5210_H_
20 #define _ATH_AR5210_H_
22 #define AR5210_MAGIC 0x19980124
26 * RTS_ENABLE includes LONG_PKT because they essentially
27 * imply the same thing, and are set or not set together
30 #define AR5210_TXD_CTRL_A_HDR_LEN(_val) (((_val) ) & 0x0003f)
31 #define AR5210_TXD_CTRL_A_TX_RATE(_val) (((_val) << 6) & 0x003c0)
32 #define AR5210_TXD_CTRL_A_RTS_ENABLE ( 0x00c00)
33 #define AR5210_TXD_CTRL_A_CLEAR_DEST_MASK(_val) (((_val) << 12) & 0x01000)
34 #define AR5210_TXD_CTRL_A_ANT_MODE(_val) (((_val) << 13) & 0x02000)
35 #define AR5210_TXD_CTRL_A_PKT_TYPE(_val) (((_val) << 14) & 0x1c000)
36 #define AR5210_TXD_CTRL_A_INT_REQ ( 0x20000)
37 #define AR5210_TXD_CTRL_A_KEY_VALID ( 0x40000)
38 #define AR5210_TXD_CTRL_B_KEY_ID(_val) (((_val) ) & 0x0003f)
39 #define AR5210_TXD_CTRL_B_RTS_DURATION(_val) (((_val) << 6) & 0x7ffc0)
42 #define INIT_CONFIG_STATUS 0x00000000
43 #define INIT_ACKTOPS 0x00000008
44 #define INIT_BCON_CNTRL_REG 0x00000000
45 #define INIT_SLOT_TIME 0x00000168
46 #define INIT_SLOT_TIME_TURBO 0x000001e0 /* More aggressive turbo slot timing = 6 us */
47 #define INIT_ACK_CTS_TIMEOUT 0x04000400
48 #define INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800
50 #define INIT_USEC 0x27
51 #define INIT_USEC_TURBO 0x4f
52 #define INIT_USEC_32 0x1f
53 #define INIT_TX_LATENCY 0x36
54 #define INIT_RX_LATENCY 0x1D
55 #define INIT_TRANSMIT_LATENCY \
56 ((INIT_RX_LATENCY << AR_USEC_RX_LATENCY_S) | \
57 (INIT_TX_LATENCY << AR_USEC_TX_LATENCY_S) | \
58 (INIT_USEC_32 << 7) | INIT_USEC )
59 #define INIT_TRANSMIT_LATENCY_TURBO \
60 ((INIT_RX_LATENCY << AR_USEC_RX_LATENCY_S) | \
61 (INIT_TX_LATENCY << AR_USEC_TX_LATENCY_S) | \
62 (INIT_USEC_32 << 7) | INIT_USEC_TURBO)
64 #define INIT_SIFS 0x230 /* = 16 us - 2 us */
65 #define INIT_SIFS_TURBO 0x1E0 /* More aggressive turbo SIFS timing - 8 us - 2 us */
68 * Various fifo fill before Tx start, in 64-byte units
69 * i.e. put the frame in the air while still DMAing
71 #define MIN_TX_FIFO_THRESHOLD 0x1
72 #define MAX_TX_FIFO_THRESHOLD ((IEEE80211_MAX_LEN / 64) + 1)
74 #define INIT_NEXT_CFP_START 0xffffffff
76 #define INIT_BEACON_PERIOD 0xffff
77 #define INIT_BEACON_EN 0 /* this should be set by AP only when it's ready */
78 #define INIT_BEACON_CONTROL \
79 ((INIT_RESET_TSF << 24) | (INIT_BEACON_EN << 23) | \
80 (INIT_TIM_OFFSET<<16) | INIT_BEACON_PERIOD)
82 #define INIT_RSSI_THR 0x00000700 /* Missed beacon counter initialized to max value of 7 */
83 #define INIT_ProgIFS 0x398 /* PIFS - 2us */
84 #define INIT_ProgIFS_TURBO 0x3C0
85 #define INIT_EIFS 0xd70
86 #define INIT_EIFS_TURBO 0x1ae0
87 #define INIT_CARR_SENSE_EN 1
88 #define INIT_PROTO_TIME_CNTRL ( (INIT_CARR_SENSE_EN << 26) | (INIT_EIFS << 12) | \
90 #define INIT_PROTO_TIME_CNTRL_TURBO ( (INIT_CARR_SENSE_EN << 26) | (INIT_EIFS_TURBO << 12) | \
91 (INIT_ProgIFS_TURBO) )
93 #define AR5210_MAX_RATE_POWER 60
95 #undef HAL_NUM_TX_QUEUES /* from ah.h */
96 #define HAL_NUM_TX_QUEUES 3
99 struct ath_hal_private ah_priv; /* base definitions */
101 uint8_t ah_macaddr[IEEE80211_ADDR_LEN];
105 uint32_t ah_maskReg; /* shadow of IMR+IER regs */
106 uint32_t ah_txOkInterruptMask;
107 uint32_t ah_txErrInterruptMask;
108 uint32_t ah_txDescInterruptMask;
109 uint32_t ah_txEolInterruptMask;
110 uint32_t ah_txUrnInterruptMask;
111 uint8_t ah_bssid[IEEE80211_ADDR_LEN];
112 HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES]; /* beacon+cab+data */
114 * Station mode support.
116 uint32_t ah_staId1Defaults; /* STA_ID1 default settings */
117 uint32_t ah_rssiThr; /* RSSI_THR settings */
119 u_int ah_sifstime; /* user-specified sifs time */
120 u_int ah_slottime; /* user-specified slot time */
121 u_int ah_acktimeout; /* user-specified ack timeout */
122 u_int ah_ctstimeout; /* user-specified cts timeout */
124 uint16_t ah_associd; /* association id */
126 #define AH5210(ah) ((struct ath_hal_5210 *)(ah))
130 extern void ar5210Detach(struct ath_hal *ah);
131 extern HAL_BOOL ar5210Reset(struct ath_hal *, HAL_OPMODE,
132 struct ieee80211_channel *, HAL_BOOL bChannelChange, HAL_STATUS *);
133 extern void ar5210SetPCUConfig(struct ath_hal *);
134 extern HAL_BOOL ar5210PhyDisable(struct ath_hal *);
135 extern HAL_BOOL ar5210Disable(struct ath_hal *);
136 extern HAL_BOOL ar5210ChipReset(struct ath_hal *, struct ieee80211_channel *);
137 extern HAL_BOOL ar5210PerCalibration(struct ath_hal *, struct ieee80211_channel *, HAL_BOOL *);
138 extern HAL_BOOL ar5210PerCalibrationN(struct ath_hal *ah, struct ieee80211_channel *chan,
139 u_int chainMask, HAL_BOOL longCal, HAL_BOOL *isCalDone);
140 extern HAL_BOOL ar5210ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *);
141 extern int16_t ar5210GetNoiseFloor(struct ath_hal *);
142 extern int16_t ar5210GetNfAdjust(struct ath_hal *,
143 const HAL_CHANNEL_INTERNAL *);
144 extern HAL_BOOL ar5210SetTxPowerLimit(struct ath_hal *, uint32_t limit);
145 extern HAL_BOOL ar5210SetTransmitPower(struct ath_hal *,
146 const struct ieee80211_channel *);
147 extern HAL_BOOL ar5210CalNoiseFloor(struct ath_hal *, HAL_CHANNEL_INTERNAL *);
148 extern HAL_BOOL ar5210ResetDma(struct ath_hal *, HAL_OPMODE);
150 extern HAL_BOOL ar5210SetTxQueueProps(struct ath_hal *ah, int q,
151 const HAL_TXQ_INFO *qInfo);
152 extern HAL_BOOL ar5210GetTxQueueProps(struct ath_hal *ah, int q,
153 HAL_TXQ_INFO *qInfo);
154 extern int ar5210SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type,
155 const HAL_TXQ_INFO *qInfo);
156 extern HAL_BOOL ar5210ReleaseTxQueue(struct ath_hal *ah, u_int q);
157 extern HAL_BOOL ar5210ResetTxQueue(struct ath_hal *ah, u_int q);
158 extern uint32_t ar5210GetTxDP(struct ath_hal *, u_int);
159 extern HAL_BOOL ar5210SetTxDP(struct ath_hal *, u_int, uint32_t txdp);
160 extern HAL_BOOL ar5210UpdateTxTrigLevel(struct ath_hal *, HAL_BOOL);
161 extern uint32_t ar5210NumTxPending(struct ath_hal *, u_int);
162 extern HAL_BOOL ar5210StartTxDma(struct ath_hal *, u_int);
163 extern HAL_BOOL ar5210StopTxDma(struct ath_hal *, u_int);
164 extern HAL_BOOL ar5210SetupTxDesc(struct ath_hal *, struct ath_desc *,
165 u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower,
166 u_int txRate0, u_int txRetries0,
167 u_int keyIx, u_int antMode, u_int flags,
168 u_int rtsctsRate, u_int rtsctsDuration,
169 u_int compicvLen, u_int compivLen, u_int comp);
170 extern HAL_BOOL ar5210SetupXTxDesc(struct ath_hal *, struct ath_desc *,
171 u_int txRate1, u_int txRetries1,
172 u_int txRate2, u_int txRetries2,
173 u_int txRate3, u_int txRetries3);
174 extern HAL_BOOL ar5210FillTxDesc(struct ath_hal *, struct ath_desc *,
175 HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList,
176 u_int descId, u_int qcuId, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
177 const struct ath_desc *ds0);
178 extern HAL_STATUS ar5210ProcTxDesc(struct ath_hal *,
179 struct ath_desc *, struct ath_tx_status *);
180 extern void ar5210GetTxIntrQueue(struct ath_hal *ah, uint32_t *);
181 extern void ar5210IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *);
182 extern HAL_BOOL ar5210GetTxCompletionRates(struct ath_hal *ah,
183 const struct ath_desc *, int *rates, int *tries);
184 extern void ar5210SetTxDescLink(struct ath_hal *ah, void *ds,
186 extern void ar5210GetTxDescLink(struct ath_hal *ah, void *ds,
188 extern void ar5210GetTxDescLinkPtr(struct ath_hal *ah, void *ds,
191 extern uint32_t ar5210GetRxDP(struct ath_hal *, HAL_RX_QUEUE);
192 extern void ar5210SetRxDP(struct ath_hal *, uint32_t rxdp, HAL_RX_QUEUE);
193 extern void ar5210EnableReceive(struct ath_hal *);
194 extern HAL_BOOL ar5210StopDmaReceive(struct ath_hal *);
195 extern void ar5210StartPcuReceive(struct ath_hal *);
196 extern void ar5210StopPcuReceive(struct ath_hal *);
197 extern void ar5210SetMulticastFilter(struct ath_hal *,
198 uint32_t filter0, uint32_t filter1);
199 extern HAL_BOOL ar5210ClrMulticastFilterIndex(struct ath_hal *, uint32_t);
200 extern HAL_BOOL ar5210SetMulticastFilterIndex(struct ath_hal *, uint32_t);
201 extern uint32_t ar5210GetRxFilter(struct ath_hal *);
202 extern void ar5210SetRxFilter(struct ath_hal *, uint32_t);
203 extern HAL_BOOL ar5210SetupRxDesc(struct ath_hal *, struct ath_desc *,
204 uint32_t, u_int flags);
205 extern HAL_STATUS ar5210ProcRxDesc(struct ath_hal *, struct ath_desc *,
206 uint32_t, struct ath_desc *, uint64_t,
207 struct ath_rx_status *);
209 extern void ar5210GetMacAddress(struct ath_hal *, uint8_t *);
210 extern HAL_BOOL ar5210SetMacAddress(struct ath_hal *ah, const uint8_t *);
211 extern void ar5210GetBssIdMask(struct ath_hal *, uint8_t *);
212 extern HAL_BOOL ar5210SetBssIdMask(struct ath_hal *, const uint8_t *);
213 extern HAL_BOOL ar5210EepromRead(struct ath_hal *, u_int off, uint16_t *data);
214 extern HAL_BOOL ar5210EepromWrite(struct ath_hal *, u_int off, uint16_t data);
215 extern HAL_BOOL ar5210SetRegulatoryDomain(struct ath_hal *,
216 uint16_t, HAL_STATUS *);
217 extern u_int ar5210GetWirelessModes(struct ath_hal *ah);
218 extern void ar5210EnableRfKill(struct ath_hal *);
219 extern HAL_BOOL ar5210GpioCfgInput(struct ath_hal *, uint32_t gpio);
220 extern HAL_BOOL ar5210GpioCfgOutput(struct ath_hal *, uint32_t gpio,
222 extern uint32_t ar5210GpioGet(struct ath_hal *, uint32_t gpio);
223 extern HAL_BOOL ar5210GpioSet(struct ath_hal *, uint32_t gpio, uint32_t);
224 extern void ar5210Gpio0SetIntr(struct ath_hal *, u_int, uint32_t ilevel);
225 extern void ar5210SetLedState(struct ath_hal *, HAL_LED_STATE);
226 extern u_int ar5210GetDefAntenna(struct ath_hal *);
227 extern void ar5210SetDefAntenna(struct ath_hal *, u_int);
228 extern HAL_ANT_SETTING ar5210GetAntennaSwitch(struct ath_hal *);
229 extern HAL_BOOL ar5210SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING);
230 extern void ar5210WriteAssocid(struct ath_hal *,
231 const uint8_t *bssid, uint16_t assocId);
232 extern uint32_t ar5210GetTsf32(struct ath_hal *);
233 extern uint64_t ar5210GetTsf64(struct ath_hal *);
234 extern void ar5210ResetTsf(struct ath_hal *);
235 extern uint32_t ar5210GetRandomSeed(struct ath_hal *);
236 extern HAL_BOOL ar5210DetectCardPresent(struct ath_hal *);
237 extern void ar5210UpdateMibCounters(struct ath_hal *, HAL_MIB_STATS *);
238 extern void ar5210EnableHwEncryption(struct ath_hal *);
239 extern void ar5210DisableHwEncryption(struct ath_hal *);
240 extern HAL_RFGAIN ar5210GetRfgain(struct ath_hal *);
241 extern HAL_BOOL ar5210SetSifsTime(struct ath_hal *, u_int);
242 extern u_int ar5210GetSifsTime(struct ath_hal *);
243 extern HAL_BOOL ar5210SetSlotTime(struct ath_hal *, u_int);
244 extern u_int ar5210GetSlotTime(struct ath_hal *);
245 extern HAL_BOOL ar5210SetAckTimeout(struct ath_hal *, u_int);
246 extern u_int ar5210GetAckTimeout(struct ath_hal *);
247 extern HAL_BOOL ar5210SetAckCTSRate(struct ath_hal *, u_int);
248 extern u_int ar5210GetAckCTSRate(struct ath_hal *);
249 extern HAL_BOOL ar5210SetCTSTimeout(struct ath_hal *, u_int);
250 extern u_int ar5210GetCTSTimeout(struct ath_hal *);
251 extern HAL_BOOL ar5210SetDecompMask(struct ath_hal *, uint16_t, int);
252 void ar5210SetCoverageClass(struct ath_hal *, uint8_t, int);
253 extern HAL_STATUS ar5210GetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
254 uint32_t, uint32_t *);
255 extern HAL_BOOL ar5210SetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
256 uint32_t, uint32_t, HAL_STATUS *);
257 extern HAL_BOOL ar5210GetDiagState(struct ath_hal *ah, int request,
258 const void *args, uint32_t argsize,
259 void **result, uint32_t *resultsize);
260 extern uint32_t ar5210Get11nExtBusy(struct ath_hal *);
261 extern HAL_BOOL ar5210GetMibCycleCounts(struct ath_hal *,
262 HAL_SURVEY_SAMPLE *);
263 extern void ar5210SetChainMasks(struct ath_hal *, uint32_t, uint32_t);
264 extern void ar5210EnableDfs(struct ath_hal *, HAL_PHYERR_PARAM *);
265 extern void ar5210GetDfsThresh(struct ath_hal *, HAL_PHYERR_PARAM *);
266 extern void ar5210UpdateDiagReg(struct ath_hal *ah, uint32_t val);
268 extern u_int ar5210GetKeyCacheSize(struct ath_hal *);
269 extern HAL_BOOL ar5210IsKeyCacheEntryValid(struct ath_hal *, uint16_t);
270 extern HAL_BOOL ar5210ResetKeyCacheEntry(struct ath_hal *, uint16_t entry);
271 extern HAL_BOOL ar5210SetKeyCacheEntry(struct ath_hal *, uint16_t entry,
272 const HAL_KEYVAL *, const uint8_t *mac, int xorKey);
273 extern HAL_BOOL ar5210SetKeyCacheEntryMac(struct ath_hal *,
274 uint16_t, const uint8_t *);
276 extern HAL_BOOL ar5210SetPowerMode(struct ath_hal *, uint32_t powerRequest,
278 extern HAL_POWER_MODE ar5210GetPowerMode(struct ath_hal *);
280 extern void ar5210SetBeaconTimers(struct ath_hal *,
281 const HAL_BEACON_TIMERS *);
282 extern void ar5210BeaconInit(struct ath_hal *, uint32_t, uint32_t);
283 extern void ar5210SetStaBeaconTimers(struct ath_hal *,
284 const HAL_BEACON_STATE *);
285 extern void ar5210ResetStaBeaconTimers(struct ath_hal *);
286 extern uint64_t ar5210GetNextTBTT(struct ath_hal *);
288 extern HAL_BOOL ar5210IsInterruptPending(struct ath_hal *);
289 extern HAL_BOOL ar5210GetPendingInterrupts(struct ath_hal *, HAL_INT *);
290 extern HAL_INT ar5210GetInterrupts(struct ath_hal *);
291 extern HAL_INT ar5210SetInterrupts(struct ath_hal *, HAL_INT ints);
293 extern const HAL_RATE_TABLE *ar5210GetRateTable(struct ath_hal *, u_int mode);
295 extern HAL_BOOL ar5210AniControl(struct ath_hal *, HAL_ANI_CMD, int );
296 extern void ar5210AniPoll(struct ath_hal *, const struct ieee80211_channel *);
297 extern void ar5210RxMonitor(struct ath_hal *, const HAL_NODE_STATS *,
298 const struct ieee80211_channel *);
299 extern void ar5210MibEvent(struct ath_hal *, const HAL_NODE_STATS *);
300 #endif /* _ATH_AR5210_H_ */