2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
4 * Copyright (c) 2001-2008, Intel Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
67 #include "opt_ifpoll.h"
70 #include <sys/param.h>
72 #include <sys/endian.h>
73 #include <sys/interrupt.h>
74 #include <sys/kernel.h>
76 #include <sys/malloc.h>
80 #include <sys/serialize.h>
81 #include <sys/serialize2.h>
82 #include <sys/socket.h>
83 #include <sys/sockio.h>
84 #include <sys/sysctl.h>
85 #include <sys/systm.h>
88 #include <net/ethernet.h>
90 #include <net/if_arp.h>
91 #include <net/if_dl.h>
92 #include <net/if_media.h>
93 #include <net/ifq_var.h>
94 #include <net/toeplitz.h>
95 #include <net/toeplitz2.h>
96 #include <net/vlan/if_vlan_var.h>
97 #include <net/vlan/if_vlan_ether.h>
98 #include <net/if_poll.h>
100 #include <netinet/in_systm.h>
101 #include <netinet/in.h>
102 #include <netinet/ip.h>
103 #include <netinet/tcp.h>
104 #include <netinet/udp.h>
106 #include <bus/pci/pcivar.h>
107 #include <bus/pci/pcireg.h>
109 #include <dev/netif/ig_hal/e1000_api.h>
110 #include <dev/netif/ig_hal/e1000_82571.h>
111 #include <dev/netif/emx/if_emx.h>
116 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \
118 if (sc->rss_debug >= lvl) \
119 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
121 #else /* !EMX_RSS_DEBUG */
122 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
123 #endif /* EMX_RSS_DEBUG */
125 #define EMX_NAME "Intel(R) PRO/1000 "
127 #define EMX_DEVICE(id) \
128 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id }
129 #define EMX_DEVICE_NULL { 0, 0, NULL }
131 static const struct emx_device {
136 EMX_DEVICE(82571EB_COPPER),
137 EMX_DEVICE(82571EB_FIBER),
138 EMX_DEVICE(82571EB_SERDES),
139 EMX_DEVICE(82571EB_SERDES_DUAL),
140 EMX_DEVICE(82571EB_SERDES_QUAD),
141 EMX_DEVICE(82571EB_QUAD_COPPER),
142 EMX_DEVICE(82571EB_QUAD_COPPER_BP),
143 EMX_DEVICE(82571EB_QUAD_COPPER_LP),
144 EMX_DEVICE(82571EB_QUAD_FIBER),
145 EMX_DEVICE(82571PT_QUAD_COPPER),
147 EMX_DEVICE(82572EI_COPPER),
148 EMX_DEVICE(82572EI_FIBER),
149 EMX_DEVICE(82572EI_SERDES),
153 EMX_DEVICE(82573E_IAMT),
156 EMX_DEVICE(80003ES2LAN_COPPER_SPT),
157 EMX_DEVICE(80003ES2LAN_SERDES_SPT),
158 EMX_DEVICE(80003ES2LAN_COPPER_DPT),
159 EMX_DEVICE(80003ES2LAN_SERDES_DPT),
164 /* required last entry */
168 static int emx_probe(device_t);
169 static int emx_attach(device_t);
170 static int emx_detach(device_t);
171 static int emx_shutdown(device_t);
172 static int emx_suspend(device_t);
173 static int emx_resume(device_t);
175 static void emx_init(void *);
176 static void emx_stop(struct emx_softc *);
177 static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
178 static void emx_start(struct ifnet *, struct ifaltq_subque *);
180 static void emx_npoll(struct ifnet *, struct ifpoll_info *);
181 static void emx_npoll_status(struct ifnet *);
182 static void emx_npoll_tx(struct ifnet *, void *, int);
183 static void emx_npoll_rx(struct ifnet *, void *, int);
185 static void emx_watchdog(struct ifaltq_subque *);
186 static void emx_media_status(struct ifnet *, struct ifmediareq *);
187 static int emx_media_change(struct ifnet *);
188 static void emx_timer(void *);
189 static void emx_serialize(struct ifnet *, enum ifnet_serialize);
190 static void emx_deserialize(struct ifnet *, enum ifnet_serialize);
191 static int emx_tryserialize(struct ifnet *, enum ifnet_serialize);
193 static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize,
197 static void emx_intr(void *);
198 static void emx_intr_mask(void *);
199 static void emx_intr_body(struct emx_softc *, boolean_t);
200 static void emx_rxeof(struct emx_rxdata *, int);
201 static void emx_txeof(struct emx_txdata *);
202 static void emx_tx_collect(struct emx_txdata *);
203 static void emx_tx_purge(struct emx_softc *);
204 static void emx_enable_intr(struct emx_softc *);
205 static void emx_disable_intr(struct emx_softc *);
207 static int emx_dma_alloc(struct emx_softc *);
208 static void emx_dma_free(struct emx_softc *);
209 static void emx_init_tx_ring(struct emx_txdata *);
210 static int emx_init_rx_ring(struct emx_rxdata *);
211 static void emx_free_tx_ring(struct emx_txdata *);
212 static void emx_free_rx_ring(struct emx_rxdata *);
213 static int emx_create_tx_ring(struct emx_txdata *);
214 static int emx_create_rx_ring(struct emx_rxdata *);
215 static void emx_destroy_tx_ring(struct emx_txdata *, int);
216 static void emx_destroy_rx_ring(struct emx_rxdata *, int);
217 static int emx_newbuf(struct emx_rxdata *, int, int);
218 static int emx_encap(struct emx_txdata *, struct mbuf **, int *, int *);
219 static int emx_txcsum(struct emx_txdata *, struct mbuf *,
220 uint32_t *, uint32_t *);
221 static int emx_tso_pullup(struct emx_txdata *, struct mbuf **);
222 static int emx_tso_setup(struct emx_txdata *, struct mbuf *,
223 uint32_t *, uint32_t *);
224 static int emx_get_txring_inuse(const struct emx_softc *, boolean_t);
226 static int emx_is_valid_eaddr(const uint8_t *);
227 static int emx_reset(struct emx_softc *);
228 static void emx_setup_ifp(struct emx_softc *);
229 static void emx_init_tx_unit(struct emx_softc *);
230 static void emx_init_rx_unit(struct emx_softc *);
231 static void emx_update_stats(struct emx_softc *);
232 static void emx_set_promisc(struct emx_softc *);
233 static void emx_disable_promisc(struct emx_softc *);
234 static void emx_set_multi(struct emx_softc *);
235 static void emx_update_link_status(struct emx_softc *);
236 static void emx_smartspeed(struct emx_softc *);
237 static void emx_set_itr(struct emx_softc *, uint32_t);
238 static void emx_disable_aspm(struct emx_softc *);
240 static void emx_print_debug_info(struct emx_softc *);
241 static void emx_print_nvm_info(struct emx_softc *);
242 static void emx_print_hw_stats(struct emx_softc *);
244 static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS);
245 static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
246 static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
247 static int emx_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
248 static int emx_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS);
250 static int emx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
251 static int emx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
253 static void emx_add_sysctl(struct emx_softc *);
255 static void emx_serialize_skipmain(struct emx_softc *);
256 static void emx_deserialize_skipmain(struct emx_softc *);
258 /* Management and WOL Support */
259 static void emx_get_mgmt(struct emx_softc *);
260 static void emx_rel_mgmt(struct emx_softc *);
261 static void emx_get_hw_control(struct emx_softc *);
262 static void emx_rel_hw_control(struct emx_softc *);
263 static void emx_enable_wol(device_t);
265 static device_method_t emx_methods[] = {
266 /* Device interface */
267 DEVMETHOD(device_probe, emx_probe),
268 DEVMETHOD(device_attach, emx_attach),
269 DEVMETHOD(device_detach, emx_detach),
270 DEVMETHOD(device_shutdown, emx_shutdown),
271 DEVMETHOD(device_suspend, emx_suspend),
272 DEVMETHOD(device_resume, emx_resume),
276 static driver_t emx_driver = {
279 sizeof(struct emx_softc),
282 static devclass_t emx_devclass;
284 DECLARE_DUMMY_MODULE(if_emx);
285 MODULE_DEPEND(emx, ig_hal, 1, 1, 1);
286 DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, NULL, NULL);
291 static int emx_int_throttle_ceil = EMX_DEFAULT_ITR;
292 static int emx_rxd = EMX_DEFAULT_RXD;
293 static int emx_txd = EMX_DEFAULT_TXD;
294 static int emx_smart_pwr_down = 0;
295 static int emx_rxr = 0;
296 static int emx_txr = 1;
298 /* Controls whether promiscuous also shows bad packets */
299 static int emx_debug_sbp = 0;
301 static int emx_82573_workaround = 1;
302 static int emx_msi_enable = 1;
304 TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil);
305 TUNABLE_INT("hw.emx.rxd", &emx_rxd);
306 TUNABLE_INT("hw.emx.rxr", &emx_rxr);
307 TUNABLE_INT("hw.emx.txd", &emx_txd);
308 TUNABLE_INT("hw.emx.txr", &emx_txr);
309 TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down);
310 TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp);
311 TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround);
312 TUNABLE_INT("hw.emx.msi.enable", &emx_msi_enable);
314 /* Global used in WOL setup with multiport cards */
315 static int emx_global_quad_port_a = 0;
317 /* Set this to one to display debug statistics */
318 static int emx_display_debug_stats = 0;
320 #if !defined(KTR_IF_EMX)
321 #define KTR_IF_EMX KTR_ALL
323 KTR_INFO_MASTER(if_emx);
324 KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin");
325 KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end");
326 KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet");
327 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet");
328 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean");
329 #define logif(name) KTR_LOG(if_emx_ ## name)
332 emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf)
334 rxd->rxd_bufaddr = htole64(rxbuf->paddr);
335 /* DD bit must be cleared */
336 rxd->rxd_staterr = 0;
340 emx_rxcsum(uint32_t staterr, struct mbuf *mp)
342 /* Ignore Checksum bit is set */
343 if (staterr & E1000_RXD_STAT_IXSM)
346 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
348 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
350 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
351 E1000_RXD_STAT_TCPCS) {
352 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
354 CSUM_FRAG_NOT_CHECKED;
355 mp->m_pkthdr.csum_data = htons(0xffff);
359 static __inline struct pktinfo *
360 emx_rssinfo(struct mbuf *m, struct pktinfo *pi,
361 uint32_t mrq, uint32_t hash, uint32_t staterr)
363 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) {
364 case EMX_RXDMRQ_IPV4_TCP:
365 pi->pi_netisr = NETISR_IP;
367 pi->pi_l3proto = IPPROTO_TCP;
370 case EMX_RXDMRQ_IPV6_TCP:
371 pi->pi_netisr = NETISR_IPV6;
373 pi->pi_l3proto = IPPROTO_TCP;
376 case EMX_RXDMRQ_IPV4:
377 if (staterr & E1000_RXD_STAT_IXSM)
381 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
382 E1000_RXD_STAT_TCPCS) {
383 pi->pi_netisr = NETISR_IP;
385 pi->pi_l3proto = IPPROTO_UDP;
393 m->m_flags |= M_HASH;
394 m->m_pkthdr.hash = toeplitz_hash(hash);
399 emx_probe(device_t dev)
401 const struct emx_device *d;
404 vid = pci_get_vendor(dev);
405 did = pci_get_device(dev);
407 for (d = emx_devices; d->desc != NULL; ++d) {
408 if (vid == d->vid && did == d->did) {
409 device_set_desc(dev, d->desc);
410 device_set_async_attach(dev, TRUE);
418 emx_attach(device_t dev)
420 struct emx_softc *sc = device_get_softc(dev);
421 int error = 0, i, throttle, msi_enable, tx_ring_max;
423 uint16_t eeprom_data, device_id, apme_mask;
424 driver_intr_t *intr_func;
426 int offset, offset_def;
432 for (i = 0; i < EMX_NRX_RING; ++i) {
433 sc->rx_data[i].sc = sc;
434 sc->rx_data[i].idx = i;
440 for (i = 0; i < EMX_NTX_RING; ++i) {
441 sc->tx_data[i].sc = sc;
442 sc->tx_data[i].idx = i;
446 * Initialize serializers
448 lwkt_serialize_init(&sc->main_serialize);
449 for (i = 0; i < EMX_NTX_RING; ++i)
450 lwkt_serialize_init(&sc->tx_data[i].tx_serialize);
451 for (i = 0; i < EMX_NRX_RING; ++i)
452 lwkt_serialize_init(&sc->rx_data[i].rx_serialize);
455 * Initialize serializer array
459 KKASSERT(i < EMX_NSERIALIZE);
460 sc->serializes[i++] = &sc->main_serialize;
462 KKASSERT(i < EMX_NSERIALIZE);
463 sc->serializes[i++] = &sc->tx_data[0].tx_serialize;
464 KKASSERT(i < EMX_NSERIALIZE);
465 sc->serializes[i++] = &sc->tx_data[1].tx_serialize;
467 KKASSERT(i < EMX_NSERIALIZE);
468 sc->serializes[i++] = &sc->rx_data[0].rx_serialize;
469 KKASSERT(i < EMX_NSERIALIZE);
470 sc->serializes[i++] = &sc->rx_data[1].rx_serialize;
472 KKASSERT(i == EMX_NSERIALIZE);
474 callout_init_mp(&sc->timer);
476 sc->dev = sc->osdep.dev = dev;
479 * Determine hardware and mac type
481 sc->hw.vendor_id = pci_get_vendor(dev);
482 sc->hw.device_id = pci_get_device(dev);
483 sc->hw.revision_id = pci_get_revid(dev);
484 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev);
485 sc->hw.subsystem_device_id = pci_get_subdevice(dev);
487 if (e1000_set_mac_type(&sc->hw))
490 /* Enable bus mastering */
491 pci_enable_busmaster(dev);
496 sc->memory_rid = EMX_BAR_MEM;
497 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
498 &sc->memory_rid, RF_ACTIVE);
499 if (sc->memory == NULL) {
500 device_printf(dev, "Unable to allocate bus resource: memory\n");
504 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
505 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
507 /* XXX This is quite goofy, it is not actually used */
508 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
511 * Don't enable MSI-X on 82574, see:
512 * 82574 specification update errata #15
514 * Don't enable MSI on 82571/82572, see:
515 * 82571/82572 specification update errata #63
517 msi_enable = emx_msi_enable;
519 (sc->hw.mac.type == e1000_82571 ||
520 sc->hw.mac.type == e1000_82572))
526 sc->intr_type = pci_alloc_1intr(dev, msi_enable,
527 &sc->intr_rid, &intr_flags);
529 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
532 unshared = device_getenv_int(dev, "irq.unshared", 0);
534 sc->flags |= EMX_FLAG_SHARED_INTR;
536 device_printf(dev, "IRQ shared\n");
538 intr_flags &= ~RF_SHAREABLE;
540 device_printf(dev, "IRQ unshared\n");
544 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
546 if (sc->intr_res == NULL) {
547 device_printf(dev, "Unable to allocate bus resource: "
553 /* Save PCI command register for Shared Code */
554 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
555 sc->hw.back = &sc->osdep;
557 /* Do Shared Code initialization */
558 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
559 device_printf(dev, "Setup of Shared code failed\n");
563 e1000_get_bus_info(&sc->hw);
565 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
566 sc->hw.phy.autoneg_wait_to_complete = FALSE;
567 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
570 * Interrupt throttle rate
572 throttle = device_getenv_int(dev, "int_throttle_ceil",
573 emx_int_throttle_ceil);
575 sc->int_throttle_ceil = 0;
578 throttle = EMX_DEFAULT_ITR;
580 /* Recalculate the tunable value to get the exact frequency. */
581 throttle = 1000000000 / 256 / throttle;
583 /* Upper 16bits of ITR is reserved and should be zero */
584 if (throttle & 0xffff0000)
585 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR;
587 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
590 e1000_init_script_state_82541(&sc->hw, TRUE);
591 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE);
594 if (sc->hw.phy.media_type == e1000_media_type_copper) {
595 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES;
596 sc->hw.phy.disable_polarity_correction = FALSE;
597 sc->hw.phy.ms_type = EMX_MASTER_SLAVE;
600 /* Set the frame limits assuming standard ethernet sized frames. */
601 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
602 sc->min_frame_size = ETHER_MIN_LEN;
604 /* This controls when hardware reports transmit completion status. */
605 sc->hw.mac.report_tx_early = 1;
607 /* Calculate # of RX rings */
608 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", emx_rxr);
609 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, EMX_NRX_RING);
612 * Calculate # of TX rings
615 * Don't enable multiple TX queues on 82574; it always gives
616 * watchdog timeout on TX queue0, when multiple TCP streams are
617 * received. It was originally suspected that the hardware TX
618 * checksum offloading caused this watchdog timeout, since only
619 * TCP ACKs are sent during TCP receiving tests. However, even
620 * if the hardware TX checksum offloading is disable, TX queue0
621 * still will give watchdog.
624 if (sc->hw.mac.type == e1000_82571 ||
625 sc->hw.mac.type == e1000_82572 ||
626 sc->hw.mac.type == e1000_80003es2lan)
627 tx_ring_max = EMX_NTX_RING;
628 sc->tx_ring_cnt = device_getenv_int(dev, "txr", emx_txr);
629 sc->tx_ring_cnt = if_ring_count2(sc->tx_ring_cnt, tx_ring_max);
631 /* Allocate RX/TX rings' busdma(9) stuffs */
632 error = emx_dma_alloc(sc);
636 /* Allocate multicast array memory. */
637 sc->mta = kmalloc(ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX,
640 /* Indicate SOL/IDER usage */
641 if (e1000_check_reset_block(&sc->hw)) {
643 "PHY reset is blocked due to SOL/IDER session.\n");
647 * Start from a known state, this is important in reading the
648 * nvm and mac from that.
650 e1000_reset_hw(&sc->hw);
652 /* Make sure we have a good EEPROM before we read from it */
653 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
655 * Some PCI-E parts fail the first check due to
656 * the link being in sleep state, call it again,
657 * if it fails a second time its a real issue.
659 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
661 "The EEPROM Checksum Is Not Valid\n");
667 /* Copy the permanent MAC address out of the EEPROM */
668 if (e1000_read_mac_addr(&sc->hw) < 0) {
669 device_printf(dev, "EEPROM read error while reading MAC"
674 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) {
675 device_printf(dev, "Invalid MAC address\n");
680 /* Determine if we have to control management hardware */
681 if (e1000_enable_mng_pass_thru(&sc->hw))
682 sc->flags |= EMX_FLAG_HAS_MGMT;
687 apme_mask = EMX_EEPROM_APME;
689 switch (sc->hw.mac.type) {
691 sc->flags |= EMX_FLAG_HAS_AMT;
696 case e1000_80003es2lan:
697 if (sc->hw.bus.func == 1) {
698 e1000_read_nvm(&sc->hw,
699 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
701 e1000_read_nvm(&sc->hw,
702 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
707 e1000_read_nvm(&sc->hw,
708 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
711 if (eeprom_data & apme_mask)
712 sc->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
715 * We have the eeprom settings, now apply the special cases
716 * where the eeprom may be wrong or the board won't support
717 * wake on lan on a particular port
719 device_id = pci_get_device(dev);
721 case E1000_DEV_ID_82571EB_FIBER:
723 * Wake events only supported on port A for dual fiber
724 * regardless of eeprom setting
726 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
731 case E1000_DEV_ID_82571EB_QUAD_COPPER:
732 case E1000_DEV_ID_82571EB_QUAD_FIBER:
733 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
734 /* if quad port sc, disable WoL on all but port A */
735 if (emx_global_quad_port_a != 0)
737 /* Reset for multiple quad port adapters */
738 if (++emx_global_quad_port_a == 4)
739 emx_global_quad_port_a = 0;
743 /* XXX disable wol */
748 * NPOLLING RX CPU offset
750 if (sc->rx_ring_cnt == ncpus2) {
753 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2;
754 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
755 if (offset >= ncpus2 ||
756 offset % sc->rx_ring_cnt != 0) {
757 device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
762 sc->rx_npoll_off = offset;
765 * NPOLLING TX CPU offset
767 if (sc->tx_ring_cnt == ncpus2) {
770 offset_def = (sc->tx_ring_cnt * device_get_unit(dev)) % ncpus2;
771 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
772 if (offset >= ncpus2 ||
773 offset % sc->tx_ring_cnt != 0) {
774 device_printf(dev, "invalid npoll.txoff %d, use %d\n",
779 sc->tx_npoll_off = offset;
781 sc->tx_ring_inuse = emx_get_txring_inuse(sc, FALSE);
783 /* Setup OS specific network interface */
786 /* Add sysctl tree, must after em_setup_ifp() */
789 /* Reset the hardware */
790 error = emx_reset(sc);
792 device_printf(dev, "Unable to reset the hardware\n");
796 /* Initialize statistics */
797 emx_update_stats(sc);
799 sc->hw.mac.get_link_status = 1;
800 emx_update_link_status(sc);
802 /* Non-AMT based hardware can now take control from firmware */
803 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) ==
805 emx_get_hw_control(sc);
808 * Missing Interrupt Following ICR read:
810 * 82571/82572 specification update errata #76
811 * 82573 specification update errata #31
812 * 82574 specification update errata #12
814 intr_func = emx_intr;
815 if ((sc->flags & EMX_FLAG_SHARED_INTR) &&
816 (sc->hw.mac.type == e1000_82571 ||
817 sc->hw.mac.type == e1000_82572 ||
818 sc->hw.mac.type == e1000_82573 ||
819 sc->hw.mac.type == e1000_82574))
820 intr_func = emx_intr_mask;
822 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, intr_func, sc,
823 &sc->intr_tag, &sc->main_serialize);
825 device_printf(dev, "Failed to register interrupt handler");
826 ether_ifdetach(&sc->arpcom.ac_if);
836 emx_detach(device_t dev)
838 struct emx_softc *sc = device_get_softc(dev);
840 if (device_is_attached(dev)) {
841 struct ifnet *ifp = &sc->arpcom.ac_if;
843 ifnet_serialize_all(ifp);
847 e1000_phy_hw_reset(&sc->hw);
850 emx_rel_hw_control(sc);
853 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
854 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
858 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
860 ifnet_deserialize_all(ifp);
863 } else if (sc->memory != NULL) {
864 emx_rel_hw_control(sc);
866 bus_generic_detach(dev);
868 if (sc->intr_res != NULL) {
869 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
873 if (sc->intr_type == PCI_INTR_TYPE_MSI)
874 pci_release_msi(dev);
876 if (sc->memory != NULL) {
877 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid,
883 /* Free sysctl tree */
884 if (sc->sysctl_tree != NULL)
885 sysctl_ctx_free(&sc->sysctl_ctx);
888 kfree(sc->mta, M_DEVBUF);
894 emx_shutdown(device_t dev)
896 return emx_suspend(dev);
900 emx_suspend(device_t dev)
902 struct emx_softc *sc = device_get_softc(dev);
903 struct ifnet *ifp = &sc->arpcom.ac_if;
905 ifnet_serialize_all(ifp);
910 emx_rel_hw_control(sc);
913 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
914 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
918 ifnet_deserialize_all(ifp);
920 return bus_generic_suspend(dev);
924 emx_resume(device_t dev)
926 struct emx_softc *sc = device_get_softc(dev);
927 struct ifnet *ifp = &sc->arpcom.ac_if;
930 ifnet_serialize_all(ifp);
934 for (i = 0; i < sc->tx_ring_inuse; ++i)
935 ifsq_devstart_sched(sc->tx_data[i].ifsq);
937 ifnet_deserialize_all(ifp);
939 return bus_generic_resume(dev);
943 emx_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
945 struct emx_softc *sc = ifp->if_softc;
946 struct emx_txdata *tdata = ifsq_get_priv(ifsq);
948 int idx = -1, nsegs = 0;
950 KKASSERT(tdata->ifsq == ifsq);
951 ASSERT_SERIALIZED(&tdata->tx_serialize);
953 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq))
956 if (!sc->link_active || (tdata->tx_flags & EMX_TXFLAG_ENABLED) == 0) {
961 while (!ifsq_is_empty(ifsq)) {
962 /* Now do we at least have a minimal? */
963 if (EMX_IS_OACTIVE(tdata)) {
964 emx_tx_collect(tdata);
965 if (EMX_IS_OACTIVE(tdata)) {
966 ifsq_set_oactive(ifsq);
972 m_head = ifsq_dequeue(ifsq, NULL);
976 if (emx_encap(tdata, &m_head, &nsegs, &idx)) {
977 IFNET_STAT_INC(ifp, oerrors, 1);
978 emx_tx_collect(tdata);
982 if (nsegs >= tdata->tx_wreg_nsegs) {
983 E1000_WRITE_REG(&sc->hw, E1000_TDT(tdata->idx), idx);
988 /* Send a copy of the frame to the BPF listener */
989 ETHER_BPF_MTAP(ifp, m_head);
991 /* Set timeout in case hardware has problems transmitting. */
992 tdata->tx_watchdog.wd_timer = EMX_TX_TIMEOUT;
995 E1000_WRITE_REG(&sc->hw, E1000_TDT(tdata->idx), idx);
999 emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1001 struct emx_softc *sc = ifp->if_softc;
1002 struct ifreq *ifr = (struct ifreq *)data;
1003 uint16_t eeprom_data = 0;
1004 int max_frame_size, mask, reinit;
1007 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1011 switch (sc->hw.mac.type) {
1014 * 82573 only supports jumbo frames
1015 * if ASPM is disabled.
1017 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1,
1019 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
1020 max_frame_size = ETHER_MAX_LEN;
1025 /* Limit Jumbo Frame size */
1029 case e1000_80003es2lan:
1030 max_frame_size = 9234;
1034 max_frame_size = MAX_JUMBO_FRAME_SIZE;
1037 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
1043 ifp->if_mtu = ifr->ifr_mtu;
1044 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
1047 if (ifp->if_flags & IFF_RUNNING)
1052 if (ifp->if_flags & IFF_UP) {
1053 if ((ifp->if_flags & IFF_RUNNING)) {
1054 if ((ifp->if_flags ^ sc->if_flags) &
1055 (IFF_PROMISC | IFF_ALLMULTI)) {
1056 emx_disable_promisc(sc);
1057 emx_set_promisc(sc);
1062 } else if (ifp->if_flags & IFF_RUNNING) {
1065 sc->if_flags = ifp->if_flags;
1070 if (ifp->if_flags & IFF_RUNNING) {
1071 emx_disable_intr(sc);
1073 #ifdef IFPOLL_ENABLE
1074 if (!(ifp->if_flags & IFF_NPOLLING))
1076 emx_enable_intr(sc);
1081 /* Check SOL/IDER usage */
1082 if (e1000_check_reset_block(&sc->hw)) {
1083 device_printf(sc->dev, "Media change is"
1084 " blocked due to SOL/IDER session.\n");
1090 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
1095 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1096 if (mask & IFCAP_RXCSUM) {
1097 ifp->if_capenable ^= IFCAP_RXCSUM;
1100 if (mask & IFCAP_VLAN_HWTAGGING) {
1101 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1104 if (mask & IFCAP_TXCSUM) {
1105 ifp->if_capenable ^= IFCAP_TXCSUM;
1106 if (ifp->if_capenable & IFCAP_TXCSUM)
1107 ifp->if_hwassist |= EMX_CSUM_FEATURES;
1109 ifp->if_hwassist &= ~EMX_CSUM_FEATURES;
1111 if (mask & IFCAP_TSO) {
1112 ifp->if_capenable ^= IFCAP_TSO;
1113 if (ifp->if_capenable & IFCAP_TSO)
1114 ifp->if_hwassist |= CSUM_TSO;
1116 ifp->if_hwassist &= ~CSUM_TSO;
1118 if (mask & IFCAP_RSS)
1119 ifp->if_capenable ^= IFCAP_RSS;
1120 if (reinit && (ifp->if_flags & IFF_RUNNING))
1125 error = ether_ioctl(ifp, command, data);
1132 emx_watchdog(struct ifaltq_subque *ifsq)
1134 struct emx_txdata *tdata = ifsq_get_priv(ifsq);
1135 struct ifnet *ifp = ifsq_get_ifp(ifsq);
1136 struct emx_softc *sc = ifp->if_softc;
1139 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1142 * The timer is set to 5 every time start queues a packet.
1143 * Then txeof keeps resetting it as long as it cleans at
1144 * least one descriptor.
1145 * Finally, anytime all descriptors are clean the timer is
1149 if (E1000_READ_REG(&sc->hw, E1000_TDT(tdata->idx)) ==
1150 E1000_READ_REG(&sc->hw, E1000_TDH(tdata->idx))) {
1152 * If we reach here, all TX jobs are completed and
1153 * the TX engine should have been idled for some time.
1154 * We don't need to call ifsq_devstart_sched() here.
1156 ifsq_clr_oactive(ifsq);
1157 tdata->tx_watchdog.wd_timer = 0;
1162 * If we are in this routine because of pause frames, then
1163 * don't reset the hardware.
1165 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) {
1166 tdata->tx_watchdog.wd_timer = EMX_TX_TIMEOUT;
1170 if_printf(ifp, "TX %d watchdog timeout -- resetting\n", tdata->idx);
1172 IFNET_STAT_INC(ifp, oerrors, 1);
1175 for (i = 0; i < sc->tx_ring_inuse; ++i)
1176 ifsq_devstart_sched(sc->tx_data[i].ifsq);
1182 struct emx_softc *sc = xsc;
1183 struct ifnet *ifp = &sc->arpcom.ac_if;
1184 device_t dev = sc->dev;
1188 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1192 /* Get the latest mac address, User can use a LAA */
1193 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
1195 /* Put the address into the Receive Address Array */
1196 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1199 * With the 82571 sc, RAR[0] may be overwritten
1200 * when the other port is reset, we make a duplicate
1201 * in RAR[14] for that eventuality, this assures
1202 * the interface continues to function.
1204 if (sc->hw.mac.type == e1000_82571) {
1205 e1000_set_laa_state_82571(&sc->hw, TRUE);
1206 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1207 E1000_RAR_ENTRIES - 1);
1210 /* Initialize the hardware */
1211 if (emx_reset(sc)) {
1212 device_printf(dev, "Unable to reset the hardware\n");
1213 /* XXX emx_stop()? */
1216 emx_update_link_status(sc);
1218 /* Setup VLAN support, basic and offload if available */
1219 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1221 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1224 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
1225 ctrl |= E1000_CTRL_VME;
1226 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
1229 /* Configure for OS presence */
1233 #ifdef IFPOLL_ENABLE
1234 if (ifp->if_flags & IFF_NPOLLING)
1237 sc->tx_ring_inuse = emx_get_txring_inuse(sc, polling);
1238 ifq_set_subq_mask(&ifp->if_snd, sc->tx_ring_inuse - 1);
1240 /* Prepare transmit descriptors and buffers */
1241 for (i = 0; i < sc->tx_ring_inuse; ++i)
1242 emx_init_tx_ring(&sc->tx_data[i]);
1243 emx_init_tx_unit(sc);
1245 /* Setup Multicast table */
1248 /* Prepare receive descriptors and buffers */
1249 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1250 if (emx_init_rx_ring(&sc->rx_data[i])) {
1252 "Could not setup receive structures\n");
1257 emx_init_rx_unit(sc);
1259 /* Don't lose promiscuous settings */
1260 emx_set_promisc(sc);
1262 ifp->if_flags |= IFF_RUNNING;
1263 for (i = 0; i < sc->tx_ring_inuse; ++i) {
1264 ifsq_clr_oactive(sc->tx_data[i].ifsq);
1265 ifsq_watchdog_start(&sc->tx_data[i].tx_watchdog);
1268 callout_reset(&sc->timer, hz, emx_timer, sc);
1269 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1271 /* MSI/X configuration for 82574 */
1272 if (sc->hw.mac.type == e1000_82574) {
1275 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1276 tmp |= E1000_CTRL_EXT_PBA_CLR;
1277 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1280 * Set the IVAR - interrupt vector routing.
1281 * Each nibble represents a vector, high bit
1282 * is enable, other 3 bits are the MSIX table
1283 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1284 * Link (other) to 2, hence the magic number.
1286 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908);
1290 * Only enable interrupts if we are not polling, make sure
1291 * they are off otherwise.
1294 emx_disable_intr(sc);
1296 emx_enable_intr(sc);
1298 /* AMT based hardware can now take control from firmware */
1299 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) ==
1300 (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT))
1301 emx_get_hw_control(sc);
1307 emx_intr_body(xsc, TRUE);
1311 emx_intr_body(struct emx_softc *sc, boolean_t chk_asserted)
1313 struct ifnet *ifp = &sc->arpcom.ac_if;
1317 ASSERT_SERIALIZED(&sc->main_serialize);
1319 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1321 if (chk_asserted && (reg_icr & E1000_ICR_INT_ASSERTED) == 0) {
1327 * XXX: some laptops trigger several spurious interrupts
1328 * on emx(4) when in the resume cycle. The ICR register
1329 * reports all-ones value in this case. Processing such
1330 * interrupts would lead to a freeze. I don't know why.
1332 if (reg_icr == 0xffffffff) {
1337 if (ifp->if_flags & IFF_RUNNING) {
1339 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
1342 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1343 lwkt_serialize_enter(
1344 &sc->rx_data[i].rx_serialize);
1345 emx_rxeof(&sc->rx_data[i], -1);
1346 lwkt_serialize_exit(
1347 &sc->rx_data[i].rx_serialize);
1350 if (reg_icr & E1000_ICR_TXDW) {
1351 struct emx_txdata *tdata = &sc->tx_data[0];
1353 lwkt_serialize_enter(&tdata->tx_serialize);
1355 if (!ifsq_is_empty(tdata->ifsq))
1356 ifsq_devstart(tdata->ifsq);
1357 lwkt_serialize_exit(&tdata->tx_serialize);
1361 /* Link status change */
1362 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1363 emx_serialize_skipmain(sc);
1365 callout_stop(&sc->timer);
1366 sc->hw.mac.get_link_status = 1;
1367 emx_update_link_status(sc);
1369 /* Deal with TX cruft when link lost */
1372 callout_reset(&sc->timer, hz, emx_timer, sc);
1374 emx_deserialize_skipmain(sc);
1377 if (reg_icr & E1000_ICR_RXO)
1384 emx_intr_mask(void *xsc)
1386 struct emx_softc *sc = xsc;
1388 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
1391 * ICR.INT_ASSERTED bit will never be set if IMS is 0,
1392 * so don't check it.
1394 emx_intr_body(sc, FALSE);
1395 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
1399 emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1401 struct emx_softc *sc = ifp->if_softc;
1403 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1405 emx_update_link_status(sc);
1407 ifmr->ifm_status = IFM_AVALID;
1408 ifmr->ifm_active = IFM_ETHER;
1410 if (!sc->link_active)
1413 ifmr->ifm_status |= IFM_ACTIVE;
1415 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1416 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1417 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
1419 switch (sc->link_speed) {
1421 ifmr->ifm_active |= IFM_10_T;
1424 ifmr->ifm_active |= IFM_100_TX;
1428 ifmr->ifm_active |= IFM_1000_T;
1431 if (sc->link_duplex == FULL_DUPLEX)
1432 ifmr->ifm_active |= IFM_FDX;
1434 ifmr->ifm_active |= IFM_HDX;
1439 emx_media_change(struct ifnet *ifp)
1441 struct emx_softc *sc = ifp->if_softc;
1442 struct ifmedia *ifm = &sc->media;
1444 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1446 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1449 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1451 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1452 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
1458 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1459 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1463 sc->hw.mac.autoneg = FALSE;
1464 sc->hw.phy.autoneg_advertised = 0;
1465 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1466 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1468 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1472 sc->hw.mac.autoneg = FALSE;
1473 sc->hw.phy.autoneg_advertised = 0;
1474 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1475 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1477 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1481 if_printf(ifp, "Unsupported media type\n");
1491 emx_encap(struct emx_txdata *tdata, struct mbuf **m_headp,
1492 int *segs_used, int *idx)
1494 bus_dma_segment_t segs[EMX_MAX_SCATTER];
1496 struct emx_txbuf *tx_buffer, *tx_buffer_mapped;
1497 struct e1000_tx_desc *ctxd = NULL;
1498 struct mbuf *m_head = *m_headp;
1499 uint32_t txd_upper, txd_lower, cmd = 0;
1500 int maxsegs, nsegs, i, j, first, last = 0, error;
1502 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1503 error = emx_tso_pullup(tdata, m_headp);
1509 txd_upper = txd_lower = 0;
1512 * Capture the first descriptor index, this descriptor
1513 * will have the index of the EOP which is the only one
1514 * that now gets a DONE bit writeback.
1516 first = tdata->next_avail_tx_desc;
1517 tx_buffer = &tdata->tx_buf[first];
1518 tx_buffer_mapped = tx_buffer;
1519 map = tx_buffer->map;
1521 maxsegs = tdata->num_tx_desc_avail - EMX_TX_RESERVED;
1522 KASSERT(maxsegs >= tdata->spare_tx_desc, ("not enough spare TX desc"));
1523 if (maxsegs > EMX_MAX_SCATTER)
1524 maxsegs = EMX_MAX_SCATTER;
1526 error = bus_dmamap_load_mbuf_defrag(tdata->txtag, map, m_headp,
1527 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1533 bus_dmamap_sync(tdata->txtag, map, BUS_DMASYNC_PREWRITE);
1536 tdata->tx_nsegs += nsegs;
1537 *segs_used += nsegs;
1539 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1540 /* TSO will consume one TX desc */
1541 i = emx_tso_setup(tdata, m_head, &txd_upper, &txd_lower);
1542 tdata->tx_nsegs += i;
1544 } else if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) {
1545 /* TX csum offloading will consume one TX desc */
1546 i = emx_txcsum(tdata, m_head, &txd_upper, &txd_lower);
1547 tdata->tx_nsegs += i;
1550 i = tdata->next_avail_tx_desc;
1552 /* Set up our transmit descriptors */
1553 for (j = 0; j < nsegs; j++) {
1554 tx_buffer = &tdata->tx_buf[i];
1555 ctxd = &tdata->tx_desc_base[i];
1557 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1558 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1559 txd_lower | segs[j].ds_len);
1560 ctxd->upper.data = htole32(txd_upper);
1563 if (++i == tdata->num_tx_desc)
1567 tdata->next_avail_tx_desc = i;
1569 KKASSERT(tdata->num_tx_desc_avail > nsegs);
1570 tdata->num_tx_desc_avail -= nsegs;
1572 /* Handle VLAN tag */
1573 if (m_head->m_flags & M_VLANTAG) {
1574 /* Set the vlan id. */
1575 ctxd->upper.fields.special =
1576 htole16(m_head->m_pkthdr.ether_vlantag);
1578 /* Tell hardware to add tag */
1579 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE);
1582 tx_buffer->m_head = m_head;
1583 tx_buffer_mapped->map = tx_buffer->map;
1584 tx_buffer->map = map;
1586 if (tdata->tx_nsegs >= tdata->tx_intr_nsegs) {
1587 tdata->tx_nsegs = 0;
1590 * Report Status (RS) is turned on
1591 * every tx_intr_nsegs descriptors.
1593 cmd = E1000_TXD_CMD_RS;
1596 * Keep track of the descriptor, which will
1597 * be written back by hardware.
1599 tdata->tx_dd[tdata->tx_dd_tail] = last;
1600 EMX_INC_TXDD_IDX(tdata->tx_dd_tail);
1601 KKASSERT(tdata->tx_dd_tail != tdata->tx_dd_head);
1605 * Last Descriptor of Packet needs End Of Packet (EOP)
1607 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1610 * Defer TDT updating, until enough descriptors are setup
1614 #ifdef EMX_TSS_DEBUG
1622 emx_set_promisc(struct emx_softc *sc)
1624 struct ifnet *ifp = &sc->arpcom.ac_if;
1627 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1629 if (ifp->if_flags & IFF_PROMISC) {
1630 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1631 /* Turn this on if you want to see bad packets */
1633 reg_rctl |= E1000_RCTL_SBP;
1634 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1635 } else if (ifp->if_flags & IFF_ALLMULTI) {
1636 reg_rctl |= E1000_RCTL_MPE;
1637 reg_rctl &= ~E1000_RCTL_UPE;
1638 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1643 emx_disable_promisc(struct emx_softc *sc)
1647 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1649 reg_rctl &= ~E1000_RCTL_UPE;
1650 reg_rctl &= ~E1000_RCTL_MPE;
1651 reg_rctl &= ~E1000_RCTL_SBP;
1652 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1656 emx_set_multi(struct emx_softc *sc)
1658 struct ifnet *ifp = &sc->arpcom.ac_if;
1659 struct ifmultiaddr *ifma;
1660 uint32_t reg_rctl = 0;
1665 bzero(mta, ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX);
1667 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1668 if (ifma->ifma_addr->sa_family != AF_LINK)
1671 if (mcnt == EMX_MCAST_ADDR_MAX)
1674 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1675 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1679 if (mcnt >= EMX_MCAST_ADDR_MAX) {
1680 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1681 reg_rctl |= E1000_RCTL_MPE;
1682 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1684 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1689 * This routine checks for link status and updates statistics.
1692 emx_timer(void *xsc)
1694 struct emx_softc *sc = xsc;
1695 struct ifnet *ifp = &sc->arpcom.ac_if;
1697 lwkt_serialize_enter(&sc->main_serialize);
1699 emx_update_link_status(sc);
1700 emx_update_stats(sc);
1702 /* Reset LAA into RAR[0] on 82571 */
1703 if (e1000_get_laa_state_82571(&sc->hw) == TRUE)
1704 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1706 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
1707 emx_print_hw_stats(sc);
1711 callout_reset(&sc->timer, hz, emx_timer, sc);
1713 lwkt_serialize_exit(&sc->main_serialize);
1717 emx_update_link_status(struct emx_softc *sc)
1719 struct e1000_hw *hw = &sc->hw;
1720 struct ifnet *ifp = &sc->arpcom.ac_if;
1721 device_t dev = sc->dev;
1722 uint32_t link_check = 0;
1724 /* Get the cached link value or read phy for real */
1725 switch (hw->phy.media_type) {
1726 case e1000_media_type_copper:
1727 if (hw->mac.get_link_status) {
1728 /* Do the work to read phy */
1729 e1000_check_for_link(hw);
1730 link_check = !hw->mac.get_link_status;
1731 if (link_check) /* ESB2 fix */
1732 e1000_cfg_on_link_up(hw);
1738 case e1000_media_type_fiber:
1739 e1000_check_for_link(hw);
1740 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1743 case e1000_media_type_internal_serdes:
1744 e1000_check_for_link(hw);
1745 link_check = sc->hw.mac.serdes_has_link;
1748 case e1000_media_type_unknown:
1753 /* Now check for a transition */
1754 if (link_check && sc->link_active == 0) {
1755 e1000_get_speed_and_duplex(hw, &sc->link_speed,
1759 * Check if we should enable/disable SPEED_MODE bit on
1762 if (sc->link_speed != SPEED_1000 &&
1763 (hw->mac.type == e1000_82571 ||
1764 hw->mac.type == e1000_82572)) {
1767 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1768 tarc0 &= ~EMX_TARC_SPEED_MODE;
1769 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1772 device_printf(dev, "Link is up %d Mbps %s\n",
1774 ((sc->link_duplex == FULL_DUPLEX) ?
1775 "Full Duplex" : "Half Duplex"));
1777 sc->link_active = 1;
1779 ifp->if_baudrate = sc->link_speed * 1000000;
1780 ifp->if_link_state = LINK_STATE_UP;
1781 if_link_state_change(ifp);
1782 } else if (!link_check && sc->link_active == 1) {
1783 ifp->if_baudrate = sc->link_speed = 0;
1784 sc->link_duplex = 0;
1786 device_printf(dev, "Link is Down\n");
1787 sc->link_active = 0;
1788 ifp->if_link_state = LINK_STATE_DOWN;
1789 if_link_state_change(ifp);
1794 emx_stop(struct emx_softc *sc)
1796 struct ifnet *ifp = &sc->arpcom.ac_if;
1799 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1801 emx_disable_intr(sc);
1803 callout_stop(&sc->timer);
1805 ifp->if_flags &= ~IFF_RUNNING;
1806 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1807 struct emx_txdata *tdata = &sc->tx_data[i];
1809 ifsq_clr_oactive(tdata->ifsq);
1810 ifsq_watchdog_stop(&tdata->tx_watchdog);
1811 tdata->tx_flags &= ~EMX_TXFLAG_ENABLED;
1815 * Disable multiple receive queues.
1818 * We should disable multiple receive queues before
1819 * resetting the hardware.
1821 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0);
1823 e1000_reset_hw(&sc->hw);
1824 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1826 for (i = 0; i < sc->tx_ring_cnt; ++i)
1827 emx_free_tx_ring(&sc->tx_data[i]);
1828 for (i = 0; i < sc->rx_ring_cnt; ++i)
1829 emx_free_rx_ring(&sc->rx_data[i]);
1833 emx_reset(struct emx_softc *sc)
1835 device_t dev = sc->dev;
1836 uint16_t rx_buffer_size;
1839 /* Set up smart power down as default off on newer adapters. */
1840 if (!emx_smart_pwr_down &&
1841 (sc->hw.mac.type == e1000_82571 ||
1842 sc->hw.mac.type == e1000_82572)) {
1843 uint16_t phy_tmp = 0;
1845 /* Speed up time to link by disabling smart power down. */
1846 e1000_read_phy_reg(&sc->hw,
1847 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1848 phy_tmp &= ~IGP02E1000_PM_SPD;
1849 e1000_write_phy_reg(&sc->hw,
1850 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1854 * Packet Buffer Allocation (PBA)
1855 * Writing PBA sets the receive portion of the buffer
1856 * the remainder is used for the transmit buffer.
1858 switch (sc->hw.mac.type) {
1859 /* Total Packet Buffer on these is 48K */
1862 case e1000_80003es2lan:
1863 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1866 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
1867 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1871 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1875 /* Devices before 82547 had a Packet Buffer of 64K. */
1876 if (sc->max_frame_size > 8192)
1877 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1879 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1881 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba);
1884 * These parameters control the automatic generation (Tx) and
1885 * response (Rx) to Ethernet PAUSE frames.
1886 * - High water mark should allow for at least two frames to be
1887 * received after sending an XOFF.
1888 * - Low water mark works best when it is very near the high water mark.
1889 * This allows the receiver to restart by sending XON when it has
1890 * drained a bit. Here we use an arbitary value of 1500 which will
1891 * restart after one full frame is pulled from the buffer. There
1892 * could be several smaller frames in the buffer and if so they will
1893 * not trigger the XON until their total number reduces the buffer
1895 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1897 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10;
1899 sc->hw.fc.high_water = rx_buffer_size -
1900 roundup2(sc->max_frame_size, 1024);
1901 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500;
1903 if (sc->hw.mac.type == e1000_80003es2lan)
1904 sc->hw.fc.pause_time = 0xFFFF;
1906 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME;
1907 sc->hw.fc.send_xon = TRUE;
1908 sc->hw.fc.requested_mode = e1000_fc_full;
1910 /* Issue a global reset */
1911 e1000_reset_hw(&sc->hw);
1912 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1913 emx_disable_aspm(sc);
1915 if (e1000_init_hw(&sc->hw) < 0) {
1916 device_printf(dev, "Hardware Initialization Failed\n");
1920 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1921 e1000_get_phy_info(&sc->hw);
1922 e1000_check_for_link(&sc->hw);
1928 emx_setup_ifp(struct emx_softc *sc)
1930 struct ifnet *ifp = &sc->arpcom.ac_if;
1933 if_initname(ifp, device_get_name(sc->dev),
1934 device_get_unit(sc->dev));
1936 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1937 ifp->if_init = emx_init;
1938 ifp->if_ioctl = emx_ioctl;
1939 ifp->if_start = emx_start;
1940 #ifdef IFPOLL_ENABLE
1941 ifp->if_npoll = emx_npoll;
1943 ifp->if_serialize = emx_serialize;
1944 ifp->if_deserialize = emx_deserialize;
1945 ifp->if_tryserialize = emx_tryserialize;
1947 ifp->if_serialize_assert = emx_serialize_assert;
1950 ifq_set_maxlen(&ifp->if_snd, sc->tx_data[0].num_tx_desc - 1);
1951 ifq_set_ready(&ifp->if_snd);
1952 ifq_set_subq_cnt(&ifp->if_snd, sc->tx_ring_cnt);
1954 ifp->if_mapsubq = ifq_mapsubq_mask;
1955 ifq_set_subq_mask(&ifp->if_snd, 0);
1957 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1959 ifp->if_capabilities = IFCAP_HWCSUM |
1960 IFCAP_VLAN_HWTAGGING |
1963 if (sc->rx_ring_cnt > 1)
1964 ifp->if_capabilities |= IFCAP_RSS;
1965 ifp->if_capenable = ifp->if_capabilities;
1966 ifp->if_hwassist = EMX_CSUM_FEATURES | CSUM_TSO;
1969 * Tell the upper layer(s) we support long frames.
1971 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1973 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1974 struct ifaltq_subque *ifsq = ifq_get_subq(&ifp->if_snd, i);
1975 struct emx_txdata *tdata = &sc->tx_data[i];
1977 ifsq_set_cpuid(ifsq, rman_get_cpuid(sc->intr_res));
1978 ifsq_set_priv(ifsq, tdata);
1979 ifsq_set_hw_serialize(ifsq, &tdata->tx_serialize);
1982 ifsq_watchdog_init(&tdata->tx_watchdog, ifsq, emx_watchdog);
1986 * Specify the media types supported by this sc and register
1987 * callbacks to update media and link information
1989 ifmedia_init(&sc->media, IFM_IMASK,
1990 emx_media_change, emx_media_status);
1991 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1992 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1993 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1995 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1997 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1998 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
2000 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
2001 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
2003 if (sc->hw.phy.type != e1000_phy_ife) {
2004 ifmedia_add(&sc->media,
2005 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2006 ifmedia_add(&sc->media,
2007 IFM_ETHER | IFM_1000_T, 0, NULL);
2010 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2011 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
2015 * Workaround for SmartSpeed on 82541 and 82547 controllers
2018 emx_smartspeed(struct emx_softc *sc)
2022 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp ||
2023 sc->hw.mac.autoneg == 0 ||
2024 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2027 if (sc->smartspeed == 0) {
2029 * If Master/Slave config fault is asserted twice,
2030 * we assume back-to-back
2032 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
2033 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2035 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
2036 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2037 e1000_read_phy_reg(&sc->hw,
2038 PHY_1000T_CTRL, &phy_tmp);
2039 if (phy_tmp & CR_1000T_MS_ENABLE) {
2040 phy_tmp &= ~CR_1000T_MS_ENABLE;
2041 e1000_write_phy_reg(&sc->hw,
2042 PHY_1000T_CTRL, phy_tmp);
2044 if (sc->hw.mac.autoneg &&
2045 !e1000_phy_setup_autoneg(&sc->hw) &&
2046 !e1000_read_phy_reg(&sc->hw,
2047 PHY_CONTROL, &phy_tmp)) {
2048 phy_tmp |= MII_CR_AUTO_NEG_EN |
2049 MII_CR_RESTART_AUTO_NEG;
2050 e1000_write_phy_reg(&sc->hw,
2051 PHY_CONTROL, phy_tmp);
2056 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) {
2057 /* If still no link, perhaps using 2/3 pair cable */
2058 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
2059 phy_tmp |= CR_1000T_MS_ENABLE;
2060 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
2061 if (sc->hw.mac.autoneg &&
2062 !e1000_phy_setup_autoneg(&sc->hw) &&
2063 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
2064 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2065 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
2069 /* Restart process after EMX_SMARTSPEED_MAX iterations */
2070 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX)
2075 emx_create_tx_ring(struct emx_txdata *tdata)
2077 device_t dev = tdata->sc->dev;
2078 struct emx_txbuf *tx_buffer;
2079 int error, i, tsize, ntxd;
2082 * Validate number of transmit descriptors. It must not exceed
2083 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2085 ntxd = device_getenv_int(dev, "txd", emx_txd);
2086 if ((ntxd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 ||
2087 ntxd > EMX_MAX_TXD || ntxd < EMX_MIN_TXD) {
2088 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
2089 EMX_DEFAULT_TXD, ntxd);
2090 tdata->num_tx_desc = EMX_DEFAULT_TXD;
2092 tdata->num_tx_desc = ntxd;
2096 * Allocate Transmit Descriptor ring
2098 tsize = roundup2(tdata->num_tx_desc * sizeof(struct e1000_tx_desc),
2100 tdata->tx_desc_base = bus_dmamem_coherent_any(tdata->sc->parent_dtag,
2101 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
2102 &tdata->tx_desc_dtag, &tdata->tx_desc_dmap,
2103 &tdata->tx_desc_paddr);
2104 if (tdata->tx_desc_base == NULL) {
2105 device_printf(dev, "Unable to allocate tx_desc memory\n");
2109 tsize = __VM_CACHELINE_ALIGN(
2110 sizeof(struct emx_txbuf) * tdata->num_tx_desc);
2111 tdata->tx_buf = kmalloc_cachealign(tsize, M_DEVBUF, M_WAITOK | M_ZERO);
2114 * Create DMA tags for tx buffers
2116 error = bus_dma_tag_create(tdata->sc->parent_dtag, /* parent */
2117 1, 0, /* alignment, bounds */
2118 BUS_SPACE_MAXADDR, /* lowaddr */
2119 BUS_SPACE_MAXADDR, /* highaddr */
2120 NULL, NULL, /* filter, filterarg */
2121 EMX_TSO_SIZE, /* maxsize */
2122 EMX_MAX_SCATTER, /* nsegments */
2123 EMX_MAX_SEGSIZE, /* maxsegsize */
2124 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
2125 BUS_DMA_ONEBPAGE, /* flags */
2128 device_printf(dev, "Unable to allocate TX DMA tag\n");
2129 kfree(tdata->tx_buf, M_DEVBUF);
2130 tdata->tx_buf = NULL;
2135 * Create DMA maps for tx buffers
2137 for (i = 0; i < tdata->num_tx_desc; i++) {
2138 tx_buffer = &tdata->tx_buf[i];
2140 error = bus_dmamap_create(tdata->txtag,
2141 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2144 device_printf(dev, "Unable to create TX DMA map\n");
2145 emx_destroy_tx_ring(tdata, i);
2151 * Setup TX parameters
2153 tdata->spare_tx_desc = EMX_TX_SPARE;
2154 tdata->tx_wreg_nsegs = EMX_DEFAULT_TXWREG;
2157 * Keep following relationship between spare_tx_desc, oact_tx_desc
2158 * and tx_intr_nsegs:
2159 * (spare_tx_desc + EMX_TX_RESERVED) <=
2160 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_intr_nsegs
2162 tdata->oact_tx_desc = tdata->num_tx_desc / 8;
2163 if (tdata->oact_tx_desc > EMX_TX_OACTIVE_MAX)
2164 tdata->oact_tx_desc = EMX_TX_OACTIVE_MAX;
2165 if (tdata->oact_tx_desc < tdata->spare_tx_desc + EMX_TX_RESERVED)
2166 tdata->oact_tx_desc = tdata->spare_tx_desc + EMX_TX_RESERVED;
2168 tdata->tx_intr_nsegs = tdata->num_tx_desc / 16;
2169 if (tdata->tx_intr_nsegs < tdata->oact_tx_desc)
2170 tdata->tx_intr_nsegs = tdata->oact_tx_desc;
2173 * Pullup extra 4bytes into the first data segment, see:
2174 * 82571/82572 specification update errata #7
2177 * 4bytes instead of 2bytes, which are mentioned in the errata,
2178 * are pulled; mainly to keep rest of the data properly aligned.
2180 if (tdata->sc->hw.mac.type == e1000_82571 ||
2181 tdata->sc->hw.mac.type == e1000_82572)
2182 tdata->tx_flags |= EMX_TXFLAG_TSO_PULLEX;
2188 emx_init_tx_ring(struct emx_txdata *tdata)
2190 /* Clear the old ring contents */
2191 bzero(tdata->tx_desc_base,
2192 sizeof(struct e1000_tx_desc) * tdata->num_tx_desc);
2195 tdata->next_avail_tx_desc = 0;
2196 tdata->next_tx_to_clean = 0;
2197 tdata->num_tx_desc_avail = tdata->num_tx_desc;
2199 tdata->tx_flags |= EMX_TXFLAG_ENABLED;
2200 if (tdata->sc->tx_ring_inuse > 1) {
2201 tdata->tx_flags |= EMX_TXFLAG_FORCECTX;
2203 if_printf(&tdata->sc->arpcom.ac_if,
2204 "TX %d force ctx setup\n", tdata->idx);
2210 emx_init_tx_unit(struct emx_softc *sc)
2212 uint32_t tctl, tarc, tipg = 0;
2215 for (i = 0; i < sc->tx_ring_inuse; ++i) {
2216 struct emx_txdata *tdata = &sc->tx_data[i];
2219 /* Setup the Base and Length of the Tx Descriptor Ring */
2220 bus_addr = tdata->tx_desc_paddr;
2221 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(i),
2222 tdata->num_tx_desc * sizeof(struct e1000_tx_desc));
2223 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(i),
2224 (uint32_t)(bus_addr >> 32));
2225 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(i),
2226 (uint32_t)bus_addr);
2227 /* Setup the HW Tx Head and Tail descriptor pointers */
2228 E1000_WRITE_REG(&sc->hw, E1000_TDT(i), 0);
2229 E1000_WRITE_REG(&sc->hw, E1000_TDH(i), 0);
2232 /* Set the default values for the Tx Inter Packet Gap timer */
2233 switch (sc->hw.mac.type) {
2234 case e1000_80003es2lan:
2235 tipg = DEFAULT_82543_TIPG_IPGR1;
2236 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2237 E1000_TIPG_IPGR2_SHIFT;
2241 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2242 sc->hw.phy.media_type == e1000_media_type_internal_serdes)
2243 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2245 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2246 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2247 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2251 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg);
2253 /* NOTE: 0 is not allowed for TIDV */
2254 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1);
2255 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0);
2257 if (sc->hw.mac.type == e1000_82571 ||
2258 sc->hw.mac.type == e1000_82572) {
2259 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2260 tarc |= EMX_TARC_SPEED_MODE;
2261 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2262 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2263 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2265 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2266 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2268 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2271 /* Program the Transmit Control Register */
2272 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL);
2273 tctl &= ~E1000_TCTL_CT;
2274 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2275 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2276 tctl |= E1000_TCTL_MULR;
2278 /* This write will effectively turn on the transmit unit. */
2279 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl);
2281 if (sc->hw.mac.type == e1000_82571 ||
2282 sc->hw.mac.type == e1000_82572 ||
2283 sc->hw.mac.type == e1000_80003es2lan) {
2284 /* Bit 28 of TARC1 must be cleared when MULR is enabled */
2285 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2287 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2290 if (sc->tx_ring_inuse > 1) {
2291 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2292 tarc &= ~EMX_TARC_COUNT_MASK;
2294 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2296 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2297 tarc &= ~EMX_TARC_COUNT_MASK;
2299 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2304 emx_destroy_tx_ring(struct emx_txdata *tdata, int ndesc)
2306 struct emx_txbuf *tx_buffer;
2309 /* Free Transmit Descriptor ring */
2310 if (tdata->tx_desc_base) {
2311 bus_dmamap_unload(tdata->tx_desc_dtag, tdata->tx_desc_dmap);
2312 bus_dmamem_free(tdata->tx_desc_dtag, tdata->tx_desc_base,
2313 tdata->tx_desc_dmap);
2314 bus_dma_tag_destroy(tdata->tx_desc_dtag);
2316 tdata->tx_desc_base = NULL;
2319 if (tdata->tx_buf == NULL)
2322 for (i = 0; i < ndesc; i++) {
2323 tx_buffer = &tdata->tx_buf[i];
2325 KKASSERT(tx_buffer->m_head == NULL);
2326 bus_dmamap_destroy(tdata->txtag, tx_buffer->map);
2328 bus_dma_tag_destroy(tdata->txtag);
2330 kfree(tdata->tx_buf, M_DEVBUF);
2331 tdata->tx_buf = NULL;
2335 * The offload context needs to be set when we transfer the first
2336 * packet of a particular protocol (TCP/UDP). This routine has been
2337 * enhanced to deal with inserted VLAN headers.
2339 * If the new packet's ether header length, ip header length and
2340 * csum offloading type are same as the previous packet, we should
2341 * avoid allocating a new csum context descriptor; mainly to take
2342 * advantage of the pipeline effect of the TX data read request.
2344 * This function returns number of TX descrptors allocated for
2348 emx_txcsum(struct emx_txdata *tdata, struct mbuf *mp,
2349 uint32_t *txd_upper, uint32_t *txd_lower)
2351 struct e1000_context_desc *TXD;
2352 int curr_txd, ehdrlen, csum_flags;
2353 uint32_t cmd, hdr_len, ip_hlen;
2355 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES;
2356 ip_hlen = mp->m_pkthdr.csum_iphlen;
2357 ehdrlen = mp->m_pkthdr.csum_lhlen;
2359 if ((tdata->tx_flags & EMX_TXFLAG_FORCECTX) == 0 &&
2360 tdata->csum_lhlen == ehdrlen && tdata->csum_iphlen == ip_hlen &&
2361 tdata->csum_flags == csum_flags) {
2363 * Same csum offload context as the previous packets;
2366 *txd_upper = tdata->csum_txd_upper;
2367 *txd_lower = tdata->csum_txd_lower;
2372 * Setup a new csum offload context.
2375 curr_txd = tdata->next_avail_tx_desc;
2376 TXD = (struct e1000_context_desc *)&tdata->tx_desc_base[curr_txd];
2380 /* Setup of IP header checksum. */
2381 if (csum_flags & CSUM_IP) {
2383 * Start offset for header checksum calculation.
2384 * End offset for header checksum calculation.
2385 * Offset of place to put the checksum.
2387 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2388 TXD->lower_setup.ip_fields.ipcse =
2389 htole16(ehdrlen + ip_hlen - 1);
2390 TXD->lower_setup.ip_fields.ipcso =
2391 ehdrlen + offsetof(struct ip, ip_sum);
2392 cmd |= E1000_TXD_CMD_IP;
2393 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2395 hdr_len = ehdrlen + ip_hlen;
2397 if (csum_flags & CSUM_TCP) {
2399 * Start offset for payload checksum calculation.
2400 * End offset for payload checksum calculation.
2401 * Offset of place to put the checksum.
2403 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2404 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2405 TXD->upper_setup.tcp_fields.tucso =
2406 hdr_len + offsetof(struct tcphdr, th_sum);
2407 cmd |= E1000_TXD_CMD_TCP;
2408 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2409 } else if (csum_flags & CSUM_UDP) {
2411 * Start offset for header checksum calculation.
2412 * End offset for header checksum calculation.
2413 * Offset of place to put the checksum.
2415 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2416 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2417 TXD->upper_setup.tcp_fields.tucso =
2418 hdr_len + offsetof(struct udphdr, uh_sum);
2419 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2422 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2423 E1000_TXD_DTYP_D; /* Data descr */
2425 /* Save the information for this csum offloading context */
2426 tdata->csum_lhlen = ehdrlen;
2427 tdata->csum_iphlen = ip_hlen;
2428 tdata->csum_flags = csum_flags;
2429 tdata->csum_txd_upper = *txd_upper;
2430 tdata->csum_txd_lower = *txd_lower;
2432 TXD->tcp_seg_setup.data = htole32(0);
2433 TXD->cmd_and_length =
2434 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
2436 if (++curr_txd == tdata->num_tx_desc)
2439 KKASSERT(tdata->num_tx_desc_avail > 0);
2440 tdata->num_tx_desc_avail--;
2442 tdata->next_avail_tx_desc = curr_txd;
2447 emx_txeof(struct emx_txdata *tdata)
2449 struct ifnet *ifp = &tdata->sc->arpcom.ac_if;
2450 struct emx_txbuf *tx_buffer;
2451 int first, num_avail;
2453 if (tdata->tx_dd_head == tdata->tx_dd_tail)
2456 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2459 num_avail = tdata->num_tx_desc_avail;
2460 first = tdata->next_tx_to_clean;
2462 while (tdata->tx_dd_head != tdata->tx_dd_tail) {
2463 int dd_idx = tdata->tx_dd[tdata->tx_dd_head];
2464 struct e1000_tx_desc *tx_desc;
2466 tx_desc = &tdata->tx_desc_base[dd_idx];
2467 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2468 EMX_INC_TXDD_IDX(tdata->tx_dd_head);
2470 if (++dd_idx == tdata->num_tx_desc)
2473 while (first != dd_idx) {
2478 tx_buffer = &tdata->tx_buf[first];
2479 if (tx_buffer->m_head) {
2480 IFNET_STAT_INC(ifp, opackets, 1);
2481 bus_dmamap_unload(tdata->txtag,
2483 m_freem(tx_buffer->m_head);
2484 tx_buffer->m_head = NULL;
2487 if (++first == tdata->num_tx_desc)
2494 tdata->next_tx_to_clean = first;
2495 tdata->num_tx_desc_avail = num_avail;
2497 if (tdata->tx_dd_head == tdata->tx_dd_tail) {
2498 tdata->tx_dd_head = 0;
2499 tdata->tx_dd_tail = 0;
2502 if (!EMX_IS_OACTIVE(tdata)) {
2503 ifsq_clr_oactive(tdata->ifsq);
2505 /* All clean, turn off the timer */
2506 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2507 tdata->tx_watchdog.wd_timer = 0;
2512 emx_tx_collect(struct emx_txdata *tdata)
2514 struct ifnet *ifp = &tdata->sc->arpcom.ac_if;
2515 struct emx_txbuf *tx_buffer;
2516 int tdh, first, num_avail, dd_idx = -1;
2518 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2521 tdh = E1000_READ_REG(&tdata->sc->hw, E1000_TDH(tdata->idx));
2522 if (tdh == tdata->next_tx_to_clean)
2525 if (tdata->tx_dd_head != tdata->tx_dd_tail)
2526 dd_idx = tdata->tx_dd[tdata->tx_dd_head];
2528 num_avail = tdata->num_tx_desc_avail;
2529 first = tdata->next_tx_to_clean;
2531 while (first != tdh) {
2536 tx_buffer = &tdata->tx_buf[first];
2537 if (tx_buffer->m_head) {
2538 IFNET_STAT_INC(ifp, opackets, 1);
2539 bus_dmamap_unload(tdata->txtag,
2541 m_freem(tx_buffer->m_head);
2542 tx_buffer->m_head = NULL;
2545 if (first == dd_idx) {
2546 EMX_INC_TXDD_IDX(tdata->tx_dd_head);
2547 if (tdata->tx_dd_head == tdata->tx_dd_tail) {
2548 tdata->tx_dd_head = 0;
2549 tdata->tx_dd_tail = 0;
2552 dd_idx = tdata->tx_dd[tdata->tx_dd_head];
2556 if (++first == tdata->num_tx_desc)
2559 tdata->next_tx_to_clean = first;
2560 tdata->num_tx_desc_avail = num_avail;
2562 if (!EMX_IS_OACTIVE(tdata)) {
2563 ifsq_clr_oactive(tdata->ifsq);
2565 /* All clean, turn off the timer */
2566 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2567 tdata->tx_watchdog.wd_timer = 0;
2572 * When Link is lost sometimes there is work still in the TX ring
2573 * which will result in a watchdog, rather than allow that do an
2574 * attempted cleanup and then reinit here. Note that this has been
2575 * seens mostly with fiber adapters.
2578 emx_tx_purge(struct emx_softc *sc)
2582 if (sc->link_active)
2585 for (i = 0; i < sc->tx_ring_inuse; ++i) {
2586 struct emx_txdata *tdata = &sc->tx_data[i];
2588 if (tdata->tx_watchdog.wd_timer) {
2589 emx_tx_collect(tdata);
2590 if (tdata->tx_watchdog.wd_timer) {
2591 if_printf(&sc->arpcom.ac_if,
2592 "Link lost, TX pending, reinit\n");
2601 emx_newbuf(struct emx_rxdata *rdata, int i, int init)
2604 bus_dma_segment_t seg;
2606 struct emx_rxbuf *rx_buffer;
2609 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2612 if_printf(&rdata->sc->arpcom.ac_if,
2613 "Unable to allocate RX mbuf\n");
2617 m->m_len = m->m_pkthdr.len = MCLBYTES;
2619 if (rdata->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2620 m_adj(m, ETHER_ALIGN);
2622 error = bus_dmamap_load_mbuf_segment(rdata->rxtag,
2623 rdata->rx_sparemap, m,
2624 &seg, 1, &nseg, BUS_DMA_NOWAIT);
2628 if_printf(&rdata->sc->arpcom.ac_if,
2629 "Unable to load RX mbuf\n");
2634 rx_buffer = &rdata->rx_buf[i];
2635 if (rx_buffer->m_head != NULL)
2636 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2638 map = rx_buffer->map;
2639 rx_buffer->map = rdata->rx_sparemap;
2640 rdata->rx_sparemap = map;
2642 rx_buffer->m_head = m;
2643 rx_buffer->paddr = seg.ds_addr;
2645 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer);
2650 emx_create_rx_ring(struct emx_rxdata *rdata)
2652 device_t dev = rdata->sc->dev;
2653 struct emx_rxbuf *rx_buffer;
2654 int i, error, rsize, nrxd;
2657 * Validate number of receive descriptors. It must not exceed
2658 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2660 nrxd = device_getenv_int(dev, "rxd", emx_rxd);
2661 if ((nrxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 ||
2662 nrxd > EMX_MAX_RXD || nrxd < EMX_MIN_RXD) {
2663 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
2664 EMX_DEFAULT_RXD, nrxd);
2665 rdata->num_rx_desc = EMX_DEFAULT_RXD;
2667 rdata->num_rx_desc = nrxd;
2671 * Allocate Receive Descriptor ring
2673 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t),
2675 rdata->rx_desc = bus_dmamem_coherent_any(rdata->sc->parent_dtag,
2676 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2677 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap,
2678 &rdata->rx_desc_paddr);
2679 if (rdata->rx_desc == NULL) {
2680 device_printf(dev, "Unable to allocate rx_desc memory\n");
2684 rsize = __VM_CACHELINE_ALIGN(
2685 sizeof(struct emx_rxbuf) * rdata->num_rx_desc);
2686 rdata->rx_buf = kmalloc_cachealign(rsize, M_DEVBUF, M_WAITOK | M_ZERO);
2689 * Create DMA tag for rx buffers
2691 error = bus_dma_tag_create(rdata->sc->parent_dtag, /* parent */
2692 1, 0, /* alignment, bounds */
2693 BUS_SPACE_MAXADDR, /* lowaddr */
2694 BUS_SPACE_MAXADDR, /* highaddr */
2695 NULL, NULL, /* filter, filterarg */
2696 MCLBYTES, /* maxsize */
2698 MCLBYTES, /* maxsegsize */
2699 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2702 device_printf(dev, "Unable to allocate RX DMA tag\n");
2703 kfree(rdata->rx_buf, M_DEVBUF);
2704 rdata->rx_buf = NULL;
2709 * Create spare DMA map for rx buffers
2711 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2712 &rdata->rx_sparemap);
2714 device_printf(dev, "Unable to create spare RX DMA map\n");
2715 bus_dma_tag_destroy(rdata->rxtag);
2716 kfree(rdata->rx_buf, M_DEVBUF);
2717 rdata->rx_buf = NULL;
2722 * Create DMA maps for rx buffers
2724 for (i = 0; i < rdata->num_rx_desc; i++) {
2725 rx_buffer = &rdata->rx_buf[i];
2727 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2730 device_printf(dev, "Unable to create RX DMA map\n");
2731 emx_destroy_rx_ring(rdata, i);
2739 emx_free_rx_ring(struct emx_rxdata *rdata)
2743 for (i = 0; i < rdata->num_rx_desc; i++) {
2744 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i];
2746 if (rx_buffer->m_head != NULL) {
2747 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2748 m_freem(rx_buffer->m_head);
2749 rx_buffer->m_head = NULL;
2753 if (rdata->fmp != NULL)
2754 m_freem(rdata->fmp);
2760 emx_free_tx_ring(struct emx_txdata *tdata)
2764 for (i = 0; i < tdata->num_tx_desc; i++) {
2765 struct emx_txbuf *tx_buffer = &tdata->tx_buf[i];
2767 if (tx_buffer->m_head != NULL) {
2768 bus_dmamap_unload(tdata->txtag, tx_buffer->map);
2769 m_freem(tx_buffer->m_head);
2770 tx_buffer->m_head = NULL;
2774 tdata->tx_flags &= ~EMX_TXFLAG_FORCECTX;
2776 tdata->csum_flags = 0;
2777 tdata->csum_lhlen = 0;
2778 tdata->csum_iphlen = 0;
2779 tdata->csum_thlen = 0;
2780 tdata->csum_mss = 0;
2781 tdata->csum_pktlen = 0;
2783 tdata->tx_dd_head = 0;
2784 tdata->tx_dd_tail = 0;
2785 tdata->tx_nsegs = 0;
2789 emx_init_rx_ring(struct emx_rxdata *rdata)
2793 /* Reset descriptor ring */
2794 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc);
2796 /* Allocate new ones. */
2797 for (i = 0; i < rdata->num_rx_desc; i++) {
2798 error = emx_newbuf(rdata, i, 1);
2803 /* Setup our descriptor pointers */
2804 rdata->next_rx_desc_to_check = 0;
2810 emx_init_rx_unit(struct emx_softc *sc)
2812 struct ifnet *ifp = &sc->arpcom.ac_if;
2814 uint32_t rctl, itr, rfctl;
2818 * Make sure receives are disabled while setting
2819 * up the descriptor ring
2821 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2822 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2825 * Set the interrupt throttling rate. Value is calculated
2826 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
2828 if (sc->int_throttle_ceil)
2829 itr = 1000000000 / 256 / sc->int_throttle_ceil;
2832 emx_set_itr(sc, itr);
2834 /* Use extended RX descriptor */
2835 rfctl = E1000_RFCTL_EXTEN;
2837 /* Disable accelerated ackknowledge */
2838 if (sc->hw.mac.type == e1000_82574)
2839 rfctl |= E1000_RFCTL_ACK_DIS;
2841 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl);
2844 * Receive Checksum Offload for TCP and UDP
2846 * Checksum offloading is also enabled if multiple receive
2847 * queue is to be supported, since we need it to figure out
2850 if ((ifp->if_capenable & IFCAP_RXCSUM) ||
2851 sc->rx_ring_cnt > 1) {
2854 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2858 * PCSD must be enabled to enable multiple
2861 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2863 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2867 * Configure multiple receive queue (RSS)
2869 if (sc->rx_ring_cnt > 1) {
2870 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE];
2873 KASSERT(sc->rx_ring_cnt == EMX_NRX_RING,
2874 ("invalid number of RX ring (%d)", sc->rx_ring_cnt));
2878 * When we reach here, RSS has already been disabled
2879 * in emx_stop(), so we could safely configure RSS key
2880 * and redirect table.
2886 toeplitz_get_key(key, sizeof(key));
2887 for (i = 0; i < EMX_NRSSRK; ++i) {
2890 rssrk = EMX_RSSRK_VAL(key, i);
2891 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2893 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk);
2897 * Configure RSS redirect table in following fashion:
2898 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2901 for (i = 0; i < EMX_RETA_SIZE; ++i) {
2904 q = (i % sc->rx_ring_cnt) << EMX_RETA_RINGIDX_SHIFT;
2905 reta |= q << (8 * i);
2907 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2909 for (i = 0; i < EMX_NRETA; ++i)
2910 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta);
2913 * Enable multiple receive queues.
2914 * Enable IPv4 RSS standard hash functions.
2915 * Disable RSS interrupt.
2917 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2918 E1000_MRQC_ENABLE_RSS_2Q |
2919 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2920 E1000_MRQC_RSS_FIELD_IPV4);
2924 * XXX TEMPORARY WORKAROUND: on some systems with 82573
2925 * long latencies are observed, like Lenovo X60. This
2926 * change eliminates the problem, but since having positive
2927 * values in RDTR is a known source of problems on other
2928 * platforms another solution is being sought.
2930 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) {
2931 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573);
2932 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573);
2935 for (i = 0; i < sc->rx_ring_cnt; ++i) {
2936 struct emx_rxdata *rdata = &sc->rx_data[i];
2939 * Setup the Base and Length of the Rx Descriptor Ring
2941 bus_addr = rdata->rx_desc_paddr;
2942 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i),
2943 rdata->num_rx_desc * sizeof(emx_rxdesc_t));
2944 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i),
2945 (uint32_t)(bus_addr >> 32));
2946 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i),
2947 (uint32_t)bus_addr);
2950 * Setup the HW Rx Head and Tail Descriptor Pointers
2952 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0);
2953 E1000_WRITE_REG(&sc->hw, E1000_RDT(i),
2954 sc->rx_data[i].num_rx_desc - 1);
2957 /* Setup the Receive Control Register */
2958 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2959 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2960 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC |
2961 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2963 /* Make sure VLAN Filters are off */
2964 rctl &= ~E1000_RCTL_VFE;
2966 /* Don't store bad paket */
2967 rctl &= ~E1000_RCTL_SBP;
2970 rctl |= E1000_RCTL_SZ_2048;
2972 if (ifp->if_mtu > ETHERMTU)
2973 rctl |= E1000_RCTL_LPE;
2975 rctl &= ~E1000_RCTL_LPE;
2977 /* Enable Receives */
2978 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
2982 emx_destroy_rx_ring(struct emx_rxdata *rdata, int ndesc)
2984 struct emx_rxbuf *rx_buffer;
2987 /* Free Receive Descriptor ring */
2988 if (rdata->rx_desc) {
2989 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap);
2990 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc,
2991 rdata->rx_desc_dmap);
2992 bus_dma_tag_destroy(rdata->rx_desc_dtag);
2994 rdata->rx_desc = NULL;
2997 if (rdata->rx_buf == NULL)
3000 for (i = 0; i < ndesc; i++) {
3001 rx_buffer = &rdata->rx_buf[i];
3003 KKASSERT(rx_buffer->m_head == NULL);
3004 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map);
3006 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap);
3007 bus_dma_tag_destroy(rdata->rxtag);
3009 kfree(rdata->rx_buf, M_DEVBUF);
3010 rdata->rx_buf = NULL;
3014 emx_rxeof(struct emx_rxdata *rdata, int count)
3016 struct ifnet *ifp = &rdata->sc->arpcom.ac_if;
3018 emx_rxdesc_t *current_desc;
3022 i = rdata->next_rx_desc_to_check;
3023 current_desc = &rdata->rx_desc[i];
3024 staterr = le32toh(current_desc->rxd_staterr);
3026 if (!(staterr & E1000_RXD_STAT_DD))
3029 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
3030 struct pktinfo *pi = NULL, pi0;
3031 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i];
3032 struct mbuf *m = NULL;
3037 mp = rx_buf->m_head;
3040 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
3041 * needs to access the last received byte in the mbuf.
3043 bus_dmamap_sync(rdata->rxtag, rx_buf->map,
3044 BUS_DMASYNC_POSTREAD);
3046 len = le16toh(current_desc->rxd_length);
3047 if (staterr & E1000_RXD_STAT_EOP) {
3054 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
3056 uint32_t mrq, rss_hash;
3059 * Save several necessary information,
3060 * before emx_newbuf() destroy it.
3062 if ((staterr & E1000_RXD_STAT_VP) && eop)
3063 vlan = le16toh(current_desc->rxd_vlan);
3065 mrq = le32toh(current_desc->rxd_mrq);
3066 rss_hash = le32toh(current_desc->rxd_rss);
3068 EMX_RSS_DPRINTF(rdata->sc, 10,
3069 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n",
3070 rdata->idx, mrq, rss_hash);
3072 if (emx_newbuf(rdata, i, 0) != 0) {
3073 IFNET_STAT_INC(ifp, iqdrops, 1);
3077 /* Assign correct length to the current fragment */
3080 if (rdata->fmp == NULL) {
3081 mp->m_pkthdr.len = len;
3082 rdata->fmp = mp; /* Store the first mbuf */
3086 * Chain mbuf's together
3088 rdata->lmp->m_next = mp;
3089 rdata->lmp = rdata->lmp->m_next;
3090 rdata->fmp->m_pkthdr.len += len;
3094 rdata->fmp->m_pkthdr.rcvif = ifp;
3095 IFNET_STAT_INC(ifp, ipackets, 1);
3097 if (ifp->if_capenable & IFCAP_RXCSUM)
3098 emx_rxcsum(staterr, rdata->fmp);
3100 if (staterr & E1000_RXD_STAT_VP) {
3101 rdata->fmp->m_pkthdr.ether_vlantag =
3103 rdata->fmp->m_flags |= M_VLANTAG;
3109 if (ifp->if_capenable & IFCAP_RSS) {
3110 pi = emx_rssinfo(m, &pi0, mrq,
3113 #ifdef EMX_RSS_DEBUG
3118 IFNET_STAT_INC(ifp, ierrors, 1);
3120 emx_setup_rxdesc(current_desc, rx_buf);
3121 if (rdata->fmp != NULL) {
3122 m_freem(rdata->fmp);
3130 ether_input_pkt(ifp, m, pi);
3132 /* Advance our pointers to the next descriptor. */
3133 if (++i == rdata->num_rx_desc)
3136 current_desc = &rdata->rx_desc[i];
3137 staterr = le32toh(current_desc->rxd_staterr);
3139 rdata->next_rx_desc_to_check = i;
3141 /* Advance the E1000's Receive Queue "Tail Pointer". */
3143 i = rdata->num_rx_desc - 1;
3144 E1000_WRITE_REG(&rdata->sc->hw, E1000_RDT(rdata->idx), i);
3148 emx_enable_intr(struct emx_softc *sc)
3150 uint32_t ims_mask = IMS_ENABLE_MASK;
3152 lwkt_serialize_handler_enable(&sc->main_serialize);
3155 if (sc->hw.mac.type == e1000_82574) {
3156 E1000_WRITE_REG(hw, EMX_EIAC, EM_MSIX_MASK);
3157 ims_mask |= EM_MSIX_MASK;
3160 E1000_WRITE_REG(&sc->hw, E1000_IMS, ims_mask);
3164 emx_disable_intr(struct emx_softc *sc)
3166 if (sc->hw.mac.type == e1000_82574)
3167 E1000_WRITE_REG(&sc->hw, EMX_EIAC, 0);
3168 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
3170 lwkt_serialize_handler_disable(&sc->main_serialize);
3174 * Bit of a misnomer, what this really means is
3175 * to enable OS management of the system... aka
3176 * to disable special hardware management features
3179 emx_get_mgmt(struct emx_softc *sc)
3181 /* A shared code workaround */
3182 if (sc->flags & EMX_FLAG_HAS_MGMT) {
3183 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
3184 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3186 /* disable hardware interception of ARP */
3187 manc &= ~(E1000_MANC_ARP_EN);
3189 /* enable receiving management packets to the host */
3190 manc |= E1000_MANC_EN_MNG2HOST;
3191 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3192 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3193 manc2h |= E1000_MNG2HOST_PORT_623;
3194 manc2h |= E1000_MNG2HOST_PORT_664;
3195 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
3197 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3202 * Give control back to hardware management
3203 * controller if there is one.
3206 emx_rel_mgmt(struct emx_softc *sc)
3208 if (sc->flags & EMX_FLAG_HAS_MGMT) {
3209 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3211 /* re-enable hardware interception of ARP */
3212 manc |= E1000_MANC_ARP_EN;
3213 manc &= ~E1000_MANC_EN_MNG2HOST;
3215 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3220 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3221 * For ASF and Pass Through versions of f/w this means that
3222 * the driver is loaded. For AMT version (only with 82573)
3223 * of the f/w this means that the network i/f is open.
3226 emx_get_hw_control(struct emx_softc *sc)
3228 /* Let firmware know the driver has taken over */
3229 if (sc->hw.mac.type == e1000_82573) {
3232 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3233 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3234 swsm | E1000_SWSM_DRV_LOAD);
3238 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3239 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3240 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3242 sc->flags |= EMX_FLAG_HW_CTRL;
3246 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3247 * For ASF and Pass Through versions of f/w this means that the
3248 * driver is no longer loaded. For AMT version (only with 82573)
3249 * of the f/w this means that the network i/f is closed.
3252 emx_rel_hw_control(struct emx_softc *sc)
3254 if ((sc->flags & EMX_FLAG_HW_CTRL) == 0)
3256 sc->flags &= ~EMX_FLAG_HW_CTRL;
3258 /* Let firmware taken over control of h/w */
3259 if (sc->hw.mac.type == e1000_82573) {
3262 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3263 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3264 swsm & ~E1000_SWSM_DRV_LOAD);
3268 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3269 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3270 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3275 emx_is_valid_eaddr(const uint8_t *addr)
3277 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3279 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3286 * Enable PCI Wake On Lan capability
3289 emx_enable_wol(device_t dev)
3291 uint16_t cap, status;
3294 /* First find the capabilities pointer*/
3295 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3297 /* Read the PM Capabilities */
3298 id = pci_read_config(dev, cap, 1);
3299 if (id != PCIY_PMG) /* Something wrong */
3303 * OK, we have the power capabilities,
3304 * so now get the status register
3306 cap += PCIR_POWER_STATUS;
3307 status = pci_read_config(dev, cap, 2);
3308 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3309 pci_write_config(dev, cap, status, 2);
3313 emx_update_stats(struct emx_softc *sc)
3315 struct ifnet *ifp = &sc->arpcom.ac_if;
3317 if (sc->hw.phy.media_type == e1000_media_type_copper ||
3318 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3319 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
3320 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
3322 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
3323 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
3324 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
3325 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
3327 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
3328 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
3329 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
3330 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
3331 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
3332 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
3333 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
3334 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
3335 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
3336 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
3337 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
3338 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
3339 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
3340 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
3341 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
3342 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
3343 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
3344 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
3345 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
3346 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
3348 /* For the 64-bit byte counters the low dword must be read first. */
3349 /* Both registers clear on the read of the high dword */
3351 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH);
3352 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH);
3354 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
3355 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
3356 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
3357 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
3358 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
3360 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
3361 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
3363 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
3364 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
3365 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
3366 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
3367 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
3368 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
3369 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
3370 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
3371 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
3372 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
3374 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
3375 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC);
3376 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS);
3377 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR);
3378 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC);
3379 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC);
3381 IFNET_STAT_SET(ifp, collisions, sc->stats.colc);
3384 IFNET_STAT_SET(ifp, ierrors,
3385 sc->stats.rxerrc + sc->stats.crcerrs + sc->stats.algnerrc +
3386 sc->stats.ruc + sc->stats.roc + sc->stats.mpc + sc->stats.cexterr);
3389 IFNET_STAT_SET(ifp, oerrors, sc->stats.ecol + sc->stats.latecol);
3393 emx_print_debug_info(struct emx_softc *sc)
3395 device_t dev = sc->dev;
3396 uint8_t *hw_addr = sc->hw.hw_addr;
3399 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3400 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3401 E1000_READ_REG(&sc->hw, E1000_CTRL),
3402 E1000_READ_REG(&sc->hw, E1000_RCTL));
3403 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3404 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\
3405 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) );
3406 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3407 sc->hw.fc.high_water, sc->hw.fc.low_water);
3408 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3409 E1000_READ_REG(&sc->hw, E1000_TIDV),
3410 E1000_READ_REG(&sc->hw, E1000_TADV));
3411 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3412 E1000_READ_REG(&sc->hw, E1000_RDTR),
3413 E1000_READ_REG(&sc->hw, E1000_RADV));
3415 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3416 device_printf(dev, "hw %d tdh = %d, hw tdt = %d\n", i,
3417 E1000_READ_REG(&sc->hw, E1000_TDH(i)),
3418 E1000_READ_REG(&sc->hw, E1000_TDT(i)));
3420 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3421 device_printf(dev, "hw %d rdh = %d, hw rdt = %d\n", i,
3422 E1000_READ_REG(&sc->hw, E1000_RDH(i)),
3423 E1000_READ_REG(&sc->hw, E1000_RDT(i)));
3426 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3427 device_printf(dev, "TX %d Tx descriptors avail = %d\n", i,
3428 sc->tx_data[i].num_tx_desc_avail);
3429 device_printf(dev, "TX %d TSO segments = %lu\n", i,
3430 sc->tx_data[i].tso_segments);
3431 device_printf(dev, "TX %d TSO ctx reused = %lu\n", i,
3432 sc->tx_data[i].tso_ctx_reused);
3437 emx_print_hw_stats(struct emx_softc *sc)
3439 device_t dev = sc->dev;
3441 device_printf(dev, "Excessive collisions = %lld\n",
3442 (long long)sc->stats.ecol);
3443 #if (DEBUG_HW > 0) /* Dont output these errors normally */
3444 device_printf(dev, "Symbol errors = %lld\n",
3445 (long long)sc->stats.symerrs);
3447 device_printf(dev, "Sequence errors = %lld\n",
3448 (long long)sc->stats.sec);
3449 device_printf(dev, "Defer count = %lld\n",
3450 (long long)sc->stats.dc);
3451 device_printf(dev, "Missed Packets = %lld\n",
3452 (long long)sc->stats.mpc);
3453 device_printf(dev, "Receive No Buffers = %lld\n",
3454 (long long)sc->stats.rnbc);
3455 /* RLEC is inaccurate on some hardware, calculate our own. */
3456 device_printf(dev, "Receive Length Errors = %lld\n",
3457 ((long long)sc->stats.roc + (long long)sc->stats.ruc));
3458 device_printf(dev, "Receive errors = %lld\n",
3459 (long long)sc->stats.rxerrc);
3460 device_printf(dev, "Crc errors = %lld\n",
3461 (long long)sc->stats.crcerrs);
3462 device_printf(dev, "Alignment errors = %lld\n",
3463 (long long)sc->stats.algnerrc);
3464 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3465 (long long)sc->stats.cexterr);
3466 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns);
3467 device_printf(dev, "XON Rcvd = %lld\n",
3468 (long long)sc->stats.xonrxc);
3469 device_printf(dev, "XON Xmtd = %lld\n",
3470 (long long)sc->stats.xontxc);
3471 device_printf(dev, "XOFF Rcvd = %lld\n",
3472 (long long)sc->stats.xoffrxc);
3473 device_printf(dev, "XOFF Xmtd = %lld\n",
3474 (long long)sc->stats.xofftxc);
3475 device_printf(dev, "Good Packets Rcvd = %lld\n",
3476 (long long)sc->stats.gprc);
3477 device_printf(dev, "Good Packets Xmtd = %lld\n",
3478 (long long)sc->stats.gptc);
3482 emx_print_nvm_info(struct emx_softc *sc)
3484 uint16_t eeprom_data;
3487 /* Its a bit crude, but it gets the job done */
3488 kprintf("\nInterface EEPROM Dump:\n");
3489 kprintf("Offset\n0x0000 ");
3490 for (i = 0, j = 0; i < 32; i++, j++) {
3491 if (j == 8) { /* Make the offset block */
3493 kprintf("\n0x00%x0 ",row);
3495 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data);
3496 kprintf("%04x ", eeprom_data);
3502 emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3504 struct emx_softc *sc;
3509 error = sysctl_handle_int(oidp, &result, 0, req);
3510 if (error || !req->newptr)
3513 sc = (struct emx_softc *)arg1;
3514 ifp = &sc->arpcom.ac_if;
3516 ifnet_serialize_all(ifp);
3519 emx_print_debug_info(sc);
3522 * This value will cause a hex dump of the
3523 * first 32 16-bit words of the EEPROM to
3527 emx_print_nvm_info(sc);
3529 ifnet_deserialize_all(ifp);
3535 emx_sysctl_stats(SYSCTL_HANDLER_ARGS)
3540 error = sysctl_handle_int(oidp, &result, 0, req);
3541 if (error || !req->newptr)
3545 struct emx_softc *sc = (struct emx_softc *)arg1;
3546 struct ifnet *ifp = &sc->arpcom.ac_if;
3548 ifnet_serialize_all(ifp);
3549 emx_print_hw_stats(sc);
3550 ifnet_deserialize_all(ifp);
3556 emx_add_sysctl(struct emx_softc *sc)
3558 #if defined(EMX_RSS_DEBUG) || defined(EMX_TSS_DEBUG)
3563 sysctl_ctx_init(&sc->sysctl_ctx);
3564 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
3565 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
3566 device_get_nameunit(sc->dev),
3568 if (sc->sysctl_tree == NULL) {
3569 device_printf(sc->dev, "can't add sysctl node\n");
3573 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3574 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3575 emx_sysctl_debug_info, "I", "Debug Information");
3577 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3578 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3579 emx_sysctl_stats, "I", "Statistics");
3581 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3582 OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_data[0].num_rx_desc, 0,
3584 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3585 OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_data[0].num_tx_desc, 0,
3588 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3589 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3590 emx_sysctl_int_throttle, "I", "interrupt throttling rate");
3591 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3592 OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3593 emx_sysctl_tx_intr_nsegs, "I", "# segments per TX interrupt");
3594 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3595 OID_AUTO, "tx_wreg_nsegs", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3596 emx_sysctl_tx_wreg_nsegs, "I",
3597 "# segments sent before write to hardware register");
3599 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3600 OID_AUTO, "rx_ring_cnt", CTLFLAG_RD, &sc->rx_ring_cnt, 0,
3602 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3603 OID_AUTO, "tx_ring_cnt", CTLFLAG_RD, &sc->tx_ring_cnt, 0,
3605 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3606 OID_AUTO, "tx_ring_inuse", CTLFLAG_RD, &sc->tx_ring_inuse, 0,
3607 "# of TX rings used");
3609 #ifdef IFPOLL_ENABLE
3610 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3611 OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW,
3612 sc, 0, emx_sysctl_npoll_rxoff, "I",
3613 "NPOLLING RX cpu offset");
3614 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3615 OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW,
3616 sc, 0, emx_sysctl_npoll_txoff, "I",
3617 "NPOLLING TX cpu offset");
3620 #ifdef EMX_RSS_DEBUG
3621 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3622 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug,
3623 0, "RSS debug level");
3624 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3625 ksnprintf(pkt_desc, sizeof(pkt_desc), "rx%d_pkt", i);
3626 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
3627 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO,
3628 pkt_desc, CTLFLAG_RW, &sc->rx_data[i].rx_pkts,
3632 #ifdef EMX_TSS_DEBUG
3633 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3634 ksnprintf(pkt_desc, sizeof(pkt_desc), "tx%d_pkt", i);
3635 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
3636 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO,
3637 pkt_desc, CTLFLAG_RW, &sc->tx_data[i].tx_pkts,
3644 emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3646 struct emx_softc *sc = (void *)arg1;
3647 struct ifnet *ifp = &sc->arpcom.ac_if;
3648 int error, throttle;
3650 throttle = sc->int_throttle_ceil;
3651 error = sysctl_handle_int(oidp, &throttle, 0, req);
3652 if (error || req->newptr == NULL)
3654 if (throttle < 0 || throttle > 1000000000 / 256)
3659 * Set the interrupt throttling rate in 256ns increments,
3660 * recalculate sysctl value assignment to get exact frequency.
3662 throttle = 1000000000 / 256 / throttle;
3664 /* Upper 16bits of ITR is reserved and should be zero */
3665 if (throttle & 0xffff0000)
3669 ifnet_serialize_all(ifp);
3672 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
3674 sc->int_throttle_ceil = 0;
3676 if (ifp->if_flags & IFF_RUNNING)
3677 emx_set_itr(sc, throttle);
3679 ifnet_deserialize_all(ifp);
3682 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
3683 sc->int_throttle_ceil);
3689 emx_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3691 struct emx_softc *sc = (void *)arg1;
3692 struct ifnet *ifp = &sc->arpcom.ac_if;
3693 struct emx_txdata *tdata = &sc->tx_data[0];
3696 segs = tdata->tx_intr_nsegs;
3697 error = sysctl_handle_int(oidp, &segs, 0, req);
3698 if (error || req->newptr == NULL)
3703 ifnet_serialize_all(ifp);
3706 * Don't allow tx_intr_nsegs to become:
3707 * o Less the oact_tx_desc
3708 * o Too large that no TX desc will cause TX interrupt to
3709 * be generated (OACTIVE will never recover)
3710 * o Too small that will cause tx_dd[] overflow
3712 if (segs < tdata->oact_tx_desc ||
3713 segs >= tdata->num_tx_desc - tdata->oact_tx_desc ||
3714 segs < tdata->num_tx_desc / EMX_TXDD_SAFE) {
3720 for (i = 0; i < sc->tx_ring_cnt; ++i)
3721 sc->tx_data[i].tx_intr_nsegs = segs;
3724 ifnet_deserialize_all(ifp);
3730 emx_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS)
3732 struct emx_softc *sc = (void *)arg1;
3733 struct ifnet *ifp = &sc->arpcom.ac_if;
3734 int error, nsegs, i;
3736 nsegs = sc->tx_data[0].tx_wreg_nsegs;
3737 error = sysctl_handle_int(oidp, &nsegs, 0, req);
3738 if (error || req->newptr == NULL)
3741 ifnet_serialize_all(ifp);
3742 for (i = 0; i < sc->tx_ring_cnt; ++i)
3743 sc->tx_data[i].tx_wreg_nsegs =nsegs;
3744 ifnet_deserialize_all(ifp);
3749 #ifdef IFPOLL_ENABLE
3752 emx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3754 struct emx_softc *sc = (void *)arg1;
3755 struct ifnet *ifp = &sc->arpcom.ac_if;
3758 off = sc->rx_npoll_off;
3759 error = sysctl_handle_int(oidp, &off, 0, req);
3760 if (error || req->newptr == NULL)
3765 ifnet_serialize_all(ifp);
3766 if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) {
3770 sc->rx_npoll_off = off;
3772 ifnet_deserialize_all(ifp);
3778 emx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3780 struct emx_softc *sc = (void *)arg1;
3781 struct ifnet *ifp = &sc->arpcom.ac_if;
3784 off = sc->tx_npoll_off;
3785 error = sysctl_handle_int(oidp, &off, 0, req);
3786 if (error || req->newptr == NULL)
3791 ifnet_serialize_all(ifp);
3792 if (off >= ncpus2 || off % sc->tx_ring_cnt != 0) {
3796 sc->tx_npoll_off = off;
3798 ifnet_deserialize_all(ifp);
3803 #endif /* IFPOLL_ENABLE */
3806 emx_dma_alloc(struct emx_softc *sc)
3811 * Create top level busdma tag
3813 error = bus_dma_tag_create(NULL, 1, 0,
3814 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3816 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3817 0, &sc->parent_dtag);
3819 device_printf(sc->dev, "could not create top level DMA tag\n");
3824 * Allocate transmit descriptors ring and buffers
3826 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3827 error = emx_create_tx_ring(&sc->tx_data[i]);
3829 device_printf(sc->dev,
3830 "Could not setup transmit structures\n");
3836 * Allocate receive descriptors ring and buffers
3838 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3839 error = emx_create_rx_ring(&sc->rx_data[i]);
3841 device_printf(sc->dev,
3842 "Could not setup receive structures\n");
3850 emx_dma_free(struct emx_softc *sc)
3854 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3855 emx_destroy_tx_ring(&sc->tx_data[i],
3856 sc->tx_data[i].num_tx_desc);
3859 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3860 emx_destroy_rx_ring(&sc->rx_data[i],
3861 sc->rx_data[i].num_rx_desc);
3864 /* Free top level busdma tag */
3865 if (sc->parent_dtag != NULL)
3866 bus_dma_tag_destroy(sc->parent_dtag);
3870 emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3872 struct emx_softc *sc = ifp->if_softc;
3874 ifnet_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, slz);
3878 emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3880 struct emx_softc *sc = ifp->if_softc;
3882 ifnet_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, slz);
3886 emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3888 struct emx_softc *sc = ifp->if_softc;
3890 return ifnet_serialize_array_try(sc->serializes, EMX_NSERIALIZE, slz);
3894 emx_serialize_skipmain(struct emx_softc *sc)
3896 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1);
3900 emx_deserialize_skipmain(struct emx_softc *sc)
3902 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1);
3908 emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3909 boolean_t serialized)
3911 struct emx_softc *sc = ifp->if_softc;
3913 ifnet_serialize_array_assert(sc->serializes, EMX_NSERIALIZE,
3917 #endif /* INVARIANTS */
3919 #ifdef IFPOLL_ENABLE
3922 emx_npoll_status(struct ifnet *ifp)
3924 struct emx_softc *sc = ifp->if_softc;
3927 ASSERT_SERIALIZED(&sc->main_serialize);
3929 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3930 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3931 callout_stop(&sc->timer);
3932 sc->hw.mac.get_link_status = 1;
3933 emx_update_link_status(sc);
3934 callout_reset(&sc->timer, hz, emx_timer, sc);
3939 emx_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused)
3941 struct emx_txdata *tdata = arg;
3943 ASSERT_SERIALIZED(&tdata->tx_serialize);
3946 if (!ifsq_is_empty(tdata->ifsq))
3947 ifsq_devstart(tdata->ifsq);
3951 emx_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle)
3953 struct emx_rxdata *rdata = arg;
3955 ASSERT_SERIALIZED(&rdata->rx_serialize);
3957 emx_rxeof(rdata, cycle);
3961 emx_npoll(struct ifnet *ifp, struct ifpoll_info *info)
3963 struct emx_softc *sc = ifp->if_softc;
3966 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3971 info->ifpi_status.status_func = emx_npoll_status;
3972 info->ifpi_status.serializer = &sc->main_serialize;
3974 txr_cnt = emx_get_txring_inuse(sc, TRUE);
3975 off = sc->tx_npoll_off;
3976 for (i = 0; i < txr_cnt; ++i) {
3977 struct emx_txdata *tdata = &sc->tx_data[i];
3980 KKASSERT(idx < ncpus2);
3981 info->ifpi_tx[idx].poll_func = emx_npoll_tx;
3982 info->ifpi_tx[idx].arg = tdata;
3983 info->ifpi_tx[idx].serializer = &tdata->tx_serialize;
3984 ifsq_set_cpuid(tdata->ifsq, idx);
3987 off = sc->rx_npoll_off;
3988 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3989 struct emx_rxdata *rdata = &sc->rx_data[i];
3992 KKASSERT(idx < ncpus2);
3993 info->ifpi_rx[idx].poll_func = emx_npoll_rx;
3994 info->ifpi_rx[idx].arg = rdata;
3995 info->ifpi_rx[idx].serializer = &rdata->rx_serialize;
3998 if (ifp->if_flags & IFF_RUNNING) {
3999 if (txr_cnt == sc->tx_ring_inuse)
4000 emx_disable_intr(sc);
4005 for (i = 0; i < sc->tx_ring_cnt; ++i) {
4006 struct emx_txdata *tdata = &sc->tx_data[i];
4008 ifsq_set_cpuid(tdata->ifsq,
4009 rman_get_cpuid(sc->intr_res));
4012 if (ifp->if_flags & IFF_RUNNING) {
4013 txr_cnt = emx_get_txring_inuse(sc, FALSE);
4014 if (txr_cnt == sc->tx_ring_inuse)
4015 emx_enable_intr(sc);
4022 #endif /* IFPOLL_ENABLE */
4025 emx_set_itr(struct emx_softc *sc, uint32_t itr)
4027 E1000_WRITE_REG(&sc->hw, E1000_ITR, itr);
4028 if (sc->hw.mac.type == e1000_82574) {
4032 * When using MSIX interrupts we need to
4033 * throttle using the EITR register
4035 for (i = 0; i < 4; ++i)
4036 E1000_WRITE_REG(&sc->hw, E1000_EITR_82574(i), itr);
4041 * Disable the L0s, 82574L Errata #20
4044 emx_disable_aspm(struct emx_softc *sc)
4046 uint16_t link_cap, link_ctrl, disable;
4047 uint8_t pcie_ptr, reg;
4048 device_t dev = sc->dev;
4050 switch (sc->hw.mac.type) {
4055 * 82573 specification update
4056 * errata #8 disable L0s
4057 * errata #41 disable L1
4059 * 82571/82572 specification update
4060 # errata #13 disable L1
4061 * errata #68 disable L0s
4063 disable = PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1;
4068 * 82574 specification update errata #20
4070 * There is no need to disable L1
4072 disable = PCIEM_LNKCTL_ASPM_L0S;
4079 pcie_ptr = pci_get_pciecap_ptr(dev);
4083 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2);
4084 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0)
4088 if_printf(&sc->arpcom.ac_if, "disable ASPM %#02x\n", disable);
4090 reg = pcie_ptr + PCIER_LINKCTRL;
4091 link_ctrl = pci_read_config(dev, reg, 2);
4092 link_ctrl &= ~disable;
4093 pci_write_config(dev, reg, link_ctrl, 2);
4097 emx_tso_pullup(struct emx_txdata *tdata, struct mbuf **mp)
4099 int iphlen, hoff, thoff, ex = 0;
4104 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4106 iphlen = m->m_pkthdr.csum_iphlen;
4107 thoff = m->m_pkthdr.csum_thlen;
4108 hoff = m->m_pkthdr.csum_lhlen;
4110 KASSERT(iphlen > 0, ("invalid ip hlen"));
4111 KASSERT(thoff > 0, ("invalid tcp hlen"));
4112 KASSERT(hoff > 0, ("invalid ether hlen"));
4114 if (tdata->tx_flags & EMX_TXFLAG_TSO_PULLEX)
4117 if (m->m_len < hoff + iphlen + thoff + ex) {
4118 m = m_pullup(m, hoff + iphlen + thoff + ex);
4125 ip = mtodoff(m, struct ip *, hoff);
4132 emx_tso_setup(struct emx_txdata *tdata, struct mbuf *mp,
4133 uint32_t *txd_upper, uint32_t *txd_lower)
4135 struct e1000_context_desc *TXD;
4136 int hoff, iphlen, thoff, hlen;
4137 int mss, pktlen, curr_txd;
4139 #ifdef EMX_TSO_DEBUG
4140 tdata->tso_segments++;
4143 iphlen = mp->m_pkthdr.csum_iphlen;
4144 thoff = mp->m_pkthdr.csum_thlen;
4145 hoff = mp->m_pkthdr.csum_lhlen;
4146 mss = mp->m_pkthdr.tso_segsz;
4147 pktlen = mp->m_pkthdr.len;
4149 if ((tdata->tx_flags & EMX_TXFLAG_FORCECTX) == 0 &&
4150 tdata->csum_flags == CSUM_TSO &&
4151 tdata->csum_iphlen == iphlen &&
4152 tdata->csum_lhlen == hoff &&
4153 tdata->csum_thlen == thoff &&
4154 tdata->csum_mss == mss &&
4155 tdata->csum_pktlen == pktlen) {
4156 *txd_upper = tdata->csum_txd_upper;
4157 *txd_lower = tdata->csum_txd_lower;
4158 #ifdef EMX_TSO_DEBUG
4159 tdata->tso_ctx_reused++;
4163 hlen = hoff + iphlen + thoff;
4166 * Setup a new TSO context.
4169 curr_txd = tdata->next_avail_tx_desc;
4170 TXD = (struct e1000_context_desc *)&tdata->tx_desc_base[curr_txd];
4172 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
4173 E1000_TXD_DTYP_D | /* Data descr type */
4174 E1000_TXD_CMD_TSE; /* Do TSE on this packet */
4176 /* IP and/or TCP header checksum calculation and insertion. */
4177 *txd_upper = (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8;
4180 * Start offset for header checksum calculation.
4181 * End offset for header checksum calculation.
4182 * Offset of place put the checksum.
4184 TXD->lower_setup.ip_fields.ipcss = hoff;
4185 TXD->lower_setup.ip_fields.ipcse = htole16(hoff + iphlen - 1);
4186 TXD->lower_setup.ip_fields.ipcso = hoff + offsetof(struct ip, ip_sum);
4189 * Start offset for payload checksum calculation.
4190 * End offset for payload checksum calculation.
4191 * Offset of place to put the checksum.
4193 TXD->upper_setup.tcp_fields.tucss = hoff + iphlen;
4194 TXD->upper_setup.tcp_fields.tucse = 0;
4195 TXD->upper_setup.tcp_fields.tucso =
4196 hoff + iphlen + offsetof(struct tcphdr, th_sum);
4199 * Payload size per packet w/o any headers.
4200 * Length of all headers up to payload.
4202 TXD->tcp_seg_setup.fields.mss = htole16(mss);
4203 TXD->tcp_seg_setup.fields.hdr_len = hlen;
4204 TXD->cmd_and_length = htole32(E1000_TXD_CMD_IFCS |
4205 E1000_TXD_CMD_DEXT | /* Extended descr */
4206 E1000_TXD_CMD_TSE | /* TSE context */
4207 E1000_TXD_CMD_IP | /* Do IP csum */
4208 E1000_TXD_CMD_TCP | /* Do TCP checksum */
4209 (pktlen - hlen)); /* Total len */
4211 /* Save the information for this TSO context */
4212 tdata->csum_flags = CSUM_TSO;
4213 tdata->csum_lhlen = hoff;
4214 tdata->csum_iphlen = iphlen;
4215 tdata->csum_thlen = thoff;
4216 tdata->csum_mss = mss;
4217 tdata->csum_pktlen = pktlen;
4218 tdata->csum_txd_upper = *txd_upper;
4219 tdata->csum_txd_lower = *txd_lower;
4221 if (++curr_txd == tdata->num_tx_desc)
4224 KKASSERT(tdata->num_tx_desc_avail > 0);
4225 tdata->num_tx_desc_avail--;
4227 tdata->next_avail_tx_desc = curr_txd;
4232 emx_get_txring_inuse(const struct emx_softc *sc, boolean_t polling)
4235 return sc->tx_ring_cnt;