sys/dev/misc/ecc/ecc_e31200.c

   1 /*
   2  * Copyright (c) 2011 The DragonFly Project.  All rights reserved.
   3  *
   4  * This code is derived from software contributed to The DragonFly Project
   5  * by Sepherosa Ziehau <sepherosa@gmail.com>
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  *
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in
  15  *    the documentation and/or other materials provided with the
  16  *    distribution.
  17  * 3. Neither the name of The DragonFly Project nor the names of its
  18  *    contributors may be used to endorse or promote products derived
  19  *    from this software without specific, prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  24  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
  25  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  26  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
  27  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  28  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  29  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  31  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  32  * SUCH DAMAGE.
  33  */
  34
  35 #include <sys/param.h>
  36 #include <sys/systm.h>
  37 #include <sys/bus.h>
  38 #include <sys/kernel.h>
  39 #include <sys/malloc.h>
  40 #include <sys/bitops.h>
  41
  42 #include <bus/pci/pcivar.h>
  43 #include <bus/pci/pcireg.h>
  44 #include <bus/pci/pcibus.h>
  45 #include <bus/pci/pci_cfgreg.h>
  46
  47 #include <vm/pmap.h>
  48
  49 #include "pcib_if.h"
  50
  51 #include <dev/misc/ecc/ecc_e31200_reg.h>
  52
  53 #define ECC_E31200_VER_1        1       /* Sandy Bridge */
  54 #define ECC_E31200_VER_2        2       /* Ivy Bridge */
  55 #define ECC_E31200_VER_3        3       /* Haswell */
  56
  57 struct ecc_e31200_memctrl {
  58         uint16_t        vid;
  59         uint16_t        did;
  60         const char      *desc;
  61         int             ver;            /* ECC_E31200_VER_ */
  62 };
  63
  64 struct ecc_e31200_softc {
  65         device_t        ecc_dev;
  66         struct callout  ecc_callout;
  67         int             ecc_ver;        /* ECC_E31200_VER_ */
  68         volatile uint8_t *ecc_addr;
  69 };
  70
  71 #define CSR_READ_4(sc, ofs)     (*(volatile uint32_t *)((sc)->ecc_addr + (ofs)))
  72
  73 #define ecc_printf(sc, fmt, arg...) \
  74         device_printf((sc)->ecc_dev, fmt , ##arg)
  75
  76 static void     ecc_e31200_identify(driver_t *, device_t);
  77 static int      ecc_e31200_probe(device_t);
  78 static int      ecc_e31200_attach(device_t);
  79 static int      ecc_e31200_detach(device_t);
  80 static void     ecc_e31200_shutdown(device_t);
  81
  82 static void     ecc_e31200_chaninfo(struct ecc_e31200_softc *, uint32_t,
  83                     const char *);
  84 static void     ecc_e31200_status(struct ecc_e31200_softc *);
  85 static void     ecc_e31200_callout(void *);
  86 static void     ecc_e31200_errlog(struct ecc_e31200_softc *);
  87 static void     ecc_e31200_errlog_ch(struct ecc_e31200_softc *, int, int,
  88                     const char *);
  89
  90 static const struct ecc_e31200_memctrl ecc_memctrls[] = {
  91         { 0x8086, 0x0108, "Intel E3-1200 memory controller",
  92           ECC_E31200_VER_1 },
  93         { 0x8086, 0x0158, "Intel E3-1200 v2 memory controller",
  94           ECC_E31200_VER_2 },
  95         { 0x8086, 0x0c08, "Intel E3-1200 v3 memory controller",
  96           ECC_E31200_VER_3 },
  97         { 0, 0, NULL } /* required last entry */
  98 };
  99
 100 static device_method_t ecc_e31200_methods[] = {
 101         /* Device interface */
 102         DEVMETHOD(device_identify,      ecc_e31200_identify),
 103         DEVMETHOD(device_probe,         ecc_e31200_probe),
 104         DEVMETHOD(device_attach,        ecc_e31200_attach),
 105         DEVMETHOD(device_detach,        ecc_e31200_detach),
 106         DEVMETHOD(device_shutdown,      ecc_e31200_shutdown),
 107         DEVMETHOD(device_suspend,       bus_generic_suspend),
 108         DEVMETHOD(device_resume,        bus_generic_resume),
 109         DEVMETHOD_END
 110 };
 111
 112 static driver_t ecc_e31200_driver = {
 113         "ecc",
 114         ecc_e31200_methods,
 115         sizeof(struct ecc_e31200_softc)
 116 };
 117 static devclass_t ecc_devclass;
 118 DRIVER_MODULE(ecc_e31200, hostb, ecc_e31200_driver, ecc_devclass, NULL, NULL);
 119 MODULE_DEPEND(ecc_e31200, pci, 1, 1, 1);
 120
 121 static void
 122 ecc_e31200_identify(driver_t *driver, device_t parent)
 123 {
 124         const struct ecc_e31200_memctrl *mc;
 125         uint16_t vid, did;
 126
 127         /* Already identified */
 128         if (device_find_child(parent, "ecc", -1) != NULL)
 129                 return;
 130
 131         vid = pci_get_vendor(parent);
 132         did = pci_get_device(parent);
 133
 134         for (mc = ecc_memctrls; mc->desc != NULL; ++mc) {
 135                 if (mc->vid == vid && mc->did == did) {
 136                         if (device_add_child(parent, "ecc", -1) == NULL)
 137                                 device_printf(parent, "add ecc child failed\n");
 138                         return;
 139                 }
 140         }
 141 }
 142
 143 static int
 144 ecc_e31200_probe(device_t dev)
 145 {
 146         const struct ecc_e31200_memctrl *mc;
 147         uint16_t vid, did;
 148
 149         vid = pci_get_vendor(dev);
 150         did = pci_get_device(dev);
 151
 152         for (mc = ecc_memctrls; mc->desc != NULL; ++mc) {
 153                 if (mc->vid == vid && mc->did == did) {
 154                         struct ecc_e31200_softc *sc = device_get_softc(dev);
 155
 156                         device_set_desc(dev, mc->desc);
 157                         sc->ecc_ver = mc->ver;
 158                         return (0);
 159                 }
 160         }
 161         return (ENXIO);
 162 }
 163
 164 static int
 165 ecc_e31200_attach(device_t dev)
 166 {
 167         struct ecc_e31200_softc *sc = device_get_softc(dev);
 168         uint32_t capa, dmfc, mch_barlo, mch_barhi;
 169         uint64_t mch_bar;
 170         int dmfc_parsed = 1;
 171
 172         callout_init_mp(&sc->ecc_callout);
 173         sc->ecc_dev = dev;
 174
 175         capa = pci_read_config(dev, PCI_E31200_CAPID0_A, 4);
 176
 177         if (sc->ecc_ver == ECC_E31200_VER_1) {
 178                 dmfc = __SHIFTOUT(capa, PCI_E31200_CAPID0_A_DMFC);
 179         } else { /* V2/V3 */
 180                 uint32_t capb;
 181
 182                 capb = pci_read_config(dev, PCI_E31200_CAPID0_B, 4);
 183                 dmfc = __SHIFTOUT(capb, PCI_E31200_CAPID0_B_DMFC);
 184         }
 185
 186         if (dmfc == PCI_E31200_CAPID0_DMFC_1067) {
 187                 ecc_printf(sc, "CAP DDR3 1067 ");
 188         } else if (dmfc == PCI_E31200_CAPID0_DMFC_1333) {
 189                 ecc_printf(sc, "CAP DDR3 1333 ");
 190         } else {
 191                 if (sc->ecc_ver == ECC_E31200_VER_1) {
 192                         if (dmfc == PCI_E31200_CAPID0_DMFC_V1_ALL)
 193                                 ecc_printf(sc, "no CAP ");
 194                         else
 195                                 dmfc_parsed = 0;
 196                 } else { /* V2/V3 */
 197                         if (dmfc == PCI_E31200_CAPID0_DMFC_1600)
 198                                 ecc_printf(sc, "CAP DDR3 1600 ");
 199                         else if (dmfc == PCI_E31200_CAPID0_DMFC_1867)
 200                                 ecc_printf(sc, "CAP DDR3 1867 ");
 201                         else if (dmfc == PCI_E31200_CAPID0_DMFC_2133)
 202                                 ecc_printf(sc, "CAP DDR3 2133 ");
 203                         else if (dmfc == PCI_E31200_CAPID0_DMFC_2400)
 204                                 ecc_printf(sc, "CAP DDR3 2400 ");
 205                         else if (dmfc == PCI_E31200_CAPID0_DMFC_2667)
 206                                 ecc_printf(sc, "CAP DDR3 2667 ");
 207                         else if (dmfc == PCI_E31200_CAPID0_DMFC_2933)
 208                                 ecc_printf(sc, "CAP DDR3 2933 ");
 209                         else
 210                                 dmfc_parsed = 0;
 211                 }
 212         }
 213         if (!dmfc_parsed) {
 214                 ecc_printf(sc, "unknown DMFC %#x\n", dmfc);
 215                 return 0;
 216         }
 217
 218         if (capa & PCI_E31200_CAPID0_A_ECCDIS) {
 219                 kprintf("NON-ECC\n");
 220                 return 0;
 221         } else {
 222                 kprintf("ECC\n");
 223         }
 224
 225         mch_barlo = pci_read_config(dev, PCI_E31200_MCHBAR_LO, 4);
 226         mch_barhi = pci_read_config(dev, PCI_E31200_MCHBAR_HI, 4);
 227
 228         mch_bar = (uint64_t)mch_barlo | (((uint64_t)mch_barhi) << 32);
 229         if (bootverbose)
 230                 ecc_printf(sc, "MCHBAR %jx\n", (uintmax_t)mch_bar);
 231
 232         if (mch_bar & PCI_E31200_MCHBAR_LO_EN) {
 233                 uint64_t map_addr = mch_bar & PCI_E31200_MCHBAR_ADDRMASK;
 234                 uint32_t dimm_ch0, dimm_ch1;
 235                 int ecc_active;
 236
 237                 sc->ecc_addr = pmap_mapdev_uncacheable(map_addr,
 238                     MCH_E31200_SIZE);
 239
 240                 if (bootverbose) {
 241                         ecc_printf(sc, "LOG0_C0 %#x\n",
 242                             CSR_READ_4(sc, MCH_E31200_ERRLOG0_C0));
 243                         ecc_printf(sc, "LOG0_C1 %#x\n",
 244                             CSR_READ_4(sc, MCH_E31200_ERRLOG0_C1));
 245                 }
 246
 247                 dimm_ch0 = CSR_READ_4(sc, MCH_E31200_DIMM_CH0);
 248                 dimm_ch1 = CSR_READ_4(sc, MCH_E31200_DIMM_CH1);
 249
 250                 if (bootverbose) {
 251                         ecc_e31200_chaninfo(sc, dimm_ch0, "channel0");
 252                         ecc_e31200_chaninfo(sc, dimm_ch1, "channel1");
 253                 }
 254
 255                 ecc_active = 1;
 256                 if (sc->ecc_ver == ECC_E31200_VER_1 ||
 257                     sc->ecc_ver == ECC_E31200_VER_2) {
 258                         if (((dimm_ch0 | dimm_ch1) & MCH_E31200_DIMM_ECC) ==
 259                             MCH_E31200_DIMM_ECC_NONE) {
 260                                 ecc_active = 0;
 261                                 ecc_printf(sc, "No ECC active\n");
 262                         }
 263                 } else { /* V3 */
 264                         uint32_t ecc_mode0, ecc_mode1;
 265
 266                         ecc_mode0 = __SHIFTOUT(dimm_ch0, MCH_E31200_DIMM_ECC);
 267                         ecc_mode1 = __SHIFTOUT(dimm_ch1, MCH_E31200_DIMM_ECC);
 268
 269                         /*
 270                          * Only active ALL/NONE is supported
 271                          */
 272
 273                         if (ecc_mode0 != MCH_E31200_DIMM_ECC_NONE &&
 274                             ecc_mode0 != MCH_E31200_DIMM_ECC_ALL) {
 275                                 ecc_active = 0;
 276                                 ecc_printf(sc, "channel0, invalid ECC "
 277                                     "active 0x%x\n", ecc_mode0);
 278                         }
 279                         if (ecc_mode1 != MCH_E31200_DIMM_ECC_NONE &&
 280                             ecc_mode1 != MCH_E31200_DIMM_ECC_ALL) {
 281                                 ecc_active = 0;
 282                                 ecc_printf(sc, "channel1, invalid ECC "
 283                                     "active 0x%x\n", ecc_mode1);
 284                         }
 285
 286                         if (ecc_mode0 == MCH_E31200_DIMM_ECC_NONE &&
 287                             ecc_mode1 == MCH_E31200_DIMM_ECC_NONE) {
 288                                 ecc_active = 0;
 289                                 ecc_printf(sc, "No ECC active\n");
 290                         }
 291                 }
 292
 293                 if (!ecc_active) {
 294                         pmap_unmapdev((vm_offset_t)sc->ecc_addr,
 295                             MCH_E31200_SIZE);
 296                         sc->ecc_addr = NULL;
 297                         return 0;
 298                 }
 299         } else {
 300                 ecc_printf(sc, "MCHBAR is not enabled\n");
 301         }
 302
 303         ecc_e31200_status(sc);
 304         callout_reset(&sc->ecc_callout, hz, ecc_e31200_callout, sc);
 305
 306         return 0;
 307 }
 308
 309 static void
 310 ecc_e31200_callout(void *xsc)
 311 {
 312         struct ecc_e31200_softc *sc = xsc;
 313
 314         ecc_e31200_status(sc);
 315         callout_reset(&sc->ecc_callout, hz, ecc_e31200_callout, sc);
 316 }
 317
 318 static void
 319 ecc_e31200_status(struct ecc_e31200_softc *sc)
 320 {
 321         device_t dev = sc->ecc_dev;
 322         uint16_t errsts;
 323
 324         errsts = pci_read_config(dev, PCI_E31200_ERRSTS, 2);
 325         if (errsts & PCI_E31200_ERRSTS_DMERR)
 326                 ecc_printf(sc, "Uncorrectable multilple-bit ECC error\n");
 327         else if (errsts & PCI_E31200_ERRSTS_DSERR)
 328                 ecc_printf(sc, "Correctable single-bit ECC error\n");
 329
 330         if (errsts & (PCI_E31200_ERRSTS_DSERR | PCI_E31200_ERRSTS_DMERR)) {
 331                 if (sc->ecc_addr != NULL)
 332                         ecc_e31200_errlog(sc);
 333
 334                 /* Clear pending errors */
 335                 pci_write_config(dev, PCI_E31200_ERRSTS, errsts, 2);
 336         }
 337 }
 338
 339 static void
 340 ecc_e31200_chaninfo(struct ecc_e31200_softc *sc, uint32_t dimm_ch,
 341     const char *desc)
 342 {
 343         int size_a, size_b, ecc;
 344
 345         size_a = __SHIFTOUT(dimm_ch, MCH_E31200_DIMM_A_SIZE);
 346         if (size_a != 0) {
 347                 ecc_printf(sc, "%s, DIMM A %dMB %s %s\n", desc,
 348                     size_a * MCH_E31200_DIMM_SIZE_UNIT,
 349                     (dimm_ch & MCH_E31200_DIMM_A_X16) ? "X16" : "X8",
 350                     (dimm_ch & MCH_E31200_DIMM_A_DUAL_RANK) ?
 351                         "DUAL" : "SINGLE");
 352         }
 353
 354         size_b = __SHIFTOUT(dimm_ch, MCH_E31200_DIMM_B_SIZE);
 355         if (size_b != 0) {
 356                 ecc_printf(sc, "%s, DIMM B %dMB %s %s\n", desc,
 357                     size_b * MCH_E31200_DIMM_SIZE_UNIT,
 358                     (dimm_ch & MCH_E31200_DIMM_B_X16) ? "X16" : "X8",
 359                     (dimm_ch & MCH_E31200_DIMM_B_DUAL_RANK) ?
 360                         "DUAL" : "SINGLE");
 361         }
 362
 363         if (size_a == 0 && size_b == 0)
 364                 return;
 365
 366         ecc = __SHIFTOUT(dimm_ch, MCH_E31200_DIMM_ECC);
 367         if (ecc == MCH_E31200_DIMM_ECC_NONE) {
 368                 ecc_printf(sc, "%s, no ECC active\n", desc);
 369         } else if (ecc == MCH_E31200_DIMM_ECC_ALL) {
 370                 ecc_printf(sc, "%s, ECC active IO/logic\n", desc);
 371         } else {
 372                 if (sc->ecc_ver == ECC_E31200_VER_1 ||
 373                     sc->ecc_ver == ECC_E31200_VER_2) {
 374                         if (ecc == MCH_E31200_DIMM_ECC_IO)
 375                                 ecc_printf(sc, "%s, ECC active IO\n", desc);
 376                         else
 377                                 ecc_printf(sc, "%s, ECC active logic\n", desc);
 378                 } else { /* V3 */
 379                         ecc_printf(sc, "%s, invalid ECC active 0x%x\n",
 380                             desc, ecc);
 381                 }
 382         }
 383
 384         if (sc->ecc_ver == ECC_E31200_VER_1 ||
 385             sc->ecc_ver == ECC_E31200_VER_2) {
 386                 /* This bit is V3 only */
 387                 dimm_ch &= ~MCH_E31200_DIMM_HORI;
 388         }
 389         if (dimm_ch & (MCH_E31200_DIMM_ENHI | MCH_E31200_DIMM_RI |
 390             MCH_E31200_DIMM_HORI)) {
 391                 ecc_printf(sc, "%s", desc);
 392                 if (dimm_ch & MCH_E31200_DIMM_RI)
 393                         kprintf(", rank interleave");
 394                 if (dimm_ch & MCH_E31200_DIMM_ENHI)
 395                         kprintf(", enhanced interleave");
 396                 if (dimm_ch & MCH_E31200_DIMM_HORI)
 397                         kprintf(", high order rank interleave");
 398                 kprintf("\n");
 399         }
 400 }
 401
 402 static void
 403 ecc_e31200_errlog(struct ecc_e31200_softc *sc)
 404 {
 405         ecc_e31200_errlog_ch(sc, MCH_E31200_ERRLOG0_C0, MCH_E31200_ERRLOG1_C0,
 406             "channel0");
 407         ecc_e31200_errlog_ch(sc, MCH_E31200_ERRLOG0_C1, MCH_E31200_ERRLOG1_C1,
 408             "channel1");
 409 }
 410
 411 static void
 412 ecc_e31200_errlog_ch(struct ecc_e31200_softc *sc,
 413     int err0_ofs, int err1_ofs, const char *desc)
 414 {
 415         uint32_t err0, err1;
 416
 417         err0 = CSR_READ_4(sc, err0_ofs);
 418         if ((err0 & (MCH_E31200_ERRLOG0_CERRSTS | MCH_E31200_ERRLOG0_MERRSTS))
 419             == 0)
 420                 return;
 421
 422         err1 = CSR_READ_4(sc, err1_ofs);
 423
 424         ecc_printf(sc, "%s error @bank %d, rank %d, chunk %d, syndrome %d, "
 425             "row %d, col %d\n", desc,
 426             __SHIFTOUT(err0, MCH_E31200_ERRLOG0_ERRBANK),
 427             __SHIFTOUT(err0, MCH_E31200_ERRLOG0_ERRRANK),
 428             __SHIFTOUT(err0, MCH_E31200_ERRLOG0_ERRCHUNK),
 429             __SHIFTOUT(err0, MCH_E31200_ERRLOG0_ERRSYND),
 430             __SHIFTOUT(err1, MCH_E31200_ERRLOG1_ERRROW),
 431             __SHIFTOUT(err1, MCH_E31200_ERRLOG1_ERRCOL));
 432 }
 433
 434 static int
 435 ecc_e31200_detach(device_t dev)
 436 {
 437         struct ecc_e31200_softc *sc = device_get_softc(dev);
 438
 439         callout_stop_sync(&sc->ecc_callout);
 440         if (sc->ecc_addr != NULL)
 441                 pmap_unmapdev((vm_offset_t)sc->ecc_addr, MCH_E31200_SIZE);
 442         return 0;
 443 }
 444
 445 static void
 446 ecc_e31200_shutdown(device_t dev)
 447 {
 448         struct ecc_e31200_softc *sc = device_get_softc(dev);
 449
 450         callout_stop_sync(&sc->ecc_callout);
 451 }