sys/dev/netif/bnx/if_bnx.c

   1 /*
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
  34  */
  35
  36 #include "opt_bnx.h"
  37 #include "opt_ifpoll.h"
  38
  39 #include <sys/param.h>
  40 #include <sys/bus.h>
  41 #include <sys/endian.h>
  42 #include <sys/kernel.h>
  43 #include <sys/interrupt.h>
  44 #include <sys/mbuf.h>
  45 #include <sys/malloc.h>
  46 #include <sys/queue.h>
  47 #include <sys/rman.h>
  48 #include <sys/serialize.h>
  49 #include <sys/socket.h>
  50 #include <sys/sockio.h>
  51 #include <sys/sysctl.h>
  52
  53 #include <netinet/ip.h>
  54 #include <netinet/tcp.h>
  55
  56 #include <net/bpf.h>
  57 #include <net/ethernet.h>
  58 #include <net/if.h>
  59 #include <net/if_arp.h>
  60 #include <net/if_dl.h>
  61 #include <net/if_media.h>
  62 #include <net/if_poll.h>
  63 #include <net/if_types.h>
  64 #include <net/ifq_var.h>
  65 #include <net/vlan/if_vlan_var.h>
  66 #include <net/vlan/if_vlan_ether.h>
  67
  68 #include <dev/netif/mii_layer/mii.h>
  69 #include <dev/netif/mii_layer/miivar.h>
  70 #include <dev/netif/mii_layer/brgphyreg.h>
  71
  72 #include <bus/pci/pcidevs.h>
  73 #include <bus/pci/pcireg.h>
  74 #include <bus/pci/pcivar.h>
  75
  76 #include <dev/netif/bge/if_bgereg.h>
  77 #include <dev/netif/bnx/if_bnxvar.h>
  78
  79 /* "device miibus" required.  See GENERIC if you get errors here. */
  80 #include "miibus_if.h"
  81
  82 #define BNX_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
  83
  84 #define BNX_INTR_CKINTVL        ((10 * hz) / 1000)      /* 10ms */
  85
  86 static const struct bnx_type {
  87         uint16_t                bnx_vid;
  88         uint16_t                bnx_did;
  89         char                    *bnx_name;
  90 } bnx_devs[] = {
  91         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717,
  92                 "Broadcom BCM5717 Gigabit Ethernet" },
  93         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5717C,
  94                 "Broadcom BCM5717C Gigabit Ethernet" },
  95         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5718,
  96                 "Broadcom BCM5718 Gigabit Ethernet" },
  97         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5719,
  98                 "Broadcom BCM5719 Gigabit Ethernet" },
  99         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720_ALT,
 100                 "Broadcom BCM5720 Gigabit Ethernet" },
 101
 102         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57761,
 103                 "Broadcom BCM57761 Gigabit Ethernet" },
 104         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57762,
 105                 "Broadcom BCM57762 Gigabit Ethernet" },
 106         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57765,
 107                 "Broadcom BCM57765 Gigabit Ethernet" },
 108         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57766,
 109                 "Broadcom BCM57766 Gigabit Ethernet" },
 110         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57781,
 111                 "Broadcom BCM57781 Gigabit Ethernet" },
 112         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57782,
 113                 "Broadcom BCM57782 Gigabit Ethernet" },
 114         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57785,
 115                 "Broadcom BCM57785 Gigabit Ethernet" },
 116         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57786,
 117                 "Broadcom BCM57786 Gigabit Ethernet" },
 118         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57791,
 119                 "Broadcom BCM57791 Fast Ethernet" },
 120         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57795,
 121                 "Broadcom BCM57795 Fast Ethernet" },
 122
 123         { 0, 0, NULL }
 124 };
 125
 126 #define BNX_IS_JUMBO_CAPABLE(sc)        ((sc)->bnx_flags & BNX_FLAG_JUMBO)
 127 #define BNX_IS_5717_PLUS(sc)            ((sc)->bnx_flags & BNX_FLAG_5717_PLUS)
 128 #define BNX_IS_57765_PLUS(sc)           ((sc)->bnx_flags & BNX_FLAG_57765_PLUS)
 129 #define BNX_IS_57765_FAMILY(sc)  \
 130         ((sc)->bnx_flags & BNX_FLAG_57765_FAMILY)
 131
 132 typedef int     (*bnx_eaddr_fcn_t)(struct bnx_softc *, uint8_t[]);
 133
 134 static int      bnx_probe(device_t);
 135 static int      bnx_attach(device_t);
 136 static int      bnx_detach(device_t);
 137 static void     bnx_shutdown(device_t);
 138 static int      bnx_suspend(device_t);
 139 static int      bnx_resume(device_t);
 140 static int      bnx_miibus_readreg(device_t, int, int);
 141 static int      bnx_miibus_writereg(device_t, int, int, int);
 142 static void     bnx_miibus_statchg(device_t);
 143
 144 #ifdef IFPOLL_ENABLE
 145 static void     bnx_npoll(struct ifnet *, struct ifpoll_info *);
 146 static void     bnx_npoll_compat(struct ifnet *, void *, int);
 147 #endif
 148 static void     bnx_intr_legacy(void *);
 149 static void     bnx_msi(void *);
 150 static void     bnx_msi_oneshot(void *);
 151 static void     bnx_intr(struct bnx_softc *);
 152 static void     bnx_enable_intr(struct bnx_softc *);
 153 static void     bnx_disable_intr(struct bnx_softc *);
 154 static void     bnx_txeof(struct bnx_softc *, uint16_t);
 155 static void     bnx_rxeof(struct bnx_softc *, uint16_t, int);
 156
 157 static void     bnx_start(struct ifnet *, struct ifaltq_subque *);
 158 static int      bnx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 159 static void     bnx_init(void *);
 160 static void     bnx_stop(struct bnx_softc *);
 161 static void     bnx_watchdog(struct ifnet *);
 162 static int      bnx_ifmedia_upd(struct ifnet *);
 163 static void     bnx_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 164 static void     bnx_tick(void *);
 165
 166 static int      bnx_alloc_jumbo_mem(struct bnx_softc *);
 167 static void     bnx_free_jumbo_mem(struct bnx_softc *);
 168 static struct bnx_jslot
 169                 *bnx_jalloc(struct bnx_softc *);
 170 static void     bnx_jfree(void *);
 171 static void     bnx_jref(void *);
 172 static int      bnx_newbuf_std(struct bnx_softc *, int, int);
 173 static int      bnx_newbuf_jumbo(struct bnx_softc *, int, int);
 174 static void     bnx_setup_rxdesc_std(struct bnx_softc *, int);
 175 static void     bnx_setup_rxdesc_jumbo(struct bnx_softc *, int);
 176 static int      bnx_init_rx_ring_std(struct bnx_softc *);
 177 static void     bnx_free_rx_ring_std(struct bnx_softc *);
 178 static int      bnx_init_rx_ring_jumbo(struct bnx_softc *);
 179 static void     bnx_free_rx_ring_jumbo(struct bnx_softc *);
 180 static void     bnx_free_tx_ring(struct bnx_softc *);
 181 static int      bnx_init_tx_ring(struct bnx_softc *);
 182 static int      bnx_dma_alloc(struct bnx_softc *);
 183 static void     bnx_dma_free(struct bnx_softc *);
 184 static int      bnx_dma_block_alloc(struct bnx_softc *, bus_size_t,
 185                     bus_dma_tag_t *, bus_dmamap_t *, void **, bus_addr_t *);
 186 static void     bnx_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
 187 static struct mbuf *
 188                 bnx_defrag_shortdma(struct mbuf *);
 189 static int      bnx_encap(struct bnx_softc *, struct mbuf **,
 190                         uint32_t *, int *);
 191 static int      bnx_setup_tso(struct bnx_softc *, struct mbuf **,
 192                     uint16_t *, uint16_t *);
 193
 194 static void     bnx_reset(struct bnx_softc *);
 195 static int      bnx_chipinit(struct bnx_softc *);
 196 static int      bnx_blockinit(struct bnx_softc *);
 197 static void     bnx_stop_block(struct bnx_softc *, bus_size_t, uint32_t);
 198 static void     bnx_enable_msi(struct bnx_softc *sc);
 199 static void     bnx_setmulti(struct bnx_softc *);
 200 static void     bnx_setpromisc(struct bnx_softc *);
 201 static void     bnx_stats_update_regs(struct bnx_softc *);
 202 static uint32_t bnx_dma_swap_options(struct bnx_softc *);
 203
 204 static uint32_t bnx_readmem_ind(struct bnx_softc *, uint32_t);
 205 static void     bnx_writemem_ind(struct bnx_softc *, uint32_t, uint32_t);
 206 #ifdef notdef
 207 static uint32_t bnx_readreg_ind(struct bnx_softc *, uint32_t);
 208 #endif
 209 static void     bnx_writereg_ind(struct bnx_softc *, uint32_t, uint32_t);
 210 static void     bnx_writemem_direct(struct bnx_softc *, uint32_t, uint32_t);
 211 static void     bnx_writembx(struct bnx_softc *, int, int);
 212 static uint8_t  bnx_nvram_getbyte(struct bnx_softc *, int, uint8_t *);
 213 static int      bnx_read_nvram(struct bnx_softc *, caddr_t, int, int);
 214 static uint8_t  bnx_eeprom_getbyte(struct bnx_softc *, uint32_t, uint8_t *);
 215 static int      bnx_read_eeprom(struct bnx_softc *, caddr_t, uint32_t, size_t);
 216
 217 static void     bnx_tbi_link_upd(struct bnx_softc *, uint32_t);
 218 static void     bnx_copper_link_upd(struct bnx_softc *, uint32_t);
 219 static void     bnx_autopoll_link_upd(struct bnx_softc *, uint32_t);
 220 static void     bnx_link_poll(struct bnx_softc *);
 221
 222 static int      bnx_get_eaddr_mem(struct bnx_softc *, uint8_t[]);
 223 static int      bnx_get_eaddr_nvram(struct bnx_softc *, uint8_t[]);
 224 static int      bnx_get_eaddr_eeprom(struct bnx_softc *, uint8_t[]);
 225 static int      bnx_get_eaddr(struct bnx_softc *, uint8_t[]);
 226
 227 static void     bnx_coal_change(struct bnx_softc *);
 228 static int      bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
 229 static int      bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
 230 static int      bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS);
 231 static int      bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS);
 232 static int      bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS);
 233 static int      bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS);
 234 static int      bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *,
 235                     int, int, uint32_t);
 236
 237 static int      bnx_msi_enable = 1;
 238 TUNABLE_INT("hw.bnx.msi.enable", &bnx_msi_enable);
 239
 240 static device_method_t bnx_methods[] = {
 241         /* Device interface */
 242         DEVMETHOD(device_probe,         bnx_probe),
 243         DEVMETHOD(device_attach,        bnx_attach),
 244         DEVMETHOD(device_detach,        bnx_detach),
 245         DEVMETHOD(device_shutdown,      bnx_shutdown),
 246         DEVMETHOD(device_suspend,       bnx_suspend),
 247         DEVMETHOD(device_resume,        bnx_resume),
 248
 249         /* bus interface */
 250         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 251         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 252
 253         /* MII interface */
 254         DEVMETHOD(miibus_readreg,       bnx_miibus_readreg),
 255         DEVMETHOD(miibus_writereg,      bnx_miibus_writereg),
 256         DEVMETHOD(miibus_statchg,       bnx_miibus_statchg),
 257
 258         { 0, 0 }
 259 };
 260
 261 static DEFINE_CLASS_0(bnx, bnx_driver, bnx_methods, sizeof(struct bnx_softc));
 262 static devclass_t bnx_devclass;
 263
 264 DECLARE_DUMMY_MODULE(if_bnx);
 265 DRIVER_MODULE(if_bnx, pci, bnx_driver, bnx_devclass, NULL, NULL);
 266 DRIVER_MODULE(miibus, bnx, miibus_driver, miibus_devclass, NULL, NULL);
 267
 268 static uint32_t
 269 bnx_readmem_ind(struct bnx_softc *sc, uint32_t off)
 270 {
 271         device_t dev = sc->bnx_dev;
 272         uint32_t val;
 273
 274         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906 &&
 275             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 276                 return 0;
 277
 278         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 279         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
 280         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 281         return (val);
 282 }
 283
 284 static void
 285 bnx_writemem_ind(struct bnx_softc *sc, uint32_t off, uint32_t val)
 286 {
 287         device_t dev = sc->bnx_dev;
 288
 289         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906 &&
 290             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
 291                 return;
 292
 293         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 294         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 295         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
 296 }
 297
 298 #ifdef notdef
 299 static uint32_t
 300 bnx_readreg_ind(struct bnx_softc *sc, uin32_t off)
 301 {
 302         device_t dev = sc->bnx_dev;
 303
 304         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 305         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 306 }
 307 #endif
 308
 309 static void
 310 bnx_writereg_ind(struct bnx_softc *sc, uint32_t off, uint32_t val)
 311 {
 312         device_t dev = sc->bnx_dev;
 313
 314         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 315         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 316 }
 317
 318 static void
 319 bnx_writemem_direct(struct bnx_softc *sc, uint32_t off, uint32_t val)
 320 {
 321         CSR_WRITE_4(sc, off, val);
 322 }
 323
 324 static void
 325 bnx_writembx(struct bnx_softc *sc, int off, int val)
 326 {
 327         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906)
 328                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
 329
 330         CSR_WRITE_4(sc, off, val);
 331 }
 332
 333 static uint8_t
 334 bnx_nvram_getbyte(struct bnx_softc *sc, int addr, uint8_t *dest)
 335 {
 336         uint32_t access, byte = 0;
 337         int i;
 338
 339         /* Lock. */
 340         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
 341         for (i = 0; i < 8000; i++) {
 342                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
 343                         break;
 344                 DELAY(20);
 345         }
 346         if (i == 8000)
 347                 return (1);
 348
 349         /* Enable access. */
 350         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
 351         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
 352
 353         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
 354         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
 355         for (i = 0; i < BNX_TIMEOUT * 10; i++) {
 356                 DELAY(10);
 357                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
 358                         DELAY(10);
 359                         break;
 360                 }
 361         }
 362
 363         if (i == BNX_TIMEOUT * 10) {
 364                 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n");
 365                 return (1);
 366         }
 367
 368         /* Get result. */
 369         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
 370
 371         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
 372
 373         /* Disable access. */
 374         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
 375
 376         /* Unlock. */
 377         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
 378         CSR_READ_4(sc, BGE_NVRAM_SWARB);
 379
 380         return (0);
 381 }
 382
 383 /*
 384  * Read a sequence of bytes from NVRAM.
 385  */
 386 static int
 387 bnx_read_nvram(struct bnx_softc *sc, caddr_t dest, int off, int cnt)
 388 {
 389         int err = 0, i;
 390         uint8_t byte = 0;
 391
 392         if (sc->bnx_asicrev != BGE_ASICREV_BCM5906)
 393                 return (1);
 394
 395         for (i = 0; i < cnt; i++) {
 396                 err = bnx_nvram_getbyte(sc, off + i, &byte);
 397                 if (err)
 398                         break;
 399                 *(dest + i) = byte;
 400         }
 401
 402         return (err ? 1 : 0);
 403 }
 404
 405 /*
 406  * Read a byte of data stored in the EEPROM at address 'addr.' The
 407  * BCM570x supports both the traditional bitbang interface and an
 408  * auto access interface for reading the EEPROM. We use the auto
 409  * access method.
 410  */
 411 static uint8_t
 412 bnx_eeprom_getbyte(struct bnx_softc *sc, uint32_t addr, uint8_t *dest)
 413 {
 414         int i;
 415         uint32_t byte = 0;
 416
 417         /*
 418          * Enable use of auto EEPROM access so we can avoid
 419          * having to use the bitbang method.
 420          */
 421         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 422
 423         /* Reset the EEPROM, load the clock period. */
 424         CSR_WRITE_4(sc, BGE_EE_ADDR,
 425             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 426         DELAY(20);
 427
 428         /* Issue the read EEPROM command. */
 429         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 430
 431         /* Wait for completion */
 432         for(i = 0; i < BNX_TIMEOUT * 10; i++) {
 433                 DELAY(10);
 434                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 435                         break;
 436         }
 437
 438         if (i == BNX_TIMEOUT) {
 439                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
 440                 return(1);
 441         }
 442
 443         /* Get result. */
 444         byte = CSR_READ_4(sc, BGE_EE_DATA);
 445
 446         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 447
 448         return(0);
 449 }
 450
 451 /*
 452  * Read a sequence of bytes from the EEPROM.
 453  */
 454 static int
 455 bnx_read_eeprom(struct bnx_softc *sc, caddr_t dest, uint32_t off, size_t len)
 456 {
 457         size_t i;
 458         int err;
 459         uint8_t byte;
 460
 461         for (byte = 0, err = 0, i = 0; i < len; i++) {
 462                 err = bnx_eeprom_getbyte(sc, off + i, &byte);
 463                 if (err)
 464                         break;
 465                 *(dest + i) = byte;
 466         }
 467
 468         return(err ? 1 : 0);
 469 }
 470
 471 static int
 472 bnx_miibus_readreg(device_t dev, int phy, int reg)
 473 {
 474         struct bnx_softc *sc = device_get_softc(dev);
 475         uint32_t val;
 476         int i;
 477
 478         KASSERT(phy == sc->bnx_phyno,
 479             ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
 480
 481         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 482         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 483                 CSR_WRITE_4(sc, BGE_MI_MODE,
 484                     sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 485                 DELAY(80);
 486         }
 487
 488         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
 489             BGE_MIPHY(phy) | BGE_MIREG(reg));
 490
 491         /* Poll for the PHY register access to complete. */
 492         for (i = 0; i < BNX_TIMEOUT; i++) {
 493                 DELAY(10);
 494                 val = CSR_READ_4(sc, BGE_MI_COMM);
 495                 if ((val & BGE_MICOMM_BUSY) == 0) {
 496                         DELAY(5);
 497                         val = CSR_READ_4(sc, BGE_MI_COMM);
 498                         break;
 499                 }
 500         }
 501         if (i == BNX_TIMEOUT) {
 502                 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
 503                     "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
 504                 val = 0;
 505         }
 506
 507         /* Restore the autopoll bit if necessary. */
 508         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 509                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
 510                 DELAY(80);
 511         }
 512
 513         if (val & BGE_MICOMM_READFAIL)
 514                 return 0;
 515
 516         return (val & 0xFFFF);
 517 }
 518
 519 static int
 520 bnx_miibus_writereg(device_t dev, int phy, int reg, int val)
 521 {
 522         struct bnx_softc *sc = device_get_softc(dev);
 523         int i;
 524
 525         KASSERT(phy == sc->bnx_phyno,
 526             ("invalid phyno %d, should be %d", phy, sc->bnx_phyno));
 527
 528         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906 &&
 529             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
 530                return 0;
 531
 532         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
 533         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 534                 CSR_WRITE_4(sc, BGE_MI_MODE,
 535                     sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
 536                 DELAY(80);
 537         }
 538
 539         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
 540             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
 541
 542         for (i = 0; i < BNX_TIMEOUT; i++) {
 543                 DELAY(10);
 544                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
 545                         DELAY(5);
 546                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
 547                         break;
 548                 }
 549         }
 550         if (i == BNX_TIMEOUT) {
 551                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
 552                     "(phy %d, reg %d, val %d)\n", phy, reg, val);
 553         }
 554
 555         /* Restore the autopoll bit if necessary. */
 556         if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
 557                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
 558                 DELAY(80);
 559         }
 560
 561         return 0;
 562 }
 563
 564 static void
 565 bnx_miibus_statchg(device_t dev)
 566 {
 567         struct bnx_softc *sc;
 568         struct mii_data *mii;
 569
 570         sc = device_get_softc(dev);
 571         mii = device_get_softc(sc->bnx_miibus);
 572
 573         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
 574             (IFM_ACTIVE | IFM_AVALID)) {
 575                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
 576                 case IFM_10_T:
 577                 case IFM_100_TX:
 578                         sc->bnx_link = 1;
 579                         break;
 580                 case IFM_1000_T:
 581                 case IFM_1000_SX:
 582                 case IFM_2500_SX:
 583                         if (sc->bnx_asicrev != BGE_ASICREV_BCM5906)
 584                                 sc->bnx_link = 1;
 585                         else
 586                                 sc->bnx_link = 0;
 587                         break;
 588                 default:
 589                         sc->bnx_link = 0;
 590                         break;
 591                 }
 592         } else {
 593                 sc->bnx_link = 0;
 594         }
 595         if (sc->bnx_link == 0)
 596                 return;
 597
 598         BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 599         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
 600             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
 601                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 602         } else {
 603                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 604         }
 605
 606         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 607                 BNX_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 608         } else {
 609                 BNX_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 610         }
 611 }
 612
 613 /*
 614  * Memory management for jumbo frames.
 615  */
 616 static int
 617 bnx_alloc_jumbo_mem(struct bnx_softc *sc)
 618 {
 619         struct ifnet *ifp = &sc->arpcom.ac_if;
 620         struct bnx_jslot *entry;
 621         uint8_t *ptr;
 622         bus_addr_t paddr;
 623         int i, error;
 624
 625         /*
 626          * Create tag for jumbo mbufs.
 627          * This is really a bit of a kludge. We allocate a special
 628          * jumbo buffer pool which (thanks to the way our DMA
 629          * memory allocation works) will consist of contiguous
 630          * pages. This means that even though a jumbo buffer might
 631          * be larger than a page size, we don't really need to
 632          * map it into more than one DMA segment. However, the
 633          * default mbuf tag will result in multi-segment mappings,
 634          * so we have to create a special jumbo mbuf tag that
 635          * lets us get away with mapping the jumbo buffers as
 636          * a single segment. I think eventually the driver should
 637          * be changed so that it uses ordinary mbufs and cluster
 638          * buffers, i.e. jumbo frames can span multiple DMA
 639          * descriptors. But that's a project for another day.
 640          */
 641
 642         /*
 643          * Create DMA stuffs for jumbo RX ring.
 644          */
 645         error = bnx_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
 646                                     &sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
 647                                     &sc->bnx_cdata.bnx_rx_jumbo_ring_map,
 648                                     (void *)&sc->bnx_ldata.bnx_rx_jumbo_ring,
 649                                     &sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
 650         if (error) {
 651                 if_printf(ifp, "could not create jumbo RX ring\n");
 652                 return error;
 653         }
 654
 655         /*
 656          * Create DMA stuffs for jumbo buffer block.
 657          */
 658         error = bnx_dma_block_alloc(sc, BNX_JMEM,
 659                                     &sc->bnx_cdata.bnx_jumbo_tag,
 660                                     &sc->bnx_cdata.bnx_jumbo_map,
 661                                     (void **)&sc->bnx_ldata.bnx_jumbo_buf,
 662                                     &paddr);
 663         if (error) {
 664                 if_printf(ifp, "could not create jumbo buffer\n");
 665                 return error;
 666         }
 667
 668         SLIST_INIT(&sc->bnx_jfree_listhead);
 669
 670         /*
 671          * Now divide it up into 9K pieces and save the addresses
 672          * in an array. Note that we play an evil trick here by using
 673          * the first few bytes in the buffer to hold the the address
 674          * of the softc structure for this interface. This is because
 675          * bnx_jfree() needs it, but it is called by the mbuf management
 676          * code which will not pass it to us explicitly.
 677          */
 678         for (i = 0, ptr = sc->bnx_ldata.bnx_jumbo_buf; i < BNX_JSLOTS; i++) {
 679                 entry = &sc->bnx_cdata.bnx_jslots[i];
 680                 entry->bnx_sc = sc;
 681                 entry->bnx_buf = ptr;
 682                 entry->bnx_paddr = paddr;
 683                 entry->bnx_inuse = 0;
 684                 entry->bnx_slot = i;
 685                 SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead, entry, jslot_link);
 686
 687                 ptr += BNX_JLEN;
 688                 paddr += BNX_JLEN;
 689         }
 690         return 0;
 691 }
 692
 693 static void
 694 bnx_free_jumbo_mem(struct bnx_softc *sc)
 695 {
 696         /* Destroy jumbo RX ring. */
 697         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_jumbo_ring_tag,
 698                            sc->bnx_cdata.bnx_rx_jumbo_ring_map,
 699                            sc->bnx_ldata.bnx_rx_jumbo_ring);
 700
 701         /* Destroy jumbo buffer block. */
 702         bnx_dma_block_free(sc->bnx_cdata.bnx_jumbo_tag,
 703                            sc->bnx_cdata.bnx_jumbo_map,
 704                            sc->bnx_ldata.bnx_jumbo_buf);
 705 }
 706
 707 /*
 708  * Allocate a jumbo buffer.
 709  */
 710 static struct bnx_jslot *
 711 bnx_jalloc(struct bnx_softc *sc)
 712 {
 713         struct bnx_jslot *entry;
 714
 715         lwkt_serialize_enter(&sc->bnx_jslot_serializer);
 716         entry = SLIST_FIRST(&sc->bnx_jfree_listhead);
 717         if (entry) {
 718                 SLIST_REMOVE_HEAD(&sc->bnx_jfree_listhead, jslot_link);
 719                 entry->bnx_inuse = 1;
 720         } else {
 721                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
 722         }
 723         lwkt_serialize_exit(&sc->bnx_jslot_serializer);
 724         return(entry);
 725 }
 726
 727 /*
 728  * Adjust usage count on a jumbo buffer.
 729  */
 730 static void
 731 bnx_jref(void *arg)
 732 {
 733         struct bnx_jslot *entry = (struct bnx_jslot *)arg;
 734         struct bnx_softc *sc = entry->bnx_sc;
 735
 736         if (sc == NULL)
 737                 panic("bnx_jref: can't find softc pointer!");
 738
 739         if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
 740                 panic("bnx_jref: asked to reference buffer "
 741                     "that we don't manage!");
 742         } else if (entry->bnx_inuse == 0) {
 743                 panic("bnx_jref: buffer already free!");
 744         } else {
 745                 atomic_add_int(&entry->bnx_inuse, 1);
 746         }
 747 }
 748
 749 /*
 750  * Release a jumbo buffer.
 751  */
 752 static void
 753 bnx_jfree(void *arg)
 754 {
 755         struct bnx_jslot *entry = (struct bnx_jslot *)arg;
 756         struct bnx_softc *sc = entry->bnx_sc;
 757
 758         if (sc == NULL)
 759                 panic("bnx_jfree: can't find softc pointer!");
 760
 761         if (&sc->bnx_cdata.bnx_jslots[entry->bnx_slot] != entry) {
 762                 panic("bnx_jfree: asked to free buffer that we don't manage!");
 763         } else if (entry->bnx_inuse == 0) {
 764                 panic("bnx_jfree: buffer already free!");
 765         } else {
 766                 /*
 767                  * Possible MP race to 0, use the serializer.  The atomic insn
 768                  * is still needed for races against bnx_jref().
 769                  */
 770                 lwkt_serialize_enter(&sc->bnx_jslot_serializer);
 771                 atomic_subtract_int(&entry->bnx_inuse, 1);
 772                 if (entry->bnx_inuse == 0) {
 773                         SLIST_INSERT_HEAD(&sc->bnx_jfree_listhead,
 774                                           entry, jslot_link);
 775                 }
 776                 lwkt_serialize_exit(&sc->bnx_jslot_serializer);
 777         }
 778 }
 779
 780
 781 /*
 782  * Intialize a standard receive ring descriptor.
 783  */
 784 static int
 785 bnx_newbuf_std(struct bnx_softc *sc, int i, int init)
 786 {
 787         struct mbuf *m_new = NULL;
 788         bus_dma_segment_t seg;
 789         bus_dmamap_t map;
 790         int error, nsegs;
 791
 792         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
 793         if (m_new == NULL)
 794                 return ENOBUFS;
 795         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 796         m_adj(m_new, ETHER_ALIGN);
 797
 798         error = bus_dmamap_load_mbuf_segment(sc->bnx_cdata.bnx_rx_mtag,
 799                         sc->bnx_cdata.bnx_rx_tmpmap, m_new,
 800                         &seg, 1, &nsegs, BUS_DMA_NOWAIT);
 801         if (error) {
 802                 m_freem(m_new);
 803                 return error;
 804         }
 805
 806         if (!init) {
 807                 bus_dmamap_sync(sc->bnx_cdata.bnx_rx_mtag,
 808                                 sc->bnx_cdata.bnx_rx_std_dmamap[i],
 809                                 BUS_DMASYNC_POSTREAD);
 810                 bus_dmamap_unload(sc->bnx_cdata.bnx_rx_mtag,
 811                         sc->bnx_cdata.bnx_rx_std_dmamap[i]);
 812         }
 813
 814         map = sc->bnx_cdata.bnx_rx_tmpmap;
 815         sc->bnx_cdata.bnx_rx_tmpmap = sc->bnx_cdata.bnx_rx_std_dmamap[i];
 816         sc->bnx_cdata.bnx_rx_std_dmamap[i] = map;
 817
 818         sc->bnx_cdata.bnx_rx_std_chain[i].bnx_mbuf = m_new;
 819         sc->bnx_cdata.bnx_rx_std_chain[i].bnx_paddr = seg.ds_addr;
 820
 821         bnx_setup_rxdesc_std(sc, i);
 822         return 0;
 823 }
 824
 825 static void
 826 bnx_setup_rxdesc_std(struct bnx_softc *sc, int i)
 827 {
 828         struct bnx_rxchain *rc;
 829         struct bge_rx_bd *r;
 830
 831         rc = &sc->bnx_cdata.bnx_rx_std_chain[i];
 832         r = &sc->bnx_ldata.bnx_rx_std_ring[i];
 833
 834         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bnx_paddr);
 835         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bnx_paddr);
 836         r->bge_len = rc->bnx_mbuf->m_len;
 837         r->bge_idx = i;
 838         r->bge_flags = BGE_RXBDFLAG_END;
 839 }
 840
 841 /*
 842  * Initialize a jumbo receive ring descriptor. This allocates
 843  * a jumbo buffer from the pool managed internally by the driver.
 844  */
 845 static int
 846 bnx_newbuf_jumbo(struct bnx_softc *sc, int i, int init)
 847 {
 848         struct mbuf *m_new = NULL;
 849         struct bnx_jslot *buf;
 850         bus_addr_t paddr;
 851
 852         /* Allocate the mbuf. */
 853         MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
 854         if (m_new == NULL)
 855                 return ENOBUFS;
 856
 857         /* Allocate the jumbo buffer */
 858         buf = bnx_jalloc(sc);
 859         if (buf == NULL) {
 860                 m_freem(m_new);
 861                 return ENOBUFS;
 862         }
 863
 864         /* Attach the buffer to the mbuf. */
 865         m_new->m_ext.ext_arg = buf;
 866         m_new->m_ext.ext_buf = buf->bnx_buf;
 867         m_new->m_ext.ext_free = bnx_jfree;
 868         m_new->m_ext.ext_ref = bnx_jref;
 869         m_new->m_ext.ext_size = BNX_JUMBO_FRAMELEN;
 870
 871         m_new->m_flags |= M_EXT;
 872
 873         m_new->m_data = m_new->m_ext.ext_buf;
 874         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
 875
 876         paddr = buf->bnx_paddr;
 877         m_adj(m_new, ETHER_ALIGN);
 878         paddr += ETHER_ALIGN;
 879
 880         /* Save necessary information */
 881         sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_mbuf = m_new;
 882         sc->bnx_cdata.bnx_rx_jumbo_chain[i].bnx_paddr = paddr;
 883
 884         /* Set up the descriptor. */
 885         bnx_setup_rxdesc_jumbo(sc, i);
 886         return 0;
 887 }
 888
 889 static void
 890 bnx_setup_rxdesc_jumbo(struct bnx_softc *sc, int i)
 891 {
 892         struct bge_rx_bd *r;
 893         struct bnx_rxchain *rc;
 894
 895         r = &sc->bnx_ldata.bnx_rx_jumbo_ring[i];
 896         rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
 897
 898         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bnx_paddr);
 899         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bnx_paddr);
 900         r->bge_len = rc->bnx_mbuf->m_len;
 901         r->bge_idx = i;
 902         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
 903 }
 904
 905 static int
 906 bnx_init_rx_ring_std(struct bnx_softc *sc)
 907 {
 908         int i, error;
 909
 910         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 911                 error = bnx_newbuf_std(sc, i, 1);
 912                 if (error)
 913                         return error;
 914         }
 915
 916         sc->bnx_std = BGE_STD_RX_RING_CNT - 1;
 917         bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bnx_std);
 918
 919         return(0);
 920 }
 921
 922 static void
 923 bnx_free_rx_ring_std(struct bnx_softc *sc)
 924 {
 925         int i;
 926
 927         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 928                 struct bnx_rxchain *rc = &sc->bnx_cdata.bnx_rx_std_chain[i];
 929
 930                 if (rc->bnx_mbuf != NULL) {
 931                         bus_dmamap_unload(sc->bnx_cdata.bnx_rx_mtag,
 932                                           sc->bnx_cdata.bnx_rx_std_dmamap[i]);
 933                         m_freem(rc->bnx_mbuf);
 934                         rc->bnx_mbuf = NULL;
 935                 }
 936                 bzero(&sc->bnx_ldata.bnx_rx_std_ring[i],
 937                     sizeof(struct bge_rx_bd));
 938         }
 939 }
 940
 941 static int
 942 bnx_init_rx_ring_jumbo(struct bnx_softc *sc)
 943 {
 944         struct bge_rcb *rcb;
 945         int i, error;
 946
 947         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 948                 error = bnx_newbuf_jumbo(sc, i, 1);
 949                 if (error)
 950                         return error;
 951         }
 952
 953         sc->bnx_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
 954
 955         rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
 956         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
 957         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
 958
 959         bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
 960
 961         return(0);
 962 }
 963
 964 static void
 965 bnx_free_rx_ring_jumbo(struct bnx_softc *sc)
 966 {
 967         int i;
 968
 969         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 970                 struct bnx_rxchain *rc = &sc->bnx_cdata.bnx_rx_jumbo_chain[i];
 971
 972                 if (rc->bnx_mbuf != NULL) {
 973                         m_freem(rc->bnx_mbuf);
 974                         rc->bnx_mbuf = NULL;
 975                 }
 976                 bzero(&sc->bnx_ldata.bnx_rx_jumbo_ring[i],
 977                     sizeof(struct bge_rx_bd));
 978         }
 979 }
 980
 981 static void
 982 bnx_free_tx_ring(struct bnx_softc *sc)
 983 {
 984         int i;
 985
 986         for (i = 0; i < BGE_TX_RING_CNT; i++) {
 987                 if (sc->bnx_cdata.bnx_tx_chain[i] != NULL) {
 988                         bus_dmamap_unload(sc->bnx_cdata.bnx_tx_mtag,
 989                                           sc->bnx_cdata.bnx_tx_dmamap[i]);
 990                         m_freem(sc->bnx_cdata.bnx_tx_chain[i]);
 991                         sc->bnx_cdata.bnx_tx_chain[i] = NULL;
 992                 }
 993                 bzero(&sc->bnx_ldata.bnx_tx_ring[i],
 994                     sizeof(struct bge_tx_bd));
 995         }
 996 }
 997
 998 static int
 999 bnx_init_tx_ring(struct bnx_softc *sc)
1000 {
1001         sc->bnx_txcnt = 0;
1002         sc->bnx_tx_saved_considx = 0;
1003         sc->bnx_tx_prodidx = 0;
1004
1005         /* Initialize transmit producer index for host-memory send ring. */
1006         bnx_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bnx_tx_prodidx);
1007         bnx_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1008
1009         return(0);
1010 }
1011
1012 static void
1013 bnx_setmulti(struct bnx_softc *sc)
1014 {
1015         struct ifnet *ifp;
1016         struct ifmultiaddr *ifma;
1017         uint32_t hashes[4] = { 0, 0, 0, 0 };
1018         int h, i;
1019
1020         ifp = &sc->arpcom.ac_if;
1021
1022         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1023                 for (i = 0; i < 4; i++)
1024                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1025                 return;
1026         }
1027
1028         /* First, zot all the existing filters. */
1029         for (i = 0; i < 4; i++)
1030                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1031
1032         /* Now program new ones. */
1033         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1034                 if (ifma->ifma_addr->sa_family != AF_LINK)
1035                         continue;
1036                 h = ether_crc32_le(
1037                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1038                     ETHER_ADDR_LEN) & 0x7f;
1039                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1040         }
1041
1042         for (i = 0; i < 4; i++)
1043                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1044 }
1045
1046 /*
1047  * Do endian, PCI and DMA initialization. Also check the on-board ROM
1048  * self-test results.
1049  */
1050 static int
1051 bnx_chipinit(struct bnx_softc *sc)
1052 {
1053         uint32_t dma_rw_ctl, mode_ctl;
1054         int i;
1055
1056         /* Set endian type before we access any non-PCI registers. */
1057         pci_write_config(sc->bnx_dev, BGE_PCI_MISC_CTL,
1058             BGE_INIT | BGE_PCIMISCCTL_TAGGED_STATUS, 4);
1059
1060         /* Clear the MAC control register */
1061         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1062
1063         /*
1064          * Clear the MAC statistics block in the NIC's
1065          * internal memory.
1066          */
1067         for (i = BGE_STATS_BLOCK;
1068             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1069                 BNX_MEMWIN_WRITE(sc, i, 0);
1070
1071         for (i = BGE_STATUS_BLOCK;
1072             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1073                 BNX_MEMWIN_WRITE(sc, i, 0);
1074
1075         if (BNX_IS_57765_FAMILY(sc)) {
1076                 uint32_t val;
1077
1078                 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0) {
1079                         mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
1080                         val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
1081
1082                         /* Access the lower 1K of PL PCI-E block registers. */
1083                         CSR_WRITE_4(sc, BGE_MODE_CTL,
1084                             val | BGE_MODECTL_PCIE_PL_SEL);
1085
1086                         val = CSR_READ_4(sc, BGE_PCIE_PL_LO_PHYCTL5);
1087                         val |= BGE_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ;
1088                         CSR_WRITE_4(sc, BGE_PCIE_PL_LO_PHYCTL5, val);
1089
1090                         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1091                 }
1092                 if (sc->bnx_chiprev != BGE_CHIPREV_57765_AX) {
1093                         mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
1094                         val = mode_ctl & ~BGE_MODECTL_PCIE_PORTS;
1095
1096                         /* Access the lower 1K of DL PCI-E block registers. */
1097                         CSR_WRITE_4(sc, BGE_MODE_CTL,
1098                             val | BGE_MODECTL_PCIE_DL_SEL);
1099
1100                         val = CSR_READ_4(sc, BGE_PCIE_DL_LO_FTSMAX);
1101                         val &= ~BGE_PCIE_DL_LO_FTSMAX_MASK;
1102                         val |= BGE_PCIE_DL_LO_FTSMAX_VAL;
1103                         CSR_WRITE_4(sc, BGE_PCIE_DL_LO_FTSMAX, val);
1104
1105                         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1106                 }
1107
1108                 val = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK);
1109                 val &= ~BGE_CPMU_LSPD_10MB_MACCLK_MASK;
1110                 val |= BGE_CPMU_LSPD_10MB_MACCLK_6_25;
1111                 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, val);
1112         }
1113
1114         /*
1115          * Set up the PCI DMA control register.
1116          */
1117         dma_rw_ctl = pci_read_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, 4);
1118         /*
1119          * Disable 32bytes cache alignment for DMA write to host memory
1120          *
1121          * NOTE:
1122          * 64bytes cache alignment for DMA write to host memory is still
1123          * enabled.
1124          */
1125         dma_rw_ctl |= BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1126         if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
1127                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1128         /*
1129          * Enable HW workaround for controllers that misinterpret
1130          * a status tag update and leave interrupts permanently
1131          * disabled.
1132          */
1133         if (sc->bnx_asicrev != BGE_ASICREV_BCM5717 &&
1134             !BNX_IS_57765_FAMILY(sc))
1135                 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1136         if (bootverbose) {
1137                 if_printf(&sc->arpcom.ac_if, "DMA read/write %#x\n",
1138                     dma_rw_ctl);
1139         }
1140         pci_write_config(sc->bnx_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1141
1142         /*
1143          * Set up general mode register.
1144          */
1145         mode_ctl = bnx_dma_swap_options(sc) | BGE_MODECTL_MAC_ATTN_INTR |
1146             BGE_MODECTL_HOST_SEND_BDS | BGE_MODECTL_TX_NO_PHDR_CSUM;
1147         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1148
1149         /*
1150          * Disable memory write invalidate.  Apparently it is not supported
1151          * properly by these devices.  Also ensure that INTx isn't disabled,
1152          * as these chips need it even when using MSI.
1153          */
1154         PCI_CLRBIT(sc->bnx_dev, BGE_PCI_CMD,
1155             (PCIM_CMD_MWRICEN | PCIM_CMD_INTxDIS), 4);
1156
1157         /* Set the timer prescaler (always 66Mhz) */
1158         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1159
1160         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
1161                 DELAY(40);      /* XXX */
1162
1163                 /* Put PHY into ready state */
1164                 BNX_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1165                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1166                 DELAY(40);
1167         }
1168
1169         return(0);
1170 }
1171
1172 static int
1173 bnx_blockinit(struct bnx_softc *sc)
1174 {
1175         struct bge_rcb *rcb;
1176         bus_size_t vrcb;
1177         bge_hostaddr taddr;
1178         uint32_t val;
1179         int i, limit;
1180
1181         /*
1182          * Initialize the memory window pointer register so that
1183          * we can access the first 32K of internal NIC RAM. This will
1184          * allow us to set up the TX send ring RCBs and the RX return
1185          * ring RCBs, plus other things which live in NIC memory.
1186          */
1187         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1188
1189         /* Configure mbuf pool watermarks */
1190         if (BNX_IS_57765_PLUS(sc)) {
1191                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1192                 if (sc->arpcom.ac_if.if_mtu > ETHERMTU) {
1193                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1194                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1195                 } else {
1196                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1197                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1198                 }
1199         } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
1200                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1201                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1202                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1203         } else {
1204                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1205                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1206                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1207         }
1208
1209         /* Configure DMA resource watermarks */
1210         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1211         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1212
1213         /* Enable buffer manager */
1214         val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
1215         /*
1216          * Change the arbitration algorithm of TXMBUF read request to
1217          * round-robin instead of priority based for BCM5719.  When
1218          * TXFIFO is almost empty, RDMA will hold its request until
1219          * TXFIFO is not almost empty.
1220          */
1221         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719)
1222                 val |= BGE_BMANMODE_NO_TX_UNDERRUN;
1223         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1224             sc->bnx_chipid == BGE_CHIPID_BCM5719_A0 ||
1225             sc->bnx_chipid == BGE_CHIPID_BCM5720_A0)
1226                 val |= BGE_BMANMODE_LOMBUF_ATTN;
1227         CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
1228
1229         /* Poll for buffer manager start indication */
1230         for (i = 0; i < BNX_TIMEOUT; i++) {
1231                 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1232                         break;
1233                 DELAY(10);
1234         }
1235
1236         if (i == BNX_TIMEOUT) {
1237                 if_printf(&sc->arpcom.ac_if,
1238                           "buffer manager failed to start\n");
1239                 return(ENXIO);
1240         }
1241
1242         /* Enable flow-through queues */
1243         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1244         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1245
1246         /* Wait until queue initialization is complete */
1247         for (i = 0; i < BNX_TIMEOUT; i++) {
1248                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1249                         break;
1250                 DELAY(10);
1251         }
1252
1253         if (i == BNX_TIMEOUT) {
1254                 if_printf(&sc->arpcom.ac_if,
1255                           "flow-through queue init failed\n");
1256                 return(ENXIO);
1257         }
1258
1259         /*
1260          * Summary of rings supported by the controller:
1261          *
1262          * Standard Receive Producer Ring
1263          * - This ring is used to feed receive buffers for "standard"
1264          *   sized frames (typically 1536 bytes) to the controller.
1265          *
1266          * Jumbo Receive Producer Ring
1267          * - This ring is used to feed receive buffers for jumbo sized
1268          *   frames (i.e. anything bigger than the "standard" frames)
1269          *   to the controller.
1270          *
1271          * Mini Receive Producer Ring
1272          * - This ring is used to feed receive buffers for "mini"
1273          *   sized frames to the controller.
1274          * - This feature required external memory for the controller
1275          *   but was never used in a production system.  Should always
1276          *   be disabled.
1277          *
1278          * Receive Return Ring
1279          * - After the controller has placed an incoming frame into a
1280          *   receive buffer that buffer is moved into a receive return
1281          *   ring.  The driver is then responsible to passing the
1282          *   buffer up to the stack.  Many versions of the controller
1283          *   support multiple RR rings.
1284          *
1285          * Send Ring
1286          * - This ring is used for outgoing frames.  Many versions of
1287          *   the controller support multiple send rings.
1288          */
1289
1290         /* Initialize the standard receive producer ring control block. */
1291         rcb = &sc->bnx_ldata.bnx_info.bnx_std_rx_rcb;
1292         rcb->bge_hostaddr.bge_addr_lo =
1293             BGE_ADDR_LO(sc->bnx_ldata.bnx_rx_std_ring_paddr);
1294         rcb->bge_hostaddr.bge_addr_hi =
1295             BGE_ADDR_HI(sc->bnx_ldata.bnx_rx_std_ring_paddr);
1296         if (BNX_IS_57765_PLUS(sc)) {
1297                 /*
1298                  * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
1299                  * Bits 15-2 : Maximum RX frame size
1300                  * Bit 1     : 1 = Ring Disabled, 0 = Ring ENabled
1301                  * Bit 0     : Reserved
1302                  */
1303                 rcb->bge_maxlen_flags =
1304                     BGE_RCB_MAXLEN_FLAGS(512, BNX_MAX_FRAMELEN << 2);
1305         } else {
1306                 /*
1307                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
1308                  * Bits 15-2 : Reserved (should be 0)
1309                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
1310                  * Bit 0     : Reserved
1311                  */
1312                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1313         }
1314         if (BNX_IS_5717_PLUS(sc))
1315                 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
1316         else
1317                 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1318         /* Write the standard receive producer ring control block. */
1319         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1320         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1321         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1322         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1323         /* Reset the standard receive producer ring producer index. */
1324         bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1325
1326         /*
1327          * Initialize the jumbo RX producer ring control
1328          * block.  We set the 'ring disabled' bit in the
1329          * flags field until we're actually ready to start
1330          * using this ring (i.e. once we set the MTU
1331          * high enough to require it).
1332          */
1333         if (BNX_IS_JUMBO_CAPABLE(sc)) {
1334                 rcb = &sc->bnx_ldata.bnx_info.bnx_jumbo_rx_rcb;
1335                 /* Get the jumbo receive producer ring RCB parameters. */
1336                 rcb->bge_hostaddr.bge_addr_lo =
1337                     BGE_ADDR_LO(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1338                 rcb->bge_hostaddr.bge_addr_hi =
1339                     BGE_ADDR_HI(sc->bnx_ldata.bnx_rx_jumbo_ring_paddr);
1340                 rcb->bge_maxlen_flags =
1341                     BGE_RCB_MAXLEN_FLAGS(BNX_MAX_FRAMELEN,
1342                     BGE_RCB_FLAG_RING_DISABLED);
1343                 if (BNX_IS_5717_PLUS(sc))
1344                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
1345                 else
1346                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1347                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1348                     rcb->bge_hostaddr.bge_addr_hi);
1349                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1350                     rcb->bge_hostaddr.bge_addr_lo);
1351                 /* Program the jumbo receive producer ring RCB parameters. */
1352                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1353                     rcb->bge_maxlen_flags);
1354                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1355                 /* Reset the jumbo receive producer ring producer index. */
1356                 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1357         }
1358
1359         /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
1360         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906 &&
1361             (sc->bnx_chipid == BGE_CHIPID_BCM5906_A0 ||
1362              sc->bnx_chipid == BGE_CHIPID_BCM5906_A1 ||
1363              sc->bnx_chipid == BGE_CHIPID_BCM5906_A2)) {
1364                 CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
1365                     (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
1366         }
1367
1368         /*
1369          * The BD ring replenish thresholds control how often the
1370          * hardware fetches new BD's from the producer rings in host
1371          * memory.  Setting the value too low on a busy system can
1372          * starve the hardware and recue the throughpout.
1373          *
1374          * Set the BD ring replentish thresholds. The recommended
1375          * values are 1/8th the number of descriptors allocated to
1376          * each ring.
1377          */
1378         val = 8;
1379         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1380         if (BNX_IS_JUMBO_CAPABLE(sc)) {
1381                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
1382                     BGE_JUMBO_RX_RING_CNT/8);
1383         }
1384         if (BNX_IS_57765_PLUS(sc)) {
1385                 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
1386                 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
1387         }
1388
1389         /*
1390          * Disable all send rings by setting the 'ring disabled' bit
1391          * in the flags field of all the TX send ring control blocks,
1392          * located in NIC memory.
1393          */
1394         if (BNX_IS_5717_PLUS(sc))
1395                 limit = 4;
1396         else if (BNX_IS_57765_FAMILY(sc))
1397                 limit = 2;
1398         else
1399                 limit = 1;
1400         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1401         for (i = 0; i < limit; i++) {
1402                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1403                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1404                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1405                 vrcb += sizeof(struct bge_rcb);
1406         }
1407
1408         /* Configure send ring RCB 0 (we use only the first ring) */
1409         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1410         BGE_HOSTADDR(taddr, sc->bnx_ldata.bnx_tx_ring_paddr);
1411         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1412         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1413         if (BNX_IS_5717_PLUS(sc)) {
1414                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
1415         } else {
1416                 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1417                     BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1418         }
1419         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1420             BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1421
1422         /*
1423          * Disable all receive return rings by setting the
1424          * 'ring disabled' bit in the flags field of all the receive
1425          * return ring control blocks, located in NIC memory.
1426          */
1427         if (BNX_IS_5717_PLUS(sc)) {
1428                 /* Should be 17, use 16 until we get an SRAM map. */
1429                 limit = 16;
1430         } else if (BNX_IS_57765_FAMILY(sc)) {
1431                 limit = 4;
1432         } else {
1433                 limit = 1;
1434         }
1435         /* Disable all receive return rings. */
1436         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1437         for (i = 0; i < limit; i++) {
1438                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1439                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1440                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1441                     BGE_RCB_FLAG_RING_DISABLED);
1442                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1443                 bnx_writembx(sc, BGE_MBX_RX_CONS0_LO +
1444                     (i * (sizeof(uint64_t))), 0);
1445                 vrcb += sizeof(struct bge_rcb);
1446         }
1447
1448         /*
1449          * Set up receive return ring 0.  Note that the NIC address
1450          * for RX return rings is 0x0.  The return rings live entirely
1451          * within the host, so the nicaddr field in the RCB isn't used.
1452          */
1453         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1454         BGE_HOSTADDR(taddr, sc->bnx_ldata.bnx_rx_return_ring_paddr);
1455         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1456         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1457         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1458         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1459             BGE_RCB_MAXLEN_FLAGS(sc->bnx_return_ring_cnt, 0));
1460
1461         /* Set random backoff seed for TX */
1462         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1463             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1464             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1465             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1466             BGE_TX_BACKOFF_SEED_MASK);
1467
1468         /* Set inter-packet gap */
1469         val = 0x2620;
1470         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
1471                 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
1472                     (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
1473         }
1474         CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
1475
1476         /*
1477          * Specify which ring to use for packets that don't match
1478          * any RX rules.
1479          */
1480         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1481
1482         /*
1483          * Configure number of RX lists. One interrupt distribution
1484          * list, sixteen active lists, one bad frames class.
1485          */
1486         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1487
1488         /* Inialize RX list placement stats mask. */
1489         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1490         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1491
1492         /* Disable host coalescing until we get it set up */
1493         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1494
1495         /* Poll to make sure it's shut down. */
1496         for (i = 0; i < BNX_TIMEOUT; i++) {
1497                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1498                         break;
1499                 DELAY(10);
1500         }
1501
1502         if (i == BNX_TIMEOUT) {
1503                 if_printf(&sc->arpcom.ac_if,
1504                           "host coalescing engine failed to idle\n");
1505                 return(ENXIO);
1506         }
1507
1508         /* Set up host coalescing defaults */
1509         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bnx_rx_coal_ticks);
1510         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bnx_tx_coal_ticks);
1511         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bnx_rx_coal_bds);
1512         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bnx_tx_coal_bds);
1513         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, sc->bnx_rx_coal_bds_int);
1514         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, sc->bnx_tx_coal_bds_int);
1515
1516         /* Set up address of status block */
1517         bzero(sc->bnx_ldata.bnx_status_block, BGE_STATUS_BLK_SZ);
1518         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1519             BGE_ADDR_HI(sc->bnx_ldata.bnx_status_block_paddr));
1520         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1521             BGE_ADDR_LO(sc->bnx_ldata.bnx_status_block_paddr));
1522
1523         /* Set up status block partail update size. */
1524         val = BGE_STATBLKSZ_32BYTE;
1525 #if 0
1526         /*
1527          * Does not seem to have visible effect in both
1528          * bulk data (1472B UDP datagram) and tiny data
1529          * (18B UDP datagram) TX tests.
1530          */
1531         val |= BGE_HCCMODE_CLRTICK_TX;
1532 #endif
1533         /* Turn on host coalescing state machine */
1534         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
1535
1536         /* Turn on RX BD completion state machine and enable attentions */
1537         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1538             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1539
1540         /* Turn on RX list placement state machine */
1541         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1542
1543         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
1544             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
1545             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
1546             BGE_MACMODE_FRMHDR_DMA_ENB;
1547
1548         if (sc->bnx_flags & BNX_FLAG_TBI)
1549                 val |= BGE_PORTMODE_TBI;
1550         else if (sc->bnx_flags & BNX_FLAG_MII_SERDES)
1551                 val |= BGE_PORTMODE_GMII;
1552         else
1553                 val |= BGE_PORTMODE_MII;
1554
1555         /* Turn on DMA, clear stats */
1556         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
1557
1558         /* Set misc. local control, enable interrupts on attentions */
1559         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1560
1561 #ifdef notdef
1562         /* Assert GPIO pins for PHY reset */
1563         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1564             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1565         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1566             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1567 #endif
1568
1569         /* Turn on write DMA state machine */
1570         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1571         /* Enable host coalescing bug fix. */
1572         val |= BGE_WDMAMODE_STATUS_TAG_FIX;
1573         if (sc->bnx_asicrev == BGE_ASICREV_BCM5785) {
1574                 /* Request larger DMA burst size to get better performance. */
1575                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
1576         }
1577         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1578         DELAY(40);
1579
1580         if (BNX_IS_57765_PLUS(sc)) {
1581                 uint32_t dmactl;
1582
1583                 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
1584                 /*
1585                  * Adjust tx margin to prevent TX data corruption and
1586                  * fix internal FIFO overflow.
1587                  */
1588                 if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1589                     sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
1590                         dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
1591                             BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
1592                             BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
1593                         dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
1594                             BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
1595                             BGE_RDMA_RSRVCTRL_TXMRGN_320B;
1596                 }
1597                 /*
1598                  * Enable fix for read DMA FIFO overruns.
1599                  * The fix is to limit the number of RX BDs
1600                  * the hardware would fetch at a fime.
1601                  */
1602                 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL,
1603                     dmactl | BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
1604         }
1605
1606         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719) {
1607                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
1608                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
1609                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
1610                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1611         } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
1612                 /*
1613                  * Allow 4KB burst length reads for non-LSO frames.
1614                  * Enable 512B burst length reads for buffer descriptors.
1615                  */
1616                 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
1617                     CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
1618                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
1619                     BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
1620         }
1621
1622         /* Turn on read DMA state machine */
1623         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
1624         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717)
1625                 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
1626         if (sc->bnx_asicrev == BGE_ASICREV_BCM5784 ||
1627             sc->bnx_asicrev == BGE_ASICREV_BCM5785 ||
1628             sc->bnx_asicrev == BGE_ASICREV_BCM57780) {
1629                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
1630                     BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
1631                     BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
1632         }
1633         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
1634                 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
1635                     BGE_RDMAMODE_H2BNC_VLAN_DET;
1636                 /*
1637                  * Allow multiple outstanding read requests from
1638                  * non-LSO read DMA engine.
1639                  */
1640                 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
1641         }
1642         if (sc->bnx_flags & BNX_FLAG_TSO)
1643                 val |= BGE_RDMAMODE_TSO4_ENABLE;
1644         val |= BGE_RDMAMODE_FIFO_LONG_BURST;
1645         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
1646         DELAY(40);
1647
1648         /* Turn on RX data completion state machine */
1649         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1650
1651         /* Turn on RX BD initiator state machine */
1652         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1653
1654         /* Turn on RX data and RX BD initiator state machine */
1655         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1656
1657         /* Turn on send BD completion state machine */
1658         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1659
1660         /* Turn on send data completion state machine */
1661         val = BGE_SDCMODE_ENABLE;
1662         if (sc->bnx_asicrev == BGE_ASICREV_BCM5761)
1663                 val |= BGE_SDCMODE_CDELAY;
1664         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
1665
1666         /* Turn on send data initiator state machine */
1667         if (sc->bnx_flags & BNX_FLAG_TSO) {
1668                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
1669                     BGE_SDIMODE_HW_LSO_PRE_DMA);
1670         } else {
1671                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1672         }
1673
1674         /* Turn on send BD initiator state machine */
1675         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1676
1677         /* Turn on send BD selector state machine */
1678         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1679
1680         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1681         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1682             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1683
1684         /* ack/clear link change events */
1685         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1686             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1687             BGE_MACSTAT_LINK_CHANGED);
1688         CSR_WRITE_4(sc, BGE_MI_STS, 0);
1689
1690         /*
1691          * Enable attention when the link has changed state for
1692          * devices that use auto polling.
1693          */
1694         if (sc->bnx_flags & BNX_FLAG_TBI) {
1695                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1696         } else {
1697                 if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
1698                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bnx_mi_mode);
1699                         DELAY(80);
1700                 }
1701         }
1702
1703         /*
1704          * Clear any pending link state attention.
1705          * Otherwise some link state change events may be lost until attention
1706          * is cleared by bnx_intr() -> bnx_softc.bnx_link_upd() sequence.
1707          * It's not necessary on newer BCM chips - perhaps enabling link
1708          * state change attentions implies clearing pending attention.
1709          */
1710         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1711             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1712             BGE_MACSTAT_LINK_CHANGED);
1713
1714         /* Enable link state change attentions. */
1715         BNX_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1716
1717         return(0);
1718 }
1719
1720 /*
1721  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1722  * against our list and return its name if we find a match. Note
1723  * that since the Broadcom controller contains VPD support, we
1724  * can get the device name string from the controller itself instead
1725  * of the compiled-in string. This is a little slow, but it guarantees
1726  * we'll always announce the right product name.
1727  */
1728 static int
1729 bnx_probe(device_t dev)
1730 {
1731         const struct bnx_type *t;
1732         uint16_t product, vendor;
1733
1734         if (!pci_is_pcie(dev))
1735                 return ENXIO;
1736
1737         product = pci_get_device(dev);
1738         vendor = pci_get_vendor(dev);
1739
1740         for (t = bnx_devs; t->bnx_name != NULL; t++) {
1741                 if (vendor == t->bnx_vid && product == t->bnx_did)
1742                         break;
1743         }
1744         if (t->bnx_name == NULL)
1745                 return ENXIO;
1746
1747         device_set_desc(dev, t->bnx_name);
1748         return 0;
1749 }
1750
1751 static int
1752 bnx_attach(device_t dev)
1753 {
1754         struct ifnet *ifp;
1755         struct bnx_softc *sc;
1756         uint32_t hwcfg = 0;
1757         int error = 0, rid, capmask;
1758         uint8_t ether_addr[ETHER_ADDR_LEN];
1759         uint16_t product;
1760         driver_intr_t *intr_func;
1761         uintptr_t mii_priv = 0;
1762         u_int intr_flags;
1763 #ifdef BNX_TSO_DEBUG
1764         char desc[32];
1765         int i;
1766 #endif
1767
1768         sc = device_get_softc(dev);
1769         sc->bnx_dev = dev;
1770         callout_init_mp(&sc->bnx_stat_timer);
1771         callout_init_mp(&sc->bnx_intr_timer);
1772         lwkt_serialize_init(&sc->bnx_jslot_serializer);
1773
1774         product = pci_get_device(dev);
1775
1776 #ifndef BURN_BRIDGES
1777         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1778                 uint32_t irq, mem;
1779
1780                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1781                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
1782
1783                 device_printf(dev, "chip is in D%d power mode "
1784                     "-- setting to D0\n", pci_get_powerstate(dev));
1785
1786                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1787
1788                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1789                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
1790         }
1791 #endif  /* !BURN_BRIDGE */
1792
1793         /*
1794          * Map control/status registers.
1795          */
1796         pci_enable_busmaster(dev);
1797
1798         rid = BGE_PCI_BAR0;
1799         sc->bnx_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1800             RF_ACTIVE);
1801
1802         if (sc->bnx_res == NULL) {
1803                 device_printf(dev, "couldn't map memory\n");
1804                 return ENXIO;
1805         }
1806
1807         sc->bnx_btag = rman_get_bustag(sc->bnx_res);
1808         sc->bnx_bhandle = rman_get_bushandle(sc->bnx_res);
1809
1810         /* Save various chip information */
1811         sc->bnx_chipid =
1812             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
1813             BGE_PCIMISCCTL_ASICREV_SHIFT;
1814         if (BGE_ASICREV(sc->bnx_chipid) == BGE_ASICREV_USE_PRODID_REG) {
1815                 /* All chips having dedicated ASICREV register have CPMU */
1816                 sc->bnx_flags |= BNX_FLAG_CPMU;
1817
1818                 switch (product) {
1819                 case PCI_PRODUCT_BROADCOM_BCM5717:
1820                 case PCI_PRODUCT_BROADCOM_BCM5717C:
1821                 case PCI_PRODUCT_BROADCOM_BCM5718:
1822                 case PCI_PRODUCT_BROADCOM_BCM5719:
1823                 case PCI_PRODUCT_BROADCOM_BCM5720_ALT:
1824                         sc->bnx_chipid = pci_read_config(dev,
1825                             BGE_PCI_GEN2_PRODID_ASICREV, 4);
1826                         break;
1827
1828                 case PCI_PRODUCT_BROADCOM_BCM57761:
1829                 case PCI_PRODUCT_BROADCOM_BCM57762:
1830                 case PCI_PRODUCT_BROADCOM_BCM57765:
1831                 case PCI_PRODUCT_BROADCOM_BCM57766:
1832                 case PCI_PRODUCT_BROADCOM_BCM57781:
1833                 case PCI_PRODUCT_BROADCOM_BCM57782:
1834                 case PCI_PRODUCT_BROADCOM_BCM57785:
1835                 case PCI_PRODUCT_BROADCOM_BCM57786:
1836                 case PCI_PRODUCT_BROADCOM_BCM57791:
1837                 case PCI_PRODUCT_BROADCOM_BCM57795:
1838                         sc->bnx_chipid = pci_read_config(dev,
1839                             BGE_PCI_GEN15_PRODID_ASICREV, 4);
1840                         break;
1841
1842                 default:
1843                         sc->bnx_chipid = pci_read_config(dev,
1844                             BGE_PCI_PRODID_ASICREV, 4);
1845                         break;
1846                 }
1847         }
1848         if (sc->bnx_chipid == BGE_CHIPID_BCM5717_C0)
1849                 sc->bnx_chipid = BGE_CHIPID_BCM5720_A0;
1850
1851         sc->bnx_asicrev = BGE_ASICREV(sc->bnx_chipid);
1852         sc->bnx_chiprev = BGE_CHIPREV(sc->bnx_chipid);
1853
1854         switch (sc->bnx_asicrev) {
1855         case BGE_ASICREV_BCM5717:
1856         case BGE_ASICREV_BCM5719:
1857         case BGE_ASICREV_BCM5720:
1858                 sc->bnx_flags |= BNX_FLAG_5717_PLUS | BNX_FLAG_57765_PLUS;
1859                 break;
1860
1861         case BGE_ASICREV_BCM57765:
1862         case BGE_ASICREV_BCM57766:
1863                 sc->bnx_flags |= BNX_FLAG_57765_FAMILY | BNX_FLAG_57765_PLUS;
1864                 break;
1865         }
1866         sc->bnx_flags |= BNX_FLAG_SHORTDMA;
1867
1868         sc->bnx_flags |= BNX_FLAG_TSO;
1869         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 &&
1870             sc->bnx_chipid == BGE_CHIPID_BCM5719_A0)
1871                 sc->bnx_flags &= ~BNX_FLAG_TSO;
1872
1873         if (sc->bnx_asicrev == BGE_ASICREV_BCM5717 ||
1874             BNX_IS_57765_FAMILY(sc)) {
1875                 /*
1876                  * All BCM57785 and BCM5718 families chips have a bug that
1877                  * under certain situation interrupt will not be enabled
1878                  * even if status tag is written to BGE_MBX_IRQ0_LO mailbox.
1879                  *
1880                  * While BCM5719 and BCM5720 have a hardware workaround
1881                  * which could fix the above bug.
1882                  * See the comment near BGE_PCIDMARWCTL_TAGGED_STATUS_WA in
1883                  * bnx_chipinit().
1884                  *
1885                  * For the rest of the chips in these two families, we will
1886                  * have to poll the status block at high rate (10ms currently)
1887                  * to check whether the interrupt is hosed or not.
1888                  * See bnx_intr_check() for details.
1889                  */
1890                 sc->bnx_flags |= BNX_FLAG_STATUSTAG_BUG;
1891         }
1892
1893         sc->bnx_pciecap = pci_get_pciecap_ptr(sc->bnx_dev);
1894         if (sc->bnx_asicrev == BGE_ASICREV_BCM5719 ||
1895             sc->bnx_asicrev == BGE_ASICREV_BCM5720)
1896                 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_2048);
1897         else
1898                 pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
1899         device_printf(dev, "CHIP ID 0x%08x; "
1900                       "ASIC REV 0x%02x; CHIP REV 0x%02x\n",
1901                       sc->bnx_chipid, sc->bnx_asicrev, sc->bnx_chiprev);
1902
1903         /*
1904          * Set various PHY quirk flags.
1905          */
1906
1907         capmask = MII_CAPMASK_DEFAULT;
1908         if (product == PCI_PRODUCT_BROADCOM_BCM57791 ||
1909             product == PCI_PRODUCT_BROADCOM_BCM57795) {
1910                 /* 10/100 only */
1911                 capmask &= ~BMSR_EXTSTAT;
1912         }
1913
1914         mii_priv |= BRGPHY_FLAG_WIRESPEED;
1915
1916         /*
1917          * Allocate interrupt
1918          */
1919         sc->bnx_irq_type = pci_alloc_1intr(dev, bnx_msi_enable, &sc->bnx_irq_rid,
1920             &intr_flags);
1921
1922         sc->bnx_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->bnx_irq_rid,
1923             intr_flags);
1924         if (sc->bnx_irq == NULL) {
1925                 device_printf(dev, "couldn't map interrupt\n");
1926                 error = ENXIO;
1927                 goto fail;
1928         }
1929
1930         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
1931                 sc->bnx_flags |= BNX_FLAG_ONESHOT_MSI;
1932                 bnx_enable_msi(sc);
1933         }
1934
1935         /* Initialize if_name earlier, so if_printf could be used */
1936         ifp = &sc->arpcom.ac_if;
1937         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1938
1939         /* Try to reset the chip. */
1940         bnx_reset(sc);
1941
1942         if (bnx_chipinit(sc)) {
1943                 device_printf(dev, "chip initialization failed\n");
1944                 error = ENXIO;
1945                 goto fail;
1946         }
1947
1948         /*
1949          * Get station address
1950          */
1951         error = bnx_get_eaddr(sc, ether_addr);
1952         if (error) {
1953                 device_printf(dev, "failed to read station address\n");
1954                 goto fail;
1955         }
1956
1957         if (BNX_IS_57765_PLUS(sc)) {
1958                 sc->bnx_return_ring_cnt = BGE_RETURN_RING_CNT;
1959         } else {
1960                 /* 5705/5750 limits RX return ring to 512 entries. */
1961                 sc->bnx_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1962         }
1963
1964         error = bnx_dma_alloc(sc);
1965         if (error)
1966                 goto fail;
1967
1968         /* Set default tuneable values. */
1969         sc->bnx_rx_coal_ticks = BNX_RX_COAL_TICKS_DEF;
1970         sc->bnx_tx_coal_ticks = BNX_TX_COAL_TICKS_DEF;
1971         sc->bnx_rx_coal_bds = BNX_RX_COAL_BDS_DEF;
1972         sc->bnx_tx_coal_bds = BNX_TX_COAL_BDS_DEF;
1973         sc->bnx_rx_coal_bds_int = BNX_RX_COAL_BDS_INT_DEF;
1974         sc->bnx_tx_coal_bds_int = BNX_TX_COAL_BDS_INT_DEF;
1975         sc->bnx_tx_wreg = BNX_TX_WREG_NSEGS;
1976
1977         /* Set up ifnet structure */
1978         ifp->if_softc = sc;
1979         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1980         ifp->if_ioctl = bnx_ioctl;
1981         ifp->if_start = bnx_start;
1982 #ifdef IFPOLL_ENABLE
1983         ifp->if_npoll = bnx_npoll;
1984 #endif
1985         ifp->if_watchdog = bnx_watchdog;
1986         ifp->if_init = bnx_init;
1987         ifp->if_mtu = ETHERMTU;
1988         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1989         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1990         ifq_set_ready(&ifp->if_snd);
1991
1992         ifp->if_capabilities |= IFCAP_HWCSUM;
1993         ifp->if_hwassist = BNX_CSUM_FEATURES;
1994         if (sc->bnx_flags & BNX_FLAG_TSO) {
1995                 ifp->if_capabilities |= IFCAP_TSO;
1996                 ifp->if_hwassist |= CSUM_TSO;
1997         }
1998         ifp->if_capenable = ifp->if_capabilities;
1999
2000         /*
2001          * Figure out what sort of media we have by checking the
2002          * hardware config word in the first 32k of NIC internal memory,
2003          * or fall back to examining the EEPROM if necessary.
2004          * Note: on some BCM5700 cards, this value appears to be unset.
2005          * If that's the case, we have to rely on identifying the NIC
2006          * by its PCI subsystem ID, as we do below for the SysKonnect
2007          * SK-9D41.
2008          */
2009         if (bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) {
2010                 hwcfg = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
2011         } else {
2012                 if (bnx_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
2013                                     sizeof(hwcfg))) {
2014                         device_printf(dev, "failed to read EEPROM\n");
2015                         error = ENXIO;
2016                         goto fail;
2017                 }
2018                 hwcfg = ntohl(hwcfg);
2019         }
2020
2021         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
2022         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
2023             (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
2024                 sc->bnx_flags |= BNX_FLAG_TBI;
2025
2026         /* Setup MI MODE */
2027         if (sc->bnx_flags & BNX_FLAG_CPMU)
2028                 sc->bnx_mi_mode = BGE_MIMODE_500KHZ_CONST;
2029         else
2030                 sc->bnx_mi_mode = BGE_MIMODE_BASE;
2031
2032         /* Setup link status update stuffs */
2033         if (sc->bnx_flags & BNX_FLAG_TBI) {
2034                 sc->bnx_link_upd = bnx_tbi_link_upd;
2035                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
2036         } else if (sc->bnx_mi_mode & BGE_MIMODE_AUTOPOLL) {
2037                 sc->bnx_link_upd = bnx_autopoll_link_upd;
2038                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
2039         } else {
2040                 sc->bnx_link_upd = bnx_copper_link_upd;
2041                 sc->bnx_link_chg = BGE_MACSTAT_LINK_CHANGED;
2042         }
2043
2044         /* Set default PHY address */
2045         sc->bnx_phyno = 1;
2046
2047         /*
2048          * PHY address mapping for various devices.
2049          *
2050          *          | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
2051          * ---------+-------+-------+-------+-------+
2052          * BCM57XX  |   1   |   X   |   X   |   X   |
2053          * BCM5704  |   1   |   X   |   1   |   X   |
2054          * BCM5717  |   1   |   8   |   2   |   9   |
2055          * BCM5719  |   1   |   8   |   2   |   9   |
2056          * BCM5720  |   1   |   8   |   2   |   9   |
2057          *
2058          * Other addresses may respond but they are not
2059          * IEEE compliant PHYs and should be ignored.
2060          */
2061         if (BNX_IS_5717_PLUS(sc)) {
2062                 int f;
2063
2064                 f = pci_get_function(dev);
2065                 if (sc->bnx_chipid == BGE_CHIPID_BCM5717_A0) {
2066                         if (CSR_READ_4(sc, BGE_SGDIG_STS) &
2067                             BGE_SGDIGSTS_IS_SERDES)
2068                                 sc->bnx_phyno = f + 8;
2069                         else
2070                                 sc->bnx_phyno = f + 1;
2071                 } else {
2072                         if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
2073                             BGE_CPMU_PHY_STRAP_IS_SERDES)
2074                                 sc->bnx_phyno = f + 8;
2075                         else
2076                                 sc->bnx_phyno = f + 1;
2077                 }
2078         }
2079
2080         if (sc->bnx_flags & BNX_FLAG_TBI) {
2081                 ifmedia_init(&sc->bnx_ifmedia, IFM_IMASK,
2082                     bnx_ifmedia_upd, bnx_ifmedia_sts);
2083                 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
2084                 ifmedia_add(&sc->bnx_ifmedia,
2085                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
2086                 ifmedia_add(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
2087                 ifmedia_set(&sc->bnx_ifmedia, IFM_ETHER|IFM_AUTO);
2088                 sc->bnx_ifmedia.ifm_media = sc->bnx_ifmedia.ifm_cur->ifm_media;
2089         } else {
2090                 struct mii_probe_args mii_args;
2091
2092                 mii_probe_args_init(&mii_args, bnx_ifmedia_upd, bnx_ifmedia_sts);
2093                 mii_args.mii_probemask = 1 << sc->bnx_phyno;
2094                 mii_args.mii_capmask = capmask;
2095                 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
2096                 mii_args.mii_priv = mii_priv;
2097
2098                 error = mii_probe(dev, &sc->bnx_miibus, &mii_args);
2099                 if (error) {
2100                         device_printf(dev, "MII without any PHY!\n");
2101                         goto fail;
2102                 }
2103         }
2104
2105         /*
2106          * Create sysctl nodes.
2107          */
2108         sysctl_ctx_init(&sc->bnx_sysctl_ctx);
2109         sc->bnx_sysctl_tree = SYSCTL_ADD_NODE(&sc->bnx_sysctl_ctx,
2110                                               SYSCTL_STATIC_CHILDREN(_hw),
2111                                               OID_AUTO,
2112                                               device_get_nameunit(dev),
2113                                               CTLFLAG_RD, 0, "");
2114         if (sc->bnx_sysctl_tree == NULL) {
2115                 device_printf(dev, "can't add sysctl node\n");
2116                 error = ENXIO;
2117                 goto fail;
2118         }
2119
2120         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2121                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2122                         OID_AUTO, "rx_coal_ticks",
2123                         CTLTYPE_INT | CTLFLAG_RW,
2124                         sc, 0, bnx_sysctl_rx_coal_ticks, "I",
2125                         "Receive coalescing ticks (usec).");
2126         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2127                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2128                         OID_AUTO, "tx_coal_ticks",
2129                         CTLTYPE_INT | CTLFLAG_RW,
2130                         sc, 0, bnx_sysctl_tx_coal_ticks, "I",
2131                         "Transmit coalescing ticks (usec).");
2132         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2133                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2134                         OID_AUTO, "rx_coal_bds",
2135                         CTLTYPE_INT | CTLFLAG_RW,
2136                         sc, 0, bnx_sysctl_rx_coal_bds, "I",
2137                         "Receive max coalesced BD count.");
2138         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2139                         SYSCTL_CHILDREN(sc->bnx_sysctl_tree),
2140                         OID_AUTO, "tx_coal_bds",
2141                         CTLTYPE_INT | CTLFLAG_RW,
2142                         sc, 0, bnx_sysctl_tx_coal_bds, "I",
2143                         "Transmit max coalesced BD count.");
2144         /*
2145          * A common design characteristic for many Broadcom
2146          * client controllers is that they only support a
2147          * single outstanding DMA read operation on the PCIe
2148          * bus. This means that it will take twice as long to
2149          * fetch a TX frame that is split into header and
2150          * payload buffers as it does to fetch a single,
2151          * contiguous TX frame (2 reads vs. 1 read). For these
2152          * controllers, coalescing buffers to reduce the number
2153          * of memory reads is effective way to get maximum
2154          * performance(about 940Mbps).  Without collapsing TX
2155          * buffers the maximum TCP bulk transfer performance
2156          * is about 850Mbps. However forcing coalescing mbufs
2157          * consumes a lot of CPU cycles, so leave it off by
2158          * default.
2159          */
2160         SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2161             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2162             "force_defrag", CTLFLAG_RW, &sc->bnx_force_defrag, 0,
2163             "Force defragment on TX path");
2164
2165         SYSCTL_ADD_INT(&sc->bnx_sysctl_ctx,
2166             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2167             "tx_wreg", CTLFLAG_RW, &sc->bnx_tx_wreg, 0,
2168             "# of segments before writing to hardware register");
2169
2170         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2171             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2172             "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2173             sc, 0, bnx_sysctl_rx_coal_bds_int, "I",
2174             "Receive max coalesced BD count during interrupt.");
2175         SYSCTL_ADD_PROC(&sc->bnx_sysctl_ctx,
2176             SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2177             "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
2178             sc, 0, bnx_sysctl_tx_coal_bds_int, "I",
2179             "Transmit max coalesced BD count during interrupt.");
2180
2181 #ifdef BNX_TSO_DEBUG
2182         for (i = 0; i < BNX_TSO_NSTATS; ++i) {
2183                 ksnprintf(desc, sizeof(desc), "tso%d", i + 1);
2184                 SYSCTL_ADD_ULONG(&sc->bnx_sysctl_ctx,
2185                     SYSCTL_CHILDREN(sc->bnx_sysctl_tree), OID_AUTO,
2186                     desc, CTLFLAG_RW, &sc->bnx_tsosegs[i], "");
2187         }
2188 #endif
2189
2190         /*
2191          * Call MI attach routine.
2192          */
2193         ether_ifattach(ifp, ether_addr, NULL);
2194
2195 #ifdef IFPOLL_ENABLE
2196         ifpoll_compat_setup(&sc->bnx_npoll,
2197             &sc->bnx_sysctl_ctx, sc->bnx_sysctl_tree,
2198             device_get_unit(dev), ifp->if_serializer);
2199 #endif
2200
2201         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
2202                 if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
2203                         intr_func = bnx_msi_oneshot;
2204                         if (bootverbose)
2205                                 device_printf(dev, "oneshot MSI\n");
2206                 } else {
2207                         intr_func = bnx_msi;
2208                 }
2209         } else {
2210                 intr_func = bnx_intr_legacy;
2211         }
2212         error = bus_setup_intr(dev, sc->bnx_irq, INTR_MPSAFE, intr_func, sc,
2213             &sc->bnx_intrhand, ifp->if_serializer);
2214         if (error) {
2215                 ether_ifdetach(ifp);
2216                 device_printf(dev, "couldn't set up irq\n");
2217                 goto fail;
2218         }
2219
2220         sc->bnx_intr_cpuid = rman_get_cpuid(sc->bnx_irq);
2221         sc->bnx_stat_cpuid = sc->bnx_intr_cpuid;
2222         ifq_set_cpuid(&ifp->if_snd, sc->bnx_intr_cpuid);
2223
2224         return(0);
2225 fail:
2226         bnx_detach(dev);
2227         return(error);
2228 }
2229
2230 static int
2231 bnx_detach(device_t dev)
2232 {
2233         struct bnx_softc *sc = device_get_softc(dev);
2234
2235         if (device_is_attached(dev)) {
2236                 struct ifnet *ifp = &sc->arpcom.ac_if;
2237
2238                 lwkt_serialize_enter(ifp->if_serializer);
2239                 bnx_stop(sc);
2240                 bnx_reset(sc);
2241                 bus_teardown_intr(dev, sc->bnx_irq, sc->bnx_intrhand);
2242                 lwkt_serialize_exit(ifp->if_serializer);
2243
2244                 ether_ifdetach(ifp);
2245         }
2246
2247         if (sc->bnx_flags & BNX_FLAG_TBI)
2248                 ifmedia_removeall(&sc->bnx_ifmedia);
2249         if (sc->bnx_miibus)
2250                 device_delete_child(dev, sc->bnx_miibus);
2251         bus_generic_detach(dev);
2252
2253         if (sc->bnx_irq != NULL) {
2254                 bus_release_resource(dev, SYS_RES_IRQ, sc->bnx_irq_rid,
2255                     sc->bnx_irq);
2256         }
2257         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI)
2258                 pci_release_msi(dev);
2259
2260         if (sc->bnx_res != NULL) {
2261                 bus_release_resource(dev, SYS_RES_MEMORY,
2262                     BGE_PCI_BAR0, sc->bnx_res);
2263         }
2264
2265         if (sc->bnx_sysctl_tree != NULL)
2266                 sysctl_ctx_free(&sc->bnx_sysctl_ctx);
2267
2268         bnx_dma_free(sc);
2269
2270         return 0;
2271 }
2272
2273 static void
2274 bnx_reset(struct bnx_softc *sc)
2275 {
2276         device_t dev;
2277         uint32_t cachesize, command, pcistate, reset;
2278         void (*write_op)(struct bnx_softc *, uint32_t, uint32_t);
2279         int i, val = 0;
2280         uint16_t devctl;
2281
2282         dev = sc->bnx_dev;
2283
2284         if (sc->bnx_asicrev != BGE_ASICREV_BCM5906)
2285                 write_op = bnx_writemem_direct;
2286         else
2287                 write_op = bnx_writereg_ind;
2288
2289         /* Save some important PCI state. */
2290         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2291         command = pci_read_config(dev, BGE_PCI_CMD, 4);
2292         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2293
2294         pci_write_config(dev, BGE_PCI_MISC_CTL,
2295             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2296             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2297             BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2298
2299         /* Disable fastboot on controllers that support it. */
2300         if (bootverbose)
2301                 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2302         CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2303
2304         /*
2305          * Write the magic number to SRAM at offset 0xB50.
2306          * When firmware finishes its initialization it will
2307          * write ~BGE_MAGIC_NUMBER to the same location.
2308          */
2309         bnx_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2310
2311         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2312
2313         /* XXX: Broadcom Linux driver. */
2314         /* Force PCI-E 1.0a mode */
2315         if (!BNX_IS_57765_PLUS(sc) &&
2316             CSR_READ_4(sc, BGE_PCIE_PHY_TSTCTL) ==
2317             (BGE_PCIE_PHY_TSTCTL_PSCRAM |
2318              BGE_PCIE_PHY_TSTCTL_PCIE10)) {
2319                 CSR_WRITE_4(sc, BGE_PCIE_PHY_TSTCTL,
2320                     BGE_PCIE_PHY_TSTCTL_PSCRAM);
2321         }
2322         if (sc->bnx_chipid != BGE_CHIPID_BCM5750_A0) {
2323                 /* Prevent PCIE link training during global reset */
2324                 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2325                 reset |= (1<<29);
2326         }
2327
2328         /*
2329          * Set GPHY Power Down Override to leave GPHY
2330          * powered up in D0 uninitialized.
2331          */
2332         if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0)
2333                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
2334
2335         /* Issue global reset */
2336         write_op(sc, BGE_MISC_CFG, reset);
2337
2338         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
2339                 uint32_t status, ctrl;
2340
2341                 status = CSR_READ_4(sc, BGE_VCPU_STATUS);
2342                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
2343                     status | BGE_VCPU_STATUS_DRV_RESET);
2344                 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
2345                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
2346                     ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
2347         }
2348
2349         DELAY(1000);
2350
2351         /* XXX: Broadcom Linux driver. */
2352         if (sc->bnx_chipid == BGE_CHIPID_BCM5750_A0) {
2353                 uint32_t v;
2354
2355                 DELAY(500000); /* wait for link training to complete */
2356                 v = pci_read_config(dev, 0xc4, 4);
2357                 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2358         }
2359
2360         devctl = pci_read_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL, 2);
2361
2362         /* Disable no snoop and disable relaxed ordering. */
2363         devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP);
2364
2365         /* Old PCI-E chips only support 128 bytes Max PayLoad Size. */
2366         if ((sc->bnx_flags & BNX_FLAG_CPMU) == 0) {
2367                 devctl &= ~PCIEM_DEVCTL_MAX_PAYLOAD_MASK;
2368                 devctl |= PCIEM_DEVCTL_MAX_PAYLOAD_128;
2369         }
2370
2371         pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVCTRL,
2372             devctl, 2);
2373
2374         /* Clear error status. */
2375         pci_write_config(dev, sc->bnx_pciecap + PCIER_DEVSTS,
2376             PCIEM_DEVSTS_CORR_ERR |
2377             PCIEM_DEVSTS_NFATAL_ERR |
2378             PCIEM_DEVSTS_FATAL_ERR |
2379             PCIEM_DEVSTS_UNSUPP_REQ, 2);
2380
2381         /* Reset some of the PCI state that got zapped by reset */
2382         pci_write_config(dev, BGE_PCI_MISC_CTL,
2383             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2384             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
2385             BGE_PCIMISCCTL_TAGGED_STATUS, 4);
2386         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2387         pci_write_config(dev, BGE_PCI_CMD, command, 4);
2388         write_op(sc, BGE_MISC_CFG, (65 << 1));
2389
2390         /* Enable memory arbiter */
2391         CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2392
2393         if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
2394                 for (i = 0; i < BNX_TIMEOUT; i++) {
2395                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2396                         if (val & BGE_VCPU_STATUS_INIT_DONE)
2397                                 break;
2398                         DELAY(100);
2399                 }
2400                 if (i == BNX_TIMEOUT) {
2401                         if_printf(&sc->arpcom.ac_if, "reset timed out\n");
2402                         return;
2403                 }
2404         } else {
2405                 /*
2406                  * Poll until we see the 1's complement of the magic number.
2407                  * This indicates that the firmware initialization
2408                  * is complete.
2409                  */
2410                 for (i = 0; i < BNX_FIRMWARE_TIMEOUT; i++) {
2411                         val = bnx_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2412                         if (val == ~BGE_MAGIC_NUMBER)
2413                                 break;
2414                         DELAY(10);
2415                 }
2416                 if (i == BNX_FIRMWARE_TIMEOUT) {
2417                         if_printf(&sc->arpcom.ac_if, "firmware handshake "
2418                                   "timed out, found 0x%08x\n", val);
2419                 }
2420
2421                 /* BCM57765 A0 needs additional time before accessing. */
2422                 if (sc->bnx_chipid == BGE_CHIPID_BCM57765_A0)
2423                         DELAY(10 * 1000);
2424         }
2425
2426         /*
2427          * XXX Wait for the value of the PCISTATE register to
2428          * return to its original pre-reset state. This is a
2429          * fairly good indicator of reset completion. If we don't
2430          * wait for the reset to fully complete, trying to read
2431          * from the device's non-PCI registers may yield garbage
2432          * results.
2433          */
2434         for (i = 0; i < BNX_TIMEOUT; i++) {
2435                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2436                         break;
2437                 DELAY(10);
2438         }
2439
2440         /* Fix up byte swapping */
2441         CSR_WRITE_4(sc, BGE_MODE_CTL, bnx_dma_swap_options(sc));
2442
2443         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2444
2445         /*
2446          * The 5704 in TBI mode apparently needs some special
2447          * adjustment to insure the SERDES drive level is set
2448          * to 1.2V.
2449          */
2450         if (sc->bnx_asicrev == BGE_ASICREV_BCM5704 &&
2451             (sc->bnx_flags & BNX_FLAG_TBI)) {
2452                 uint32_t serdescfg;
2453
2454                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2455                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2456                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2457         }
2458
2459         CSR_WRITE_4(sc, BGE_MI_MODE,
2460             sc->bnx_mi_mode & ~BGE_MIMODE_AUTOPOLL);
2461         DELAY(80);
2462
2463         /* XXX: Broadcom Linux driver. */
2464         if (!BNX_IS_57765_PLUS(sc)) {
2465                 uint32_t v;
2466
2467                 /* Enable Data FIFO protection. */
2468                 v = CSR_READ_4(sc, BGE_PCIE_TLDLPL_PORT);
2469                 CSR_WRITE_4(sc, BGE_PCIE_TLDLPL_PORT, v | (1 << 25));
2470         }
2471
2472         DELAY(10000);
2473
2474         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
2475                 BNX_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
2476                     CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
2477         }
2478 }
2479
2480 /*
2481  * Frame reception handling. This is called if there's a frame
2482  * on the receive return list.
2483  *
2484  * Note: we have to be able to handle two possibilities here:
2485  * 1) the frame is from the jumbo recieve ring
2486  * 2) the frame is from the standard receive ring
2487  */
2488
2489 static void
2490 bnx_rxeof(struct bnx_softc *sc, uint16_t rx_prod, int count)
2491 {
2492         struct ifnet *ifp;
2493         int stdcnt = 0, jumbocnt = 0;
2494
2495         ifp = &sc->arpcom.ac_if;
2496
2497         while (sc->bnx_rx_saved_considx != rx_prod && count != 0) {
2498                 struct bge_rx_bd        *cur_rx;
2499                 uint32_t                rxidx;
2500                 struct mbuf             *m = NULL;
2501                 uint16_t                vlan_tag = 0;
2502                 int                     have_tag = 0;
2503
2504                 --count;
2505
2506                 cur_rx =
2507             &sc->bnx_ldata.bnx_rx_return_ring[sc->bnx_rx_saved_considx];
2508
2509                 rxidx = cur_rx->bge_idx;
2510                 BNX_INC(sc->bnx_rx_saved_considx, sc->bnx_return_ring_cnt);
2511
2512                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2513                         have_tag = 1;
2514                         vlan_tag = cur_rx->bge_vlan_tag;
2515                 }
2516
2517                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2518                         BNX_INC(sc->bnx_jumbo, BGE_JUMBO_RX_RING_CNT);
2519                         jumbocnt++;
2520
2521                         if (rxidx != sc->bnx_jumbo) {
2522                                 IFNET_STAT_INC(ifp, ierrors, 1);
2523                                 if_printf(ifp, "sw jumbo index(%d) "
2524                                     "and hw jumbo index(%d) mismatch, drop!\n",
2525                                     sc->bnx_jumbo, rxidx);
2526                                 bnx_setup_rxdesc_jumbo(sc, rxidx);
2527                                 continue;
2528                         }
2529
2530                         m = sc->bnx_cdata.bnx_rx_jumbo_chain[rxidx].bnx_mbuf;
2531                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2532                                 IFNET_STAT_INC(ifp, ierrors, 1);
2533                                 bnx_setup_rxdesc_jumbo(sc, sc->bnx_jumbo);
2534                                 continue;
2535                         }
2536                         if (bnx_newbuf_jumbo(sc, sc->bnx_jumbo, 0)) {
2537                                 IFNET_STAT_INC(ifp, ierrors, 1);
2538                                 bnx_setup_rxdesc_jumbo(sc, sc->bnx_jumbo);
2539                                 continue;
2540                         }
2541                 } else {
2542                         BNX_INC(sc->bnx_std, BGE_STD_RX_RING_CNT);
2543                         stdcnt++;
2544
2545                         if (rxidx != sc->bnx_std) {
2546                                 IFNET_STAT_INC(ifp, ierrors, 1);
2547                                 if_printf(ifp, "sw std index(%d) "
2548                                     "and hw std index(%d) mismatch, drop!\n",
2549                                     sc->bnx_std, rxidx);
2550                                 bnx_setup_rxdesc_std(sc, rxidx);
2551                                 continue;
2552                         }
2553
2554                         m = sc->bnx_cdata.bnx_rx_std_chain[rxidx].bnx_mbuf;
2555                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2556                                 IFNET_STAT_INC(ifp, ierrors, 1);
2557                                 bnx_setup_rxdesc_std(sc, sc->bnx_std);
2558                                 continue;
2559                         }
2560                         if (bnx_newbuf_std(sc, sc->bnx_std, 0)) {
2561                                 IFNET_STAT_INC(ifp, ierrors, 1);
2562                                 bnx_setup_rxdesc_std(sc, sc->bnx_std);
2563                                 continue;
2564                         }
2565                 }
2566
2567                 IFNET_STAT_INC(ifp, ipackets, 1);
2568                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2569                 m->m_pkthdr.rcvif = ifp;
2570
2571                 if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2572                     (cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
2573                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2574                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2575                                 if ((cur_rx->bge_error_flag &
2576                                     BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
2577                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2578                         }
2579                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
2580                                 m->m_pkthdr.csum_data =
2581                                     cur_rx->bge_tcp_udp_csum;
2582                                 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2583                                     CSUM_PSEUDO_HDR;
2584                         }
2585                 }
2586
2587                 /*
2588                  * If we received a packet with a vlan tag, pass it
2589                  * to vlan_input() instead of ether_input().
2590                  */
2591                 if (have_tag) {
2592                         m->m_flags |= M_VLANTAG;
2593                         m->m_pkthdr.ether_vlantag = vlan_tag;
2594                 }
2595                 ifp->if_input(ifp, m);
2596         }
2597
2598         bnx_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bnx_rx_saved_considx);
2599         if (stdcnt)
2600                 bnx_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bnx_std);
2601         if (jumbocnt)
2602                 bnx_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bnx_jumbo);
2603 }
2604
2605 static void
2606 bnx_txeof(struct bnx_softc *sc, uint16_t tx_cons)
2607 {
2608         struct ifnet *ifp;
2609
2610         ifp = &sc->arpcom.ac_if;
2611
2612         /*
2613          * Go through our tx ring and free mbufs for those
2614          * frames that have been sent.
2615          */
2616         while (sc->bnx_tx_saved_considx != tx_cons) {
2617                 uint32_t idx = 0;
2618
2619                 idx = sc->bnx_tx_saved_considx;
2620                 if (sc->bnx_cdata.bnx_tx_chain[idx] != NULL) {
2621                         IFNET_STAT_INC(ifp, opackets, 1);
2622                         bus_dmamap_unload(sc->bnx_cdata.bnx_tx_mtag,
2623                             sc->bnx_cdata.bnx_tx_dmamap[idx]);
2624                         m_freem(sc->bnx_cdata.bnx_tx_chain[idx]);
2625                         sc->bnx_cdata.bnx_tx_chain[idx] = NULL;
2626                 }
2627                 sc->bnx_txcnt--;
2628                 BNX_INC(sc->bnx_tx_saved_considx, BGE_TX_RING_CNT);
2629         }
2630
2631         if ((BGE_TX_RING_CNT - sc->bnx_txcnt) >=
2632             (BNX_NSEG_RSVD + BNX_NSEG_SPARE))
2633                 ifq_clr_oactive(&ifp->if_snd);
2634
2635         if (sc->bnx_txcnt == 0)
2636                 ifp->if_timer = 0;
2637
2638         if (!ifq_is_empty(&ifp->if_snd))
2639                 if_devstart(ifp);
2640 }
2641
2642 #ifdef IFPOLL_ENABLE
2643
2644 static void
2645 bnx_npoll(struct ifnet *ifp, struct ifpoll_info *info)
2646 {
2647         struct bnx_softc *sc = ifp->if_softc;
2648
2649         ASSERT_SERIALIZED(ifp->if_serializer);
2650
2651         if (info != NULL) {
2652                 int cpuid = sc->bnx_npoll.ifpc_cpuid;
2653
2654                 info->ifpi_rx[cpuid].poll_func = bnx_npoll_compat;
2655                 info->ifpi_rx[cpuid].arg = NULL;
2656                 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
2657
2658                 if (ifp->if_flags & IFF_RUNNING)
2659                         bnx_disable_intr(sc);
2660                 ifq_set_cpuid(&ifp->if_snd, cpuid);
2661         } else {
2662                 if (ifp->if_flags & IFF_RUNNING)
2663                         bnx_enable_intr(sc);
2664                 ifq_set_cpuid(&ifp->if_snd, sc->bnx_intr_cpuid);
2665         }
2666 }
2667
2668 static void
2669 bnx_npoll_compat(struct ifnet *ifp, void *arg __unused, int cycle)
2670 {
2671         struct bnx_softc *sc = ifp->if_softc;
2672         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2673         uint16_t rx_prod, tx_cons;
2674
2675         ASSERT_SERIALIZED(ifp->if_serializer);
2676
2677         if (sc->bnx_npoll.ifpc_stcount-- == 0) {
2678                 sc->bnx_npoll.ifpc_stcount = sc->bnx_npoll.ifpc_stfrac;
2679                 /*
2680                  * Process link state changes.
2681                  */
2682                 bnx_link_poll(sc);
2683         }
2684
2685         sc->bnx_status_tag = sblk->bge_status_tag;
2686
2687         /*
2688          * Use a load fence to ensure that status_tag is saved
2689          * before rx_prod and tx_cons.
2690          */
2691         cpu_lfence();
2692
2693         rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2694         tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2695
2696         if (sc->bnx_rx_saved_considx != rx_prod)
2697                 bnx_rxeof(sc, rx_prod, cycle);
2698
2699         if (sc->bnx_tx_saved_considx != tx_cons)
2700                 bnx_txeof(sc, tx_cons);
2701
2702         if (sc->bnx_coal_chg)
2703                 bnx_coal_change(sc);
2704 }
2705
2706 #endif  /* IFPOLL_ENABLE */
2707
2708 static void
2709 bnx_intr_legacy(void *xsc)
2710 {
2711         struct bnx_softc *sc = xsc;
2712         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2713
2714         if (sc->bnx_status_tag == sblk->bge_status_tag) {
2715                 uint32_t val;
2716
2717                 val = pci_read_config(sc->bnx_dev, BGE_PCI_PCISTATE, 4);
2718                 if (val & BGE_PCISTAT_INTR_NOTACT)
2719                         return;
2720         }
2721
2722         /*
2723          * NOTE:
2724          * Interrupt will have to be disabled if tagged status
2725          * is used, else interrupt will always be asserted on
2726          * certain chips (at least on BCM5750 AX/BX).
2727          */
2728         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
2729
2730         bnx_intr(sc);
2731 }
2732
2733 static void
2734 bnx_msi(void *xsc)
2735 {
2736         struct bnx_softc *sc = xsc;
2737
2738         /* Disable interrupt first */
2739         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
2740         bnx_intr(sc);
2741 }
2742
2743 static void
2744 bnx_msi_oneshot(void *xsc)
2745 {
2746         bnx_intr(xsc);
2747 }
2748
2749 static void
2750 bnx_intr(struct bnx_softc *sc)
2751 {
2752         struct ifnet *ifp = &sc->arpcom.ac_if;
2753         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
2754         uint16_t rx_prod, tx_cons;
2755         uint32_t status;
2756
2757         sc->bnx_status_tag = sblk->bge_status_tag;
2758         /*
2759          * Use a load fence to ensure that status_tag is saved
2760          * before rx_prod, tx_cons and status.
2761          */
2762         cpu_lfence();
2763
2764         rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
2765         tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
2766         status = sblk->bge_status;
2767
2768         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bnx_link_evt)
2769                 bnx_link_poll(sc);
2770
2771         if (ifp->if_flags & IFF_RUNNING) {
2772                 if (sc->bnx_rx_saved_considx != rx_prod)
2773                         bnx_rxeof(sc, rx_prod, -1);
2774
2775                 if (sc->bnx_tx_saved_considx != tx_cons)
2776                         bnx_txeof(sc, tx_cons);
2777         }
2778
2779         bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
2780
2781         if (sc->bnx_coal_chg)
2782                 bnx_coal_change(sc);
2783 }
2784
2785 static void
2786 bnx_tick(void *xsc)
2787 {
2788         struct bnx_softc *sc = xsc;
2789         struct ifnet *ifp = &sc->arpcom.ac_if;
2790
2791         lwkt_serialize_enter(ifp->if_serializer);
2792
2793         KKASSERT(mycpuid == sc->bnx_stat_cpuid);
2794
2795         bnx_stats_update_regs(sc);
2796
2797         if (sc->bnx_flags & BNX_FLAG_TBI) {
2798                 /*
2799                  * Since in TBI mode auto-polling can't be used we should poll
2800                  * link status manually. Here we register pending link event
2801                  * and trigger interrupt.
2802                  */
2803                 sc->bnx_link_evt++;
2804                 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
2805         } else if (!sc->bnx_link) {
2806                 mii_tick(device_get_softc(sc->bnx_miibus));
2807         }
2808
2809         callout_reset(&sc->bnx_stat_timer, hz, bnx_tick, sc);
2810
2811         lwkt_serialize_exit(ifp->if_serializer);
2812 }
2813
2814 static void
2815 bnx_stats_update_regs(struct bnx_softc *sc)
2816 {
2817         struct ifnet *ifp = &sc->arpcom.ac_if;
2818         struct bge_mac_stats_regs stats;
2819         uint32_t *s;
2820         int i;
2821
2822         s = (uint32_t *)&stats;
2823         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2824                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2825                 s++;
2826         }
2827
2828         IFNET_STAT_SET(ifp, collisions,
2829            (stats.dot3StatsSingleCollisionFrames +
2830            stats.dot3StatsMultipleCollisionFrames +
2831            stats.dot3StatsExcessiveCollisions +
2832            stats.dot3StatsLateCollisions));
2833 }
2834
2835 /*
2836  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2837  * pointers to descriptors.
2838  */
2839 static int
2840 bnx_encap(struct bnx_softc *sc, struct mbuf **m_head0, uint32_t *txidx,
2841     int *segs_used)
2842 {
2843         struct bge_tx_bd *d = NULL;
2844         uint16_t csum_flags = 0, vlan_tag = 0, mss = 0;
2845         bus_dma_segment_t segs[BNX_NSEG_NEW];
2846         bus_dmamap_t map;
2847         int error, maxsegs, nsegs, idx, i;
2848         struct mbuf *m_head = *m_head0, *m_new;
2849
2850         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
2851 #ifdef BNX_TSO_DEBUG
2852                 int tso_nsegs;
2853 #endif
2854
2855                 error = bnx_setup_tso(sc, m_head0, &mss, &csum_flags);
2856                 if (error)
2857                         return error;
2858                 m_head = *m_head0;
2859
2860 #ifdef BNX_TSO_DEBUG
2861                 tso_nsegs = (m_head->m_pkthdr.len /
2862                     m_head->m_pkthdr.tso_segsz) - 1;
2863                 if (tso_nsegs > (BNX_TSO_NSTATS - 1))
2864                         tso_nsegs = BNX_TSO_NSTATS - 1;
2865                 else if (tso_nsegs < 0)
2866                         tso_nsegs = 0;
2867                 sc->bnx_tsosegs[tso_nsegs]++;
2868 #endif
2869         } else if (m_head->m_pkthdr.csum_flags & BNX_CSUM_FEATURES) {
2870                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2871                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2872                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2873                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2874                 if (m_head->m_flags & M_LASTFRAG)
2875                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2876                 else if (m_head->m_flags & M_FRAG)
2877                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2878         }
2879         if (m_head->m_flags & M_VLANTAG) {
2880                 csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
2881                 vlan_tag = m_head->m_pkthdr.ether_vlantag;
2882         }
2883
2884         idx = *txidx;
2885         map = sc->bnx_cdata.bnx_tx_dmamap[idx];
2886
2887         maxsegs = (BGE_TX_RING_CNT - sc->bnx_txcnt) - BNX_NSEG_RSVD;
2888         KASSERT(maxsegs >= BNX_NSEG_SPARE,
2889                 ("not enough segments %d", maxsegs));
2890
2891         if (maxsegs > BNX_NSEG_NEW)
2892                 maxsegs = BNX_NSEG_NEW;
2893
2894         /*
2895          * Pad outbound frame to BGE_MIN_FRAMELEN for an unusual reason.
2896          * The bge hardware will pad out Tx runts to BGE_MIN_FRAMELEN,
2897          * but when such padded frames employ the bge IP/TCP checksum
2898          * offload, the hardware checksum assist gives incorrect results
2899          * (possibly from incorporating its own padding into the UDP/TCP
2900          * checksum; who knows).  If we pad such runts with zeros, the
2901          * onboard checksum comes out correct.
2902          */
2903         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2904             m_head->m_pkthdr.len < BNX_MIN_FRAMELEN) {
2905                 error = m_devpad(m_head, BNX_MIN_FRAMELEN);
2906                 if (error)
2907                         goto back;
2908         }
2909
2910         if ((sc->bnx_flags & BNX_FLAG_SHORTDMA) && m_head->m_next != NULL) {
2911                 m_new = bnx_defrag_shortdma(m_head);
2912                 if (m_new == NULL) {
2913                         error = ENOBUFS;
2914                         goto back;
2915                 }
2916                 *m_head0 = m_head = m_new;
2917         }
2918         if ((m_head->m_pkthdr.csum_flags & CSUM_TSO) == 0 &&
2919             sc->bnx_force_defrag && m_head->m_next != NULL) {
2920                 /*
2921                  * Forcefully defragment mbuf chain to overcome hardware
2922                  * limitation which only support a single outstanding
2923                  * DMA read operation.  If it fails, keep moving on using
2924                  * the original mbuf chain.
2925                  */
2926                 m_new = m_defrag(m_head, MB_DONTWAIT);
2927                 if (m_new != NULL)
2928                         *m_head0 = m_head = m_new;
2929         }
2930
2931         error = bus_dmamap_load_mbuf_defrag(sc->bnx_cdata.bnx_tx_mtag, map,
2932                         m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2933         if (error)
2934                 goto back;
2935         *segs_used += nsegs;
2936
2937         m_head = *m_head0;
2938         bus_dmamap_sync(sc->bnx_cdata.bnx_tx_mtag, map, BUS_DMASYNC_PREWRITE);
2939
2940         for (i = 0; ; i++) {
2941                 d = &sc->bnx_ldata.bnx_tx_ring[idx];
2942
2943                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
2944                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
2945                 d->bge_len = segs[i].ds_len;
2946                 d->bge_flags = csum_flags;
2947                 d->bge_vlan_tag = vlan_tag;
2948                 d->bge_mss = mss;
2949
2950                 if (i == nsegs - 1)
2951                         break;
2952                 BNX_INC(idx, BGE_TX_RING_CNT);
2953         }
2954         /* Mark the last segment as end of packet... */
2955         d->bge_flags |= BGE_TXBDFLAG_END;
2956
2957         /*
2958          * Insure that the map for this transmission is placed at
2959          * the array index of the last descriptor in this chain.
2960          */
2961         sc->bnx_cdata.bnx_tx_dmamap[*txidx] = sc->bnx_cdata.bnx_tx_dmamap[idx];
2962         sc->bnx_cdata.bnx_tx_dmamap[idx] = map;
2963         sc->bnx_cdata.bnx_tx_chain[idx] = m_head;
2964         sc->bnx_txcnt += nsegs;
2965
2966         BNX_INC(idx, BGE_TX_RING_CNT);
2967         *txidx = idx;
2968 back:
2969         if (error) {
2970                 m_freem(*m_head0);
2971                 *m_head0 = NULL;
2972         }
2973         return error;
2974 }
2975
2976 /*
2977  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2978  * to the mbuf data regions directly in the transmit descriptors.
2979  */
2980 static void
2981 bnx_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
2982 {
2983         struct bnx_softc *sc = ifp->if_softc;
2984         struct mbuf *m_head = NULL;
2985         uint32_t prodidx;
2986         int nsegs = 0;
2987
2988         ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
2989
2990         if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
2991                 return;
2992
2993         prodidx = sc->bnx_tx_prodidx;
2994
2995         while (sc->bnx_cdata.bnx_tx_chain[prodidx] == NULL) {
2996                 /*
2997                  * Sanity check: avoid coming within BGE_NSEG_RSVD
2998                  * descriptors of the end of the ring.  Also make
2999                  * sure there are BGE_NSEG_SPARE descriptors for
3000                  * jumbo buffers' or TSO segments' defragmentation.
3001                  */
3002                 if ((BGE_TX_RING_CNT - sc->bnx_txcnt) <
3003                     (BNX_NSEG_RSVD + BNX_NSEG_SPARE)) {
3004                         ifq_set_oactive(&ifp->if_snd);
3005                         break;
3006                 }
3007
3008                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3009                 if (m_head == NULL)
3010                         break;
3011
3012                 /*
3013                  * Pack the data into the transmit ring. If we
3014                  * don't have room, set the OACTIVE flag and wait
3015                  * for the NIC to drain the ring.
3016                  */
3017                 if (bnx_encap(sc, &m_head, &prodidx, &nsegs)) {
3018                         ifq_set_oactive(&ifp->if_snd);
3019                         IFNET_STAT_INC(ifp, oerrors, 1);
3020                         break;
3021                 }
3022
3023                 if (nsegs >= sc->bnx_tx_wreg) {
3024                         /* Transmit */
3025                         bnx_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3026                         nsegs = 0;
3027                 }
3028
3029                 ETHER_BPF_MTAP(ifp, m_head);
3030
3031                 /*
3032                  * Set a timeout in case the chip goes out to lunch.
3033                  */
3034                 ifp->if_timer = 5;
3035         }
3036
3037         if (nsegs > 0) {
3038                 /* Transmit */
3039                 bnx_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
3040         }
3041         sc->bnx_tx_prodidx = prodidx;
3042 }
3043
3044 static void
3045 bnx_init(void *xsc)
3046 {
3047         struct bnx_softc *sc = xsc;
3048         struct ifnet *ifp = &sc->arpcom.ac_if;
3049         uint16_t *m;
3050         uint32_t mode;
3051
3052         ASSERT_SERIALIZED(ifp->if_serializer);
3053
3054         /* Cancel pending I/O and flush buffers. */
3055         bnx_stop(sc);
3056         bnx_reset(sc);
3057         bnx_chipinit(sc);
3058
3059         /*
3060          * Init the various state machines, ring
3061          * control blocks and firmware.
3062          */
3063         if (bnx_blockinit(sc)) {
3064                 if_printf(ifp, "initialization failure\n");
3065                 bnx_stop(sc);
3066                 return;
3067         }
3068
3069         /* Specify MTU. */
3070         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
3071             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
3072
3073         /* Load our MAC address. */
3074         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
3075         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
3076         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
3077
3078         /* Enable or disable promiscuous mode as needed. */
3079         bnx_setpromisc(sc);
3080
3081         /* Program multicast filter. */
3082         bnx_setmulti(sc);
3083
3084         /* Init RX ring. */
3085         if (bnx_init_rx_ring_std(sc)) {
3086                 if_printf(ifp, "RX ring initialization failed\n");
3087                 bnx_stop(sc);
3088                 return;
3089         }
3090
3091         /* Init jumbo RX ring. */
3092         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
3093                 if (bnx_init_rx_ring_jumbo(sc)) {
3094                         if_printf(ifp, "Jumbo RX ring initialization failed\n");
3095                         bnx_stop(sc);
3096                         return;
3097                 }
3098         }
3099
3100         /* Init our RX return ring index */
3101         sc->bnx_rx_saved_considx = 0;
3102
3103         /* Init TX ring. */
3104         bnx_init_tx_ring(sc);
3105
3106         /* Enable TX MAC state machine lockup fix. */
3107         mode = CSR_READ_4(sc, BGE_TX_MODE);
3108         mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
3109         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
3110                 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3111                 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
3112                     (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
3113         }
3114         /* Turn on transmitter */
3115         CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
3116
3117         /* Turn on receiver */
3118         BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3119
3120         /*
3121          * Set the number of good frames to receive after RX MBUF
3122          * Low Watermark has been reached.  After the RX MAC receives
3123          * this number of frames, it will drop subsequent incoming
3124          * frames until the MBUF High Watermark is reached.
3125          */
3126         if (BNX_IS_57765_FAMILY(sc))
3127                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
3128         else
3129                 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
3130
3131         if (sc->bnx_irq_type == PCI_INTR_TYPE_MSI) {
3132                 if (bootverbose) {
3133                         if_printf(ifp, "MSI_MODE: %#x\n",
3134                             CSR_READ_4(sc, BGE_MSI_MODE));
3135                 }
3136         }
3137
3138         /* Tell firmware we're alive. */
3139         BNX_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3140
3141         /* Enable host interrupts if polling(4) is not enabled. */
3142         PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4);
3143 #ifdef IFPOLL_ENABLE
3144         if (ifp->if_flags & IFF_NPOLLING)
3145                 bnx_disable_intr(sc);
3146         else
3147 #endif
3148         bnx_enable_intr(sc);
3149
3150         bnx_ifmedia_upd(ifp);
3151
3152         ifp->if_flags |= IFF_RUNNING;
3153         ifq_clr_oactive(&ifp->if_snd);
3154
3155         callout_reset_bycpu(&sc->bnx_stat_timer, hz, bnx_tick, sc,
3156             sc->bnx_stat_cpuid);
3157 }
3158
3159 /*
3160  * Set media options.
3161  */
3162 static int
3163 bnx_ifmedia_upd(struct ifnet *ifp)
3164 {
3165         struct bnx_softc *sc = ifp->if_softc;
3166
3167         /* If this is a 1000baseX NIC, enable the TBI port. */
3168         if (sc->bnx_flags & BNX_FLAG_TBI) {
3169                 struct ifmedia *ifm = &sc->bnx_ifmedia;
3170
3171                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
3172                         return(EINVAL);
3173
3174                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
3175                 case IFM_AUTO:
3176                         break;
3177
3178                 case IFM_1000_SX:
3179                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
3180                                 BNX_CLRBIT(sc, BGE_MAC_MODE,
3181                                     BGE_MACMODE_HALF_DUPLEX);
3182                         } else {
3183                                 BNX_SETBIT(sc, BGE_MAC_MODE,
3184                                     BGE_MACMODE_HALF_DUPLEX);
3185                         }
3186                         break;
3187                 default:
3188                         return(EINVAL);
3189                 }
3190         } else {
3191                 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3192
3193                 sc->bnx_link_evt++;
3194                 sc->bnx_link = 0;
3195                 if (mii->mii_instance) {
3196                         struct mii_softc *miisc;
3197
3198                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3199                                 mii_phy_reset(miisc);
3200                 }
3201                 mii_mediachg(mii);
3202
3203                 /*
3204                  * Force an interrupt so that we will call bnx_link_upd
3205                  * if needed and clear any pending link state attention.
3206                  * Without this we are not getting any further interrupts
3207                  * for link state changes and thus will not UP the link and
3208                  * not be able to send in bnx_start.  The only way to get
3209                  * things working was to receive a packet and get an RX
3210                  * intr.
3211                  *
3212                  * bnx_tick should help for fiber cards and we might not
3213                  * need to do this here if BNX_FLAG_TBI is set but as
3214                  * we poll for fiber anyway it should not harm.
3215                  */
3216                 BNX_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
3217         }
3218         return(0);
3219 }
3220
3221 /*
3222  * Report current media status.
3223  */
3224 static void
3225 bnx_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3226 {
3227         struct bnx_softc *sc = ifp->if_softc;
3228
3229         if (sc->bnx_flags & BNX_FLAG_TBI) {
3230                 ifmr->ifm_status = IFM_AVALID;
3231                 ifmr->ifm_active = IFM_ETHER;
3232                 if (CSR_READ_4(sc, BGE_MAC_STS) &
3233                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
3234                         ifmr->ifm_status |= IFM_ACTIVE;
3235                 } else {
3236                         ifmr->ifm_active |= IFM_NONE;
3237                         return;
3238                 }
3239
3240                 ifmr->ifm_active |= IFM_1000_SX;
3241                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
3242                         ifmr->ifm_active |= IFM_HDX;
3243                 else
3244                         ifmr->ifm_active |= IFM_FDX;
3245         } else {
3246                 struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3247
3248                 mii_pollstat(mii);
3249                 ifmr->ifm_active = mii->mii_media_active;
3250                 ifmr->ifm_status = mii->mii_media_status;
3251         }
3252 }
3253
3254 static int
3255 bnx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3256 {
3257         struct bnx_softc *sc = ifp->if_softc;
3258         struct ifreq *ifr = (struct ifreq *)data;
3259         int mask, error = 0;
3260
3261         ASSERT_SERIALIZED(ifp->if_serializer);
3262
3263         switch (command) {
3264         case SIOCSIFMTU:
3265                 if ((!BNX_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3266                     (BNX_IS_JUMBO_CAPABLE(sc) &&
3267                      ifr->ifr_mtu > BNX_JUMBO_MTU)) {
3268                         error = EINVAL;
3269                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3270                         ifp->if_mtu = ifr->ifr_mtu;
3271                         if (ifp->if_flags & IFF_RUNNING)
3272                                 bnx_init(sc);
3273                 }
3274                 break;
3275         case SIOCSIFFLAGS:
3276                 if (ifp->if_flags & IFF_UP) {
3277                         if (ifp->if_flags & IFF_RUNNING) {
3278                                 mask = ifp->if_flags ^ sc->bnx_if_flags;
3279
3280                                 /*
3281                                  * If only the state of the PROMISC flag
3282                                  * changed, then just use the 'set promisc
3283                                  * mode' command instead of reinitializing
3284                                  * the entire NIC. Doing a full re-init
3285                                  * means reloading the firmware and waiting
3286                                  * for it to start up, which may take a
3287                                  * second or two.  Similarly for ALLMULTI.
3288                                  */
3289                                 if (mask & IFF_PROMISC)
3290                                         bnx_setpromisc(sc);
3291                                 if (mask & IFF_ALLMULTI)
3292                                         bnx_setmulti(sc);
3293                         } else {
3294                                 bnx_init(sc);
3295                         }
3296                 } else if (ifp->if_flags & IFF_RUNNING) {
3297                         bnx_stop(sc);
3298                 }
3299                 sc->bnx_if_flags = ifp->if_flags;
3300                 break;
3301         case SIOCADDMULTI:
3302         case SIOCDELMULTI:
3303                 if (ifp->if_flags & IFF_RUNNING)
3304                         bnx_setmulti(sc);
3305                 break;
3306         case SIOCSIFMEDIA:
3307         case SIOCGIFMEDIA:
3308                 if (sc->bnx_flags & BNX_FLAG_TBI) {
3309                         error = ifmedia_ioctl(ifp, ifr,
3310                             &sc->bnx_ifmedia, command);
3311                 } else {
3312                         struct mii_data *mii;
3313
3314                         mii = device_get_softc(sc->bnx_miibus);
3315                         error = ifmedia_ioctl(ifp, ifr,
3316                                               &mii->mii_media, command);
3317                 }
3318                 break;
3319         case SIOCSIFCAP:
3320                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3321                 if (mask & IFCAP_HWCSUM) {
3322                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
3323                         if (ifp->if_capenable & IFCAP_TXCSUM)
3324                                 ifp->if_hwassist |= BNX_CSUM_FEATURES;
3325                         else
3326                                 ifp->if_hwassist &= ~BNX_CSUM_FEATURES;
3327                 }
3328                 if (mask & IFCAP_TSO) {
3329                         ifp->if_capenable ^= (mask & IFCAP_TSO);
3330                         if (ifp->if_capenable & IFCAP_TSO)
3331                                 ifp->if_hwassist |= CSUM_TSO;
3332                         else
3333                                 ifp->if_hwassist &= ~CSUM_TSO;
3334                 }
3335                 break;
3336         default:
3337                 error = ether_ioctl(ifp, command, data);
3338                 break;
3339         }
3340         return error;
3341 }
3342
3343 static void
3344 bnx_watchdog(struct ifnet *ifp)
3345 {
3346         struct bnx_softc *sc = ifp->if_softc;
3347
3348         if_printf(ifp, "watchdog timeout -- resetting\n");
3349
3350         bnx_init(sc);
3351
3352         IFNET_STAT_INC(ifp, oerrors, 1);
3353
3354         if (!ifq_is_empty(&ifp->if_snd))
3355                 if_devstart(ifp);
3356 }
3357
3358 /*
3359  * Stop the adapter and free any mbufs allocated to the
3360  * RX and TX lists.
3361  */
3362 static void
3363 bnx_stop(struct bnx_softc *sc)
3364 {
3365         struct ifnet *ifp = &sc->arpcom.ac_if;
3366
3367         ASSERT_SERIALIZED(ifp->if_serializer);
3368
3369         callout_stop(&sc->bnx_stat_timer);
3370
3371         /*
3372          * Disable all of the receiver blocks
3373          */
3374         bnx_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3375         bnx_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3376         bnx_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3377         bnx_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3378         bnx_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3379         bnx_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3380
3381         /*
3382          * Disable all of the transmit blocks
3383          */
3384         bnx_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3385         bnx_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3386         bnx_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3387         bnx_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3388         bnx_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3389         bnx_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3390
3391         /*
3392          * Shut down all of the memory managers and related
3393          * state machines.
3394          */
3395         bnx_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3396         bnx_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3397         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3398         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3399
3400         /* Disable host interrupts. */
3401         bnx_disable_intr(sc);
3402
3403         /*
3404          * Tell firmware we're shutting down.
3405          */
3406         BNX_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3407
3408         /* Free the RX lists. */
3409         bnx_free_rx_ring_std(sc);
3410
3411         /* Free jumbo RX list. */
3412         if (BNX_IS_JUMBO_CAPABLE(sc))
3413                 bnx_free_rx_ring_jumbo(sc);
3414
3415         /* Free TX buffers. */
3416         bnx_free_tx_ring(sc);
3417
3418         sc->bnx_status_tag = 0;
3419         sc->bnx_link = 0;
3420         sc->bnx_coal_chg = 0;
3421
3422         sc->bnx_tx_saved_considx = BNX_TXCONS_UNSET;
3423
3424         ifp->if_flags &= ~IFF_RUNNING;
3425         ifq_clr_oactive(&ifp->if_snd);
3426         ifp->if_timer = 0;
3427 }
3428
3429 /*
3430  * Stop all chip I/O so that the kernel's probe routines don't
3431  * get confused by errant DMAs when rebooting.
3432  */
3433 static void
3434 bnx_shutdown(device_t dev)
3435 {
3436         struct bnx_softc *sc = device_get_softc(dev);
3437         struct ifnet *ifp = &sc->arpcom.ac_if;
3438
3439         lwkt_serialize_enter(ifp->if_serializer);
3440         bnx_stop(sc);
3441         bnx_reset(sc);
3442         lwkt_serialize_exit(ifp->if_serializer);
3443 }
3444
3445 static int
3446 bnx_suspend(device_t dev)
3447 {
3448         struct bnx_softc *sc = device_get_softc(dev);
3449         struct ifnet *ifp = &sc->arpcom.ac_if;
3450
3451         lwkt_serialize_enter(ifp->if_serializer);
3452         bnx_stop(sc);
3453         lwkt_serialize_exit(ifp->if_serializer);
3454
3455         return 0;
3456 }
3457
3458 static int
3459 bnx_resume(device_t dev)
3460 {
3461         struct bnx_softc *sc = device_get_softc(dev);
3462         struct ifnet *ifp = &sc->arpcom.ac_if;
3463
3464         lwkt_serialize_enter(ifp->if_serializer);
3465
3466         if (ifp->if_flags & IFF_UP) {
3467                 bnx_init(sc);
3468
3469                 if (!ifq_is_empty(&ifp->if_snd))
3470                         if_devstart(ifp);
3471         }
3472
3473         lwkt_serialize_exit(ifp->if_serializer);
3474
3475         return 0;
3476 }
3477
3478 static void
3479 bnx_setpromisc(struct bnx_softc *sc)
3480 {
3481         struct ifnet *ifp = &sc->arpcom.ac_if;
3482
3483         if (ifp->if_flags & IFF_PROMISC)
3484                 BNX_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3485         else
3486                 BNX_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3487 }
3488
3489 static void
3490 bnx_dma_free(struct bnx_softc *sc)
3491 {
3492         int i;
3493
3494         /* Destroy RX mbuf DMA stuffs. */
3495         if (sc->bnx_cdata.bnx_rx_mtag != NULL) {
3496                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3497                         bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3498                             sc->bnx_cdata.bnx_rx_std_dmamap[i]);
3499                 }
3500                 bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3501                                    sc->bnx_cdata.bnx_rx_tmpmap);
3502                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3503         }
3504
3505         /* Destroy TX mbuf DMA stuffs. */
3506         if (sc->bnx_cdata.bnx_tx_mtag != NULL) {
3507                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3508                         bus_dmamap_destroy(sc->bnx_cdata.bnx_tx_mtag,
3509                             sc->bnx_cdata.bnx_tx_dmamap[i]);
3510                 }
3511                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_tx_mtag);
3512         }
3513
3514         /* Destroy standard RX ring */
3515         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_std_ring_tag,
3516                            sc->bnx_cdata.bnx_rx_std_ring_map,
3517                            sc->bnx_ldata.bnx_rx_std_ring);
3518
3519         if (BNX_IS_JUMBO_CAPABLE(sc))
3520                 bnx_free_jumbo_mem(sc);
3521
3522         /* Destroy RX return ring */
3523         bnx_dma_block_free(sc->bnx_cdata.bnx_rx_return_ring_tag,
3524                            sc->bnx_cdata.bnx_rx_return_ring_map,
3525                            sc->bnx_ldata.bnx_rx_return_ring);
3526
3527         /* Destroy TX ring */
3528         bnx_dma_block_free(sc->bnx_cdata.bnx_tx_ring_tag,
3529                            sc->bnx_cdata.bnx_tx_ring_map,
3530                            sc->bnx_ldata.bnx_tx_ring);
3531
3532         /* Destroy status block */
3533         bnx_dma_block_free(sc->bnx_cdata.bnx_status_tag,
3534                            sc->bnx_cdata.bnx_status_map,
3535                            sc->bnx_ldata.bnx_status_block);
3536
3537         /* Destroy the parent tag */
3538         if (sc->bnx_cdata.bnx_parent_tag != NULL)
3539                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_parent_tag);
3540 }
3541
3542 static int
3543 bnx_dma_alloc(struct bnx_softc *sc)
3544 {
3545         struct ifnet *ifp = &sc->arpcom.ac_if;
3546         bus_size_t txmaxsz;
3547         int i, error;
3548
3549         /*
3550          * Allocate the parent bus DMA tag appropriate for PCI.
3551          *
3552          * All of the NetExtreme/NetLink controllers have 4GB boundary
3553          * DMA bug.
3554          * Whenever an address crosses a multiple of the 4GB boundary
3555          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3556          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3557          * state machine will lockup and cause the device to hang.
3558          */
3559         error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G,
3560                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3561                                    NULL, NULL,
3562                                    BUS_SPACE_MAXSIZE_32BIT, 0,
3563                                    BUS_SPACE_MAXSIZE_32BIT,
3564                                    0, &sc->bnx_cdata.bnx_parent_tag);
3565         if (error) {
3566                 if_printf(ifp, "could not allocate parent dma tag\n");
3567                 return error;
3568         }
3569
3570         /*
3571          * Create DMA tag and maps for RX mbufs.
3572          */
3573         error = bus_dma_tag_create(sc->bnx_cdata.bnx_parent_tag, 1, 0,
3574                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3575                                    NULL, NULL, MCLBYTES, 1, MCLBYTES,
3576                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
3577                                    &sc->bnx_cdata.bnx_rx_mtag);
3578         if (error) {
3579                 if_printf(ifp, "could not allocate RX mbuf dma tag\n");
3580                 return error;
3581         }
3582
3583         error = bus_dmamap_create(sc->bnx_cdata.bnx_rx_mtag,
3584                                   BUS_DMA_WAITOK, &sc->bnx_cdata.bnx_rx_tmpmap);
3585         if (error) {
3586                 bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3587                 sc->bnx_cdata.bnx_rx_mtag = NULL;
3588                 return error;
3589         }
3590
3591         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3592                 error = bus_dmamap_create(sc->bnx_cdata.bnx_rx_mtag,
3593                                           BUS_DMA_WAITOK,
3594                                           &sc->bnx_cdata.bnx_rx_std_dmamap[i]);
3595                 if (error) {
3596                         int j;
3597
3598                         for (j = 0; j < i; ++j) {
3599                                 bus_dmamap_destroy(sc->bnx_cdata.bnx_rx_mtag,
3600                                         sc->bnx_cdata.bnx_rx_std_dmamap[j]);
3601                         }
3602                         bus_dma_tag_destroy(sc->bnx_cdata.bnx_rx_mtag);
3603                         sc->bnx_cdata.bnx_rx_mtag = NULL;
3604
3605                         if_printf(ifp, "could not create DMA map for RX\n");
3606                         return error;
3607                 }
3608         }
3609
3610         /*
3611          * Create DMA tag and maps for TX mbufs.
3612          */
3613         if (sc->bnx_flags & BNX_FLAG_TSO)
3614                 txmaxsz = IP_MAXPACKET + sizeof(struct ether_vlan_header);
3615         else
3616                 txmaxsz = BNX_JUMBO_FRAMELEN;
3617         error = bus_dma_tag_create(sc->bnx_cdata.bnx_parent_tag, 1, 0,
3618                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3619                                    NULL, NULL,
3620                                    txmaxsz, BNX_NSEG_NEW, PAGE_SIZE,
3621                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
3622                                    BUS_DMA_ONEBPAGE,
3623                                    &sc->bnx_cdata.bnx_tx_mtag);
3624         if (error) {
3625                 if_printf(ifp, "could not allocate TX mbuf dma tag\n");
3626                 return error;
3627         }
3628
3629         for (i = 0; i < BGE_TX_RING_CNT; i++) {
3630                 error = bus_dmamap_create(sc->bnx_cdata.bnx_tx_mtag,
3631                                           BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
3632                                           &sc->bnx_cdata.bnx_tx_dmamap[i]);
3633                 if (error) {
3634                         int j;
3635
3636                         for (j = 0; j < i; ++j) {
3637                                 bus_dmamap_destroy(sc->bnx_cdata.bnx_tx_mtag,
3638                                         sc->bnx_cdata.bnx_tx_dmamap[j]);
3639                         }
3640                         bus_dma_tag_destroy(sc->bnx_cdata.bnx_tx_mtag);
3641                         sc->bnx_cdata.bnx_tx_mtag = NULL;
3642
3643                         if_printf(ifp, "could not create DMA map for TX\n");
3644                         return error;
3645                 }
3646         }
3647
3648         /*
3649          * Create DMA stuffs for standard RX ring.
3650          */
3651         error = bnx_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3652                                     &sc->bnx_cdata.bnx_rx_std_ring_tag,
3653                                     &sc->bnx_cdata.bnx_rx_std_ring_map,
3654                                     (void *)&sc->bnx_ldata.bnx_rx_std_ring,
3655                                     &sc->bnx_ldata.bnx_rx_std_ring_paddr);
3656         if (error) {
3657                 if_printf(ifp, "could not create std RX ring\n");
3658                 return error;
3659         }
3660
3661         /*
3662          * Create jumbo buffer pool.
3663          */
3664         if (BNX_IS_JUMBO_CAPABLE(sc)) {
3665                 error = bnx_alloc_jumbo_mem(sc);
3666                 if (error) {
3667                         if_printf(ifp, "could not create jumbo buffer pool\n");
3668                         return error;
3669                 }
3670         }
3671
3672         /*
3673          * Create DMA stuffs for RX return ring.
3674          */
3675         error = bnx_dma_block_alloc(sc,
3676             BGE_RX_RTN_RING_SZ(sc->bnx_return_ring_cnt),
3677             &sc->bnx_cdata.bnx_rx_return_ring_tag,
3678             &sc->bnx_cdata.bnx_rx_return_ring_map,
3679             (void *)&sc->bnx_ldata.bnx_rx_return_ring,
3680             &sc->bnx_ldata.bnx_rx_return_ring_paddr);
3681         if (error) {
3682                 if_printf(ifp, "could not create RX ret ring\n");
3683                 return error;
3684         }
3685
3686         /*
3687          * Create DMA stuffs for TX ring.
3688          */
3689         error = bnx_dma_block_alloc(sc, BGE_TX_RING_SZ,
3690                                     &sc->bnx_cdata.bnx_tx_ring_tag,
3691                                     &sc->bnx_cdata.bnx_tx_ring_map,
3692                                     (void *)&sc->bnx_ldata.bnx_tx_ring,
3693                                     &sc->bnx_ldata.bnx_tx_ring_paddr);
3694         if (error) {
3695                 if_printf(ifp, "could not create TX ring\n");
3696                 return error;
3697         }
3698
3699         /*
3700          * Create DMA stuffs for status block.
3701          */
3702         error = bnx_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3703                                     &sc->bnx_cdata.bnx_status_tag,
3704                                     &sc->bnx_cdata.bnx_status_map,
3705                                     (void *)&sc->bnx_ldata.bnx_status_block,
3706                                     &sc->bnx_ldata.bnx_status_block_paddr);
3707         if (error) {
3708                 if_printf(ifp, "could not create status block\n");
3709                 return error;
3710         }
3711
3712         return 0;
3713 }
3714
3715 static int
3716 bnx_dma_block_alloc(struct bnx_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3717                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3718 {
3719         bus_dmamem_t dmem;
3720         int error;
3721
3722         error = bus_dmamem_coherent(sc->bnx_cdata.bnx_parent_tag, PAGE_SIZE, 0,
3723                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3724                                     size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3725         if (error)
3726                 return error;
3727
3728         *tag = dmem.dmem_tag;
3729         *map = dmem.dmem_map;
3730         *addr = dmem.dmem_addr;
3731         *paddr = dmem.dmem_busaddr;
3732
3733         return 0;
3734 }
3735
3736 static void
3737 bnx_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3738 {
3739         if (tag != NULL) {
3740                 bus_dmamap_unload(tag, map);
3741                 bus_dmamem_free(tag, addr, map);
3742                 bus_dma_tag_destroy(tag);
3743         }
3744 }
3745
3746 static void
3747 bnx_tbi_link_upd(struct bnx_softc *sc, uint32_t status)
3748 {
3749         struct ifnet *ifp = &sc->arpcom.ac_if;
3750
3751 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3752
3753         /*
3754          * Sometimes PCS encoding errors are detected in
3755          * TBI mode (on fiber NICs), and for some reason
3756          * the chip will signal them as link changes.
3757          * If we get a link change event, but the 'PCS
3758          * encoding error' bit in the MAC status register
3759          * is set, don't bother doing a link check.
3760          * This avoids spurious "gigabit link up" messages
3761          * that sometimes appear on fiber NICs during
3762          * periods of heavy traffic.
3763          */
3764         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3765                 if (!sc->bnx_link) {
3766                         sc->bnx_link++;
3767                         if (sc->bnx_asicrev == BGE_ASICREV_BCM5704) {
3768                                 BNX_CLRBIT(sc, BGE_MAC_MODE,
3769                                     BGE_MACMODE_TBI_SEND_CFGS);
3770                         }
3771                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3772
3773                         if (bootverbose)
3774                                 if_printf(ifp, "link UP\n");
3775
3776                         ifp->if_link_state = LINK_STATE_UP;
3777                         if_link_state_change(ifp);
3778                 }
3779         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3780                 if (sc->bnx_link) {
3781                         sc->bnx_link = 0;
3782
3783                         if (bootverbose)
3784                                 if_printf(ifp, "link DOWN\n");
3785
3786                         ifp->if_link_state = LINK_STATE_DOWN;
3787                         if_link_state_change(ifp);
3788                 }
3789         }
3790
3791 #undef PCS_ENCODE_ERR
3792
3793         /* Clear the attention. */
3794         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3795             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3796             BGE_MACSTAT_LINK_CHANGED);
3797 }
3798
3799 static void
3800 bnx_copper_link_upd(struct bnx_softc *sc, uint32_t status __unused)
3801 {
3802         struct ifnet *ifp = &sc->arpcom.ac_if;
3803         struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3804
3805         mii_pollstat(mii);
3806         bnx_miibus_statchg(sc->bnx_dev);
3807
3808         if (bootverbose) {
3809                 if (sc->bnx_link)
3810                         if_printf(ifp, "link UP\n");
3811                 else
3812                         if_printf(ifp, "link DOWN\n");
3813         }
3814
3815         /* Clear the attention. */
3816         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3817             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3818             BGE_MACSTAT_LINK_CHANGED);
3819 }
3820
3821 static void
3822 bnx_autopoll_link_upd(struct bnx_softc *sc, uint32_t status __unused)
3823 {
3824         struct ifnet *ifp = &sc->arpcom.ac_if;
3825         struct mii_data *mii = device_get_softc(sc->bnx_miibus);
3826
3827         mii_pollstat(mii);
3828
3829         if (!sc->bnx_link &&
3830             (mii->mii_media_status & IFM_ACTIVE) &&
3831             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3832                 sc->bnx_link++;
3833                 if (bootverbose)
3834                         if_printf(ifp, "link UP\n");
3835         } else if (sc->bnx_link &&
3836             (!(mii->mii_media_status & IFM_ACTIVE) ||
3837             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3838                 sc->bnx_link = 0;
3839                 if (bootverbose)
3840                         if_printf(ifp, "link DOWN\n");
3841         }
3842
3843         /* Clear the attention. */
3844         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3845             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3846             BGE_MACSTAT_LINK_CHANGED);
3847 }
3848
3849 static int
3850 bnx_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
3851 {
3852         struct bnx_softc *sc = arg1;
3853
3854         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3855             &sc->bnx_rx_coal_ticks,
3856             BNX_RX_COAL_TICKS_MIN, BNX_RX_COAL_TICKS_MAX,
3857             BNX_RX_COAL_TICKS_CHG);
3858 }
3859
3860 static int
3861 bnx_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
3862 {
3863         struct bnx_softc *sc = arg1;
3864
3865         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3866             &sc->bnx_tx_coal_ticks,
3867             BNX_TX_COAL_TICKS_MIN, BNX_TX_COAL_TICKS_MAX,
3868             BNX_TX_COAL_TICKS_CHG);
3869 }
3870
3871 static int
3872 bnx_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS)
3873 {
3874         struct bnx_softc *sc = arg1;
3875
3876         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3877             &sc->bnx_rx_coal_bds,
3878             BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
3879             BNX_RX_COAL_BDS_CHG);
3880 }
3881
3882 static int
3883 bnx_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS)
3884 {
3885         struct bnx_softc *sc = arg1;
3886
3887         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3888             &sc->bnx_tx_coal_bds,
3889             BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
3890             BNX_TX_COAL_BDS_CHG);
3891 }
3892
3893 static int
3894 bnx_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS)
3895 {
3896         struct bnx_softc *sc = arg1;
3897
3898         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3899             &sc->bnx_rx_coal_bds_int,
3900             BNX_RX_COAL_BDS_MIN, BNX_RX_COAL_BDS_MAX,
3901             BNX_RX_COAL_BDS_INT_CHG);
3902 }
3903
3904 static int
3905 bnx_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS)
3906 {
3907         struct bnx_softc *sc = arg1;
3908
3909         return bnx_sysctl_coal_chg(oidp, arg1, arg2, req,
3910             &sc->bnx_tx_coal_bds_int,
3911             BNX_TX_COAL_BDS_MIN, BNX_TX_COAL_BDS_MAX,
3912             BNX_TX_COAL_BDS_INT_CHG);
3913 }
3914
3915 static int
3916 bnx_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
3917     int coal_min, int coal_max, uint32_t coal_chg_mask)
3918 {
3919         struct bnx_softc *sc = arg1;
3920         struct ifnet *ifp = &sc->arpcom.ac_if;
3921         int error = 0, v;
3922
3923         lwkt_serialize_enter(ifp->if_serializer);
3924
3925         v = *coal;
3926         error = sysctl_handle_int(oidp, &v, 0, req);
3927         if (!error && req->newptr != NULL) {
3928                 if (v < coal_min || v > coal_max) {
3929                         error = EINVAL;
3930                 } else {
3931                         *coal = v;
3932                         sc->bnx_coal_chg |= coal_chg_mask;
3933                 }
3934         }
3935
3936         lwkt_serialize_exit(ifp->if_serializer);
3937         return error;
3938 }
3939
3940 static void
3941 bnx_coal_change(struct bnx_softc *sc)
3942 {
3943         struct ifnet *ifp = &sc->arpcom.ac_if;
3944
3945         ASSERT_SERIALIZED(ifp->if_serializer);
3946
3947         if (sc->bnx_coal_chg & BNX_RX_COAL_TICKS_CHG) {
3948                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
3949                             sc->bnx_rx_coal_ticks);
3950                 DELAY(10);
3951                 CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
3952
3953                 if (bootverbose) {
3954                         if_printf(ifp, "rx_coal_ticks -> %u\n",
3955                                   sc->bnx_rx_coal_ticks);
3956                 }
3957         }
3958
3959         if (sc->bnx_coal_chg & BNX_TX_COAL_TICKS_CHG) {
3960                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
3961                             sc->bnx_tx_coal_ticks);
3962                 DELAY(10);
3963                 CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
3964
3965                 if (bootverbose) {
3966                         if_printf(ifp, "tx_coal_ticks -> %u\n",
3967                                   sc->bnx_tx_coal_ticks);
3968                 }
3969         }
3970
3971         if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_CHG) {
3972                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
3973                             sc->bnx_rx_coal_bds);
3974                 DELAY(10);
3975                 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
3976
3977                 if (bootverbose) {
3978                         if_printf(ifp, "rx_coal_bds -> %u\n",
3979                                   sc->bnx_rx_coal_bds);
3980                 }
3981         }
3982
3983         if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_CHG) {
3984                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
3985                             sc->bnx_tx_coal_bds);
3986                 DELAY(10);
3987                 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
3988
3989                 if (bootverbose) {
3990                         if_printf(ifp, "tx_coal_bds -> %u\n",
3991                                   sc->bnx_tx_coal_bds);
3992                 }
3993         }
3994
3995         if (sc->bnx_coal_chg & BNX_RX_COAL_BDS_INT_CHG) {
3996                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT,
3997                     sc->bnx_rx_coal_bds_int);
3998                 DELAY(10);
3999                 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT);
4000
4001                 if (bootverbose) {
4002                         if_printf(ifp, "rx_coal_bds_int -> %u\n",
4003                             sc->bnx_rx_coal_bds_int);
4004                 }
4005         }
4006
4007         if (sc->bnx_coal_chg & BNX_TX_COAL_BDS_INT_CHG) {
4008                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT,
4009                     sc->bnx_tx_coal_bds_int);
4010                 DELAY(10);
4011                 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT);
4012
4013                 if (bootverbose) {
4014                         if_printf(ifp, "tx_coal_bds_int -> %u\n",
4015                             sc->bnx_tx_coal_bds_int);
4016                 }
4017         }
4018
4019         sc->bnx_coal_chg = 0;
4020 }
4021
4022 static void
4023 bnx_intr_check(void *xsc)
4024 {
4025         struct bnx_softc *sc = xsc;
4026         struct ifnet *ifp = &sc->arpcom.ac_if;
4027         struct bge_status_block *sblk = sc->bnx_ldata.bnx_status_block;
4028
4029         lwkt_serialize_enter(ifp->if_serializer);
4030
4031         KKASSERT(mycpuid == sc->bnx_intr_cpuid);
4032
4033         if ((ifp->if_flags & (IFF_RUNNING | IFF_NPOLLING)) != IFF_RUNNING) {
4034                 lwkt_serialize_exit(ifp->if_serializer);
4035                 return;
4036         }
4037
4038         if (sblk->bge_idx[0].bge_rx_prod_idx != sc->bnx_rx_saved_considx ||
4039             sblk->bge_idx[0].bge_tx_cons_idx != sc->bnx_tx_saved_considx) {
4040                 if (sc->bnx_rx_check_considx == sc->bnx_rx_saved_considx &&
4041                     sc->bnx_tx_check_considx == sc->bnx_tx_saved_considx) {
4042                         if (!sc->bnx_intr_maylose) {
4043                                 sc->bnx_intr_maylose = TRUE;
4044                                 goto done;
4045                         }
4046                         if (bootverbose)
4047                                 if_printf(ifp, "lost interrupt\n");
4048                         bnx_msi(sc);
4049                 }
4050         }
4051         sc->bnx_intr_maylose = FALSE;
4052         sc->bnx_rx_check_considx = sc->bnx_rx_saved_considx;
4053         sc->bnx_tx_check_considx = sc->bnx_tx_saved_considx;
4054
4055 done:
4056         callout_reset(&sc->bnx_intr_timer, BNX_INTR_CKINTVL,
4057             bnx_intr_check, sc);
4058         lwkt_serialize_exit(ifp->if_serializer);
4059 }
4060
4061 static void
4062 bnx_enable_intr(struct bnx_softc *sc)
4063 {
4064         struct ifnet *ifp = &sc->arpcom.ac_if;
4065
4066         lwkt_serialize_handler_enable(ifp->if_serializer);
4067
4068         /*
4069          * Enable interrupt.
4070          */
4071         bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
4072         if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
4073                 /* XXX Linux driver */
4074                 bnx_writembx(sc, BGE_MBX_IRQ0_LO, sc->bnx_status_tag << 24);
4075         }
4076
4077         /*
4078          * Unmask the interrupt when we stop polling.
4079          */
4080         PCI_CLRBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
4081             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
4082
4083         /*
4084          * Trigger another interrupt, since above writing
4085          * to interrupt mailbox0 may acknowledge pending
4086          * interrupt.
4087          */
4088         BNX_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4089
4090         if (sc->bnx_flags & BNX_FLAG_STATUSTAG_BUG) {
4091                 sc->bnx_intr_maylose = FALSE;
4092                 sc->bnx_rx_check_considx = 0;
4093                 sc->bnx_tx_check_considx = 0;
4094
4095                 if (bootverbose)
4096                         if_printf(ifp, "status tag bug workaround\n");
4097
4098                 /* 10ms check interval */
4099                 callout_reset_bycpu(&sc->bnx_intr_timer, BNX_INTR_CKINTVL,
4100                     bnx_intr_check, sc, sc->bnx_intr_cpuid);
4101         }
4102 }
4103
4104 static void
4105 bnx_disable_intr(struct bnx_softc *sc)
4106 {
4107         struct ifnet *ifp = &sc->arpcom.ac_if;
4108
4109         /*
4110          * Mask the interrupt when we start polling.
4111          */
4112         PCI_SETBIT(sc->bnx_dev, BGE_PCI_MISC_CTL,
4113             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
4114
4115         /*
4116          * Acknowledge possible asserted interrupt.
4117          */
4118         bnx_writembx(sc, BGE_MBX_IRQ0_LO, 1);
4119
4120         callout_stop(&sc->bnx_intr_timer);
4121         sc->bnx_intr_maylose = FALSE;
4122         sc->bnx_rx_check_considx = 0;
4123         sc->bnx_tx_check_considx = 0;
4124
4125         sc->bnx_npoll.ifpc_stcount = 0;
4126
4127         lwkt_serialize_handler_disable(ifp->if_serializer);
4128 }
4129
4130 static int
4131 bnx_get_eaddr_mem(struct bnx_softc *sc, uint8_t ether_addr[])
4132 {
4133         uint32_t mac_addr;
4134         int ret = 1;
4135
4136         mac_addr = bnx_readmem_ind(sc, 0x0c14);
4137         if ((mac_addr >> 16) == 0x484b) {
4138                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
4139                 ether_addr[1] = (uint8_t)mac_addr;
4140                 mac_addr = bnx_readmem_ind(sc, 0x0c18);
4141                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
4142                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
4143                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
4144                 ether_addr[5] = (uint8_t)mac_addr;
4145                 ret = 0;
4146         }
4147         return ret;
4148 }
4149
4150 static int
4151 bnx_get_eaddr_nvram(struct bnx_softc *sc, uint8_t ether_addr[])
4152 {
4153         int mac_offset = BGE_EE_MAC_OFFSET;
4154
4155         if (BNX_IS_5717_PLUS(sc)) {
4156                 int f;
4157
4158                 f = pci_get_function(sc->bnx_dev);
4159                 if (f & 1)
4160                         mac_offset = BGE_EE_MAC_OFFSET_5717;
4161                 if (f > 1)
4162                         mac_offset += BGE_EE_MAC_OFFSET_5717_OFF;
4163         } else if (sc->bnx_asicrev == BGE_ASICREV_BCM5906) {
4164                 mac_offset = BGE_EE_MAC_OFFSET_5906;
4165         }
4166
4167         return bnx_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN);
4168 }
4169
4170 static int
4171 bnx_get_eaddr_eeprom(struct bnx_softc *sc, uint8_t ether_addr[])
4172 {
4173         if (sc->bnx_flags & BNX_FLAG_NO_EEPROM)
4174                 return 1;
4175
4176         return bnx_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
4177                                ETHER_ADDR_LEN);
4178 }
4179
4180 static int
4181 bnx_get_eaddr(struct bnx_softc *sc, uint8_t eaddr[])
4182 {
4183         static const bnx_eaddr_fcn_t bnx_eaddr_funcs[] = {
4184                 /* NOTE: Order is critical */
4185                 bnx_get_eaddr_mem,
4186                 bnx_get_eaddr_nvram,
4187                 bnx_get_eaddr_eeprom,
4188                 NULL
4189         };
4190         const bnx_eaddr_fcn_t *func;
4191
4192         for (func = bnx_eaddr_funcs; *func != NULL; ++func) {
4193                 if ((*func)(sc, eaddr) == 0)
4194                         break;
4195         }
4196         return (*func == NULL ? ENXIO : 0);
4197 }
4198
4199 /*
4200  * NOTE: 'm' is not freed upon failure
4201  */
4202 struct mbuf *
4203 bnx_defrag_shortdma(struct mbuf *m)
4204 {
4205         struct mbuf *n;
4206         int found;
4207
4208         /*
4209          * If device receive two back-to-back send BDs with less than
4210          * or equal to 8 total bytes then the device may hang.  The two
4211          * back-to-back send BDs must in the same frame for this failure
4212          * to occur.  Scan mbuf chains and see whether two back-to-back
4213          * send BDs are there.  If this is the case, allocate new mbuf
4214          * and copy the frame to workaround the silicon bug.
4215          */
4216         for (n = m, found = 0; n != NULL; n = n->m_next) {
4217                 if (n->m_len < 8) {
4218                         found++;
4219                         if (found > 1)
4220                                 break;
4221                         continue;
4222                 }
4223                 found = 0;
4224         }
4225
4226         if (found > 1)
4227                 n = m_defrag(m, MB_DONTWAIT);
4228         else
4229                 n = m;
4230         return n;
4231 }
4232
4233 static void
4234 bnx_stop_block(struct bnx_softc *sc, bus_size_t reg, uint32_t bit)
4235 {
4236         int i;
4237
4238         BNX_CLRBIT(sc, reg, bit);
4239         for (i = 0; i < BNX_TIMEOUT; i++) {
4240                 if ((CSR_READ_4(sc, reg) & bit) == 0)
4241                         return;
4242                 DELAY(100);
4243         }
4244 }
4245
4246 static void
4247 bnx_link_poll(struct bnx_softc *sc)
4248 {
4249         uint32_t status;
4250
4251         status = CSR_READ_4(sc, BGE_MAC_STS);
4252         if ((status & sc->bnx_link_chg) || sc->bnx_link_evt) {
4253                 sc->bnx_link_evt = 0;
4254                 sc->bnx_link_upd(sc, status);
4255         }
4256 }
4257
4258 static void
4259 bnx_enable_msi(struct bnx_softc *sc)
4260 {
4261         uint32_t msi_mode;
4262
4263         msi_mode = CSR_READ_4(sc, BGE_MSI_MODE);
4264         msi_mode |= BGE_MSIMODE_ENABLE;
4265         if (sc->bnx_flags & BNX_FLAG_ONESHOT_MSI) {
4266                 /*
4267                  * NOTE:
4268                  * 5718-PG105-R says that "one shot" mode
4269                  * does not work if MSI is used, however,
4270                  * it obviously works.
4271                  */
4272                 msi_mode &= ~BGE_MSIMODE_ONESHOT_DISABLE;
4273         }
4274         CSR_WRITE_4(sc, BGE_MSI_MODE, msi_mode);
4275 }
4276
4277 static uint32_t
4278 bnx_dma_swap_options(struct bnx_softc *sc)
4279 {
4280         uint32_t dma_options;
4281
4282         dma_options = BGE_MODECTL_WORDSWAP_NONFRAME |
4283             BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA;
4284 #if BYTE_ORDER == BIG_ENDIAN
4285         dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
4286 #endif
4287         if (sc->bnx_asicrev == BGE_ASICREV_BCM5720) {
4288                 dma_options |= BGE_MODECTL_BYTESWAP_B2HRX_DATA |
4289                     BGE_MODECTL_WORDSWAP_B2HRX_DATA | BGE_MODECTL_B2HRX_ENABLE |
4290                     BGE_MODECTL_HTX2B_ENABLE;
4291         }
4292         return dma_options;
4293 }
4294
4295 static int
4296 bnx_setup_tso(struct bnx_softc *sc, struct mbuf **mp,
4297     uint16_t *mss0, uint16_t *flags0)
4298 {
4299         struct mbuf *m;
4300         struct ip *ip;
4301         struct tcphdr *th;
4302         int thoff, iphlen, hoff, hlen;
4303         uint16_t flags, mss;
4304
4305         m = *mp;
4306         KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4307
4308         hoff = m->m_pkthdr.csum_lhlen;
4309         iphlen = m->m_pkthdr.csum_iphlen;
4310         thoff = m->m_pkthdr.csum_thlen;
4311
4312         KASSERT(hoff > 0, ("invalid ether header len"));
4313         KASSERT(iphlen > 0, ("invalid ip header len"));
4314         KASSERT(thoff > 0, ("invalid tcp header len"));
4315
4316         if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
4317                 m = m_pullup(m, hoff + iphlen + thoff);
4318                 if (m == NULL) {
4319                         *mp = NULL;
4320                         return ENOBUFS;
4321                 }
4322                 *mp = m;
4323         }
4324         ip = mtodoff(m, struct ip *, hoff);
4325         th = mtodoff(m, struct tcphdr *, hoff + iphlen);
4326
4327         mss = m->m_pkthdr.tso_segsz;
4328         flags = BGE_TXBDFLAG_CPU_PRE_DMA | BGE_TXBDFLAG_CPU_POST_DMA;
4329
4330         ip->ip_len = htons(mss + iphlen + thoff);
4331         th->th_sum = 0;
4332
4333         hlen = (iphlen + thoff) >> 2;
4334         mss |= ((hlen & 0x3) << 14);
4335         flags |= ((hlen & 0xf8) << 7) | ((hlen & 0x4) << 2);
4336
4337         *mss0 = mss;
4338         *flags0 = flags;
4339
4340         return 0;
4341 }