contrib/gcc-5.0/gcc/config/i386/btver2.md

   1 ;; Copyright (C) 2012-2015 Free Software Foundation, Inc.
   2 ;;
   3 ;; This file is part of GCC.
   4 ;;
   5 ;; GCC is free software; you can redistribute it and/or modify
   6 ;; it under the terms of the GNU General Public License as published by
   7 ;; the Free Software Foundation; either version 3, or (at your option)
   8 ;; any later version.
   9 ;;
  10 ;; GCC is distributed in the hope that it will be useful,
  11 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 ;; GNU General Public License for more details.
  14 ;;
  15 ;; You should have received a copy of the GNU General Public License
  16 ;; along with GCC; see the file COPYING3.  If not see
  17 ;; <http://www.gnu.org/licenses/>.
  18
  19 ;; AMD btver2 scheduling
  20
  21 ;; Instructions decoded are that are classifed as direct (fast path single),
  22 ;; double (fast path double) and vector instructions.
  23 ;; Direct instrucions are decoded and convereted into 1 cop
  24 ;; Double instrucions are decoded and converetd into 2 cops
  25 ;; Vector instrucions are microcoded and they generated converted to
  26 ;; 3 or more cops.
  27
  28 (define_attr "btver2_decode" "direct,vector,double"
  29   (const_string "direct"))
  30
  31 (define_attr "btver2_sse_attr" "other,rcp,sqrt,maxmin"
  32   (const_string "other"))
  33
  34 (define_automaton "btver2,btver2_int,btver2_agu,btver2_fp")
  35
  36 ;; Decoder decodes up to two insns (2 fastpath singles) or
  37 ;;(2 fastpath doubles) or combination of both at a cycle.
  38 ;; In case of vector (microded) instruction decoder decodes only one insn
  39 ;; at a cycle .To model that we have 2 "decoder" units.
  40
  41 (define_cpu_unit "btver2-decode0" "btver2")
  42 (define_cpu_unit "btver2-decode1" "btver2")
  43
  44 ;; "me" unit converts the decoded insn into cops.
  45 ;; It can generate upto 2 cops from two fast path singles in cycle x+1,
  46 ;; to model we have two "mes". In case of fast path double it converts
  47 ;; them to 2 cops in cycle x+1. Vector instructions are modelled to block
  48 ;; all decoder units.
  49
  50 (define_cpu_unit "me0" "btver2")
  51 (define_cpu_unit "me1" "btver2")
  52
  53 (define_reservation "btver2-direct" "(btver2-decode0|btver2-decode1),(me0|me1)")
  54
  55 (define_reservation "btver2-double" "(btver2-decode0|btver2-decode1),(me0+me1)")
  56
  57 (define_reservation "btver2-vector" "(btver2-decode0+btver2-decode1),(me0+me1)")
  58
  59 ;; Integer operations
  60 ;; There are 2 ALU pipes
  61
  62 (define_cpu_unit "btver2-ieu0" "btver2_int")
  63 (define_cpu_unit "btver2-ieu1" "btver2_int")
  64
  65 ;; There are 2 AGU pipes one for load and one for store.
  66
  67 (define_cpu_unit "btver2-load"  "btver2_agu")
  68 (define_cpu_unit "btver2-store" "btver2_agu")
  69
  70 ;; ALU operations can take place in ALU pipe0 or pipe1.
  71 (define_reservation "btver2-alu" "(btver2-ieu0|btver2-ieu1)")
  72
  73 ;; MUL and DIV operations can take place in to ALU pipe1.
  74 (define_reservation "btver2-mul" "btver2-ieu1")
  75 (define_reservation "btver2-div" "btver2-ieu1")
  76
  77 ;; vectorpath (microcoded) instructions are single issue instructions.
  78 ;; So, they occupy all the integer units.
  79 (define_reservation "btver2-ivector" "btver2-ieu0+btver2-ieu1+
  80                                       btver2-load+btver2-store")
  81
  82 ;;Floating point pipes.
  83 (define_cpu_unit "btver2-fp0" "btver2_fp")
  84 (define_cpu_unit "btver2-fp1" "btver2_fp")
  85
  86 (define_reservation "btver2-fpa" "btver2-fp0")
  87 (define_reservation "btver2-vimul" "btver2-fp0")
  88 (define_reservation "btver2-valu" "btver2-fp0|btver2-fp1")
  89 (define_reservation "btver2-stc" "btver2-fp1")
  90 (define_reservation "btver2-fpm" "btver2-fp1")
  91
  92 ;; vectorpath (microcoded) instructions are single issue instructions.
  93 ;; So, they occupy all the fp units.
  94 (define_reservation "btver2-fvector" "btver2-fp0+btver2-fp1+
  95                                       btver2-load+btver2-store")
  96
  97 ;; Call instruction
  98 (define_insn_reservation "btver2_call" 2
  99                          (and (eq_attr "cpu" "btver2")
 100                               (eq_attr "type" "call,callv"))
 101                          "btver2-double,btver2-load")
 102
 103 ;; General instructions
 104 ;;
 105
 106 (define_insn_reservation "btver2_push_mem" 4
 107                          (and (eq_attr "cpu" "btver2")
 108                               (and (eq_attr "memory" "load")
 109                                    (eq_attr "type" "push")))
 110                          "btver2-direct,btver2-load,btver2-alu")
 111
 112 (define_insn_reservation "btver2_push" 1
 113                          (and (eq_attr "cpu" "btver2")
 114                               (eq_attr "type" "push"))
 115                          "btver2-direct,btver2-alu")
 116
 117 (define_insn_reservation "btver2_pop_mem" 4
 118                          (and (eq_attr "cpu" "btver2")
 119                               (and (eq_attr "memory" "load")
 120                                    (eq_attr "type" "pop")))
 121                          "btver2-direct,btver2-load,btver2-alu")
 122
 123 (define_insn_reservation "btver2_pop" 1
 124                          (and (eq_attr "cpu" "btver2")
 125                               (eq_attr "type" "pop"))
 126                          "btver2-direct,btver2-alu")
 127
 128 (define_insn_reservation "btver2_leave" 3
 129                          (and (eq_attr "cpu" "btver2")
 130                               (eq_attr "type" "leave"))
 131                          "btver2-double,btver2-alu")
 132
 133 (define_insn_reservation "btver2_lea" 1
 134                          (and (eq_attr "cpu" "btver2")
 135                               (eq_attr "type" "lea"))
 136                          "btver2-direct,btver2-alu")
 137
 138 ;; Integer
 139 (define_insn_reservation "btver2_imul_DI" 6
 140                          (and (eq_attr "cpu" "btver2")
 141                               (and (eq_attr "type" "imul")
 142                                    (and (eq_attr "mode" "DI")
 143                                         (eq_attr "memory" "none,unknown"))))
 144                          "btver2-direct,btver2-mul*4")
 145
 146 (define_insn_reservation "btver2_imul" 3
 147                          (and (eq_attr "cpu" "btver2")
 148                               (and (eq_attr "type" "imul")
 149                                    (eq_attr "memory" "none,unknown")))
 150                          "btver2-direct,btver2-mul")
 151
 152 (define_insn_reservation "btver2_imul_mem_DI" 9
 153                          (and (eq_attr "cpu" "btver2")
 154                               (and (eq_attr "type" "imul")
 155                                    (and (eq_attr "mode" "DI")
 156                                         (eq_attr "memory" "load,both"))))
 157                          "btver2-direct,btver2-load,btver2-mul*4")
 158
 159 (define_insn_reservation "btver2_imul_mem" 6
 160                          (and (eq_attr "cpu" "btver2")
 161                               (and (eq_attr "type" "imul")
 162                                    (eq_attr "memory" "load,both")))
 163                          "btver2-direct,btver2-load,btver2-mul")
 164
 165 (define_insn_reservation "btver2_idiv_DI" 41
 166                             (and (eq_attr "cpu" "btver2")
 167                                  (and (eq_attr "type" "idiv")
 168                                       (and (eq_attr "mode" "DI")
 169                                            (eq_attr "memory" "none,unknown"))))
 170                          "btver2-double,btver2-div")
 171
 172 (define_insn_reservation "btver2_idiv_mem_DI" 44
 173                          (and (eq_attr "cpu" "btver2")
 174                               (and (eq_attr "type" "idiv")
 175                                    (and (eq_attr "mode" "DI")
 176                                         (eq_attr "memory" "load"))))
 177                          "btver2-double,btver2-load,btver2-div")
 178
 179 (define_insn_reservation "btver2_idiv_SI" 25
 180                          (and (eq_attr "cpu" "btver2")
 181                               (and (eq_attr "type" "idiv")
 182                                    (and (eq_attr "mode" "SI")
 183                                         (eq_attr "memory" "none,unknown"))))
 184                          "btver2-double,btver2-div*25")
 185
 186 (define_insn_reservation "btver2_idiv_mem_SI" 28
 187                          (and (eq_attr "cpu" "btver2")
 188                               (and (eq_attr "type" "idiv")
 189                                    (and (eq_attr "mode" "SI")
 190                                         (eq_attr "memory" "load"))))
 191                          "btver2-double,btver2-load,btver2-div*25")
 192
 193 (define_insn_reservation "btver2_idiv_HI" 17
 194                          (and (eq_attr "cpu" "btver2")
 195                               (and (eq_attr "type" "idiv")
 196                                    (and (eq_attr "mode" "HI")
 197                                         (eq_attr "memory" "none,unknown"))))
 198                          "btver2-double,btver2-div*17")
 199
 200 (define_insn_reservation "btver2_idiv_mem_HI" 20
 201                          (and (eq_attr "cpu" "btver2")
 202                               (and (eq_attr "type" "idiv")
 203                                    (and (eq_attr "mode" "HI")
 204                                         (eq_attr "memory" "load"))))
 205                          "btver2-double,btver2-load,btver2-div*17")
 206
 207 (define_insn_reservation "btver2_idiv_QI" 12
 208                          (and (eq_attr "cpu" "btver2")
 209                               (and (eq_attr "type" "idiv")
 210                                    (and (eq_attr "mode" "SI")
 211                                         (eq_attr "memory" "none,unknown"))))
 212                          "btver2-direct,btver2-div*12")
 213
 214 (define_insn_reservation "btver2_idiv_mem_QI" 15
 215                          (and (eq_attr "cpu" "btver2")
 216                               (and (eq_attr "type" "idiv")
 217                                    (and (eq_attr "mode" "SI")
 218                                         (eq_attr "memory" "load"))))
 219                          "btver2-direct,btver2-load,btver2-div*12")
 220
 221 (define_insn_reservation "btver2_str" 7
 222                          (and (eq_attr "cpu" "btver2")
 223                               (and (eq_attr "type" "str")
 224                                    (eq_attr "memory" "load,both,store")))
 225                          "btver2-vector,btver2-ivector")
 226
 227 (define_insn_reservation "btver2_idirect_loadmov" 4
 228                          (and (eq_attr "cpu" "btver2")
 229                               (and (eq_attr "type" "imov")
 230                                    (eq_attr "memory" "load")))
 231                          "btver2-direct,btver2-load,btver2-alu")
 232
 233 (define_insn_reservation "btver2_idirect_load" 4
 234                          (and (eq_attr "cpu" "btver2")
 235                               (and (eq_attr "bdver1_decode" "direct")
 236                                    (and (eq_attr "unit" "integer,unknown")
 237                                         (eq_attr "memory" "load"))))
 238                          "btver2-direct,btver2-load,btver2-alu")
 239
 240 (define_insn_reservation "btver2_idirect_movstore" 4
 241                          (and (eq_attr "cpu" "btver2")
 242                               (and (eq_attr "type" "imov")
 243                                    (eq_attr "memory" "store")))
 244                          "btver2-direct,btver2-alu,btver2-store")
 245
 246 (define_insn_reservation "btver2_idirect_both" 4
 247                          (and (eq_attr "cpu" "btver2")
 248                               (and (eq_attr "bdver1_decode" "direct")
 249                                    (and (eq_attr "unit" "integer,unknown")
 250                                         (eq_attr "memory" "both"))))
 251                          "btver2-direct,btver2-load,btver2-alu,btver2-store")
 252
 253 (define_insn_reservation "btver2_idirect_store" 4
 254                          (and (eq_attr "cpu" "btver2")
 255                               (and (eq_attr "bdver1_decode" "direct")
 256                                    (and (eq_attr "unit" "integer,unknown")
 257                                         (eq_attr "memory" "store"))))
 258                          "btver2-direct,btver2-alu,btver2-store")
 259
 260 ;; Other integer instrucions
 261 (define_insn_reservation "btver2_idirect" 1
 262                          (and (eq_attr "cpu" "btver2")
 263                               (and (eq_attr "btver2_decode" "direct")
 264                                    (and (eq_attr "unit" "integer,unknown")
 265                                         (eq_attr "memory" "none,unknown"))))
 266                          "btver2-direct,btver2-alu")
 267
 268 ;; Floating point instructions
 269 (define_insn_reservation "btver2_fldxf" 19
 270                          (and (eq_attr "cpu" "btver2")
 271                               (and (eq_attr "type" "fmov")
 272                                    (and (eq_attr "memory" "load")
 273                                         (eq_attr "mode" "XF"))))
 274                          "btver2-vector,btver2-load,btver2-fvector*5")
 275
 276 (define_insn_reservation "btver2_fld" 11
 277                          (and (eq_attr "cpu" "btver2")
 278                               (and (eq_attr "type" "fmov")
 279                                    (eq_attr "memory" "load")))
 280                          "btver2-direct,btver2-load,(btver2-fp0|btver2-fp1)")
 281
 282 (define_insn_reservation "btver2_fstxf" 24
 283                          (and (eq_attr "cpu" "btver2")
 284                               (and (eq_attr "type" "fmov")
 285                                    (and (eq_attr "memory" "both")
 286                                         (eq_attr "mode" "XF"))))
 287                          "btver2-vector,btver2-fvector*9,btver2-store")
 288
 289 (define_insn_reservation "btver2_fst" 11
 290                          (and (eq_attr "cpu" "btver2")
 291                               (and (eq_attr "type" "fmov")
 292                                    (eq_attr "memory" "store,both")))
 293                          "btver2-direct,btver2-fp1,btver2-store")
 294
 295 (define_insn_reservation "btver2_fist" 9
 296                          (and (eq_attr "cpu" "btver2")
 297                               (eq_attr "type" "fistp,fisttp"))
 298                          "btver2-direct,btver2-load,btver2-fp1")
 299
 300 (define_insn_reservation "btver2_fmov" 2
 301                          (and (eq_attr "cpu" "btver2")
 302                               (eq_attr "type" "fmov"))
 303                          "btver2-direct,(btver2-fp0|btver2-fp1)")
 304
 305 (define_insn_reservation "btver2_fadd_load" 8
 306                          (and (eq_attr "cpu" "btver2")
 307                               (and (eq_attr "type" "fop")
 308                                    (eq_attr "memory" "load")))
 309                          "btver2-direct,btver2-load,btver2-fp0")
 310
 311 (define_insn_reservation "btver2_fadd" 3
 312                          (and (eq_attr "cpu" "btver2")
 313                               (eq_attr "type" "fop"))
 314                          "btver2-direct,btver2-fp0")
 315
 316 (define_insn_reservation "btver2_fmul_load" 10
 317                          (and (eq_attr "cpu" "btver2")
 318                               (and (eq_attr "type" "fmul")
 319                                    (eq_attr "memory" "load")))
 320                          "btver2-direct,btver2-load,btver2-fp1*3")
 321
 322 (define_insn_reservation "btver2_fmul" 5
 323                          (and (eq_attr "cpu" "btver2")
 324                               (eq_attr "type" "fmul"))
 325                          "btver2-direct,(btver2-fp1*3)")
 326
 327 (define_insn_reservation "btver2_fsgn" 2
 328                          (and (eq_attr "cpu" "btver2")
 329                               (eq_attr "type" "fsgn"))
 330                          "btver2-direct,btver2-fp1*2")
 331
 332 (define_insn_reservation "btver2_fdiv_load" 24
 333                          (and (eq_attr "cpu" "btver2")
 334                               (and (eq_attr "type" "fdiv")
 335                                    (eq_attr "memory" "load")))
 336                          "btver2-direct,btver2-load,btver2-fp1*19")
 337
 338 (define_insn_reservation "btver2_fdiv" 19
 339                          (and (eq_attr "cpu" "btver2")
 340                               (eq_attr "type" "fdiv"))
 341                          "btver2-direct,btver2-fp1*19")
 342
 343 (define_insn_reservation "btver2_fcmov_load" 12
 344                          (and (eq_attr "cpu" "btver2")
 345                               (and (eq_attr "type" "fcmov")
 346                                    (eq_attr "memory" "load")))
 347                          "btver2-vector,btver2-load,(btver2-fp0|btver2-fp1)*7")
 348
 349 (define_insn_reservation "btver2_fcmov" 7
 350                          (and (eq_attr "cpu" "btver2")
 351                               (eq_attr "type" "fcmov"))
 352                          "btver2-vector,(btver2-fp0|btver2-fp1)*7")
 353
 354 (define_insn_reservation "btver2_fcomi_load" 7
 355                          (and (eq_attr "cpu" "btver2")
 356                               (and (eq_attr "type" "fcmp")
 357                                    (and (eq_attr "bdver1_decode" "double")
 358                                         (eq_attr "memory" "load"))))
 359                          "btver2-direct,btver2-load,btver2-fp0*2")
 360
 361 (define_insn_reservation "btver2_fcomi" 2
 362                          (and (eq_attr "cpu" "btver2")
 363                               (and (eq_attr "bdver1_decode" "double")
 364                                    (eq_attr "type" "fcmp")))
 365                          "btver2-direct, btver2-fp0*2")
 366
 367 (define_insn_reservation "btver2_fcom_load" 6
 368                          (and (eq_attr "cpu" "btver2")
 369                               (and (eq_attr "type" "fcmp")
 370                                    (eq_attr "memory" "load")))
 371                          "btver2-direct,btver2-load,btver2-fp0")
 372
 373 (define_insn_reservation "btver2_fcom" 1
 374                          (and (eq_attr "cpu" "btver2")
 375                               (eq_attr "type" "fcmp"))
 376                           "btver2-direct,btver2-fp0")
 377
 378 (define_insn_reservation "btver2_fxch" 1
 379                          (and (eq_attr "cpu" "btver2")
 380                               (eq_attr "type" "fxch"))
 381                          "btver2-direct,btver2-fp1")
 382
 383 ;; SSE AVX maxmin,rcp,sqrt
 384 (define_insn_reservation "btver2_sse_maxmin" 2
 385                          (and (eq_attr "cpu" "btver2")
 386                               (and (eq_attr "mode" "V8SF,V4DF,V2DF,V4SF,SF,DF")
 387                                    (and (eq_attr "memory" "none,unknown")
 388                                         (and (eq_attr "btver2_sse_attr" "maxmin")
 389                                              (eq_attr "type" "sse,sseadd")))))
 390                          "btver2-direct,btver2-fpa")
 391
 392 (define_insn_reservation "btver2_sse_maxmin_mem" 7
 393                          (and (eq_attr "cpu" "btver2")
 394                               (and (eq_attr "mode" "V8SF,V4DF,V2DF,V4SF,SF,DF")
 395                                    (and (eq_attr "memory" "load")
 396                                         (and (eq_attr "btver2_sse_attr" "maxmin")
 397                                              (eq_attr "type" "sse,sseadd")))))
 398                          "btver2-direct,btver2-load,btver2-fpa")
 399
 400 (define_insn_reservation "btver2_sse_rcp" 2
 401                          (and (eq_attr "cpu" "btver2")
 402                               (and (eq_attr "mode" "V4SF,SF")
 403                                    (and (eq_attr "memory" "none,unknown")
 404                                         (and (eq_attr "btver2_sse_attr" "rcp")
 405                                              (eq_attr "type" "sse")))))
 406                          "btver2-direct,btver2-fpm")
 407
 408 (define_insn_reservation "btver2_sse_rcp_mem" 7
 409                          (and (eq_attr "cpu" "btver2")
 410                               (and (eq_attr "mode" "V4SF,SF")
 411                                    (and (eq_attr "memory" "load")
 412                                         (and (eq_attr "btver2_sse_attr" "rcp")
 413                                              (eq_attr "type" "sse")))))
 414                          "btver2-direct,btver2-load,btver2-fpm")
 415
 416 (define_insn_reservation "btver2_avx_rcp" 2
 417                          (and (eq_attr "cpu" "btver2")
 418                               (and (eq_attr "mode" "V8SF")
 419                                    (and (eq_attr "memory" "none,unknown")
 420                                         (and (eq_attr "btver2_sse_attr" "rcp")
 421                                              (eq_attr "type" "sse")))))
 422                          "btver2-double,btver2-fpm*2")
 423
 424 (define_insn_reservation "btver2_avx_rcp_mem" 7
 425                          (and (eq_attr "cpu" "btver2")
 426                               (and (eq_attr "mode" "V8SF")
 427                                    (and (eq_attr "memory" "load")
 428                                         (and (eq_attr "btver2_sse_attr" "rcp")
 429                                              (eq_attr "type" "sse")))))
 430                          "btver2-double,btver2-load,btver2-fpm*2")
 431
 432 (define_insn_reservation "btver2_sse_sqrt_v4sf" 21
 433                          (and (eq_attr "cpu" "btver2")
 434                               (and (eq_attr "mode" "V4SF")
 435                                    (and (eq_attr "memory" "none,unknown")
 436                                         (and (eq_attr "btver2_sse_attr" "sqrt")
 437                                              (eq_attr "type" "sse")))))
 438                          "btver2-direct,btver2-fpm*21")
 439
 440 (define_insn_reservation "btver2_sse_sqrt_v4sf_mem" 26
 441                          (and (eq_attr "cpu" "btver2")
 442                               (and (eq_attr "mode" "V4SF")
 443                                    (and (eq_attr "memory" "load")
 444                                         (and (eq_attr "btver2_sse_attr" "sqrt")
 445                                              (eq_attr "type" "sse")))))
 446                          "btver2-direct,btver2-load,btver2-fpm*21")
 447
 448 (define_insn_reservation "btver2_sse_sqrt_v4df" 54
 449                          (and (eq_attr "cpu" "btver2")
 450                               (and (eq_attr "mode" "V4DF")
 451                                    (and (eq_attr "memory" "none,unknown")
 452                                         (and (eq_attr "btver2_sse_attr" "sqrt")
 453                                              (eq_attr "type" "sse")))))
 454                          "btver2-double,btver2-fpm*54")
 455
 456 (define_insn_reservation "btver2_sse_sqrt_v4df_mem" 59
 457                          (and (eq_attr "cpu" "btver2")
 458                               (and (eq_attr "mode" "V4DF")
 459                                    (and (eq_attr "memory" "load")
 460                                         (and (eq_attr "btver2_sse_attr" "sqrt")
 461                                              (eq_attr "type" "sse")))))
 462                          "btver2-double,btver2-load,btver2-fpm*54")
 463
 464 (define_insn_reservation "btver2_sse_sqrt_sf" 16
 465                          (and (eq_attr "cpu" "btver2")
 466                               (and (eq_attr "mode" "SF")
 467                                    (and (eq_attr "memory" "none,unknown")
 468                                         (and (eq_attr "btver2_sse_attr" "sqrt")
 469                                              (eq_attr "type" "sse")))))
 470                          "btver2-direct,btver2-fpm*16")
 471
 472 (define_insn_reservation "btver2_sse_sqrt_sf_mem" 21
 473                          (and (eq_attr "cpu" "btver2")
 474                               (and (eq_attr "mode" "SF")
 475                                    (and (eq_attr "memory" "load")
 476                                         (and (eq_attr "btver2_sse_attr" "sqrt")
 477                                              (eq_attr "type" "sse")))))
 478                          "btver2-direct,btver2-load,btver2-fpm*16")
 479
 480 (define_insn_reservation "btver2_sse_sqrt_df" 27
 481                          (and (eq_attr "cpu" "btver2")
 482                               (and (eq_attr "mode" "V2DF,DF")
 483                                    (and (eq_attr "memory" "none,unknown")
 484                                         (and (eq_attr "btver2_sse_attr" "sqrt")
 485                                              (eq_attr "type" "sse")))))
 486                          "btver2-direct,btver2-fpm*27")
 487
 488 (define_insn_reservation "btver2_sse_sqrt_df_mem" 32
 489                          (and (eq_attr "cpu" "btver2")
 490                               (and (eq_attr "mode" "V2DF,DF")
 491                                    (and (eq_attr "memory" "load")
 492                                         (and (eq_attr "btver2_sse_attr" "sqrt")
 493                                              (eq_attr "type" "sse")))))
 494                          "btver2-direct,btver2-load,btver2-fpm*27")
 495
 496 (define_insn_reservation "btver2_sse_sqrt_v8sf" 42
 497                          (and (eq_attr "cpu" "btver2")
 498                               (and (eq_attr "mode" "V8SF")
 499                                    (and (eq_attr "memory" "none,unknown")
 500                                         (and (eq_attr "btver2_sse_attr" "sqrt")
 501                                              (eq_attr "type" "sse")))))
 502                          "btver2-double,btver2-fpm*42")
 503
 504 (define_insn_reservation "btver2_sse_sqrt_v8sf_mem" 42
 505                          (and (eq_attr "cpu" "btver2")
 506                               (and (eq_attr "mode" "V8SF")
 507                                    (and (eq_attr "memory" "load")
 508                                         (and (eq_attr "btver2_sse_attr" "sqrt")
 509                                              (eq_attr "type" "sse")))))
 510                          "btver2-double,btver2-load,btver2-fpm*42")
 511
 512 ;; Bitmanipulation instrucions BMI LZCNT POPCNT
 513 (define_insn_reservation "btver2_bmi_reg_direct"   1
 514                          (and (eq_attr "cpu" "btver2")
 515                               (and (eq_attr "btver2_decode" "direct")
 516                                    (and (eq_attr "memory" "none")
 517                                         (eq_attr "type" "bitmanip"))))
 518                          "btver2-direct,btver2-alu")
 519
 520 (define_insn_reservation "btver2_bmi_mem_direct" 4
 521                          (and (eq_attr "cpu" "btver2")
 522                               (and (eq_attr "btver2_decode" "direct")
 523                                    (and (eq_attr "memory" "load")
 524                                         (eq_attr "type" "bitmanip"))))
 525                          "btver2-direct,btver2-load,btver2-alu")
 526
 527 (define_insn_reservation "btver2_bmi_reg_double"  2
 528                          (and (eq_attr "cpu" "btver2")
 529                               (and (eq_attr "btver2_decode" "double")
 530                                    (and (eq_attr "memory" "none")
 531                                         (eq_attr "type" "bitmanip,alu1"))))
 532                          "btver2-double,btver2-alu")
 533
 534 (define_insn_reservation "btver2_bmi_double_store"  5
 535                          (and (eq_attr "cpu" "btver2")
 536                               (and (eq_attr "memory" "store")
 537                                    (and (eq_attr "btver2_decode" "double")
 538                                         (eq_attr "type" "bitmanip,alu1"))))
 539                          "btver2-double,btver2-alu,btver2-store")
 540
 541 (define_insn_reservation "btver2_bmi_double_load" 4
 542                          (and (eq_attr "cpu" "btver2")
 543                               (and (eq_attr "btver2_decode" "double")
 544                                    (and (eq_attr "memory" "load")
 545                                         (eq_attr "type" "bitmanip,alu1"))))
 546                          "btver2-double,btver2-load,btver2-alu")
 547
 548 ;; F16C converts
 549 (define_insn_reservation "btver2_ssecvt_load_direct" 8
 550                          (and (eq_attr "cpu" "btver2")
 551                               (and (eq_attr "mode" "V8SF,V4SF")
 552                                    (and (eq_attr "memory" "load")
 553                                         (and (eq_attr "btver2_decode" "direct")
 554                                              (eq_attr "type" "ssecvt")))))
 555                          "btver2-direct,btver2-load,btver2-stc")
 556
 557 (define_insn_reservation "btver2_ssecvt_store_direct" 8
 558                          (and (eq_attr "cpu" "btver2")
 559                              (and (eq_attr "mode" "V8SF,V4SF")
 560                                   (and (eq_attr "memory" "store")
 561                                         (and (eq_attr "btver2_decode" "direct")
 562                                              (eq_attr "type" "ssecvt")))))
 563                          "btver2-direct,btver2-stc,btver2-store")
 564
 565 (define_insn_reservation "btver2_ssecvt_reg_direct" 3
 566                          (and (eq_attr "cpu" "btver2")
 567                               (and (eq_attr "mode" "V8SF,V4SF")
 568                                    (and (eq_attr "btver2_decode" "direct")
 569                                         (eq_attr "type" "ssecvt"))))
 570                          "btver2-direct,btver2-stc")
 571
 572 (define_insn_reservation "btver2_ssecvt_load_double" 8
 573                          (and (eq_attr "cpu" "btver2")
 574                               (and (eq_attr "mode" "V8SF,V4SF")
 575                                   (and (eq_attr "memory" "load")
 576                                         (and (eq_attr "btver2_decode" "double")
 577                                              (eq_attr "type" "ssecvt")))))
 578                          "btver2-double,btver2-load,btver2-stc*2")
 579
 580 (define_insn_reservation "btver2_ssecvt_reg_double" 3
 581                          (and (eq_attr "cpu" "btver2")
 582                               (and (eq_attr "mode" "V8SF,V4SF")
 583                                    (and (eq_attr "btver2_decode" "double")
 584                                         (eq_attr "type" "ssecvt"))))
 585                          "btver2-double,btver2-stc*2")
 586
 587 (define_insn_reservation "btver2_ssecvt_store_vector" 11
 588                          (and (eq_attr "cpu" "btver2")
 589                               (and (eq_attr "mode" "V8SF,V4SF")
 590                                    (and (eq_attr "memory" "store")
 591                                         (and (eq_attr "btver2_decode" "vector")
 592                                              (eq_attr "type" "ssecvt")))))
 593                          "btver2-vector,btver2-stc,(btver2-fpa|btver2-fpm),btver2-store")
 594
 595 (define_insn_reservation "btver2_ssecvt_reg_vector" 6
 596                          (and (eq_attr "cpu" "btver2")
 597                               (and (eq_attr "mode" "V8SF,V4SF")
 598                                    (and (eq_attr "btver2_decode" "vector")
 599                                         (eq_attr "type" "ssecvt"))))
 600                          "btver2-vector,btver2-stc,(btver2-fpa|btver2-fpm)")
 601
 602 ;; avx256 adds
 603 (define_insn_reservation "btver2_avx_add_load_256" 8
 604                          (and (eq_attr "cpu" "btver2")
 605                               (and (eq_attr "mode" "V4DF,V8SF")
 606                                    (and (eq_attr "memory" "load")
 607                                         (eq_attr "type" "sseadd,sseadd1"))))
 608                          "btver2-double,btver2-load,btver2-fpa")
 609
 610 (define_insn_reservation "btver2_avx_add_reg_256" 3
 611                          (and (eq_attr "cpu" "btver2")
 612                               (and (eq_attr "mode" "V4DF,V8SF")
 613                                    (and (eq_attr "memory" "none,unknown")
 614                                         (eq_attr "type" "sseadd,sseadd1"))))
 615                          "btver2-double,btver2-fpa")
 616
 617 ;; avx256 logs
 618 (define_insn_reservation "btver2_avx_load_log" 6
 619                          (and (eq_attr "cpu" "btver2")
 620                               (and (eq_attr "mode" "V4DF,V8SF")
 621                                    (and (eq_attr "memory" "load")
 622                                         (and (eq_attr "btver2_decode" "!vector")
 623                                              (eq_attr "type" "sselog,sselog1")))))
 624                          "btver2-double,btver2-load,(btver2-fpa|btver2-fpm)")
 625
 626 (define_insn_reservation "btver2_avx_reg_log" 1
 627                          (and (eq_attr "cpu" "btver2")
 628                               (and (eq_attr "mode" "V4DF,V8SF")
 629                                    (and (eq_attr "memory" "none,unknown")
 630                                         (and (eq_attr "btver2_decode" "!vector")
 631                                              (eq_attr "type" "sselog,sselog1")))))
 632                          "btver2-double,(btver2-fpa|btver2-fpm)")
 633
 634 ;; avx256 sse
 635
 636 (define_insn_reservation "btver2_avx_load_sse" 6
 637                          (and (eq_attr "cpu" "btver2")
 638                               (and (eq_attr "mode" "V4DF,V8SF")
 639                                    (and (eq_attr "memory" "load")
 640                                         (and (eq_attr "btver2_decode" "!vector")
 641                                              (eq_attr "type" "sse")))))
 642                          "btver2-double,btver2-load,(btver2-fpa|btver2-fpm)")
 643
 644 (define_insn_reservation "btver2_avx_reg_sse" 1
 645                          (and (eq_attr "cpu" "btver2")
 646                               (and (eq_attr "mode" "V4DF,V8SF")
 647                                    (and (eq_attr "memory" "none,unknown")
 648                                         (and (eq_attr "btver2_decode" "!vector")
 649                                              (eq_attr "type" "sse")))))
 650                          "btver2-double,(btver2-fpa|btver2-fpm)")
 651
 652 ;; avx256 moves
 653 (define_insn_reservation "btver2_avx_load_int_mov" 6
 654                          (and (eq_attr "cpu" "btver2")
 655                               (and (eq_attr "mode" "OI")
 656                                    (and (eq_attr "memory" "load")
 657                                         (eq_attr "type" "ssemov"))))
 658                          "btver2-double,btver2-load,btver2-valu")
 659
 660 (define_insn_reservation "btver2_avx_store_int_mov" 6
 661                          (and (eq_attr "cpu" "btver2")
 662                               (and (eq_attr "mode" "OI")
 663                                    (and (eq_attr "memory" "store")
 664                                         (eq_attr "type" "ssemov"))))
 665                          "btver2-double,btver2-valu,btver2-store")
 666
 667 (define_insn_reservation "btver2_avx_int_mov" 1
 668                          (and (eq_attr "cpu" "btver2")
 669                               (and (eq_attr "mode" "OI")
 670                                    (and (eq_attr "memory" "none,unknown")
 671                                         (eq_attr "type" "ssemov"))))
 672                          "btver2-double,btver2-valu")
 673
 674 (define_insn_reservation "btver2_avx_load_from_vectors" 6
 675                          (and (eq_attr "cpu" "btver2")
 676                               (and (eq_attr "mode" "V8SF,V4DF")
 677                                    (and (ior ( match_operand:V4SF 1 "memory_operand")
 678                                              ( match_operand:V2DF 1 "memory_operand"))
 679                                         (and (eq_attr "memory" "load")
 680                                              (eq_attr "type" "ssemov")))))
 681                          "btver2-double,btver2-load,(btver2-fpa|btver2-fpm)")
 682
 683 (define_insn_reservation "btver2_avx_loads_from_scalar" 6
 684                          (and (eq_attr "cpu" "btver2")
 685                               (and (eq_attr "mode" "V8SF,V4DF")
 686                                    (and (ior ( match_operand:SF 1 "memory_operand")
 687                                              ( match_operand:DF 1 "memory_operand"))
 688                                         (and (eq_attr "memory" "load")
 689                                              (eq_attr "type" "ssemov")))))
 690                          "btver2-double,btver2-load,(btver2-fpa|btver2-fpm)*2")
 691
 692 (define_insn_reservation "btver2_avx_store_move" 6
 693                          (and (eq_attr "cpu" "btver2")
 694                               (and (eq_attr "mode" "V4DF,V8SF")
 695                                    (and (eq_attr "memory" "store")
 696                                         (and (eq_attr "btver2_decode" "!vector")
 697                                              (eq_attr "type" "ssemov")))))
 698                          "btver2-double,(btver2-fpa|btver2-fpm),btver2-store")
 699
 700 (define_insn_reservation "btver2_avx_load_move" 6
 701                          (and (eq_attr "cpu" "btver2")
 702                               (and (eq_attr "mode" "V4DF,V8SF")
 703                                    (and (eq_attr "memory" "load")
 704                                         (and (eq_attr "btver2_decode" "!vector")
 705                                              (eq_attr "type" "ssemov")))))
 706                          "btver2-double,btver2-load,(btver2-fpa|btver2-fpm)")
 707
 708 (define_insn_reservation "btver2_avx_reg_move" 1
 709                          (and (eq_attr "cpu" "btver2")
 710                               (and (eq_attr "mode" "V4DF,V8SF")
 711                                    (and (eq_attr "memory" "none,unknown")
 712                                         (and (eq_attr "btver2_decode" "!vector")
 713                                              (eq_attr "type" "ssemov")))))
 714                          "btver2-double,(btver2-fpa|btver2-fpm)")
 715 ;; avx256 cmps
 716 (define_insn_reservation "btver2_avx_load_cmp" 7
 717                          (and (eq_attr "cpu" "btver2")
 718                               (and (eq_attr "mode" "V4DF,V8SF")
 719                                    (and (eq_attr "memory" "load")
 720                                         (eq_attr "type" "ssecmp"))))
 721                          "btver2-double,btver2-load,(btver2-fpa|btver2-fpm)*2")
 722
 723 (define_insn_reservation "btver2_avx_cmp" 2
 724                          (and (eq_attr "cpu" "btver2")
 725                               (and (eq_attr "mode" "V4DF,V8SF")
 726                                    (and (eq_attr "memory" "none,unknown")
 727                                         (eq_attr "type" "ssecmp"))))
 728                          "btver2-double,(btver2-fpa|btver2-fpm)*2")
 729
 730 ;; ssecvts 256
 731 (define_insn_reservation "btver2_ssecvt_256_load" 8
 732                          (and (eq_attr "cpu" "btver2")
 733                               (and (eq_attr "mode" "V4DF,OI")
 734                                    (and (eq_attr "memory" "none,unknown")
 735                                         (and (eq_attr "btver2_decode" "!vector")
 736                                              (eq_attr "type" "ssecvt")))))
 737                          "btver2-double,btver2-load,btver2-stc*2")
 738
 739 (define_insn_reservation "btver2_ssecvt_256" 3
 740                          (and (eq_attr "cpu" "btver2")
 741                               (and (eq_attr "mode" "V4DF,OI")
 742                                    (and (eq_attr "memory" "none,unknown")
 743                                         (and (eq_attr "btver2_decode" "!vector")
 744                                              (eq_attr "type" "ssecvt")))))
 745                          "btver2-double,btver2-stc*2")
 746
 747 (define_insn_reservation "btver2_ssecvt_256_vector_load" 11
 748                          (and (eq_attr "cpu" "btver2")
 749                               (and (eq_attr "mode" "V4DF,OI")
 750                                    (and (eq_attr "memory" "none,unknown")
 751                                         (and (eq_attr "btver2_decode" "vector")
 752                                              (eq_attr "type" "ssecvt")))))
 753                          "btver2-vector,btver2-load,btver2-stc*2,(btver2-fpa|btver2-fpm)")
 754
 755 (define_insn_reservation "btver2_ssecvt_256_vector" 6
 756                          (and (eq_attr "cpu" "btver2")
 757                               (and (eq_attr "mode" "V4DF,OI")
 758                                    (and (eq_attr "memory" "none,unknown")
 759                                         (and (eq_attr "btver2_decode" "vector")
 760                                              (eq_attr "type" "ssecvt")))))
 761                          "btver2-vector,btver2-stc*2,(btver2-fpa|btver2-fpm)")
 762
 763 ;; avx256 divides
 764 (define_insn_reservation "btver2_avx_load_div" 43
 765                          (and (eq_attr "cpu" "btver2")
 766                               (and (eq_attr "mode" "V4DF,V8SF")
 767                                    (and (eq_attr "memory" "load")
 768                                         (and (eq_attr "btver2_decode" "!vector")
 769                                              (eq_attr "type" "ssediv")))))
 770                          "btver2-double,btver2-load,btver2-fpm*38")
 771
 772 (define_insn_reservation "btver2_avx_div" 38
 773                          (and (eq_attr "cpu" "btver2")
 774                               (and (eq_attr "mode" "V4DF,V8SF")
 775                                    (and (eq_attr "memory" "none,unknown")
 776                                         (and (eq_attr "btver2_decode" "!vector")
 777                                              (eq_attr "type" "ssediv")))))
 778                          "btver2-double,btver2-fpm*38")
 779
 780 ;; avx256  multiply
 781
 782 (define_insn_reservation "btver2_avx_mul_load_pd" 9
 783                          (and (eq_attr "cpu" "btver2")
 784                               (and (eq_attr "mode" "V4DF")
 785                                    (and (eq_attr "memory" "load")
 786                                         (and (eq_attr "btver2_decode" "!vector")
 787                                              (eq_attr "type" "ssemul")))))
 788                         "btver2-double,btver2-load,btver2-fpm*4")
 789
 790 (define_insn_reservation "btver2_avx_mul_load_ps" 7
 791                          (and (eq_attr "cpu" "btver2")
 792                               (and (eq_attr "mode" "V8SF")
 793                                    (and (eq_attr "memory" "load")
 794                                         (and (eq_attr "btver2_decode" "!vector")
 795                                              (eq_attr "type" "ssemul")))))
 796                          "btver2-double,btver2-load,btver2-fpm*2")
 797
 798
 799 (define_insn_reservation "btver2_avx_mul_256_pd" 4
 800                          (and (eq_attr "cpu" "btver2")
 801                               (and (eq_attr "mode" "V4DF")
 802                                    (and (eq_attr "memory" "none,unknown")
 803                                         (and (eq_attr "btver2_decode" "!vector")
 804                                              (eq_attr "type" "ssemul")))))
 805                          "btver2-double,btver2-fpm*4")
 806
 807 (define_insn_reservation "btver2_avx_mul_256_ps" 2
 808                          (and (eq_attr "cpu" "btver2")
 809                               (and (eq_attr "mode" "V8SF")
 810                                    (and (eq_attr "memory" "none,unknown")
 811                                         (and (eq_attr "btver2_decode" "!vector")
 812                                              (eq_attr "type" "ssemul")))))
 813                          "btver2-double,btver2-fpm*2")
 814
 815 (define_insn_reservation "btver2_avx_dpps_load_ps" 17
 816                          (and (eq_attr "cpu" "btver2")
 817                               (and (eq_attr "mode" "V8SF")
 818                                    (and (eq_attr "memory" "load")
 819                                         (and (eq_attr "btver2_decode" "vector")
 820                                              (eq_attr "type" "ssemul")))))
 821                          "btver2-vector,btver2-fpm*6,btver2-fpa*6")
 822
 823 (define_insn_reservation "btver2_avx_dpps_ps" 12
 824                          (and (eq_attr "cpu" "btver2")
 825                               (and (eq_attr "mode" "V8SF")
 826                                    (and (eq_attr "memory" "none,unknown")
 827                                         (and (eq_attr "btver2_decode" "vector")
 828                                              (eq_attr "type" "ssemul")))))
 829                          "btver2-vector,btver2-fpm*6,btver2-fpa*6")
 830
 831 ;; AES/CLMUL
 832
 833 (define_insn_reservation "btver2_aes_double" 3
 834                          (and (eq_attr "cpu" "btver2")
 835                               (and (match_operand:V2DI 0 "register_operand")
 836                                    (and (eq_attr "memory" "none,unknown")
 837                                         (and (eq_attr "btver2_decode" "double")
 838                                              (eq_attr "type" "sselog1")))))
 839                          "btver2-double,btver2-valu,btver2-vimul")
 840
 841 (define_insn_reservation "btver2_aes_direct" 2
 842                          (and (eq_attr "cpu" "btver2")
 843                               (and (match_operand:V2DI 0 "register_operand")
 844                                    (and (eq_attr "memory" "none,unknown")
 845                                         (and (eq_attr "btver2_decode" "direct")
 846                                              (eq_attr "type" "sselog1")))))
 847                          "btver2-direct,btver2-vimul")
 848
 849 ;; AVX128 SSE4* SSSE3 SSE3* SSE2 SSE instructions
 850
 851 (define_insn_reservation "btver2_sseint_load_direct" 6
 852                          (and (eq_attr "cpu" "btver2")
 853                               (and (eq_attr "mode" "TI")
 854                                    (and (eq_attr "memory" "load")
 855                                         (and (eq_attr "btver2_decode" "direct")
 856                                              (eq_attr "type" "sse,ssecmp,sseiadd")))))
 857                          "btver2-direct,btver2-load,btver2-valu")
 858
 859 (define_insn_reservation "btver2_sseint_direct" 1
 860                          (and (eq_attr "cpu" "btver2")
 861                               (and (eq_attr "mode" "TI")
 862                                    (and (eq_attr "memory" "none,unknown")
 863                                         (and (eq_attr "btver2_decode" "direct")
 864                                              (eq_attr "type" "sse,ssecmp,sseiadd")))))
 865                          "btver2-direct,btver2-valu")
 866
 867 (define_insn_reservation "btver2_sselog_direct" 1
 868                          (and (eq_attr "cpu" "btver2")
 869                               (and (eq_attr "mode" "V2DF,V4SF")
 870                                    (and (eq_attr "memory" "none,unknown")
 871                                         (and (eq_attr "btver2_decode" "direct")
 872                                              (eq_attr "type" "sse,sselog")))))
 873                          "btver2-direct,(btver2-fpa|btver2-fpm)")
 874
 875 (define_insn_reservation "btver2_sselog_load_direct" 6
 876                          (and (eq_attr "cpu" "btver2")
 877                               (and (eq_attr "mode" "V2DF,V4SF")
 878                                    (and (eq_attr "memory" "load")
 879                                         (and (eq_attr "btver2_decode" "direct")
 880                                              (eq_attr "type" "sse,sselog")))))
 881                          "btver2-direct,btver2-load,(btver2-fpa|btver2-fpm)")
 882
 883 (define_insn_reservation "btver2_intext_reg_128" 3
 884                          (and (eq_attr "cpu" "btver2")
 885                               (and (eq_attr "mode" "SF,QI,SI,HI,SI")
 886                                    (and (eq_attr "memory" "none,unknown")
 887                                         (and (eq_attr "btver2_decode" "direct")
 888                                              (eq_attr "type" "sselog")))))
 889                          "btver2-direct,btver2-fpa")
 890
 891 (define_insn_reservation "btver2_sse_mov_direct" 1
 892                          (and (eq_attr "cpu" "btver2")
 893                               (and (eq_attr "mode" "V2DF,V4SF")
 894                                    (and (eq_attr "memory" "none,unknown")
 895                                         (and (eq_attr "btver2_decode" "direct")
 896                                              (eq_attr "type" "ssemov")))))
 897                          "btver2-direct,(btver2-fpa|btver2-fpm)")
 898
 899 (define_insn_reservation "btver2_sse_mov_vector" 2
 900                          (and (eq_attr "cpu" "btver2")
 901                               (and (eq_attr "mode" "V2DF,V4SF")
 902                                    (and (eq_attr "memory" "none,unknown")
 903                                         (and (eq_attr "btver2_decode" "vector")
 904                                              (eq_attr "type" "ssemov")))))
 905                          "btver2-vector,(btver2-fpa|btver2-fpm)*2")
 906
 907 (define_insn_reservation "btver2_ssecomi_load_128" 8
 908                          (and (eq_attr "cpu" "btver2")
 909                               (and (eq_attr "mode" "TI")
 910                                    (and (eq_attr "memory" "load")
 911                                         (and (eq_attr "btver2_decode" "!vector")
 912                                              (eq_attr "type" "ssecomi")))))
 913                          "btver2-direct,btver2-load,btver2-fpa")
 914
 915 (define_insn_reservation "btver2_ssecomi_reg_128" 3
 916                          (and (eq_attr "cpu" "btver2")
 917                               (and (eq_attr "mode" "TI")
 918                                    (and (eq_attr "memory" "none,unknown")
 919                                         (and (eq_attr "btver2_decode" "!vector")
 920                                              (eq_attr "type" "ssecomi")))))
 921                          "btver2-direct,btver2-fpa")
 922
 923 (define_insn_reservation "btver2_ssemul_load_v2df" 14
 924                          (and (eq_attr "cpu" "btver2")
 925                               (and (eq_attr "mode" "V2DF")
 926                                    (and (eq_attr "memory" "load")
 927                                         (and (eq_attr "btver2_decode" "vector")
 928                                              (eq_attr "type" "ssemul")))))
 929                          "btver2-vector,btver2-load,btver2-fpm*2,btver2-fpa")
 930
 931 (define_insn_reservation "btver2_ssemul_reg_v2df" 9
 932                          (and (eq_attr "cpu" "btver2")
 933                               (and (eq_attr "mode" "V2DF")
 934                                    (and (eq_attr "memory" "none,unknown")
 935                                         (and (eq_attr "btver2_decode" "vector")
 936                                              (eq_attr "type" "ssemul")))))
 937                          "btver2-vector,btver2-fpm*2,btver2-fpa")
 938
 939 (define_insn_reservation "btver2_ssemul_load_v4sf" 16
 940                          (and (eq_attr "cpu" "btver2")
 941                               (and (eq_attr "mode" "V4SF")
 942                                    (and (eq_attr "memory" "none,unknown")
 943                                         (and (eq_attr "btver2_decode" "vector")
 944                                              (eq_attr "type" "ssemul")))))
 945                         "btver2-vector,btver2-load,btver2-fpm*3,btver2-fpa*2")
 946
 947 (define_insn_reservation "btver2_ssemul_reg_v4sf" 11
 948                          (and (eq_attr "cpu" "btver2")
 949                               (and (eq_attr "mode" "V4SF")
 950                                    (and (eq_attr "memory" "none,unknown")
 951                                         (and (eq_attr "btver2_decode" "vector")
 952                                              (eq_attr "type" "ssemul")))))
 953                          "btver2-vector,btver2-fpm*3,btver2-fpa*2")
 954
 955 (define_insn_reservation "btver2_sse_store_vectmov" 8
 956                          (and (eq_attr "cpu" "btver2")
 957                               (and (eq_attr "memory" "load")
 958                                    (and (eq_attr "btver2_decode" "vector")
 959                                         (eq_attr "type" "ssemov"))))
 960                         "btver2-vector,btver2-valu*3,btver2-store")
 961
 962 (define_insn_reservation "btver2_sse_load_vectmov" 8
 963                          (and (eq_attr "cpu" "btver2")
 964                               (and (eq_attr "memory" "load")
 965                                    (and (eq_attr "btver2_decode" "vector")
 966                                         (eq_attr "type" "ssemov"))))
 967                          "btver2-vector,btver2-load,btver2-valu*3")
 968
 969 (define_insn_reservation "btver2_sse_vectmov" 3
 970                          (and (eq_attr "cpu" "btver2")
 971                               (and (eq_attr "memory" "none,unknown")
 972                                    (and (eq_attr "btver2_decode" "vector")
 973                                         (eq_attr "type" "ssemov"))))
 974                          "btver2-vector,btver2-valu*3")
 975
 976
 977 (define_insn_reservation "btver2_sseimul" 2
 978                          (and (eq_attr "cpu" "btver2")
 979                               (and (eq_attr "memory" "none,unknown")
 980                                    (and (eq_attr "btver2_decode" "direct")
 981                                         (eq_attr "type" "sseimul"))))
 982                          "btver2-direct,btver2-vimul")
 983
 984 (define_insn_reservation "btver2_sseimul_load" 7
 985                          (and (eq_attr "cpu" "btver2")
 986                               (and (eq_attr "memory" "load")
 987                                    (and (eq_attr "btver2_decode" "direct")
 988                                         (eq_attr "type" "sseimul"))))
 989                          "btver2-direct,btver2-load,btver2-vimul")
 990
 991 (define_insn_reservation "btver2_sseimul_load_vect" 9
 992                          (and (eq_attr "cpu" "btver2")
 993                               (and (eq_attr "memory" "load")
 994                                    (and (eq_attr "btver2_decode" "vector")
 995                                         (eq_attr "type" "sseimul"))))
 996                          "btver2-vector,btver2-load,btver2-vimul*2,btver2-valu")
 997
 998 (define_insn_reservation "btver2_sseimul_vect" 4
 999                          (and (eq_attr "cpu" "btver2")
1000                               (and (eq_attr "memory" "none,unknown")
1001                                    (and (eq_attr "btver2_decode" "vector")
1002                                         (eq_attr "type" "sseimul"))))
1003                          "btver2-vector,btver2-vimul*2,btver2-valu")
1004
1005 (define_insn_reservation "btver2_sseins" 3
1006                          (and (eq_attr "cpu" "btver2")
1007                               (and (eq_attr "memory" "none,unknown")
1008                                    (eq_attr "type" "sseins")))
1009                          "btver2-vector,btver2-valu*3")
1010
1011 (define_insn_reservation "btver2_sseishft_load" 6
1012                          (and (eq_attr "cpu" "btver2")
1013                               (and (eq_attr "memory" "load")
1014                                    (and (eq_attr "btver2_decode" "direct")
1015                                         (eq_attr "type" "sseishft"))))
1016                          "btver2-direct,btver2-load,btver2-valu")
1017
1018 (define_insn_reservation "btver2_sseishft_direct" 1
1019                          (and (eq_attr "cpu" "btver2")
1020                               (and (eq_attr "memory" "none,unknown")
1021                                    (and (eq_attr "btver2_decode" "direct")
1022                                         (eq_attr "type" "sseishft"))))
1023                          "btver2-direct,btver2-valu")
1024
1025 (define_insn_reservation "btver2_sselog1_load" 6
1026                          (and (eq_attr "cpu" "btver2")
1027                               (and (eq_attr "mode"  "!V8SF,!V4DF")
1028                                    (and (eq_attr "memory" "load")
1029                                         (and (eq_attr "btver2_decode" "direct")
1030                                              (eq_attr "type" "sselog1")))))
1031                          "btver2-direct,btver2-load,btver2-valu")
1032
1033 (define_insn_reservation "btver2_sselog1_direct" 1
1034                          (and (eq_attr "cpu" "btver2")
1035                               (and (eq_attr "mode"  "!V8SF,!V4DF")
1036                                    (and (eq_attr "memory" "none,unknown")
1037                                         (and (eq_attr "btver2_decode" "direct")
1038                                              (eq_attr "type" "sselog1")))))
1039                          "btver2-direct,btver2-valu")
1040
1041 (define_insn_reservation "btver2_sselog1_vector_load" 7
1042                          (and (eq_attr "cpu" "btver2")
1043                               (and (eq_attr "memory" "load")
1044                                    (and (eq_attr "btver2_decode" "vector")
1045                                         (eq_attr "type" "sselog1"))))
1046                          "btver2-vector,btver2-valu*2")
1047
1048 (define_insn_reservation "btver2_sselog1_vector" 2
1049                          (and (eq_attr "cpu" "btver2")
1050                               (and (eq_attr "memory" "none,unknown")
1051                                    (and (eq_attr "btver2_decode" "vector")
1052                                         (eq_attr "type" "sselog1"))))
1053                          "btver2-vector,btver2-valu*2")
1054
1055 (define_insn_reservation "btver2_sseadd_load" 8
1056                          (and (eq_attr "cpu" "btver2")
1057                               (and (eq_attr "mode" "V4SF,V2DF")
1058                                    (and (eq_attr "memory" "load")
1059                                         (and (eq_attr "btver2_decode" "direct")
1060                                              (eq_attr "type" "sseadd,sseadd1")))))
1061                          "btver2-direct,btver2-load,btver2-fpa")
1062
1063 (define_insn_reservation "btver2_sseadd_reg" 3
1064                          (and (eq_attr "cpu" "btver2")
1065                               (and (eq_attr "mode" "V4SF,V2DF")
1066                                    (and (eq_attr "memory" "none,unknown")
1067                                         (and (eq_attr "btver2_decode" "direct")
1068                                              (eq_attr "type" "sseadd,sseadd1")))))
1069                          "btver2-direct,btver2-fpa")
1070
1071 ;;SSE2 SSEint SSEfp SSE
1072
1073 (define_insn_reservation "btver2_sseint_to_scalar_move_with_load" 8
1074                          (and (eq_attr "cpu" "btver2")
1075                               (and (eq_attr "mode" "SI,DI")
1076                                    (and (eq_attr "memory" "load")
1077                                         (and (eq_attr "btver2_decode" "direct")
1078                                              (eq_attr "type" "ssemov")))))
1079                          "btver2-direct,btver2-load,btver2-fpa")
1080
1081 (define_insn_reservation "btver2_sseint_to_scalar_move_with_store" 8
1082                          (and (eq_attr "cpu" "btver2")
1083                               (and (eq_attr "mode" "SI,DI")
1084                                    (and (eq_attr "memory" "store")
1085                                         (and (eq_attr "btver2_decode" "direct")
1086                                              (eq_attr "type" "ssemov")))))
1087                          "btver2-direct,btver2-fpa,btver2-store")
1088
1089
1090 (define_insn_reservation "btver2_scalar_to_sseint_move_with_load" 11
1091                          (and (eq_attr "cpu" "btver2")
1092                               (and (eq_attr "mode" "TI")
1093                                    (and (ior ( match_operand:SI 1 "memory_operand")
1094                                              ( match_operand:DI 1 "memory_operand"))
1095                                         (eq_attr "type" "ssemov"))))
1096                          "btver2-direct,btver2-load,btver2-stc,btver2-valu")
1097
1098 (define_insn_reservation "btver2_sseint_to_scalar" 3
1099                          (and (eq_attr "cpu" "btver2")
1100                               (and (eq_attr "mode" "SI,DI")
1101                                    (and (eq_attr "memory" "none,unknown")
1102                                         (and (eq_attr "btver2_decode" "direct")
1103                                              (eq_attr "type" "ssemov")))))
1104                          "btver2-direct,btver2-fpa")
1105
1106 (define_insn_reservation "btver2_scalar_to_sseint" 6
1107                          (and (eq_attr "cpu" "btver2")
1108                               (and (eq_attr "mode" "TI")
1109                                    (and (ior ( match_operand:SI 1 "register_operand")
1110                                              ( match_operand:DI 1 "register_operand"))
1111                                         (eq_attr "type" "ssemov"))))
1112                             "btver2-direct,btver2-stc,btver2-valu")
1113
1114 (define_insn_reservation "btver2_sse_int_load" 6
1115                          (and (eq_attr "cpu" "btver2")
1116                               (and (eq_attr "mode" "TI")
1117                                    (and (eq_attr "memory" "load")
1118                                         (and (eq_attr "btver2_decode" "direct")
1119                                              (eq_attr "type" "ssemov,sselog,sseishft1")))))
1120                          "btver2-direct,btver2-load,btver2-valu")
1121
1122 (define_insn_reservation "btver2_sse_int_direct" 1
1123                          (and (eq_attr "cpu" "btver2")
1124                               (and (eq_attr "mode" "TI")
1125                                    (and (eq_attr "memory" "none,unknown")
1126                                         (and (eq_attr "btver2_decode" "direct")
1127                                              (eq_attr "type" "ssemov,sselog,sseishft1")))))
1128                          "btver2-direct,btver2-valu")
1129
1130 (define_insn_reservation "btver2_sse_int_cvt_load" 6
1131                          (and (eq_attr "cpu" "btver2")
1132                               (and (eq_attr "mode" "DI")
1133                                    (and (eq_attr "memory" "load")
1134                                         (and (eq_attr "btver2_decode" "direct")
1135                                              (eq_attr "type" "sseicvt")))))
1136                          "btver2-direct,btver2-load,btver2-valu")
1137
1138 (define_insn_reservation "btver2_sse_int_cvt" 1
1139                          (and (eq_attr "cpu" "btver2")
1140                               (and (eq_attr "mode" "DI")
1141                                    (and (eq_attr "memory" "none,unknown")
1142                                         (and (eq_attr "btver2_decode" "direct")
1143                                              (eq_attr "type" "sseicvt")))))
1144                          "btver2-direct,btver2-valu")
1145
1146 (define_insn_reservation "btver2_sse_int_32_move" 3
1147                          (and (eq_attr "cpu" "btver2")
1148                               (and (eq_attr "mode" "SI,DI")
1149                                    (and (eq_attr "memory" "none,unknown")
1150                                         (and (eq_attr "btver2_decode" "direct")
1151                                              (eq_attr "type" "ssemov")))))
1152                          "btver2-direct,btver2-fpa")
1153
1154 (define_insn_reservation "btver2_int_32_sse_move" 6
1155                          (and (eq_attr "cpu" "btver2")
1156                               (and (eq_attr "mode" "TI")
1157                                    (and (ior ( match_operand:SI 1 "register_operand")
1158                                              ( match_operand:DI 1 "register_operand"))
1159                                         (eq_attr "type" "ssemov"))))
1160                          "btver2-direct,btver2-stc,btver2-valu")
1161
1162 (define_insn_reservation "btver2_sse2cvt_load_direct" 8
1163                          (and (eq_attr "cpu" "btver2")
1164                               (and (eq_attr "mode" "TI,V4SF,V2DF,DI")
1165                                    (and (eq_attr "memory" "load")
1166                                         (and (eq_attr "btver2_decode" "direct")
1167                                              (eq_attr "type" "ssecvt")))))
1168                          "btver2-direct,btver2-load,btver2-stc")
1169
1170 (define_insn_reservation "btver2_sse2cvt_reg_direct" 3
1171                          (and (eq_attr "cpu" "btver2")
1172                               (and (eq_attr "mode" "TI,V4SF,V2DF,DI")
1173                                    (and (eq_attr "btver2_decode" "direct")
1174                                         (eq_attr "type" "ssecvt"))))
1175                          "btver2-direct,btver2-stc")
1176
1177 (define_insn_reservation "btver2_sseicvt_load_si" 11
1178                          (and (eq_attr "cpu" "btver2")
1179                               (and (eq_attr "mode" "SI")
1180                                    (and (eq_attr "memory" "load")
1181                                         (and (eq_attr "btver2_decode" "double")
1182                                              (eq_attr "type" "sseicvt")))))
1183                          "btver2-double,btver2-load,btver2-stc,btver2-fpa")
1184
1185 (define_insn_reservation "btver2_sseicvt_si" 6
1186                          (and (eq_attr "cpu" "btver2")
1187                               (and (eq_attr "mode" "SI")
1188                                    (and (eq_attr "btver2_decode" "double")
1189                                         (eq_attr "type" "sseicvt"))))
1190                          "btver2-double,btver2-stc,btver2-fpa")
1191
1192 (define_insn_reservation "btver2_ssecvt_load_df" 11
1193                          (and (eq_attr "cpu" "btver2")
1194                               (and (eq_attr "mode" "DF")
1195                                    (and (eq_attr "memory" "load")
1196                                         (and (eq_attr "btver2_decode" "double")
1197                                              (eq_attr "type" "ssecvt")))))
1198                          "btver2-double,btver2-load,btver2-stc*2")
1199
1200
1201 (define_insn_reservation "btver2_ssecvt_df" 6
1202                          (and (eq_attr "cpu" "btver2")
1203                               (and (eq_attr "mode" "DF")
1204                                    (and (eq_attr "btver2_decode" "double")
1205                                         (eq_attr "type" "ssecvt"))))
1206                          "btver2-double,btver2-stc*2")
1207
1208 (define_insn_reservation "btver2_ssecvt_load_sf" 12
1209                          (and (eq_attr "cpu" "btver2")
1210                               (and (eq_attr "mode" "SF")
1211                                    (and (eq_attr "memory" "load")
1212                                         (and (eq_attr "btver2_decode" "double")
1213                                              (eq_attr "type" "ssecvt")))))
1214                          "btver2-double,btver2-load,btver2-stc*2")
1215
1216 (define_insn_reservation "btver2_ssecvt_sf" 7
1217                          (and (eq_attr "cpu" "btver2")
1218                               (and (eq_attr "mode" "SF")
1219                                    (and (eq_attr "btver2_decode" "double")
1220                                         (eq_attr "type" "ssecvt"))))
1221                          "btver2-double,btver2-stc*2")
1222
1223 (define_insn_reservation "btver2_sseicvt_load_df" 14
1224                          (and (eq_attr "cpu" "btver2")
1225                               (and (eq_attr "mode" "DF,SF")
1226                                    (and (eq_attr "memory" "load")
1227                                         (and (eq_attr "btver2_decode" "double")
1228                                              (eq_attr "type" "sseicvt")))))
1229                          "btver2-double,btver2-load,btver2-stc")
1230 ;;st,ld-stc
1231 (define_insn_reservation "btver2_sseicvt_df" 9
1232                          (and (eq_attr "cpu" "btver2")
1233                               (and (eq_attr "mode" "DF,SF")
1234                                    (and (eq_attr "btver2_decode" "double")
1235                                         (eq_attr "type" "sseicvt"))))
1236                          "btver2-double,btver2-stc")
1237
1238
1239 (define_insn_reservation "btver2_scalar_sse_load_add" 8
1240                          (and (eq_attr "cpu" "btver2")
1241                               (and (eq_attr "mode" "DF,SF")
1242                                    (and (eq_attr "memory" "load")
1243                                         (and (eq_attr "btver2_decode" "direct")
1244                                              (eq_attr "type" "sseadd")))))
1245                          "btver2-direct,btver2-load,btver2-fpa")
1246
1247 (define_insn_reservation "btver2_scalar_sse_add" 3
1248                          (and (eq_attr "cpu" "btver2")
1249                               (and (eq_attr "mode" "DF,SF")
1250                                    (and (eq_attr "memory" "none,unknown")
1251                                         (and (eq_attr "btver2_decode" "direct")
1252                                              (eq_attr "type" "sseadd")))))
1253                          "btver2-direct,btver2-fpa")
1254
1255 (define_insn_reservation "btver2_int_sse_cmp_load" 7
1256                          (and (eq_attr "cpu" "btver2")
1257                               (and (eq_attr "mode" "V2DF,V4SF,DF,SF")
1258                                    (and (eq_attr "memory" "load")
1259                                         (and (eq_attr "btver2_decode" "direct")
1260                                              (eq_attr "type" "ssecmp")))))
1261                          "btver2-direct,btver2-load,btver2-fpa")
1262
1263 (define_insn_reservation "btver2_int_sse_cmp" 2
1264                          (and (eq_attr "cpu" "btver2")
1265                               (and (eq_attr "mode" "V2DF,V4SF,DF,SF")
1266                                    (and (eq_attr "memory" "none,unknown")
1267                                         (and (eq_attr "btver2_decode" "direct")
1268                                              (eq_attr "type" "ssecmp")))))
1269                          "btver2-direct,btver2-fpa")
1270
1271 (define_insn_reservation "btver2_int_sse_comsi_load" 7
1272                          (and (eq_attr "cpu" "btver2")
1273                               (and (eq_attr "mode" "DF,SF")
1274                                    (and (eq_attr "memory" "load")
1275                                         (and (eq_attr "btver2_decode" "direct")
1276                                              (eq_attr "type" "ssecomi")))))
1277                          "btver2-direct,btver2-fpa")
1278
1279 (define_insn_reservation "btver2_int_sse_comsi" 2
1280                          (and (eq_attr "cpu" "btver2")
1281                              (and (eq_attr "mode" "DF,SF")
1282                                    (and (eq_attr "memory" "none,unknown")
1283                                         (and (eq_attr "btver2_decode" "direct")
1284                                              (eq_attr "type" "ssecomi")))))
1285                          "btver2-direct,btver2-fpa")
1286
1287 (define_insn_reservation "btver2_ssemmx_mov_load_default" 6
1288                          (and (eq_attr "cpu" "btver2")
1289                               (and (eq_attr "memory" "load")
1290                                    (and (eq_attr "btver2_decode" "direct")
1291                                         (eq_attr "type" "ssemov,mmxmov"))))
1292                          "btver2-direct,btver2-load,(btver2-fpa|btver2-fpm)")
1293
1294 (define_insn_reservation "btver2_ssemmx_mov_store_default" 6
1295                          (and (eq_attr "cpu" "btver2")
1296                               (and (eq_attr "memory" "store,both")
1297                                    (and (eq_attr "btver2_decode" "direct")
1298                                         (eq_attr "type" "ssemov,mmxmov"))))
1299                          "btver2-direct,(btver2-fpa|btver2-fpm),btver2-store")
1300
1301 (define_insn_reservation "btver2_sse_mov_default" 1
1302                          (and (eq_attr "cpu" "btver2")
1303                               (and (eq_attr "memory" "none,unknown")
1304                                    (and (eq_attr "btver2_decode" "direct")
1305                                         (eq_attr "type" "ssemov,mmxmov"))))
1306                          "btver2-direct,(btver2-fpa|btver2-fpm)")
1307
1308 (define_insn_reservation "btver2_sse_shuf_double" 2
1309                          (and (eq_attr "cpu" "btver2")
1310                               (and (eq_attr "memory" "none,unknown")
1311                                    (and (eq_attr "mode" "V4DF,V8SF")
1312                                         (eq_attr "type" "sseshuf"))))
1313                          "btver2-double,(btver2-fpa|btver2-fpm)")
1314
1315 (define_insn_reservation "btver2_sse_shuf_direct" 1
1316                          (and (eq_attr "cpu" "btver2")
1317                               (and (eq_attr "memory" "none,unknown")
1318                                    (and (eq_attr "mode" "V2DF,V4SF")
1319                                         (eq_attr "type" "sseshuf,sseshuf1"))))
1320                          "btver2-direct,(btver2-fpa|btver2-fpm)")
1321
1322 (define_insn_reservation "btver2_sse_shuf_double_load" 7
1323                          (and (eq_attr "cpu" "btver2")
1324                               (and (eq_attr "memory" "load")
1325                                    (and (eq_attr "mode" "V4DF,V8SF")
1326                                         (eq_attr "type" "sseshuf"))))
1327                          "btver2-double,btver2-load,(btver2-fpa|btver2-fpm)")
1328
1329 (define_insn_reservation "btver2_sse_shuf_direct_load" 6
1330                          (and (eq_attr "cpu" "btver2")
1331                               (and (eq_attr "memory" "load")
1332                                    (and (eq_attr "mode" "V2DF,V4SF")
1333                                         (eq_attr "type" "sseshuf,sseshuf1"))))
1334                          "btver2-direct,btver2-load,(btver2-fpa|btver2-fpm)")
1335
1336 (define_insn_reservation "btver2_sse_div" 19
1337                          (and (eq_attr "cpu" "btver2")
1338                               (and (eq_attr "mode" "V2DF,DF,V4SF")
1339                                    (and (eq_attr "memory" "none,unknown")
1340                                         (eq_attr "type" "ssediv"))))
1341                          "btver2-direct,btver2-fpm*19")
1342
1343 (define_insn_reservation "btver2_sse_div_sf" 14
1344                          (and (eq_attr "cpu" "btver2")
1345                              (and (eq_attr "mode" "SF")
1346                                    (and (eq_attr "memory" "none,unknown")
1347                                         (eq_attr "type" "ssediv"))))
1348                          "btver2-direct,btver2-fpm*14")
1349
1350 (define_insn_reservation "btver2_sse_mul" 4
1351                          (and (eq_attr "cpu" "btver2")
1352                               (and (eq_attr "mode" "V2DF,DF,V4SF,SF")
1353                                    (and (eq_attr "memory" "none,unknown")
1354                                         (eq_attr "type" "ssemul"))))
1355                          "btver2-direct,btver2-fpm*2")
1356
1357 (define_insn_reservation "btver2_sse_mul_sf" 2
1358                          (and (eq_attr "cpu" "btver2")
1359                               (and (eq_attr "mode" "V2DF,DF,V4SF,SF")
1360                                    (and (eq_attr "memory" "none,unknown")
1361                                         (eq_attr "type" "ssemul"))))
1362                          "btver2-direct,btver2-fpm")
1363
1364 (define_insn_reservation "btver2_sse_div_load" 24
1365                          (and (eq_attr "cpu" "btver2")
1366                               (and (eq_attr "mode" "V2DF,DF,V4SF")
1367                                    (and (eq_attr "memory" "load")
1368                                         (eq_attr "type" "ssediv"))))
1369                          "btver2-direct,btver2-load,btver2-fpm*19")
1370
1371 (define_insn_reservation "btver2_sse_div_sf_load" 19
1372                          (and (eq_attr "cpu" "btver2")
1373                               (and (eq_attr "mode" "SF")
1374                                    (and (eq_attr "memory" "load")
1375                                         (eq_attr "type" "ssediv"))))
1376                          "btver2-direct,btver2-load,btver2-fpm*14")
1377
1378 (define_insn_reservation "btver2_sse_mul_load" 9
1379                          (and (eq_attr "cpu" "btver2")
1380                               (and (eq_attr "mode" "V2DF,DF,V4SF,SF")
1381                                    (and (eq_attr "memory" "load")
1382                                         (eq_attr "type" "ssemul"))))
1383                          "btver2-direct,btver2-load,btver2-fpm*2")
1384
1385 (define_insn_reservation "btver2_sse_mul_sf_load" 7
1386                          (and (eq_attr "cpu" "btver2")
1387                               (and (eq_attr "mode" "V2DF,DF,V4SF,SF")
1388                                    (and (eq_attr "memory" "load")
1389                                         (eq_attr "type" "ssemul"))))
1390                          "btver2-direct,btver2-load,btver2-fpm")
1391