2 * Copyright (c) 1997 Semen Ustimenko (semenu@FreeBSD.org)
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * $FreeBSD: src/sys/dev/tx/if_tx.c,v 1.61.2.1 2002/10/29 01:43:49 semenu Exp $
30 * EtherPower II 10/100 Fast Ethernet (SMC 9432 serie)
32 * These cards are based on SMC83c17x (EPIC) chip and one of the various
33 * PHYs (QS6612, AC101 and LXT970 were seen). The media support depends on
34 * card model. All cards support 10baseT/UTP and 100baseTX half- and full-
35 * duplex (SMB9432TX). SMC9432BTX also supports 10baseT/BNC. SMC9432FTX also
36 * supports fibre optics.
38 * Thanks are going to Steve Bauer and Jason Wright.
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/sockio.h>
45 #include <sys/malloc.h>
46 #include <sys/kernel.h>
47 #include <sys/socket.h>
48 #include <sys/queue.h>
49 #include <sys/serialize.h>
52 #include <sys/thread2.h>
53 #include <sys/interrupt.h>
56 #include <net/ifq_var.h>
57 #include <net/if_arp.h>
58 #include <net/ethernet.h>
59 #include <net/if_dl.h>
60 #include <net/if_media.h>
64 #include <net/vlan/if_vlan_var.h>
66 #include <vm/vm.h> /* for vtophys */
67 #include <vm/pmap.h> /* for vtophys */
69 #include <bus/pci/pcireg.h>
70 #include <bus/pci/pcivar.h>
71 #include <bus/pci/pcidevs.h>
73 #include <dev/netif/mii_layer/mii.h>
74 #include <dev/netif/mii_layer/miivar.h>
75 #include <dev/netif/mii_layer/miidevs.h>
76 #include <dev/netif/mii_layer/lxtphyreg.h>
78 #include "miibus_if.h"
80 #include <dev/netif/tx/if_txreg.h>
81 #include <dev/netif/tx/if_txvar.h>
83 static int epic_ifioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
84 static void epic_intr(void *);
85 static void epic_tx_underrun(epic_softc_t *);
86 static int epic_common_attach(epic_softc_t *);
87 static void epic_ifstart(struct ifnet *);
88 static void epic_ifwatchdog(struct ifnet *);
89 static void epic_stats_update(void *);
90 static int epic_init(epic_softc_t *);
91 static void epic_stop(epic_softc_t *);
92 static void epic_rx_done(epic_softc_t *);
93 static void epic_tx_done(epic_softc_t *);
94 static int epic_init_rings(epic_softc_t *);
95 static void epic_free_rings(epic_softc_t *);
96 static void epic_stop_activity(epic_softc_t *);
97 static int epic_queue_last_packet(epic_softc_t *);
98 static void epic_start_activity(epic_softc_t *);
99 static void epic_set_rx_mode(epic_softc_t *);
100 static void epic_set_tx_mode(epic_softc_t *);
101 static void epic_set_mc_table(epic_softc_t *);
102 static int epic_read_eeprom(epic_softc_t *,u_int16_t);
103 static void epic_output_eepromw(epic_softc_t *, u_int16_t);
104 static u_int16_t epic_input_eepromw(epic_softc_t *);
105 static u_int8_t epic_eeprom_clock(epic_softc_t *,u_int8_t);
106 static void epic_write_eepromreg(epic_softc_t *,u_int8_t);
107 static u_int8_t epic_read_eepromreg(epic_softc_t *);
109 static int epic_read_phy_reg(epic_softc_t *, int, int);
110 static void epic_write_phy_reg(epic_softc_t *, int, int, int);
112 static int epic_miibus_readreg(device_t, int, int);
113 static int epic_miibus_writereg(device_t, int, int, int);
114 static void epic_miibus_statchg(device_t);
115 static void epic_miibus_mediainit(device_t);
117 static int epic_ifmedia_upd(struct ifnet *);
118 static void epic_ifmedia_sts(struct ifnet *, struct ifmediareq *);
120 static int epic_probe(device_t);
121 static int epic_attach(device_t);
122 static void epic_shutdown(device_t);
123 static int epic_detach(device_t);
125 static device_method_t epic_methods[] = {
126 /* Device interface */
127 DEVMETHOD(device_probe, epic_probe),
128 DEVMETHOD(device_attach, epic_attach),
129 DEVMETHOD(device_detach, epic_detach),
130 DEVMETHOD(device_shutdown, epic_shutdown),
133 DEVMETHOD(miibus_readreg, epic_miibus_readreg),
134 DEVMETHOD(miibus_writereg, epic_miibus_writereg),
135 DEVMETHOD(miibus_statchg, epic_miibus_statchg),
136 DEVMETHOD(miibus_mediainit, epic_miibus_mediainit),
141 static driver_t epic_driver = {
147 static devclass_t epic_devclass;
149 DECLARE_DUMMY_MODULE(if_tx);
150 MODULE_DEPEND(if_tx, miibus, 1, 1, 1);
151 DRIVER_MODULE(if_tx, pci, epic_driver, epic_devclass, NULL, NULL);
152 DRIVER_MODULE(miibus, tx, miibus_driver, miibus_devclass, NULL, NULL);
154 static struct epic_type epic_devs[] = {
155 { PCI_VENDOR_SMC, PCI_PRODUCT_SMC_83C170,
156 "SMC EtherPower II 10/100" },
161 epic_probe(device_t dev)
166 vid = pci_get_vendor(dev);
167 did = pci_get_device(dev);
168 for (t = epic_devs; t->name != NULL; ++t) {
169 if (vid == t->ven_id && did == t->dev_id) {
170 device_set_desc(dev, t->name);
177 #if defined(EPIC_USEIOSPACE)
178 #define EPIC_RES SYS_RES_IOPORT
179 #define EPIC_RID PCIR_BAR(0)
181 #define EPIC_RES SYS_RES_MEMORY
182 #define EPIC_RID PCIR_BAR(1)
186 * Attach routine: map registers, allocate softc, rings and descriptors.
187 * Reset to known state.
190 epic_attach(device_t dev)
197 sc = device_get_softc(dev);
199 /* Preinitialize softc structure */
201 callout_init(&sc->tx_stat_timer);
203 /* Fill ifnet structure */
205 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
207 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_MULTICAST;
208 ifp->if_ioctl = epic_ifioctl;
209 ifp->if_start = epic_ifstart;
210 ifp->if_watchdog = epic_ifwatchdog;
211 ifp->if_init = (if_init_f_t*)epic_init;
213 ifp->if_baudrate = 10000000;
214 ifq_set_maxlen(&ifp->if_snd, TX_RING_SIZE - 1);
215 ifq_set_ready(&ifp->if_snd);
217 pci_enable_busmaster(dev);
220 sc->res = bus_alloc_resource_any(dev, EPIC_RES, &rid, RF_ACTIVE);
222 if (sc->res == NULL) {
223 device_printf(dev, "couldn't map ports/memory\n");
228 sc->sc_st = rman_get_bustag(sc->res);
229 sc->sc_sh = rman_get_bushandle(sc->res);
231 /* Allocate interrupt */
233 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
234 RF_SHAREABLE | RF_ACTIVE);
236 if (sc->irq == NULL) {
237 device_printf(dev, "couldn't map interrupt\n");
242 /* Do OS independent part, including chip wakeup and reset */
243 error = epic_common_attach(sc);
249 /* Do ifmedia setup */
250 if (mii_phy_probe(dev, &sc->miibus,
251 epic_ifmedia_upd, epic_ifmedia_sts)) {
252 device_printf(dev, "ERROR! MII without any PHY!?\n");
257 /* board type and ... */
259 for(i=0x2c;i<0x32;i++) {
260 tmp = epic_read_eeprom(sc, i);
261 if (' ' == (u_int8_t)tmp) break;
262 kprintf("%c", (u_int8_t)tmp);
264 if (' ' == (u_int8_t)tmp) break;
265 kprintf("%c", (u_int8_t)tmp);
269 /* Attach to OS's managers */
270 ether_ifattach(ifp, sc->sc_macaddr, NULL);
271 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
273 error = bus_setup_intr(dev, sc->irq, INTR_MPSAFE,
274 epic_intr, sc, &sc->sc_ih,
278 device_printf(dev, "couldn't set up irq\n");
283 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->irq));
293 * Detach driver and free resources
296 epic_detach(device_t dev)
298 epic_softc_t *sc = device_get_softc(dev);
299 struct ifnet *ifp = &sc->arpcom.ac_if;
301 if (device_is_attached(dev)) {
302 lwkt_serialize_enter(ifp->if_serializer);
304 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
305 lwkt_serialize_exit(ifp->if_serializer);
311 device_delete_child(dev, sc->miibus);
312 bus_generic_detach(dev);
315 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
317 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
320 kfree(sc->tx_flist, M_DEVBUF);
322 kfree(sc->tx_desc, M_DEVBUF);
324 kfree(sc->rx_desc, M_DEVBUF);
333 * Stop all chip I/O so that the kernel's probe routines don't
334 * get confused by errant DMAs when rebooting.
337 epic_shutdown(device_t dev)
342 sc = device_get_softc(dev);
343 ifp = &sc->arpcom.ac_if;
344 lwkt_serialize_enter(ifp->if_serializer);
346 lwkt_serialize_exit(ifp->if_serializer);
350 * This is if_ioctl handler.
353 epic_ifioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
355 epic_softc_t *sc = ifp->if_softc;
356 struct mii_data *mii;
357 struct ifreq *ifr = (struct ifreq *) data;
362 if (ifp->if_mtu == ifr->ifr_mtu)
365 /* XXX Though the datasheet doesn't imply any
366 * limitations on RX and TX sizes beside max 64Kb
367 * DMA transfer, seems we can't send more then 1600
368 * data bytes per ethernet packet. (Transmitter hangs
369 * up if more data is sent)
371 if (ifr->ifr_mtu + ifp->if_hdrlen <= EPIC_MAX_MTU) {
372 ifp->if_mtu = ifr->ifr_mtu;
381 * If the interface is marked up and stopped, then start it.
382 * If it is marked down and running, then stop it.
384 if (ifp->if_flags & IFF_UP) {
385 if ((ifp->if_flags & IFF_RUNNING) == 0) {
390 if (ifp->if_flags & IFF_RUNNING) {
396 /* Handle IFF_PROMISC and IFF_ALLMULTI flags */
397 epic_stop_activity(sc);
398 epic_set_mc_table(sc);
399 epic_set_rx_mode(sc);
400 epic_start_activity(sc);
405 epic_set_mc_table(sc);
411 mii = device_get_softc(sc->miibus);
412 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
416 error = ether_ioctl(ifp, command, data);
423 * OS-independed part of attach process. allocate memory for descriptors
424 * and frag lists, wake up chip, read MAC address and PHY identyfier.
425 * Return -1 on failure.
428 epic_common_attach(epic_softc_t *sc)
433 sc->tx_flist = kmalloc(sizeof(struct epic_frag_list)*TX_RING_SIZE,
434 M_DEVBUF, M_WAITOK | M_ZERO);
435 sc->tx_desc = kmalloc(sizeof(struct epic_tx_desc)*TX_RING_SIZE,
436 M_DEVBUF, M_WAITOK | M_ZERO);
437 sc->rx_desc = kmalloc(sizeof(struct epic_rx_desc)*RX_RING_SIZE,
438 M_DEVBUF, M_WAITOK | M_ZERO);
440 /* Bring the chip out of low-power mode. */
441 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
444 /* Workaround for Application Note 7-15 */
445 for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
447 /* Read mac address from EEPROM */
448 for (i = 0; i < ETHER_ADDR_LEN / sizeof(u_int16_t); i++)
449 ((u_int16_t *)sc->sc_macaddr)[i] = epic_read_eeprom(sc,i);
451 /* Set Non-Volatile Control Register from EEPROM */
452 CSR_WRITE_4(sc, NVCTL, epic_read_eeprom(sc, EEPROM_NVCTL) & 0x1F);
455 sc->tx_threshold = TRANSMIT_THRESHOLD;
456 sc->txcon = TXCON_DEFAULT;
457 sc->miicfg = MIICFG_SMI_ENABLE;
458 sc->phyid = EPIC_UNKN_PHY;
462 sub_vid = pci_get_subvendor(sc->dev);
463 sc->cardid = pci_get_subdevice(sc->dev);
465 if (sub_vid != PCI_VENDOR_SMC)
466 device_printf(sc->dev, "unknown card vendor %04xh\n", sub_vid);
472 * This is if_start handler. It takes mbufs from if_snd queue
473 * and queue them for transmit, one by one, until TX ring become full
474 * or queue become empty.
477 epic_ifstart(struct ifnet *ifp)
479 epic_softc_t *sc = ifp->if_softc;
480 struct epic_tx_buffer *buf;
481 struct epic_tx_desc *desc;
482 struct epic_frag_list *flist;
487 while (sc->pending_txs < TX_RING_SIZE) {
488 buf = sc->tx_buffer + sc->cur_tx;
489 desc = sc->tx_desc + sc->cur_tx;
490 flist = sc->tx_flist + sc->cur_tx;
492 /* Get next packet to send */
493 m0 = ifq_dequeue(&ifp->if_snd, NULL);
495 /* If nothing to send, return */
499 /* Fill fragments list */
501 (NULL != m) && (i < EPIC_MAX_FRAGS);
502 m = m->m_next, i++) {
503 flist->frag[i].fraglen = m->m_len;
504 flist->frag[i].fragaddr = vtophys(mtod(m, caddr_t));
508 /* If packet was more than EPIC_MAX_FRAGS parts, */
509 /* recopy packet to new allocated mbuf cluster */
511 m = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
518 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t));
519 flist->frag[0].fraglen =
520 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
521 m->m_pkthdr.rcvif = ifp;
524 flist->frag[0].fragaddr = vtophys(mtod(m, caddr_t));
531 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
532 desc->control = 0x01;
534 max(m0->m_pkthdr.len,ETHER_MIN_LEN-ETHER_CRC_LEN);
535 desc->status = 0x8000;
536 CSR_WRITE_4(sc, COMMAND, COMMAND_TXQUEUED);
538 /* Set watchdog timer */
544 ifq_set_oactive(&ifp->if_snd);
551 * Synopsis: Finish all received frames.
554 epic_rx_done(epic_softc_t *sc)
557 struct ifnet *ifp = &sc->sc_if;
558 struct epic_rx_buffer *buf;
559 struct epic_rx_desc *desc;
562 while ((sc->rx_desc[sc->cur_rx].status & 0x8000) == 0) {
563 buf = sc->rx_buffer + sc->cur_rx;
564 desc = sc->rx_desc + sc->cur_rx;
566 /* Switch to next descriptor */
567 sc->cur_rx = (sc->cur_rx+1) & RX_RING_MASK;
570 * Check for RX errors. This should only happen if
571 * SAVE_ERRORED_PACKETS is set. RX errors generate
572 * RXE interrupt usually.
574 if ((desc->status & 1) == 0) {
575 sc->sc_if.if_ierrors++;
576 desc->status = 0x8000;
580 /* Save packet length and mbuf contained packet */
581 len = desc->rxlength - ETHER_CRC_LEN;
584 /* Try to get mbuf cluster */
585 buf->mbuf = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
586 if (NULL == buf->mbuf) {
588 desc->status = 0x8000;
593 /* Point to new mbuf, and give descriptor to chip */
594 desc->bufaddr = vtophys(mtod(buf->mbuf, caddr_t));
595 desc->status = 0x8000;
597 /* First mbuf in packet holds the ethernet and packet headers */
598 m->m_pkthdr.rcvif = ifp;
599 m->m_pkthdr.len = m->m_len = len;
601 /* Give mbuf to OS */
602 ifp->if_input(ifp, m);
604 /* Successfuly received frame */
612 * Synopsis: Do last phase of transmission. I.e. if desc is
613 * transmitted, decrease pending_txs counter, free mbuf contained
614 * packet, switch to next descriptor and repeat until no packets
615 * are pending or descriptor is not transmitted yet.
618 epic_tx_done(epic_softc_t *sc)
620 struct epic_tx_buffer *buf;
621 struct epic_tx_desc *desc;
624 while (sc->pending_txs > 0) {
625 buf = sc->tx_buffer + sc->dirty_tx;
626 desc = sc->tx_desc + sc->dirty_tx;
627 status = desc->status;
629 /* If packet is not transmitted, thou followed */
630 /* packets are not transmitted too */
631 if (status & 0x8000) break;
633 /* Packet is transmitted. Switch to next and */
636 sc->dirty_tx = (sc->dirty_tx + 1) & TX_RING_MASK;
640 /* Check for errors and collisions */
641 if (status & 0x0001) sc->sc_if.if_opackets++;
642 else sc->sc_if.if_oerrors++;
643 sc->sc_if.if_collisions += (status >> 8) & 0x1F;
644 #if defined(EPIC_DIAG)
645 if ((status & 0x1001) == 0x1001) {
646 if_printf(&sc->sc_if,
647 "Tx ERROR: excessive coll. number\n");
652 if (sc->pending_txs < TX_RING_SIZE)
653 ifq_clr_oactive(&sc->sc_if.if_snd);
662 epic_softc_t * sc = (epic_softc_t *) arg;
665 while (i-- && ((status = CSR_READ_4(sc, INTSTAT)) & INTSTAT_INT_ACTV)) {
666 CSR_WRITE_4(sc, INTSTAT, status);
668 if (status & (INTSTAT_RQE|INTSTAT_RCC|INTSTAT_OVW)) {
670 if (status & (INTSTAT_RQE|INTSTAT_OVW)) {
671 #if defined(EPIC_DIAG)
672 if (status & INTSTAT_OVW)
673 if_printf(&sc->sc_if, "RX buffer overflow\n");
674 if (status & INTSTAT_RQE)
675 if_printf(&sc->sc_if, "RX FIFO overflow\n");
677 if ((CSR_READ_4(sc, COMMAND) & COMMAND_RXQUEUED) == 0)
678 CSR_WRITE_4(sc, COMMAND, COMMAND_RXQUEUED);
679 sc->sc_if.if_ierrors++;
683 if (status & (INTSTAT_TXC|INTSTAT_TCC|INTSTAT_TQE)) {
685 if (!ifq_is_empty(&sc->sc_if.if_snd))
686 if_devstart(&sc->sc_if);
689 /* Check for rare errors */
690 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
691 INTSTAT_APE|INTSTAT_DPE|INTSTAT_TXU|INTSTAT_RXE)) {
692 if (status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
693 INTSTAT_APE|INTSTAT_DPE)) {
694 if_printf(&sc->sc_if, "PCI fatal errors occurred: %s%s%s%s\n",
695 (status&INTSTAT_PMA)?"PMA ":"",
696 (status&INTSTAT_PTA)?"PTA ":"",
697 (status&INTSTAT_APE)?"APE ":"",
698 (status&INTSTAT_DPE)?"DPE":""
707 if (status & INTSTAT_RXE) {
708 #if defined(EPIC_DIAG)
709 if_printf(sc->sc_if, "CRC/Alignment error\n");
711 sc->sc_if.if_ierrors++;
714 if (status & INTSTAT_TXU) {
715 epic_tx_underrun(sc);
716 sc->sc_if.if_oerrors++;
721 /* If no packets are pending, then no timeouts */
722 if (sc->pending_txs == 0) sc->sc_if.if_timer = 0;
728 * Handle the TX underrun error: increase the TX threshold
729 * and restart the transmitter.
732 epic_tx_underrun(epic_softc_t *sc)
734 if (sc->tx_threshold > TRANSMIT_THRESHOLD_MAX) {
735 sc->txcon &= ~TXCON_EARLY_TRANSMIT_ENABLE;
736 #if defined(EPIC_DIAG)
737 if_printf(&sc->sc_if, "Tx UNDERRUN: early TX disabled\n");
740 sc->tx_threshold += 0x40;
741 #if defined(EPIC_DIAG)
742 if_printf(&sc->sc_if, "Tx UNDERRUN: "
743 "TX threshold increased to %d\n", sc->tx_threshold);
747 /* We must set TXUGO to reset the stuck transmitter */
748 CSR_WRITE_4(sc, COMMAND, COMMAND_TXUGO);
750 /* Update the TX threshold */
751 epic_stop_activity(sc);
752 epic_set_tx_mode(sc);
753 epic_start_activity(sc);
759 * Synopsis: This one is called if packets wasn't transmitted
760 * during timeout. Try to deallocate transmitted packets, and
761 * if success continue to work.
764 epic_ifwatchdog(struct ifnet *ifp)
766 epic_softc_t *sc = ifp->if_softc;
768 if_printf(ifp, "device timeout %d packets\n", sc->pending_txs);
770 /* Try to finish queued packets */
773 /* If not successful */
774 if (sc->pending_txs > 0) {
776 ifp->if_oerrors+=sc->pending_txs;
778 /* Reinitialize board */
779 if_printf(ifp, "reinitialization\n");
784 if_printf(ifp, "seems we can continue normally\n");
787 if (!ifq_is_empty(&ifp->if_snd))
792 * Despite the name of this function, it doesn't update statistics, it only
793 * helps in autonegotiation process.
796 epic_stats_update(void *xsc)
798 epic_softc_t *sc = xsc;
799 struct ifnet *ifp = &sc->sc_if;
800 struct mii_data * mii;
802 lwkt_serialize_enter(ifp->if_serializer);
804 mii = device_get_softc(sc->miibus);
807 callout_reset(&sc->tx_stat_timer, hz, epic_stats_update, sc);
809 lwkt_serialize_exit(ifp->if_serializer);
816 epic_ifmedia_upd(struct ifnet *ifp)
819 struct mii_data *mii;
821 struct mii_softc *miisc;
825 mii = device_get_softc(sc->miibus);
826 ifm = &mii->mii_media;
827 media = ifm->ifm_cur->ifm_media;
829 /* Do not do anything if interface is not up */
830 if ((ifp->if_flags & IFF_UP) == 0)
834 * Lookup current selected PHY
836 if (IFM_INST(media) == sc->serinst) {
837 sc->phyid = EPIC_SERIAL;
840 /* If we're not selecting serial interface, select MII mode */
841 sc->miicfg &= ~MIICFG_SERIAL_ENABLE;
842 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
844 /* Default to unknown PHY */
845 sc->phyid = EPIC_UNKN_PHY;
847 /* Lookup selected PHY */
848 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
849 miisc = LIST_NEXT(miisc, mii_list)) {
850 if (IFM_INST(media) == miisc->mii_inst) {
856 /* Identify selected PHY */
858 int id1, id2, model, oui;
860 id1 = PHY_READ(sc->physc, MII_PHYIDR1);
861 id2 = PHY_READ(sc->physc, MII_PHYIDR2);
863 oui = MII_OUI(id1, id2);
864 model = MII_MODEL(id2);
866 case MII_OUI_QUALSEMI:
867 if (model == MII_MODEL_QUALSEMI_QS6612)
868 sc->phyid = EPIC_QS6612_PHY;
870 case MII_OUI_xxALTIMA:
871 if (model == MII_MODEL_xxALTIMA_AC101)
872 sc->phyid = EPIC_AC101_PHY;
874 case MII_OUI_xxLEVEL1:
875 if (model == MII_MODEL_xxLEVEL1_LXT970)
876 sc->phyid = EPIC_LXT970_PHY;
883 * Do PHY specific card setup
886 /* Call this, to isolate all not selected PHYs and
891 /* Do our own setup */
893 case EPIC_QS6612_PHY:
896 /* We have to powerup fiber tranceivers */
897 if (IFM_SUBTYPE(media) == IFM_100_FX)
898 sc->miicfg |= MIICFG_694_ENABLE;
900 sc->miicfg &= ~MIICFG_694_ENABLE;
901 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
904 case EPIC_LXT970_PHY:
905 /* We have to powerup fiber tranceivers */
906 cfg = PHY_READ(sc->physc, MII_LXTPHY_CONFIG);
907 if (IFM_SUBTYPE(media) == IFM_100_FX)
908 cfg |= CONFIG_LEDC1 | CONFIG_LEDC0;
910 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0);
911 PHY_WRITE(sc->physc, MII_LXTPHY_CONFIG, cfg);
915 /* Select serial PHY, (10base2/BNC usually) */
916 sc->miicfg |= MIICFG_694_ENABLE | MIICFG_SERIAL_ENABLE;
917 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
919 /* There is no driver to fill this */
920 mii->mii_media_active = media;
921 mii->mii_media_status = 0;
923 /* We need to call this manualy as i wasn't called
926 epic_miibus_statchg(sc->dev);
930 if_printf(ifp, "ERROR! Unknown PHY selected\n");
938 * Report current media status.
941 epic_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
944 struct mii_data *mii;
947 mii = device_get_softc(sc->miibus);
949 /* Nothing should be selected if interface is down */
950 if ((ifp->if_flags & IFF_UP) == 0) {
951 ifmr->ifm_active = IFM_NONE;
952 ifmr->ifm_status = 0;
957 /* Call underlying pollstat, if not serial PHY */
958 if (sc->phyid != EPIC_SERIAL)
961 /* Simply copy media info */
962 ifmr->ifm_active = mii->mii_media_active;
963 ifmr->ifm_status = mii->mii_media_status;
969 * Callback routine, called on media change.
972 epic_miibus_statchg(device_t dev)
975 struct mii_data *mii;
978 sc = device_get_softc(dev);
979 mii = device_get_softc(sc->miibus);
980 media = mii->mii_media_active;
982 sc->txcon &= ~(TXCON_LOOPBACK_MODE | TXCON_FULL_DUPLEX);
984 /* If we are in full-duplex mode or loopback operation,
985 * we need to decouple receiver and transmitter.
987 if (IFM_OPTIONS(media) & (IFM_FDX | IFM_LOOP))
988 sc->txcon |= TXCON_FULL_DUPLEX;
990 /* On some cards we need manualy set fullduplex led */
991 if (sc->cardid == SMC9432FTX ||
992 sc->cardid == SMC9432FTX_SC) {
993 if (IFM_OPTIONS(media) & IFM_FDX)
994 sc->miicfg |= MIICFG_694_ENABLE;
996 sc->miicfg &= ~MIICFG_694_ENABLE;
998 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1001 /* Update baudrate */
1002 if (IFM_SUBTYPE(media) == IFM_100_TX ||
1003 IFM_SUBTYPE(media) == IFM_100_FX)
1004 sc->sc_if.if_baudrate = 100000000;
1006 sc->sc_if.if_baudrate = 10000000;
1008 epic_stop_activity(sc);
1009 epic_set_tx_mode(sc);
1010 epic_start_activity(sc);
1016 epic_miibus_mediainit(device_t dev)
1019 struct mii_data *mii;
1020 struct ifmedia *ifm;
1023 sc = device_get_softc(dev);
1024 mii = device_get_softc(sc->miibus);
1025 ifm = &mii->mii_media;
1027 /* Add Serial Media Interface if present, this applies to
1030 if (CSR_READ_4(sc, MIICFG) & MIICFG_PHY_PRESENT) {
1031 /* Store its instance */
1032 sc->serinst = mii->mii_instance++;
1034 /* Add as 10base2/BNC media */
1035 media = IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, sc->serinst);
1036 ifmedia_add(ifm, media, 0, NULL);
1038 /* Report to user */
1039 if_printf(&sc->sc_if, "serial PHY detected (10Base2/BNC)\n");
1046 * Reset chip, allocate rings, and update media.
1049 epic_init(epic_softc_t *sc)
1051 struct ifnet *ifp = &sc->sc_if;
1054 /* If interface is already running, then we need not do anything */
1055 if (ifp->if_flags & IFF_RUNNING) {
1059 /* Soft reset the chip (we have to power up card before) */
1060 CSR_WRITE_4(sc, GENCTL, 0);
1061 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1064 * Reset takes 15 pci ticks which depends on PCI bus speed.
1065 * Assuming it >= 33000000 hz, we have wait at least 495e-6 sec.
1070 CSR_WRITE_4(sc, GENCTL, 0);
1072 /* Workaround for Application Note 7-15 */
1073 for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
1075 /* Initialize rings */
1076 if (epic_init_rings(sc)) {
1077 if_printf(ifp, "failed to init rings\n");
1081 /* Give rings to EPIC */
1082 CSR_WRITE_4(sc, PRCDAR, vtophys(sc->rx_desc));
1083 CSR_WRITE_4(sc, PTCDAR, vtophys(sc->tx_desc));
1085 /* Put node address to EPIC */
1086 CSR_WRITE_4(sc, LAN0, ((u_int16_t *)sc->sc_macaddr)[0]);
1087 CSR_WRITE_4(sc, LAN1, ((u_int16_t *)sc->sc_macaddr)[1]);
1088 CSR_WRITE_4(sc, LAN2, ((u_int16_t *)sc->sc_macaddr)[2]);
1090 /* Set tx mode, includeing transmit threshold */
1091 epic_set_tx_mode(sc);
1093 /* Compute and set RXCON. */
1094 epic_set_rx_mode(sc);
1096 /* Set multicast table */
1097 epic_set_mc_table(sc);
1099 /* Enable interrupts by setting the interrupt mask. */
1100 CSR_WRITE_4(sc, INTMASK,
1101 INTSTAT_RCC | /* INTSTAT_RQE | INTSTAT_OVW | INTSTAT_RXE | */
1102 /* INTSTAT_TXC | */ INTSTAT_TCC | INTSTAT_TQE | INTSTAT_TXU |
1105 /* Acknowledge all pending interrupts */
1106 CSR_WRITE_4(sc, INTSTAT, CSR_READ_4(sc, INTSTAT));
1108 /* Enable interrupts, set for PCI read multiple and etc */
1109 CSR_WRITE_4(sc, GENCTL,
1110 GENCTL_ENABLE_INTERRUPT | GENCTL_MEMORY_READ_MULTIPLE |
1111 GENCTL_ONECOPY | GENCTL_RECEIVE_FIFO_THRESHOLD64);
1113 /* Mark interface running ... */
1114 if (ifp->if_flags & IFF_UP) ifp->if_flags |= IFF_RUNNING;
1115 else ifp->if_flags &= ~IFF_RUNNING;
1118 ifq_clr_oactive(&ifp->if_snd);
1120 /* Start Rx process */
1121 epic_start_activity(sc);
1123 /* Set appropriate media */
1124 epic_ifmedia_upd(ifp);
1126 callout_reset(&sc->tx_stat_timer, hz, epic_stats_update, sc);
1132 * Synopsis: calculate and set Rx mode. Chip must be in idle state to
1136 epic_set_rx_mode(epic_softc_t *sc)
1138 u_int32_t flags = sc->sc_if.if_flags;
1139 u_int32_t rxcon = RXCON_DEFAULT;
1141 #if defined(EPIC_EARLY_RX)
1142 rxcon |= RXCON_EARLY_RX;
1145 rxcon |= (flags & IFF_PROMISC) ? RXCON_PROMISCUOUS_MODE : 0;
1147 CSR_WRITE_4(sc, RXCON, rxcon);
1153 * Synopsis: Set transmit control register. Chip must be in idle state to
1157 epic_set_tx_mode(epic_softc_t *sc)
1159 if (sc->txcon & TXCON_EARLY_TRANSMIT_ENABLE)
1160 CSR_WRITE_4(sc, ETXTHR, sc->tx_threshold);
1162 CSR_WRITE_4(sc, TXCON, sc->txcon);
1166 * Synopsis: Program multicast filter honoring IFF_ALLMULTI and IFF_PROMISC
1167 * flags. (Note, that setting PROMISC bit in EPIC's RXCON will only touch
1168 * individual frames, multicast filter must be manually programmed)
1170 * Note: EPIC must be in idle state.
1173 epic_set_mc_table(epic_softc_t *sc)
1175 struct ifnet *ifp = &sc->sc_if;
1176 struct ifmultiaddr *ifma;
1177 u_int16_t filter[4];
1180 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
1181 CSR_WRITE_4(sc, MC0, 0xFFFF);
1182 CSR_WRITE_4(sc, MC1, 0xFFFF);
1183 CSR_WRITE_4(sc, MC2, 0xFFFF);
1184 CSR_WRITE_4(sc, MC3, 0xFFFF);
1194 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1195 if (ifma->ifma_addr->sa_family != AF_LINK)
1197 h = (ether_crc32_be(
1198 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1199 ETHER_ADDR_LEN) >> 26) & 0x3f;
1200 filter[h >> 4] |= 1 << (h & 0xF);
1203 CSR_WRITE_4(sc, MC0, filter[0]);
1204 CSR_WRITE_4(sc, MC1, filter[1]);
1205 CSR_WRITE_4(sc, MC2, filter[2]);
1206 CSR_WRITE_4(sc, MC3, filter[3]);
1212 * Synopsis: Start receive process and transmit one, if they need.
1215 epic_start_activity(epic_softc_t *sc)
1217 /* Start rx process */
1218 CSR_WRITE_4(sc, COMMAND,
1219 COMMAND_RXQUEUED | COMMAND_START_RX |
1220 (sc->pending_txs?COMMAND_TXQUEUED:0));
1224 * Synopsis: Completely stop Rx and Tx processes. If TQE is set additional
1225 * packet needs to be queued to stop Tx DMA.
1228 epic_stop_activity(epic_softc_t *sc)
1232 /* Stop Tx and Rx DMA */
1233 CSR_WRITE_4(sc, COMMAND,
1234 COMMAND_STOP_RX | COMMAND_STOP_RDMA | COMMAND_STOP_TDMA);
1236 /* Wait Rx and Tx DMA to stop (why 1 ms ??? XXX) */
1237 for (i=0; i<0x1000; i++) {
1238 status = CSR_READ_4(sc, INTSTAT) & (INTSTAT_TXIDLE | INTSTAT_RXIDLE);
1239 if (status == (INTSTAT_TXIDLE | INTSTAT_RXIDLE))
1244 /* Catch all finished packets */
1248 status = CSR_READ_4(sc, INTSTAT);
1250 if ((status & INTSTAT_RXIDLE) == 0)
1251 if_printf(&sc->sc_if, "ERROR! Can't stop Rx DMA\n");
1253 if ((status & INTSTAT_TXIDLE) == 0)
1254 if_printf(&sc->sc_if, "ERROR! Can't stop Tx DMA\n");
1257 * May need to queue one more packet if TQE, this is rare
1258 * but existing case.
1260 if ((status & INTSTAT_TQE) && !(status & INTSTAT_TXIDLE))
1261 epic_queue_last_packet(sc);
1266 * The EPIC transmitter may stuck in TQE state. It will not go IDLE until
1267 * a packet from current descriptor will be copied to internal RAM. We
1268 * compose a dummy packet here and queue it for transmission.
1270 * XXX the packet will then be actually sent over network...
1273 epic_queue_last_packet(epic_softc_t *sc)
1275 struct epic_tx_desc *desc;
1276 struct epic_frag_list *flist;
1277 struct epic_tx_buffer *buf;
1281 if_printf(&sc->sc_if, "queue last packet\n");
1283 desc = sc->tx_desc + sc->cur_tx;
1284 flist = sc->tx_flist + sc->cur_tx;
1285 buf = sc->tx_buffer + sc->cur_tx;
1287 if ((desc->status & 0x8000) || (buf->mbuf != NULL))
1290 MGETHDR(m0, MB_DONTWAIT, MT_DATA);
1295 m0->m_len = min(MHLEN, ETHER_MIN_LEN-ETHER_CRC_LEN);
1296 flist->frag[0].fraglen = m0->m_len;
1297 m0->m_pkthdr.len = m0->m_len;
1298 m0->m_pkthdr.rcvif = &sc->sc_if;
1299 bzero(mtod(m0,caddr_t), m0->m_len);
1301 /* Fill fragments list */
1302 flist->frag[0].fraglen = m0->m_len;
1303 flist->frag[0].fragaddr = vtophys(mtod(m0, caddr_t));
1304 flist->numfrags = 1;
1306 /* Fill in descriptor */
1309 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
1310 desc->control = 0x01;
1311 desc->txlength = max(m0->m_pkthdr.len,ETHER_MIN_LEN-ETHER_CRC_LEN);
1312 desc->status = 0x8000;
1314 /* Launch transmition */
1315 CSR_WRITE_4(sc, COMMAND, COMMAND_STOP_TDMA | COMMAND_TXQUEUED);
1317 /* Wait Tx DMA to stop (for how long??? XXX) */
1318 for (i=0; i<1000; i++) {
1319 if (CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE)
1324 if ((CSR_READ_4(sc, INTSTAT) & INTSTAT_TXIDLE) == 0)
1325 if_printf(&sc->sc_if, "ERROR! can't stop Tx DMA (2)\n");
1333 * Synopsis: Shut down board and deallocates rings.
1336 epic_stop(epic_softc_t *sc)
1338 sc->sc_if.if_timer = 0;
1340 callout_stop(&sc->tx_stat_timer);
1342 /* Disable interrupts */
1343 CSR_WRITE_4(sc, INTMASK, 0);
1344 CSR_WRITE_4(sc, GENCTL, 0);
1346 /* Try to stop Rx and TX processes */
1347 epic_stop_activity(sc);
1350 CSR_WRITE_4(sc, GENCTL, GENCTL_SOFT_RESET);
1353 /* Make chip go to bed */
1354 CSR_WRITE_4(sc, GENCTL, GENCTL_POWER_DOWN);
1356 /* Free memory allocated for rings */
1357 epic_free_rings(sc);
1359 /* Mark as stoped */
1360 sc->sc_if.if_flags &= ~IFF_RUNNING;
1364 * Synopsis: This function should free all memory allocated for rings.
1367 epic_free_rings(epic_softc_t *sc)
1371 for (i=0; i<RX_RING_SIZE; i++) {
1372 struct epic_rx_buffer *buf = sc->rx_buffer + i;
1373 struct epic_rx_desc *desc = sc->rx_desc + i;
1376 desc->buflength = 0;
1379 if (buf->mbuf) m_freem(buf->mbuf);
1383 for (i=0; i<TX_RING_SIZE; i++) {
1384 struct epic_tx_buffer *buf = sc->tx_buffer + i;
1385 struct epic_tx_desc *desc = sc->tx_desc + i;
1388 desc->buflength = 0;
1391 if (buf->mbuf) m_freem(buf->mbuf);
1397 * Synopsis: Allocates mbufs for Rx ring and point Rx descs to them.
1398 * Point Tx descs to fragment lists. Check that all descs and fraglists
1399 * are bounded and aligned properly.
1402 epic_init_rings(epic_softc_t *sc)
1406 sc->cur_rx = sc->cur_tx = sc->dirty_tx = sc->pending_txs = 0;
1408 for (i = 0; i < RX_RING_SIZE; i++) {
1409 struct epic_rx_buffer *buf = sc->rx_buffer + i;
1410 struct epic_rx_desc *desc = sc->rx_desc + i;
1412 desc->status = 0; /* Owned by driver */
1413 desc->next = vtophys(sc->rx_desc + ((i+1) & RX_RING_MASK));
1415 if ((desc->next & 3) ||
1416 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) {
1417 epic_free_rings(sc);
1421 buf->mbuf = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
1422 if (NULL == buf->mbuf) {
1423 epic_free_rings(sc);
1426 desc->bufaddr = vtophys(mtod(buf->mbuf, caddr_t));
1428 desc->buflength = MCLBYTES; /* Max RX buffer length */
1429 desc->status = 0x8000; /* Set owner bit to NIC */
1432 for (i = 0; i < TX_RING_SIZE; i++) {
1433 struct epic_tx_buffer *buf = sc->tx_buffer + i;
1434 struct epic_tx_desc *desc = sc->tx_desc + i;
1437 desc->next = vtophys(sc->tx_desc + ((i+1) & TX_RING_MASK));
1439 if ((desc->next & 3) ||
1440 ((desc->next & PAGE_MASK) + sizeof *desc) > PAGE_SIZE) {
1441 epic_free_rings(sc);
1446 desc->bufaddr = vtophys(sc->tx_flist + i);
1448 if ((desc->bufaddr & 3) ||
1449 ((desc->bufaddr & PAGE_MASK) + sizeof(struct epic_frag_list)) > PAGE_SIZE) {
1450 epic_free_rings(sc);
1459 * EEPROM operation functions
1462 epic_write_eepromreg(epic_softc_t *sc, u_int8_t val)
1466 CSR_WRITE_1(sc, EECTL, val);
1468 for (i=0; i<0xFF; i++)
1469 if ((CSR_READ_1(sc, EECTL) & 0x20) == 0) break;
1475 epic_read_eepromreg(epic_softc_t *sc)
1477 return CSR_READ_1(sc, EECTL);
1481 epic_eeprom_clock(epic_softc_t *sc, u_int8_t val)
1483 epic_write_eepromreg(sc, val);
1484 epic_write_eepromreg(sc, (val | 0x4));
1485 epic_write_eepromreg(sc, val);
1487 return epic_read_eepromreg(sc);
1491 epic_output_eepromw(epic_softc_t *sc, u_int16_t val)
1495 for (i = 0xF; i >= 0; i--) {
1497 epic_eeprom_clock(sc, 0x0B);
1499 epic_eeprom_clock(sc, 0x03);
1504 epic_input_eepromw(epic_softc_t *sc)
1506 u_int16_t retval = 0;
1509 for (i = 0xF; i >= 0; i--) {
1510 if (epic_eeprom_clock(sc, 0x3) & 0x10)
1518 epic_read_eeprom(epic_softc_t *sc, u_int16_t loc)
1523 epic_write_eepromreg(sc, 3);
1525 if (epic_read_eepromreg(sc) & 0x40)
1526 read_cmd = (loc & 0x3F) | 0x180;
1528 read_cmd = (loc & 0xFF) | 0x600;
1530 epic_output_eepromw(sc, read_cmd);
1532 dataval = epic_input_eepromw(sc);
1534 epic_write_eepromreg(sc, 1);
1540 * Here goes MII read/write routines
1543 epic_read_phy_reg(epic_softc_t *sc, int phy, int reg)
1547 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x01));
1549 for (i = 0; i < 0x100; i++) {
1550 if ((CSR_READ_4(sc, MIICTL) & 0x01) == 0) break;
1554 return (CSR_READ_4(sc, MIIDATA));
1558 epic_write_phy_reg(epic_softc_t *sc, int phy, int reg, int val)
1562 CSR_WRITE_4(sc, MIIDATA, val);
1563 CSR_WRITE_4(sc, MIICTL, ((reg << 4) | (phy << 9) | 0x02));
1565 for(i=0;i<0x100;i++) {
1566 if ((CSR_READ_4(sc, MIICTL) & 0x02) == 0) break;
1574 epic_miibus_readreg(device_t dev, int phy, int reg)
1578 sc = device_get_softc(dev);
1580 return (PHY_READ_2(sc, phy, reg));
1584 epic_miibus_writereg(device_t dev, int phy, int reg, int data)
1588 sc = device_get_softc(dev);
1590 PHY_WRITE_2(sc, phy, reg, data);