3 * Copyright 2008 (c) Intel Corporation
4 * Jesse Barnes <jbarnes@virtuousgeek.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 * $FreeBSD: src/sys/dev/drm2/i915/i915_suspend.c,v 1.1 2012/05/22 11:07:44 kib Exp $
29 #include <dev/drm/drmP.h>
30 #include <dev/drm/drm.h>
32 #include "intel_drv.h"
34 static bool i915_pipe_enabled(struct drm_device *dev, enum i915_pipe pipe)
36 struct drm_i915_private *dev_priv = dev->dev_private;
39 /* On IVB, 3rd pipe shares PLL with another one */
43 if (HAS_PCH_SPLIT(dev))
44 dpll_reg = PCH_DPLL(pipe);
46 dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B;
48 return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE);
51 static void i915_save_palette(struct drm_device *dev, enum i915_pipe pipe)
53 struct drm_i915_private *dev_priv = dev->dev_private;
54 unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
58 if (!i915_pipe_enabled(dev, pipe))
61 if (HAS_PCH_SPLIT(dev))
62 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
65 array = dev_priv->save_palette_a;
67 array = dev_priv->save_palette_b;
69 for (i = 0; i < 256; i++)
70 array[i] = I915_READ(reg + (i << 2));
73 static void i915_restore_palette(struct drm_device *dev, enum i915_pipe pipe)
75 struct drm_i915_private *dev_priv = dev->dev_private;
76 unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B);
80 if (!i915_pipe_enabled(dev, pipe))
83 if (HAS_PCH_SPLIT(dev))
84 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B;
87 array = dev_priv->save_palette_a;
89 array = dev_priv->save_palette_b;
91 for (i = 0; i < 256; i++)
92 I915_WRITE(reg + (i << 2), array[i]);
95 static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
97 struct drm_i915_private *dev_priv = dev->dev_private;
99 I915_WRITE8(index_port, reg);
100 return I915_READ8(data_port);
103 static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
105 struct drm_i915_private *dev_priv = dev->dev_private;
108 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
109 return I915_READ8(VGA_AR_DATA_READ);
112 static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
114 struct drm_i915_private *dev_priv = dev->dev_private;
117 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
118 I915_WRITE8(VGA_AR_DATA_WRITE, val);
121 static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
123 struct drm_i915_private *dev_priv = dev->dev_private;
125 I915_WRITE8(index_port, reg);
126 I915_WRITE8(data_port, val);
129 static void i915_save_vga(struct drm_device *dev)
131 struct drm_i915_private *dev_priv = dev->dev_private;
133 u16 cr_index, cr_data, st01;
135 /* VGA color palette registers */
136 dev_priv->saveDACMASK = I915_READ8(VGA_DACMASK);
139 dev_priv->saveMSR = I915_READ8(VGA_MSR_READ);
140 if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
141 cr_index = VGA_CR_INDEX_CGA;
142 cr_data = VGA_CR_DATA_CGA;
145 cr_index = VGA_CR_INDEX_MDA;
146 cr_data = VGA_CR_DATA_MDA;
150 /* CRT controller regs */
151 i915_write_indexed(dev, cr_index, cr_data, 0x11,
152 i915_read_indexed(dev, cr_index, cr_data, 0x11) &
154 for (i = 0; i <= 0x24; i++)
155 dev_priv->saveCR[i] =
156 i915_read_indexed(dev, cr_index, cr_data, i);
157 /* Make sure we don't turn off CR group 0 writes */
158 dev_priv->saveCR[0x11] &= ~0x80;
160 /* Attribute controller registers */
162 dev_priv->saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
163 for (i = 0; i <= 0x14; i++)
164 dev_priv->saveAR[i] = i915_read_ar(dev, st01, i, 0);
166 I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX);
169 /* Graphics controller registers */
170 for (i = 0; i < 9; i++)
171 dev_priv->saveGR[i] =
172 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);
174 dev_priv->saveGR[0x10] =
175 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
176 dev_priv->saveGR[0x11] =
177 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
178 dev_priv->saveGR[0x18] =
179 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
181 /* Sequencer registers */
182 for (i = 0; i < 8; i++)
183 dev_priv->saveSR[i] =
184 i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
187 static void i915_restore_vga(struct drm_device *dev)
189 struct drm_i915_private *dev_priv = dev->dev_private;
191 u16 cr_index, cr_data, st01;
194 I915_WRITE8(VGA_MSR_WRITE, dev_priv->saveMSR);
195 if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
196 cr_index = VGA_CR_INDEX_CGA;
197 cr_data = VGA_CR_DATA_CGA;
200 cr_index = VGA_CR_INDEX_MDA;
201 cr_data = VGA_CR_DATA_MDA;
205 /* Sequencer registers, don't write SR07 */
206 for (i = 0; i < 7; i++)
207 i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
208 dev_priv->saveSR[i]);
210 /* CRT controller regs */
211 /* Enable CR group 0 writes */
212 i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
213 for (i = 0; i <= 0x24; i++)
214 i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->saveCR[i]);
216 /* Graphics controller regs */
217 for (i = 0; i < 9; i++)
218 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
219 dev_priv->saveGR[i]);
221 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
222 dev_priv->saveGR[0x10]);
223 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
224 dev_priv->saveGR[0x11]);
225 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
226 dev_priv->saveGR[0x18]);
228 /* Attribute controller registers */
229 I915_READ8(st01); /* switch back to index mode */
230 for (i = 0; i <= 0x14; i++)
231 i915_write_ar(dev, st01, i, dev_priv->saveAR[i], 0);
232 I915_READ8(st01); /* switch back to index mode */
233 I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX | 0x20);
236 /* VGA color palette registers */
237 I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK);
240 static void i915_save_modeset_reg(struct drm_device *dev)
242 struct drm_i915_private *dev_priv = dev->dev_private;
245 if (drm_core_check_feature(dev, DRIVER_MODESET))
249 dev_priv->saveCURACNTR = I915_READ(_CURACNTR);
250 dev_priv->saveCURAPOS = I915_READ(_CURAPOS);
251 dev_priv->saveCURABASE = I915_READ(_CURABASE);
252 dev_priv->saveCURBCNTR = I915_READ(_CURBCNTR);
253 dev_priv->saveCURBPOS = I915_READ(_CURBPOS);
254 dev_priv->saveCURBBASE = I915_READ(_CURBBASE);
256 dev_priv->saveCURSIZE = I915_READ(CURSIZE);
258 if (HAS_PCH_SPLIT(dev)) {
259 dev_priv->savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL);
260 dev_priv->saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL);
263 /* Pipe & plane A info */
264 dev_priv->savePIPEACONF = I915_READ(_PIPEACONF);
265 dev_priv->savePIPEASRC = I915_READ(_PIPEASRC);
266 if (HAS_PCH_SPLIT(dev)) {
267 dev_priv->saveFPA0 = I915_READ(_PCH_FPA0);
268 dev_priv->saveFPA1 = I915_READ(_PCH_FPA1);
269 dev_priv->saveDPLL_A = I915_READ(_PCH_DPLL_A);
271 dev_priv->saveFPA0 = I915_READ(_FPA0);
272 dev_priv->saveFPA1 = I915_READ(_FPA1);
273 dev_priv->saveDPLL_A = I915_READ(_DPLL_A);
275 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
276 dev_priv->saveDPLL_A_MD = I915_READ(_DPLL_A_MD);
277 dev_priv->saveHTOTAL_A = I915_READ(_HTOTAL_A);
278 dev_priv->saveHBLANK_A = I915_READ(_HBLANK_A);
279 dev_priv->saveHSYNC_A = I915_READ(_HSYNC_A);
280 dev_priv->saveVTOTAL_A = I915_READ(_VTOTAL_A);
281 dev_priv->saveVBLANK_A = I915_READ(_VBLANK_A);
282 dev_priv->saveVSYNC_A = I915_READ(_VSYNC_A);
283 if (!HAS_PCH_SPLIT(dev))
284 dev_priv->saveBCLRPAT_A = I915_READ(_BCLRPAT_A);
286 if (HAS_PCH_SPLIT(dev)) {
287 dev_priv->savePIPEA_DATA_M1 = I915_READ(_PIPEA_DATA_M1);
288 dev_priv->savePIPEA_DATA_N1 = I915_READ(_PIPEA_DATA_N1);
289 dev_priv->savePIPEA_LINK_M1 = I915_READ(_PIPEA_LINK_M1);
290 dev_priv->savePIPEA_LINK_N1 = I915_READ(_PIPEA_LINK_N1);
292 dev_priv->saveFDI_TXA_CTL = I915_READ(_FDI_TXA_CTL);
293 dev_priv->saveFDI_RXA_CTL = I915_READ(_FDI_RXA_CTL);
295 dev_priv->savePFA_CTL_1 = I915_READ(_PFA_CTL_1);
296 dev_priv->savePFA_WIN_SZ = I915_READ(_PFA_WIN_SZ);
297 dev_priv->savePFA_WIN_POS = I915_READ(_PFA_WIN_POS);
299 dev_priv->saveTRANSACONF = I915_READ(_TRANSACONF);
300 dev_priv->saveTRANS_HTOTAL_A = I915_READ(_TRANS_HTOTAL_A);
301 dev_priv->saveTRANS_HBLANK_A = I915_READ(_TRANS_HBLANK_A);
302 dev_priv->saveTRANS_HSYNC_A = I915_READ(_TRANS_HSYNC_A);
303 dev_priv->saveTRANS_VTOTAL_A = I915_READ(_TRANS_VTOTAL_A);
304 dev_priv->saveTRANS_VBLANK_A = I915_READ(_TRANS_VBLANK_A);
305 dev_priv->saveTRANS_VSYNC_A = I915_READ(_TRANS_VSYNC_A);
308 dev_priv->saveDSPACNTR = I915_READ(_DSPACNTR);
309 dev_priv->saveDSPASTRIDE = I915_READ(_DSPASTRIDE);
310 dev_priv->saveDSPASIZE = I915_READ(_DSPASIZE);
311 dev_priv->saveDSPAPOS = I915_READ(_DSPAPOS);
312 dev_priv->saveDSPAADDR = I915_READ(_DSPAADDR);
313 if (INTEL_INFO(dev)->gen >= 4) {
314 dev_priv->saveDSPASURF = I915_READ(_DSPASURF);
315 dev_priv->saveDSPATILEOFF = I915_READ(_DSPATILEOFF);
317 i915_save_palette(dev, PIPE_A);
318 dev_priv->savePIPEASTAT = I915_READ(_PIPEASTAT);
320 /* Pipe & plane B info */
321 dev_priv->savePIPEBCONF = I915_READ(_PIPEBCONF);
322 dev_priv->savePIPEBSRC = I915_READ(_PIPEBSRC);
323 if (HAS_PCH_SPLIT(dev)) {
324 dev_priv->saveFPB0 = I915_READ(_PCH_FPB0);
325 dev_priv->saveFPB1 = I915_READ(_PCH_FPB1);
326 dev_priv->saveDPLL_B = I915_READ(_PCH_DPLL_B);
328 dev_priv->saveFPB0 = I915_READ(_FPB0);
329 dev_priv->saveFPB1 = I915_READ(_FPB1);
330 dev_priv->saveDPLL_B = I915_READ(_DPLL_B);
332 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
333 dev_priv->saveDPLL_B_MD = I915_READ(_DPLL_B_MD);
334 dev_priv->saveHTOTAL_B = I915_READ(_HTOTAL_B);
335 dev_priv->saveHBLANK_B = I915_READ(_HBLANK_B);
336 dev_priv->saveHSYNC_B = I915_READ(_HSYNC_B);
337 dev_priv->saveVTOTAL_B = I915_READ(_VTOTAL_B);
338 dev_priv->saveVBLANK_B = I915_READ(_VBLANK_B);
339 dev_priv->saveVSYNC_B = I915_READ(_VSYNC_B);
340 if (!HAS_PCH_SPLIT(dev))
341 dev_priv->saveBCLRPAT_B = I915_READ(_BCLRPAT_B);
343 if (HAS_PCH_SPLIT(dev)) {
344 dev_priv->savePIPEB_DATA_M1 = I915_READ(_PIPEB_DATA_M1);
345 dev_priv->savePIPEB_DATA_N1 = I915_READ(_PIPEB_DATA_N1);
346 dev_priv->savePIPEB_LINK_M1 = I915_READ(_PIPEB_LINK_M1);
347 dev_priv->savePIPEB_LINK_N1 = I915_READ(_PIPEB_LINK_N1);
349 dev_priv->saveFDI_TXB_CTL = I915_READ(_FDI_TXB_CTL);
350 dev_priv->saveFDI_RXB_CTL = I915_READ(_FDI_RXB_CTL);
352 dev_priv->savePFB_CTL_1 = I915_READ(_PFB_CTL_1);
353 dev_priv->savePFB_WIN_SZ = I915_READ(_PFB_WIN_SZ);
354 dev_priv->savePFB_WIN_POS = I915_READ(_PFB_WIN_POS);
356 dev_priv->saveTRANSBCONF = I915_READ(_TRANSBCONF);
357 dev_priv->saveTRANS_HTOTAL_B = I915_READ(_TRANS_HTOTAL_B);
358 dev_priv->saveTRANS_HBLANK_B = I915_READ(_TRANS_HBLANK_B);
359 dev_priv->saveTRANS_HSYNC_B = I915_READ(_TRANS_HSYNC_B);
360 dev_priv->saveTRANS_VTOTAL_B = I915_READ(_TRANS_VTOTAL_B);
361 dev_priv->saveTRANS_VBLANK_B = I915_READ(_TRANS_VBLANK_B);
362 dev_priv->saveTRANS_VSYNC_B = I915_READ(_TRANS_VSYNC_B);
365 dev_priv->saveDSPBCNTR = I915_READ(_DSPBCNTR);
366 dev_priv->saveDSPBSTRIDE = I915_READ(_DSPBSTRIDE);
367 dev_priv->saveDSPBSIZE = I915_READ(_DSPBSIZE);
368 dev_priv->saveDSPBPOS = I915_READ(_DSPBPOS);
369 dev_priv->saveDSPBADDR = I915_READ(_DSPBADDR);
370 if (INTEL_INFO(dev)->gen >= 4) {
371 dev_priv->saveDSPBSURF = I915_READ(_DSPBSURF);
372 dev_priv->saveDSPBTILEOFF = I915_READ(_DSPBTILEOFF);
374 i915_save_palette(dev, PIPE_B);
375 dev_priv->savePIPEBSTAT = I915_READ(_PIPEBSTAT);
378 switch (INTEL_INFO(dev)->gen) {
381 for (i = 0; i < 16; i++)
382 dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
386 for (i = 0; i < 16; i++)
387 dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
390 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
391 for (i = 0; i < 8; i++)
392 dev_priv->saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
394 for (i = 0; i < 8; i++)
395 dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
402 static void i915_restore_modeset_reg(struct drm_device *dev)
404 struct drm_i915_private *dev_priv = dev->dev_private;
405 int dpll_a_reg, fpa0_reg, fpa1_reg;
406 int dpll_b_reg, fpb0_reg, fpb1_reg;
409 if (drm_core_check_feature(dev, DRIVER_MODESET))
413 switch (INTEL_INFO(dev)->gen) {
416 for (i = 0; i < 16; i++)
417 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), dev_priv->saveFENCE[i]);
421 for (i = 0; i < 16; i++)
422 I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->saveFENCE[i]);
426 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
427 for (i = 0; i < 8; i++)
428 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]);
429 for (i = 0; i < 8; i++)
430 I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]);
435 if (HAS_PCH_SPLIT(dev)) {
436 dpll_a_reg = _PCH_DPLL_A;
437 dpll_b_reg = _PCH_DPLL_B;
438 fpa0_reg = _PCH_FPA0;
439 fpb0_reg = _PCH_FPB0;
440 fpa1_reg = _PCH_FPA1;
441 fpb1_reg = _PCH_FPB1;
443 dpll_a_reg = _DPLL_A;
444 dpll_b_reg = _DPLL_B;
451 if (HAS_PCH_SPLIT(dev)) {
452 I915_WRITE(PCH_DREF_CONTROL, dev_priv->savePCH_DREF_CONTROL);
453 I915_WRITE(DISP_ARB_CTL, dev_priv->saveDISP_ARB_CTL);
456 /* Pipe & plane A info */
457 /* Prime the clock */
458 if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
459 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A &
461 POSTING_READ(dpll_a_reg);
464 I915_WRITE(fpa0_reg, dev_priv->saveFPA0);
465 I915_WRITE(fpa1_reg, dev_priv->saveFPA1);
466 /* Actually enable it */
467 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A);
468 POSTING_READ(dpll_a_reg);
470 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
471 I915_WRITE(_DPLL_A_MD, dev_priv->saveDPLL_A_MD);
472 POSTING_READ(_DPLL_A_MD);
477 I915_WRITE(_HTOTAL_A, dev_priv->saveHTOTAL_A);
478 I915_WRITE(_HBLANK_A, dev_priv->saveHBLANK_A);
479 I915_WRITE(_HSYNC_A, dev_priv->saveHSYNC_A);
480 I915_WRITE(_VTOTAL_A, dev_priv->saveVTOTAL_A);
481 I915_WRITE(_VBLANK_A, dev_priv->saveVBLANK_A);
482 I915_WRITE(_VSYNC_A, dev_priv->saveVSYNC_A);
483 if (!HAS_PCH_SPLIT(dev))
484 I915_WRITE(_BCLRPAT_A, dev_priv->saveBCLRPAT_A);
486 if (HAS_PCH_SPLIT(dev)) {
487 I915_WRITE(_PIPEA_DATA_M1, dev_priv->savePIPEA_DATA_M1);
488 I915_WRITE(_PIPEA_DATA_N1, dev_priv->savePIPEA_DATA_N1);
489 I915_WRITE(_PIPEA_LINK_M1, dev_priv->savePIPEA_LINK_M1);
490 I915_WRITE(_PIPEA_LINK_N1, dev_priv->savePIPEA_LINK_N1);
492 I915_WRITE(_FDI_RXA_CTL, dev_priv->saveFDI_RXA_CTL);
493 I915_WRITE(_FDI_TXA_CTL, dev_priv->saveFDI_TXA_CTL);
495 I915_WRITE(_PFA_CTL_1, dev_priv->savePFA_CTL_1);
496 I915_WRITE(_PFA_WIN_SZ, dev_priv->savePFA_WIN_SZ);
497 I915_WRITE(_PFA_WIN_POS, dev_priv->savePFA_WIN_POS);
499 I915_WRITE(_TRANSACONF, dev_priv->saveTRANSACONF);
500 I915_WRITE(_TRANS_HTOTAL_A, dev_priv->saveTRANS_HTOTAL_A);
501 I915_WRITE(_TRANS_HBLANK_A, dev_priv->saveTRANS_HBLANK_A);
502 I915_WRITE(_TRANS_HSYNC_A, dev_priv->saveTRANS_HSYNC_A);
503 I915_WRITE(_TRANS_VTOTAL_A, dev_priv->saveTRANS_VTOTAL_A);
504 I915_WRITE(_TRANS_VBLANK_A, dev_priv->saveTRANS_VBLANK_A);
505 I915_WRITE(_TRANS_VSYNC_A, dev_priv->saveTRANS_VSYNC_A);
508 /* Restore plane info */
509 I915_WRITE(_DSPASIZE, dev_priv->saveDSPASIZE);
510 I915_WRITE(_DSPAPOS, dev_priv->saveDSPAPOS);
511 I915_WRITE(_PIPEASRC, dev_priv->savePIPEASRC);
512 I915_WRITE(_DSPAADDR, dev_priv->saveDSPAADDR);
513 I915_WRITE(_DSPASTRIDE, dev_priv->saveDSPASTRIDE);
514 if (INTEL_INFO(dev)->gen >= 4) {
515 I915_WRITE(_DSPASURF, dev_priv->saveDSPASURF);
516 I915_WRITE(_DSPATILEOFF, dev_priv->saveDSPATILEOFF);
519 I915_WRITE(_PIPEACONF, dev_priv->savePIPEACONF);
521 i915_restore_palette(dev, PIPE_A);
522 /* Enable the plane */
523 I915_WRITE(_DSPACNTR, dev_priv->saveDSPACNTR);
524 I915_WRITE(_DSPAADDR, I915_READ(_DSPAADDR));
526 /* Pipe & plane B info */
527 if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
528 I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B &
530 POSTING_READ(dpll_b_reg);
533 I915_WRITE(fpb0_reg, dev_priv->saveFPB0);
534 I915_WRITE(fpb1_reg, dev_priv->saveFPB1);
535 /* Actually enable it */
536 I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B);
537 POSTING_READ(dpll_b_reg);
539 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
540 I915_WRITE(_DPLL_B_MD, dev_priv->saveDPLL_B_MD);
541 POSTING_READ(_DPLL_B_MD);
546 I915_WRITE(_HTOTAL_B, dev_priv->saveHTOTAL_B);
547 I915_WRITE(_HBLANK_B, dev_priv->saveHBLANK_B);
548 I915_WRITE(_HSYNC_B, dev_priv->saveHSYNC_B);
549 I915_WRITE(_VTOTAL_B, dev_priv->saveVTOTAL_B);
550 I915_WRITE(_VBLANK_B, dev_priv->saveVBLANK_B);
551 I915_WRITE(_VSYNC_B, dev_priv->saveVSYNC_B);
552 if (!HAS_PCH_SPLIT(dev))
553 I915_WRITE(_BCLRPAT_B, dev_priv->saveBCLRPAT_B);
555 if (HAS_PCH_SPLIT(dev)) {
556 I915_WRITE(_PIPEB_DATA_M1, dev_priv->savePIPEB_DATA_M1);
557 I915_WRITE(_PIPEB_DATA_N1, dev_priv->savePIPEB_DATA_N1);
558 I915_WRITE(_PIPEB_LINK_M1, dev_priv->savePIPEB_LINK_M1);
559 I915_WRITE(_PIPEB_LINK_N1, dev_priv->savePIPEB_LINK_N1);
561 I915_WRITE(_FDI_RXB_CTL, dev_priv->saveFDI_RXB_CTL);
562 I915_WRITE(_FDI_TXB_CTL, dev_priv->saveFDI_TXB_CTL);
564 I915_WRITE(_PFB_CTL_1, dev_priv->savePFB_CTL_1);
565 I915_WRITE(_PFB_WIN_SZ, dev_priv->savePFB_WIN_SZ);
566 I915_WRITE(_PFB_WIN_POS, dev_priv->savePFB_WIN_POS);
568 I915_WRITE(_TRANSBCONF, dev_priv->saveTRANSBCONF);
569 I915_WRITE(_TRANS_HTOTAL_B, dev_priv->saveTRANS_HTOTAL_B);
570 I915_WRITE(_TRANS_HBLANK_B, dev_priv->saveTRANS_HBLANK_B);
571 I915_WRITE(_TRANS_HSYNC_B, dev_priv->saveTRANS_HSYNC_B);
572 I915_WRITE(_TRANS_VTOTAL_B, dev_priv->saveTRANS_VTOTAL_B);
573 I915_WRITE(_TRANS_VBLANK_B, dev_priv->saveTRANS_VBLANK_B);
574 I915_WRITE(_TRANS_VSYNC_B, dev_priv->saveTRANS_VSYNC_B);
577 /* Restore plane info */
578 I915_WRITE(_DSPBSIZE, dev_priv->saveDSPBSIZE);
579 I915_WRITE(_DSPBPOS, dev_priv->saveDSPBPOS);
580 I915_WRITE(_PIPEBSRC, dev_priv->savePIPEBSRC);
581 I915_WRITE(_DSPBADDR, dev_priv->saveDSPBADDR);
582 I915_WRITE(_DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
583 if (INTEL_INFO(dev)->gen >= 4) {
584 I915_WRITE(_DSPBSURF, dev_priv->saveDSPBSURF);
585 I915_WRITE(_DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
588 I915_WRITE(_PIPEBCONF, dev_priv->savePIPEBCONF);
590 i915_restore_palette(dev, PIPE_B);
591 /* Enable the plane */
592 I915_WRITE(_DSPBCNTR, dev_priv->saveDSPBCNTR);
593 I915_WRITE(_DSPBADDR, I915_READ(_DSPBADDR));
596 I915_WRITE(_CURAPOS, dev_priv->saveCURAPOS);
597 I915_WRITE(_CURACNTR, dev_priv->saveCURACNTR);
598 I915_WRITE(_CURABASE, dev_priv->saveCURABASE);
599 I915_WRITE(_CURBPOS, dev_priv->saveCURBPOS);
600 I915_WRITE(_CURBCNTR, dev_priv->saveCURBCNTR);
601 I915_WRITE(_CURBBASE, dev_priv->saveCURBBASE);
603 I915_WRITE(CURSIZE, dev_priv->saveCURSIZE);
608 static void i915_save_display(struct drm_device *dev)
610 struct drm_i915_private *dev_priv = dev->dev_private;
612 /* Display arbitration control */
613 dev_priv->saveDSPARB = I915_READ(DSPARB);
615 /* This is only meaningful in non-KMS mode */
616 /* Don't save them in KMS mode */
617 i915_save_modeset_reg(dev);
620 if (HAS_PCH_SPLIT(dev)) {
621 dev_priv->saveADPA = I915_READ(PCH_ADPA);
623 dev_priv->saveADPA = I915_READ(ADPA);
627 if (HAS_PCH_SPLIT(dev)) {
628 dev_priv->savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
629 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
630 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
631 dev_priv->saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
632 dev_priv->saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
633 dev_priv->saveLVDS = I915_READ(PCH_LVDS);
635 dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
636 dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
637 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
638 dev_priv->saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
639 if (INTEL_INFO(dev)->gen >= 4)
640 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
641 if (IS_MOBILE(dev) && !IS_I830(dev))
642 dev_priv->saveLVDS = I915_READ(LVDS);
645 if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
646 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
648 if (HAS_PCH_SPLIT(dev)) {
649 dev_priv->savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
650 dev_priv->savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
651 dev_priv->savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
653 dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
654 dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
655 dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
658 /* Display Port state */
659 if (SUPPORTS_INTEGRATED_DP(dev)) {
660 dev_priv->saveDP_B = I915_READ(DP_B);
661 dev_priv->saveDP_C = I915_READ(DP_C);
662 dev_priv->saveDP_D = I915_READ(DP_D);
663 dev_priv->savePIPEA_GMCH_DATA_M = I915_READ(_PIPEA_GMCH_DATA_M);
664 dev_priv->savePIPEB_GMCH_DATA_M = I915_READ(_PIPEB_GMCH_DATA_M);
665 dev_priv->savePIPEA_GMCH_DATA_N = I915_READ(_PIPEA_GMCH_DATA_N);
666 dev_priv->savePIPEB_GMCH_DATA_N = I915_READ(_PIPEB_GMCH_DATA_N);
667 dev_priv->savePIPEA_DP_LINK_M = I915_READ(_PIPEA_DP_LINK_M);
668 dev_priv->savePIPEB_DP_LINK_M = I915_READ(_PIPEB_DP_LINK_M);
669 dev_priv->savePIPEA_DP_LINK_N = I915_READ(_PIPEA_DP_LINK_N);
670 dev_priv->savePIPEB_DP_LINK_N = I915_READ(_PIPEB_DP_LINK_N);
672 /* FIXME: save TV & SDVO state */
674 /* Only save FBC state on the platform that supports FBC */
675 if (I915_HAS_FBC(dev)) {
676 if (HAS_PCH_SPLIT(dev)) {
677 dev_priv->saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE);
678 } else if (IS_GM45(dev)) {
679 dev_priv->saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
681 dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
682 dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
683 dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
684 dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
689 dev_priv->saveVGA0 = I915_READ(VGA0);
690 dev_priv->saveVGA1 = I915_READ(VGA1);
691 dev_priv->saveVGA_PD = I915_READ(VGA_PD);
692 if (HAS_PCH_SPLIT(dev))
693 dev_priv->saveVGACNTRL = I915_READ(CPU_VGACNTRL);
695 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
700 static void i915_restore_display(struct drm_device *dev)
702 struct drm_i915_private *dev_priv = dev->dev_private;
704 /* Display arbitration */
705 I915_WRITE(DSPARB, dev_priv->saveDSPARB);
707 /* Display port ratios (must be done before clock is set) */
708 if (SUPPORTS_INTEGRATED_DP(dev)) {
709 I915_WRITE(_PIPEA_GMCH_DATA_M, dev_priv->savePIPEA_GMCH_DATA_M);
710 I915_WRITE(_PIPEB_GMCH_DATA_M, dev_priv->savePIPEB_GMCH_DATA_M);
711 I915_WRITE(_PIPEA_GMCH_DATA_N, dev_priv->savePIPEA_GMCH_DATA_N);
712 I915_WRITE(_PIPEB_GMCH_DATA_N, dev_priv->savePIPEB_GMCH_DATA_N);
713 I915_WRITE(_PIPEA_DP_LINK_M, dev_priv->savePIPEA_DP_LINK_M);
714 I915_WRITE(_PIPEB_DP_LINK_M, dev_priv->savePIPEB_DP_LINK_M);
715 I915_WRITE(_PIPEA_DP_LINK_N, dev_priv->savePIPEA_DP_LINK_N);
716 I915_WRITE(_PIPEB_DP_LINK_N, dev_priv->savePIPEB_DP_LINK_N);
719 /* This is only meaningful in non-KMS mode */
720 /* Don't restore them in KMS mode */
721 i915_restore_modeset_reg(dev);
724 if (HAS_PCH_SPLIT(dev))
725 I915_WRITE(PCH_ADPA, dev_priv->saveADPA);
727 I915_WRITE(ADPA, dev_priv->saveADPA);
730 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
731 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
733 if (HAS_PCH_SPLIT(dev)) {
734 I915_WRITE(PCH_LVDS, dev_priv->saveLVDS);
735 } else if (IS_MOBILE(dev) && !IS_I830(dev))
736 I915_WRITE(LVDS, dev_priv->saveLVDS);
738 if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
739 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
741 if (HAS_PCH_SPLIT(dev)) {
742 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->saveBLC_PWM_CTL);
743 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->saveBLC_PWM_CTL2);
744 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL);
745 I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->saveBLC_CPU_PWM_CTL2);
746 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
747 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
748 I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR);
749 I915_WRITE(PCH_PP_CONTROL, dev_priv->savePP_CONTROL);
750 I915_WRITE(RSTDBYCTL,
751 dev_priv->saveMCHBAR_RENDER_STANDBY);
753 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
754 I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
755 I915_WRITE(BLC_HIST_CTL, dev_priv->saveBLC_HIST_CTL);
756 I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
757 I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
758 I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
759 I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
762 /* Display Port state */
763 if (SUPPORTS_INTEGRATED_DP(dev)) {
764 I915_WRITE(DP_B, dev_priv->saveDP_B);
765 I915_WRITE(DP_C, dev_priv->saveDP_C);
766 I915_WRITE(DP_D, dev_priv->saveDP_D);
768 /* FIXME: restore TV & SDVO state */
770 /* only restore FBC info on the platform that supports FBC*/
771 intel_disable_fbc(dev);
772 if (I915_HAS_FBC(dev)) {
773 if (HAS_PCH_SPLIT(dev)) {
774 I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
775 } else if (IS_GM45(dev)) {
776 I915_WRITE(DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
778 I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
779 I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
780 I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
781 I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
785 if (HAS_PCH_SPLIT(dev))
786 I915_WRITE(CPU_VGACNTRL, dev_priv->saveVGACNTRL);
788 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
790 I915_WRITE(VGA0, dev_priv->saveVGA0);
791 I915_WRITE(VGA1, dev_priv->saveVGA1);
792 I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
793 POSTING_READ(VGA_PD);
796 i915_restore_vga(dev);
799 int i915_save_state(struct drm_device *dev)
801 struct drm_i915_private *dev_priv = dev->dev_private;
804 dev_priv->saveLBB = pci_read_config(dev->device, LBB, 1);
806 /* Hardware status page */
807 dev_priv->saveHWS = I915_READ(HWS_PGA);
809 i915_save_display(dev);
811 /* Interrupt state */
812 if (HAS_PCH_SPLIT(dev)) {
813 dev_priv->saveDEIER = I915_READ(DEIER);
814 dev_priv->saveDEIMR = I915_READ(DEIMR);
815 dev_priv->saveGTIER = I915_READ(GTIER);
816 dev_priv->saveGTIMR = I915_READ(GTIMR);
817 dev_priv->saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);
818 dev_priv->saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);
819 dev_priv->saveMCHBAR_RENDER_STANDBY =
820 I915_READ(RSTDBYCTL);
821 dev_priv->savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);
823 dev_priv->saveIER = I915_READ(IER);
824 dev_priv->saveIMR = I915_READ(IMR);
827 if (IS_IRONLAKE_M(dev))
828 ironlake_disable_drps(dev);
829 if (INTEL_INFO(dev)->gen >= 6)
830 gen6_disable_rps(dev);
832 /* Cache mode state */
833 dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
835 /* Memory Arbitration state */
836 dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
839 for (i = 0; i < 16; i++) {
840 dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2));
841 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
843 for (i = 0; i < 3; i++)
844 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
849 int i915_restore_state(struct drm_device *dev)
851 struct drm_i915_private *dev_priv = dev->dev_private;
854 pci_write_config(dev->device, LBB, dev_priv->saveLBB, 1);
857 /* Hardware status page */
858 I915_WRITE(HWS_PGA, dev_priv->saveHWS);
860 i915_restore_display(dev);
862 /* Interrupt state */
863 if (HAS_PCH_SPLIT(dev)) {
864 I915_WRITE(DEIER, dev_priv->saveDEIER);
865 I915_WRITE(DEIMR, dev_priv->saveDEIMR);
866 I915_WRITE(GTIER, dev_priv->saveGTIER);
867 I915_WRITE(GTIMR, dev_priv->saveGTIMR);
868 I915_WRITE(_FDI_RXA_IMR, dev_priv->saveFDI_RXA_IMR);
869 I915_WRITE(_FDI_RXB_IMR, dev_priv->saveFDI_RXB_IMR);
870 I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->savePCH_PORT_HOTPLUG);
872 I915_WRITE(IER, dev_priv->saveIER);
873 I915_WRITE(IMR, dev_priv->saveIMR);
877 if (drm_core_check_feature(dev, DRIVER_MODESET))
878 intel_init_clock_gating(dev);
880 if (IS_IRONLAKE_M(dev)) {
881 ironlake_enable_drps(dev);
882 intel_init_emon(dev);
885 if (INTEL_INFO(dev)->gen >= 6) {
886 gen6_enable_rps(dev_priv);
887 gen6_update_ring_freq(dev_priv);
892 /* Cache mode state */
893 I915_WRITE(CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
895 /* Memory arbitration state */
896 I915_WRITE(MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
898 for (i = 0; i < 16; i++) {
899 I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]);
900 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i]);
902 for (i = 0; i < 3; i++)
903 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
905 intel_iic_reset(dev);