2 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
3 * Copyright (c) 1992 Terrence R. Lambert.
4 * Copyright (c) 2003 Peter Wemm.
5 * Copyright (c) 2008 The DragonFly Project.
8 * This code is derived from software contributed to Berkeley by
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the University of
22 * California, Berkeley and its contributors.
23 * 4. Neither the name of the University nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
40 * $FreeBSD: src/sys/i386/i386/machdep.c,v 1.385.2.30 2003/05/31 08:48:05 alc Exp $
43 //#include "use_npx.h"
45 #include "opt_compat.h"
48 #include "opt_directio.h"
51 #include "opt_msgbuf.h"
54 #include <sys/param.h>
55 #include <sys/systm.h>
56 #include <sys/sysproto.h>
57 #include <sys/signalvar.h>
58 #include <sys/kernel.h>
59 #include <sys/linker.h>
60 #include <sys/malloc.h>
64 #include <sys/reboot.h>
66 #include <sys/msgbuf.h>
67 #include <sys/sysent.h>
68 #include <sys/sysctl.h>
69 #include <sys/vmmeter.h>
71 #include <sys/usched.h>
75 #include <vm/vm_param.h>
77 #include <vm/vm_kern.h>
78 #include <vm/vm_object.h>
79 #include <vm/vm_page.h>
80 #include <vm/vm_map.h>
81 #include <vm/vm_pager.h>
82 #include <vm/vm_extern.h>
84 #include <sys/thread2.h>
85 #include <sys/mplock2.h>
86 #include <sys/mutex2.h>
94 #include <machine/cpu.h>
95 #include <machine/clock.h>
96 #include <machine/specialreg.h>
98 #include <machine/bootinfo.h>
100 #include <machine/md_var.h>
101 #include <machine/metadata.h>
102 #include <machine/pc/bios.h>
103 #include <machine/pcb_ext.h> /* pcb.h included via sys/user.h */
104 #include <machine/globaldata.h> /* CPU_prvspace */
105 #include <machine/smp.h>
107 #include <machine/perfmon.h>
109 #include <machine/cputypes.h>
110 #include <machine/intr_machdep.h>
113 #include <bus/isa/isa_device.h>
115 #include <machine_base/isa/isa_intr.h>
116 #include <bus/isa/rtc.h>
117 #include <sys/random.h>
118 #include <sys/ptrace.h>
119 #include <machine/sigframe.h>
121 #include <sys/machintr.h>
122 #include <machine_base/icu/icu_abi.h>
123 #include <machine_base/icu/elcr_var.h>
124 #include <machine_base/apic/lapic.h>
125 #include <machine_base/apic/ioapic.h>
126 #include <machine_base/apic/ioapic_abi.h>
127 #include <machine/mptable.h>
129 #define PHYSMAP_ENTRIES 10
131 extern u_int64_t hammer_time(u_int64_t, u_int64_t);
133 extern void printcpuinfo(void); /* XXX header file */
134 extern void identify_cpu(void);
136 extern void finishidentcpu(void);
138 extern void panicifcpuunsupported(void);
140 static void cpu_startup(void *);
141 static void pic_finish(void *);
142 static void cpu_finish(void *);
144 #ifndef CPU_DISABLE_SSE
145 static void set_fpregs_xmm(struct save87 *, struct savexmm *);
146 static void fill_fpregs_xmm(struct savexmm *, struct save87 *);
147 #endif /* CPU_DISABLE_SSE */
149 extern void ffs_rawread_setup(void);
150 #endif /* DIRECTIO */
151 static void init_locks(void);
153 SYSINIT(cpu, SI_BOOT2_START_CPU, SI_ORDER_FIRST, cpu_startup, NULL)
154 SYSINIT(pic_finish, SI_BOOT2_FINISH_PIC, SI_ORDER_FIRST, pic_finish, NULL)
155 SYSINIT(cpu_finish, SI_BOOT2_FINISH_CPU, SI_ORDER_FIRST, cpu_finish, NULL)
158 extern vm_offset_t ksym_start, ksym_end;
161 struct privatespace CPU_prvspace[MAXCPU] __aligned(4096); /* XXX */
163 int _udatasel, _ucodesel, _ucode32sel;
165 int64_t tsc_offsets[MAXCPU];
168 #if defined(SWTCH_OPTIM_STATS)
169 extern int swtch_optim_stats;
170 SYSCTL_INT(_debug, OID_AUTO, swtch_optim_stats,
171 CTLFLAG_RD, &swtch_optim_stats, 0, "");
172 SYSCTL_INT(_debug, OID_AUTO, tlb_flush_count,
173 CTLFLAG_RD, &tlb_flush_count, 0, "");
175 SYSCTL_INT(_hw, OID_AUTO, cpu_mwait_halt,
176 CTLFLAG_RW, &cpu_mwait_halt, 0, "");
180 u_long ebda_addr = 0;
182 int imcr_present = 0;
184 int naps = 0; /* # of Applications processors */
187 struct mtx dt_lock; /* lock for GDT and LDT */
190 sysctl_hw_physmem(SYSCTL_HANDLER_ARGS)
192 u_long pmem = ctob(physmem);
194 int error = sysctl_handle_long(oidp, &pmem, 0, req);
198 SYSCTL_PROC(_hw, HW_PHYSMEM, physmem, CTLTYPE_ULONG|CTLFLAG_RD,
199 0, 0, sysctl_hw_physmem, "LU", "Total system memory in bytes (number of pages * page size)");
202 sysctl_hw_usermem(SYSCTL_HANDLER_ARGS)
204 int error = sysctl_handle_int(oidp, 0,
205 ctob(physmem - vmstats.v_wire_count), req);
209 SYSCTL_PROC(_hw, HW_USERMEM, usermem, CTLTYPE_INT|CTLFLAG_RD,
210 0, 0, sysctl_hw_usermem, "IU", "");
213 sysctl_hw_availpages(SYSCTL_HANDLER_ARGS)
215 int error = sysctl_handle_int(oidp, 0,
216 x86_64_btop(avail_end - avail_start), req);
220 SYSCTL_PROC(_hw, OID_AUTO, availpages, CTLTYPE_INT|CTLFLAG_RD,
221 0, 0, sysctl_hw_availpages, "I", "");
227 * The number of PHYSMAP entries must be one less than the number of
228 * PHYSSEG entries because the PHYSMAP entry that spans the largest
229 * physical address that is accessible by ISA DMA is split into two
232 #define PHYSMAP_SIZE (2 * (VM_PHYSSEG_MAX - 1))
234 vm_paddr_t phys_avail[PHYSMAP_SIZE + 2];
235 vm_paddr_t dump_avail[PHYSMAP_SIZE + 2];
237 /* must be 2 less so 0 0 can signal end of chunks */
238 #define PHYS_AVAIL_ARRAY_END (NELEM(phys_avail) - 2)
239 #define DUMP_AVAIL_ARRAY_END (NELEM(dump_avail) - 2)
241 static vm_offset_t buffer_sva, buffer_eva;
242 vm_offset_t clean_sva, clean_eva;
243 static vm_offset_t pager_sva, pager_eva;
244 static struct trapframe proc0_tf;
247 cpu_startup(void *dummy)
251 vm_offset_t firstaddr;
254 * Good {morning,afternoon,evening,night}.
256 kprintf("%s", version);
259 panicifcpuunsupported();
263 kprintf("real memory = %ju (%ju MB)\n",
265 (intmax_t)Realmem / 1024 / 1024);
267 * Display any holes after the first chunk of extended memory.
272 kprintf("Physical memory chunk(s):\n");
273 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
274 vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx];
276 kprintf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n",
277 (intmax_t)phys_avail[indx],
278 (intmax_t)phys_avail[indx + 1] - 1,
280 (intmax_t)(size1 / PAGE_SIZE));
285 * Allocate space for system data structures.
286 * The first available kernel virtual address is in "v".
287 * As pages of kernel virtual memory are allocated, "v" is incremented.
288 * As pages of memory are allocated and cleared,
289 * "firstaddr" is incremented.
290 * An index into the kernel page table corresponding to the
291 * virtual memory address maintained in "v" is kept in "mapaddr".
295 * Make two passes. The first pass calculates how much memory is
296 * needed and allocates it. The second pass assigns virtual
297 * addresses to the various data structures.
301 v = (caddr_t)firstaddr;
303 #define valloc(name, type, num) \
304 (name) = (type *)v; v = (caddr_t)((name)+(num))
305 #define valloclim(name, type, num, lim) \
306 (name) = (type *)v; v = (caddr_t)((lim) = ((name)+(num)))
309 * The nominal buffer size (and minimum KVA allocation) is BKVASIZE.
310 * For the first 64MB of ram nominally allocate sufficient buffers to
311 * cover 1/4 of our ram. Beyond the first 64MB allocate additional
312 * buffers to cover 1/20 of our ram over 64MB. When auto-sizing
313 * the buffer cache we limit the eventual kva reservation to
316 * factor represents the 1/4 x ram conversion.
319 long factor = 4 * BKVASIZE / 1024;
320 long kbytes = physmem * (PAGE_SIZE / 1024);
324 nbuf += min((kbytes - 4096) / factor, 65536 / factor);
326 nbuf += (kbytes - 65536) * 2 / (factor * 5);
327 if (maxbcache && nbuf > maxbcache / BKVASIZE)
328 nbuf = maxbcache / BKVASIZE;
332 * Do not allow the buffer_map to be more then 1/2 the size of the
335 if (nbuf > (virtual_end - virtual_start +
336 virtual2_end - virtual2_start) / (BKVASIZE * 2)) {
337 nbuf = (virtual_end - virtual_start +
338 virtual2_end - virtual2_start) / (BKVASIZE * 2);
339 kprintf("Warning: nbufs capped at %ld due to kvm\n", nbuf);
343 * Do not allow the buffer_map to use more than 50% of available
344 * physical-equivalent memory. Since the VM pages which back
345 * individual buffers are typically wired, having too many bufs
346 * can prevent the system from paging properly.
348 if (nbuf > physmem * PAGE_SIZE / (BKVASIZE * 2)) {
349 nbuf = physmem * PAGE_SIZE / (BKVASIZE * 2);
350 kprintf("Warning: nbufs capped at %ld due to physmem\n", nbuf);
354 * Do not allow the sizeof(struct buf) * nbuf to exceed half of
355 * the valloc space which is just the virtual_end - virtual_start
356 * section. We use valloc() to allocate the buf header array.
358 if (nbuf > (virtual_end - virtual_start) / sizeof(struct buf) / 2) {
359 nbuf = (virtual_end - virtual_start) /
360 sizeof(struct buf) / 2;
361 kprintf("Warning: nbufs capped at %ld due to valloc "
362 "considerations", nbuf);
365 nswbuf = lmax(lmin(nbuf / 4, 256), 16);
367 if (nswbuf < NSWBUF_MIN)
374 valloc(swbuf, struct buf, nswbuf);
375 valloc(buf, struct buf, nbuf);
378 * End of first pass, size has been calculated so allocate memory
380 if (firstaddr == 0) {
381 size = (vm_size_t)(v - firstaddr);
382 firstaddr = kmem_alloc(&kernel_map, round_page(size));
384 panic("startup: no room for tables");
389 * End of second pass, addresses have been assigned
391 * nbuf is an int, make sure we don't overflow the field.
393 * On 64-bit systems fragmentation can create serious performance
394 * loss due to the large number of buffers the system is likely
395 * going to maintain. The easiest solution is to create a KVA
396 * section that is twice as big as the nominal buffer cache size,
397 * hence the multiplication by 2 below.
399 if ((vm_size_t)(v - firstaddr) != size)
400 panic("startup: table size inconsistency");
402 kmem_suballoc(&kernel_map, &clean_map, &clean_sva, &clean_eva,
403 ((vm_offset_t)nbuf * BKVASIZE * 2) +
404 (nswbuf * MAXPHYS) + pager_map_size);
405 kmem_suballoc(&clean_map, &buffer_map, &buffer_sva, &buffer_eva,
406 ((vm_offset_t)nbuf * BKVASIZE * 2));
407 buffer_map.system_map = 1;
408 kmem_suballoc(&clean_map, &pager_map, &pager_sva, &pager_eva,
409 ((vm_offset_t)nswbuf * MAXPHYS) + pager_map_size);
410 pager_map.system_map = 1;
412 #if defined(USERCONFIG)
414 cninit(); /* the preferred console may have changed */
417 kprintf("avail memory = %ju (%ju MB)\n",
418 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages),
419 (uintmax_t)ptoa(vmstats.v_free_count + vmstats.v_dma_pages) /
423 * Set up buffers, so they can be used to read disk labels.
426 vm_pager_bufferinit();
430 cpu_finish(void *dummy __unused)
436 pic_finish(void *dummy __unused)
438 /* Log ELCR information */
441 /* Log MPTABLE information */
442 mptable_pci_int_dump();
445 MachIntrABI.finalize();
449 * Send an interrupt to process.
451 * Stack is set up to allow sigcode stored
452 * at top to call routine, followed by kcall
453 * to sigreturn routine below. After sigreturn
454 * resets the signal mask, the stack, and the
455 * frame pointer, it returns to the user
459 sendsig(sig_t catcher, int sig, sigset_t *mask, u_long code)
461 struct lwp *lp = curthread->td_lwp;
462 struct proc *p = lp->lwp_proc;
463 struct trapframe *regs;
464 struct sigacts *psp = p->p_sigacts;
465 struct sigframe sf, *sfp;
469 regs = lp->lwp_md.md_regs;
470 oonstack = (lp->lwp_sigstk.ss_flags & SS_ONSTACK) ? 1 : 0;
472 /* Save user context */
473 bzero(&sf, sizeof(struct sigframe));
474 sf.sf_uc.uc_sigmask = *mask;
475 sf.sf_uc.uc_stack = lp->lwp_sigstk;
476 sf.sf_uc.uc_mcontext.mc_onstack = oonstack;
477 KKASSERT(__offsetof(struct trapframe, tf_rdi) == 0);
478 bcopy(regs, &sf.sf_uc.uc_mcontext.mc_rdi, sizeof(struct trapframe));
480 /* Make the size of the saved context visible to userland */
481 sf.sf_uc.uc_mcontext.mc_len = sizeof(sf.sf_uc.uc_mcontext);
483 /* Allocate and validate space for the signal handler context. */
484 if ((lp->lwp_flags & LWP_ALTSTACK) != 0 && !oonstack &&
485 SIGISMEMBER(psp->ps_sigonstack, sig)) {
486 sp = (char *)(lp->lwp_sigstk.ss_sp + lp->lwp_sigstk.ss_size -
487 sizeof(struct sigframe));
488 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
490 /* We take red zone into account */
491 sp = (char *)regs->tf_rsp - sizeof(struct sigframe) - 128;
495 * XXX AVX needs 64-byte alignment but sigframe has other fields and
496 * the embedded ucontext is not at the front, so aligning this won't
497 * help us. Fortunately we bcopy in/out of the sigframe, so the
500 * The problem though is if userland winds up trying to use the
503 sfp = (struct sigframe *)((intptr_t)sp & ~(intptr_t)0xF);
505 /* Translate the signal is appropriate */
506 if (p->p_sysent->sv_sigtbl) {
507 if (sig <= p->p_sysent->sv_sigsize)
508 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
512 * Build the argument list for the signal handler.
514 * Arguments are in registers (%rdi, %rsi, %rdx, %rcx)
516 regs->tf_rdi = sig; /* argument 1 */
517 regs->tf_rdx = (register_t)&sfp->sf_uc; /* argument 3 */
519 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
521 * Signal handler installed with SA_SIGINFO.
523 * action(signo, siginfo, ucontext)
525 regs->tf_rsi = (register_t)&sfp->sf_si; /* argument 2 */
526 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
527 sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher;
529 /* fill siginfo structure */
530 sf.sf_si.si_signo = sig;
531 sf.sf_si.si_code = code;
532 sf.sf_si.si_addr = (void *)regs->tf_addr;
535 * Old FreeBSD-style arguments.
537 * handler (signo, code, [uc], addr)
539 regs->tf_rsi = (register_t)code; /* argument 2 */
540 regs->tf_rcx = (register_t)regs->tf_addr; /* argument 4 */
541 sf.sf_ahu.sf_handler = catcher;
545 * If we're a vm86 process, we want to save the segment registers.
546 * We also change eflags to be our emulated eflags, not the actual
550 if (regs->tf_eflags & PSL_VM) {
551 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
552 struct vm86_kernel *vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
554 sf.sf_uc.uc_mcontext.mc_gs = tf->tf_vm86_gs;
555 sf.sf_uc.uc_mcontext.mc_fs = tf->tf_vm86_fs;
556 sf.sf_uc.uc_mcontext.mc_es = tf->tf_vm86_es;
557 sf.sf_uc.uc_mcontext.mc_ds = tf->tf_vm86_ds;
559 if (vm86->vm86_has_vme == 0)
560 sf.sf_uc.uc_mcontext.mc_eflags =
561 (tf->tf_eflags & ~(PSL_VIF | PSL_VIP)) |
562 (vm86->vm86_eflags & (PSL_VIF | PSL_VIP));
565 * Clear PSL_NT to inhibit T_TSSFLT faults on return from
566 * syscalls made by the signal handler. This just avoids
567 * wasting time for our lazy fixup of such faults. PSL_NT
568 * does nothing in vm86 mode, but vm86 programs can set it
569 * almost legitimately in probes for old cpu types.
571 tf->tf_eflags &= ~(PSL_VM | PSL_NT | PSL_VIF | PSL_VIP);
576 * Save the FPU state and reinit the FP unit
578 npxpush(&sf.sf_uc.uc_mcontext);
581 * Copy the sigframe out to the user's stack.
583 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) {
585 * Something is wrong with the stack pointer.
586 * ...Kill the process.
591 regs->tf_rsp = (register_t)sfp;
592 regs->tf_rip = PS_STRINGS - *(p->p_sysent->sv_szsigcode);
595 * i386 abi specifies that the direction flag must be cleared
598 regs->tf_rflags &= ~(PSL_T|PSL_D);
601 * 64 bit mode has a code and stack selector but
602 * no data or extra selector. %fs and %gs are not
605 regs->tf_cs = _ucodesel;
606 regs->tf_ss = _udatasel;
611 * Sanitize the trapframe for a virtual kernel passing control to a custom
612 * VM context. Remove any items that would otherwise create a privilage
615 * XXX at the moment we allow userland to set the resume flag. Is this a
619 cpu_sanitize_frame(struct trapframe *frame)
621 frame->tf_cs = _ucodesel;
622 frame->tf_ss = _udatasel;
623 /* XXX VM (8086) mode not supported? */
624 frame->tf_rflags &= (PSL_RF | PSL_USERCHANGE | PSL_VM_UNSUPP);
625 frame->tf_rflags |= PSL_RESERVED_DEFAULT | PSL_I;
631 * Sanitize the tls so loading the descriptor does not blow up
632 * on us. For x86_64 we don't have to do anything.
635 cpu_sanitize_tls(struct savetls *tls)
641 * sigreturn(ucontext_t *sigcntxp)
643 * System call to cleanup state after a signal
644 * has been taken. Reset signal mask and
645 * stack state from context left by sendsig (above).
646 * Return to previous pc and psl as specified by
647 * context left by sendsig. Check carefully to
648 * make sure that the user has not modified the
649 * state to gain improper privileges.
653 #define EFL_SECURE(ef, oef) ((((ef) ^ (oef)) & ~PSL_USERCHANGE) == 0)
654 #define CS_SECURE(cs) (ISPL(cs) == SEL_UPL)
657 sys_sigreturn(struct sigreturn_args *uap)
659 struct lwp *lp = curthread->td_lwp;
660 struct trapframe *regs;
668 * We have to copy the information into kernel space so userland
669 * can't modify it while we are sniffing it.
671 regs = lp->lwp_md.md_regs;
672 error = copyin(uap->sigcntxp, &uc, sizeof(uc));
676 rflags = ucp->uc_mcontext.mc_rflags;
678 /* VM (8086) mode not supported */
679 rflags &= ~PSL_VM_UNSUPP;
682 if (eflags & PSL_VM) {
683 struct trapframe_vm86 *tf = (struct trapframe_vm86 *)regs;
684 struct vm86_kernel *vm86;
687 * if pcb_ext == 0 or vm86_inited == 0, the user hasn't
688 * set up the vm86 area, and we can't enter vm86 mode.
690 if (lp->lwp_thread->td_pcb->pcb_ext == 0)
692 vm86 = &lp->lwp_thread->td_pcb->pcb_ext->ext_vm86;
693 if (vm86->vm86_inited == 0)
696 /* go back to user mode if both flags are set */
697 if ((eflags & PSL_VIP) && (eflags & PSL_VIF))
698 trapsignal(lp, SIGBUS, 0);
700 if (vm86->vm86_has_vme) {
701 eflags = (tf->tf_eflags & ~VME_USERCHANGE) |
702 (eflags & VME_USERCHANGE) | PSL_VM;
704 vm86->vm86_eflags = eflags; /* save VIF, VIP */
705 eflags = (tf->tf_eflags & ~VM_USERCHANGE) |
706 (eflags & VM_USERCHANGE) | PSL_VM;
708 bcopy(&ucp->uc_mcontext.mc_gs, tf, sizeof(struct trapframe));
709 tf->tf_eflags = eflags;
710 tf->tf_vm86_ds = tf->tf_ds;
711 tf->tf_vm86_es = tf->tf_es;
712 tf->tf_vm86_fs = tf->tf_fs;
713 tf->tf_vm86_gs = tf->tf_gs;
714 tf->tf_ds = _udatasel;
715 tf->tf_es = _udatasel;
716 tf->tf_fs = _udatasel;
717 tf->tf_gs = _udatasel;
722 * Don't allow users to change privileged or reserved flags.
725 * XXX do allow users to change the privileged flag PSL_RF.
726 * The cpu sets PSL_RF in tf_eflags for faults. Debuggers
727 * should sometimes set it there too. tf_eflags is kept in
728 * the signal context during signal handling and there is no
729 * other place to remember it, so the PSL_RF bit may be
730 * corrupted by the signal handler without us knowing.
731 * Corruption of the PSL_RF bit at worst causes one more or
732 * one less debugger trap, so allowing it is fairly harmless.
734 if (!EFL_SECURE(rflags & ~PSL_RF, regs->tf_rflags & ~PSL_RF)) {
735 kprintf("sigreturn: rflags = 0x%lx\n", (long)rflags);
740 * Don't allow users to load a valid privileged %cs. Let the
741 * hardware check for invalid selectors, excess privilege in
742 * other selectors, invalid %eip's and invalid %esp's.
744 cs = ucp->uc_mcontext.mc_cs;
745 if (!CS_SECURE(cs)) {
746 kprintf("sigreturn: cs = 0x%x\n", cs);
747 trapsignal(lp, SIGBUS, T_PROTFLT);
750 bcopy(&ucp->uc_mcontext.mc_rdi, regs, sizeof(struct trapframe));
754 * Restore the FPU state from the frame
757 npxpop(&ucp->uc_mcontext);
759 if (ucp->uc_mcontext.mc_onstack & 1)
760 lp->lwp_sigstk.ss_flags |= SS_ONSTACK;
762 lp->lwp_sigstk.ss_flags &= ~SS_ONSTACK;
764 lp->lwp_sigmask = ucp->uc_sigmask;
765 SIG_CANTMASK(lp->lwp_sigmask);
772 * Machine dependent boot() routine
774 * I haven't seen anything to put here yet
775 * Possibly some stuff might be grafted back here from boot()
783 * Shutdown the CPU as much as possible
789 __asm__ __volatile("hlt");
793 * cpu_idle() represents the idle LWKT. You cannot return from this function
794 * (unless you want to blow things up!). Instead we look for runnable threads
795 * and loop or halt as appropriate. Giant is not held on entry to the thread.
797 * The main loop is entered with a critical section held, we must release
798 * the critical section before doing anything else. lwkt_switch() will
799 * check for pending interrupts due to entering and exiting its own
802 * NOTE: On an SMP system we rely on a scheduler IPI to wake a HLTed cpu up.
803 * However, there are cases where the idlethread will be entered with
804 * the possibility that no IPI will occur and in such cases
805 * lwkt_switch() sets TDF_IDLE_NOHLT.
807 * NOTE: cpu_idle_hlt again defaults to 2 (use ACPI sleep states). Set to
808 * 1 to just use hlt and for debugging purposes.
810 * NOTE: cpu_idle_repeat determines how many entries into the idle thread
811 * must occur before it starts using ACPI halt.
813 static int cpu_idle_hlt = 2;
814 static int cpu_idle_hltcnt;
815 static int cpu_idle_spincnt;
816 static u_int cpu_idle_repeat = 750;
817 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hlt, CTLFLAG_RW,
818 &cpu_idle_hlt, 0, "Idle loop HLT enable");
819 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_hltcnt, CTLFLAG_RW,
820 &cpu_idle_hltcnt, 0, "Idle loop entry halts");
821 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_spincnt, CTLFLAG_RW,
822 &cpu_idle_spincnt, 0, "Idle loop entry spins");
823 SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_repeat, CTLFLAG_RW,
824 &cpu_idle_repeat, 0, "Idle entries before acpi hlt");
827 cpu_idle_default_hook(void)
830 * We must guarentee that hlt is exactly the instruction
833 __asm __volatile("sti; hlt");
836 /* Other subsystems (e.g., ACPI) can hook this later. */
837 void (*cpu_idle_hook)(void) = cpu_idle_default_hook;
842 globaldata_t gd = mycpu;
843 struct thread *td __debugvar = gd->gd_curthread;
848 KKASSERT(td->td_critcount == 0);
851 * See if there are any LWKTs ready to go.
856 * When halting inside a cli we must check for reqflags
857 * races, particularly [re]schedule requests. Running
858 * splz() does the job.
861 * 0 Never halt, just spin
863 * 1 Always use HLT (or MONITOR/MWAIT if avail).
864 * This typically eats more power than the
867 * 2 Use HLT/MONITOR/MWAIT up to a point and then
868 * use the ACPI halt (default). This is a hybrid
869 * approach. See machdep.cpu_idle_repeat.
871 * 3 Always use the ACPI halt. This typically
872 * eats the least amount of power but the cpu
873 * will be slow waking up. Slows down e.g.
874 * compiles and other pipe/event oriented stuff.
876 * NOTE: Interrupts are enabled and we are not in a critical
879 * NOTE: Preemptions do not reset gd_idle_repeat. Also we
880 * don't bother capping gd_idle_repeat, it is ok if
883 ++gd->gd_idle_repeat;
884 reqflags = gd->gd_reqflags;
885 quick = (cpu_idle_hlt == 1) ||
887 gd->gd_idle_repeat < cpu_idle_repeat);
889 if (quick && (cpu_mi_feature & CPU_MI_MONITOR) &&
890 (reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
892 cpu_mmw_pause_int(&gd->gd_reqflags, reqflags,
895 } else if (cpu_idle_hlt) {
896 __asm __volatile("cli");
898 if ((gd->gd_reqflags & RQF_IDLECHECK_WK_MASK) == 0) {
900 cpu_idle_default_hook();
904 __asm __volatile("sti");
908 __asm __volatile("sti");
915 * This routine is called if a spinlock has been held through the
916 * exponential backoff period and is seriously contested. On a real cpu
920 cpu_spinlock_contested(void)
926 * Clear registers on exec
929 exec_setregs(u_long entry, u_long stack, u_long ps_strings)
931 struct thread *td = curthread;
932 struct lwp *lp = td->td_lwp;
933 struct pcb *pcb = td->td_pcb;
934 struct trapframe *regs = lp->lwp_md.md_regs;
936 /* was i386_user_cleanup() in NetBSD */
940 bzero((char *)regs, sizeof(struct trapframe));
941 regs->tf_rip = entry;
942 regs->tf_rsp = ((stack - 8) & ~0xFul) + 8; /* align the stack */
943 regs->tf_rdi = stack; /* argv */
944 regs->tf_rflags = PSL_USER | (regs->tf_rflags & PSL_T);
945 regs->tf_ss = _udatasel;
946 regs->tf_cs = _ucodesel;
947 regs->tf_rbx = ps_strings;
950 * Reset the hardware debug registers if they were in use.
951 * They won't have any meaning for the newly exec'd process.
953 if (pcb->pcb_flags & PCB_DBREGS) {
959 pcb->pcb_dr7 = 0; /* JG set bit 10? */
960 if (pcb == td->td_pcb) {
962 * Clear the debug registers on the running
963 * CPU, otherwise they will end up affecting
964 * the next process we switch to.
968 pcb->pcb_flags &= ~PCB_DBREGS;
972 * Initialize the math emulator (if any) for the current process.
973 * Actually, just clear the bit that says that the emulator has
974 * been initialized. Initialization is delayed until the process
975 * traps to the emulator (if it is done at all) mainly because
976 * emulators don't provide an entry point for initialization.
978 pcb->pcb_flags &= ~FP_SOFTFP;
981 * NOTE: do not set CR0_TS here. npxinit() must do it after clearing
982 * gd_npxthread. Otherwise a preemptive interrupt thread
983 * may panic in npxdna().
986 load_cr0(rcr0() | CR0_MP);
989 * NOTE: The MSR values must be correct so we can return to
990 * userland. gd_user_fs/gs must be correct so the switch
991 * code knows what the current MSR values are.
993 pcb->pcb_fsbase = 0; /* Values loaded from PCB on switch */
995 mdcpu->gd_user_fs = 0; /* Cache of current MSR values */
996 mdcpu->gd_user_gs = 0;
997 wrmsr(MSR_FSBASE, 0); /* Set MSR values for return to userland */
998 wrmsr(MSR_KGSBASE, 0);
1000 /* Initialize the npx (if any) for the current process. */
1001 npxinit(__INITIAL_FPUCW__);
1004 pcb->pcb_ds = _udatasel;
1005 pcb->pcb_es = _udatasel;
1006 pcb->pcb_fs = _udatasel;
1007 pcb->pcb_gs = _udatasel;
1016 cr0 |= CR0_NE; /* Done by npxinit() */
1017 cr0 |= CR0_MP | CR0_TS; /* Done at every execve() too. */
1018 cr0 |= CR0_WP | CR0_AM;
1024 sysctl_machdep_adjkerntz(SYSCTL_HANDLER_ARGS)
1027 error = sysctl_handle_int(oidp, oidp->oid_arg1, oidp->oid_arg2,
1029 if (!error && req->newptr)
1034 SYSCTL_PROC(_machdep, CPU_ADJKERNTZ, adjkerntz, CTLTYPE_INT|CTLFLAG_RW,
1035 &adjkerntz, 0, sysctl_machdep_adjkerntz, "I", "");
1037 SYSCTL_INT(_machdep, CPU_DISRTCSET, disable_rtc_set,
1038 CTLFLAG_RW, &disable_rtc_set, 0, "");
1041 SYSCTL_STRUCT(_machdep, CPU_BOOTINFO, bootinfo,
1042 CTLFLAG_RD, &bootinfo, bootinfo, "");
1045 SYSCTL_INT(_machdep, CPU_WALLCLOCK, wall_cmos_clock,
1046 CTLFLAG_RW, &wall_cmos_clock, 0, "");
1048 extern u_long bootdev; /* not a cdev_t - encoding is different */
1049 SYSCTL_ULONG(_machdep, OID_AUTO, guessed_bootdev,
1050 CTLFLAG_RD, &bootdev, 0, "Boot device (not in cdev_t format)");
1053 * Initialize 386 and configure to run kernel
1057 * Initialize segments & interrupt table
1061 struct user_segment_descriptor gdt[NGDT * MAXCPU]; /* global descriptor table */
1062 struct gate_descriptor idt_arr[MAXCPU][NIDT];
1064 union descriptor ldt[NLDT]; /* local descriptor table */
1067 /* table descriptors - used to load tables by cpu */
1068 struct region_descriptor r_gdt;
1069 struct region_descriptor r_idt_arr[MAXCPU];
1071 /* JG proc0paddr is a virtual address */
1074 char proc0paddr_buff[LWKT_THREAD_STACK];
1077 /* software prototypes -- in more palatable form */
1078 struct soft_segment_descriptor gdt_segs[] = {
1079 /* GNULL_SEL 0 Null Descriptor */
1080 { 0x0, /* segment base address */
1082 0, /* segment type */
1083 0, /* segment descriptor priority level */
1084 0, /* segment descriptor present */
1086 0, /* default 32 vs 16 bit size */
1087 0 /* limit granularity (byte/page units)*/ },
1088 /* GCODE_SEL 1 Code Descriptor for kernel */
1089 { 0x0, /* segment base address */
1090 0xfffff, /* length - all address space */
1091 SDT_MEMERA, /* segment type */
1092 SEL_KPL, /* segment descriptor priority level */
1093 1, /* segment descriptor present */
1095 0, /* default 32 vs 16 bit size */
1096 1 /* limit granularity (byte/page units)*/ },
1097 /* GDATA_SEL 2 Data Descriptor for kernel */
1098 { 0x0, /* segment base address */
1099 0xfffff, /* length - all address space */
1100 SDT_MEMRWA, /* segment type */
1101 SEL_KPL, /* segment descriptor priority level */
1102 1, /* segment descriptor present */
1104 0, /* default 32 vs 16 bit size */
1105 1 /* limit granularity (byte/page units)*/ },
1106 /* GUCODE32_SEL 3 32 bit Code Descriptor for user */
1107 { 0x0, /* segment base address */
1108 0xfffff, /* length - all address space */
1109 SDT_MEMERA, /* segment type */
1110 SEL_UPL, /* segment descriptor priority level */
1111 1, /* segment descriptor present */
1113 1, /* default 32 vs 16 bit size */
1114 1 /* limit granularity (byte/page units)*/ },
1115 /* GUDATA_SEL 4 32/64 bit Data Descriptor for user */
1116 { 0x0, /* segment base address */
1117 0xfffff, /* length - all address space */
1118 SDT_MEMRWA, /* segment type */
1119 SEL_UPL, /* segment descriptor priority level */
1120 1, /* segment descriptor present */
1122 1, /* default 32 vs 16 bit size */
1123 1 /* limit granularity (byte/page units)*/ },
1124 /* GUCODE_SEL 5 64 bit Code Descriptor for user */
1125 { 0x0, /* segment base address */
1126 0xfffff, /* length - all address space */
1127 SDT_MEMERA, /* segment type */
1128 SEL_UPL, /* segment descriptor priority level */
1129 1, /* segment descriptor present */
1131 0, /* default 32 vs 16 bit size */
1132 1 /* limit granularity (byte/page units)*/ },
1133 /* GPROC0_SEL 6 Proc 0 Tss Descriptor */
1135 0x0, /* segment base address */
1136 sizeof(struct x86_64tss)-1,/* length - all address space */
1137 SDT_SYSTSS, /* segment type */
1138 SEL_KPL, /* segment descriptor priority level */
1139 1, /* segment descriptor present */
1141 0, /* unused - default 32 vs 16 bit size */
1142 0 /* limit granularity (byte/page units)*/ },
1143 /* Actually, the TSS is a system descriptor which is double size */
1144 { 0x0, /* segment base address */
1146 0, /* segment type */
1147 0, /* segment descriptor priority level */
1148 0, /* segment descriptor present */
1150 0, /* default 32 vs 16 bit size */
1151 0 /* limit granularity (byte/page units)*/ },
1152 /* GUGS32_SEL 8 32 bit GS Descriptor for user */
1153 { 0x0, /* segment base address */
1154 0xfffff, /* length - all address space */
1155 SDT_MEMRWA, /* segment type */
1156 SEL_UPL, /* segment descriptor priority level */
1157 1, /* segment descriptor present */
1159 1, /* default 32 vs 16 bit size */
1160 1 /* limit granularity (byte/page units)*/ },
1164 setidt_global(int idx, inthand_t *func, int typ, int dpl, int ist)
1168 for (cpu = 0; cpu < MAXCPU; ++cpu) {
1169 struct gate_descriptor *ip = &idt_arr[cpu][idx];
1171 ip->gd_looffset = (uintptr_t)func;
1172 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1178 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1183 setidt(int idx, inthand_t *func, int typ, int dpl, int ist, int cpu)
1185 struct gate_descriptor *ip;
1187 KASSERT(cpu >= 0 && cpu < ncpus, ("invalid cpu %d", cpu));
1189 ip = &idt_arr[cpu][idx];
1190 ip->gd_looffset = (uintptr_t)func;
1191 ip->gd_selector = GSEL(GCODE_SEL, SEL_KPL);
1197 ip->gd_hioffset = ((uintptr_t)func)>>16 ;
1200 #define IDTVEC(name) __CONCAT(X,name)
1203 IDTVEC(div), IDTVEC(dbg), IDTVEC(nmi), IDTVEC(bpt), IDTVEC(ofl),
1204 IDTVEC(bnd), IDTVEC(ill), IDTVEC(dna), IDTVEC(fpusegm),
1205 IDTVEC(tss), IDTVEC(missing), IDTVEC(stk), IDTVEC(prot),
1206 IDTVEC(page), IDTVEC(mchk), IDTVEC(rsvd), IDTVEC(fpu), IDTVEC(align),
1207 IDTVEC(xmm), IDTVEC(dblfault),
1208 IDTVEC(fast_syscall), IDTVEC(fast_syscall32);
1210 #ifdef DEBUG_INTERRUPTS
1211 extern inthand_t *Xrsvdary[256];
1215 sdtossd(struct user_segment_descriptor *sd, struct soft_segment_descriptor *ssd)
1217 ssd->ssd_base = (sd->sd_hibase << 24) | sd->sd_lobase;
1218 ssd->ssd_limit = (sd->sd_hilimit << 16) | sd->sd_lolimit;
1219 ssd->ssd_type = sd->sd_type;
1220 ssd->ssd_dpl = sd->sd_dpl;
1221 ssd->ssd_p = sd->sd_p;
1222 ssd->ssd_def32 = sd->sd_def32;
1223 ssd->ssd_gran = sd->sd_gran;
1227 ssdtosd(struct soft_segment_descriptor *ssd, struct user_segment_descriptor *sd)
1230 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1231 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xff;
1232 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1233 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1234 sd->sd_type = ssd->ssd_type;
1235 sd->sd_dpl = ssd->ssd_dpl;
1236 sd->sd_p = ssd->ssd_p;
1237 sd->sd_long = ssd->ssd_long;
1238 sd->sd_def32 = ssd->ssd_def32;
1239 sd->sd_gran = ssd->ssd_gran;
1243 ssdtosyssd(struct soft_segment_descriptor *ssd,
1244 struct system_segment_descriptor *sd)
1247 sd->sd_lobase = (ssd->ssd_base) & 0xffffff;
1248 sd->sd_hibase = (ssd->ssd_base >> 24) & 0xfffffffffful;
1249 sd->sd_lolimit = (ssd->ssd_limit) & 0xffff;
1250 sd->sd_hilimit = (ssd->ssd_limit >> 16) & 0xf;
1251 sd->sd_type = ssd->ssd_type;
1252 sd->sd_dpl = ssd->ssd_dpl;
1253 sd->sd_p = ssd->ssd_p;
1254 sd->sd_gran = ssd->ssd_gran;
1258 * Populate the (physmap) array with base/bound pairs describing the
1259 * available physical memory in the system, then test this memory and
1260 * build the phys_avail array describing the actually-available memory.
1262 * If we cannot accurately determine the physical memory map, then use
1263 * value from the 0xE801 call, and failing that, the RTC.
1265 * Total memory size may be set by the kernel environment variable
1266 * hw.physmem or the compile-time define MAXMEM.
1268 * Memory is aligned to PHYSMAP_ALIGN which must be a multiple
1269 * of PAGE_SIZE. This also greatly reduces the memory test time
1270 * which would otherwise be excessive on machines with > 8G of ram.
1272 * XXX first should be vm_paddr_t.
1275 #define PHYSMAP_ALIGN (vm_paddr_t)(128 * 1024)
1276 #define PHYSMAP_ALIGN_MASK (vm_paddr_t)(PHYSMAP_ALIGN - 1)
1279 getmemsize(caddr_t kmdp, u_int64_t first)
1281 int off, physmap_idx, pa_indx, da_indx;
1283 vm_paddr_t physmap[PHYSMAP_SIZE];
1285 vm_paddr_t msgbuf_size;
1286 u_long physmem_tunable;
1288 struct bios_smap *smapbase, *smap, *smapend;
1290 quad_t dcons_addr, dcons_size;
1292 bzero(physmap, sizeof(physmap));
1296 * get memory map from INT 15:E820, kindly supplied by the loader.
1298 * subr_module.c says:
1299 * "Consumer may safely assume that size value precedes data."
1300 * ie: an int32_t immediately precedes smap.
1302 smapbase = (struct bios_smap *)preload_search_info(kmdp,
1303 MODINFO_METADATA | MODINFOMD_SMAP);
1304 if (smapbase == NULL)
1305 panic("No BIOS smap info from loader!");
1307 smapsize = *((u_int32_t *)smapbase - 1);
1308 smapend = (struct bios_smap *)((uintptr_t)smapbase + smapsize);
1310 for (smap = smapbase; smap < smapend; smap++) {
1311 if (boothowto & RB_VERBOSE)
1312 kprintf("SMAP type=%02x base=%016lx len=%016lx\n",
1313 smap->type, smap->base, smap->length);
1315 if (smap->type != SMAP_TYPE_MEMORY)
1318 if (smap->length == 0)
1321 for (i = 0; i <= physmap_idx; i += 2) {
1322 if (smap->base < physmap[i + 1]) {
1323 if (boothowto & RB_VERBOSE) {
1324 kprintf("Overlapping or non-monotonic "
1325 "memory region, ignoring "
1331 if (i <= physmap_idx)
1334 Realmem += smap->length;
1336 if (smap->base == physmap[physmap_idx + 1]) {
1337 physmap[physmap_idx + 1] += smap->length;
1342 if (physmap_idx == PHYSMAP_SIZE) {
1343 kprintf("Too many segments in the physical "
1344 "address map, giving up\n");
1347 physmap[physmap_idx] = smap->base;
1348 physmap[physmap_idx + 1] = smap->base + smap->length;
1351 base_memory = physmap[1] / 1024;
1352 /* make hole for AP bootstrap code */
1353 physmap[1] = mp_bootaddress(base_memory);
1355 /* Save EBDA address, if any */
1356 ebda_addr = (u_long)(*(u_short *)(KERNBASE + 0x40e));
1360 * Maxmem isn't the "maximum memory", it's one larger than the
1361 * highest page of the physical address space. It should be
1362 * called something like "Maxphyspage". We may adjust this
1363 * based on ``hw.physmem'' and the results of the memory test.
1365 Maxmem = atop(physmap[physmap_idx + 1]);
1368 Maxmem = MAXMEM / 4;
1371 if (TUNABLE_ULONG_FETCH("hw.physmem", &physmem_tunable))
1372 Maxmem = atop(physmem_tunable);
1375 * Don't allow MAXMEM or hw.physmem to extend the amount of memory
1378 if (Maxmem > atop(physmap[physmap_idx + 1]))
1379 Maxmem = atop(physmap[physmap_idx + 1]);
1382 * Blowing out the DMAP will blow up the system.
1384 if (Maxmem > atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS)) {
1385 kprintf("Limiting Maxmem due to DMAP size\n");
1386 Maxmem = atop(DMAP_MAX_ADDRESS - DMAP_MIN_ADDRESS);
1389 if (atop(physmap[physmap_idx + 1]) != Maxmem &&
1390 (boothowto & RB_VERBOSE)) {
1391 kprintf("Physical memory use set to %ldK\n", Maxmem * 4);
1395 * Call pmap initialization to make new kernel address space
1399 pmap_bootstrap(&first);
1400 physmap[0] = PAGE_SIZE;
1403 * Align the physmap to PHYSMAP_ALIGN and cut out anything
1406 for (i = j = 0; i <= physmap_idx; i += 2) {
1407 if (physmap[i+1] > ptoa(Maxmem))
1408 physmap[i+1] = ptoa(Maxmem);
1409 physmap[i] = (physmap[i] + PHYSMAP_ALIGN_MASK) &
1410 ~PHYSMAP_ALIGN_MASK;
1411 physmap[i+1] = physmap[i+1] & ~PHYSMAP_ALIGN_MASK;
1413 physmap[j] = physmap[i];
1414 physmap[j+1] = physmap[i+1];
1416 if (physmap[i] < physmap[i+1])
1419 physmap_idx = j - 2;
1422 * Align anything else used in the validation loop.
1424 first = (first + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
1427 * Size up each available chunk of physical memory.
1431 phys_avail[pa_indx++] = physmap[0];
1432 phys_avail[pa_indx] = physmap[0];
1433 dump_avail[da_indx] = physmap[0];
1437 * Get dcons buffer address
1439 if (kgetenv_quad("dcons.addr", &dcons_addr) == 0 ||
1440 kgetenv_quad("dcons.size", &dcons_size) == 0)
1444 * Validate the physical memory. The physical memory segments
1445 * have already been aligned to PHYSMAP_ALIGN which is a multiple
1448 for (i = 0; i <= physmap_idx; i += 2) {
1451 end = physmap[i + 1];
1453 for (pa = physmap[i]; pa < end; pa += PHYSMAP_ALIGN) {
1454 int tmp, page_bad, full;
1455 int *ptr = (int *)CADDR1;
1459 * block out kernel memory as not available.
1461 if (pa >= 0x200000 && pa < first)
1465 * block out dcons buffer
1468 && pa >= trunc_page(dcons_addr)
1469 && pa < dcons_addr + dcons_size) {
1476 * map page into kernel: valid, read/write,non-cacheable
1478 *pte = pa | PG_V | PG_RW | PG_N;
1483 * Test for alternating 1's and 0's
1485 *(volatile int *)ptr = 0xaaaaaaaa;
1487 if (*(volatile int *)ptr != 0xaaaaaaaa)
1490 * Test for alternating 0's and 1's
1492 *(volatile int *)ptr = 0x55555555;
1494 if (*(volatile int *)ptr != 0x55555555)
1499 *(volatile int *)ptr = 0xffffffff;
1501 if (*(volatile int *)ptr != 0xffffffff)
1506 *(volatile int *)ptr = 0x0;
1508 if (*(volatile int *)ptr != 0x0)
1511 * Restore original value.
1516 * Adjust array of valid/good pages.
1518 if (page_bad == TRUE)
1521 * If this good page is a continuation of the
1522 * previous set of good pages, then just increase
1523 * the end pointer. Otherwise start a new chunk.
1524 * Note that "end" points one higher than end,
1525 * making the range >= start and < end.
1526 * If we're also doing a speculative memory
1527 * test and we at or past the end, bump up Maxmem
1528 * so that we keep going. The first bad page
1529 * will terminate the loop.
1531 if (phys_avail[pa_indx] == pa) {
1532 phys_avail[pa_indx] += PHYSMAP_ALIGN;
1535 if (pa_indx == PHYS_AVAIL_ARRAY_END) {
1537 "Too many holes in the physical address space, giving up\n");
1542 phys_avail[pa_indx++] = pa;
1543 phys_avail[pa_indx] = pa + PHYSMAP_ALIGN;
1545 physmem += PHYSMAP_ALIGN / PAGE_SIZE;
1547 if (dump_avail[da_indx] == pa) {
1548 dump_avail[da_indx] += PHYSMAP_ALIGN;
1551 if (da_indx == DUMP_AVAIL_ARRAY_END) {
1555 dump_avail[da_indx++] = pa;
1556 dump_avail[da_indx] = pa + PHYSMAP_ALIGN;
1567 * The last chunk must contain at least one page plus the message
1568 * buffer to avoid complicating other code (message buffer address
1569 * calculation, etc.).
1571 msgbuf_size = (MSGBUF_SIZE + PHYSMAP_ALIGN_MASK) & ~PHYSMAP_ALIGN_MASK;
1573 while (phys_avail[pa_indx - 1] + PHYSMAP_ALIGN +
1574 msgbuf_size >= phys_avail[pa_indx]) {
1575 physmem -= atop(phys_avail[pa_indx] - phys_avail[pa_indx - 1]);
1576 phys_avail[pa_indx--] = 0;
1577 phys_avail[pa_indx--] = 0;
1580 Maxmem = atop(phys_avail[pa_indx]);
1582 /* Trim off space for the message buffer. */
1583 phys_avail[pa_indx] -= msgbuf_size;
1585 avail_end = phys_avail[pa_indx];
1587 /* Map the message buffer. */
1588 for (off = 0; off < msgbuf_size; off += PAGE_SIZE) {
1589 pmap_kenter((vm_offset_t)msgbufp + off,
1590 phys_avail[pa_indx] + off);
1594 struct machintr_abi MachIntrABI;
1605 * 7 Device Not Available (x87)
1607 * 9 Coprocessor Segment overrun (unsupported, reserved)
1609 * 11 Segment not present
1611 * 13 General Protection
1614 * 16 x87 FP Exception pending
1615 * 17 Alignment Check
1617 * 19 SIMD floating point
1619 * 32-255 INTn/external sources
1622 hammer_time(u_int64_t modulep, u_int64_t physfree)
1625 int gsel_tss, x, cpu;
1627 int metadata_missing, off;
1629 struct mdglobaldata *gd;
1633 * Prevent lowering of the ipl if we call tsleep() early.
1635 gd = &CPU_prvspace[0].mdglobaldata;
1636 bzero(gd, sizeof(*gd));
1639 * Note: on both UP and SMP curthread must be set non-NULL
1640 * early in the boot sequence because the system assumes
1641 * that 'curthread' is never NULL.
1644 gd->mi.gd_curthread = &thread0;
1645 thread0.td_gd = &gd->mi;
1647 atdevbase = ISA_HOLE_START + PTOV_OFFSET;
1650 metadata_missing = 0;
1651 if (bootinfo.bi_modulep) {
1652 preload_metadata = (caddr_t)bootinfo.bi_modulep + KERNBASE;
1653 preload_bootstrap_relocate(KERNBASE);
1655 metadata_missing = 1;
1657 if (bootinfo.bi_envp)
1658 kern_envp = (caddr_t)bootinfo.bi_envp + KERNBASE;
1661 preload_metadata = (caddr_t)(uintptr_t)(modulep + PTOV_OFFSET);
1662 preload_bootstrap_relocate(PTOV_OFFSET);
1663 kmdp = preload_search_by_type("elf kernel");
1665 kmdp = preload_search_by_type("elf64 kernel");
1666 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int);
1667 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *) + PTOV_OFFSET;
1669 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t);
1670 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t);
1673 if (boothowto & RB_VERBOSE)
1677 * Default MachIntrABI to ICU
1679 MachIntrABI = MachIntrABI_ICU;
1682 * start with one cpu. Note: with one cpu, ncpus2_shift, ncpus2_mask,
1683 * and ncpus_fit_mask remain 0.
1688 /* Init basic tunables, hz etc */
1692 * make gdt memory segments
1694 gdt_segs[GPROC0_SEL].ssd_base =
1695 (uintptr_t) &CPU_prvspace[0].mdglobaldata.gd_common_tss;
1697 gd->mi.gd_prvspace = &CPU_prvspace[0];
1699 for (x = 0; x < NGDT; x++) {
1700 if (x != GPROC0_SEL && x != (GPROC0_SEL + 1))
1701 ssdtosd(&gdt_segs[x], &gdt[x]);
1703 ssdtosyssd(&gdt_segs[GPROC0_SEL],
1704 (struct system_segment_descriptor *)&gdt[GPROC0_SEL]);
1706 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
1707 r_gdt.rd_base = (long) gdt;
1710 wrmsr(MSR_FSBASE, 0); /* User value */
1711 wrmsr(MSR_GSBASE, (u_int64_t)&gd->mi);
1712 wrmsr(MSR_KGSBASE, 0); /* User value while in the kernel */
1714 mi_gdinit(&gd->mi, 0);
1716 proc0paddr = proc0paddr_buff;
1717 mi_proc0init(&gd->mi, proc0paddr);
1718 safepri = TDPRI_MAX;
1720 /* spinlocks and the BGL */
1724 for (x = 0; x < NIDT; x++)
1725 setidt_global(x, &IDTVEC(rsvd), SDT_SYSIGT, SEL_KPL, 0);
1726 setidt_global(IDT_DE, &IDTVEC(div), SDT_SYSIGT, SEL_KPL, 0);
1727 setidt_global(IDT_DB, &IDTVEC(dbg), SDT_SYSIGT, SEL_KPL, 0);
1728 setidt_global(IDT_NMI, &IDTVEC(nmi), SDT_SYSIGT, SEL_KPL, 1);
1729 setidt_global(IDT_BP, &IDTVEC(bpt), SDT_SYSIGT, SEL_UPL, 0);
1730 setidt_global(IDT_OF, &IDTVEC(ofl), SDT_SYSIGT, SEL_KPL, 0);
1731 setidt_global(IDT_BR, &IDTVEC(bnd), SDT_SYSIGT, SEL_KPL, 0);
1732 setidt_global(IDT_UD, &IDTVEC(ill), SDT_SYSIGT, SEL_KPL, 0);
1733 setidt_global(IDT_NM, &IDTVEC(dna), SDT_SYSIGT, SEL_KPL, 0);
1734 setidt_global(IDT_DF, &IDTVEC(dblfault), SDT_SYSIGT, SEL_KPL, 1);
1735 setidt_global(IDT_FPUGP, &IDTVEC(fpusegm), SDT_SYSIGT, SEL_KPL, 0);
1736 setidt_global(IDT_TS, &IDTVEC(tss), SDT_SYSIGT, SEL_KPL, 0);
1737 setidt_global(IDT_NP, &IDTVEC(missing), SDT_SYSIGT, SEL_KPL, 0);
1738 setidt_global(IDT_SS, &IDTVEC(stk), SDT_SYSIGT, SEL_KPL, 0);
1739 setidt_global(IDT_GP, &IDTVEC(prot), SDT_SYSIGT, SEL_KPL, 0);
1740 setidt_global(IDT_PF, &IDTVEC(page), SDT_SYSIGT, SEL_KPL, 0);
1741 setidt_global(IDT_MF, &IDTVEC(fpu), SDT_SYSIGT, SEL_KPL, 0);
1742 setidt_global(IDT_AC, &IDTVEC(align), SDT_SYSIGT, SEL_KPL, 0);
1743 setidt_global(IDT_MC, &IDTVEC(mchk), SDT_SYSIGT, SEL_KPL, 0);
1744 setidt_global(IDT_XF, &IDTVEC(xmm), SDT_SYSIGT, SEL_KPL, 0);
1746 for (cpu = 0; cpu < MAXCPU; ++cpu) {
1747 r_idt_arr[cpu].rd_limit = sizeof(idt_arr[cpu]) - 1;
1748 r_idt_arr[cpu].rd_base = (long) &idt_arr[cpu][0];
1751 lidt(&r_idt_arr[0]);
1754 * Initialize the console before we print anything out.
1759 if (metadata_missing)
1760 kprintf("WARNING: loader(8) metadata is missing!\n");
1770 * Initialize IRQ mapping
1773 * SHOULD be after elcr_probe()
1775 MachIntrABI_ICU.initmap();
1776 MachIntrABI_IOAPIC.initmap();
1780 if (boothowto & RB_KDB)
1781 Debugger("Boot flags requested debugger");
1785 finishidentcpu(); /* Final stage of CPU initialization */
1786 setidt(6, &IDTVEC(ill), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1787 setidt(13, &IDTVEC(prot), SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
1789 identify_cpu(); /* Final stage of CPU initialization */
1790 initializecpu(); /* Initialize CPU registers */
1792 TUNABLE_INT_FETCH("hw.apic_io_enable", &ioapic_enable); /* for compat */
1793 TUNABLE_INT_FETCH("hw.ioapic_enable", &ioapic_enable);
1794 TUNABLE_INT_FETCH("hw.lapic_enable", &lapic_enable);
1797 * Some of the virtual machines do not work w/ I/O APIC
1798 * enabled. If the user does not explicitly enable or
1799 * disable the I/O APIC (ioapic_enable < 0), then we
1800 * disable I/O APIC on all virtual machines.
1803 * This must be done after identify_cpu(), which sets
1806 if (ioapic_enable < 0) {
1807 if (cpu_feature2 & CPUID2_VMM)
1813 /* make an initial tss so cpu can get interrupt stack on syscall! */
1814 gd->gd_common_tss.tss_rsp0 =
1815 (register_t)(thread0.td_kstack +
1816 KSTACK_PAGES * PAGE_SIZE - sizeof(struct pcb));
1817 /* Ensure the stack is aligned to 16 bytes */
1818 gd->gd_common_tss.tss_rsp0 &= ~(register_t)0xF;
1820 /* double fault stack */
1821 gd->gd_common_tss.tss_ist1 =
1822 (long)&gd->mi.gd_prvspace->idlestack[
1823 sizeof(gd->mi.gd_prvspace->idlestack)];
1825 /* Set the IO permission bitmap (empty due to tss seg limit) */
1826 gd->gd_common_tss.tss_iobase = sizeof(struct x86_64tss);
1828 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
1829 gd->gd_tss_gdt = &gdt[GPROC0_SEL];
1830 gd->gd_common_tssd = *gd->gd_tss_gdt;
1833 /* Set up the fast syscall stuff */
1834 msr = rdmsr(MSR_EFER) | EFER_SCE;
1835 wrmsr(MSR_EFER, msr);
1836 wrmsr(MSR_LSTAR, (u_int64_t)IDTVEC(fast_syscall));
1837 wrmsr(MSR_CSTAR, (u_int64_t)IDTVEC(fast_syscall32));
1838 msr = ((u_int64_t)GSEL(GCODE_SEL, SEL_KPL) << 32) |
1839 ((u_int64_t)GSEL(GUCODE32_SEL, SEL_UPL) << 48);
1840 wrmsr(MSR_STAR, msr);
1841 wrmsr(MSR_SF_MASK, PSL_NT|PSL_T|PSL_I|PSL_C|PSL_D|PSL_IOPL);
1843 getmemsize(kmdp, physfree);
1844 init_param2(physmem);
1846 /* now running on new page tables, configured,and u/iom is accessible */
1848 /* Map the message buffer. */
1850 for (off = 0; off < round_page(MSGBUF_SIZE); off += PAGE_SIZE)
1851 pmap_kenter((vm_offset_t)msgbufp + off, avail_end + off);
1854 msgbufinit(msgbufp, MSGBUF_SIZE);
1857 /* transfer to user mode */
1859 _ucodesel = GSEL(GUCODE_SEL, SEL_UPL);
1860 _udatasel = GSEL(GUDATA_SEL, SEL_UPL);
1861 _ucode32sel = GSEL(GUCODE32_SEL, SEL_UPL);
1867 /* setup proc 0's pcb */
1868 thread0.td_pcb->pcb_flags = 0;
1869 thread0.td_pcb->pcb_cr3 = KPML4phys;
1870 thread0.td_pcb->pcb_ext = NULL;
1871 lwp0.lwp_md.md_regs = &proc0_tf; /* XXX needed? */
1873 /* Location of kernel stack for locore */
1874 return ((u_int64_t)thread0.td_pcb);
1878 * Initialize machine-dependant portions of the global data structure.
1879 * Note that the global data area and cpu0's idlestack in the private
1880 * data space were allocated in locore.
1882 * Note: the idlethread's cpl is 0
1884 * WARNING! Called from early boot, 'mycpu' may not work yet.
1887 cpu_gdinit(struct mdglobaldata *gd, int cpu)
1890 gd->mi.gd_curthread = &gd->mi.gd_idlethread;
1892 lwkt_init_thread(&gd->mi.gd_idlethread,
1893 gd->mi.gd_prvspace->idlestack,
1894 sizeof(gd->mi.gd_prvspace->idlestack),
1896 lwkt_set_comm(&gd->mi.gd_idlethread, "idle_%d", cpu);
1897 gd->mi.gd_idlethread.td_switch = cpu_lwkt_switch;
1898 gd->mi.gd_idlethread.td_sp -= sizeof(void *);
1899 *(void **)gd->mi.gd_idlethread.td_sp = cpu_idle_restore;
1903 is_globaldata_space(vm_offset_t saddr, vm_offset_t eaddr)
1905 if (saddr >= (vm_offset_t)&CPU_prvspace[0] &&
1906 eaddr <= (vm_offset_t)&CPU_prvspace[MAXCPU]) {
1909 if (saddr >= DMAP_MIN_ADDRESS && eaddr <= DMAP_MAX_ADDRESS)
1915 globaldata_find(int cpu)
1917 KKASSERT(cpu >= 0 && cpu < ncpus);
1918 return(&CPU_prvspace[cpu].mdglobaldata.mi);
1922 ptrace_set_pc(struct lwp *lp, unsigned long addr)
1924 lp->lwp_md.md_regs->tf_rip = addr;
1929 ptrace_single_step(struct lwp *lp)
1931 lp->lwp_md.md_regs->tf_rflags |= PSL_T;
1936 fill_regs(struct lwp *lp, struct reg *regs)
1938 struct trapframe *tp;
1940 if ((tp = lp->lwp_md.md_regs) == NULL)
1942 bcopy(&tp->tf_rdi, ®s->r_rdi, sizeof(*regs));
1947 set_regs(struct lwp *lp, struct reg *regs)
1949 struct trapframe *tp;
1951 tp = lp->lwp_md.md_regs;
1952 if (!EFL_SECURE(regs->r_rflags, tp->tf_rflags) ||
1953 !CS_SECURE(regs->r_cs))
1955 bcopy(®s->r_rdi, &tp->tf_rdi, sizeof(*regs));
1960 #ifndef CPU_DISABLE_SSE
1962 fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87)
1964 struct env87 *penv_87 = &sv_87->sv_env;
1965 struct envxmm *penv_xmm = &sv_xmm->sv_env;
1968 /* FPU control/status */
1969 penv_87->en_cw = penv_xmm->en_cw;
1970 penv_87->en_sw = penv_xmm->en_sw;
1971 penv_87->en_tw = penv_xmm->en_tw;
1972 penv_87->en_fip = penv_xmm->en_fip;
1973 penv_87->en_fcs = penv_xmm->en_fcs;
1974 penv_87->en_opcode = penv_xmm->en_opcode;
1975 penv_87->en_foo = penv_xmm->en_foo;
1976 penv_87->en_fos = penv_xmm->en_fos;
1979 for (i = 0; i < 8; ++i)
1980 sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc;
1984 set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm)
1986 struct env87 *penv_87 = &sv_87->sv_env;
1987 struct envxmm *penv_xmm = &sv_xmm->sv_env;
1990 /* FPU control/status */
1991 penv_xmm->en_cw = penv_87->en_cw;
1992 penv_xmm->en_sw = penv_87->en_sw;
1993 penv_xmm->en_tw = penv_87->en_tw;
1994 penv_xmm->en_fip = penv_87->en_fip;
1995 penv_xmm->en_fcs = penv_87->en_fcs;
1996 penv_xmm->en_opcode = penv_87->en_opcode;
1997 penv_xmm->en_foo = penv_87->en_foo;
1998 penv_xmm->en_fos = penv_87->en_fos;
2001 for (i = 0; i < 8; ++i)
2002 sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
2004 #endif /* CPU_DISABLE_SSE */
2007 fill_fpregs(struct lwp *lp, struct fpreg *fpregs)
2009 if (lp->lwp_thread == NULL || lp->lwp_thread->td_pcb == NULL)
2011 #ifndef CPU_DISABLE_SSE
2013 fill_fpregs_xmm(&lp->lwp_thread->td_pcb->pcb_save.sv_xmm,
2014 (struct save87 *)fpregs);
2017 #endif /* CPU_DISABLE_SSE */
2018 bcopy(&lp->lwp_thread->td_pcb->pcb_save.sv_87, fpregs, sizeof *fpregs);
2023 set_fpregs(struct lwp *lp, struct fpreg *fpregs)
2025 #ifndef CPU_DISABLE_SSE
2027 set_fpregs_xmm((struct save87 *)fpregs,
2028 &lp->lwp_thread->td_pcb->pcb_save.sv_xmm);
2031 #endif /* CPU_DISABLE_SSE */
2032 bcopy(fpregs, &lp->lwp_thread->td_pcb->pcb_save.sv_87, sizeof *fpregs);
2037 fill_dbregs(struct lwp *lp, struct dbreg *dbregs)
2042 dbregs->dr[0] = rdr0();
2043 dbregs->dr[1] = rdr1();
2044 dbregs->dr[2] = rdr2();
2045 dbregs->dr[3] = rdr3();
2046 dbregs->dr[4] = rdr4();
2047 dbregs->dr[5] = rdr5();
2048 dbregs->dr[6] = rdr6();
2049 dbregs->dr[7] = rdr7();
2052 if (lp->lwp_thread == NULL || (pcb = lp->lwp_thread->td_pcb) == NULL)
2054 dbregs->dr[0] = pcb->pcb_dr0;
2055 dbregs->dr[1] = pcb->pcb_dr1;
2056 dbregs->dr[2] = pcb->pcb_dr2;
2057 dbregs->dr[3] = pcb->pcb_dr3;
2060 dbregs->dr[6] = pcb->pcb_dr6;
2061 dbregs->dr[7] = pcb->pcb_dr7;
2066 set_dbregs(struct lwp *lp, struct dbreg *dbregs)
2069 load_dr0(dbregs->dr[0]);
2070 load_dr1(dbregs->dr[1]);
2071 load_dr2(dbregs->dr[2]);
2072 load_dr3(dbregs->dr[3]);
2073 load_dr4(dbregs->dr[4]);
2074 load_dr5(dbregs->dr[5]);
2075 load_dr6(dbregs->dr[6]);
2076 load_dr7(dbregs->dr[7]);
2079 struct ucred *ucred;
2081 uint64_t mask1, mask2;
2084 * Don't let an illegal value for dr7 get set. Specifically,
2085 * check for undefined settings. Setting these bit patterns
2086 * result in undefined behaviour and can lead to an unexpected
2089 /* JG this loop looks unreadable */
2090 /* Check 4 2-bit fields for invalid patterns.
2091 * These fields are R/Wi, for i = 0..3
2093 /* Is 10 in LENi allowed when running in compatibility mode? */
2094 /* Pattern 10 in R/Wi might be used to indicate
2095 * breakpoint on I/O. Further analysis should be
2096 * carried to decide if it is safe and useful to
2097 * provide access to that capability
2099 for (i = 0, mask1 = 0x3<<16, mask2 = 0x2<<16; i < 4;
2100 i++, mask1 <<= 4, mask2 <<= 4)
2101 if ((dbregs->dr[7] & mask1) == mask2)
2104 pcb = lp->lwp_thread->td_pcb;
2105 ucred = lp->lwp_proc->p_ucred;
2108 * Don't let a process set a breakpoint that is not within the
2109 * process's address space. If a process could do this, it
2110 * could halt the system by setting a breakpoint in the kernel
2111 * (if ddb was enabled). Thus, we need to check to make sure
2112 * that no breakpoints are being enabled for addresses outside
2113 * process's address space, unless, perhaps, we were called by
2116 * XXX - what about when the watched area of the user's
2117 * address space is written into from within the kernel
2118 * ... wouldn't that still cause a breakpoint to be generated
2119 * from within kernel mode?
2122 if (priv_check_cred(ucred, PRIV_ROOT, 0) != 0) {
2123 if (dbregs->dr[7] & 0x3) {
2124 /* dr0 is enabled */
2125 if (dbregs->dr[0] >= VM_MAX_USER_ADDRESS)
2129 if (dbregs->dr[7] & (0x3<<2)) {
2130 /* dr1 is enabled */
2131 if (dbregs->dr[1] >= VM_MAX_USER_ADDRESS)
2135 if (dbregs->dr[7] & (0x3<<4)) {
2136 /* dr2 is enabled */
2137 if (dbregs->dr[2] >= VM_MAX_USER_ADDRESS)
2141 if (dbregs->dr[7] & (0x3<<6)) {
2142 /* dr3 is enabled */
2143 if (dbregs->dr[3] >= VM_MAX_USER_ADDRESS)
2148 pcb->pcb_dr0 = dbregs->dr[0];
2149 pcb->pcb_dr1 = dbregs->dr[1];
2150 pcb->pcb_dr2 = dbregs->dr[2];
2151 pcb->pcb_dr3 = dbregs->dr[3];
2152 pcb->pcb_dr6 = dbregs->dr[6];
2153 pcb->pcb_dr7 = dbregs->dr[7];
2155 pcb->pcb_flags |= PCB_DBREGS;
2162 * Return > 0 if a hardware breakpoint has been hit, and the
2163 * breakpoint was in user space. Return 0, otherwise.
2166 user_dbreg_trap(void)
2168 u_int64_t dr7, dr6; /* debug registers dr6 and dr7 */
2169 u_int64_t bp; /* breakpoint bits extracted from dr6 */
2170 int nbp; /* number of breakpoints that triggered */
2171 caddr_t addr[4]; /* breakpoint addresses */
2175 if ((dr7 & 0xff) == 0) {
2177 * all GE and LE bits in the dr7 register are zero,
2178 * thus the trap couldn't have been caused by the
2179 * hardware debug registers
2190 * None of the breakpoint bits are set meaning this
2191 * trap was not caused by any of the debug registers
2197 * at least one of the breakpoints were hit, check to see
2198 * which ones and if any of them are user space addresses
2202 addr[nbp++] = (caddr_t)rdr0();
2205 addr[nbp++] = (caddr_t)rdr1();
2208 addr[nbp++] = (caddr_t)rdr2();
2211 addr[nbp++] = (caddr_t)rdr3();
2214 for (i=0; i<nbp; i++) {
2216 (caddr_t)VM_MAX_USER_ADDRESS) {
2218 * addr[i] is in user space
2225 * None of the breakpoints are in user space.
2233 Debugger(const char *msg)
2235 kprintf("Debugger(\"%s\") called.\n", msg);
2242 * Provide inb() and outb() as functions. They are normally only
2243 * available as macros calling inlined functions, thus cannot be
2244 * called inside DDB.
2246 * The actual code is stolen from <machine/cpufunc.h>, and de-inlined.
2252 /* silence compiler warnings */
2254 void outb(u_int, u_char);
2261 * We use %%dx and not %1 here because i/o is done at %dx and not at
2262 * %edx, while gcc generates inferior code (movw instead of movl)
2263 * if we tell it to load (u_short) port.
2265 __asm __volatile("inb %%dx,%0" : "=a" (data) : "d" (port));
2270 outb(u_int port, u_char data)
2274 * Use an unnecessary assignment to help gcc's register allocator.
2275 * This make a large difference for gcc-1.40 and a tiny difference
2276 * for gcc-2.6.0. For gcc-1.40, al had to be ``asm("ax")'' for
2277 * best results. gcc-2.6.0 can't handle this.
2280 __asm __volatile("outb %0,%%dx" : : "a" (al), "d" (port));
2288 * initialize all the SMP locks
2291 /* critical region when masking or unmasking interupts */
2292 struct spinlock_deprecated imen_spinlock;
2294 /* critical region for old style disable_intr/enable_intr */
2295 struct spinlock_deprecated mpintr_spinlock;
2297 /* critical region around INTR() routines */
2298 struct spinlock_deprecated intr_spinlock;
2300 /* lock region used by kernel profiling */
2301 struct spinlock_deprecated mcount_spinlock;
2303 /* locks com (tty) data/hardware accesses: a FASTINTR() */
2304 struct spinlock_deprecated com_spinlock;
2306 /* lock regions around the clock hardware */
2307 struct spinlock_deprecated clock_spinlock;
2313 * Get the initial mplock with a count of 1 for the BSP.
2314 * This uses a LOGICAL cpu ID, ie BSP == 0.
2316 cpu_get_initial_mplock();
2318 spin_lock_init(&mcount_spinlock);
2319 spin_lock_init(&intr_spinlock);
2320 spin_lock_init(&mpintr_spinlock);
2321 spin_lock_init(&imen_spinlock);
2322 spin_lock_init(&com_spinlock);
2323 spin_lock_init(&clock_spinlock);
2325 /* our token pool needs to work early */
2326 lwkt_token_pool_init();