sys/dev/drm2/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*-
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  * $FreeBSD: src/sys/dev/drm2/i915/i915_dma.c,v 1.1 2012/05/22 11:07:44 kib Exp $
  28  */
  29
  30 #include <dev/drm2/drmP.h>
  31 #include <dev/drm2/drm.h>
  32 #include <dev/drm2/i915/i915_drm.h>
  33 #include <dev/drm2/i915/i915_drv.h>
  34 #include <dev/drm2/i915/intel_drv.h>
  35 #include <dev/drm2/i915/intel_ringbuffer.h>
  36
  37 static struct drm_i915_private *i915_mch_dev;
  38 /*
  39  * Lock protecting IPS related data structures
  40  *   - i915_mch_dev
  41  *   - dev_priv->max_delay
  42  *   - dev_priv->min_delay
  43  *   - dev_priv->fmax
  44  *   - dev_priv->gpu_busy
  45  */
  46 static struct lock mchdev_lock;
  47 LOCK_SYSINIT(mchdev, &mchdev_lock, "mchdev", LK_CANRECURSE);
  48
  49 static void i915_pineview_get_mem_freq(struct drm_device *dev);
  50 static void i915_ironlake_get_mem_freq(struct drm_device *dev);
  51 static int i915_driver_unload_int(struct drm_device *dev, bool locked);
  52
  53 static void i915_write_hws_pga(struct drm_device *dev)
  54 {
  55         drm_i915_private_t *dev_priv = dev->dev_private;
  56         u32 addr;
  57
  58         addr = dev_priv->status_page_dmah->busaddr;
  59         if (INTEL_INFO(dev)->gen >= 4)
  60                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
  61         I915_WRITE(HWS_PGA, addr);
  62 }
  63
  64 /**
  65  * Sets up the hardware status page for devices that need a physical address
  66  * in the register.
  67  */
  68 static int i915_init_phys_hws(struct drm_device *dev)
  69 {
  70         drm_i915_private_t *dev_priv = dev->dev_private;
  71         struct intel_ring_buffer *ring = LP_RING(dev_priv);
  72
  73         /*
  74          * Program Hardware Status Page
  75          * XXXKIB Keep 4GB limit for allocation for now.  This method
  76          * of allocation is used on <= 965 hardware, that has several
  77          * erratas regarding the use of physical memory > 4 GB.
  78          */
  79         DRM_UNLOCK(dev);
  80         dev_priv->status_page_dmah =
  81                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
  82         DRM_LOCK(dev);
  83         if (!dev_priv->status_page_dmah) {
  84                 DRM_ERROR("Can not allocate hardware status page\n");
  85                 return -ENOMEM;
  86         }
  87         ring->status_page.page_addr = dev_priv->hw_status_page =
  88             dev_priv->status_page_dmah->vaddr;
  89         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
  90
  91         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
  92
  93         i915_write_hws_pga(dev);
  94         DRM_DEBUG("Enabled hardware status page, phys %jx\n",
  95             (uintmax_t)dev_priv->dma_status_page);
  96         return 0;
  97 }
  98
  99 /**
 100  * Frees the hardware status page, whether it's a physical address or a virtual
 101  * address set up by the X Server.
 102  */
 103 static void i915_free_hws(struct drm_device *dev)
 104 {
 105         drm_i915_private_t *dev_priv = dev->dev_private;
 106         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 107
 108         if (dev_priv->status_page_dmah) {
 109                 drm_pci_free(dev, dev_priv->status_page_dmah);
 110                 dev_priv->status_page_dmah = NULL;
 111         }
 112
 113         if (dev_priv->status_gfx_addr) {
 114                 dev_priv->status_gfx_addr = 0;
 115                 ring->status_page.gfx_addr = 0;
 116                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
 117         }
 118
 119         /* Need to rewrite hardware status page */
 120         I915_WRITE(HWS_PGA, 0x1ffff000);
 121 }
 122
 123 void i915_kernel_lost_context(struct drm_device * dev)
 124 {
 125         drm_i915_private_t *dev_priv = dev->dev_private;
 126         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 127
 128         /*
 129          * We should never lose context on the ring with modesetting
 130          * as we don't expose it to userspace
 131          */
 132         if (drm_core_check_feature(dev, DRIVER_MODESET))
 133                 return;
 134
 135         ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 136         ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 137         ring->space = ring->head - (ring->tail + 8);
 138         if (ring->space < 0)
 139                 ring->space += ring->size;
 140
 141 #if 1
 142         KIB_NOTYET();
 143 #else
 144         if (!dev->primary->master)
 145                 return;
 146 #endif
 147
 148         if (ring->head == ring->tail && dev_priv->sarea_priv)
 149                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 150 }
 151
 152 static int i915_dma_cleanup(struct drm_device * dev)
 153 {
 154         drm_i915_private_t *dev_priv = dev->dev_private;
 155         int i;
 156
 157
 158         /* Make sure interrupts are disabled here because the uninstall ioctl
 159          * may not have been called from userspace and after dev_private
 160          * is freed, it's too late.
 161          */
 162         if (dev->irq_enabled)
 163                 drm_irq_uninstall(dev);
 164
 165         for (i = 0; i < I915_NUM_RINGS; i++)
 166                 intel_cleanup_ring_buffer(&dev_priv->rings[i]);
 167
 168         /* Clear the HWS virtual address at teardown */
 169         if (I915_NEED_GFX_HWS(dev))
 170                 i915_free_hws(dev);
 171
 172         return 0;
 173 }
 174
 175 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 176 {
 177         drm_i915_private_t *dev_priv = dev->dev_private;
 178         int ret;
 179
 180         dev_priv->sarea = drm_getsarea(dev);
 181         if (!dev_priv->sarea) {
 182                 DRM_ERROR("can not find sarea!\n");
 183                 i915_dma_cleanup(dev);
 184                 return -EINVAL;
 185         }
 186
 187         dev_priv->sarea_priv = (drm_i915_sarea_t *)
 188             ((u8 *) dev_priv->sarea->virtual + init->sarea_priv_offset);
 189
 190         if (init->ring_size != 0) {
 191                 if (LP_RING(dev_priv)->obj != NULL) {
 192                         i915_dma_cleanup(dev);
 193                         DRM_ERROR("Client tried to initialize ringbuffer in "
 194                                   "GEM mode\n");
 195                         return -EINVAL;
 196                 }
 197
 198                 ret = intel_render_ring_init_dri(dev,
 199                                                  init->ring_start,
 200                                                  init->ring_size);
 201                 if (ret) {
 202                         i915_dma_cleanup(dev);
 203                         return ret;
 204                 }
 205         }
 206
 207         dev_priv->cpp = init->cpp;
 208         dev_priv->back_offset = init->back_offset;
 209         dev_priv->front_offset = init->front_offset;
 210         dev_priv->current_page = 0;
 211         dev_priv->sarea_priv->pf_current_page = 0;
 212
 213         /* Allow hardware batchbuffers unless told otherwise.
 214          */
 215         dev_priv->allow_batchbuffer = 1;
 216
 217         return 0;
 218 }
 219
 220 static int i915_dma_resume(struct drm_device * dev)
 221 {
 222         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 223         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 224
 225         DRM_DEBUG("\n");
 226
 227         if (ring->map.handle == NULL) {
 228                 DRM_ERROR("can not ioremap virtual address for"
 229                           " ring buffer\n");
 230                 return -ENOMEM;
 231         }
 232
 233         /* Program Hardware Status Page */
 234         if (!ring->status_page.page_addr) {
 235                 DRM_ERROR("Can not find hardware status page\n");
 236                 return -EINVAL;
 237         }
 238         DRM_DEBUG("hw status page @ %p\n", ring->status_page.page_addr);
 239         if (ring->status_page.gfx_addr != 0)
 240                 intel_ring_setup_status_page(ring);
 241         else
 242                 i915_write_hws_pga(dev);
 243
 244         DRM_DEBUG("Enabled hardware status page\n");
 245
 246         return 0;
 247 }
 248
 249 static int i915_dma_init(struct drm_device *dev, void *data,
 250                          struct drm_file *file_priv)
 251 {
 252         drm_i915_init_t *init = data;
 253         int retcode = 0;
 254
 255         switch (init->func) {
 256         case I915_INIT_DMA:
 257                 retcode = i915_initialize(dev, init);
 258                 break;
 259         case I915_CLEANUP_DMA:
 260                 retcode = i915_dma_cleanup(dev);
 261                 break;
 262         case I915_RESUME_DMA:
 263                 retcode = i915_dma_resume(dev);
 264                 break;
 265         default:
 266                 retcode = -EINVAL;
 267                 break;
 268         }
 269
 270         return retcode;
 271 }
 272
 273 /* Implement basically the same security restrictions as hardware does
 274  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 275  *
 276  * Most of the calculations below involve calculating the size of a
 277  * particular instruction.  It's important to get the size right as
 278  * that tells us where the next instruction to check is.  Any illegal
 279  * instruction detected will be given a size of zero, which is a
 280  * signal to abort the rest of the buffer.
 281  */
 282 static int do_validate_cmd(int cmd)
 283 {
 284         switch (((cmd >> 29) & 0x7)) {
 285         case 0x0:
 286                 switch ((cmd >> 23) & 0x3f) {
 287                 case 0x0:
 288                         return 1;       /* MI_NOOP */
 289                 case 0x4:
 290                         return 1;       /* MI_FLUSH */
 291                 default:
 292                         return 0;       /* disallow everything else */
 293                 }
 294                 break;
 295         case 0x1:
 296                 return 0;       /* reserved */
 297         case 0x2:
 298                 return (cmd & 0xff) + 2;        /* 2d commands */
 299         case 0x3:
 300                 if (((cmd >> 24) & 0x1f) <= 0x18)
 301                         return 1;
 302
 303                 switch ((cmd >> 24) & 0x1f) {
 304                 case 0x1c:
 305                         return 1;
 306                 case 0x1d:
 307                         switch ((cmd >> 16) & 0xff) {
 308                         case 0x3:
 309                                 return (cmd & 0x1f) + 2;
 310                         case 0x4:
 311                                 return (cmd & 0xf) + 2;
 312                         default:
 313                                 return (cmd & 0xffff) + 2;
 314                         }
 315                 case 0x1e:
 316                         if (cmd & (1 << 23))
 317                                 return (cmd & 0xffff) + 1;
 318                         else
 319                                 return 1;
 320                 case 0x1f:
 321                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 322                                 return (cmd & 0x1ffff) + 2;
 323                         else if (cmd & (1 << 17))       /* indirect random */
 324                                 if ((cmd & 0xffff) == 0)
 325                                         return 0;       /* unknown length, too hard */
 326                                 else
 327                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 328                         else
 329                                 return 2;       /* indirect sequential */
 330                 default:
 331                         return 0;
 332                 }
 333         default:
 334                 return 0;
 335         }
 336
 337         return 0;
 338 }
 339
 340 static int validate_cmd(int cmd)
 341 {
 342         int ret = do_validate_cmd(cmd);
 343
 344 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 345
 346         return ret;
 347 }
 348
 349 static int i915_emit_cmds(struct drm_device *dev, int __user *buffer,
 350                           int dwords)
 351 {
 352         drm_i915_private_t *dev_priv = dev->dev_private;
 353         int i;
 354
 355         if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
 356                 return -EINVAL;
 357
 358         BEGIN_LP_RING((dwords+1)&~1);
 359
 360         for (i = 0; i < dwords;) {
 361                 int cmd, sz;
 362
 363                 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
 364                         return -EINVAL;
 365
 366                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 367                         return -EINVAL;
 368
 369                 OUT_RING(cmd);
 370
 371                 while (++i, --sz) {
 372                         if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
 373                                                          sizeof(cmd))) {
 374                                 return -EINVAL;
 375                         }
 376                         OUT_RING(cmd);
 377                 }
 378         }
 379
 380         if (dwords & 1)
 381                 OUT_RING(0);
 382
 383         ADVANCE_LP_RING();
 384
 385         return 0;
 386 }
 387
 388 int i915_emit_box(struct drm_device * dev,
 389                   struct drm_clip_rect *boxes,
 390                   int i, int DR1, int DR4)
 391 {
 392         struct drm_clip_rect box;
 393
 394         if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
 395                 return -EFAULT;
 396         }
 397
 398         return (i915_emit_box_p(dev, &box, DR1, DR4));
 399 }
 400
 401 int
 402 i915_emit_box_p(struct drm_device *dev, struct drm_clip_rect *box,
 403     int DR1, int DR4)
 404 {
 405         drm_i915_private_t *dev_priv = dev->dev_private;
 406         int ret;
 407
 408         if (box->y2 <= box->y1 || box->x2 <= box->x1 || box->y2 <= 0 ||
 409             box->x2 <= 0) {
 410                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 411                           box->x1, box->y1, box->x2, box->y2);
 412                 return -EINVAL;
 413         }
 414
 415         if (INTEL_INFO(dev)->gen >= 4) {
 416                 ret = BEGIN_LP_RING(4);
 417                 if (ret != 0)
 418                         return (ret);
 419
 420                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 421                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 422                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 423                 OUT_RING(DR4);
 424         } else {
 425                 ret = BEGIN_LP_RING(6);
 426                 if (ret != 0)
 427                         return (ret);
 428
 429                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 430                 OUT_RING(DR1);
 431                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 432                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 433                 OUT_RING(DR4);
 434                 OUT_RING(0);
 435         }
 436         ADVANCE_LP_RING();
 437
 438         return 0;
 439 }
 440
 441 /* XXX: Emitting the counter should really be moved to part of the IRQ
 442  * emit. For now, do it in both places:
 443  */
 444
 445 static void i915_emit_breadcrumb(struct drm_device *dev)
 446 {
 447         drm_i915_private_t *dev_priv = dev->dev_private;
 448
 449         if (++dev_priv->counter > 0x7FFFFFFFUL)
 450                 dev_priv->counter = 0;
 451         if (dev_priv->sarea_priv)
 452                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
 453
 454         if (BEGIN_LP_RING(4) == 0) {
 455                 OUT_RING(MI_STORE_DWORD_INDEX);
 456                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 457                 OUT_RING(dev_priv->counter);
 458                 OUT_RING(0);
 459                 ADVANCE_LP_RING();
 460         }
 461 }
 462
 463 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 464     drm_i915_cmdbuffer_t * cmd, struct drm_clip_rect *cliprects, void *cmdbuf)
 465 {
 466         int nbox = cmd->num_cliprects;
 467         int i = 0, count, ret;
 468
 469         if (cmd->sz & 0x3) {
 470                 DRM_ERROR("alignment\n");
 471                 return -EINVAL;
 472         }
 473
 474         i915_kernel_lost_context(dev);
 475
 476         count = nbox ? nbox : 1;
 477
 478         for (i = 0; i < count; i++) {
 479                 if (i < nbox) {
 480                         ret = i915_emit_box_p(dev, &cmd->cliprects[i],
 481                             cmd->DR1, cmd->DR4);
 482                         if (ret)
 483                                 return ret;
 484                 }
 485
 486                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 487                 if (ret)
 488                         return ret;
 489         }
 490
 491         i915_emit_breadcrumb(dev);
 492         return 0;
 493 }
 494
 495 static int
 496 i915_dispatch_batchbuffer(struct drm_device * dev,
 497     drm_i915_batchbuffer_t * batch, struct drm_clip_rect *cliprects)
 498 {
 499         drm_i915_private_t *dev_priv = dev->dev_private;
 500         int nbox = batch->num_cliprects;
 501         int i, count, ret;
 502
 503         if ((batch->start | batch->used) & 0x7) {
 504                 DRM_ERROR("alignment\n");
 505                 return -EINVAL;
 506         }
 507
 508         i915_kernel_lost_context(dev);
 509
 510         count = nbox ? nbox : 1;
 511
 512         for (i = 0; i < count; i++) {
 513                 if (i < nbox) {
 514                         int ret = i915_emit_box_p(dev, &cliprects[i],
 515                             batch->DR1, batch->DR4);
 516                         if (ret)
 517                                 return ret;
 518                 }
 519
 520                 if (!IS_I830(dev) && !IS_845G(dev)) {
 521                         ret = BEGIN_LP_RING(2);
 522                         if (ret != 0)
 523                                 return (ret);
 524
 525                         if (INTEL_INFO(dev)->gen >= 4) {
 526                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) |
 527                                     MI_BATCH_NON_SECURE_I965);
 528                                 OUT_RING(batch->start);
 529                         } else {
 530                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 531                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 532                         }
 533                 } else {
 534                         ret = BEGIN_LP_RING(4);
 535                         if (ret != 0)
 536                                 return (ret);
 537
 538                         OUT_RING(MI_BATCH_BUFFER);
 539                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 540                         OUT_RING(batch->start + batch->used - 4);
 541                         OUT_RING(0);
 542                 }
 543                 ADVANCE_LP_RING();
 544         }
 545
 546         i915_emit_breadcrumb(dev);
 547
 548         return 0;
 549 }
 550
 551 static int i915_dispatch_flip(struct drm_device * dev)
 552 {
 553         drm_i915_private_t *dev_priv = dev->dev_private;
 554         int ret;
 555
 556         if (!dev_priv->sarea_priv)
 557                 return -EINVAL;
 558
 559         DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
 560                   __func__,
 561                   dev_priv->current_page,
 562                   dev_priv->sarea_priv->pf_current_page);
 563
 564         i915_kernel_lost_context(dev);
 565
 566         ret = BEGIN_LP_RING(10);
 567         if (ret)
 568                 return ret;
 569         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 570         OUT_RING(0);
 571
 572         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 573         OUT_RING(0);
 574         if (dev_priv->current_page == 0) {
 575                 OUT_RING(dev_priv->back_offset);
 576                 dev_priv->current_page = 1;
 577         } else {
 578                 OUT_RING(dev_priv->front_offset);
 579                 dev_priv->current_page = 0;
 580         }
 581         OUT_RING(0);
 582
 583         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 584         OUT_RING(0);
 585
 586         ADVANCE_LP_RING();
 587
 588         if (++dev_priv->counter > 0x7FFFFFFFUL)
 589                 dev_priv->counter = 0;
 590         if (dev_priv->sarea_priv)
 591                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
 592
 593         if (BEGIN_LP_RING(4) == 0) {
 594                 OUT_RING(MI_STORE_DWORD_INDEX);
 595                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 596                 OUT_RING(dev_priv->counter);
 597                 OUT_RING(0);
 598                 ADVANCE_LP_RING();
 599         }
 600
 601         dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 602         return 0;
 603 }
 604
 605 static int
 606 i915_quiescent(struct drm_device *dev)
 607 {
 608         struct intel_ring_buffer *ring = LP_RING(dev->dev_private);
 609
 610         i915_kernel_lost_context(dev);
 611         return (intel_wait_ring_idle(ring));
 612 }
 613
 614 static int
 615 i915_flush_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv)
 616 {
 617         int ret;
 618
 619         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 620
 621         DRM_LOCK(dev);
 622         ret = i915_quiescent(dev);
 623         DRM_UNLOCK(dev);
 624
 625         return (ret);
 626 }
 627
 628 static int i915_batchbuffer(struct drm_device *dev, void *data,
 629                             struct drm_file *file_priv)
 630 {
 631         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 632         drm_i915_sarea_t *sarea_priv;
 633         drm_i915_batchbuffer_t *batch = data;
 634         struct drm_clip_rect *cliprects;
 635         size_t cliplen;
 636         int ret;
 637
 638         if (!dev_priv->allow_batchbuffer) {
 639                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 640                 return -EINVAL;
 641         }
 642         DRM_UNLOCK(dev);
 643
 644         DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
 645                   batch->start, batch->used, batch->num_cliprects);
 646
 647         cliplen = batch->num_cliprects * sizeof(struct drm_clip_rect);
 648         if (batch->num_cliprects < 0)
 649                 return -EFAULT;
 650         if (batch->num_cliprects != 0) {
 651                 cliprects = kmalloc(batch->num_cliprects *
 652                     sizeof(struct drm_clip_rect), DRM_MEM_DMA,
 653                     M_WAITOK | M_ZERO);
 654
 655                 ret = -copyin(batch->cliprects, cliprects,
 656                     batch->num_cliprects * sizeof(struct drm_clip_rect));
 657                 if (ret != 0) {
 658                         DRM_LOCK(dev);
 659                         goto fail_free;
 660                 }
 661         } else
 662                 cliprects = NULL;
 663
 664         DRM_LOCK(dev);
 665         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 666         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 667
 668         sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
 669         if (sarea_priv)
 670                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 671
 672 fail_free:
 673         kfree(cliprects, DRM_MEM_DMA);
 674         return ret;
 675 }
 676
 677 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 678                           struct drm_file *file_priv)
 679 {
 680         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 681         drm_i915_sarea_t *sarea_priv;
 682         drm_i915_cmdbuffer_t *cmdbuf = data;
 683         struct drm_clip_rect *cliprects = NULL;
 684         void *batch_data;
 685         int ret;
 686
 687         DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 688                   cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 689
 690         if (cmdbuf->num_cliprects < 0)
 691                 return -EINVAL;
 692
 693         DRM_UNLOCK(dev);
 694
 695         batch_data = kmalloc(cmdbuf->sz, DRM_MEM_DMA, M_WAITOK);
 696
 697         ret = -copyin(cmdbuf->buf, batch_data, cmdbuf->sz);
 698         if (ret != 0) {
 699                 DRM_LOCK(dev);
 700                 goto fail_batch_free;
 701         }
 702
 703         if (cmdbuf->num_cliprects) {
 704                 cliprects = kmalloc(cmdbuf->num_cliprects *
 705                     sizeof(struct drm_clip_rect), DRM_MEM_DMA,
 706                     M_WAITOK | M_ZERO);
 707                 ret = -copyin(cmdbuf->cliprects, cliprects,
 708                     cmdbuf->num_cliprects * sizeof(struct drm_clip_rect));
 709                 if (ret != 0) {
 710                         DRM_LOCK(dev);
 711                         goto fail_clip_free;
 712                 }
 713         }
 714
 715         DRM_LOCK(dev);
 716         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 717         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 718         if (ret) {
 719                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 720                 goto fail_clip_free;
 721         }
 722
 723         sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
 724         if (sarea_priv)
 725                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 726
 727 fail_clip_free:
 728         kfree(cliprects, DRM_MEM_DMA);
 729 fail_batch_free:
 730         kfree(batch_data, DRM_MEM_DMA);
 731         return ret;
 732 }
 733
 734 static int i915_flip_bufs(struct drm_device *dev, void *data,
 735                           struct drm_file *file_priv)
 736 {
 737         int ret;
 738
 739         DRM_DEBUG("%s\n", __func__);
 740
 741         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 742
 743         ret = i915_dispatch_flip(dev);
 744
 745         return ret;
 746 }
 747
 748 static int i915_getparam(struct drm_device *dev, void *data,
 749                          struct drm_file *file_priv)
 750 {
 751         drm_i915_private_t *dev_priv = dev->dev_private;
 752         drm_i915_getparam_t *param = data;
 753         int value;
 754
 755         if (!dev_priv) {
 756                 DRM_ERROR("called with no initialization\n");
 757                 return -EINVAL;
 758         }
 759
 760         switch (param->param) {
 761         case I915_PARAM_IRQ_ACTIVE:
 762                 value = dev->irq_enabled ? 1 : 0;
 763                 break;
 764         case I915_PARAM_ALLOW_BATCHBUFFER:
 765                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 766                 break;
 767         case I915_PARAM_LAST_DISPATCH:
 768                 value = READ_BREADCRUMB(dev_priv);
 769                 break;
 770         case I915_PARAM_CHIPSET_ID:
 771                 value = dev->pci_device;
 772                 break;
 773         case I915_PARAM_HAS_GEM:
 774                 value = 1;
 775                 break;
 776         case I915_PARAM_NUM_FENCES_AVAIL:
 777                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 778                 break;
 779         case I915_PARAM_HAS_OVERLAY:
 780                 value = dev_priv->overlay ? 1 : 0;
 781                 break;
 782         case I915_PARAM_HAS_PAGEFLIPPING:
 783                 value = 1;
 784                 break;
 785         case I915_PARAM_HAS_EXECBUF2:
 786                 value = 1;
 787                 break;
 788         case I915_PARAM_HAS_BSD:
 789                 value = HAS_BSD(dev);
 790                 break;
 791         case I915_PARAM_HAS_BLT:
 792                 value = HAS_BLT(dev);
 793                 break;
 794         case I915_PARAM_HAS_RELAXED_FENCING:
 795                 value = 1;
 796                 break;
 797         case I915_PARAM_HAS_COHERENT_RINGS:
 798                 value = 1;
 799                 break;
 800         case I915_PARAM_HAS_EXEC_CONSTANTS:
 801                 value = INTEL_INFO(dev)->gen >= 4;
 802                 break;
 803         case I915_PARAM_HAS_RELAXED_DELTA:
 804                 value = 1;
 805                 break;
 806         case I915_PARAM_HAS_GEN7_SOL_RESET:
 807                 value = 1;
 808                 break;
 809         case I915_PARAM_HAS_LLC:
 810                 value = HAS_LLC(dev);
 811                 break;
 812         default:
 813                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
 814                                  param->param);
 815                 return -EINVAL;
 816         }
 817
 818         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 819                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 820                 return -EFAULT;
 821         }
 822
 823         return 0;
 824 }
 825
 826 static int i915_setparam(struct drm_device *dev, void *data,
 827                          struct drm_file *file_priv)
 828 {
 829         drm_i915_private_t *dev_priv = dev->dev_private;
 830         drm_i915_setparam_t *param = data;
 831
 832         if (!dev_priv) {
 833                 DRM_ERROR("called with no initialization\n");
 834                 return -EINVAL;
 835         }
 836
 837         switch (param->param) {
 838         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 839                 break;
 840         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 841                 dev_priv->tex_lru_log_granularity = param->value;
 842                 break;
 843         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 844                 dev_priv->allow_batchbuffer = param->value;
 845                 break;
 846         case I915_SETPARAM_NUM_USED_FENCES:
 847                 if (param->value > dev_priv->num_fence_regs ||
 848                     param->value < 0)
 849                         return -EINVAL;
 850                 /* Userspace can use first N regs */
 851                 dev_priv->fence_reg_start = param->value;
 852                 break;
 853         default:
 854                 DRM_DEBUG("unknown parameter %d\n", param->param);
 855                 return -EINVAL;
 856         }
 857
 858         return 0;
 859 }
 860
 861 static int i915_set_status_page(struct drm_device *dev, void *data,
 862                                 struct drm_file *file_priv)
 863 {
 864         drm_i915_private_t *dev_priv = dev->dev_private;
 865         drm_i915_hws_addr_t *hws = data;
 866         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 867
 868         if (!I915_NEED_GFX_HWS(dev))
 869                 return -EINVAL;
 870
 871         if (!dev_priv) {
 872                 DRM_ERROR("called with no initialization\n");
 873                 return -EINVAL;
 874         }
 875
 876         DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
 877         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 878                 DRM_ERROR("tried to set status page when mode setting active\n");
 879                 return 0;
 880         }
 881
 882         ring->status_page.gfx_addr = dev_priv->status_gfx_addr =
 883             hws->addr & (0x1ffff<<12);
 884
 885         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
 886         dev_priv->hws_map.size = 4*1024;
 887         dev_priv->hws_map.type = 0;
 888         dev_priv->hws_map.flags = 0;
 889         dev_priv->hws_map.mtrr = 0;
 890
 891         drm_core_ioremap_wc(&dev_priv->hws_map, dev);
 892         if (dev_priv->hws_map.virtual == NULL) {
 893                 i915_dma_cleanup(dev);
 894                 ring->status_page.gfx_addr = dev_priv->status_gfx_addr = 0;
 895                 DRM_ERROR("can not ioremap virtual address for"
 896                                 " G33 hw status page\n");
 897                 return -ENOMEM;
 898         }
 899         ring->status_page.page_addr = dev_priv->hw_status_page =
 900             dev_priv->hws_map.virtual;
 901
 902         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 903         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
 904         DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n",
 905                         dev_priv->status_gfx_addr);
 906         DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
 907         return 0;
 908 }
 909
 910 static bool
 911 intel_enable_ppgtt(struct drm_device *dev)
 912 {
 913         if (i915_enable_ppgtt >= 0)
 914                 return i915_enable_ppgtt;
 915
 916         /* Disable ppgtt on SNB if VT-d is on. */
 917         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_enabled)
 918                 return false;
 919
 920         return true;
 921 }
 922
 923 static int
 924 i915_load_gem_init(struct drm_device *dev)
 925 {
 926         struct drm_i915_private *dev_priv = dev->dev_private;
 927         unsigned long prealloc_size, gtt_size, mappable_size;
 928         int ret;
 929
 930         prealloc_size = dev_priv->mm.gtt.stolen_size;
 931         gtt_size = dev_priv->mm.gtt.gtt_total_entries << PAGE_SHIFT;
 932         mappable_size = dev_priv->mm.gtt.gtt_mappable_entries << PAGE_SHIFT;
 933
 934         /* Basic memrange allocator for stolen space */
 935         drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);
 936
 937         DRM_LOCK(dev);
 938         if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
 939                 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
 940                  * aperture accordingly when using aliasing ppgtt. */
 941                 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
 942                 /* For paranoia keep the guard page in between. */
 943                 gtt_size -= PAGE_SIZE;
 944
 945                 i915_gem_do_init(dev, 0, mappable_size, gtt_size);
 946
 947                 ret = i915_gem_init_aliasing_ppgtt(dev);
 948                 if (ret) {
 949                         DRM_UNLOCK(dev);
 950                         return ret;
 951                 }
 952         } else {
 953                 /* Let GEM Manage all of the aperture.
 954                  *
 955                  * However, leave one page at the end still bound to the scratch
 956                  * page.  There are a number of places where the hardware
 957                  * apparently prefetches past the end of the object, and we've
 958                  * seen multiple hangs with the GPU head pointer stuck in a
 959                  * batchbuffer bound at the last page of the aperture.  One page
 960                  * should be enough to keep any prefetching inside of the
 961                  * aperture.
 962                  */
 963                 i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE);
 964         }
 965
 966         ret = i915_gem_init_hw(dev);
 967         DRM_UNLOCK(dev);
 968         if (ret != 0) {
 969                 i915_gem_cleanup_aliasing_ppgtt(dev);
 970                 return (ret);
 971         }
 972
 973 #if 0
 974         /* Try to set up FBC with a reasonable compressed buffer size */
 975         if (I915_HAS_FBC(dev) && i915_powersave) {
 976                 int cfb_size;
 977
 978                 /* Leave 1M for line length buffer & misc. */
 979
 980                 /* Try to get a 32M buffer... */
 981                 if (prealloc_size > (36*1024*1024))
 982                         cfb_size = 32*1024*1024;
 983                 else /* fall back to 7/8 of the stolen space */
 984                         cfb_size = prealloc_size * 7 / 8;
 985                 i915_setup_compression(dev, cfb_size);
 986         }
 987 #endif
 988
 989         /* Allow hardware batchbuffers unless told otherwise. */
 990         dev_priv->allow_batchbuffer = 1;
 991         return 0;
 992 }
 993
 994 static int
 995 i915_load_modeset_init(struct drm_device *dev)
 996 {
 997         struct drm_i915_private *dev_priv = dev->dev_private;
 998         int ret;
 999
1000         ret = intel_parse_bios(dev);
1001         if (ret)
1002                 DRM_INFO("failed to find VBIOS tables\n");
1003
1004 #if 0
1005         intel_register_dsm_handler();
1006 #endif
1007
1008         /* IIR "flip pending" bit means done if this bit is set */
1009         if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
1010                 dev_priv->flip_pending_is_done = true;
1011
1012         intel_modeset_init(dev);
1013
1014         ret = i915_load_gem_init(dev);
1015         if (ret != 0)
1016                 goto cleanup_gem;
1017
1018         intel_modeset_gem_init(dev);
1019
1020         ret = drm_irq_install(dev);
1021         if (ret)
1022                 goto cleanup_gem;
1023
1024         dev->vblank_disable_allowed = 1;
1025
1026         ret = intel_fbdev_init(dev);
1027         if (ret)
1028                 goto cleanup_gem;
1029
1030         drm_kms_helper_poll_init(dev);
1031
1032         /* We're off and running w/KMS */
1033         dev_priv->mm.suspended = 0;
1034
1035         return (0);
1036
1037 cleanup_gem:
1038         DRM_LOCK(dev);
1039         i915_gem_cleanup_ringbuffer(dev);
1040         DRM_UNLOCK(dev);
1041         i915_gem_cleanup_aliasing_ppgtt(dev);
1042         return (ret);
1043 }
1044
1045 static int
1046 i915_get_bridge_dev(struct drm_device *dev)
1047 {
1048         struct drm_i915_private *dev_priv;
1049
1050         dev_priv = dev->dev_private;
1051
1052         dev_priv->bridge_dev = intel_gtt_get_bridge_device();
1053         if (dev_priv->bridge_dev == NULL) {
1054                 DRM_ERROR("bridge device not found\n");
1055                 return (-1);
1056         }
1057         return (0);
1058 }
1059
1060 #define MCHBAR_I915 0x44
1061 #define MCHBAR_I965 0x48
1062 #define MCHBAR_SIZE (4*4096)
1063
1064 #define DEVEN_REG 0x54
1065 #define   DEVEN_MCHBAR_EN (1 << 28)
1066
1067 /* Allocate space for the MCH regs if needed, return nonzero on error */
1068 static int
1069 intel_alloc_mchbar_resource(struct drm_device *dev)
1070 {
1071         drm_i915_private_t *dev_priv;
1072         device_t vga;
1073         int reg;
1074         u32 temp_lo, temp_hi;
1075         u64 mchbar_addr, temp;
1076
1077         dev_priv = dev->dev_private;
1078         reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1079
1080         if (INTEL_INFO(dev)->gen >= 4)
1081                 temp_hi = pci_read_config(dev_priv->bridge_dev, reg + 4, 4);
1082         else
1083                 temp_hi = 0;
1084         temp_lo = pci_read_config(dev_priv->bridge_dev, reg, 4);
1085         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1086
1087         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1088 #ifdef XXX_CONFIG_PNP
1089         if (mchbar_addr &&
1090             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1091                 return 0;
1092 #endif
1093
1094         /* Get some space for it */
1095         vga = device_get_parent(dev->device);
1096         dev_priv->mch_res_rid = 0x100;
1097         dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
1098             dev->device, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
1099             MCHBAR_SIZE, RF_ACTIVE | RF_SHAREABLE);
1100         if (dev_priv->mch_res == NULL) {
1101                 DRM_ERROR("failed mchbar resource alloc\n");
1102                 return (-ENOMEM);
1103         }
1104
1105         if (INTEL_INFO(dev)->gen >= 4) {
1106                 temp = rman_get_start(dev_priv->mch_res);
1107                 temp >>= 32;
1108                 pci_write_config(dev_priv->bridge_dev, reg + 4, temp, 4);
1109         }
1110         pci_write_config(dev_priv->bridge_dev, reg,
1111             rman_get_start(dev_priv->mch_res) & UINT32_MAX, 4);
1112         return (0);
1113 }
1114
1115 static void
1116 intel_setup_mchbar(struct drm_device *dev)
1117 {
1118         drm_i915_private_t *dev_priv;
1119         int mchbar_reg;
1120         u32 temp;
1121         bool enabled;
1122
1123         dev_priv = dev->dev_private;
1124         mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1125
1126         dev_priv->mchbar_need_disable = false;
1127
1128         if (IS_I915G(dev) || IS_I915GM(dev)) {
1129                 temp = pci_read_config(dev_priv->bridge_dev, DEVEN_REG, 4);
1130                 enabled = (temp & DEVEN_MCHBAR_EN) != 0;
1131         } else {
1132                 temp = pci_read_config(dev_priv->bridge_dev, mchbar_reg, 4);
1133                 enabled = temp & 1;
1134         }
1135
1136         /* If it's already enabled, don't have to do anything */
1137         if (enabled) {
1138                 DRM_DEBUG("mchbar already enabled\n");
1139                 return;
1140         }
1141
1142         if (intel_alloc_mchbar_resource(dev))
1143                 return;
1144
1145         dev_priv->mchbar_need_disable = true;
1146
1147         /* Space is allocated or reserved, so enable it. */
1148         if (IS_I915G(dev) || IS_I915GM(dev)) {
1149                 pci_write_config(dev_priv->bridge_dev, DEVEN_REG,
1150                     temp | DEVEN_MCHBAR_EN, 4);
1151         } else {
1152                 temp = pci_read_config(dev_priv->bridge_dev, mchbar_reg, 4);
1153                 pci_write_config(dev_priv->bridge_dev, mchbar_reg, temp | 1, 4);
1154         }
1155 }
1156
1157 static void
1158 intel_teardown_mchbar(struct drm_device *dev)
1159 {
1160         drm_i915_private_t *dev_priv;
1161         device_t vga;
1162         int mchbar_reg;
1163         u32 temp;
1164
1165         dev_priv = dev->dev_private;
1166         mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1167
1168         if (dev_priv->mchbar_need_disable) {
1169                 if (IS_I915G(dev) || IS_I915GM(dev)) {
1170                         temp = pci_read_config(dev_priv->bridge_dev,
1171                             DEVEN_REG, 4);
1172                         temp &= ~DEVEN_MCHBAR_EN;
1173                         pci_write_config(dev_priv->bridge_dev, DEVEN_REG,
1174                             temp, 4);
1175                 } else {
1176                         temp = pci_read_config(dev_priv->bridge_dev,
1177                             mchbar_reg, 4);
1178                         temp &= ~1;
1179                         pci_write_config(dev_priv->bridge_dev, mchbar_reg,
1180                             temp, 4);
1181                 }
1182         }
1183
1184         if (dev_priv->mch_res != NULL) {
1185                 vga = device_get_parent(dev->device);
1186                 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev->device,
1187                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1188                 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev->device,
1189                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1190                 dev_priv->mch_res = NULL;
1191         }
1192 }
1193
1194 int
1195 i915_driver_load(struct drm_device *dev, unsigned long flags)
1196 {
1197         struct drm_i915_private *dev_priv = dev->dev_private;
1198         unsigned long base, size;
1199         int mmio_bar, ret;
1200
1201         ret = 0;
1202
1203         /* i915 has 4 more counters */
1204         dev->counters += 4;
1205         dev->types[6] = _DRM_STAT_IRQ;
1206         dev->types[7] = _DRM_STAT_PRIMARY;
1207         dev->types[8] = _DRM_STAT_SECONDARY;
1208         dev->types[9] = _DRM_STAT_DMA;
1209
1210         dev_priv = kmalloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER,
1211             M_ZERO | M_WAITOK);
1212         if (dev_priv == NULL)
1213                 return -ENOMEM;
1214
1215         dev->dev_private = (void *)dev_priv;
1216         dev_priv->dev = dev;
1217         dev_priv->info = i915_get_device_id(dev->pci_device);
1218
1219         if (i915_get_bridge_dev(dev)) {
1220                 kfree(dev_priv, DRM_MEM_DRIVER);
1221                 return (-EIO);
1222         }
1223         dev_priv->mm.gtt = intel_gtt_get();
1224
1225         /* Add register map (needed for suspend/resume) */
1226         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1227         base = drm_get_resource_start(dev, mmio_bar);
1228         size = drm_get_resource_len(dev, mmio_bar);
1229
1230         ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
1231             _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
1232
1233         dev_priv->tq = taskqueue_create("915", M_WAITOK,
1234             taskqueue_thread_enqueue, &dev_priv->tq);
1235         taskqueue_start_threads(&dev_priv->tq, 1, PWAIT, "i915 taskq");
1236         lockinit(&dev_priv->gt_lock, "915gt", 0, LK_CANRECURSE);
1237         lockinit(&dev_priv->error_lock, "915err", 0, LK_CANRECURSE);
1238         lockinit(&dev_priv->error_completion_lock, "915cmp", 0, LK_CANRECURSE);
1239         lockinit(&dev_priv->rps_lock, "915rps", 0, LK_CANRECURSE);
1240
1241         dev_priv->has_gem = 1;
1242         intel_irq_init(dev);
1243
1244         intel_setup_mchbar(dev);
1245         intel_setup_gmbus(dev);
1246         intel_opregion_setup(dev);
1247
1248         intel_setup_bios(dev);
1249
1250         i915_gem_load(dev);
1251
1252         /* Init HWS */
1253         if (!I915_NEED_GFX_HWS(dev)) {
1254                 ret = i915_init_phys_hws(dev);
1255                 if (ret != 0) {
1256                         drm_rmmap(dev, dev_priv->mmio_map);
1257                         drm_free(dev_priv, sizeof(struct drm_i915_private),
1258                             DRM_MEM_DRIVER);
1259                         return ret;
1260                 }
1261         }
1262
1263         if (IS_PINEVIEW(dev))
1264                 i915_pineview_get_mem_freq(dev);
1265         else if (IS_GEN5(dev))
1266                 i915_ironlake_get_mem_freq(dev);
1267
1268         lockinit(&dev_priv->irq_lock, "userirq", 0, LK_CANRECURSE);
1269
1270         if (IS_IVYBRIDGE(dev))
1271                 dev_priv->num_pipe = 3;
1272         else if (IS_MOBILE(dev) || !IS_GEN2(dev))
1273                 dev_priv->num_pipe = 2;
1274         else
1275                 dev_priv->num_pipe = 1;
1276
1277         ret = drm_vblank_init(dev, dev_priv->num_pipe);
1278         if (ret)
1279                 goto out_gem_unload;
1280
1281         /* Start out suspended */
1282         dev_priv->mm.suspended = 1;
1283
1284         intel_detect_pch(dev);
1285
1286         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1287                 DRM_UNLOCK(dev);
1288                 ret = i915_load_modeset_init(dev);
1289                 DRM_LOCK(dev);
1290                 if (ret < 0) {
1291                         DRM_ERROR("failed to init modeset\n");
1292                         goto out_gem_unload;
1293                 }
1294         }
1295
1296         intel_opregion_init(dev);
1297
1298         callout_init(&dev_priv->hangcheck_timer, 1);
1299         callout_reset(&dev_priv->hangcheck_timer, DRM_I915_HANGCHECK_PERIOD,
1300             i915_hangcheck_elapsed, dev);
1301
1302         if (IS_GEN5(dev)) {
1303                 lockmgr(&mchdev_lock, LK_EXCLUSIVE);
1304                 i915_mch_dev = dev_priv;
1305                 dev_priv->mchdev_lock = &mchdev_lock;
1306                 lockmgr(&mchdev_lock, LK_RELEASE);
1307         }
1308
1309         return (0);
1310
1311 out_gem_unload:
1312         /* XXXKIB */
1313         (void) i915_driver_unload_int(dev, true);
1314         return (ret);
1315 }
1316
1317 static int
1318 i915_driver_unload_int(struct drm_device *dev, bool locked)
1319 {
1320         struct drm_i915_private *dev_priv = dev->dev_private;
1321         int ret;
1322
1323         if (!locked)
1324                 DRM_LOCK(dev);
1325         ret = i915_gpu_idle(dev, true);
1326         if (ret)
1327                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1328         if (!locked)
1329                 DRM_UNLOCK(dev);
1330
1331         i915_free_hws(dev);
1332
1333         intel_teardown_mchbar(dev);
1334
1335         if (locked)
1336                 DRM_UNLOCK(dev);
1337         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1338                 intel_fbdev_fini(dev);
1339                 intel_modeset_cleanup(dev);
1340         }
1341
1342         /* Free error state after interrupts are fully disabled. */
1343         callout_stop(&dev_priv->hangcheck_timer);
1344         callout_drain(&dev_priv->hangcheck_timer);
1345
1346         i915_destroy_error_state(dev);
1347
1348         intel_opregion_fini(dev);
1349
1350         if (locked)
1351                 DRM_LOCK(dev);
1352
1353         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1354                 if (!locked)
1355                         DRM_LOCK(dev);
1356                 i915_gem_free_all_phys_object(dev);
1357                 i915_gem_cleanup_ringbuffer(dev);
1358                 if (!locked)
1359                         DRM_UNLOCK(dev);
1360                 i915_gem_cleanup_aliasing_ppgtt(dev);
1361 #if 1
1362                 KIB_NOTYET();
1363 #else
1364                 if (I915_HAS_FBC(dev) && i915_powersave)
1365                         i915_cleanup_compression(dev);
1366 #endif
1367                 drm_mm_takedown(&dev_priv->mm.stolen);
1368
1369                 intel_cleanup_overlay(dev);
1370
1371                 if (!I915_NEED_GFX_HWS(dev))
1372                         i915_free_hws(dev);
1373         }
1374
1375         i915_gem_unload(dev);
1376
1377         lockuninit(&dev_priv->irq_lock);
1378
1379         if (dev_priv->tq != NULL)
1380                 taskqueue_free(dev_priv->tq);
1381
1382         bus_generic_detach(dev->device);
1383         drm_rmmap(dev, dev_priv->mmio_map);
1384         intel_teardown_gmbus(dev);
1385
1386         lockuninit(&dev_priv->error_lock);
1387         lockuninit(&dev_priv->error_completion_lock);
1388         lockuninit(&dev_priv->rps_lock);
1389         drm_free(dev->dev_private, sizeof(drm_i915_private_t),
1390             DRM_MEM_DRIVER);
1391
1392         return (0);
1393 }
1394
1395 int
1396 i915_driver_unload(struct drm_device *dev)
1397 {
1398
1399         return (i915_driver_unload_int(dev, true));
1400 }
1401
1402 int
1403 i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1404 {
1405         struct drm_i915_file_private *i915_file_priv;
1406
1407         i915_file_priv = kmalloc(sizeof(*i915_file_priv), DRM_MEM_FILES,
1408             M_WAITOK | M_ZERO);
1409
1410         lockinit(&i915_file_priv->mm.lck, "915fp", 0, LK_CANRECURSE);
1411         INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
1412         file_priv->driver_priv = i915_file_priv;
1413
1414         return (0);
1415 }
1416
1417 void
1418 i915_driver_lastclose(struct drm_device * dev)
1419 {
1420         drm_i915_private_t *dev_priv = dev->dev_private;
1421
1422         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
1423 #if 1
1424                 KIB_NOTYET();
1425 #else
1426                 drm_fb_helper_restore();
1427                 vga_switcheroo_process_delayed_switch();
1428 #endif
1429                 return;
1430         }
1431         i915_gem_lastclose(dev);
1432         i915_dma_cleanup(dev);
1433 }
1434
1435 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1436 {
1437
1438         i915_gem_release(dev, file_priv);
1439 }
1440
1441 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
1442 {
1443         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1444
1445         lockuninit(&i915_file_priv->mm.lck);
1446         drm_free(i915_file_priv, sizeof(*i915_file_priv), DRM_MEM_FILES);
1447 }
1448
1449 struct drm_ioctl_desc i915_ioctls[] = {
1450         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1451         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1452         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1453         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1454         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1455         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1456         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1457         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1458         DRM_IOCTL_DEF(DRM_I915_ALLOC, drm_noop, DRM_AUTH),
1459         DRM_IOCTL_DEF(DRM_I915_FREE, drm_noop, DRM_AUTH),
1460         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1461         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1462         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1463         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1464         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
1465         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1466         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1467         DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1468         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH | DRM_UNLOCKED),
1469         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH | DRM_UNLOCKED),
1470         DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1471         DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1472         DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1473         DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
1474         DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1475         DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1476         DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
1477         DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1478         DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1479         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
1480         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1481         DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1482         DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1483         DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
1484         DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
1485         DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1486         DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1487         DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1488         DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1489         DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1490         DRM_IOCTL_DEF(DRM_I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1491         DRM_IOCTL_DEF(DRM_I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1492 };
1493
1494 struct drm_driver_info i915_driver_info = {
1495         .driver_features =   DRIVER_USE_AGP | DRIVER_REQUIRE_AGP |
1496             DRIVER_USE_MTRR | DRIVER_HAVE_IRQ | DRIVER_LOCKLESS_IRQ |
1497             DRIVER_GEM /*| DRIVER_MODESET*/,
1498
1499         .buf_priv_size  = sizeof(drm_i915_private_t),
1500         .load           = i915_driver_load,
1501         .open           = i915_driver_open,
1502         .unload         = i915_driver_unload,
1503         .preclose       = i915_driver_preclose,
1504         .lastclose      = i915_driver_lastclose,
1505         .postclose      = i915_driver_postclose,
1506         .device_is_agp  = i915_driver_device_is_agp,
1507         .gem_init_object = i915_gem_init_object,
1508         .gem_free_object = i915_gem_free_object,
1509         .gem_pager_ops  = &i915_gem_pager_ops,
1510         .dumb_create    = i915_gem_dumb_create,
1511         .dumb_map_offset = i915_gem_mmap_gtt,
1512         .dumb_destroy   = i915_gem_dumb_destroy,
1513         .sysctl_init    = i915_sysctl_init,
1514         .sysctl_cleanup = i915_sysctl_cleanup,
1515
1516         .ioctls         = i915_ioctls,
1517         .max_ioctl      = DRM_ARRAY_SIZE(i915_ioctls),
1518
1519         .name           = DRIVER_NAME,
1520         .desc           = DRIVER_DESC,
1521         .date           = DRIVER_DATE,
1522         .major          = DRIVER_MAJOR,
1523         .minor          = DRIVER_MINOR,
1524         .patchlevel     = DRIVER_PATCHLEVEL,
1525 };
1526
1527 /**
1528  * Determine if the device really is AGP or not.
1529  *
1530  * All Intel graphics chipsets are treated as AGP, even if they are really
1531  * built-in.
1532  *
1533  * \param dev   The device to be tested.
1534  *
1535  * \returns
1536  * A value of 1 is always retured to indictate every i9x5 is AGP.
1537  */
1538 int i915_driver_device_is_agp(struct drm_device * dev)
1539 {
1540         return 1;
1541 }
1542
1543 static void i915_pineview_get_mem_freq(struct drm_device *dev)
1544 {
1545         drm_i915_private_t *dev_priv = dev->dev_private;
1546         u32 tmp;
1547
1548         tmp = I915_READ(CLKCFG);
1549
1550         switch (tmp & CLKCFG_FSB_MASK) {
1551         case CLKCFG_FSB_533:
1552                 dev_priv->fsb_freq = 533; /* 133*4 */
1553                 break;
1554         case CLKCFG_FSB_800:
1555                 dev_priv->fsb_freq = 800; /* 200*4 */
1556                 break;
1557         case CLKCFG_FSB_667:
1558                 dev_priv->fsb_freq =  667; /* 167*4 */
1559                 break;
1560         case CLKCFG_FSB_400:
1561                 dev_priv->fsb_freq = 400; /* 100*4 */
1562                 break;
1563         }
1564
1565         switch (tmp & CLKCFG_MEM_MASK) {
1566         case CLKCFG_MEM_533:
1567                 dev_priv->mem_freq = 533;
1568                 break;
1569         case CLKCFG_MEM_667:
1570                 dev_priv->mem_freq = 667;
1571                 break;
1572         case CLKCFG_MEM_800:
1573                 dev_priv->mem_freq = 800;
1574                 break;
1575         }
1576
1577         /* detect pineview DDR3 setting */
1578         tmp = I915_READ(CSHRDDR3CTL);
1579         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
1580 }
1581
1582 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1583 {
1584         drm_i915_private_t *dev_priv = dev->dev_private;
1585         u16 ddrpll, csipll;
1586
1587         ddrpll = I915_READ16(DDRMPLL1);
1588         csipll = I915_READ16(CSIPLL0);
1589
1590         switch (ddrpll & 0xff) {
1591         case 0xc:
1592                 dev_priv->mem_freq = 800;
1593                 break;
1594         case 0x10:
1595                 dev_priv->mem_freq = 1066;
1596                 break;
1597         case 0x14:
1598                 dev_priv->mem_freq = 1333;
1599                 break;
1600         case 0x18:
1601                 dev_priv->mem_freq = 1600;
1602                 break;
1603         default:
1604                 DRM_DEBUG("unknown memory frequency 0x%02x\n",
1605                                  ddrpll & 0xff);
1606                 dev_priv->mem_freq = 0;
1607                 break;
1608         }
1609
1610         dev_priv->r_t = dev_priv->mem_freq;
1611
1612         switch (csipll & 0x3ff) {
1613         case 0x00c:
1614                 dev_priv->fsb_freq = 3200;
1615                 break;
1616         case 0x00e:
1617                 dev_priv->fsb_freq = 3733;
1618                 break;
1619         case 0x010:
1620                 dev_priv->fsb_freq = 4266;
1621                 break;
1622         case 0x012:
1623                 dev_priv->fsb_freq = 4800;
1624                 break;
1625         case 0x014:
1626                 dev_priv->fsb_freq = 5333;
1627                 break;
1628         case 0x016:
1629                 dev_priv->fsb_freq = 5866;
1630                 break;
1631         case 0x018:
1632                 dev_priv->fsb_freq = 6400;
1633                 break;
1634         default:
1635                 DRM_DEBUG("unknown fsb frequency 0x%04x\n",
1636                                  csipll & 0x3ff);
1637                 dev_priv->fsb_freq = 0;
1638                 break;
1639         }
1640
1641         if (dev_priv->fsb_freq == 3200) {
1642                 dev_priv->c_m = 0;
1643         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1644                 dev_priv->c_m = 1;
1645         } else {
1646                 dev_priv->c_m = 2;
1647         }
1648 }
1649
1650 static const struct cparams {
1651         u16 i;
1652         u16 t;
1653         u16 m;
1654         u16 c;
1655 } cparams[] = {
1656         { 1, 1333, 301, 28664 },
1657         { 1, 1066, 294, 24460 },
1658         { 1, 800, 294, 25192 },
1659         { 0, 1333, 276, 27605 },
1660         { 0, 1066, 276, 27605 },
1661         { 0, 800, 231, 23784 },
1662 };
1663
1664 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1665 {
1666         u64 total_count, diff, ret;
1667         u32 count1, count2, count3, m = 0, c = 0;
1668         unsigned long now = jiffies_to_msecs(jiffies), diff1;
1669         int i;
1670
1671         diff1 = now - dev_priv->last_time1;
1672         /*
1673          * sysctl(8) reads the value of sysctl twice in rapid
1674          * succession.  There is high chance that it happens in the
1675          * same timer tick.  Use the cached value to not divide by
1676          * zero and give the hw a chance to gather more samples.
1677          */
1678         if (diff1 <= 10)
1679                 return (dev_priv->chipset_power);
1680
1681         count1 = I915_READ(DMIEC);
1682         count2 = I915_READ(DDREC);
1683         count3 = I915_READ(CSIEC);
1684
1685         total_count = count1 + count2 + count3;
1686
1687         /* FIXME: handle per-counter overflow */
1688         if (total_count < dev_priv->last_count1) {
1689                 diff = ~0UL - dev_priv->last_count1;
1690                 diff += total_count;
1691         } else {
1692                 diff = total_count - dev_priv->last_count1;
1693         }
1694
1695         for (i = 0; i < DRM_ARRAY_SIZE(cparams); i++) {
1696                 if (cparams[i].i == dev_priv->c_m &&
1697                     cparams[i].t == dev_priv->r_t) {
1698                         m = cparams[i].m;
1699                         c = cparams[i].c;
1700                         break;
1701                 }
1702         }
1703
1704         diff = diff / diff1;
1705         ret = ((m * diff) + c);
1706         ret = ret / 10;
1707
1708         dev_priv->last_count1 = total_count;
1709         dev_priv->last_time1 = now;
1710
1711         dev_priv->chipset_power = ret;
1712         return (ret);
1713 }
1714
1715 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1716 {
1717         unsigned long m, x, b;
1718         u32 tsfs;
1719
1720         tsfs = I915_READ(TSFS);
1721
1722         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1723         x = I915_READ8(I915_TR1);
1724
1725         b = tsfs & TSFS_INTR_MASK;
1726
1727         return ((m * x) / 127) - b;
1728 }
1729
1730 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
1731 {
1732         static const struct v_table {
1733                 u16 vd; /* in .1 mil */
1734                 u16 vm; /* in .1 mil */
1735         } v_table[] = {
1736                 { 0, 0, },
1737                 { 375, 0, },
1738                 { 500, 0, },
1739                 { 625, 0, },
1740                 { 750, 0, },
1741                 { 875, 0, },
1742                 { 1000, 0, },
1743                 { 1125, 0, },
1744                 { 4125, 3000, },
1745                 { 4125, 3000, },
1746                 { 4125, 3000, },
1747                 { 4125, 3000, },
1748                 { 4125, 3000, },
1749                 { 4125, 3000, },
1750                 { 4125, 3000, },
1751                 { 4125, 3000, },
1752                 { 4125, 3000, },
1753                 { 4125, 3000, },
1754                 { 4125, 3000, },
1755                 { 4125, 3000, },
1756                 { 4125, 3000, },
1757                 { 4125, 3000, },
1758                 { 4125, 3000, },
1759                 { 4125, 3000, },
1760                 { 4125, 3000, },
1761                 { 4125, 3000, },
1762                 { 4125, 3000, },
1763                 { 4125, 3000, },
1764                 { 4125, 3000, },
1765                 { 4125, 3000, },
1766                 { 4125, 3000, },
1767                 { 4125, 3000, },
1768                 { 4250, 3125, },
1769                 { 4375, 3250, },
1770                 { 4500, 3375, },
1771                 { 4625, 3500, },
1772                 { 4750, 3625, },
1773                 { 4875, 3750, },
1774                 { 5000, 3875, },
1775                 { 5125, 4000, },
1776                 { 5250, 4125, },
1777                 { 5375, 4250, },
1778                 { 5500, 4375, },
1779                 { 5625, 4500, },
1780                 { 5750, 4625, },
1781                 { 5875, 4750, },
1782                 { 6000, 4875, },
1783                 { 6125, 5000, },
1784                 { 6250, 5125, },
1785                 { 6375, 5250, },
1786                 { 6500, 5375, },
1787                 { 6625, 5500, },
1788                 { 6750, 5625, },
1789                 { 6875, 5750, },
1790                 { 7000, 5875, },
1791                 { 7125, 6000, },
1792                 { 7250, 6125, },
1793                 { 7375, 6250, },
1794                 { 7500, 6375, },
1795                 { 7625, 6500, },
1796                 { 7750, 6625, },
1797                 { 7875, 6750, },
1798                 { 8000, 6875, },
1799                 { 8125, 7000, },
1800                 { 8250, 7125, },
1801                 { 8375, 7250, },
1802                 { 8500, 7375, },
1803                 { 8625, 7500, },
1804                 { 8750, 7625, },
1805                 { 8875, 7750, },
1806                 { 9000, 7875, },
1807                 { 9125, 8000, },
1808                 { 9250, 8125, },
1809                 { 9375, 8250, },
1810                 { 9500, 8375, },
1811                 { 9625, 8500, },
1812                 { 9750, 8625, },
1813                 { 9875, 8750, },
1814                 { 10000, 8875, },
1815                 { 10125, 9000, },
1816                 { 10250, 9125, },
1817                 { 10375, 9250, },
1818                 { 10500, 9375, },
1819                 { 10625, 9500, },
1820                 { 10750, 9625, },
1821                 { 10875, 9750, },
1822                 { 11000, 9875, },
1823                 { 11125, 10000, },
1824                 { 11250, 10125, },
1825                 { 11375, 10250, },
1826                 { 11500, 10375, },
1827                 { 11625, 10500, },
1828                 { 11750, 10625, },
1829                 { 11875, 10750, },
1830                 { 12000, 10875, },
1831                 { 12125, 11000, },
1832                 { 12250, 11125, },
1833                 { 12375, 11250, },
1834                 { 12500, 11375, },
1835                 { 12625, 11500, },
1836                 { 12750, 11625, },
1837                 { 12875, 11750, },
1838                 { 13000, 11875, },
1839                 { 13125, 12000, },
1840                 { 13250, 12125, },
1841                 { 13375, 12250, },
1842                 { 13500, 12375, },
1843                 { 13625, 12500, },
1844                 { 13750, 12625, },
1845                 { 13875, 12750, },
1846                 { 14000, 12875, },
1847                 { 14125, 13000, },
1848                 { 14250, 13125, },
1849                 { 14375, 13250, },
1850                 { 14500, 13375, },
1851                 { 14625, 13500, },
1852                 { 14750, 13625, },
1853                 { 14875, 13750, },
1854                 { 15000, 13875, },
1855                 { 15125, 14000, },
1856                 { 15250, 14125, },
1857                 { 15375, 14250, },
1858                 { 15500, 14375, },
1859                 { 15625, 14500, },
1860                 { 15750, 14625, },
1861                 { 15875, 14750, },
1862                 { 16000, 14875, },
1863                 { 16125, 15000, },
1864         };
1865         if (dev_priv->info->is_mobile)
1866                 return v_table[pxvid].vm;
1867         else
1868                 return v_table[pxvid].vd;
1869 }
1870
1871 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1872 {
1873         struct timespec now, diff1;
1874         u64 diff;
1875         unsigned long diffms;
1876         u32 count;
1877
1878         if (dev_priv->info->gen != 5)
1879                 return;
1880
1881         nanotime(&now);
1882         diff1 = now;
1883         timespecsub(&diff1, &dev_priv->last_time2);
1884
1885         /* Don't divide by 0 */
1886         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1887         if (!diffms)
1888                 return;
1889
1890         count = I915_READ(GFXEC);
1891
1892         if (count < dev_priv->last_count2) {
1893                 diff = ~0UL - dev_priv->last_count2;
1894                 diff += count;
1895         } else {
1896                 diff = count - dev_priv->last_count2;
1897         }
1898
1899         dev_priv->last_count2 = count;
1900         dev_priv->last_time2 = now;
1901
1902         /* More magic constants... */
1903         diff = diff * 1181;
1904         diff = diff / (diffms * 10);
1905         dev_priv->gfx_power = diff;
1906 }
1907
1908 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1909 {
1910         unsigned long t, corr, state1, corr2, state2;
1911         u32 pxvid, ext_v;
1912
1913         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1914         pxvid = (pxvid >> 24) & 0x7f;
1915         ext_v = pvid_to_extvid(dev_priv, pxvid);
1916
1917         state1 = ext_v;
1918
1919         t = i915_mch_val(dev_priv);
1920
1921         /* Revel in the empirically derived constants */
1922
1923         /* Correction factor in 1/100000 units */
1924         if (t > 80)
1925                 corr = ((t * 2349) + 135940);
1926         else if (t >= 50)
1927                 corr = ((t * 964) + 29317);
1928         else /* < 50 */
1929                 corr = ((t * 301) + 1004);
1930
1931         corr = corr * ((150142 * state1) / 10000 - 78642);
1932         corr /= 100000;
1933         corr2 = (corr * dev_priv->corr);
1934
1935         state2 = (corr2 * state1) / 10000;
1936         state2 /= 100; /* convert to mW */
1937
1938         i915_update_gfx_val(dev_priv);
1939
1940         return dev_priv->gfx_power + state2;
1941 }
1942
1943 /**
1944  * i915_read_mch_val - return value for IPS use
1945  *
1946  * Calculate and return a value for the IPS driver to use when deciding whether
1947  * we have thermal and power headroom to increase CPU or GPU power budget.
1948  */
1949 unsigned long i915_read_mch_val(void)
1950 {
1951         struct drm_i915_private *dev_priv;
1952         unsigned long chipset_val, graphics_val, ret = 0;
1953
1954         lockmgr(&mchdev_lock, LK_EXCLUSIVE);
1955         if (!i915_mch_dev)
1956                 goto out_unlock;
1957         dev_priv = i915_mch_dev;
1958
1959         chipset_val = i915_chipset_val(dev_priv);
1960         graphics_val = i915_gfx_val(dev_priv);
1961
1962         ret = chipset_val + graphics_val;
1963
1964 out_unlock:
1965         lockmgr(&mchdev_lock, LK_RELEASE);
1966
1967         return ret;
1968 }
1969
1970 /**
1971  * i915_gpu_raise - raise GPU frequency limit
1972  *
1973  * Raise the limit; IPS indicates we have thermal headroom.
1974  */
1975 bool i915_gpu_raise(void)
1976 {
1977         struct drm_i915_private *dev_priv;
1978         bool ret = true;
1979
1980         lockmgr(&mchdev_lock, LK_EXCLUSIVE);
1981         if (!i915_mch_dev) {
1982                 ret = false;
1983                 goto out_unlock;
1984         }
1985         dev_priv = i915_mch_dev;
1986
1987         if (dev_priv->max_delay > dev_priv->fmax)
1988                 dev_priv->max_delay--;
1989
1990 out_unlock:
1991         lockmgr(&mchdev_lock, LK_RELEASE);
1992
1993         return ret;
1994 }
1995
1996 /**
1997  * i915_gpu_lower - lower GPU frequency limit
1998  *
1999  * IPS indicates we're close to a thermal limit, so throttle back the GPU
2000  * frequency maximum.
2001  */
2002 bool i915_gpu_lower(void)
2003 {
2004         struct drm_i915_private *dev_priv;
2005         bool ret = true;
2006
2007         lockmgr(&mchdev_lock, LK_EXCLUSIVE);
2008         if (!i915_mch_dev) {
2009                 ret = false;
2010                 goto out_unlock;
2011         }
2012         dev_priv = i915_mch_dev;
2013
2014         if (dev_priv->max_delay < dev_priv->min_delay)
2015                 dev_priv->max_delay++;
2016
2017 out_unlock:
2018         lockmgr(&mchdev_lock, LK_RELEASE);
2019
2020         return ret;
2021 }
2022
2023 /**
2024  * i915_gpu_busy - indicate GPU business to IPS
2025  *
2026  * Tell the IPS driver whether or not the GPU is busy.
2027  */
2028 bool i915_gpu_busy(void)
2029 {
2030         struct drm_i915_private *dev_priv;
2031         bool ret = false;
2032
2033         lockmgr(&mchdev_lock, LK_EXCLUSIVE);
2034         if (!i915_mch_dev)
2035                 goto out_unlock;
2036         dev_priv = i915_mch_dev;
2037
2038         ret = dev_priv->busy;
2039
2040 out_unlock:
2041         lockmgr(&mchdev_lock, LK_RELEASE);
2042
2043         return ret;
2044 }
2045
2046 /**
2047  * i915_gpu_turbo_disable - disable graphics turbo
2048  *
2049  * Disable graphics turbo by resetting the max frequency and setting the
2050  * current frequency to the default.
2051  */
2052 bool i915_gpu_turbo_disable(void)
2053 {
2054         struct drm_i915_private *dev_priv;
2055         bool ret = true;
2056
2057         lockmgr(&mchdev_lock, LK_EXCLUSIVE);
2058         if (!i915_mch_dev) {
2059                 ret = false;
2060                 goto out_unlock;
2061         }
2062         dev_priv = i915_mch_dev;
2063
2064         dev_priv->max_delay = dev_priv->fstart;
2065
2066         if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
2067                 ret = false;
2068
2069 out_unlock:
2070         lockmgr(&mchdev_lock, LK_RELEASE);
2071
2072         return ret;
2073 }