2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2008,2010 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 * Eric Anholt <eric@anholt.net>
27 * Chris Wilson <chris@chris-wilson.co.uk>
29 * Copyright (c) 2011 The FreeBSD Foundation
30 * All rights reserved.
32 * This software was developed by Konstantin Belousov under sponsorship from
33 * the FreeBSD Foundation.
35 * Redistribution and use in source and binary forms, with or without
36 * modification, are permitted provided that the following conditions
38 * 1. Redistributions of source code must retain the above copyright
39 * notice, this list of conditions and the following disclaimer.
40 * 2. Redistributions in binary form must reproduce the above copyright
41 * notice, this list of conditions and the following disclaimer in the
42 * documentation and/or other materials provided with the distribution.
44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
45 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
46 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
47 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
48 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
49 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
50 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
51 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
56 * $FreeBSD: src/sys/dev/drm2/i915/intel_iic.c,v 1.1 2012/05/22 11:07:44 kib Exp $
59 #include <sys/mplock2.h>
61 #include <dev/drm2/drmP.h>
62 #include <dev/drm2/drm.h>
63 #include <dev/drm2/i915/i915_drm.h>
64 #include <dev/drm2/i915/i915_drv.h>
65 #include <dev/drm2/i915/intel_drv.h>
66 #include <dev/iicbus/iic.h>
67 #include <dev/iicbus/iiconf.h>
68 #include <dev/iicbus/iicbus.h>
69 #include "iicbus_if.h"
72 static int intel_iic_quirk_xfer(device_t idev, struct iic_msg *msgs, int nmsgs);
73 static void intel_teardown_gmbus_m(struct drm_device *dev, int m);
75 /* Intel GPIO access functions */
77 #define I2C_RISEFALL_TIME 10
79 struct intel_iic_softc {
80 struct drm_device *drm_dev;
89 intel_iic_quirk_set(struct drm_i915_private *dev_priv, bool enable)
93 /* When using bit bashing for I2C, this bit needs to be set to 1 */
94 if (!IS_PINEVIEW(dev_priv->dev))
97 val = I915_READ(DSPCLK_GATE_D);
99 val |= DPCUNIT_CLOCK_GATE_DISABLE;
101 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
102 I915_WRITE(DSPCLK_GATE_D, val);
106 intel_iic_get_reserved(device_t idev)
108 struct intel_iic_softc *sc;
109 struct drm_device *dev;
110 struct drm_i915_private *dev_priv;
113 sc = device_get_softc(idev);
115 dev_priv = dev->dev_private;
117 if (!IS_I830(dev) && !IS_845G(dev)) {
118 reserved = I915_READ_NOTRACE(sc->reg) &
119 (GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE);
128 intel_iic_reset(struct drm_device *dev)
130 struct drm_i915_private *dev_priv;
132 dev_priv = dev->dev_private;
133 if (HAS_PCH_SPLIT(dev))
134 I915_WRITE(PCH_GMBUS0, 0);
136 I915_WRITE(GMBUS0, 0);
140 intel_iicbus_reset(device_t idev, u_char speed, u_char addr, u_char *oldaddr)
142 struct intel_iic_softc *sc;
143 struct drm_device *dev;
145 sc = device_get_softc(idev);
148 intel_iic_reset(dev);
153 intel_iicbb_setsda(device_t idev, int val)
155 struct intel_iic_softc *sc;
156 struct drm_i915_private *dev_priv;
160 sc = device_get_softc(idev);
161 dev_priv = sc->drm_dev->dev_private;
163 reserved = intel_iic_get_reserved(idev);
165 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
167 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
170 I915_WRITE_NOTRACE(sc->reg, reserved | data_bits);
171 POSTING_READ(sc->reg);
175 intel_iicbb_setscl(device_t idev, int val)
177 struct intel_iic_softc *sc;
178 struct drm_i915_private *dev_priv;
179 u32 clock_bits, reserved;
181 sc = device_get_softc(idev);
182 dev_priv = sc->drm_dev->dev_private;
184 reserved = intel_iic_get_reserved(idev);
186 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
188 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
191 I915_WRITE_NOTRACE(sc->reg, reserved | clock_bits);
192 POSTING_READ(sc->reg);
196 intel_iicbb_getsda(device_t idev)
198 struct intel_iic_softc *sc;
199 struct drm_i915_private *dev_priv;
202 sc = device_get_softc(idev);
203 dev_priv = sc->drm_dev->dev_private;
205 reserved = intel_iic_get_reserved(idev);
207 I915_WRITE_NOTRACE(sc->reg, reserved | GPIO_DATA_DIR_MASK);
208 I915_WRITE_NOTRACE(sc->reg, reserved);
209 return ((I915_READ_NOTRACE(sc->reg) & GPIO_DATA_VAL_IN) != 0);
213 intel_iicbb_getscl(device_t idev)
215 struct intel_iic_softc *sc;
216 struct drm_i915_private *dev_priv;
219 sc = device_get_softc(idev);
220 dev_priv = sc->drm_dev->dev_private;
222 reserved = intel_iic_get_reserved(idev);
224 I915_WRITE_NOTRACE(sc->reg, reserved | GPIO_CLOCK_DIR_MASK);
225 I915_WRITE_NOTRACE(sc->reg, reserved);
226 return ((I915_READ_NOTRACE(sc->reg) & GPIO_CLOCK_VAL_IN) != 0);
230 intel_gmbus_transfer(device_t idev, struct iic_msg *msgs, uint32_t nmsgs)
232 struct intel_iic_softc *sc;
233 struct drm_i915_private *dev_priv;
235 int error, i, reg_offset, unit;
239 sc = device_get_softc(idev);
240 dev_priv = sc->drm_dev->dev_private;
241 unit = device_get_unit(idev);
243 lockmgr(&dev_priv->gmbus_lock, LK_EXCLUSIVE);
244 if (sc->force_bit_dev) {
245 error = intel_iic_quirk_xfer(dev_priv->bbbus[unit], msgs, nmsgs);
249 reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0;
251 I915_WRITE(GMBUS0 + reg_offset, sc->reg0);
253 for (i = 0; i < nmsgs; i++) {
257 if ((msgs[i].flags & IIC_M_RD) != 0) {
258 I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_WAIT |
259 (i + 1 == nmsgs ? GMBUS_CYCLE_STOP : 0) |
260 (len << GMBUS_BYTE_COUNT_SHIFT) |
261 (msgs[i].slave << GMBUS_SLAVE_ADDR_SHIFT) |
262 GMBUS_SLAVE_READ | GMBUS_SW_RDY);
263 POSTING_READ(GMBUS2 + reg_offset);
267 if (_intel_wait_for(sc->drm_dev,
268 (I915_READ(GMBUS2 + reg_offset) &
269 (GMBUS_SATOER | GMBUS_HW_RDY)) != 0,
272 if ((I915_READ(GMBUS2 + reg_offset) &
276 val = I915_READ(GMBUS3 + reg_offset);
280 } while (--len != 0 && ++loop < 4);
285 val |= *buf++ << (8 * loop);
286 } while (--len != 0 && ++loop < 4);
288 I915_WRITE(GMBUS3 + reg_offset, val);
289 I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_WAIT |
290 (i + 1 == nmsgs ? GMBUS_CYCLE_STOP : 0) |
291 (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) |
292 (msgs[i].slave << GMBUS_SLAVE_ADDR_SHIFT) |
293 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
294 POSTING_READ(GMBUS2+reg_offset);
297 if (_intel_wait_for(sc->drm_dev,
298 (I915_READ(GMBUS2 + reg_offset) &
299 (GMBUS_SATOER | GMBUS_HW_RDY)) != 0,
302 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
307 val |= *buf++ << (8 * loop);
308 } while (--len != 0 && ++loop < 4);
310 I915_WRITE(GMBUS3 + reg_offset, val);
311 POSTING_READ(GMBUS2 + reg_offset);
315 if (i + 1 < nmsgs && _intel_wait_for(sc->drm_dev,
316 (I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER |
317 GMBUS_HW_WAIT_PHASE)) != 0,
320 if ((I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) != 0)
326 /* Mark the GMBUS interface as disabled after waiting for idle.
327 * We will re-enable it at the start of the next xfer,
328 * till then let it sleep.
330 if (_intel_wait_for(dev,
331 (I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0,
333 DRM_INFO("GMBUS timed out waiting for idle\n");
334 I915_WRITE(GMBUS0 + reg_offset, 0);
336 lockmgr(&dev_priv->gmbus_lock, LK_RELEASE);
340 /* Toggle the Software Clear Interrupt bit. This has the effect
341 * of resetting the GMBUS controller and so clearing the
342 * BUS_ERROR raised by the slave's NAK.
344 I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
345 I915_WRITE(GMBUS1 + reg_offset, 0);
350 DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
351 sc->reg0 & 0xff, sc->name);
352 I915_WRITE(GMBUS0 + reg_offset, 0);
355 * Hardware may not support GMBUS over these pins?
356 * Try GPIO bitbanging instead.
358 sc->force_bit_dev = true;
360 error = intel_iic_quirk_xfer(dev_priv->bbbus[unit], msgs, nmsgs);
365 intel_gmbus_set_speed(device_t idev, int speed)
367 struct intel_iic_softc *sc;
369 sc = device_get_softc(device_get_parent(idev));
371 sc->reg0 = (sc->reg0 & ~(0x3 << 8)) | speed;
375 intel_gmbus_force_bit(device_t idev, bool force_bit)
377 struct intel_iic_softc *sc;
379 sc = device_get_softc(device_get_parent(idev));
380 sc->force_bit_dev = force_bit;
384 intel_iic_quirk_xfer(device_t idev, struct iic_msg *msgs, int nmsgs)
387 struct intel_iic_softc *sc;
388 struct drm_i915_private *dev_priv;
392 bridge_dev = device_get_parent(device_get_parent(idev));
393 sc = device_get_softc(bridge_dev);
394 dev_priv = sc->drm_dev->dev_private;
396 intel_iic_reset(sc->drm_dev);
397 intel_iic_quirk_set(dev_priv, true);
398 IICBB_SETSDA(bridge_dev, 1);
399 IICBB_SETSCL(bridge_dev, 1);
400 DELAY(I2C_RISEFALL_TIME);
402 /* convert slave addresses to format expected by iicbb */
403 for (i = 0; i < nmsgs; i++) {
405 /* force use of repeated start instead of default stop+start */
406 if (i != (nmsgs - 1))
407 msgs[i].flags |= IIC_M_NOSTOP;
409 ret = iicbus_transfer(idev, msgs, nmsgs);
410 /* restore the addresses */
411 for (i = 0; i < nmsgs; i++)
413 IICBB_SETSDA(bridge_dev, 1);
414 IICBB_SETSCL(bridge_dev, 1);
415 intel_iic_quirk_set(dev_priv, false);
420 static const char *gpio_names[GMBUS_NUM_PORTS] = {
432 intel_gmbus_probe(device_t dev)
435 return (BUS_PROBE_SPECIFIC);
439 intel_gmbus_attach(device_t idev)
441 struct drm_i915_private *dev_priv;
442 struct intel_iic_softc *sc;
445 sc = device_get_softc(idev);
446 sc->drm_dev = device_get_softc(device_get_parent(idev));
447 dev_priv = sc->drm_dev->dev_private;
448 pin = device_get_unit(idev);
450 ksnprintf(sc->name, sizeof(sc->name), "gmbus bus %s", gpio_names[pin]);
451 device_set_desc(idev, sc->name);
453 /* By default use a conservative clock rate */
454 sc->reg0 = pin | GMBUS_RATE_100KHZ;
456 /* XXX force bit banging until GMBUS is fully debugged */
457 if (IS_GEN2(sc->drm_dev)) {
458 sc->force_bit_dev = true;
461 /* add bus interface device */
462 sc->iic_dev = device_add_child(idev, "iicbus", -1);
463 if (sc->iic_dev == NULL)
465 device_quiet(sc->iic_dev);
466 bus_generic_attach(idev);
472 intel_gmbus_detach(device_t idev)
474 struct intel_iic_softc *sc;
475 struct drm_i915_private *dev_priv;
479 sc = device_get_softc(idev);
480 u = device_get_unit(idev);
481 dev_priv = sc->drm_dev->dev_private;
484 bus_generic_detach(idev);
486 device_delete_child(idev, child);
492 intel_iicbb_probe(device_t dev)
495 return (BUS_PROBE_DEFAULT);
499 intel_iicbb_attach(device_t idev)
501 static const int map_pin_to_reg[] = {
512 struct intel_iic_softc *sc;
513 struct drm_i915_private *dev_priv;
516 sc = device_get_softc(idev);
517 sc->drm_dev = device_get_softc(device_get_parent(idev));
518 dev_priv = sc->drm_dev->dev_private;
519 pin = device_get_unit(idev);
521 ksnprintf(sc->name, sizeof(sc->name), "i915 iicbb %s", gpio_names[pin]);
522 device_set_desc(idev, sc->name);
524 sc->reg0 = pin | GMBUS_RATE_100KHZ;
525 sc->reg = map_pin_to_reg[pin];
526 if (HAS_PCH_SPLIT(dev_priv->dev))
527 sc->reg += PCH_GPIOA - GPIOA;
529 /* add generic bit-banging code */
530 sc->iic_dev = device_add_child(idev, "iicbb", -1);
531 if (sc->iic_dev == NULL)
533 device_quiet(sc->iic_dev);
534 bus_generic_attach(idev);
540 intel_iicbb_detach(device_t idev)
542 struct intel_iic_softc *sc;
545 sc = device_get_softc(idev);
547 bus_generic_detach(idev);
549 device_delete_child(idev, child);
553 static device_method_t intel_gmbus_methods[] = {
554 DEVMETHOD(device_probe, intel_gmbus_probe),
555 DEVMETHOD(device_attach, intel_gmbus_attach),
556 DEVMETHOD(device_detach, intel_gmbus_detach),
557 DEVMETHOD(iicbus_reset, intel_iicbus_reset),
558 DEVMETHOD(iicbus_transfer, intel_gmbus_transfer),
561 static driver_t intel_gmbus_driver = {
564 sizeof(struct intel_iic_softc)
566 static devclass_t intel_gmbus_devclass;
567 DRIVER_MODULE_ORDERED(intel_gmbus, drmn, intel_gmbus_driver,
568 intel_gmbus_devclass, 0, 0, SI_ORDER_FIRST);
569 DRIVER_MODULE(iicbus, intel_gmbus, iicbus_driver, iicbus_devclass, 0, 0);
571 static device_method_t intel_iicbb_methods[] = {
572 DEVMETHOD(device_probe, intel_iicbb_probe),
573 DEVMETHOD(device_attach, intel_iicbb_attach),
574 DEVMETHOD(device_detach, intel_iicbb_detach),
576 DEVMETHOD(bus_add_child, bus_generic_add_child),
577 DEVMETHOD(bus_print_child, bus_generic_print_child),
579 DEVMETHOD(iicbb_callback, iicbus_null_callback),
580 DEVMETHOD(iicbb_reset, intel_iicbus_reset),
581 DEVMETHOD(iicbb_setsda, intel_iicbb_setsda),
582 DEVMETHOD(iicbb_setscl, intel_iicbb_setscl),
583 DEVMETHOD(iicbb_getsda, intel_iicbb_getsda),
584 DEVMETHOD(iicbb_getscl, intel_iicbb_getscl),
587 static driver_t intel_iicbb_driver = {
590 sizeof(struct intel_iic_softc)
592 static devclass_t intel_iicbb_devclass;
593 DRIVER_MODULE_ORDERED(intel_iicbb, drmn, intel_iicbb_driver,
594 intel_iicbb_devclass, 0, 0, SI_ORDER_FIRST);
595 DRIVER_MODULE(iicbb, intel_iicbb, iicbb_driver, iicbb_devclass, 0, 0);
598 intel_setup_gmbus(struct drm_device *dev)
600 struct drm_i915_private *dev_priv;
604 dev_priv = dev->dev_private;
605 lockinit(&dev_priv->gmbus_lock, "gmbus", 0, LK_CANRECURSE);
606 dev_priv->gmbus_bridge = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS,
607 DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
608 dev_priv->bbbus_bridge = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS,
609 DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
610 dev_priv->gmbus = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS,
611 DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
612 dev_priv->bbbus = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS,
613 DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
616 * The Giant there is recursed, most likely. Normally, the
617 * intel_setup_gmbus() is called from the attach method of the
621 for (i = 0; i < GMBUS_NUM_PORTS; i++) {
623 * Initialized bbbus_bridge before gmbus_bridge, since
624 * gmbus may decide to force quirk transfer in the
627 dev_priv->bbbus_bridge[i] = device_add_child(dev->device,
629 if (dev_priv->bbbus_bridge[i] == NULL) {
630 DRM_ERROR("bbbus bridge %d creation failed\n", i);
634 device_quiet(dev_priv->bbbus_bridge[i]);
635 ret = device_probe_and_attach(dev_priv->bbbus_bridge[i]);
637 DRM_ERROR("bbbus bridge %d attach failed, %d\n", i,
642 iic_dev = device_find_child(dev_priv->bbbus_bridge[i], "iicbb",
644 if (iic_dev == NULL) {
645 DRM_ERROR("bbbus bridge doesn't have iicbb child\n");
648 iic_dev = device_find_child(iic_dev, "iicbus", -1);
649 if (iic_dev == NULL) {
651 "bbbus bridge doesn't have iicbus grandchild\n");
655 dev_priv->bbbus[i] = iic_dev;
657 dev_priv->gmbus_bridge[i] = device_add_child(dev->device,
659 if (dev_priv->gmbus_bridge[i] == NULL) {
660 DRM_ERROR("gmbus bridge %d creation failed\n", i);
664 device_quiet(dev_priv->gmbus_bridge[i]);
665 ret = device_probe_and_attach(dev_priv->gmbus_bridge[i]);
667 DRM_ERROR("gmbus bridge %d attach failed, %d\n", i,
673 iic_dev = device_find_child(dev_priv->gmbus_bridge[i],
675 if (iic_dev == NULL) {
676 DRM_ERROR("gmbus bridge doesn't have iicbus child\n");
679 dev_priv->gmbus[i] = iic_dev;
681 intel_iic_reset(dev);
688 intel_teardown_gmbus_m(dev, i);
694 intel_teardown_gmbus_m(struct drm_device *dev, int m)
696 struct drm_i915_private *dev_priv;
698 dev_priv = dev->dev_private;
700 kfree(dev_priv->gmbus, DRM_MEM_DRIVER);
701 dev_priv->gmbus = NULL;
702 kfree(dev_priv->bbbus, DRM_MEM_DRIVER);
703 dev_priv->bbbus = NULL;
704 kfree(dev_priv->gmbus_bridge, DRM_MEM_DRIVER);
705 dev_priv->gmbus_bridge = NULL;
706 kfree(dev_priv->bbbus_bridge, DRM_MEM_DRIVER);
707 dev_priv->bbbus_bridge = NULL;
708 lockuninit(&dev_priv->gmbus_lock);
712 intel_teardown_gmbus(struct drm_device *dev)
716 intel_teardown_gmbus_m(dev, GMBUS_NUM_PORTS);