drm2: Handle locking
[dragonfly.git] / sys / dev / drm2 / i915 / intel_iic.c
1 /*
2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3  * Copyright © 2006-2008,2010 Intel Corporation
4  *   Jesse Barnes <jesse.barnes@intel.com>
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the next
14  * paragraph) shall be included in all copies or substantial portions of the
15  * Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23  * DEALINGS IN THE SOFTWARE.
24  *
25  * Authors:
26  *      Eric Anholt <eric@anholt.net>
27  *      Chris Wilson <chris@chris-wilson.co.uk>
28  *
29  * Copyright (c) 2011 The FreeBSD Foundation
30  * All rights reserved.
31  *
32  * This software was developed by Konstantin Belousov under sponsorship from
33  * the FreeBSD Foundation.
34  *
35  * Redistribution and use in source and binary forms, with or without
36  * modification, are permitted provided that the following conditions
37  * are met:
38  * 1. Redistributions of source code must retain the above copyright
39  *    notice, this list of conditions and the following disclaimer.
40  * 2. Redistributions in binary form must reproduce the above copyright
41  *    notice, this list of conditions and the following disclaimer in the
42  *    documentation and/or other materials provided with the distribution.
43  *
44  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
45  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
46  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
47  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
48  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
49  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
50  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
51  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
52  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
53  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
54  * SUCH DAMAGE.
55  *
56  * $FreeBSD: src/sys/dev/drm2/i915/intel_iic.c,v 1.1 2012/05/22 11:07:44 kib Exp $
57  */
58
59 #include <sys/mplock2.h>
60
61 #include <dev/drm2/drmP.h>
62 #include <dev/drm2/drm.h>
63 #include <dev/drm2/i915/i915_drm.h>
64 #include <dev/drm2/i915/i915_drv.h>
65 #include <dev/drm2/i915/intel_drv.h>
66 #include <dev/iicbus/iic.h>
67 #include <dev/iicbus/iiconf.h>
68 #include <dev/iicbus/iicbus.h>
69 #include "iicbus_if.h"
70 #include "iicbb_if.h"
71
72 static int intel_iic_quirk_xfer(device_t idev, struct iic_msg *msgs, int nmsgs);
73 static void intel_teardown_gmbus_m(struct drm_device *dev, int m);
74
75 /* Intel GPIO access functions */
76
77 #define I2C_RISEFALL_TIME 10
78
79 struct intel_iic_softc {
80         struct drm_device *drm_dev;
81         device_t iic_dev;
82         bool force_bit_dev;
83         char name[32];
84         uint32_t reg;
85         uint32_t reg0;
86 };
87
88 static void
89 intel_iic_quirk_set(struct drm_i915_private *dev_priv, bool enable)
90 {
91         u32 val;
92
93         /* When using bit bashing for I2C, this bit needs to be set to 1 */
94         if (!IS_PINEVIEW(dev_priv->dev))
95                 return;
96
97         val = I915_READ(DSPCLK_GATE_D);
98         if (enable)
99                 val |= DPCUNIT_CLOCK_GATE_DISABLE;
100         else
101                 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
102         I915_WRITE(DSPCLK_GATE_D, val);
103 }
104
105 static u32
106 intel_iic_get_reserved(device_t idev)
107 {
108         struct intel_iic_softc *sc;
109         struct drm_device *dev;
110         struct drm_i915_private *dev_priv;
111         u32 reserved;
112
113         sc = device_get_softc(idev);
114         dev = sc->drm_dev;
115         dev_priv = dev->dev_private;
116
117         if (!IS_I830(dev) && !IS_845G(dev)) {
118                 reserved = I915_READ_NOTRACE(sc->reg) &
119                     (GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE);
120         } else {
121                 reserved = 0;
122         }
123
124         return (reserved);
125 }
126
127 void
128 intel_iic_reset(struct drm_device *dev)
129 {
130         struct drm_i915_private *dev_priv;
131
132         dev_priv = dev->dev_private;
133         if (HAS_PCH_SPLIT(dev))
134                 I915_WRITE(PCH_GMBUS0, 0);
135         else
136                 I915_WRITE(GMBUS0, 0);
137 }
138
139 static int
140 intel_iicbus_reset(device_t idev, u_char speed, u_char addr, u_char *oldaddr)
141 {
142         struct intel_iic_softc *sc;
143         struct drm_device *dev;
144
145         sc = device_get_softc(idev);
146         dev = sc->drm_dev;
147
148         intel_iic_reset(dev);
149         return (0);
150 }
151
152 static void
153 intel_iicbb_setsda(device_t idev, int val)
154 {
155         struct intel_iic_softc *sc;
156         struct drm_i915_private *dev_priv;
157         u32 reserved;
158         u32 data_bits;
159
160         sc = device_get_softc(idev);
161         dev_priv = sc->drm_dev->dev_private;
162
163         reserved = intel_iic_get_reserved(idev);
164         if (val)
165                 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
166         else
167                 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
168                     GPIO_DATA_VAL_MASK;
169
170         I915_WRITE_NOTRACE(sc->reg, reserved | data_bits);
171         POSTING_READ(sc->reg);
172 }
173
174 static void
175 intel_iicbb_setscl(device_t idev, int val)
176 {
177         struct intel_iic_softc *sc;
178         struct drm_i915_private *dev_priv;
179         u32 clock_bits, reserved;
180
181         sc = device_get_softc(idev);
182         dev_priv = sc->drm_dev->dev_private;
183
184         reserved = intel_iic_get_reserved(idev);
185         if (val)
186                 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
187         else
188                 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
189                     GPIO_CLOCK_VAL_MASK;
190
191         I915_WRITE_NOTRACE(sc->reg, reserved | clock_bits);
192         POSTING_READ(sc->reg);
193 }
194
195 static int
196 intel_iicbb_getsda(device_t idev)
197 {
198         struct intel_iic_softc *sc;
199         struct drm_i915_private *dev_priv;
200         u32 reserved;
201
202         sc = device_get_softc(idev);
203         dev_priv = sc->drm_dev->dev_private;
204
205         reserved = intel_iic_get_reserved(idev);
206
207         I915_WRITE_NOTRACE(sc->reg, reserved | GPIO_DATA_DIR_MASK);
208         I915_WRITE_NOTRACE(sc->reg, reserved);
209         return ((I915_READ_NOTRACE(sc->reg) & GPIO_DATA_VAL_IN) != 0);
210 }
211
212 static int
213 intel_iicbb_getscl(device_t idev)
214 {
215         struct intel_iic_softc *sc;
216         struct drm_i915_private *dev_priv;
217         u32 reserved;
218
219         sc = device_get_softc(idev);
220         dev_priv = sc->drm_dev->dev_private;
221
222         reserved = intel_iic_get_reserved(idev);
223
224         I915_WRITE_NOTRACE(sc->reg, reserved | GPIO_CLOCK_DIR_MASK);
225         I915_WRITE_NOTRACE(sc->reg, reserved);
226         return ((I915_READ_NOTRACE(sc->reg) & GPIO_CLOCK_VAL_IN) != 0);
227 }
228
229 static int
230 intel_gmbus_transfer(device_t idev, struct iic_msg *msgs, uint32_t nmsgs)
231 {
232         struct intel_iic_softc *sc;
233         struct drm_i915_private *dev_priv;
234         u8 *buf;
235         int error, i, reg_offset, unit;
236         u32 val, loop;
237         u16 len;
238
239         sc = device_get_softc(idev);
240         dev_priv = sc->drm_dev->dev_private;
241         unit = device_get_unit(idev);
242
243         lockmgr(&dev_priv->gmbus_lock, LK_EXCLUSIVE);
244         if (sc->force_bit_dev) {
245                 error = intel_iic_quirk_xfer(dev_priv->bbbus[unit], msgs, nmsgs);
246                 goto out;
247         }
248
249         reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0;
250
251         I915_WRITE(GMBUS0 + reg_offset, sc->reg0);
252
253         for (i = 0; i < nmsgs; i++) {
254                 len = msgs[i].len;
255                 buf = msgs[i].buf;
256
257                 if ((msgs[i].flags & IIC_M_RD) != 0) {
258                         I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_WAIT |
259                             (i + 1 == nmsgs ? GMBUS_CYCLE_STOP : 0) |
260                             (len << GMBUS_BYTE_COUNT_SHIFT) |
261                             (msgs[i].slave << GMBUS_SLAVE_ADDR_SHIFT) |
262                             GMBUS_SLAVE_READ | GMBUS_SW_RDY);
263                         POSTING_READ(GMBUS2 + reg_offset);
264                         do {
265                                 loop = 0;
266
267                                 if (_intel_wait_for(sc->drm_dev,
268                                     (I915_READ(GMBUS2 + reg_offset) &
269                                         (GMBUS_SATOER | GMBUS_HW_RDY)) != 0,
270                                     50, 1, "915gbr"))
271                                         goto timeout;
272                                 if ((I915_READ(GMBUS2 + reg_offset) &
273                                     GMBUS_SATOER) != 0)
274                                         goto clear_err;
275
276                                 val = I915_READ(GMBUS3 + reg_offset);
277                                 do {
278                                         *buf++ = val & 0xff;
279                                         val >>= 8;
280                                 } while (--len != 0 && ++loop < 4);
281                         } while (len != 0);
282                 } else {
283                         val = loop = 0;
284                         do {
285                                 val |= *buf++ << (8 * loop);
286                         } while (--len != 0 && ++loop < 4);
287
288                         I915_WRITE(GMBUS3 + reg_offset, val);
289                         I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_WAIT |
290                             (i + 1 == nmsgs ? GMBUS_CYCLE_STOP : 0) |
291                             (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) |
292                             (msgs[i].slave << GMBUS_SLAVE_ADDR_SHIFT) |
293                             GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
294                         POSTING_READ(GMBUS2+reg_offset);
295
296                         while (len != 0) {
297                                 if (_intel_wait_for(sc->drm_dev,
298                                     (I915_READ(GMBUS2 + reg_offset) &
299                                         (GMBUS_SATOER | GMBUS_HW_RDY)) != 0,
300                                     50, 1, "915gbw"))
301                                         goto timeout;
302                                 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
303                                         goto clear_err;
304
305                                 val = loop = 0;
306                                 do {
307                                         val |= *buf++ << (8 * loop);
308                                 } while (--len != 0 && ++loop < 4);
309
310                                 I915_WRITE(GMBUS3 + reg_offset, val);
311                                 POSTING_READ(GMBUS2 + reg_offset);
312                         }
313                 }
314
315                 if (i + 1 < nmsgs && _intel_wait_for(sc->drm_dev,
316                     (I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER |
317                         GMBUS_HW_WAIT_PHASE)) != 0,
318                     50, 1, "915gbh"))
319                         goto timeout;
320                 if ((I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) != 0)
321                         goto clear_err;
322         }
323
324         error = 0;
325 done:
326         /* Mark the GMBUS interface as disabled after waiting for idle.
327          * We will re-enable it at the start of the next xfer,
328          * till then let it sleep.
329          */
330         if (_intel_wait_for(dev,
331             (I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0,
332             10, 1, "915gbu"))
333                 DRM_INFO("GMBUS timed out waiting for idle\n");
334         I915_WRITE(GMBUS0 + reg_offset, 0);
335 out:
336         lockmgr(&dev_priv->gmbus_lock, LK_RELEASE);
337         return (error);
338
339 clear_err:
340         /* Toggle the Software Clear Interrupt bit. This has the effect
341          * of resetting the GMBUS controller and so clearing the
342          * BUS_ERROR raised by the slave's NAK.
343          */
344         I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
345         I915_WRITE(GMBUS1 + reg_offset, 0);
346         error = EIO;
347         goto done;
348
349 timeout:
350         DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
351             sc->reg0 & 0xff, sc->name);
352         I915_WRITE(GMBUS0 + reg_offset, 0);
353
354         /*
355          * Hardware may not support GMBUS over these pins?
356          * Try GPIO bitbanging instead.
357          */
358         sc->force_bit_dev = true;
359
360         error = intel_iic_quirk_xfer(dev_priv->bbbus[unit], msgs, nmsgs);
361         goto out;
362 }
363
364 void
365 intel_gmbus_set_speed(device_t idev, int speed)
366 {
367         struct intel_iic_softc *sc;
368
369         sc = device_get_softc(device_get_parent(idev));
370
371         sc->reg0 = (sc->reg0 & ~(0x3 << 8)) | speed;
372 }
373
374 void
375 intel_gmbus_force_bit(device_t idev, bool force_bit)
376 {
377         struct intel_iic_softc *sc;
378
379         sc = device_get_softc(device_get_parent(idev));
380         sc->force_bit_dev = force_bit;
381 }
382
383 static int
384 intel_iic_quirk_xfer(device_t idev, struct iic_msg *msgs, int nmsgs)
385 {
386         device_t bridge_dev;
387         struct intel_iic_softc *sc;
388         struct drm_i915_private *dev_priv;
389         int ret;
390         int i;
391
392         bridge_dev = device_get_parent(device_get_parent(idev));
393         sc = device_get_softc(bridge_dev);
394         dev_priv = sc->drm_dev->dev_private;
395
396         intel_iic_reset(sc->drm_dev);
397         intel_iic_quirk_set(dev_priv, true);
398         IICBB_SETSDA(bridge_dev, 1);
399         IICBB_SETSCL(bridge_dev, 1);
400         DELAY(I2C_RISEFALL_TIME);
401
402         /* convert slave addresses to format expected by iicbb */
403         for (i = 0; i < nmsgs; i++) {
404                 msgs[i].slave <<= 1;
405                 /* force use of repeated start instead of default stop+start */
406                 if (i != (nmsgs - 1))
407                          msgs[i].flags |= IIC_M_NOSTOP;
408         }
409         ret = iicbus_transfer(idev, msgs, nmsgs);
410         /* restore the addresses */
411         for (i = 0; i < nmsgs; i++)
412                 msgs[i].slave >>= 1;
413         IICBB_SETSDA(bridge_dev, 1);
414         IICBB_SETSCL(bridge_dev, 1);
415         intel_iic_quirk_set(dev_priv, false);
416
417         return (ret);
418 }
419
420 static const char *gpio_names[GMBUS_NUM_PORTS] = {
421         "disabled",
422         "ssc",
423         "vga",
424         "panel",
425         "dpc",
426         "dpb",
427         "reserved",
428         "dpd",
429 };
430
431 static int
432 intel_gmbus_probe(device_t dev)
433 {
434
435         return (BUS_PROBE_SPECIFIC);
436 }
437
438 static int
439 intel_gmbus_attach(device_t idev)
440 {
441         struct drm_i915_private *dev_priv;
442         struct intel_iic_softc *sc;
443         int pin;
444
445         sc = device_get_softc(idev);
446         sc->drm_dev = device_get_softc(device_get_parent(idev));
447         dev_priv = sc->drm_dev->dev_private;
448         pin = device_get_unit(idev);
449
450         ksnprintf(sc->name, sizeof(sc->name), "gmbus bus %s", gpio_names[pin]);
451         device_set_desc(idev, sc->name);
452
453         /* By default use a conservative clock rate */
454         sc->reg0 = pin | GMBUS_RATE_100KHZ;
455
456         /* XXX force bit banging until GMBUS is fully debugged */
457         if (IS_GEN2(sc->drm_dev)) {
458                 sc->force_bit_dev = true;
459         }
460
461         /* add bus interface device */
462         sc->iic_dev = device_add_child(idev, "iicbus", -1);
463         if (sc->iic_dev == NULL)
464                 return (ENXIO);
465         device_quiet(sc->iic_dev);
466         bus_generic_attach(idev);
467
468         return (0);
469 }
470
471 static int
472 intel_gmbus_detach(device_t idev)
473 {
474         struct intel_iic_softc *sc;
475         struct drm_i915_private *dev_priv;
476         device_t child;
477         int u;
478
479         sc = device_get_softc(idev);
480         u = device_get_unit(idev);
481         dev_priv = sc->drm_dev->dev_private;
482
483         child = sc->iic_dev;
484         bus_generic_detach(idev);
485         if (child != NULL)
486                 device_delete_child(idev, child);
487
488         return (0);
489 }
490
491 static int
492 intel_iicbb_probe(device_t dev)
493 {
494
495         return (BUS_PROBE_DEFAULT);
496 }
497
498 static int
499 intel_iicbb_attach(device_t idev)
500 {
501         static const int map_pin_to_reg[] = {
502                 0,
503                 GPIOB,
504                 GPIOA,
505                 GPIOC,
506                 GPIOD,
507                 GPIOE,
508                 0,
509                 GPIOF
510         };
511
512         struct intel_iic_softc *sc;
513         struct drm_i915_private *dev_priv;
514         int pin;
515
516         sc = device_get_softc(idev);
517         sc->drm_dev = device_get_softc(device_get_parent(idev));
518         dev_priv = sc->drm_dev->dev_private;
519         pin = device_get_unit(idev);
520
521         ksnprintf(sc->name, sizeof(sc->name), "i915 iicbb %s", gpio_names[pin]);
522         device_set_desc(idev, sc->name);
523
524         sc->reg0 = pin | GMBUS_RATE_100KHZ;
525         sc->reg = map_pin_to_reg[pin];
526         if (HAS_PCH_SPLIT(dev_priv->dev))
527                 sc->reg += PCH_GPIOA - GPIOA;
528
529         /* add generic bit-banging code */
530         sc->iic_dev = device_add_child(idev, "iicbb", -1);
531         if (sc->iic_dev == NULL)
532                 return (ENXIO);
533         device_quiet(sc->iic_dev);
534         bus_generic_attach(idev);
535
536         return (0);
537 }
538
539 static int
540 intel_iicbb_detach(device_t idev)
541 {
542         struct intel_iic_softc *sc;
543         device_t child;
544
545         sc = device_get_softc(idev);
546         child = sc->iic_dev;
547         bus_generic_detach(idev);
548         if (child)
549                 device_delete_child(idev, child);
550         return (0);
551 }
552
553 static device_method_t intel_gmbus_methods[] = {
554         DEVMETHOD(device_probe,         intel_gmbus_probe),
555         DEVMETHOD(device_attach,        intel_gmbus_attach),
556         DEVMETHOD(device_detach,        intel_gmbus_detach),
557         DEVMETHOD(iicbus_reset,         intel_iicbus_reset),
558         DEVMETHOD(iicbus_transfer,      intel_gmbus_transfer),
559         DEVMETHOD_END
560 };
561 static driver_t intel_gmbus_driver = {
562         "intel_gmbus",
563         intel_gmbus_methods,
564         sizeof(struct intel_iic_softc)
565 };
566 static devclass_t intel_gmbus_devclass;
567 DRIVER_MODULE_ORDERED(intel_gmbus, drmn, intel_gmbus_driver,
568     intel_gmbus_devclass, 0, 0, SI_ORDER_FIRST);
569 DRIVER_MODULE(iicbus, intel_gmbus, iicbus_driver, iicbus_devclass, 0, 0);
570
571 static device_method_t intel_iicbb_methods[] =  {
572         DEVMETHOD(device_probe,         intel_iicbb_probe),
573         DEVMETHOD(device_attach,        intel_iicbb_attach),
574         DEVMETHOD(device_detach,        intel_iicbb_detach),
575
576         DEVMETHOD(bus_add_child,        bus_generic_add_child),
577         DEVMETHOD(bus_print_child,      bus_generic_print_child),
578
579         DEVMETHOD(iicbb_callback,       iicbus_null_callback),
580         DEVMETHOD(iicbb_reset,          intel_iicbus_reset),
581         DEVMETHOD(iicbb_setsda,         intel_iicbb_setsda),
582         DEVMETHOD(iicbb_setscl,         intel_iicbb_setscl),
583         DEVMETHOD(iicbb_getsda,         intel_iicbb_getsda),
584         DEVMETHOD(iicbb_getscl,         intel_iicbb_getscl),
585         DEVMETHOD_END
586 };
587 static driver_t intel_iicbb_driver = {
588         "intel_iicbb",
589         intel_iicbb_methods,
590         sizeof(struct intel_iic_softc)
591 };
592 static devclass_t intel_iicbb_devclass;
593 DRIVER_MODULE_ORDERED(intel_iicbb, drmn, intel_iicbb_driver,
594     intel_iicbb_devclass, 0, 0, SI_ORDER_FIRST);
595 DRIVER_MODULE(iicbb, intel_iicbb, iicbb_driver, iicbb_devclass, 0, 0);
596
597 int
598 intel_setup_gmbus(struct drm_device *dev)
599 {
600         struct drm_i915_private *dev_priv;
601         device_t iic_dev;
602         int i, ret;
603
604         dev_priv = dev->dev_private;
605         lockinit(&dev_priv->gmbus_lock, "gmbus", 0, LK_CANRECURSE);
606         dev_priv->gmbus_bridge = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS,
607             DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
608         dev_priv->bbbus_bridge = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS,
609             DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
610         dev_priv->gmbus = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS,
611             DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
612         dev_priv->bbbus = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS,
613             DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
614
615         /*
616          * The Giant there is recursed, most likely.  Normally, the
617          * intel_setup_gmbus() is called from the attach method of the
618          * driver.
619          */
620         get_mplock();
621         for (i = 0; i < GMBUS_NUM_PORTS; i++) {
622                 /*
623                  * Initialized bbbus_bridge before gmbus_bridge, since
624                  * gmbus may decide to force quirk transfer in the
625                  * attachment code.
626                  */
627                 dev_priv->bbbus_bridge[i] = device_add_child(dev->device,
628                     "intel_iicbb", i);
629                 if (dev_priv->bbbus_bridge[i] == NULL) {
630                         DRM_ERROR("bbbus bridge %d creation failed\n", i);
631                         ret = ENXIO;
632                         goto err;
633                 }
634                 device_quiet(dev_priv->bbbus_bridge[i]);
635                 ret = device_probe_and_attach(dev_priv->bbbus_bridge[i]);
636                 if (ret != 0) {
637                         DRM_ERROR("bbbus bridge %d attach failed, %d\n", i,
638                             ret);
639                         goto err;
640                 }
641
642                 iic_dev = device_find_child(dev_priv->bbbus_bridge[i], "iicbb",
643                     -1);
644                 if (iic_dev == NULL) {
645                         DRM_ERROR("bbbus bridge doesn't have iicbb child\n");
646                         goto err;
647                 }
648                 iic_dev = device_find_child(iic_dev, "iicbus", -1);
649                 if (iic_dev == NULL) {
650                         DRM_ERROR(
651                 "bbbus bridge doesn't have iicbus grandchild\n");
652                         goto err;
653                 }
654
655                 dev_priv->bbbus[i] = iic_dev;
656
657                 dev_priv->gmbus_bridge[i] = device_add_child(dev->device,
658                     "intel_gmbus", i);
659                 if (dev_priv->gmbus_bridge[i] == NULL) {
660                         DRM_ERROR("gmbus bridge %d creation failed\n", i);
661                         ret = ENXIO;
662                         goto err;
663                 }
664                 device_quiet(dev_priv->gmbus_bridge[i]);
665                 ret = device_probe_and_attach(dev_priv->gmbus_bridge[i]);
666                 if (ret != 0) {
667                         DRM_ERROR("gmbus bridge %d attach failed, %d\n", i,
668                             ret);
669                         ret = ENXIO;
670                         goto err;
671                 }
672
673                 iic_dev = device_find_child(dev_priv->gmbus_bridge[i],
674                     "iicbus", -1);
675                 if (iic_dev == NULL) {
676                         DRM_ERROR("gmbus bridge doesn't have iicbus child\n");
677                         goto err;
678                 }
679                 dev_priv->gmbus[i] = iic_dev;
680
681                 intel_iic_reset(dev);
682         }
683
684         rel_mplock();
685         return (0);
686
687 err:
688         intel_teardown_gmbus_m(dev, i);
689         rel_mplock();
690         return (ret);
691 }
692
693 static void
694 intel_teardown_gmbus_m(struct drm_device *dev, int m)
695 {
696         struct drm_i915_private *dev_priv;
697
698         dev_priv = dev->dev_private;
699
700         kfree(dev_priv->gmbus, DRM_MEM_DRIVER);
701         dev_priv->gmbus = NULL;
702         kfree(dev_priv->bbbus, DRM_MEM_DRIVER);
703         dev_priv->bbbus = NULL;
704         kfree(dev_priv->gmbus_bridge, DRM_MEM_DRIVER);
705         dev_priv->gmbus_bridge = NULL;
706         kfree(dev_priv->bbbus_bridge, DRM_MEM_DRIVER);
707         dev_priv->bbbus_bridge = NULL;
708         lockuninit(&dev_priv->gmbus_lock);
709 }
710
711 void
712 intel_teardown_gmbus(struct drm_device *dev)
713 {
714
715         get_mplock();
716         intel_teardown_gmbus_m(dev, GMBUS_NUM_PORTS);
717         rel_mplock();
718 }