2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
26 * $FreeBSD: src/sys/dev/drm2/i915/intel_display.c,v 1.2 2012/05/24 19:13:54 dim Exp $
30 #include <sys/limits.h>
33 #include <drm/drm_edid.h>
34 #include "intel_drv.h"
35 #include <drm/i915_drm.h>
37 #include <drm/drm_dp_helper.h>
38 #include <drm/drm_crtc_helper.h>
40 #include <linux/err.h>
42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
69 #define INTEL_P2_NUM 2
70 typedef struct intel_limit intel_limit_t;
72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
75 int, int, intel_clock_t *, intel_clock_t *);
79 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
83 int target, int refclk, intel_clock_t *match_clock,
84 intel_clock_t *best_clock);
86 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
87 int target, int refclk, intel_clock_t *match_clock,
88 intel_clock_t *best_clock);
91 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
92 int target, int refclk, intel_clock_t *match_clock,
93 intel_clock_t *best_clock);
95 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
96 int target, int refclk, intel_clock_t *match_clock,
97 intel_clock_t *best_clock);
99 static inline u32 /* units of 100MHz */
100 intel_fdi_link_freq(struct drm_device *dev)
103 struct drm_i915_private *dev_priv = dev->dev_private;
104 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
109 static const intel_limit_t intel_limits_i8xx_dvo = {
110 .dot = { .min = 25000, .max = 350000 },
111 .vco = { .min = 930000, .max = 1400000 },
112 .n = { .min = 3, .max = 16 },
113 .m = { .min = 96, .max = 140 },
114 .m1 = { .min = 18, .max = 26 },
115 .m2 = { .min = 6, .max = 16 },
116 .p = { .min = 4, .max = 128 },
117 .p1 = { .min = 2, .max = 33 },
118 .p2 = { .dot_limit = 165000,
119 .p2_slow = 4, .p2_fast = 2 },
120 .find_pll = intel_find_best_PLL,
123 static const intel_limit_t intel_limits_i8xx_lvds = {
124 .dot = { .min = 25000, .max = 350000 },
125 .vco = { .min = 930000, .max = 1400000 },
126 .n = { .min = 3, .max = 16 },
127 .m = { .min = 96, .max = 140 },
128 .m1 = { .min = 18, .max = 26 },
129 .m2 = { .min = 6, .max = 16 },
130 .p = { .min = 4, .max = 128 },
131 .p1 = { .min = 1, .max = 6 },
132 .p2 = { .dot_limit = 165000,
133 .p2_slow = 14, .p2_fast = 7 },
134 .find_pll = intel_find_best_PLL,
137 static const intel_limit_t intel_limits_i9xx_sdvo = {
138 .dot = { .min = 20000, .max = 400000 },
139 .vco = { .min = 1400000, .max = 2800000 },
140 .n = { .min = 1, .max = 6 },
141 .m = { .min = 70, .max = 120 },
142 .m1 = { .min = 10, .max = 22 },
143 .m2 = { .min = 5, .max = 9 },
144 .p = { .min = 5, .max = 80 },
145 .p1 = { .min = 1, .max = 8 },
146 .p2 = { .dot_limit = 200000,
147 .p2_slow = 10, .p2_fast = 5 },
148 .find_pll = intel_find_best_PLL,
151 static const intel_limit_t intel_limits_i9xx_lvds = {
152 .dot = { .min = 20000, .max = 400000 },
153 .vco = { .min = 1400000, .max = 2800000 },
154 .n = { .min = 1, .max = 6 },
155 .m = { .min = 70, .max = 120 },
156 .m1 = { .min = 10, .max = 22 },
157 .m2 = { .min = 5, .max = 9 },
158 .p = { .min = 7, .max = 98 },
159 .p1 = { .min = 1, .max = 8 },
160 .p2 = { .dot_limit = 112000,
161 .p2_slow = 14, .p2_fast = 7 },
162 .find_pll = intel_find_best_PLL,
166 static const intel_limit_t intel_limits_g4x_sdvo = {
167 .dot = { .min = 25000, .max = 270000 },
168 .vco = { .min = 1750000, .max = 3500000},
169 .n = { .min = 1, .max = 4 },
170 .m = { .min = 104, .max = 138 },
171 .m1 = { .min = 17, .max = 23 },
172 .m2 = { .min = 5, .max = 11 },
173 .p = { .min = 10, .max = 30 },
174 .p1 = { .min = 1, .max = 3},
175 .p2 = { .dot_limit = 270000,
179 .find_pll = intel_g4x_find_best_PLL,
182 static const intel_limit_t intel_limits_g4x_hdmi = {
183 .dot = { .min = 22000, .max = 400000 },
184 .vco = { .min = 1750000, .max = 3500000},
185 .n = { .min = 1, .max = 4 },
186 .m = { .min = 104, .max = 138 },
187 .m1 = { .min = 16, .max = 23 },
188 .m2 = { .min = 5, .max = 11 },
189 .p = { .min = 5, .max = 80 },
190 .p1 = { .min = 1, .max = 8},
191 .p2 = { .dot_limit = 165000,
192 .p2_slow = 10, .p2_fast = 5 },
193 .find_pll = intel_g4x_find_best_PLL,
196 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
197 .dot = { .min = 20000, .max = 115000 },
198 .vco = { .min = 1750000, .max = 3500000 },
199 .n = { .min = 1, .max = 3 },
200 .m = { .min = 104, .max = 138 },
201 .m1 = { .min = 17, .max = 23 },
202 .m2 = { .min = 5, .max = 11 },
203 .p = { .min = 28, .max = 112 },
204 .p1 = { .min = 2, .max = 8 },
205 .p2 = { .dot_limit = 0,
206 .p2_slow = 14, .p2_fast = 14
208 .find_pll = intel_g4x_find_best_PLL,
211 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
212 .dot = { .min = 80000, .max = 224000 },
213 .vco = { .min = 1750000, .max = 3500000 },
214 .n = { .min = 1, .max = 3 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 14, .max = 42 },
219 .p1 = { .min = 2, .max = 6 },
220 .p2 = { .dot_limit = 0,
221 .p2_slow = 7, .p2_fast = 7
223 .find_pll = intel_g4x_find_best_PLL,
226 static const intel_limit_t intel_limits_g4x_display_port = {
227 .dot = { .min = 161670, .max = 227000 },
228 .vco = { .min = 1750000, .max = 3500000},
229 .n = { .min = 1, .max = 2 },
230 .m = { .min = 97, .max = 108 },
231 .m1 = { .min = 0x10, .max = 0x12 },
232 .m2 = { .min = 0x05, .max = 0x06 },
233 .p = { .min = 10, .max = 20 },
234 .p1 = { .min = 1, .max = 2},
235 .p2 = { .dot_limit = 0,
236 .p2_slow = 10, .p2_fast = 10 },
237 .find_pll = intel_find_pll_g4x_dp,
240 static const intel_limit_t intel_limits_pineview_sdvo = {
241 .dot = { .min = 20000, .max = 400000},
242 .vco = { .min = 1700000, .max = 3500000 },
243 /* Pineview's Ncounter is a ring counter */
244 .n = { .min = 3, .max = 6 },
245 .m = { .min = 2, .max = 256 },
246 /* Pineview only has one combined m divider, which we treat as m2. */
247 .m1 = { .min = 0, .max = 0 },
248 .m2 = { .min = 0, .max = 254 },
249 .p = { .min = 5, .max = 80 },
250 .p1 = { .min = 1, .max = 8 },
251 .p2 = { .dot_limit = 200000,
252 .p2_slow = 10, .p2_fast = 5 },
253 .find_pll = intel_find_best_PLL,
256 static const intel_limit_t intel_limits_pineview_lvds = {
257 .dot = { .min = 20000, .max = 400000 },
258 .vco = { .min = 1700000, .max = 3500000 },
259 .n = { .min = 3, .max = 6 },
260 .m = { .min = 2, .max = 256 },
261 .m1 = { .min = 0, .max = 0 },
262 .m2 = { .min = 0, .max = 254 },
263 .p = { .min = 7, .max = 112 },
264 .p1 = { .min = 1, .max = 8 },
265 .p2 = { .dot_limit = 112000,
266 .p2_slow = 14, .p2_fast = 14 },
267 .find_pll = intel_find_best_PLL,
270 /* Ironlake / Sandybridge
272 * We calculate clock using (register_value + 2) for N/M1/M2, so here
273 * the range value for them is (actual_value - 2).
275 static const intel_limit_t intel_limits_ironlake_dac = {
276 .dot = { .min = 25000, .max = 350000 },
277 .vco = { .min = 1760000, .max = 3510000 },
278 .n = { .min = 1, .max = 5 },
279 .m = { .min = 79, .max = 127 },
280 .m1 = { .min = 12, .max = 22 },
281 .m2 = { .min = 5, .max = 9 },
282 .p = { .min = 5, .max = 80 },
283 .p1 = { .min = 1, .max = 8 },
284 .p2 = { .dot_limit = 225000,
285 .p2_slow = 10, .p2_fast = 5 },
286 .find_pll = intel_g4x_find_best_PLL,
289 static const intel_limit_t intel_limits_ironlake_single_lvds = {
290 .dot = { .min = 25000, .max = 350000 },
291 .vco = { .min = 1760000, .max = 3510000 },
292 .n = { .min = 1, .max = 3 },
293 .m = { .min = 79, .max = 118 },
294 .m1 = { .min = 12, .max = 22 },
295 .m2 = { .min = 5, .max = 9 },
296 .p = { .min = 28, .max = 112 },
297 .p1 = { .min = 2, .max = 8 },
298 .p2 = { .dot_limit = 225000,
299 .p2_slow = 14, .p2_fast = 14 },
300 .find_pll = intel_g4x_find_best_PLL,
303 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 3 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 14, .max = 56 },
311 .p1 = { .min = 2, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 7, .p2_fast = 7 },
314 .find_pll = intel_g4x_find_best_PLL,
317 /* LVDS 100mhz refclk limits. */
318 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 2 },
322 .m = { .min = 79, .max = 126 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 28, .max = 112 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 14, .p2_fast = 14 },
329 .find_pll = intel_g4x_find_best_PLL,
332 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
333 .dot = { .min = 25000, .max = 350000 },
334 .vco = { .min = 1760000, .max = 3510000 },
335 .n = { .min = 1, .max = 3 },
336 .m = { .min = 79, .max = 126 },
337 .m1 = { .min = 12, .max = 22 },
338 .m2 = { .min = 5, .max = 9 },
339 .p = { .min = 14, .max = 42 },
340 .p1 = { .min = 2, .max = 6 },
341 .p2 = { .dot_limit = 225000,
342 .p2_slow = 7, .p2_fast = 7 },
343 .find_pll = intel_g4x_find_best_PLL,
346 static const intel_limit_t intel_limits_ironlake_display_port = {
347 .dot = { .min = 25000, .max = 350000 },
348 .vco = { .min = 1760000, .max = 3510000},
349 .n = { .min = 1, .max = 2 },
350 .m = { .min = 81, .max = 90 },
351 .m1 = { .min = 12, .max = 22 },
352 .m2 = { .min = 5, .max = 9 },
353 .p = { .min = 10, .max = 20 },
354 .p1 = { .min = 1, .max = 2},
355 .p2 = { .dot_limit = 0,
356 .p2_slow = 10, .p2_fast = 10 },
357 .find_pll = intel_find_pll_ironlake_dp,
360 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
363 struct drm_device *dev = crtc->dev;
364 struct drm_i915_private *dev_priv = dev->dev_private;
365 const intel_limit_t *limit;
367 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
368 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
369 LVDS_CLKB_POWER_UP) {
370 /* LVDS dual channel */
371 if (refclk == 100000)
372 limit = &intel_limits_ironlake_dual_lvds_100m;
374 limit = &intel_limits_ironlake_dual_lvds;
376 if (refclk == 100000)
377 limit = &intel_limits_ironlake_single_lvds_100m;
379 limit = &intel_limits_ironlake_single_lvds;
381 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
383 limit = &intel_limits_ironlake_display_port;
385 limit = &intel_limits_ironlake_dac;
390 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
392 struct drm_device *dev = crtc->dev;
393 struct drm_i915_private *dev_priv = dev->dev_private;
394 const intel_limit_t *limit;
396 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
397 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
399 /* LVDS with dual channel */
400 limit = &intel_limits_g4x_dual_channel_lvds;
402 /* LVDS with dual channel */
403 limit = &intel_limits_g4x_single_channel_lvds;
404 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
405 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
406 limit = &intel_limits_g4x_hdmi;
407 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
408 limit = &intel_limits_g4x_sdvo;
409 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
410 limit = &intel_limits_g4x_display_port;
411 } else /* The option is for other outputs */
412 limit = &intel_limits_i9xx_sdvo;
417 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
419 struct drm_device *dev = crtc->dev;
420 const intel_limit_t *limit;
422 if (HAS_PCH_SPLIT(dev))
423 limit = intel_ironlake_limit(crtc, refclk);
424 else if (IS_G4X(dev)) {
425 limit = intel_g4x_limit(crtc);
426 } else if (IS_PINEVIEW(dev)) {
427 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
428 limit = &intel_limits_pineview_lvds;
430 limit = &intel_limits_pineview_sdvo;
431 } else if (!IS_GEN2(dev)) {
432 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
433 limit = &intel_limits_i9xx_lvds;
435 limit = &intel_limits_i9xx_sdvo;
437 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
438 limit = &intel_limits_i8xx_lvds;
440 limit = &intel_limits_i8xx_dvo;
445 /* m1 is reserved as 0 in Pineview, n is a ring counter */
446 static void pineview_clock(int refclk, intel_clock_t *clock)
448 clock->m = clock->m2 + 2;
449 clock->p = clock->p1 * clock->p2;
450 clock->vco = refclk * clock->m / clock->n;
451 clock->dot = clock->vco / clock->p;
454 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
456 if (IS_PINEVIEW(dev)) {
457 pineview_clock(refclk, clock);
460 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
461 clock->p = clock->p1 * clock->p2;
462 clock->vco = refclk * clock->m / (clock->n + 2);
463 clock->dot = clock->vco / clock->p;
467 * Returns whether any output on the specified pipe is of the specified type
469 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
471 struct drm_device *dev = crtc->dev;
472 struct drm_mode_config *mode_config = &dev->mode_config;
473 struct intel_encoder *encoder;
475 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
476 if (encoder->base.crtc == crtc && encoder->type == type)
482 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
484 * Returns whether the given set of divisors are valid for a given refclk with
485 * the given connectors.
488 static bool intel_PLL_is_valid(struct drm_device *dev,
489 const intel_limit_t *limit,
490 const intel_clock_t *clock)
492 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
493 INTELPllInvalid("p1 out of range\n");
494 if (clock->p < limit->p.min || limit->p.max < clock->p)
495 INTELPllInvalid("p out of range\n");
496 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
497 INTELPllInvalid("m2 out of range\n");
498 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
499 INTELPllInvalid("m1 out of range\n");
500 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
501 INTELPllInvalid("m1 <= m2\n");
502 if (clock->m < limit->m.min || limit->m.max < clock->m)
503 INTELPllInvalid("m out of range\n");
504 if (clock->n < limit->n.min || limit->n.max < clock->n)
505 INTELPllInvalid("n out of range\n");
506 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
507 INTELPllInvalid("vco out of range\n");
508 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
509 * connector, etc., rather than just a single range.
511 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
512 INTELPllInvalid("dot out of range\n");
518 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
519 int target, int refclk, intel_clock_t *match_clock,
520 intel_clock_t *best_clock)
523 struct drm_device *dev = crtc->dev;
524 struct drm_i915_private *dev_priv = dev->dev_private;
528 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
529 (I915_READ(LVDS)) != 0) {
531 * For LVDS, if the panel is on, just rely on its current
532 * settings for dual-channel. We haven't figured out how to
533 * reliably set up different single/dual channel state, if we
536 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
538 clock.p2 = limit->p2.p2_fast;
540 clock.p2 = limit->p2.p2_slow;
542 if (target < limit->p2.dot_limit)
543 clock.p2 = limit->p2.p2_slow;
545 clock.p2 = limit->p2.p2_fast;
548 memset(best_clock, 0, sizeof(*best_clock));
550 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
552 for (clock.m2 = limit->m2.min;
553 clock.m2 <= limit->m2.max; clock.m2++) {
554 /* m1 is always 0 in Pineview */
555 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
557 for (clock.n = limit->n.min;
558 clock.n <= limit->n.max; clock.n++) {
559 for (clock.p1 = limit->p1.min;
560 clock.p1 <= limit->p1.max; clock.p1++) {
563 intel_clock(dev, refclk, &clock);
564 if (!intel_PLL_is_valid(dev, limit,
568 clock.p != match_clock->p)
571 this_err = abs(clock.dot - target);
572 if (this_err < err) {
581 return (err != target);
585 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
586 int target, int refclk, intel_clock_t *match_clock,
587 intel_clock_t *best_clock)
589 struct drm_device *dev = crtc->dev;
590 struct drm_i915_private *dev_priv = dev->dev_private;
594 /* approximately equals target * 0.00585 */
595 int err_most = (target >> 8) + (target >> 9);
598 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
601 if (HAS_PCH_SPLIT(dev))
605 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
607 clock.p2 = limit->p2.p2_fast;
609 clock.p2 = limit->p2.p2_slow;
611 if (target < limit->p2.dot_limit)
612 clock.p2 = limit->p2.p2_slow;
614 clock.p2 = limit->p2.p2_fast;
617 memset(best_clock, 0, sizeof(*best_clock));
618 max_n = limit->n.max;
619 /* based on hardware requirement, prefer smaller n to precision */
620 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
621 /* based on hardware requirement, prefere larger m1,m2 */
622 for (clock.m1 = limit->m1.max;
623 clock.m1 >= limit->m1.min; clock.m1--) {
624 for (clock.m2 = limit->m2.max;
625 clock.m2 >= limit->m2.min; clock.m2--) {
626 for (clock.p1 = limit->p1.max;
627 clock.p1 >= limit->p1.min; clock.p1--) {
630 intel_clock(dev, refclk, &clock);
631 if (!intel_PLL_is_valid(dev, limit,
635 clock.p != match_clock->p)
638 this_err = abs(clock.dot - target);
639 if (this_err < err_most) {
653 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
654 int target, int refclk, intel_clock_t *match_clock,
655 intel_clock_t *best_clock)
657 struct drm_device *dev = crtc->dev;
660 if (target < 200000) {
673 intel_clock(dev, refclk, &clock);
674 memcpy(best_clock, &clock, sizeof(intel_clock_t));
678 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
680 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
681 int target, int refclk, intel_clock_t *match_clock,
682 intel_clock_t *best_clock)
685 if (target < 200000) {
698 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
699 clock.p = (clock.p1 * clock.p2);
700 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
702 memcpy(best_clock, &clock, sizeof(intel_clock_t));
707 * intel_wait_for_vblank - wait for vblank on a given pipe
709 * @pipe: pipe to wait for
711 * Wait for vblank to occur on a given pipe. Needed for various bits of
714 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
716 struct drm_i915_private *dev_priv = dev->dev_private;
717 int pipestat_reg = PIPESTAT(pipe);
719 /* Clear existing vblank status. Note this will clear any other
720 * sticky status fields as well.
722 * This races with i915_driver_irq_handler() with the result
723 * that either function could miss a vblank event. Here it is not
724 * fatal, as we will either wait upon the next vblank interrupt or
725 * timeout. Generally speaking intel_wait_for_vblank() is only
726 * called during modeset at which time the GPU should be idle and
727 * should *not* be performing page flips and thus not waiting on
729 * Currently, the result of us stealing a vblank from the irq
730 * handler is that a single frame will be skipped during swapbuffers.
732 I915_WRITE(pipestat_reg,
733 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
735 /* Wait for vblank interrupt bit to set */
736 if (_intel_wait_for(dev,
737 I915_READ(pipestat_reg) & PIPE_VBLANK_INTERRUPT_STATUS,
739 DRM_DEBUG_KMS("vblank wait timed out\n");
743 * intel_wait_for_pipe_off - wait for pipe to turn off
745 * @pipe: pipe to wait for
747 * After disabling a pipe, we can't wait for vblank in the usual way,
748 * spinning on the vblank interrupt status bit, since we won't actually
749 * see an interrupt when the pipe is disabled.
752 * wait for the pipe register state bit to turn off
755 * wait for the display line value to settle (it usually
756 * ends up stopping at the start of the next frame).
759 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
761 struct drm_i915_private *dev_priv = dev->dev_private;
763 if (INTEL_INFO(dev)->gen >= 4) {
764 int reg = PIPECONF(pipe);
766 /* Wait for the Pipe State to go off */
767 if (_intel_wait_for(dev,
768 (I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, 100,
770 DRM_DEBUG_KMS("pipe_off wait timed out\n");
772 u32 last_line, line_mask;
773 int reg = PIPEDSL(pipe);
774 unsigned long timeout = jiffies + msecs_to_jiffies(100);
777 line_mask = DSL_LINEMASK_GEN2;
779 line_mask = DSL_LINEMASK_GEN3;
781 /* Wait for the display line to settle */
783 last_line = I915_READ(reg) & line_mask;
785 } while (((I915_READ(reg) & line_mask) != last_line) &&
786 time_after(timeout, jiffies));
787 if (time_after(jiffies, timeout))
788 DRM_DEBUG_KMS("pipe_off wait timed out\n");
792 static const char *state_string(bool enabled)
794 return enabled ? "on" : "off";
797 /* Only for pre-ILK configs */
798 static void assert_pll(struct drm_i915_private *dev_priv,
799 enum i915_pipe pipe, bool state)
806 val = I915_READ(reg);
807 cur_state = !!(val & DPLL_VCO_ENABLE);
808 if (cur_state != state)
809 kprintf("PLL state assertion failure (expected %s, current %s)\n",
810 state_string(state), state_string(cur_state));
812 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
813 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
816 static void assert_pch_pll(struct drm_i915_private *dev_priv,
817 enum i915_pipe pipe, bool state)
823 if (HAS_PCH_CPT(dev_priv->dev)) {
826 pch_dpll = I915_READ(PCH_DPLL_SEL);
828 /* Make sure the selected PLL is enabled to the transcoder */
829 KASSERT(((pch_dpll >> (4 * pipe)) & 8) != 0,
830 ("transcoder %d PLL not enabled\n", pipe));
832 /* Convert the transcoder pipe number to a pll pipe number */
833 pipe = (pch_dpll >> (4 * pipe)) & 1;
836 reg = _PCH_DPLL(pipe);
837 val = I915_READ(reg);
838 cur_state = !!(val & DPLL_VCO_ENABLE);
839 if (cur_state != state)
840 kprintf("PCH PLL state assertion failure (expected %s, current %s)\n",
841 state_string(state), state_string(cur_state));
843 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
844 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
846 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
847 enum i915_pipe pipe, bool state)
853 reg = FDI_TX_CTL(pipe);
854 val = I915_READ(reg);
855 cur_state = !!(val & FDI_TX_ENABLE);
856 if (cur_state != state)
857 kprintf("FDI TX state assertion failure (expected %s, current %s)\n",
858 state_string(state), state_string(cur_state));
860 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
861 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
863 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
864 enum i915_pipe pipe, bool state)
870 reg = FDI_RX_CTL(pipe);
871 val = I915_READ(reg);
872 cur_state = !!(val & FDI_RX_ENABLE);
873 if (cur_state != state)
874 kprintf("FDI RX state assertion failure (expected %s, current %s)\n",
875 state_string(state), state_string(cur_state));
877 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
878 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
880 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
886 /* ILK FDI PLL is always enabled */
887 if (dev_priv->info->gen == 5)
890 reg = FDI_TX_CTL(pipe);
891 val = I915_READ(reg);
892 if (!(val & FDI_TX_PLL_ENABLE))
893 kprintf("FDI TX PLL assertion failure, should be active but is disabled\n");
896 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
902 reg = FDI_RX_CTL(pipe);
903 val = I915_READ(reg);
904 if (!(val & FDI_RX_PLL_ENABLE))
905 kprintf("FDI RX PLL assertion failure, should be active but is disabled\n");
908 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
911 int pp_reg, lvds_reg;
913 enum i915_pipe panel_pipe = PIPE_A;
916 if (HAS_PCH_SPLIT(dev_priv->dev)) {
917 pp_reg = PCH_PP_CONTROL;
924 val = I915_READ(pp_reg);
925 if (!(val & PANEL_POWER_ON) ||
926 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
929 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
932 if (panel_pipe == pipe && locked)
933 kprintf("panel assertion failure, pipe %c regs locked\n",
937 void assert_pipe(struct drm_i915_private *dev_priv,
938 enum i915_pipe pipe, bool state)
944 /* if we need the pipe A quirk it must be always on */
945 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
948 reg = PIPECONF(pipe);
949 val = I915_READ(reg);
950 cur_state = !!(val & PIPECONF_ENABLE);
951 if (cur_state != state)
952 kprintf("pipe %c assertion failure (expected %s, current %s)\n",
953 pipe_name(pipe), state_string(state), state_string(cur_state));
956 static void assert_plane(struct drm_i915_private *dev_priv,
957 enum plane plane, bool state)
963 reg = DSPCNTR(plane);
964 val = I915_READ(reg);
965 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
966 if (cur_state != state)
967 kprintf("plane %c assertion failure, (expected %s, current %s)\n",
968 plane_name(plane), state_string(state), state_string(cur_state));
971 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
972 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
974 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
981 /* Planes are fixed to pipes on ILK+ */
982 if (HAS_PCH_SPLIT(dev_priv->dev)) {
984 val = I915_READ(reg);
985 if ((val & DISPLAY_PLANE_ENABLE) != 0)
986 kprintf("plane %c assertion failure, should be disabled but not\n",
991 /* Need to check both planes against the pipe */
992 for (i = 0; i < 2; i++) {
994 val = I915_READ(reg);
995 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
996 DISPPLANE_SEL_PIPE_SHIFT;
997 if ((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe)
998 kprintf("plane %c assertion failure, should be off on pipe %c but is still active\n",
999 plane_name(i), pipe_name(pipe));
1003 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1008 val = I915_READ(PCH_DREF_CONTROL);
1009 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1010 DREF_SUPERSPREAD_SOURCE_MASK));
1012 kprintf("PCH refclk assertion failure, should be active but is disabled\n");
1015 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1016 enum i915_pipe pipe)
1022 reg = TRANSCONF(pipe);
1023 val = I915_READ(reg);
1024 enabled = !!(val & TRANS_ENABLE);
1026 kprintf("transcoder assertion failed, should be off on pipe %c but is still active\n",
1030 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1031 enum i915_pipe pipe, u32 val)
1033 if ((val & PORT_ENABLE) == 0)
1036 if (HAS_PCH_CPT(dev_priv->dev)) {
1037 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1040 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1046 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1047 enum i915_pipe pipe, u32 val)
1049 if ((val & LVDS_PORT_EN) == 0)
1052 if (HAS_PCH_CPT(dev_priv->dev)) {
1053 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1056 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1062 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1063 enum i915_pipe pipe, u32 val)
1065 if ((val & ADPA_DAC_ENABLE) == 0)
1067 if (HAS_PCH_CPT(dev_priv->dev)) {
1068 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1071 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1077 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1078 enum i915_pipe pipe, u32 port_sel, u32 val)
1080 if ((val & DP_PORT_EN) == 0)
1083 if (HAS_PCH_CPT(dev_priv->dev)) {
1084 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1085 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1086 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1089 if ((val & DP_PIPE_MASK) != (pipe << 30))
1095 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1096 enum i915_pipe pipe, int reg, u32 port_sel)
1098 u32 val = I915_READ(reg);
1099 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val))
1100 kprintf("PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1101 reg, pipe_name(pipe));
1104 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1105 enum i915_pipe pipe, int reg)
1107 u32 val = I915_READ(reg);
1108 if (hdmi_pipe_enabled(dev_priv, val, pipe))
1109 kprintf("PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1110 reg, pipe_name(pipe));
1113 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1114 enum i915_pipe pipe)
1119 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1120 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1121 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1124 val = I915_READ(reg);
1125 if (adpa_pipe_enabled(dev_priv, val, pipe))
1126 kprintf("PCH VGA enabled on transcoder %c, should be disabled\n",
1130 val = I915_READ(reg);
1131 if (lvds_pipe_enabled(dev_priv, val, pipe))
1132 kprintf("PCH LVDS enabled on transcoder %c, should be disabled\n",
1135 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1136 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1137 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1141 * intel_enable_pll - enable a PLL
1142 * @dev_priv: i915 private structure
1143 * @pipe: pipe PLL to enable
1145 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1146 * make sure the PLL reg is writable first though, since the panel write
1147 * protect mechanism may be enabled.
1149 * Note! This is for pre-ILK only.
1151 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum i915_pipe pipe)
1156 /* No really, not for ILK+ */
1157 KASSERT(dev_priv->info->gen < 5, ("Wrong device gen"));
1159 /* PLL is protected by panel, make sure we can write it */
1160 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1161 assert_panel_unlocked(dev_priv, pipe);
1164 val = I915_READ(reg);
1165 val |= DPLL_VCO_ENABLE;
1167 /* We do this three times for luck */
1168 I915_WRITE(reg, val);
1170 DELAY(150); /* wait for warmup */
1171 I915_WRITE(reg, val);
1173 DELAY(150); /* wait for warmup */
1174 I915_WRITE(reg, val);
1176 DELAY(150); /* wait for warmup */
1180 * intel_disable_pll - disable a PLL
1181 * @dev_priv: i915 private structure
1182 * @pipe: pipe PLL to disable
1184 * Disable the PLL for @pipe, making sure the pipe is off first.
1186 * Note! This is for pre-ILK only.
1188 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum i915_pipe pipe)
1193 /* Don't disable pipe A or pipe A PLLs if needed */
1194 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1197 /* Make sure the pipe isn't still relying on us */
1198 assert_pipe_disabled(dev_priv, pipe);
1201 val = I915_READ(reg);
1202 val &= ~DPLL_VCO_ENABLE;
1203 I915_WRITE(reg, val);
1208 * intel_enable_pch_pll - enable PCH PLL
1209 * @dev_priv: i915 private structure
1210 * @pipe: pipe PLL to enable
1212 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1213 * drives the transcoder clock.
1215 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1216 enum i915_pipe pipe)
1224 /* PCH only available on ILK+ */
1225 KASSERT(dev_priv->info->gen >= 5, ("Wrong device gen"));
1227 /* PCH refclock must be enabled first */
1228 assert_pch_refclk_enabled(dev_priv);
1230 reg = _PCH_DPLL(pipe);
1231 val = I915_READ(reg);
1232 val |= DPLL_VCO_ENABLE;
1233 I915_WRITE(reg, val);
1238 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1239 enum i915_pipe pipe)
1242 u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1243 pll_sel = TRANSC_DPLL_ENABLE;
1248 /* PCH only available on ILK+ */
1249 KASSERT(dev_priv->info->gen >= 5, ("Wrong device gen"));
1251 /* Make sure transcoder isn't still depending on us */
1252 assert_transcoder_disabled(dev_priv, pipe);
1255 pll_sel |= TRANSC_DPLLA_SEL;
1257 pll_sel |= TRANSC_DPLLB_SEL;
1260 if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1263 reg = _PCH_DPLL(pipe);
1264 val = I915_READ(reg);
1265 val &= ~DPLL_VCO_ENABLE;
1266 I915_WRITE(reg, val);
1271 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1272 enum i915_pipe pipe)
1275 u32 val, pipeconf_val;
1276 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1278 /* PCH only available on ILK+ */
1279 KASSERT(dev_priv->info->gen >= 5, ("Wrong device gen"));
1281 /* Make sure PCH DPLL is enabled */
1282 assert_pch_pll_enabled(dev_priv, pipe);
1284 /* FDI must be feeding us bits for PCH ports */
1285 assert_fdi_tx_enabled(dev_priv, pipe);
1286 assert_fdi_rx_enabled(dev_priv, pipe);
1289 reg = TRANSCONF(pipe);
1290 val = I915_READ(reg);
1291 pipeconf_val = I915_READ(PIPECONF(pipe));
1293 if (HAS_PCH_IBX(dev_priv->dev)) {
1295 * make the BPC in transcoder be consistent with
1296 * that in pipeconf reg.
1298 val &= ~PIPE_BPC_MASK;
1299 val |= pipeconf_val & PIPE_BPC_MASK;
1302 val &= ~TRANS_INTERLACE_MASK;
1303 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1304 if (HAS_PCH_IBX(dev_priv->dev) &&
1305 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1306 val |= TRANS_LEGACY_INTERLACED_ILK;
1308 val |= TRANS_INTERLACED;
1310 val |= TRANS_PROGRESSIVE;
1312 I915_WRITE(reg, val | TRANS_ENABLE);
1313 if (_intel_wait_for(dev_priv->dev, I915_READ(reg) & TRANS_STATE_ENABLE,
1315 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1318 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1319 enum i915_pipe pipe)
1324 /* FDI relies on the transcoder */
1325 assert_fdi_tx_disabled(dev_priv, pipe);
1326 assert_fdi_rx_disabled(dev_priv, pipe);
1328 /* Ports must be off as well */
1329 assert_pch_ports_disabled(dev_priv, pipe);
1331 reg = TRANSCONF(pipe);
1332 val = I915_READ(reg);
1333 val &= ~TRANS_ENABLE;
1334 I915_WRITE(reg, val);
1335 /* wait for PCH transcoder off, transcoder state */
1336 if (_intel_wait_for(dev_priv->dev,
1337 (I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50,
1339 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1343 * intel_enable_pipe - enable a pipe, asserting requirements
1344 * @dev_priv: i915 private structure
1345 * @pipe: pipe to enable
1346 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1348 * Enable @pipe, making sure that various hardware specific requirements
1349 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1351 * @pipe should be %PIPE_A or %PIPE_B.
1353 * Will wait until the pipe is actually running (i.e. first vblank) before
1356 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe,
1363 * A pipe without a PLL won't actually be able to drive bits from
1364 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1367 if (!HAS_PCH_SPLIT(dev_priv->dev))
1368 assert_pll_enabled(dev_priv, pipe);
1371 /* if driving the PCH, we need FDI enabled */
1372 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1373 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1375 /* FIXME: assert CPU port conditions for SNB+ */
1378 reg = PIPECONF(pipe);
1379 val = I915_READ(reg);
1380 if (val & PIPECONF_ENABLE)
1383 I915_WRITE(reg, val | PIPECONF_ENABLE);
1384 intel_wait_for_vblank(dev_priv->dev, pipe);
1388 * intel_disable_pipe - disable a pipe, asserting requirements
1389 * @dev_priv: i915 private structure
1390 * @pipe: pipe to disable
1392 * Disable @pipe, making sure that various hardware specific requirements
1393 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1395 * @pipe should be %PIPE_A or %PIPE_B.
1397 * Will wait until the pipe has shut down before returning.
1399 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1400 enum i915_pipe pipe)
1406 * Make sure planes won't keep trying to pump pixels to us,
1407 * or we might hang the display.
1409 assert_planes_disabled(dev_priv, pipe);
1411 /* Don't disable pipe A or pipe A PLLs if needed */
1412 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1415 reg = PIPECONF(pipe);
1416 val = I915_READ(reg);
1417 if ((val & PIPECONF_ENABLE) == 0)
1420 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1421 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1425 * Plane regs are double buffered, going from enabled->disabled needs a
1426 * trigger in order to latch. The display address reg provides this.
1428 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1431 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1432 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1436 * intel_enable_plane - enable a display plane on a given pipe
1437 * @dev_priv: i915 private structure
1438 * @plane: plane to enable
1439 * @pipe: pipe being fed
1441 * Enable @plane on @pipe, making sure that @pipe is running first.
1443 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1444 enum plane plane, enum i915_pipe pipe)
1449 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1450 assert_pipe_enabled(dev_priv, pipe);
1452 reg = DSPCNTR(plane);
1453 val = I915_READ(reg);
1454 if (val & DISPLAY_PLANE_ENABLE)
1457 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1458 intel_flush_display_plane(dev_priv, plane);
1459 intel_wait_for_vblank(dev_priv->dev, pipe);
1463 * intel_disable_plane - disable a display plane
1464 * @dev_priv: i915 private structure
1465 * @plane: plane to disable
1466 * @pipe: pipe consuming the data
1468 * Disable @plane; should be an independent operation.
1470 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1471 enum plane plane, enum i915_pipe pipe)
1476 reg = DSPCNTR(plane);
1477 val = I915_READ(reg);
1478 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1481 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1482 intel_flush_display_plane(dev_priv, plane);
1483 intel_wait_for_vblank(dev_priv->dev, pipe);
1486 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1487 enum i915_pipe pipe, int reg, u32 port_sel)
1489 u32 val = I915_READ(reg);
1490 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1491 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1492 I915_WRITE(reg, val & ~DP_PORT_EN);
1496 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1497 enum i915_pipe pipe, int reg)
1499 u32 val = I915_READ(reg);
1500 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1501 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1503 I915_WRITE(reg, val & ~PORT_ENABLE);
1507 /* Disable any ports connected to this transcoder */
1508 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1509 enum i915_pipe pipe)
1513 val = I915_READ(PCH_PP_CONTROL);
1514 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1516 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1517 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1518 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1521 val = I915_READ(reg);
1522 if (adpa_pipe_enabled(dev_priv, val, pipe))
1523 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1526 val = I915_READ(reg);
1527 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1528 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1529 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1534 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1535 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1536 disable_pch_hdmi(dev_priv, pipe, HDMID);
1540 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1541 struct drm_i915_gem_object *obj,
1542 struct intel_ring_buffer *pipelined)
1544 struct drm_i915_private *dev_priv = dev->dev_private;
1548 alignment = 0; /* shut gcc */
1549 switch (obj->tiling_mode) {
1550 case I915_TILING_NONE:
1551 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1552 alignment = 128 * 1024;
1553 else if (INTEL_INFO(dev)->gen >= 4)
1554 alignment = 4 * 1024;
1556 alignment = 64 * 1024;
1559 /* pin() will align the object as required by fence */
1563 /* FIXME: Is this true? */
1564 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1567 KASSERT(0, ("Wrong tiling for fb obj"));
1570 dev_priv->mm.interruptible = false;
1571 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1573 goto err_interruptible;
1575 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1576 * fence, whereas 965+ only requires a fence if using
1577 * framebuffer compression. For simplicity, we always install
1578 * a fence as the cost is not that onerous.
1580 if (obj->tiling_mode != I915_TILING_NONE) {
1581 ret = i915_gem_object_get_fence(obj, pipelined);
1585 i915_gem_object_pin_fence(obj);
1588 dev_priv->mm.interruptible = true;
1592 i915_gem_object_unpin(obj);
1594 dev_priv->mm.interruptible = true;
1598 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1600 i915_gem_object_unpin_fence(obj);
1601 i915_gem_object_unpin(obj);
1604 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1605 * is assumed to be a power-of-two. */
1606 unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
1610 int tile_rows, tiles;
1614 tiles = *x / (512/bpp);
1617 return tile_rows * pitch * 8 + tiles * 4096;
1620 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1623 struct drm_device *dev = crtc->dev;
1624 struct drm_i915_private *dev_priv = dev->dev_private;
1625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1626 struct intel_framebuffer *intel_fb;
1627 struct drm_i915_gem_object *obj;
1628 int plane = intel_crtc->plane;
1629 unsigned long Start, Offset;
1638 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1642 intel_fb = to_intel_framebuffer(fb);
1643 obj = intel_fb->obj;
1645 reg = DSPCNTR(plane);
1646 dspcntr = I915_READ(reg);
1647 /* Mask out pixel format bits in case we change it */
1648 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1649 switch (fb->bits_per_pixel) {
1651 dspcntr |= DISPPLANE_8BPP;
1654 if (fb->depth == 15)
1655 dspcntr |= DISPPLANE_BGRX555;
1657 dspcntr |= DISPPLANE_BGRX565;
1661 dspcntr |= DISPPLANE_BGRX888;
1664 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1667 if (INTEL_INFO(dev)->gen >= 4) {
1668 if (obj->tiling_mode != I915_TILING_NONE)
1669 dspcntr |= DISPPLANE_TILED;
1671 dspcntr &= ~DISPPLANE_TILED;
1674 I915_WRITE(reg, dspcntr);
1676 Start = obj->gtt_offset;
1677 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1679 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1680 Start, Offset, x, y, fb->pitches[0]);
1681 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1682 if (INTEL_INFO(dev)->gen >= 4) {
1683 I915_WRITE(DSPSURF(plane), Start);
1684 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1685 I915_WRITE(DSPADDR(plane), Offset);
1687 I915_WRITE(DSPADDR(plane), Start + Offset);
1693 static int ironlake_update_plane(struct drm_crtc *crtc,
1694 struct drm_framebuffer *fb, int x, int y)
1696 struct drm_device *dev = crtc->dev;
1697 struct drm_i915_private *dev_priv = dev->dev_private;
1698 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1699 struct intel_framebuffer *intel_fb;
1700 struct drm_i915_gem_object *obj;
1701 int plane = intel_crtc->plane;
1702 unsigned long Start, Offset;
1712 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1716 intel_fb = to_intel_framebuffer(fb);
1717 obj = intel_fb->obj;
1719 reg = DSPCNTR(plane);
1720 dspcntr = I915_READ(reg);
1721 /* Mask out pixel format bits in case we change it */
1722 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1723 switch (fb->bits_per_pixel) {
1725 dspcntr |= DISPPLANE_8BPP;
1728 if (fb->depth != 16) {
1729 DRM_ERROR("bpp 16, depth %d\n", fb->depth);
1733 dspcntr |= DISPPLANE_BGRX565;
1737 if (fb->depth == 24)
1738 dspcntr |= DISPPLANE_BGRX888;
1739 else if (fb->depth == 30)
1740 dspcntr |= DISPPLANE_BGRX101010;
1742 DRM_ERROR("bpp %d depth %d\n", fb->bits_per_pixel,
1748 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1752 if (obj->tiling_mode != I915_TILING_NONE)
1753 dspcntr |= DISPPLANE_TILED;
1755 dspcntr &= ~DISPPLANE_TILED;
1758 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1760 I915_WRITE(reg, dspcntr);
1762 Start = obj->gtt_offset;
1763 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1765 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1766 Start, Offset, x, y, fb->pitches[0]);
1767 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1768 I915_WRITE(DSPSURF(plane), Start);
1769 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1770 I915_WRITE(DSPADDR(plane), Offset);
1776 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1778 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1779 int x, int y, enum mode_set_atomic state)
1781 struct drm_device *dev = crtc->dev;
1782 struct drm_i915_private *dev_priv = dev->dev_private;
1784 if (dev_priv->display.disable_fbc)
1785 dev_priv->display.disable_fbc(dev);
1786 intel_increase_pllclock(crtc);
1788 return dev_priv->display.update_plane(crtc, fb, x, y);
1792 intel_finish_fb(struct drm_framebuffer *old_fb)
1794 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1795 struct drm_device *dev = obj->base.dev;
1796 struct drm_i915_private *dev_priv = dev->dev_private;
1797 bool was_interruptible = dev_priv->mm.interruptible;
1800 /* XXX */ lockmgr(&dev->event_lock, LK_EXCLUSIVE);
1801 while (!atomic_read(&dev_priv->mm.wedged) &&
1802 atomic_read(&obj->pending_flip) != 0) {
1803 lksleep(&obj->pending_flip, &dev->event_lock,
1806 /* XXX */ lockmgr(&dev->event_lock, LK_RELEASE);
1808 /* Big Hammer, we also need to ensure that any pending
1809 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1810 * current scanout is retired before unpinning the old
1813 * This should only fail upon a hung GPU, in which case we
1814 * can safely continue.
1816 dev_priv->mm.interruptible = false;
1817 ret = i915_gem_object_finish_gpu(obj);
1818 dev_priv->mm.interruptible = was_interruptible;
1823 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1824 struct drm_framebuffer *old_fb)
1826 struct drm_device *dev = crtc->dev;
1828 struct drm_i915_master_private *master_priv;
1830 drm_i915_private_t *dev_priv = dev->dev_private;
1832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1837 DRM_ERROR("No FB bound\n");
1841 switch (intel_crtc->plane) {
1846 if (IS_IVYBRIDGE(dev))
1848 /* fall through otherwise */
1850 DRM_ERROR("no plane for crtc\n");
1855 ret = intel_pin_and_fence_fb_obj(dev,
1856 to_intel_framebuffer(crtc->fb)->obj,
1860 DRM_ERROR("pin & fence failed\n");
1865 intel_finish_fb(old_fb);
1867 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
1868 LEAVE_ATOMIC_MODE_SET);
1870 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
1872 DRM_ERROR("failed to update base address\n");
1877 intel_wait_for_vblank(dev, intel_crtc->pipe);
1878 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
1884 if (!dev->primary->master)
1887 master_priv = dev->primary->master->driver_priv;
1888 if (!master_priv->sarea_priv)
1891 if (intel_crtc->pipe) {
1892 master_priv->sarea_priv->pipeB_x = x;
1893 master_priv->sarea_priv->pipeB_y = y;
1895 master_priv->sarea_priv->pipeA_x = x;
1896 master_priv->sarea_priv->pipeA_y = y;
1900 if (!dev_priv->sarea_priv)
1903 if (intel_crtc->pipe) {
1904 dev_priv->sarea_priv->planeB_x = x;
1905 dev_priv->sarea_priv->planeB_y = y;
1907 dev_priv->sarea_priv->planeA_x = x;
1908 dev_priv->sarea_priv->planeA_y = y;
1915 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
1917 struct drm_device *dev = crtc->dev;
1918 struct drm_i915_private *dev_priv = dev->dev_private;
1921 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1922 dpa_ctl = I915_READ(DP_A);
1923 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1925 if (clock < 200000) {
1927 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1928 /* workaround for 160Mhz:
1929 1) program 0x4600c bits 15:0 = 0x8124
1930 2) program 0x46010 bit 0 = 1
1931 3) program 0x46034 bit 24 = 1
1932 4) program 0x64000 bit 14 = 1
1934 temp = I915_READ(0x4600c);
1936 I915_WRITE(0x4600c, temp | 0x8124);
1938 temp = I915_READ(0x46010);
1939 I915_WRITE(0x46010, temp | 1);
1941 temp = I915_READ(0x46034);
1942 I915_WRITE(0x46034, temp | (1 << 24));
1944 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1946 I915_WRITE(DP_A, dpa_ctl);
1952 static void intel_fdi_normal_train(struct drm_crtc *crtc)
1954 struct drm_device *dev = crtc->dev;
1955 struct drm_i915_private *dev_priv = dev->dev_private;
1956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1957 int pipe = intel_crtc->pipe;
1960 /* enable normal train */
1961 reg = FDI_TX_CTL(pipe);
1962 temp = I915_READ(reg);
1963 if (IS_IVYBRIDGE(dev)) {
1964 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
1965 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
1967 temp &= ~FDI_LINK_TRAIN_NONE;
1968 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
1970 I915_WRITE(reg, temp);
1972 reg = FDI_RX_CTL(pipe);
1973 temp = I915_READ(reg);
1974 if (HAS_PCH_CPT(dev)) {
1975 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1976 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1978 temp &= ~FDI_LINK_TRAIN_NONE;
1979 temp |= FDI_LINK_TRAIN_NONE;
1981 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1983 /* wait one idle pattern time */
1987 /* IVB wants error correction enabled */
1988 if (IS_IVYBRIDGE(dev))
1989 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
1990 FDI_FE_ERRC_ENABLE);
1993 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
1995 struct drm_i915_private *dev_priv = dev->dev_private;
1996 u32 flags = I915_READ(SOUTH_CHICKEN1);
1998 flags |= FDI_PHASE_SYNC_OVR(pipe);
1999 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2000 flags |= FDI_PHASE_SYNC_EN(pipe);
2001 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2002 POSTING_READ(SOUTH_CHICKEN1);
2005 /* The FDI link training functions for ILK/Ibexpeak. */
2006 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2008 struct drm_device *dev = crtc->dev;
2009 struct drm_i915_private *dev_priv = dev->dev_private;
2010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2011 int pipe = intel_crtc->pipe;
2012 int plane = intel_crtc->plane;
2013 u32 reg, temp, tries;
2015 /* FDI needs bits from pipe & plane first */
2016 assert_pipe_enabled(dev_priv, pipe);
2017 assert_plane_enabled(dev_priv, plane);
2019 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2021 reg = FDI_RX_IMR(pipe);
2022 temp = I915_READ(reg);
2023 temp &= ~FDI_RX_SYMBOL_LOCK;
2024 temp &= ~FDI_RX_BIT_LOCK;
2025 I915_WRITE(reg, temp);
2029 /* enable CPU FDI TX and PCH FDI RX */
2030 reg = FDI_TX_CTL(pipe);
2031 temp = I915_READ(reg);
2033 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2034 temp &= ~FDI_LINK_TRAIN_NONE;
2035 temp |= FDI_LINK_TRAIN_PATTERN_1;
2036 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2038 reg = FDI_RX_CTL(pipe);
2039 temp = I915_READ(reg);
2040 temp &= ~FDI_LINK_TRAIN_NONE;
2041 temp |= FDI_LINK_TRAIN_PATTERN_1;
2042 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2047 /* Ironlake workaround, enable clock pointer after FDI enable*/
2048 if (HAS_PCH_IBX(dev)) {
2049 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2050 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2051 FDI_RX_PHASE_SYNC_POINTER_EN);
2054 reg = FDI_RX_IIR(pipe);
2055 for (tries = 0; tries < 5; tries++) {
2056 temp = I915_READ(reg);
2057 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2059 if ((temp & FDI_RX_BIT_LOCK)) {
2060 DRM_DEBUG_KMS("FDI train 1 done.\n");
2061 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2066 DRM_ERROR("FDI train 1 fail!\n");
2069 reg = FDI_TX_CTL(pipe);
2070 temp = I915_READ(reg);
2071 temp &= ~FDI_LINK_TRAIN_NONE;
2072 temp |= FDI_LINK_TRAIN_PATTERN_2;
2073 I915_WRITE(reg, temp);
2075 reg = FDI_RX_CTL(pipe);
2076 temp = I915_READ(reg);
2077 temp &= ~FDI_LINK_TRAIN_NONE;
2078 temp |= FDI_LINK_TRAIN_PATTERN_2;
2079 I915_WRITE(reg, temp);
2084 reg = FDI_RX_IIR(pipe);
2085 for (tries = 0; tries < 5; tries++) {
2086 temp = I915_READ(reg);
2087 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2089 if (temp & FDI_RX_SYMBOL_LOCK) {
2090 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2091 DRM_DEBUG_KMS("FDI train 2 done.\n");
2096 DRM_ERROR("FDI train 2 fail!\n");
2098 DRM_DEBUG_KMS("FDI train done\n");
2102 static const int snb_b_fdi_train_param[] = {
2103 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2104 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2105 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2106 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2109 /* The FDI link training functions for SNB/Cougarpoint. */
2110 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2112 struct drm_device *dev = crtc->dev;
2113 struct drm_i915_private *dev_priv = dev->dev_private;
2114 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2115 int pipe = intel_crtc->pipe;
2118 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2120 reg = FDI_RX_IMR(pipe);
2121 temp = I915_READ(reg);
2122 temp &= ~FDI_RX_SYMBOL_LOCK;
2123 temp &= ~FDI_RX_BIT_LOCK;
2124 I915_WRITE(reg, temp);
2129 /* enable CPU FDI TX and PCH FDI RX */
2130 reg = FDI_TX_CTL(pipe);
2131 temp = I915_READ(reg);
2133 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2134 temp &= ~FDI_LINK_TRAIN_NONE;
2135 temp |= FDI_LINK_TRAIN_PATTERN_1;
2136 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2138 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2139 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2141 reg = FDI_RX_CTL(pipe);
2142 temp = I915_READ(reg);
2143 if (HAS_PCH_CPT(dev)) {
2144 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2145 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2147 temp &= ~FDI_LINK_TRAIN_NONE;
2148 temp |= FDI_LINK_TRAIN_PATTERN_1;
2150 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2155 if (HAS_PCH_CPT(dev))
2156 cpt_phase_pointer_enable(dev, pipe);
2158 for (i = 0; i < 4; i++) {
2159 reg = FDI_TX_CTL(pipe);
2160 temp = I915_READ(reg);
2161 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2162 temp |= snb_b_fdi_train_param[i];
2163 I915_WRITE(reg, temp);
2168 reg = FDI_RX_IIR(pipe);
2169 temp = I915_READ(reg);
2170 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2172 if (temp & FDI_RX_BIT_LOCK) {
2173 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2174 DRM_DEBUG_KMS("FDI train 1 done.\n");
2179 DRM_ERROR("FDI train 1 fail!\n");
2182 reg = FDI_TX_CTL(pipe);
2183 temp = I915_READ(reg);
2184 temp &= ~FDI_LINK_TRAIN_NONE;
2185 temp |= FDI_LINK_TRAIN_PATTERN_2;
2187 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2189 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2191 I915_WRITE(reg, temp);
2193 reg = FDI_RX_CTL(pipe);
2194 temp = I915_READ(reg);
2195 if (HAS_PCH_CPT(dev)) {
2196 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2197 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2199 temp &= ~FDI_LINK_TRAIN_NONE;
2200 temp |= FDI_LINK_TRAIN_PATTERN_2;
2202 I915_WRITE(reg, temp);
2207 for (i = 0; i < 4; i++) {
2208 reg = FDI_TX_CTL(pipe);
2209 temp = I915_READ(reg);
2210 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2211 temp |= snb_b_fdi_train_param[i];
2212 I915_WRITE(reg, temp);
2217 reg = FDI_RX_IIR(pipe);
2218 temp = I915_READ(reg);
2219 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2221 if (temp & FDI_RX_SYMBOL_LOCK) {
2222 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2223 DRM_DEBUG_KMS("FDI train 2 done.\n");
2228 DRM_ERROR("FDI train 2 fail!\n");
2230 DRM_DEBUG_KMS("FDI train done.\n");
2233 /* Manual link training for Ivy Bridge A0 parts */
2234 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2236 struct drm_device *dev = crtc->dev;
2237 struct drm_i915_private *dev_priv = dev->dev_private;
2238 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2239 int pipe = intel_crtc->pipe;
2242 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2244 reg = FDI_RX_IMR(pipe);
2245 temp = I915_READ(reg);
2246 temp &= ~FDI_RX_SYMBOL_LOCK;
2247 temp &= ~FDI_RX_BIT_LOCK;
2248 I915_WRITE(reg, temp);
2253 /* enable CPU FDI TX and PCH FDI RX */
2254 reg = FDI_TX_CTL(pipe);
2255 temp = I915_READ(reg);
2257 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2258 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2259 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2260 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2261 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2262 temp |= FDI_COMPOSITE_SYNC;
2263 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2265 reg = FDI_RX_CTL(pipe);
2266 temp = I915_READ(reg);
2267 temp &= ~FDI_LINK_TRAIN_AUTO;
2268 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2269 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2270 temp |= FDI_COMPOSITE_SYNC;
2271 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2276 for (i = 0; i < 4; i++) {
2277 reg = FDI_TX_CTL(pipe);
2278 temp = I915_READ(reg);
2279 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2280 temp |= snb_b_fdi_train_param[i];
2281 I915_WRITE(reg, temp);
2286 reg = FDI_RX_IIR(pipe);
2287 temp = I915_READ(reg);
2288 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2290 if (temp & FDI_RX_BIT_LOCK ||
2291 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2292 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2293 DRM_DEBUG_KMS("FDI train 1 done.\n");
2298 DRM_ERROR("FDI train 1 fail!\n");
2301 reg = FDI_TX_CTL(pipe);
2302 temp = I915_READ(reg);
2303 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2304 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2305 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2306 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2307 I915_WRITE(reg, temp);
2309 reg = FDI_RX_CTL(pipe);
2310 temp = I915_READ(reg);
2311 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2312 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2313 I915_WRITE(reg, temp);
2318 for (i = 0; i < 4; i++ ) {
2319 reg = FDI_TX_CTL(pipe);
2320 temp = I915_READ(reg);
2321 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2322 temp |= snb_b_fdi_train_param[i];
2323 I915_WRITE(reg, temp);
2328 reg = FDI_RX_IIR(pipe);
2329 temp = I915_READ(reg);
2330 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2332 if (temp & FDI_RX_SYMBOL_LOCK) {
2333 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2334 DRM_DEBUG_KMS("FDI train 2 done.\n");
2339 DRM_ERROR("FDI train 2 fail!\n");
2341 DRM_DEBUG_KMS("FDI train done.\n");
2344 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2346 struct drm_device *dev = crtc->dev;
2347 struct drm_i915_private *dev_priv = dev->dev_private;
2348 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2349 int pipe = intel_crtc->pipe;
2352 /* Write the TU size bits so error detection works */
2353 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2354 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2356 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2357 reg = FDI_RX_CTL(pipe);
2358 temp = I915_READ(reg);
2359 temp &= ~((0x7 << 19) | (0x7 << 16));
2360 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2361 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2362 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2367 /* Switch from Rawclk to PCDclk */
2368 temp = I915_READ(reg);
2369 I915_WRITE(reg, temp | FDI_PCDCLK);
2374 /* Enable CPU FDI TX PLL, always on for Ironlake */
2375 reg = FDI_TX_CTL(pipe);
2376 temp = I915_READ(reg);
2377 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2378 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2385 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2387 struct drm_i915_private *dev_priv = dev->dev_private;
2388 u32 flags = I915_READ(SOUTH_CHICKEN1);
2390 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2391 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2392 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2393 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2394 POSTING_READ(SOUTH_CHICKEN1);
2397 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2399 struct drm_device *dev = crtc->dev;
2400 struct drm_i915_private *dev_priv = dev->dev_private;
2401 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2402 int pipe = intel_crtc->pipe;
2405 /* disable CPU FDI tx and PCH FDI rx */
2406 reg = FDI_TX_CTL(pipe);
2407 temp = I915_READ(reg);
2408 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2411 reg = FDI_RX_CTL(pipe);
2412 temp = I915_READ(reg);
2413 temp &= ~(0x7 << 16);
2414 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2415 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2420 /* Ironlake workaround, disable clock pointer after downing FDI */
2421 if (HAS_PCH_IBX(dev)) {
2422 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2423 I915_WRITE(FDI_RX_CHICKEN(pipe),
2424 I915_READ(FDI_RX_CHICKEN(pipe) &
2425 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2426 } else if (HAS_PCH_CPT(dev)) {
2427 cpt_phase_pointer_disable(dev, pipe);
2430 /* still set train pattern 1 */
2431 reg = FDI_TX_CTL(pipe);
2432 temp = I915_READ(reg);
2433 temp &= ~FDI_LINK_TRAIN_NONE;
2434 temp |= FDI_LINK_TRAIN_PATTERN_1;
2435 I915_WRITE(reg, temp);
2437 reg = FDI_RX_CTL(pipe);
2438 temp = I915_READ(reg);
2439 if (HAS_PCH_CPT(dev)) {
2440 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2441 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2443 temp &= ~FDI_LINK_TRAIN_NONE;
2444 temp |= FDI_LINK_TRAIN_PATTERN_1;
2446 /* BPC in FDI rx is consistent with that in PIPECONF */
2447 temp &= ~(0x07 << 16);
2448 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2449 I915_WRITE(reg, temp);
2456 * When we disable a pipe, we need to clear any pending scanline wait events
2457 * to avoid hanging the ring, which we assume we are waiting on.
2459 static void intel_clear_scanline_wait(struct drm_device *dev)
2461 struct drm_i915_private *dev_priv = dev->dev_private;
2462 struct intel_ring_buffer *ring;
2466 /* Can't break the hang on i8xx */
2469 ring = LP_RING(dev_priv);
2470 tmp = I915_READ_CTL(ring);
2471 if (tmp & RING_WAIT)
2472 I915_WRITE_CTL(ring, tmp);
2475 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2477 struct drm_i915_gem_object *obj;
2478 struct drm_i915_private *dev_priv;
2479 struct drm_device *dev;
2481 if (crtc->fb == NULL)
2484 obj = to_intel_framebuffer(crtc->fb)->obj;
2486 dev_priv = dev->dev_private;
2487 lockmgr(&dev->event_lock, LK_EXCLUSIVE);
2488 while (atomic_read(&obj->pending_flip) != 0)
2489 lksleep(&obj->pending_flip, &dev->event_lock, 0, "915wfl", 0);
2490 lockmgr(&dev->event_lock, LK_RELEASE);
2493 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2495 struct drm_device *dev = crtc->dev;
2496 struct drm_mode_config *mode_config = &dev->mode_config;
2497 struct intel_encoder *encoder;
2500 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2501 * must be driven by its own crtc; no sharing is possible.
2503 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2504 if (encoder->base.crtc != crtc)
2507 switch (encoder->type) {
2508 case INTEL_OUTPUT_EDP:
2509 if (!intel_encoder_is_pch_edp(&encoder->base))
2519 * Enable PCH resources required for PCH ports:
2521 * - FDI training & RX/TX
2522 * - update transcoder timings
2523 * - DP transcoding bits
2526 static void ironlake_pch_enable(struct drm_crtc *crtc)
2528 struct drm_device *dev = crtc->dev;
2529 struct drm_i915_private *dev_priv = dev->dev_private;
2530 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2531 int pipe = intel_crtc->pipe;
2532 u32 reg, temp, transc_sel;
2534 /* For PCH output, training FDI link */
2535 dev_priv->display.fdi_link_train(crtc);
2537 intel_enable_pch_pll(dev_priv, pipe);
2539 if (HAS_PCH_CPT(dev)) {
2540 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2543 /* Be sure PCH DPLL SEL is set */
2544 temp = I915_READ(PCH_DPLL_SEL);
2546 temp &= ~(TRANSA_DPLLB_SEL);
2547 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2548 } else if (pipe == 1) {
2549 temp &= ~(TRANSB_DPLLB_SEL);
2550 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2551 } else if (pipe == 2) {
2552 temp &= ~(TRANSC_DPLLB_SEL);
2553 temp |= (TRANSC_DPLL_ENABLE | transc_sel);
2555 I915_WRITE(PCH_DPLL_SEL, temp);
2558 /* set transcoder timing, panel must allow it */
2559 assert_panel_unlocked(dev_priv, pipe);
2560 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2561 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2562 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2564 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2565 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2566 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2567 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
2569 intel_fdi_normal_train(crtc);
2571 /* For PCH DP, enable TRANS_DP_CTL */
2572 if (HAS_PCH_CPT(dev) &&
2573 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2574 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2575 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2576 reg = TRANS_DP_CTL(pipe);
2577 temp = I915_READ(reg);
2578 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2579 TRANS_DP_SYNC_MASK |
2581 temp |= (TRANS_DP_OUTPUT_ENABLE |
2582 TRANS_DP_ENH_FRAMING);
2583 temp |= bpc << 9; /* same format but at 11:9 */
2585 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2586 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2587 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2588 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2590 switch (intel_trans_dp_port_sel(crtc)) {
2592 temp |= TRANS_DP_PORT_SEL_B;
2595 temp |= TRANS_DP_PORT_SEL_C;
2598 temp |= TRANS_DP_PORT_SEL_D;
2601 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2602 temp |= TRANS_DP_PORT_SEL_B;
2606 I915_WRITE(reg, temp);
2609 intel_enable_transcoder(dev_priv, pipe);
2612 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2614 struct drm_i915_private *dev_priv = dev->dev_private;
2615 int dslreg = PIPEDSL(pipe);
2618 temp = I915_READ(dslreg);
2620 if (wait_for(I915_READ(dslreg) != temp, 5)) {
2621 if (wait_for(I915_READ(dslreg) != temp, 5))
2622 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
2626 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2628 struct drm_device *dev = crtc->dev;
2629 struct drm_i915_private *dev_priv = dev->dev_private;
2630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2631 int pipe = intel_crtc->pipe;
2632 int plane = intel_crtc->plane;
2636 if (intel_crtc->active)
2639 intel_crtc->active = true;
2640 intel_update_watermarks(dev);
2642 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2643 temp = I915_READ(PCH_LVDS);
2644 if ((temp & LVDS_PORT_EN) == 0)
2645 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2648 is_pch_port = intel_crtc_driving_pch(crtc);
2651 ironlake_fdi_pll_enable(crtc);
2653 ironlake_fdi_disable(crtc);
2655 /* Enable panel fitting for LVDS */
2656 if (dev_priv->pch_pf_size &&
2657 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2658 /* Force use of hard-coded filter coefficients
2659 * as some pre-programmed values are broken,
2662 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2663 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2664 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
2667 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2668 intel_enable_plane(dev_priv, plane, pipe);
2671 ironlake_pch_enable(crtc);
2673 intel_crtc_load_lut(crtc);
2676 intel_update_fbc(dev);
2679 intel_crtc_update_cursor(crtc, true);
2682 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2684 struct drm_device *dev = crtc->dev;
2685 struct drm_i915_private *dev_priv = dev->dev_private;
2686 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2687 int pipe = intel_crtc->pipe;
2688 int plane = intel_crtc->plane;
2691 if (!intel_crtc->active)
2694 intel_crtc_wait_for_pending_flips(crtc);
2695 drm_vblank_off(dev, pipe);
2696 intel_crtc_update_cursor(crtc, false);
2698 intel_disable_plane(dev_priv, plane, pipe);
2700 if (dev_priv->cfb_plane == plane)
2701 intel_disable_fbc(dev);
2703 intel_disable_pipe(dev_priv, pipe);
2706 I915_WRITE(PF_CTL(pipe), 0);
2707 I915_WRITE(PF_WIN_SZ(pipe), 0);
2709 ironlake_fdi_disable(crtc);
2711 /* This is a horrible layering violation; we should be doing this in
2712 * the connector/encoder ->prepare instead, but we don't always have
2713 * enough information there about the config to know whether it will
2714 * actually be necessary or just cause undesired flicker.
2716 intel_disable_pch_ports(dev_priv, pipe);
2718 intel_disable_transcoder(dev_priv, pipe);
2720 if (HAS_PCH_CPT(dev)) {
2721 /* disable TRANS_DP_CTL */
2722 reg = TRANS_DP_CTL(pipe);
2723 temp = I915_READ(reg);
2724 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2725 temp |= TRANS_DP_PORT_SEL_NONE;
2726 I915_WRITE(reg, temp);
2728 /* disable DPLL_SEL */
2729 temp = I915_READ(PCH_DPLL_SEL);
2732 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2735 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2738 /* C shares PLL A or B */
2739 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2742 KASSERT(1, ("Wrong pipe %d", pipe)); /* wtf */
2744 I915_WRITE(PCH_DPLL_SEL, temp);
2747 /* disable PCH DPLL */
2748 if (!intel_crtc->no_pll)
2749 intel_disable_pch_pll(dev_priv, pipe);
2751 /* Switch from PCDclk to Rawclk */
2752 reg = FDI_RX_CTL(pipe);
2753 temp = I915_READ(reg);
2754 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2756 /* Disable CPU FDI TX PLL */
2757 reg = FDI_TX_CTL(pipe);
2758 temp = I915_READ(reg);
2759 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2764 reg = FDI_RX_CTL(pipe);
2765 temp = I915_READ(reg);
2766 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2768 /* Wait for the clocks to turn off. */
2772 intel_crtc->active = false;
2773 intel_update_watermarks(dev);
2776 intel_update_fbc(dev);
2777 intel_clear_scanline_wait(dev);
2781 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2783 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2784 int pipe = intel_crtc->pipe;
2785 int plane = intel_crtc->plane;
2787 /* XXX: When our outputs are all unaware of DPMS modes other than off
2788 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2791 case DRM_MODE_DPMS_ON:
2792 case DRM_MODE_DPMS_STANDBY:
2793 case DRM_MODE_DPMS_SUSPEND:
2794 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2795 ironlake_crtc_enable(crtc);
2798 case DRM_MODE_DPMS_OFF:
2799 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2800 ironlake_crtc_disable(crtc);
2805 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2807 if (!enable && intel_crtc->overlay) {
2808 struct drm_device *dev = intel_crtc->base.dev;
2809 struct drm_i915_private *dev_priv = dev->dev_private;
2812 dev_priv->mm.interruptible = false;
2813 (void) intel_overlay_switch_off(intel_crtc->overlay);
2814 dev_priv->mm.interruptible = true;
2818 /* Let userspace switch the overlay on again. In most cases userspace
2819 * has to recompute where to put it anyway.
2823 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2825 struct drm_device *dev = crtc->dev;
2826 struct drm_i915_private *dev_priv = dev->dev_private;
2827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2828 int pipe = intel_crtc->pipe;
2829 int plane = intel_crtc->plane;
2831 if (intel_crtc->active)
2834 intel_crtc->active = true;
2835 intel_update_watermarks(dev);
2837 intel_enable_pll(dev_priv, pipe);
2838 intel_enable_pipe(dev_priv, pipe, false);
2839 intel_enable_plane(dev_priv, plane, pipe);
2841 intel_crtc_load_lut(crtc);
2842 intel_update_fbc(dev);
2844 /* Give the overlay scaler a chance to enable if it's on this pipe */
2845 intel_crtc_dpms_overlay(intel_crtc, true);
2846 intel_crtc_update_cursor(crtc, true);
2849 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2851 struct drm_device *dev = crtc->dev;
2852 struct drm_i915_private *dev_priv = dev->dev_private;
2853 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2854 int pipe = intel_crtc->pipe;
2855 int plane = intel_crtc->plane;
2857 if (!intel_crtc->active)
2860 /* Give the overlay scaler a chance to disable if it's on this pipe */
2861 intel_crtc_wait_for_pending_flips(crtc);
2862 drm_vblank_off(dev, pipe);
2863 intel_crtc_dpms_overlay(intel_crtc, false);
2864 intel_crtc_update_cursor(crtc, false);
2866 if (dev_priv->cfb_plane == plane)
2867 intel_disable_fbc(dev);
2869 intel_disable_plane(dev_priv, plane, pipe);
2870 intel_disable_pipe(dev_priv, pipe);
2871 intel_disable_pll(dev_priv, pipe);
2873 intel_crtc->active = false;
2874 intel_update_fbc(dev);
2875 intel_update_watermarks(dev);
2876 intel_clear_scanline_wait(dev);
2879 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2881 /* XXX: When our outputs are all unaware of DPMS modes other than off
2882 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2885 case DRM_MODE_DPMS_ON:
2886 case DRM_MODE_DPMS_STANDBY:
2887 case DRM_MODE_DPMS_SUSPEND:
2888 i9xx_crtc_enable(crtc);
2890 case DRM_MODE_DPMS_OFF:
2891 i9xx_crtc_disable(crtc);
2897 * Sets the power management mode of the pipe and plane.
2899 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2901 struct drm_device *dev = crtc->dev;
2902 struct drm_i915_private *dev_priv = dev->dev_private;
2904 struct drm_i915_master_private *master_priv;
2906 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2907 int pipe = intel_crtc->pipe;
2910 if (intel_crtc->dpms_mode == mode)
2913 intel_crtc->dpms_mode = mode;
2915 dev_priv->display.dpms(crtc, mode);
2918 if (!dev->primary->master)
2921 master_priv = dev->primary->master->driver_priv;
2922 if (!master_priv->sarea_priv)
2925 if (!dev_priv->sarea_priv)
2929 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2934 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2935 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2937 dev_priv->sarea_priv->planeA_w = enabled ? crtc->mode.hdisplay : 0;
2938 dev_priv->sarea_priv->planeA_h = enabled ? crtc->mode.vdisplay : 0;
2943 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2944 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2946 dev_priv->sarea_priv->planeB_w = enabled ? crtc->mode.hdisplay : 0;
2947 dev_priv->sarea_priv->planeB_h = enabled ? crtc->mode.vdisplay : 0;
2951 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
2956 static void intel_crtc_disable(struct drm_crtc *crtc)
2958 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2959 struct drm_device *dev = crtc->dev;
2961 /* Flush any pending WAITs before we disable the pipe. Note that
2962 * we need to drop the struct_mutex in order to acquire it again
2963 * during the lowlevel dpms routines around a couple of the
2964 * operations. It does not look trivial nor desirable to move
2965 * that locking higher. So instead we leave a window for the
2966 * submission of further commands on the fb before we can actually
2967 * disable it. This race with userspace exists anyway, and we can
2968 * only rely on the pipe being disabled by userspace after it
2969 * receives the hotplug notification and has flushed any pending
2974 intel_finish_fb(crtc->fb);
2978 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2979 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
2980 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
2984 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2989 /* Prepare for a mode set.
2991 * Note we could be a lot smarter here. We need to figure out which outputs
2992 * will be enabled, which disabled (in short, how the config will changes)
2993 * and perform the minimum necessary steps to accomplish that, e.g. updating
2994 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2995 * panel fitting is in the proper state, etc.
2997 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
2999 i9xx_crtc_disable(crtc);
3002 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3004 i9xx_crtc_enable(crtc);
3007 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3009 ironlake_crtc_disable(crtc);
3012 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3014 ironlake_crtc_enable(crtc);
3017 void intel_encoder_prepare(struct drm_encoder *encoder)
3019 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3020 /* lvds has its own version of prepare see intel_lvds_prepare */
3021 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3024 void intel_encoder_commit(struct drm_encoder *encoder)
3026 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3027 struct drm_device *dev = encoder->dev;
3028 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3029 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3031 /* lvds has its own version of commit see intel_lvds_commit */
3032 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3034 if (HAS_PCH_CPT(dev))
3035 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3038 void intel_encoder_destroy(struct drm_encoder *encoder)
3040 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3042 drm_encoder_cleanup(encoder);
3043 drm_free(intel_encoder, DRM_MEM_KMS);
3046 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3047 const struct drm_display_mode *mode,
3048 struct drm_display_mode *adjusted_mode)
3050 struct drm_device *dev = crtc->dev;
3052 if (HAS_PCH_SPLIT(dev)) {
3053 /* FDI link clock is fixed at 2.7G */
3054 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3058 /* All interlaced capable intel hw wants timings in frames. Note though
3059 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3060 * timings, so we need to be careful not to clobber these.*/
3061 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3062 drm_mode_set_crtcinfo(adjusted_mode, 0);
3067 static int i945_get_display_clock_speed(struct drm_device *dev)
3072 static int i915_get_display_clock_speed(struct drm_device *dev)
3077 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3082 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3086 gcfgc = pci_read_config(dev->dev, GCFGC, 2);
3088 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3091 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3092 case GC_DISPLAY_CLOCK_333_MHZ:
3095 case GC_DISPLAY_CLOCK_190_200_MHZ:
3101 static int i865_get_display_clock_speed(struct drm_device *dev)
3106 static int i855_get_display_clock_speed(struct drm_device *dev)
3109 /* Assume that the hardware is in the high speed state. This
3110 * should be the default.
3112 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3113 case GC_CLOCK_133_200:
3114 case GC_CLOCK_100_200:
3116 case GC_CLOCK_166_250:
3118 case GC_CLOCK_100_133:
3122 /* Shouldn't happen */
3126 static int i830_get_display_clock_speed(struct drm_device *dev)
3140 fdi_reduce_ratio(u32 *num, u32 *den)
3142 while (*num > 0xffffff || *den > 0xffffff) {
3149 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3150 int link_clock, struct fdi_m_n *m_n)
3152 m_n->tu = 64; /* default size */
3154 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3155 m_n->gmch_m = bits_per_pixel * pixel_clock;
3156 m_n->gmch_n = link_clock * nlanes * 8;
3157 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3159 m_n->link_m = pixel_clock;
3160 m_n->link_n = link_clock;
3161 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3164 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3166 if (i915_panel_use_ssc >= 0)
3167 return i915_panel_use_ssc != 0;
3168 return dev_priv->lvds_use_ssc
3169 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3173 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3174 * @crtc: CRTC structure
3175 * @mode: requested mode
3177 * A pipe may be connected to one or more outputs. Based on the depth of the
3178 * attached framebuffer, choose a good color depth to use on the pipe.
3180 * If possible, match the pipe depth to the fb depth. In some cases, this
3181 * isn't ideal, because the connected output supports a lesser or restricted
3182 * set of depths. Resolve that here:
3183 * LVDS typically supports only 6bpc, so clamp down in that case
3184 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3185 * Displays may support a restricted set as well, check EDID and clamp as
3187 * DP may want to dither down to 6bpc to fit larger modes
3190 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3191 * true if they don't match).
3193 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3194 unsigned int *pipe_bpp,
3195 struct drm_display_mode *mode)
3197 struct drm_device *dev = crtc->dev;
3198 struct drm_i915_private *dev_priv = dev->dev_private;
3199 struct drm_encoder *encoder;
3200 struct drm_connector *connector;
3201 unsigned int display_bpc = UINT_MAX, bpc;
3203 /* Walk the encoders & connectors on this crtc, get min bpc */
3204 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3205 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3207 if (encoder->crtc != crtc)
3210 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3211 unsigned int lvds_bpc;
3213 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3219 if (lvds_bpc < display_bpc) {
3220 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3221 display_bpc = lvds_bpc;
3226 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
3227 /* Use VBT settings if we have an eDP panel */
3228 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
3230 if (edp_bpc < display_bpc) {
3231 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
3232 display_bpc = edp_bpc;
3237 /* Not one of the known troublemakers, check the EDID */
3238 list_for_each_entry(connector, &dev->mode_config.connector_list,
3240 if (connector->encoder != encoder)
3243 /* Don't use an invalid EDID bpc value */
3244 if (connector->display_info.bpc &&
3245 connector->display_info.bpc < display_bpc) {
3246 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3247 display_bpc = connector->display_info.bpc;
3252 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3253 * through, clamp it down. (Note: >12bpc will be caught below.)
3255 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3256 if (display_bpc > 8 && display_bpc < 12) {
3257 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3260 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3266 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3267 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3272 * We could just drive the pipe at the highest bpc all the time and
3273 * enable dithering as needed, but that costs bandwidth. So choose
3274 * the minimum value that expresses the full color range of the fb but
3275 * also stays within the max display bpc discovered above.
3278 switch (crtc->fb->depth) {
3280 bpc = 8; /* since we go through a colormap */
3284 bpc = 6; /* min is 18bpp */
3296 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3297 bpc = min((unsigned int)8, display_bpc);
3301 display_bpc = min(display_bpc, bpc);
3303 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3306 *pipe_bpp = display_bpc * 3;
3308 return display_bpc != bpc;
3311 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3313 struct drm_device *dev = crtc->dev;
3314 struct drm_i915_private *dev_priv = dev->dev_private;
3317 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3318 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3319 refclk = dev_priv->lvds_ssc_freq * 1000;
3320 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3322 } else if (!IS_GEN2(dev)) {
3331 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3332 intel_clock_t *clock)
3334 /* SDVO TV has fixed PLL values depend on its clock range,
3335 this mirrors vbios setting. */
3336 if (adjusted_mode->clock >= 100000
3337 && adjusted_mode->clock < 140500) {
3343 } else if (adjusted_mode->clock >= 140500
3344 && adjusted_mode->clock <= 200000) {
3353 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3354 intel_clock_t *clock,
3355 intel_clock_t *reduced_clock)
3357 struct drm_device *dev = crtc->dev;
3358 struct drm_i915_private *dev_priv = dev->dev_private;
3359 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3360 int pipe = intel_crtc->pipe;
3363 if (IS_PINEVIEW(dev)) {
3364 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3366 fp2 = (1 << reduced_clock->n) << 16 |
3367 reduced_clock->m1 << 8 | reduced_clock->m2;
3369 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3371 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3375 I915_WRITE(FP0(pipe), fp);
3377 intel_crtc->lowfreq_avail = false;
3378 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3379 reduced_clock && i915_powersave) {
3380 I915_WRITE(FP1(pipe), fp2);
3381 intel_crtc->lowfreq_avail = true;
3383 I915_WRITE(FP1(pipe), fp);
3387 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
3388 struct drm_display_mode *mode,
3389 struct drm_display_mode *adjusted_mode,
3391 struct drm_framebuffer *old_fb)
3393 struct drm_device *dev = crtc->dev;
3394 struct drm_i915_private *dev_priv = dev->dev_private;
3395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3396 int pipe = intel_crtc->pipe;
3397 int plane = intel_crtc->plane;
3398 int refclk, num_connectors = 0;
3399 intel_clock_t clock, reduced_clock;
3400 u32 dpll, dspcntr, pipeconf, vsyncshift;
3401 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3402 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3403 struct drm_mode_config *mode_config = &dev->mode_config;
3404 struct intel_encoder *encoder;
3405 const intel_limit_t *limit;
3410 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3411 if (encoder->base.crtc != crtc)
3414 switch (encoder->type) {
3415 case INTEL_OUTPUT_LVDS:
3418 case INTEL_OUTPUT_SDVO:
3419 case INTEL_OUTPUT_HDMI:
3421 if (encoder->needs_tv_clock)
3424 case INTEL_OUTPUT_DVO:
3427 case INTEL_OUTPUT_TVOUT:
3430 case INTEL_OUTPUT_ANALOG:
3433 case INTEL_OUTPUT_DISPLAYPORT:
3441 refclk = i9xx_get_refclk(crtc, num_connectors);
3444 * Returns a set of divisors for the desired target clock with the given
3445 * refclk, or false. The returned values represent the clock equation:
3446 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3448 limit = intel_limit(crtc, refclk);
3449 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
3452 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3456 /* Ensure that the cursor is valid for the new mode before changing... */
3457 intel_crtc_update_cursor(crtc, true);
3459 if (is_lvds && dev_priv->lvds_downclock_avail) {
3461 * Ensure we match the reduced clock's P to the target clock.
3462 * If the clocks don't match, we can't switch the display clock
3463 * by using the FP0/FP1. In such case we will disable the LVDS
3464 * downclock feature.
3466 has_reduced_clock = limit->find_pll(limit, crtc,
3467 dev_priv->lvds_downclock,
3473 if (is_sdvo && is_tv)
3474 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
3476 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
3477 &reduced_clock : NULL);
3479 dpll = DPLL_VGA_MODE_DIS;
3481 if (!IS_GEN2(dev)) {
3483 dpll |= DPLLB_MODE_LVDS;
3485 dpll |= DPLLB_MODE_DAC_SERIAL;
3487 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3488 if (pixel_multiplier > 1) {
3489 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3490 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3492 dpll |= DPLL_DVO_HIGH_SPEED;
3495 dpll |= DPLL_DVO_HIGH_SPEED;
3497 /* compute bitmask from p1 value */
3498 if (IS_PINEVIEW(dev))
3499 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3501 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3502 if (IS_G4X(dev) && has_reduced_clock)
3503 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3507 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3510 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3513 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3516 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3519 if (INTEL_INFO(dev)->gen >= 4)
3520 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3523 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3526 dpll |= PLL_P1_DIVIDE_BY_TWO;
3528 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3530 dpll |= PLL_P2_DIVIDE_BY_4;
3534 if (is_sdvo && is_tv)
3535 dpll |= PLL_REF_INPUT_TVCLKINBC;
3537 /* XXX: just matching BIOS for now */
3538 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3540 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3541 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3543 dpll |= PLL_REF_INPUT_DREFCLK;
3545 /* setup pipeconf */
3546 pipeconf = I915_READ(PIPECONF(pipe));
3548 /* Set up the display plane register */
3549 dspcntr = DISPPLANE_GAMMA_ENABLE;
3552 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3554 dspcntr |= DISPPLANE_SEL_PIPE_B;
3556 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
3557 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3560 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3564 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3565 pipeconf |= PIPECONF_DOUBLE_WIDE;
3567 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
3570 /* default to 8bpc */
3571 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
3573 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3574 pipeconf |= PIPECONF_BPP_6 |
3575 PIPECONF_DITHER_EN |
3576 PIPECONF_DITHER_TYPE_SP;
3580 dpll |= DPLL_VCO_ENABLE;
3582 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3583 drm_mode_debug_printmodeline(mode);
3585 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3587 POSTING_READ(DPLL(pipe));
3590 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3591 * This is an exception to the general rule that mode_set doesn't turn
3595 temp = I915_READ(LVDS);
3596 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3598 temp |= LVDS_PIPEB_SELECT;
3600 temp &= ~LVDS_PIPEB_SELECT;
3602 /* set the corresponsding LVDS_BORDER bit */
3603 temp |= dev_priv->lvds_border_bits;
3604 /* Set the B0-B3 data pairs corresponding to whether we're going to
3605 * set the DPLLs for dual-channel mode or not.
3608 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3610 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3612 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3613 * appropriately here, but we need to look more thoroughly into how
3614 * panels behave in the two modes.
3616 /* set the dithering flag on LVDS as needed */
3617 if (INTEL_INFO(dev)->gen >= 4) {
3618 if (dev_priv->lvds_dither)
3619 temp |= LVDS_ENABLE_DITHER;
3621 temp &= ~LVDS_ENABLE_DITHER;
3623 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
3624 lvds_sync |= LVDS_HSYNC_POLARITY;
3625 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
3626 lvds_sync |= LVDS_VSYNC_POLARITY;
3627 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
3629 char flags[2] = "-+";
3630 DRM_INFO("Changing LVDS panel from "
3631 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
3632 flags[!(temp & LVDS_HSYNC_POLARITY)],
3633 flags[!(temp & LVDS_VSYNC_POLARITY)],
3634 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
3635 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
3636 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
3639 I915_WRITE(LVDS, temp);
3643 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3646 I915_WRITE(DPLL(pipe), dpll);
3648 /* Wait for the clocks to stabilize. */
3649 POSTING_READ(DPLL(pipe));
3652 if (INTEL_INFO(dev)->gen >= 4) {
3655 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
3657 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
3661 I915_WRITE(DPLL_MD(pipe), temp);
3663 /* The pixel multiplier can only be updated once the
3664 * DPLL is enabled and the clocks are stable.
3666 * So write it again.
3668 I915_WRITE(DPLL(pipe), dpll);
3671 if (HAS_PIPE_CXSR(dev)) {
3672 if (intel_crtc->lowfreq_avail) {
3673 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3674 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3676 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3677 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3681 pipeconf &= ~PIPECONF_INTERLACE_MASK;
3682 if (!IS_GEN2(dev) &&
3683 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
3684 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
3685 /* the chip adds 2 halflines automatically */
3686 adjusted_mode->crtc_vtotal -= 1;
3687 adjusted_mode->crtc_vblank_end -= 1;
3688 vsyncshift = adjusted_mode->crtc_hsync_start
3689 - adjusted_mode->crtc_htotal/2;
3691 pipeconf |= PIPECONF_PROGRESSIVE;
3696 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
3698 I915_WRITE(HTOTAL(pipe),
3699 (adjusted_mode->crtc_hdisplay - 1) |
3700 ((adjusted_mode->crtc_htotal - 1) << 16));
3701 I915_WRITE(HBLANK(pipe),
3702 (adjusted_mode->crtc_hblank_start - 1) |
3703 ((adjusted_mode->crtc_hblank_end - 1) << 16));
3704 I915_WRITE(HSYNC(pipe),
3705 (adjusted_mode->crtc_hsync_start - 1) |
3706 ((adjusted_mode->crtc_hsync_end - 1) << 16));
3708 I915_WRITE(VTOTAL(pipe),
3709 (adjusted_mode->crtc_vdisplay - 1) |
3710 ((adjusted_mode->crtc_vtotal - 1) << 16));
3711 I915_WRITE(VBLANK(pipe),
3712 (adjusted_mode->crtc_vblank_start - 1) |
3713 ((adjusted_mode->crtc_vblank_end - 1) << 16));
3714 I915_WRITE(VSYNC(pipe),
3715 (adjusted_mode->crtc_vsync_start - 1) |
3716 ((adjusted_mode->crtc_vsync_end - 1) << 16));
3718 /* pipesrc and dspsize control the size that is scaled from,
3719 * which should always be the user's requested size.
3721 I915_WRITE(DSPSIZE(plane),
3722 ((mode->vdisplay - 1) << 16) |
3723 (mode->hdisplay - 1));
3724 I915_WRITE(DSPPOS(plane), 0);
3725 I915_WRITE(PIPESRC(pipe),
3726 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3728 I915_WRITE(PIPECONF(pipe), pipeconf);
3729 POSTING_READ(PIPECONF(pipe));
3730 intel_enable_pipe(dev_priv, pipe, false);
3732 intel_wait_for_vblank(dev, pipe);
3734 I915_WRITE(DSPCNTR(plane), dspcntr);
3735 POSTING_READ(DSPCNTR(plane));
3736 intel_enable_plane(dev_priv, plane, pipe);
3738 ret = intel_pipe_set_base(crtc, x, y, old_fb);
3740 intel_update_watermarks(dev);
3746 * Initialize reference clocks when the driver loads
3748 void ironlake_init_pch_refclk(struct drm_device *dev)
3750 struct drm_i915_private *dev_priv = dev->dev_private;
3751 struct drm_mode_config *mode_config = &dev->mode_config;
3752 struct intel_encoder *encoder;
3754 bool has_lvds = false;
3755 bool has_cpu_edp = false;
3756 bool has_pch_edp = false;
3757 bool has_panel = false;
3758 bool has_ck505 = false;
3759 bool can_ssc = false;
3761 /* We need to take the global config into account */
3762 list_for_each_entry(encoder, &mode_config->encoder_list,
3764 switch (encoder->type) {
3765 case INTEL_OUTPUT_LVDS:
3769 case INTEL_OUTPUT_EDP:
3771 if (intel_encoder_is_pch_edp(&encoder->base))
3779 if (HAS_PCH_IBX(dev)) {
3780 has_ck505 = dev_priv->display_clock_mode;
3781 can_ssc = has_ck505;
3787 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
3788 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
3791 /* Ironlake: try to setup display ref clock before DPLL
3792 * enabling. This is only under driver's control after
3793 * PCH B stepping, previous chipset stepping should be
3794 * ignoring this setting.
3796 temp = I915_READ(PCH_DREF_CONTROL);
3797 /* Always enable nonspread source */
3798 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3801 temp |= DREF_NONSPREAD_CK505_ENABLE;
3803 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3806 temp &= ~DREF_SSC_SOURCE_MASK;
3807 temp |= DREF_SSC_SOURCE_ENABLE;
3809 /* SSC must be turned on before enabling the CPU output */
3810 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
3811 DRM_DEBUG_KMS("Using SSC on panel\n");
3812 temp |= DREF_SSC1_ENABLE;
3814 temp &= ~DREF_SSC1_ENABLE;
3816 /* Get SSC going before enabling the outputs */
3817 I915_WRITE(PCH_DREF_CONTROL, temp);
3818 POSTING_READ(PCH_DREF_CONTROL);
3821 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3823 /* Enable CPU source on CPU attached eDP */
3825 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
3826 DRM_DEBUG_KMS("Using SSC on eDP\n");
3827 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3830 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3832 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
3834 I915_WRITE(PCH_DREF_CONTROL, temp);
3835 POSTING_READ(PCH_DREF_CONTROL);
3838 DRM_DEBUG_KMS("Disabling SSC entirely\n");
3840 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3842 /* Turn off CPU output */
3843 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
3845 I915_WRITE(PCH_DREF_CONTROL, temp);
3846 POSTING_READ(PCH_DREF_CONTROL);
3849 /* Turn off the SSC source */
3850 temp &= ~DREF_SSC_SOURCE_MASK;
3851 temp |= DREF_SSC_SOURCE_DISABLE;
3854 temp &= ~ DREF_SSC1_ENABLE;
3856 I915_WRITE(PCH_DREF_CONTROL, temp);
3857 POSTING_READ(PCH_DREF_CONTROL);
3862 static int ironlake_get_refclk(struct drm_crtc *crtc)
3864 struct drm_device *dev = crtc->dev;
3865 struct drm_i915_private *dev_priv = dev->dev_private;
3866 struct intel_encoder *encoder;
3867 struct drm_mode_config *mode_config = &dev->mode_config;
3868 struct intel_encoder *edp_encoder = NULL;
3869 int num_connectors = 0;
3870 bool is_lvds = false;
3872 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3873 if (encoder->base.crtc != crtc)
3876 switch (encoder->type) {
3877 case INTEL_OUTPUT_LVDS:
3880 case INTEL_OUTPUT_EDP:
3881 edp_encoder = encoder;
3887 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3888 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3889 dev_priv->lvds_ssc_freq);
3890 return dev_priv->lvds_ssc_freq * 1000;
3896 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
3897 struct drm_display_mode *mode,
3898 struct drm_display_mode *adjusted_mode,
3900 struct drm_framebuffer *old_fb)
3902 struct drm_device *dev = crtc->dev;
3903 struct drm_i915_private *dev_priv = dev->dev_private;
3904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3905 int pipe = intel_crtc->pipe;
3906 int plane = intel_crtc->plane;
3907 int refclk, num_connectors = 0;
3908 intel_clock_t clock, reduced_clock;
3909 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
3910 bool ok, has_reduced_clock = false, is_sdvo = false;
3911 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3912 struct intel_encoder *has_edp_encoder = NULL;
3913 struct drm_mode_config *mode_config = &dev->mode_config;
3914 struct intel_encoder *encoder;
3915 const intel_limit_t *limit;
3917 struct fdi_m_n m_n = {0};
3920 int target_clock, pixel_multiplier, lane, link_bw, factor;
3921 unsigned int pipe_bpp;
3924 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3925 if (encoder->base.crtc != crtc)
3928 switch (encoder->type) {
3929 case INTEL_OUTPUT_LVDS:
3932 case INTEL_OUTPUT_SDVO:
3933 case INTEL_OUTPUT_HDMI:
3935 if (encoder->needs_tv_clock)
3938 case INTEL_OUTPUT_TVOUT:
3941 case INTEL_OUTPUT_ANALOG:
3944 case INTEL_OUTPUT_DISPLAYPORT:
3947 case INTEL_OUTPUT_EDP:
3948 has_edp_encoder = encoder;
3955 refclk = ironlake_get_refclk(crtc);
3958 * Returns a set of divisors for the desired target clock with the given
3959 * refclk, or false. The returned values represent the clock equation:
3960 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3962 limit = intel_limit(crtc, refclk);
3963 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
3966 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3970 /* Ensure that the cursor is valid for the new mode before changing... */
3971 intel_crtc_update_cursor(crtc, true);
3973 if (is_lvds && dev_priv->lvds_downclock_avail) {
3975 * Ensure we match the reduced clock's P to the target clock.
3976 * If the clocks don't match, we can't switch the display clock
3977 * by using the FP0/FP1. In such case we will disable the LVDS
3978 * downclock feature.
3980 has_reduced_clock = limit->find_pll(limit, crtc,
3981 dev_priv->lvds_downclock,
3986 /* SDVO TV has fixed PLL values depend on its clock range,
3987 this mirrors vbios setting. */
3988 if (is_sdvo && is_tv) {
3989 if (adjusted_mode->clock >= 100000
3990 && adjusted_mode->clock < 140500) {
3996 } else if (adjusted_mode->clock >= 140500
3997 && adjusted_mode->clock <= 200000) {
4007 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4009 /* CPU eDP doesn't require FDI link, so just set DP M/N
4010 according to current link config */
4011 if (has_edp_encoder &&
4012 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4013 target_clock = mode->clock;
4014 intel_edp_link_config(has_edp_encoder,
4017 /* [e]DP over FDI requires target mode clock
4018 instead of link clock */
4019 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4020 target_clock = mode->clock;
4022 target_clock = adjusted_mode->clock;
4024 /* FDI is a binary signal running at ~2.7GHz, encoding
4025 * each output octet as 10 bits. The actual frequency
4026 * is stored as a divider into a 100MHz clock, and the
4027 * mode pixel clock is stored in units of 1KHz.
4028 * Hence the bw of each lane in terms of the mode signal
4031 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4034 /* determine panel color depth */
4035 temp = I915_READ(PIPECONF(pipe));
4036 temp &= ~PIPE_BPC_MASK;
4037 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
4052 kprintf("intel_choose_pipe_bpp returned invalid value %d\n",
4059 intel_crtc->bpp = pipe_bpp;
4060 I915_WRITE(PIPECONF(pipe), temp);
4064 * Account for spread spectrum to avoid
4065 * oversubscribing the link. Max center spread
4066 * is 2.5%; use 5% for safety's sake.
4068 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4069 lane = bps / (link_bw * 8) + 1;
4072 intel_crtc->fdi_lanes = lane;
4074 if (pixel_multiplier > 1)
4075 link_bw *= pixel_multiplier;
4076 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4079 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4080 if (has_reduced_clock)
4081 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4084 /* Enable autotuning of the PLL clock (if permissible) */
4087 if ((intel_panel_use_ssc(dev_priv) &&
4088 dev_priv->lvds_ssc_freq == 100) ||
4089 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4091 } else if (is_sdvo && is_tv)
4094 if (clock.m < factor * clock.n)
4100 dpll |= DPLLB_MODE_LVDS;
4102 dpll |= DPLLB_MODE_DAC_SERIAL;
4104 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4105 if (pixel_multiplier > 1) {
4106 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4108 dpll |= DPLL_DVO_HIGH_SPEED;
4110 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4111 dpll |= DPLL_DVO_HIGH_SPEED;
4113 /* compute bitmask from p1 value */
4114 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4116 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4120 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4123 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4126 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4129 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4133 if (is_sdvo && is_tv)
4134 dpll |= PLL_REF_INPUT_TVCLKINBC;
4136 /* XXX: just matching BIOS for now */
4137 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4139 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4140 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4142 dpll |= PLL_REF_INPUT_DREFCLK;
4144 /* setup pipeconf */
4145 pipeconf = I915_READ(PIPECONF(pipe));
4147 /* Set up the display plane register */
4148 dspcntr = DISPPLANE_GAMMA_ENABLE;
4150 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
4151 drm_mode_debug_printmodeline(mode);
4153 /* PCH eDP needs FDI, but CPU eDP does not */
4154 if (!intel_crtc->no_pll) {
4155 if (!has_edp_encoder ||
4156 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4157 I915_WRITE(_PCH_FP0(pipe), fp);
4158 I915_WRITE(_PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4160 POSTING_READ(_PCH_DPLL(pipe));
4164 if (dpll == (I915_READ(_PCH_DPLL(0)) & 0x7fffffff) &&
4165 fp == I915_READ(_PCH_FP0(0))) {
4166 intel_crtc->use_pll_a = true;
4167 DRM_DEBUG_KMS("using pipe a dpll\n");
4168 } else if (dpll == (I915_READ(_PCH_DPLL(1)) & 0x7fffffff) &&
4169 fp == I915_READ(_PCH_FP0(1))) {
4170 intel_crtc->use_pll_a = false;
4171 DRM_DEBUG_KMS("using pipe b dpll\n");
4173 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
4178 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4179 * This is an exception to the general rule that mode_set doesn't turn
4183 temp = I915_READ(PCH_LVDS);
4184 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4185 if (HAS_PCH_CPT(dev)) {
4186 temp &= ~PORT_TRANS_SEL_MASK;
4187 temp |= PORT_TRANS_SEL_CPT(pipe);
4190 temp |= LVDS_PIPEB_SELECT;
4192 temp &= ~LVDS_PIPEB_SELECT;
4195 /* set the corresponsding LVDS_BORDER bit */
4196 temp |= dev_priv->lvds_border_bits;
4197 /* Set the B0-B3 data pairs corresponding to whether we're going to
4198 * set the DPLLs for dual-channel mode or not.
4201 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4203 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4205 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4206 * appropriately here, but we need to look more thoroughly into how
4207 * panels behave in the two modes.
4209 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4210 lvds_sync |= LVDS_HSYNC_POLARITY;
4211 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4212 lvds_sync |= LVDS_VSYNC_POLARITY;
4213 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4215 char flags[2] = "-+";
4216 DRM_INFO("Changing LVDS panel from "
4217 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4218 flags[!(temp & LVDS_HSYNC_POLARITY)],
4219 flags[!(temp & LVDS_VSYNC_POLARITY)],
4220 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4221 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4222 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4225 I915_WRITE(PCH_LVDS, temp);
4228 pipeconf &= ~PIPECONF_DITHER_EN;
4229 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4230 if ((is_lvds && dev_priv->lvds_dither) || dither) {
4231 pipeconf |= PIPECONF_DITHER_EN;
4232 pipeconf |= PIPECONF_DITHER_TYPE_SP;
4234 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4235 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4237 /* For non-DP output, clear any trans DP clock recovery setting.*/
4238 I915_WRITE(TRANSDATA_M1(pipe), 0);
4239 I915_WRITE(TRANSDATA_N1(pipe), 0);
4240 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4241 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
4244 if (!intel_crtc->no_pll &&
4245 (!has_edp_encoder ||
4246 intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
4247 I915_WRITE(_PCH_DPLL(pipe), dpll);
4249 /* Wait for the clocks to stabilize. */
4250 POSTING_READ(_PCH_DPLL(pipe));
4253 /* The pixel multiplier can only be updated once the
4254 * DPLL is enabled and the clocks are stable.
4256 * So write it again.
4258 I915_WRITE(_PCH_DPLL(pipe), dpll);
4261 intel_crtc->lowfreq_avail = false;
4262 if (!intel_crtc->no_pll) {
4263 if (is_lvds && has_reduced_clock && i915_powersave) {
4264 I915_WRITE(_PCH_FP1(pipe), fp2);
4265 intel_crtc->lowfreq_avail = true;
4266 if (HAS_PIPE_CXSR(dev)) {
4267 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4268 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4271 I915_WRITE(_PCH_FP1(pipe), fp);
4272 if (HAS_PIPE_CXSR(dev)) {
4273 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4274 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4279 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4280 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4281 pipeconf |= PIPECONF_INTERLACED_ILK;
4282 /* the chip adds 2 halflines automatically */
4283 adjusted_mode->crtc_vtotal -= 1;
4284 adjusted_mode->crtc_vblank_end -= 1;
4285 I915_WRITE(VSYNCSHIFT(pipe),
4286 adjusted_mode->crtc_hsync_start
4287 - adjusted_mode->crtc_htotal/2);
4289 pipeconf |= PIPECONF_PROGRESSIVE;
4290 I915_WRITE(VSYNCSHIFT(pipe), 0);
4293 I915_WRITE(HTOTAL(pipe),
4294 (adjusted_mode->crtc_hdisplay - 1) |
4295 ((adjusted_mode->crtc_htotal - 1) << 16));
4296 I915_WRITE(HBLANK(pipe),
4297 (adjusted_mode->crtc_hblank_start - 1) |
4298 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4299 I915_WRITE(HSYNC(pipe),
4300 (adjusted_mode->crtc_hsync_start - 1) |
4301 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4303 I915_WRITE(VTOTAL(pipe),
4304 (adjusted_mode->crtc_vdisplay - 1) |
4305 ((adjusted_mode->crtc_vtotal - 1) << 16));
4306 I915_WRITE(VBLANK(pipe),
4307 (adjusted_mode->crtc_vblank_start - 1) |
4308 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4309 I915_WRITE(VSYNC(pipe),
4310 (adjusted_mode->crtc_vsync_start - 1) |
4311 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4313 /* pipesrc controls the size that is scaled from, which should
4314 * always be the user's requested size.
4316 I915_WRITE(PIPESRC(pipe),
4317 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4319 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4320 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4321 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4322 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4324 if (has_edp_encoder &&
4325 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4326 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4329 I915_WRITE(PIPECONF(pipe), pipeconf);
4330 POSTING_READ(PIPECONF(pipe));
4332 intel_wait_for_vblank(dev, pipe);
4334 I915_WRITE(DSPCNTR(plane), dspcntr);
4335 POSTING_READ(DSPCNTR(plane));
4337 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4339 intel_update_watermarks(dev);
4344 static int intel_crtc_mode_set(struct drm_crtc *crtc,
4345 struct drm_display_mode *mode,
4346 struct drm_display_mode *adjusted_mode,
4348 struct drm_framebuffer *old_fb)
4350 struct drm_device *dev = crtc->dev;
4351 struct drm_i915_private *dev_priv = dev->dev_private;
4352 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4353 int pipe = intel_crtc->pipe;
4356 drm_vblank_pre_modeset(dev, pipe);
4358 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4360 drm_vblank_post_modeset(dev, pipe);
4363 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4365 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
4370 static bool intel_eld_uptodate(struct drm_connector *connector,
4371 int reg_eldv, uint32_t bits_eldv,
4372 int reg_elda, uint32_t bits_elda,
4375 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4376 uint8_t *eld = connector->eld;
4379 i = I915_READ(reg_eldv);
4388 i = I915_READ(reg_elda);
4390 I915_WRITE(reg_elda, i);
4392 for (i = 0; i < eld[2]; i++)
4393 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
4399 static void g4x_write_eld(struct drm_connector *connector,
4400 struct drm_crtc *crtc)
4402 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4403 uint8_t *eld = connector->eld;
4408 i = I915_READ(G4X_AUD_VID_DID);
4410 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
4411 eldv = G4X_ELDV_DEVCL_DEVBLC;
4413 eldv = G4X_ELDV_DEVCTG;
4415 if (intel_eld_uptodate(connector,
4416 G4X_AUD_CNTL_ST, eldv,
4417 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
4418 G4X_HDMIW_HDMIEDID))
4421 i = I915_READ(G4X_AUD_CNTL_ST);
4422 i &= ~(eldv | G4X_ELD_ADDR);
4423 len = (i >> 9) & 0x1f; /* ELD buffer size */
4424 I915_WRITE(G4X_AUD_CNTL_ST, i);
4429 if (eld[2] < (uint8_t)len)
4431 DRM_DEBUG_KMS("ELD size %d\n", len);
4432 for (i = 0; i < len; i++)
4433 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
4435 i = I915_READ(G4X_AUD_CNTL_ST);
4437 I915_WRITE(G4X_AUD_CNTL_ST, i);
4440 static void ironlake_write_eld(struct drm_connector *connector,
4441 struct drm_crtc *crtc)
4443 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4444 uint8_t *eld = connector->eld;
4453 if (HAS_PCH_IBX(connector->dev)) {
4454 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
4455 aud_config = IBX_AUD_CONFIG_A;
4456 aud_cntl_st = IBX_AUD_CNTL_ST_A;
4457 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
4459 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
4460 aud_config = CPT_AUD_CONFIG_A;
4461 aud_cntl_st = CPT_AUD_CNTL_ST_A;
4462 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
4465 i = to_intel_crtc(crtc)->pipe;
4466 hdmiw_hdmiedid += i * 0x100;
4467 aud_cntl_st += i * 0x100;
4468 aud_config += i * 0x100;
4470 DRM_DEBUG_KMS("ELD on pipe %c\n", pipe_name(i));
4472 i = I915_READ(aud_cntl_st);
4473 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
4475 DRM_DEBUG_KMS("Audio directed to unknown port\n");
4476 /* operate blindly on all ports */
4477 eldv = IBX_ELD_VALIDB;
4478 eldv |= IBX_ELD_VALIDB << 4;
4479 eldv |= IBX_ELD_VALIDB << 8;
4481 DRM_DEBUG_KMS("ELD on port %c\n", 'A' + i);
4482 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
4485 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
4486 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
4487 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
4488 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
4490 I915_WRITE(aud_config, 0);
4492 if (intel_eld_uptodate(connector,
4493 aud_cntrl_st2, eldv,
4494 aud_cntl_st, IBX_ELD_ADDRESS,
4498 i = I915_READ(aud_cntrl_st2);
4500 I915_WRITE(aud_cntrl_st2, i);
4505 i = I915_READ(aud_cntl_st);
4506 i &= ~IBX_ELD_ADDRESS;
4507 I915_WRITE(aud_cntl_st, i);
4509 /* 84 bytes of hw ELD buffer */
4511 if (eld[2] < (uint8_t)len)
4513 DRM_DEBUG_KMS("ELD size %d\n", len);
4514 for (i = 0; i < len; i++)
4515 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
4517 i = I915_READ(aud_cntrl_st2);
4519 I915_WRITE(aud_cntrl_st2, i);
4522 void intel_write_eld(struct drm_encoder *encoder,
4523 struct drm_display_mode *mode)
4525 struct drm_crtc *crtc = encoder->crtc;
4526 struct drm_connector *connector;
4527 struct drm_device *dev = encoder->dev;
4528 struct drm_i915_private *dev_priv = dev->dev_private;
4530 connector = drm_select_eld(encoder, mode);
4534 DRM_DEBUG_KMS("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4536 drm_get_connector_name(connector),
4537 connector->encoder->base.id,
4538 drm_get_encoder_name(connector->encoder));
4540 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
4542 if (dev_priv->display.write_eld)
4543 dev_priv->display.write_eld(connector, crtc);
4546 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4547 void intel_crtc_load_lut(struct drm_crtc *crtc)
4549 struct drm_device *dev = crtc->dev;
4550 struct drm_i915_private *dev_priv = dev->dev_private;
4551 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4552 int palreg = PALETTE(intel_crtc->pipe);
4555 /* The clocks have to be on to load the palette. */
4556 if (!crtc->enabled || !intel_crtc->active)
4559 /* use legacy palette for Ironlake */
4560 if (HAS_PCH_SPLIT(dev))
4561 palreg = LGC_PALETTE(intel_crtc->pipe);
4563 for (i = 0; i < 256; i++) {
4564 I915_WRITE(palreg + 4 * i,
4565 (intel_crtc->lut_r[i] << 16) |
4566 (intel_crtc->lut_g[i] << 8) |
4567 intel_crtc->lut_b[i]);
4571 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4573 struct drm_device *dev = crtc->dev;
4574 struct drm_i915_private *dev_priv = dev->dev_private;
4575 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4576 bool visible = base != 0;
4579 if (intel_crtc->cursor_visible == visible)
4582 cntl = I915_READ(_CURACNTR);
4584 /* On these chipsets we can only modify the base whilst
4585 * the cursor is disabled.
4587 I915_WRITE(_CURABASE, base);
4589 cntl &= ~(CURSOR_FORMAT_MASK);
4590 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4591 cntl |= CURSOR_ENABLE |
4592 CURSOR_GAMMA_ENABLE |
4595 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4596 I915_WRITE(_CURACNTR, cntl);
4598 intel_crtc->cursor_visible = visible;
4601 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4603 struct drm_device *dev = crtc->dev;
4604 struct drm_i915_private *dev_priv = dev->dev_private;
4605 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4606 int pipe = intel_crtc->pipe;
4607 bool visible = base != 0;
4609 if (intel_crtc->cursor_visible != visible) {
4610 uint32_t cntl = I915_READ(CURCNTR(pipe));
4612 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4613 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4614 cntl |= pipe << 28; /* Connect to correct pipe */
4616 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4617 cntl |= CURSOR_MODE_DISABLE;
4619 I915_WRITE(CURCNTR(pipe), cntl);
4621 intel_crtc->cursor_visible = visible;
4623 /* and commit changes on next vblank */
4624 I915_WRITE(CURBASE(pipe), base);
4627 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
4629 struct drm_device *dev = crtc->dev;
4630 struct drm_i915_private *dev_priv = dev->dev_private;
4631 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4632 int pipe = intel_crtc->pipe;
4633 bool visible = base != 0;
4635 if (intel_crtc->cursor_visible != visible) {
4636 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
4638 cntl &= ~CURSOR_MODE;
4639 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4641 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4642 cntl |= CURSOR_MODE_DISABLE;
4644 I915_WRITE(CURCNTR_IVB(pipe), cntl);
4646 intel_crtc->cursor_visible = visible;
4648 /* and commit changes on next vblank */
4649 I915_WRITE(CURBASE_IVB(pipe), base);
4652 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4653 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4656 struct drm_device *dev = crtc->dev;
4657 struct drm_i915_private *dev_priv = dev->dev_private;
4658 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4659 int pipe = intel_crtc->pipe;
4660 int x = intel_crtc->cursor_x;
4661 int y = intel_crtc->cursor_y;
4667 if (on && crtc->enabled && crtc->fb) {
4668 base = intel_crtc->cursor_addr;
4669 if (x > (int) crtc->fb->width)
4672 if (y > (int) crtc->fb->height)
4678 if (x + intel_crtc->cursor_width < 0)
4681 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4684 pos |= x << CURSOR_X_SHIFT;
4687 if (y + intel_crtc->cursor_height < 0)
4690 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4693 pos |= y << CURSOR_Y_SHIFT;
4695 visible = base != 0;
4696 if (!visible && !intel_crtc->cursor_visible)
4699 if (IS_IVYBRIDGE(dev)) {
4700 I915_WRITE(CURPOS_IVB(pipe), pos);
4701 ivb_update_cursor(crtc, base);
4703 I915_WRITE(CURPOS(pipe), pos);
4704 if (IS_845G(dev) || IS_I865G(dev))
4705 i845_update_cursor(crtc, base);
4707 i9xx_update_cursor(crtc, base);
4711 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4712 struct drm_file *file,
4714 uint32_t width, uint32_t height)
4716 struct drm_device *dev = crtc->dev;
4717 struct drm_i915_private *dev_priv = dev->dev_private;
4718 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4719 struct drm_i915_gem_object *obj;
4723 DRM_DEBUG_KMS("\n");
4725 /* if we want to turn off the cursor ignore width and height */
4727 DRM_DEBUG_KMS("cursor off\n");
4734 /* Currently we only support 64x64 cursors */
4735 if (width != 64 || height != 64) {
4736 DRM_ERROR("we currently only support 64x64 cursors\n");
4740 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
4741 if (&obj->base == NULL)
4744 if (obj->base.size < width * height * 4) {
4745 DRM_ERROR("buffer is to small\n");
4750 /* we only need to pin inside GTT if cursor is non-phy */
4752 if (!dev_priv->info->cursor_needs_physical) {
4753 if (obj->tiling_mode) {
4754 DRM_ERROR("cursor cannot be tiled\n");
4759 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
4761 DRM_ERROR("failed to move cursor bo into the GTT\n");
4765 ret = i915_gem_object_put_fence(obj);
4767 DRM_ERROR("failed to release fence for cursor\n");
4771 addr = obj->gtt_offset;
4773 int align = IS_I830(dev) ? 16 * 1024 : 256;
4774 ret = i915_gem_attach_phys_object(dev, obj,
4775 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4778 DRM_ERROR("failed to attach phys object\n");
4781 addr = obj->phys_obj->handle->busaddr;
4785 I915_WRITE(CURSIZE, (height << 12) | width);
4788 if (intel_crtc->cursor_bo) {
4789 if (dev_priv->info->cursor_needs_physical) {
4790 if (intel_crtc->cursor_bo != obj)
4791 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4793 i915_gem_object_unpin(intel_crtc->cursor_bo);
4794 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
4799 intel_crtc->cursor_addr = addr;
4800 intel_crtc->cursor_bo = obj;
4801 intel_crtc->cursor_width = width;
4802 intel_crtc->cursor_height = height;
4804 intel_crtc_update_cursor(crtc, true);
4808 i915_gem_object_unpin(obj);
4812 drm_gem_object_unreference_unlocked(&obj->base);
4816 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4820 intel_crtc->cursor_x = x;
4821 intel_crtc->cursor_y = y;
4823 intel_crtc_update_cursor(crtc, true);
4828 /** Sets the color ramps on behalf of RandR */
4829 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4830 u16 blue, int regno)
4832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4834 intel_crtc->lut_r[regno] = red >> 8;
4835 intel_crtc->lut_g[regno] = green >> 8;
4836 intel_crtc->lut_b[regno] = blue >> 8;
4839 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4840 u16 *blue, int regno)
4842 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4844 *red = intel_crtc->lut_r[regno] << 8;
4845 *green = intel_crtc->lut_g[regno] << 8;
4846 *blue = intel_crtc->lut_b[regno] << 8;
4849 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4850 u16 *blue, uint32_t start, uint32_t size)
4852 int end = (start + size > 256) ? 256 : start + size, i;
4853 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4855 for (i = start; i < end; i++) {
4856 intel_crtc->lut_r[i] = red[i] >> 8;
4857 intel_crtc->lut_g[i] = green[i] >> 8;
4858 intel_crtc->lut_b[i] = blue[i] >> 8;
4861 intel_crtc_load_lut(crtc);
4865 * Get a pipe with a simple mode set on it for doing load-based monitor
4868 * It will be up to the load-detect code to adjust the pipe as appropriate for
4869 * its requirements. The pipe will be connected to no other encoders.
4871 * Currently this code will only succeed if there is a pipe with no encoders
4872 * configured for it. In the future, it could choose to temporarily disable
4873 * some outputs to free up a pipe for its use.
4875 * \return crtc, or NULL if no pipes are available.
4878 /* VESA 640x480x72Hz mode to set on the pipe */
4879 static struct drm_display_mode load_detect_mode = {
4880 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4881 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4884 static struct drm_framebuffer *
4885 intel_framebuffer_create(struct drm_device *dev,
4886 struct drm_mode_fb_cmd2 *mode_cmd,
4887 struct drm_i915_gem_object *obj)
4889 struct intel_framebuffer *intel_fb;
4892 intel_fb = kmalloc(sizeof(*intel_fb), DRM_MEM_KMS, M_WAITOK | M_ZERO);
4894 drm_gem_object_unreference_unlocked(&obj->base);
4895 return ERR_PTR(-ENOMEM);
4898 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
4900 drm_gem_object_unreference_unlocked(&obj->base);
4901 kfree(intel_fb, DRM_MEM_KMS);
4902 return ERR_PTR(ret);
4905 return &intel_fb->base;
4909 intel_framebuffer_pitch_for_width(int width, int bpp)
4911 u32 pitch = howmany(width * bpp, 8);
4912 return roundup2(pitch, 64);
4916 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
4918 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
4919 return roundup2(pitch * mode->vdisplay, PAGE_SIZE);
4922 static struct drm_framebuffer *
4923 intel_framebuffer_create_for_mode(struct drm_device *dev,
4924 struct drm_display_mode *mode,
4927 struct drm_i915_gem_object *obj;
4928 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
4930 obj = i915_gem_alloc_object(dev,
4931 intel_framebuffer_size_for_mode(mode, bpp));
4933 return ERR_PTR(-ENOMEM);
4935 mode_cmd.width = mode->hdisplay;
4936 mode_cmd.height = mode->vdisplay;
4937 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
4939 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
4941 return intel_framebuffer_create(dev, &mode_cmd, obj);
4945 mode_fits_in_fbdev(struct drm_device *dev,
4946 struct drm_display_mode *mode, struct drm_framebuffer **res)
4948 struct drm_i915_private *dev_priv = dev->dev_private;
4949 struct drm_i915_gem_object *obj;
4950 struct drm_framebuffer *fb;
4952 if (dev_priv->fbdev == NULL) {
4957 obj = dev_priv->fbdev->ifb.obj;
4963 fb = &dev_priv->fbdev->ifb.base;
4964 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
4965 fb->bits_per_pixel)) {
4970 if (obj->base.size < mode->vdisplay * fb->pitches[0]) {
4979 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4980 struct drm_connector *connector,
4981 struct drm_display_mode *mode,
4982 struct intel_load_detect_pipe *old)
4984 struct intel_crtc *intel_crtc;
4985 struct drm_crtc *possible_crtc;
4986 struct drm_encoder *encoder = &intel_encoder->base;
4987 struct drm_crtc *crtc = NULL;
4988 struct drm_device *dev = encoder->dev;
4989 struct drm_framebuffer *old_fb;
4992 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4993 connector->base.id, drm_get_connector_name(connector),
4994 encoder->base.id, drm_get_encoder_name(encoder));
4997 * Algorithm gets a little messy:
4999 * - if the connector already has an assigned crtc, use it (but make
5000 * sure it's on first)
5002 * - try to find the first unused crtc that can drive this connector,
5003 * and use that if we find one
5006 /* See if we already have a CRTC for this connector */
5007 if (encoder->crtc) {
5008 crtc = encoder->crtc;
5010 intel_crtc = to_intel_crtc(crtc);
5011 old->dpms_mode = intel_crtc->dpms_mode;
5012 old->load_detect_temp = false;
5014 /* Make sure the crtc and connector are running */
5015 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
5016 struct drm_encoder_helper_funcs *encoder_funcs;
5017 struct drm_crtc_helper_funcs *crtc_funcs;
5019 crtc_funcs = crtc->helper_private;
5020 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
5022 encoder_funcs = encoder->helper_private;
5023 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5029 /* Find an unused one (if possible) */
5030 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5032 if (!(encoder->possible_crtcs & (1 << i)))
5034 if (!possible_crtc->enabled) {
5035 crtc = possible_crtc;
5041 * If we didn't find an unused CRTC, don't use any.
5044 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5048 encoder->crtc = crtc;
5049 connector->encoder = encoder;
5051 intel_crtc = to_intel_crtc(crtc);
5052 old->dpms_mode = intel_crtc->dpms_mode;
5053 old->load_detect_temp = true;
5054 old->release_fb = NULL;
5057 mode = &load_detect_mode;
5061 /* We need a framebuffer large enough to accommodate all accesses
5062 * that the plane may generate whilst we perform load detection.
5063 * We can not rely on the fbcon either being present (we get called
5064 * during its initialisation to detect all boot displays, or it may
5065 * not even exist) or that it is large enough to satisfy the
5068 r = mode_fits_in_fbdev(dev, mode, &crtc->fb);
5069 if (crtc->fb == NULL) {
5070 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5071 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5072 old->release_fb = crtc->fb;
5074 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5075 if (IS_ERR(crtc->fb)) {
5076 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5080 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
5081 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5082 if (old->release_fb)
5083 old->release_fb->funcs->destroy(old->release_fb);
5088 /* let the connector get through one full cycle before testing */
5089 intel_wait_for_vblank(dev, intel_crtc->pipe);
5094 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
5095 struct drm_connector *connector,
5096 struct intel_load_detect_pipe *old)
5098 struct drm_encoder *encoder = &intel_encoder->base;
5099 struct drm_device *dev = encoder->dev;
5100 struct drm_crtc *crtc = encoder->crtc;
5101 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5102 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5104 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5105 connector->base.id, drm_get_connector_name(connector),
5106 encoder->base.id, drm_get_encoder_name(encoder));
5108 if (old->load_detect_temp) {
5109 connector->encoder = NULL;
5110 drm_helper_disable_unused_functions(dev);
5112 if (old->release_fb)
5113 old->release_fb->funcs->destroy(old->release_fb);
5118 /* Switch crtc and encoder back off if necessary */
5119 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5120 encoder_funcs->dpms(encoder, old->dpms_mode);
5121 crtc_funcs->dpms(crtc, old->dpms_mode);
5125 /* Returns the clock of the currently programmed mode of the given pipe. */
5126 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5128 struct drm_i915_private *dev_priv = dev->dev_private;
5129 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5130 int pipe = intel_crtc->pipe;
5131 u32 dpll = I915_READ(DPLL(pipe));
5133 intel_clock_t clock;
5135 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5136 fp = I915_READ(FP0(pipe));
5138 fp = I915_READ(FP1(pipe));
5140 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5141 if (IS_PINEVIEW(dev)) {
5142 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5143 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5145 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5146 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5149 if (!IS_GEN2(dev)) {
5150 if (IS_PINEVIEW(dev))
5151 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5152 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5154 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5155 DPLL_FPA01_P1_POST_DIV_SHIFT);
5157 switch (dpll & DPLL_MODE_MASK) {
5158 case DPLLB_MODE_DAC_SERIAL:
5159 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5162 case DPLLB_MODE_LVDS:
5163 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5167 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5168 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5172 /* XXX: Handle the 100Mhz refclk */
5173 intel_clock(dev, 96000, &clock);
5175 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5178 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5179 DPLL_FPA01_P1_POST_DIV_SHIFT);
5182 if ((dpll & PLL_REF_INPUT_MASK) ==
5183 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5184 /* XXX: might not be 66MHz */
5185 intel_clock(dev, 66000, &clock);
5187 intel_clock(dev, 48000, &clock);
5189 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5192 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5193 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5195 if (dpll & PLL_P2_DIVIDE_BY_4)
5200 intel_clock(dev, 48000, &clock);
5204 /* XXX: It would be nice to validate the clocks, but we can't reuse
5205 * i830PllIsValid() because it relies on the xf86_config connector
5206 * configuration being accurate, which it isn't necessarily.
5212 /** Returns the currently programmed mode of the given pipe. */
5213 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5214 struct drm_crtc *crtc)
5216 struct drm_i915_private *dev_priv = dev->dev_private;
5217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5218 int pipe = intel_crtc->pipe;
5219 struct drm_display_mode *mode;
5220 int htot = I915_READ(HTOTAL(pipe));
5221 int hsync = I915_READ(HSYNC(pipe));
5222 int vtot = I915_READ(VTOTAL(pipe));
5223 int vsync = I915_READ(VSYNC(pipe));
5225 mode = kmalloc(sizeof(*mode), DRM_MEM_KMS, M_WAITOK | M_ZERO);
5227 mode->clock = intel_crtc_clock_get(dev, crtc);
5228 mode->hdisplay = (htot & 0xffff) + 1;
5229 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5230 mode->hsync_start = (hsync & 0xffff) + 1;
5231 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5232 mode->vdisplay = (vtot & 0xffff) + 1;
5233 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5234 mode->vsync_start = (vsync & 0xffff) + 1;
5235 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5237 drm_mode_set_name(mode);
5238 drm_mode_set_crtcinfo(mode, 0);
5243 static void intel_increase_pllclock(struct drm_crtc *crtc)
5245 struct drm_device *dev = crtc->dev;
5246 drm_i915_private_t *dev_priv = dev->dev_private;
5247 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5248 int pipe = intel_crtc->pipe;
5249 int dpll_reg = DPLL(pipe);
5252 if (HAS_PCH_SPLIT(dev))
5255 if (!dev_priv->lvds_downclock_avail)
5258 dpll = I915_READ(dpll_reg);
5259 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5260 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5262 assert_panel_unlocked(dev_priv, pipe);
5264 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5265 I915_WRITE(dpll_reg, dpll);
5266 intel_wait_for_vblank(dev, pipe);
5268 dpll = I915_READ(dpll_reg);
5269 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5270 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5274 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5276 struct drm_device *dev = crtc->dev;
5277 drm_i915_private_t *dev_priv = dev->dev_private;
5278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5280 if (HAS_PCH_SPLIT(dev))
5283 if (!dev_priv->lvds_downclock_avail)
5287 * Since this is called by a timer, we should never get here in
5290 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5291 int pipe = intel_crtc->pipe;
5292 int dpll_reg = DPLL(pipe);
5295 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5297 assert_panel_unlocked(dev_priv, pipe);
5299 dpll = I915_READ(dpll_reg);
5300 dpll |= DISPLAY_RATE_SELECT_FPA1;
5301 I915_WRITE(dpll_reg, dpll);
5302 intel_wait_for_vblank(dev, pipe);
5303 dpll = I915_READ(dpll_reg);
5304 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5305 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5309 void intel_mark_busy(struct drm_device *dev)
5311 i915_update_gfx_val(dev->dev_private);
5314 void intel_mark_idle(struct drm_device *dev)
5316 struct drm_crtc *crtc;
5318 if (!i915_powersave)
5321 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5325 intel_decrease_pllclock(crtc);
5329 static void intel_crtc_destroy(struct drm_crtc *crtc)
5331 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5332 struct drm_device *dev = crtc->dev;
5333 struct intel_unpin_work *work;
5335 lockmgr(&dev->event_lock, LK_EXCLUSIVE);
5336 work = intel_crtc->unpin_work;
5337 intel_crtc->unpin_work = NULL;
5338 lockmgr(&dev->event_lock, LK_RELEASE);
5341 cancel_work_sync(&work->work);
5342 kfree(work, DRM_MEM_KMS);
5345 drm_crtc_cleanup(crtc);
5347 drm_free(intel_crtc, DRM_MEM_KMS);
5350 static void intel_unpin_work_fn(struct work_struct *__work)
5352 struct intel_unpin_work *work =
5353 container_of(__work, struct intel_unpin_work, work);
5354 struct drm_device *dev;
5358 intel_unpin_fb_obj(work->old_fb_obj);
5359 drm_gem_object_unreference(&work->pending_flip_obj->base);
5360 drm_gem_object_unreference(&work->old_fb_obj->base);
5362 intel_update_fbc(work->dev);
5364 drm_free(work, DRM_MEM_KMS);
5367 static void do_intel_finish_page_flip(struct drm_device *dev,
5368 struct drm_crtc *crtc)
5370 drm_i915_private_t *dev_priv = dev->dev_private;
5371 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5372 struct intel_unpin_work *work;
5373 struct drm_i915_gem_object *obj;
5375 /* Ignore early vblank irqs */
5376 if (intel_crtc == NULL)
5379 lockmgr(&dev->event_lock, LK_EXCLUSIVE);
5380 work = intel_crtc->unpin_work;
5381 if (work == NULL || !atomic_read(&work->pending)) {
5382 lockmgr(&dev->event_lock, LK_RELEASE);
5386 intel_crtc->unpin_work = NULL;
5389 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
5391 drm_vblank_put(dev, intel_crtc->pipe);
5393 lockmgr(&dev->event_lock, LK_RELEASE);
5395 obj = work->old_fb_obj;
5397 atomic_clear_mask(1 << intel_crtc->plane,
5398 &obj->pending_flip.counter);
5399 wakeup(&obj->pending_flip);
5401 queue_work(dev_priv->wq, &work->work);
5404 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5406 drm_i915_private_t *dev_priv = dev->dev_private;
5407 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5409 do_intel_finish_page_flip(dev, crtc);
5412 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5414 drm_i915_private_t *dev_priv = dev->dev_private;
5415 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5417 do_intel_finish_page_flip(dev, crtc);
5420 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5422 drm_i915_private_t *dev_priv = dev->dev_private;
5423 struct intel_crtc *intel_crtc =
5424 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5426 lockmgr(&dev->event_lock, LK_EXCLUSIVE);
5427 if (intel_crtc->unpin_work)
5428 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
5429 lockmgr(&dev->event_lock, LK_RELEASE);
5432 static int intel_gen2_queue_flip(struct drm_device *dev,
5433 struct drm_crtc *crtc,
5434 struct drm_framebuffer *fb,
5435 struct drm_i915_gem_object *obj)
5437 struct drm_i915_private *dev_priv = dev->dev_private;
5438 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5439 unsigned long offset;
5443 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
5447 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5448 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
5450 ret = BEGIN_LP_RING(6);
5454 /* Can't queue multiple flips, so wait for the previous
5455 * one to finish before executing the next.
5457 if (intel_crtc->plane)
5458 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5460 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5461 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5463 OUT_RING(MI_DISPLAY_FLIP |
5464 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5465 OUT_RING(fb->pitches[0]);
5466 OUT_RING(obj->gtt_offset + offset);
5467 OUT_RING(0); /* aux display base address, unused */
5473 static int intel_gen3_queue_flip(struct drm_device *dev,
5474 struct drm_crtc *crtc,
5475 struct drm_framebuffer *fb,
5476 struct drm_i915_gem_object *obj)
5478 struct drm_i915_private *dev_priv = dev->dev_private;
5479 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5480 unsigned long offset;
5484 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
5488 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5489 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
5491 ret = BEGIN_LP_RING(6);
5495 if (intel_crtc->plane)
5496 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5498 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5499 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5501 OUT_RING(MI_DISPLAY_FLIP_I915 |
5502 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5503 OUT_RING(fb->pitches[0]);
5504 OUT_RING(obj->gtt_offset + offset);
5512 static int intel_gen4_queue_flip(struct drm_device *dev,
5513 struct drm_crtc *crtc,
5514 struct drm_framebuffer *fb,
5515 struct drm_i915_gem_object *obj)
5517 struct drm_i915_private *dev_priv = dev->dev_private;
5518 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5519 uint32_t pf, pipesrc;
5522 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
5526 ret = BEGIN_LP_RING(4);
5530 /* i965+ uses the linear or tiled offsets from the
5531 * Display Registers (which do not change across a page-flip)
5532 * so we need only reprogram the base address.
5534 OUT_RING(MI_DISPLAY_FLIP |
5535 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5536 OUT_RING(fb->pitches[0]);
5537 OUT_RING(obj->gtt_offset | obj->tiling_mode);
5539 /* XXX Enabling the panel-fitter across page-flip is so far
5540 * untested on non-native modes, so ignore it for now.
5541 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5544 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
5545 OUT_RING(pf | pipesrc);
5551 static int intel_gen6_queue_flip(struct drm_device *dev,
5552 struct drm_crtc *crtc,
5553 struct drm_framebuffer *fb,
5554 struct drm_i915_gem_object *obj)
5556 struct drm_i915_private *dev_priv = dev->dev_private;
5557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5558 uint32_t pf, pipesrc;
5561 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
5565 ret = BEGIN_LP_RING(4);
5569 OUT_RING(MI_DISPLAY_FLIP |
5570 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5571 OUT_RING(fb->pitches[0] | obj->tiling_mode);
5572 OUT_RING(obj->gtt_offset);
5574 /* Contrary to the suggestions in the documentation,
5575 * "Enable Panel Fitter" does not seem to be required when page
5576 * flipping with a non-native mode, and worse causes a normal
5578 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
5581 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
5582 OUT_RING(pf | pipesrc);
5589 * On gen7 we currently use the blit ring because (in early silicon at least)
5590 * the render ring doesn't give us interrpts for page flip completion, which
5591 * means clients will hang after the first flip is queued. Fortunately the
5592 * blit ring generates interrupts properly, so use it instead.
5594 static int intel_gen7_queue_flip(struct drm_device *dev,
5595 struct drm_crtc *crtc,
5596 struct drm_framebuffer *fb,
5597 struct drm_i915_gem_object *obj)
5599 struct drm_i915_private *dev_priv = dev->dev_private;
5600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5601 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
5604 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
5608 ret = intel_ring_begin(ring, 4);
5612 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
5613 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
5614 intel_ring_emit(ring, (obj->gtt_offset));
5615 intel_ring_emit(ring, (MI_NOOP));
5616 intel_ring_advance(ring);
5621 static int intel_default_queue_flip(struct drm_device *dev,
5622 struct drm_crtc *crtc,
5623 struct drm_framebuffer *fb,
5624 struct drm_i915_gem_object *obj)
5629 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5630 struct drm_framebuffer *fb,
5631 struct drm_pending_vblank_event *event)
5633 struct drm_device *dev = crtc->dev;
5634 struct drm_i915_private *dev_priv = dev->dev_private;
5635 struct intel_framebuffer *intel_fb;
5636 struct drm_i915_gem_object *obj;
5637 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5638 struct intel_unpin_work *work;
5641 work = kmalloc(sizeof *work, DRM_MEM_KMS, M_WAITOK | M_ZERO);
5643 work->event = event;
5644 work->dev = crtc->dev;
5645 intel_fb = to_intel_framebuffer(crtc->fb);
5646 work->old_fb_obj = intel_fb->obj;
5647 INIT_WORK(&work->work, intel_unpin_work_fn);
5649 ret = drm_vblank_get(dev, intel_crtc->pipe);
5653 /* We borrow the event spin lock for protecting unpin_work */
5654 lockmgr(&dev->event_lock, LK_EXCLUSIVE);
5655 if (intel_crtc->unpin_work) {
5656 lockmgr(&dev->event_lock, LK_RELEASE);
5657 drm_free(work, DRM_MEM_KMS);
5658 drm_vblank_put(dev, intel_crtc->pipe);
5660 DRM_DEBUG("flip queue: crtc already busy\n");
5663 intel_crtc->unpin_work = work;
5664 lockmgr(&dev->event_lock, LK_RELEASE);
5666 intel_fb = to_intel_framebuffer(fb);
5667 obj = intel_fb->obj;
5671 /* Reference the objects for the scheduled work. */
5672 drm_gem_object_reference(&work->old_fb_obj->base);
5673 drm_gem_object_reference(&obj->base);
5677 work->pending_flip_obj = obj;
5679 work->enable_stall_check = true;
5681 /* Block clients from rendering to the new back buffer until
5682 * the flip occurs and the object is no longer visible.
5684 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
5686 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
5688 goto cleanup_pending;
5689 intel_disable_fbc(dev);
5695 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
5696 drm_gem_object_unreference(&work->old_fb_obj->base);
5697 drm_gem_object_unreference(&obj->base);
5700 lockmgr(&dev->event_lock, LK_EXCLUSIVE);
5701 intel_crtc->unpin_work = NULL;
5702 lockmgr(&dev->event_lock, LK_RELEASE);
5704 drm_vblank_put(dev, intel_crtc->pipe);
5706 drm_free(work, DRM_MEM_KMS);
5711 static void intel_sanitize_modesetting(struct drm_device *dev,
5712 int pipe, int plane)
5714 struct drm_i915_private *dev_priv = dev->dev_private;
5717 /* Clear any frame start delays used for debugging left by the BIOS */
5718 for_each_pipe(pipe) {
5719 reg = PIPECONF(pipe);
5720 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
5723 if (HAS_PCH_SPLIT(dev))
5726 /* Who knows what state these registers were left in by the BIOS or
5729 * If we leave the registers in a conflicting state (e.g. with the
5730 * display plane reading from the other pipe than the one we intend
5731 * to use) then when we attempt to teardown the active mode, we will
5732 * not disable the pipes and planes in the correct order -- leaving
5733 * a plane reading from a disabled pipe and possibly leading to
5734 * undefined behaviour.
5737 reg = DSPCNTR(plane);
5738 val = I915_READ(reg);
5740 if ((val & DISPLAY_PLANE_ENABLE) == 0)
5742 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
5745 /* This display plane is active and attached to the other CPU pipe. */
5748 /* Disable the plane and wait for it to stop reading from the pipe. */
5749 intel_disable_plane(dev_priv, plane, pipe);
5750 intel_disable_pipe(dev_priv, pipe);
5753 static void intel_crtc_reset(struct drm_crtc *crtc)
5755 struct drm_device *dev = crtc->dev;
5756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5758 /* Reset flags back to the 'unknown' status so that they
5759 * will be correctly set on the initial modeset.
5761 intel_crtc->dpms_mode = -1;
5763 /* We need to fix up any BIOS configuration that conflicts with
5766 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
5769 static struct drm_crtc_helper_funcs intel_helper_funcs = {
5770 .dpms = intel_crtc_dpms,
5771 .mode_fixup = intel_crtc_mode_fixup,
5772 .mode_set = intel_crtc_mode_set,
5773 .mode_set_base = intel_pipe_set_base,
5774 .mode_set_base_atomic = intel_pipe_set_base_atomic,
5775 .load_lut = intel_crtc_load_lut,
5776 .disable = intel_crtc_disable,
5779 static const struct drm_crtc_funcs intel_crtc_funcs = {
5780 .reset = intel_crtc_reset,
5781 .cursor_set = intel_crtc_cursor_set,
5782 .cursor_move = intel_crtc_cursor_move,
5783 .gamma_set = intel_crtc_gamma_set,
5784 .set_config = drm_crtc_helper_set_config,
5785 .destroy = intel_crtc_destroy,
5786 .page_flip = intel_crtc_page_flip,
5789 static void intel_crtc_init(struct drm_device *dev, int pipe)
5791 drm_i915_private_t *dev_priv = dev->dev_private;
5792 struct intel_crtc *intel_crtc;
5795 intel_crtc = kmalloc(sizeof(struct intel_crtc) +
5796 (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)),
5797 DRM_MEM_KMS, M_WAITOK | M_ZERO);
5799 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5801 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5802 for (i = 0; i < 256; i++) {
5803 intel_crtc->lut_r[i] = i;
5804 intel_crtc->lut_g[i] = i;
5805 intel_crtc->lut_b[i] = i;
5808 /* Swap pipes & planes for FBC on pre-965 */
5809 intel_crtc->pipe = pipe;
5810 intel_crtc->plane = pipe;
5811 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
5812 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5813 intel_crtc->plane = !pipe;
5816 KASSERT(pipe < DRM_ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) &&
5817 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] == NULL,
5818 ("plane_to_crtc is already initialized"));
5819 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5820 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5822 intel_crtc_reset(&intel_crtc->base);
5823 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5824 intel_crtc->bpp = 24; /* default for pre-Ironlake */
5826 if (HAS_PCH_SPLIT(dev)) {
5827 if (pipe == 2 && IS_IVYBRIDGE(dev))
5828 intel_crtc->no_pll = true;
5829 intel_helper_funcs.prepare = ironlake_crtc_prepare;
5830 intel_helper_funcs.commit = ironlake_crtc_commit;
5832 intel_helper_funcs.prepare = i9xx_crtc_prepare;
5833 intel_helper_funcs.commit = i9xx_crtc_commit;
5836 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5838 intel_crtc->busy = false;
5840 callout_init_mp(&intel_crtc->idle_callout);
5843 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5844 struct drm_file *file)
5846 drm_i915_private_t *dev_priv = dev->dev_private;
5847 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5848 struct drm_mode_object *drmmode_obj;
5849 struct intel_crtc *crtc;
5852 DRM_ERROR("called with no initialization\n");
5856 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5857 DRM_MODE_OBJECT_CRTC);
5860 DRM_ERROR("no such CRTC id\n");
5864 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5865 pipe_from_crtc_id->pipe = crtc->pipe;
5870 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5872 struct intel_encoder *encoder;
5876 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5877 if (type_mask & encoder->clone_mask)
5878 index_mask |= (1 << entry);
5885 static bool has_edp_a(struct drm_device *dev)
5887 struct drm_i915_private *dev_priv = dev->dev_private;
5889 if (!IS_MOBILE(dev))
5892 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
5896 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
5902 static void intel_setup_outputs(struct drm_device *dev)
5904 struct drm_i915_private *dev_priv = dev->dev_private;
5905 struct intel_encoder *encoder;
5906 bool dpd_is_edp = false;
5909 has_lvds = intel_lvds_init(dev);
5910 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
5911 /* disable the panel fitter on everything but LVDS */
5912 I915_WRITE(PFIT_CONTROL, 0);
5915 if (HAS_PCH_SPLIT(dev)) {
5916 dpd_is_edp = intel_dpd_is_edp(dev);
5919 intel_dp_init(dev, DP_A);
5921 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5922 intel_dp_init(dev, PCH_DP_D);
5925 intel_crt_init(dev);
5927 if (HAS_PCH_SPLIT(dev)) {
5931 "HDMIB %d PCH_DP_B %d HDMIC %d HDMID %d PCH_DP_C %d PCH_DP_D %d LVDS %d\n",
5932 (I915_READ(HDMIB) & PORT_DETECTED) != 0,
5933 (I915_READ(PCH_DP_B) & DP_DETECTED) != 0,
5934 (I915_READ(HDMIC) & PORT_DETECTED) != 0,
5935 (I915_READ(HDMID) & PORT_DETECTED) != 0,
5936 (I915_READ(PCH_DP_C) & DP_DETECTED) != 0,
5937 (I915_READ(PCH_DP_D) & DP_DETECTED) != 0,
5938 (I915_READ(PCH_LVDS) & LVDS_DETECTED) != 0);
5940 if (I915_READ(HDMIB) & PORT_DETECTED) {
5941 /* PCH SDVOB multiplex with HDMIB */
5942 found = intel_sdvo_init(dev, PCH_SDVOB);
5944 intel_hdmi_init(dev, HDMIB);
5945 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5946 intel_dp_init(dev, PCH_DP_B);
5949 if (I915_READ(HDMIC) & PORT_DETECTED)
5950 intel_hdmi_init(dev, HDMIC);
5952 if (I915_READ(HDMID) & PORT_DETECTED)
5953 intel_hdmi_init(dev, HDMID);
5955 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5956 intel_dp_init(dev, PCH_DP_C);
5958 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5959 intel_dp_init(dev, PCH_DP_D);
5961 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5964 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5965 DRM_DEBUG_KMS("probing SDVOB\n");
5966 found = intel_sdvo_init(dev, SDVOB);
5967 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5968 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5969 intel_hdmi_init(dev, SDVOB);
5972 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5973 DRM_DEBUG_KMS("probing DP_B\n");
5974 intel_dp_init(dev, DP_B);
5978 /* Before G4X SDVOC doesn't have its own detect register */
5980 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5981 DRM_DEBUG_KMS("probing SDVOC\n");
5982 found = intel_sdvo_init(dev, SDVOC);
5985 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5987 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5988 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5989 intel_hdmi_init(dev, SDVOC);
5991 if (SUPPORTS_INTEGRATED_DP(dev)) {
5992 DRM_DEBUG_KMS("probing DP_C\n");
5993 intel_dp_init(dev, DP_C);
5997 if (SUPPORTS_INTEGRATED_DP(dev) &&
5998 (I915_READ(DP_D) & DP_DETECTED)) {
5999 DRM_DEBUG_KMS("probing DP_D\n");
6000 intel_dp_init(dev, DP_D);
6002 } else if (IS_GEN2(dev)) {
6006 intel_dvo_init(dev);
6010 if (SUPPORTS_TV(dev))
6013 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6014 encoder->base.possible_crtcs = encoder->crtc_mask;
6015 encoder->base.possible_clones =
6016 intel_encoder_clones(dev, encoder->clone_mask);
6019 /* disable all the possible outputs/crtcs before entering KMS mode */
6020 drm_helper_disable_unused_functions(dev);
6022 if (HAS_PCH_SPLIT(dev))
6023 ironlake_init_pch_refclk(dev);
6026 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6028 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6030 drm_framebuffer_cleanup(fb);
6031 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6033 drm_free(intel_fb, DRM_MEM_KMS);
6036 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6037 struct drm_file *file,
6038 unsigned int *handle)
6040 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6041 struct drm_i915_gem_object *obj = intel_fb->obj;
6043 return drm_gem_handle_create(file, &obj->base, handle);
6046 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6047 .destroy = intel_user_framebuffer_destroy,
6048 .create_handle = intel_user_framebuffer_create_handle,
6051 int intel_framebuffer_init(struct drm_device *dev,
6052 struct intel_framebuffer *intel_fb,
6053 struct drm_mode_fb_cmd2 *mode_cmd,
6054 struct drm_i915_gem_object *obj)
6058 if (obj->tiling_mode == I915_TILING_Y)
6061 if (mode_cmd->pitches[0] & 63)
6064 switch (mode_cmd->pixel_format) {
6065 case DRM_FORMAT_RGB332:
6066 case DRM_FORMAT_RGB565:
6067 case DRM_FORMAT_XRGB8888:
6068 case DRM_FORMAT_XBGR8888:
6069 case DRM_FORMAT_ARGB8888:
6070 case DRM_FORMAT_XRGB2101010:
6071 case DRM_FORMAT_ARGB2101010:
6072 /* RGB formats are common across chipsets */
6074 case DRM_FORMAT_YUYV:
6075 case DRM_FORMAT_UYVY:
6076 case DRM_FORMAT_YVYU:
6077 case DRM_FORMAT_VYUY:
6080 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6081 mode_cmd->pixel_format);
6085 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6087 DRM_ERROR("framebuffer init failed %d\n", ret);
6091 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6092 intel_fb->obj = obj;
6096 static struct drm_framebuffer *
6097 intel_user_framebuffer_create(struct drm_device *dev,
6098 struct drm_file *filp,
6099 struct drm_mode_fb_cmd2 *mode_cmd)
6101 struct drm_i915_gem_object *obj;
6103 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6104 mode_cmd->handles[0]));
6105 if (&obj->base == NULL)
6106 return ERR_PTR(-ENOENT);
6108 return intel_framebuffer_create(dev, mode_cmd, obj);
6111 static const struct drm_mode_config_funcs intel_mode_funcs = {
6112 .fb_create = intel_user_framebuffer_create,
6113 .output_poll_changed = intel_fb_output_poll_changed,
6116 /* Set up chip specific display functions */
6117 static void intel_init_display(struct drm_device *dev)
6119 struct drm_i915_private *dev_priv = dev->dev_private;
6121 /* We always want a DPMS function */
6122 if (HAS_PCH_SPLIT(dev)) {
6123 dev_priv->display.dpms = ironlake_crtc_dpms;
6124 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
6125 dev_priv->display.update_plane = ironlake_update_plane;
6127 dev_priv->display.dpms = i9xx_crtc_dpms;
6128 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
6129 dev_priv->display.update_plane = i9xx_update_plane;
6132 if (I915_HAS_FBC(dev)) {
6133 if (HAS_PCH_SPLIT(dev)) {
6134 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6135 dev_priv->display.enable_fbc = ironlake_enable_fbc;
6136 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6137 } else if (IS_GM45(dev)) {
6138 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6139 dev_priv->display.enable_fbc = g4x_enable_fbc;
6140 dev_priv->display.disable_fbc = g4x_disable_fbc;
6141 } else if (IS_CRESTLINE(dev)) {
6142 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6143 dev_priv->display.enable_fbc = i8xx_enable_fbc;
6144 dev_priv->display.disable_fbc = i8xx_disable_fbc;
6146 /* 855GM needs testing */
6149 /* Returns the core display clock speed */
6150 if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
6151 dev_priv->display.get_display_clock_speed =
6152 i945_get_display_clock_speed;
6153 else if (IS_I915G(dev))
6154 dev_priv->display.get_display_clock_speed =
6155 i915_get_display_clock_speed;
6156 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
6157 dev_priv->display.get_display_clock_speed =
6158 i9xx_misc_get_display_clock_speed;
6159 else if (IS_I915GM(dev))
6160 dev_priv->display.get_display_clock_speed =
6161 i915gm_get_display_clock_speed;
6162 else if (IS_I865G(dev))
6163 dev_priv->display.get_display_clock_speed =
6164 i865_get_display_clock_speed;
6165 else if (IS_I85X(dev))
6166 dev_priv->display.get_display_clock_speed =
6167 i855_get_display_clock_speed;
6169 dev_priv->display.get_display_clock_speed =
6170 i830_get_display_clock_speed;
6172 /* For FIFO watermark updates */
6173 if (HAS_PCH_SPLIT(dev)) {
6175 /* IVB configs may use multi-threaded forcewake */
6176 if (IS_IVYBRIDGE(dev)) {
6179 /* A small trick here - if the bios hasn't configured MT forcewake,
6180 * and if the device is in RC6, then force_wake_mt_get will not wake
6181 * the device and the ECOBUS read will return zero. Which will be
6182 * (correctly) interpreted by the test below as MT forcewake being
6186 ecobus = I915_READ_NOTRACE(ECOBUS);
6189 if (ecobus & FORCEWAKE_MT_ENABLE) {
6190 DRM_DEBUG_KMS("Using MT version of forcewake\n");
6194 if (HAS_PCH_IBX(dev))
6195 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
6196 else if (HAS_PCH_CPT(dev))
6197 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
6200 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
6201 dev_priv->display.update_wm = ironlake_update_wm;
6203 DRM_DEBUG_KMS("Failed to get proper latency. "
6205 dev_priv->display.update_wm = NULL;
6207 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6208 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
6209 dev_priv->display.write_eld = ironlake_write_eld;
6210 } else if (IS_GEN6(dev)) {
6211 if (SNB_READ_WM0_LATENCY()) {
6212 dev_priv->display.update_wm = sandybridge_update_wm;
6213 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
6215 DRM_DEBUG_KMS("Failed to read display plane latency. "
6217 dev_priv->display.update_wm = NULL;
6219 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6220 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
6221 dev_priv->display.write_eld = ironlake_write_eld;
6222 } else if (IS_IVYBRIDGE(dev)) {
6223 /* FIXME: detect B0+ stepping and use auto training */
6224 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
6225 if (SNB_READ_WM0_LATENCY()) {
6226 dev_priv->display.update_wm = sandybridge_update_wm;
6227 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
6229 DRM_DEBUG_KMS("Failed to read display plane latency. "
6231 dev_priv->display.update_wm = NULL;
6233 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6234 dev_priv->display.write_eld = ironlake_write_eld;
6236 dev_priv->display.update_wm = NULL;
6237 } else if (IS_PINEVIEW(dev)) {
6238 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6241 dev_priv->mem_freq)) {
6242 DRM_INFO("failed to find known CxSR latency "
6243 "(found ddr%s fsb freq %d, mem freq %d), "
6245 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6246 dev_priv->fsb_freq, dev_priv->mem_freq);
6247 /* Disable CxSR and never update its watermark again */
6248 pineview_disable_cxsr(dev);
6249 dev_priv->display.update_wm = NULL;
6251 dev_priv->display.update_wm = pineview_update_wm;
6252 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6253 } else if (IS_G4X(dev)) {
6254 dev_priv->display.write_eld = g4x_write_eld;
6255 dev_priv->display.update_wm = g4x_update_wm;
6256 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6257 } else if (IS_GEN4(dev)) {
6258 dev_priv->display.update_wm = i965_update_wm;
6259 if (IS_CRESTLINE(dev))
6260 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6261 else if (IS_BROADWATER(dev))
6262 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6263 } else if (IS_GEN3(dev)) {
6264 dev_priv->display.update_wm = i9xx_update_wm;
6265 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6266 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6267 } else if (IS_I865G(dev)) {
6268 dev_priv->display.update_wm = i830_update_wm;
6269 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6270 dev_priv->display.get_fifo_size = i830_get_fifo_size;
6271 } else if (IS_I85X(dev)) {
6272 dev_priv->display.update_wm = i9xx_update_wm;
6273 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6274 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6276 dev_priv->display.update_wm = i830_update_wm;
6277 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6279 dev_priv->display.get_fifo_size = i845_get_fifo_size;
6281 dev_priv->display.get_fifo_size = i830_get_fifo_size;
6284 /* Default just returns -ENODEV to indicate unsupported */
6285 dev_priv->display.queue_flip = intel_default_queue_flip;
6287 switch (INTEL_INFO(dev)->gen) {
6289 dev_priv->display.queue_flip = intel_gen2_queue_flip;
6293 dev_priv->display.queue_flip = intel_gen3_queue_flip;
6298 dev_priv->display.queue_flip = intel_gen4_queue_flip;
6302 dev_priv->display.queue_flip = intel_gen6_queue_flip;
6305 dev_priv->display.queue_flip = intel_gen7_queue_flip;
6311 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6312 * resume, or other times. This quirk makes sure that's the case for
6315 static void quirk_pipea_force(struct drm_device *dev)
6317 struct drm_i915_private *dev_priv = dev->dev_private;
6319 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6320 DRM_DEBUG("applying pipe a force quirk\n");
6324 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
6326 static void quirk_ssc_force_disable(struct drm_device *dev)
6328 struct drm_i915_private *dev_priv = dev->dev_private;
6329 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
6332 struct intel_quirk {
6334 int subsystem_vendor;
6335 int subsystem_device;
6336 void (*hook)(struct drm_device *dev);
6339 #define PCI_ANY_ID (~0u)
6341 struct intel_quirk intel_quirks[] = {
6342 /* HP Mini needs pipe A force quirk (LP: #322104) */
6343 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
6345 /* Thinkpad R31 needs pipe A force quirk */
6346 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6347 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6348 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6350 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6351 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
6352 /* ThinkPad X40 needs pipe A force quirk */
6354 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6355 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6357 /* 855 & before need to leave pipe A & dpll A up */
6358 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6359 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6361 /* Lenovo U160 cannot use SSC on LVDS */
6362 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
6364 /* Sony Vaio Y cannot use SSC on LVDS */
6365 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
6368 static void intel_init_quirks(struct drm_device *dev)
6370 struct intel_quirk *q;
6375 for (i = 0; i < DRM_ARRAY_SIZE(intel_quirks); i++) {
6376 q = &intel_quirks[i];
6377 if (pci_get_device(d) == q->device &&
6378 (pci_get_subvendor(d) == q->subsystem_vendor ||
6379 q->subsystem_vendor == PCI_ANY_ID) &&
6380 (pci_get_subdevice(d) == q->subsystem_device ||
6381 q->subsystem_device == PCI_ANY_ID))
6386 /* Disable the VGA plane that we never use */
6387 static void i915_disable_vga(struct drm_device *dev)
6389 struct drm_i915_private *dev_priv = dev->dev_private;
6393 if (HAS_PCH_SPLIT(dev))
6394 vga_reg = CPU_VGACNTRL;
6399 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6401 outb(VGA_SR_INDEX, 1);
6402 sr1 = inb(VGA_SR_DATA);
6403 outb(VGA_SR_DATA, sr1 | 1 << 5);
6405 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6409 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6410 POSTING_READ(vga_reg);
6413 void intel_modeset_init(struct drm_device *dev)
6415 struct drm_i915_private *dev_priv = dev->dev_private;
6418 drm_mode_config_init(dev);
6420 dev->mode_config.min_width = 0;
6421 dev->mode_config.min_height = 0;
6423 dev->mode_config.preferred_depth = 24;
6424 dev->mode_config.prefer_shadow = 1;
6426 dev->mode_config.funcs = __DECONST(struct drm_mode_config_funcs *,
6429 intel_init_quirks(dev);
6431 intel_init_display(dev);
6434 dev->mode_config.max_width = 2048;
6435 dev->mode_config.max_height = 2048;
6436 } else if (IS_GEN3(dev)) {
6437 dev->mode_config.max_width = 4096;
6438 dev->mode_config.max_height = 4096;
6440 dev->mode_config.max_width = 8192;
6441 dev->mode_config.max_height = 8192;
6443 dev->mode_config.fb_base = dev->agp->base;
6445 DRM_DEBUG_KMS("%d display pipe%s available.\n",
6446 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6448 for (i = 0; i < dev_priv->num_pipe; i++) {
6449 intel_crtc_init(dev, i);
6450 ret = intel_plane_init(dev, i);
6452 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
6455 /* Just disable it once at startup */
6456 i915_disable_vga(dev);
6457 intel_setup_outputs(dev);
6459 intel_init_clock_gating(dev);
6461 if (IS_IRONLAKE_M(dev)) {
6462 ironlake_enable_drps(dev);
6463 intel_init_emon(dev);
6467 gen6_enable_rps(dev_priv);
6468 gen6_update_ring_freq(dev_priv);
6471 callout_init_mp(&dev_priv->idle_callout);
6474 void intel_modeset_gem_init(struct drm_device *dev)
6476 if (IS_IRONLAKE_M(dev))
6477 ironlake_enable_rc6(dev);
6479 intel_setup_overlay(dev);
6482 void intel_modeset_cleanup(struct drm_device *dev)
6484 struct drm_i915_private *dev_priv = dev->dev_private;
6485 struct drm_crtc *crtc;
6486 struct intel_crtc *intel_crtc;
6488 drm_kms_helper_poll_fini(dev);
6492 intel_unregister_dsm_handler();
6495 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6496 /* Skip inactive CRTCs */
6500 intel_crtc = to_intel_crtc(crtc);
6501 intel_increase_pllclock(crtc);
6504 intel_disable_fbc(dev);
6506 if (IS_IRONLAKE_M(dev))
6507 ironlake_disable_drps(dev);
6509 gen6_disable_rps(dev);
6511 if (IS_IRONLAKE_M(dev))
6512 ironlake_disable_rc6(dev);
6516 /* Disable the irq before mode object teardown, for the irq might
6517 * enqueue unpin/hotplug work. */
6518 drm_irq_uninstall(dev);
6519 cancel_work_sync(&dev_priv->hotplug_work);
6520 cancel_work_sync(&dev_priv->rps.work);
6522 /* flush any delayed tasks or pending work */
6523 flush_scheduled_work();
6525 drm_mode_config_cleanup(dev);
6529 * Return which encoder is currently attached for connector.
6531 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6533 return &intel_attached_encoder(connector)->base;
6536 void intel_connector_attach_encoder(struct intel_connector *connector,
6537 struct intel_encoder *encoder)
6539 connector->encoder = encoder;
6540 drm_mode_connector_attach_encoder(&connector->base,
6545 * set vga decode state - true == enable VGA decode
6547 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6549 struct drm_i915_private *dev_priv;
6550 device_t bridge_dev;
6553 dev_priv = dev->dev_private;
6554 bridge_dev = intel_gtt_get_bridge_device();
6555 gmch_ctrl = pci_read_config(bridge_dev, INTEL_GMCH_CTRL, 2);
6557 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6559 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6560 pci_write_config(bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl, 2);
6564 struct intel_display_error_state {
6565 struct intel_cursor_error_state {
6572 struct intel_pipe_error_state {
6584 struct intel_plane_error_state {
6595 struct intel_display_error_state *
6596 intel_display_capture_error_state(struct drm_device *dev)
6598 drm_i915_private_t *dev_priv = dev->dev_private;
6599 struct intel_display_error_state *error;
6602 error = kmalloc(sizeof(*error), DRM_MEM_KMS, M_NOWAIT);
6606 for (i = 0; i < 2; i++) {
6607 error->cursor[i].control = I915_READ(CURCNTR(i));
6608 error->cursor[i].position = I915_READ(CURPOS(i));
6609 error->cursor[i].base = I915_READ(CURBASE(i));
6611 error->plane[i].control = I915_READ(DSPCNTR(i));
6612 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
6613 error->plane[i].size = I915_READ(DSPSIZE(i));
6614 error->plane[i].pos = I915_READ(DSPPOS(i));
6615 error->plane[i].addr = I915_READ(DSPADDR(i));
6616 if (INTEL_INFO(dev)->gen >= 4) {
6617 error->plane[i].surface = I915_READ(DSPSURF(i));
6618 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
6621 error->pipe[i].conf = I915_READ(PIPECONF(i));
6622 error->pipe[i].source = I915_READ(PIPESRC(i));
6623 error->pipe[i].htotal = I915_READ(HTOTAL(i));
6624 error->pipe[i].hblank = I915_READ(HBLANK(i));
6625 error->pipe[i].hsync = I915_READ(HSYNC(i));
6626 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
6627 error->pipe[i].vblank = I915_READ(VBLANK(i));
6628 error->pipe[i].vsync = I915_READ(VSYNC(i));
6635 intel_display_print_error_state(struct sbuf *m,
6636 struct drm_device *dev,
6637 struct intel_display_error_state *error)
6641 for (i = 0; i < 2; i++) {
6642 sbuf_printf(m, "Pipe [%d]:\n", i);
6643 sbuf_printf(m, " CONF: %08x\n", error->pipe[i].conf);
6644 sbuf_printf(m, " SRC: %08x\n", error->pipe[i].source);
6645 sbuf_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
6646 sbuf_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
6647 sbuf_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
6648 sbuf_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
6649 sbuf_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
6650 sbuf_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
6652 sbuf_printf(m, "Plane [%d]:\n", i);
6653 sbuf_printf(m, " CNTR: %08x\n", error->plane[i].control);
6654 sbuf_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
6655 sbuf_printf(m, " SIZE: %08x\n", error->plane[i].size);
6656 sbuf_printf(m, " POS: %08x\n", error->plane[i].pos);
6657 sbuf_printf(m, " ADDR: %08x\n", error->plane[i].addr);
6658 if (INTEL_INFO(dev)->gen >= 4) {
6659 sbuf_printf(m, " SURF: %08x\n", error->plane[i].surface);
6660 sbuf_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
6663 sbuf_printf(m, "Cursor [%d]:\n", i);
6664 sbuf_printf(m, " CNTR: %08x\n", error->cursor[i].control);
6665 sbuf_printf(m, " POS: %08x\n", error->cursor[i].position);
6666 sbuf_printf(m, " BASE: %08x\n", error->cursor[i].base);