2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
26 * Copyright (c) 2011 The FreeBSD Foundation
27 * All rights reserved.
29 * This software was developed by Konstantin Belousov under sponsorship from
30 * the FreeBSD Foundation.
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
35 * 1. Redistributions of source code must retain the above copyright
36 * notice, this list of conditions and the following disclaimer.
37 * 2. Redistributions in binary form must reproduce the above copyright
38 * notice, this list of conditions and the following disclaimer in the
39 * documentation and/or other materials provided with the distribution.
41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
42 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
44 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
47 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
48 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
49 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
50 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
55 #include <machine/md_var.h>
58 #include <drm/drm_vma_manager.h>
59 #include <drm/i915_drm.h>
61 #include "i915_trace.h"
62 #include "intel_drv.h"
63 #include <linux/shmem_fs.h>
64 #include <linux/slab.h>
65 #include <linux/swap.h>
66 #include <linux/pci.h>
68 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
69 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
71 static __must_check int
72 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
74 static __must_check int
75 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
76 struct i915_address_space *vm,
78 bool map_and_fenceable,
80 static int i915_gem_phys_pwrite(struct drm_device *dev,
81 struct drm_i915_gem_object *obj,
82 struct drm_i915_gem_pwrite *args,
83 struct drm_file *file);
85 static void i915_gem_write_fence(struct drm_device *dev, int reg,
86 struct drm_i915_gem_object *obj);
87 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
88 struct drm_i915_fence_reg *fence,
91 static unsigned long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
92 static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
93 static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
95 static bool cpu_cache_is_coherent(struct drm_device *dev,
96 enum i915_cache_level level)
98 return HAS_LLC(dev) || level != I915_CACHE_NONE;
101 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
103 if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
106 return obj->pin_display;
109 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
111 if (obj->tiling_mode)
112 i915_gem_release_mmap(obj);
114 /* As we do not have an associated fence register, we will force
115 * a tiling change if we ever need to acquire one.
117 obj->fence_dirty = false;
118 obj->fence_reg = I915_FENCE_REG_NONE;
121 /* some bookkeeping */
122 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
125 spin_lock(&dev_priv->mm.object_stat_lock);
126 dev_priv->mm.object_count++;
127 dev_priv->mm.object_memory += size;
128 spin_unlock(&dev_priv->mm.object_stat_lock);
131 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
134 spin_lock(&dev_priv->mm.object_stat_lock);
135 dev_priv->mm.object_count--;
136 dev_priv->mm.object_memory -= size;
137 spin_unlock(&dev_priv->mm.object_stat_lock);
141 i915_gem_wait_for_error(struct i915_gpu_error *error)
145 #define EXIT_COND (!i915_reset_in_progress(error) || \
146 i915_terminally_wedged(error))
151 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
152 * userspace. If it takes that long something really bad is going on and
153 * we should simply try to bail out and fail as gracefully as possible.
155 ret = wait_event_interruptible_timeout(error->reset_queue,
159 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
161 } else if (ret < 0) {
169 int i915_mutex_lock_interruptible(struct drm_device *dev)
171 struct drm_i915_private *dev_priv = dev->dev_private;
174 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
178 ret = lockmgr(&dev->struct_mutex, LK_EXCLUSIVE|LK_SLEEPFAIL);
182 WARN_ON(i915_verify_lists(dev));
187 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
189 return i915_gem_obj_bound_any(obj) && !obj->active;
193 i915_gem_init_ioctl(struct drm_device *dev, void *data,
194 struct drm_file *file)
196 struct drm_i915_private *dev_priv = dev->dev_private;
197 struct drm_i915_gem_init *args = data;
199 if (drm_core_check_feature(dev, DRIVER_MODESET))
202 if (args->gtt_start >= args->gtt_end ||
203 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
206 /* GEM with user mode setting was never supported on ilk and later. */
207 if (INTEL_INFO(dev)->gen >= 5)
210 mutex_lock(&dev->struct_mutex);
211 dev_priv->gtt.mappable_end = args->gtt_end;
212 kprintf("INITGLOBALGTT GTT_START %016jx\n", (uintmax_t)args->gtt_start);
213 i915_gem_init_global_gtt(dev);
215 i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
218 mutex_unlock(&dev->struct_mutex);
224 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
225 struct drm_file *file)
227 struct drm_i915_private *dev_priv = dev->dev_private;
228 struct drm_i915_gem_get_aperture *args = data;
229 struct drm_i915_gem_object *obj;
233 mutex_lock(&dev->struct_mutex);
234 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
236 pinned += i915_gem_obj_ggtt_size(obj);
237 mutex_unlock(&dev->struct_mutex);
239 args->aper_size = dev_priv->gtt.base.total;
240 args->aper_available_size = args->aper_size - pinned;
245 void *i915_gem_object_alloc(struct drm_device *dev)
247 return kmalloc(sizeof(struct drm_i915_gem_object),
248 M_DRM, M_WAITOK | M_ZERO);
251 void i915_gem_object_free(struct drm_i915_gem_object *obj)
257 i915_gem_create(struct drm_file *file,
258 struct drm_device *dev,
262 struct drm_i915_gem_object *obj;
266 size = roundup(size, PAGE_SIZE);
270 /* Allocate the new object */
271 obj = i915_gem_alloc_object(dev, size);
275 ret = drm_gem_handle_create(file, &obj->base, &handle);
276 /* drop reference from allocate - handle holds it now */
277 drm_gem_object_unreference_unlocked(&obj->base);
286 i915_gem_dumb_create(struct drm_file *file,
287 struct drm_device *dev,
288 struct drm_mode_create_dumb *args)
290 /* have to work out size/pitch and return them */
291 args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
292 args->size = args->pitch * args->height;
293 return i915_gem_create(file, dev,
294 args->size, &args->handle);
298 * Creates a new mm object and returns a handle to it.
301 i915_gem_create_ioctl(struct drm_device *dev, void *data,
302 struct drm_file *file)
304 struct drm_i915_gem_create *args = data;
306 return i915_gem_create(file, dev,
307 args->size, &args->handle);
311 __copy_to_user_swizzled(char __user *cpu_vaddr,
312 const char *gpu_vaddr, int gpu_offset,
315 int ret, cpu_offset = 0;
318 int cacheline_end = ALIGN(gpu_offset + 1, 64);
319 int this_length = min(cacheline_end - gpu_offset, length);
320 int swizzled_gpu_offset = gpu_offset ^ 64;
322 ret = __copy_to_user(cpu_vaddr + cpu_offset,
323 gpu_vaddr + swizzled_gpu_offset,
328 cpu_offset += this_length;
329 gpu_offset += this_length;
330 length -= this_length;
337 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
338 const char __user *cpu_vaddr,
341 int ret, cpu_offset = 0;
344 int cacheline_end = ALIGN(gpu_offset + 1, 64);
345 int this_length = min(cacheline_end - gpu_offset, length);
346 int swizzled_gpu_offset = gpu_offset ^ 64;
348 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
349 cpu_vaddr + cpu_offset,
354 cpu_offset += this_length;
355 gpu_offset += this_length;
356 length -= this_length;
362 /* Per-page copy function for the shmem pread fastpath.
363 * Flushes invalid cachelines before reading the target if
364 * needs_clflush is set. */
366 shmem_pread_fast(struct vm_page *page, int shmem_page_offset, int page_length,
367 char __user *user_data,
368 bool page_do_bit17_swizzling, bool needs_clflush)
373 if (unlikely(page_do_bit17_swizzling))
376 vaddr = kmap_atomic(page);
378 drm_clflush_virt_range(vaddr + shmem_page_offset,
380 ret = __copy_to_user_inatomic(user_data,
381 vaddr + shmem_page_offset,
383 kunmap_atomic(vaddr);
385 return ret ? -EFAULT : 0;
389 shmem_clflush_swizzled_range(char *addr, unsigned long length,
392 if (unlikely(swizzled)) {
393 unsigned long start = (unsigned long) addr;
394 unsigned long end = (unsigned long) addr + length;
396 /* For swizzling simply ensure that we always flush both
397 * channels. Lame, but simple and it works. Swizzled
398 * pwrite/pread is far from a hotpath - current userspace
399 * doesn't use it at all. */
400 start = round_down(start, 128);
401 end = round_up(end, 128);
403 drm_clflush_virt_range((void *)start, end - start);
405 drm_clflush_virt_range(addr, length);
410 /* Only difference to the fast-path function is that this can handle bit17
411 * and uses non-atomic copy and kmap functions. */
413 shmem_pread_slow(struct vm_page *page, int shmem_page_offset, int page_length,
414 char __user *user_data,
415 bool page_do_bit17_swizzling, bool needs_clflush)
422 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
424 page_do_bit17_swizzling);
426 if (page_do_bit17_swizzling)
427 ret = __copy_to_user_swizzled(user_data,
428 vaddr, shmem_page_offset,
431 ret = __copy_to_user(user_data,
432 vaddr + shmem_page_offset,
436 return ret ? - EFAULT : 0;
440 i915_gem_shmem_pread(struct drm_device *dev,
441 struct drm_i915_gem_object *obj,
442 struct drm_i915_gem_pread *args,
443 struct drm_file *file)
445 char __user *user_data;
448 int shmem_page_offset, page_length, ret = 0;
449 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
451 int needs_clflush = 0;
454 user_data = to_user_ptr(args->data_ptr);
457 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
459 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
460 /* If we're not in the cpu read domain, set ourself into the gtt
461 * read domain and manually flush cachelines (if required). This
462 * optimizes for the case when the gpu will dirty the data
463 * anyway again before the next pread happens. */
464 needs_clflush = !cpu_cache_is_coherent(dev, obj->cache_level);
465 ret = i915_gem_object_wait_rendering(obj, true);
470 ret = i915_gem_object_get_pages(obj);
474 i915_gem_object_pin_pages(obj);
476 offset = args->offset;
478 for (i = 0; i < (obj->base.size >> PAGE_SHIFT); i++) {
479 struct vm_page *page = obj->pages[i];
484 /* Operation in this page
486 * shmem_page_offset = offset within page in shmem file
487 * page_length = bytes to copy for this page
489 shmem_page_offset = offset_in_page(offset);
490 page_length = remain;
491 if ((shmem_page_offset + page_length) > PAGE_SIZE)
492 page_length = PAGE_SIZE - shmem_page_offset;
494 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
495 (page_to_phys(page) & (1 << 17)) != 0;
497 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
498 user_data, page_do_bit17_swizzling,
503 mutex_unlock(&dev->struct_mutex);
505 if (likely(!i915_prefault_disable) && !prefaulted) {
506 ret = fault_in_multipages_writeable(user_data, remain);
507 /* Userspace is tricking us, but we've already clobbered
508 * its pages with the prefault and promised to write the
509 * data up to the first fault. Hence ignore any errors
510 * and just continue. */
515 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
516 user_data, page_do_bit17_swizzling,
519 mutex_lock(&dev->struct_mutex);
522 mark_page_accessed(page);
527 remain -= page_length;
528 user_data += page_length;
529 offset += page_length;
533 i915_gem_object_unpin_pages(obj);
539 * Reads data from the object referenced by handle.
541 * On error, the contents of *data are undefined.
544 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
545 struct drm_file *file)
547 struct drm_i915_gem_pread *args = data;
548 struct drm_i915_gem_object *obj;
554 ret = i915_mutex_lock_interruptible(dev);
558 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
559 if (&obj->base == NULL) {
564 /* Bounds check source. */
565 if (args->offset > obj->base.size ||
566 args->size > obj->base.size - args->offset) {
571 trace_i915_gem_object_pread(obj, args->offset, args->size);
573 ret = i915_gem_shmem_pread(dev, obj, args, file);
576 drm_gem_object_unreference(&obj->base);
578 mutex_unlock(&dev->struct_mutex);
582 /* This is the fast write path which cannot handle
583 * page faults in the source data
586 #if 0 /* XXX: buggy on core2 machines */
588 fast_user_write(struct io_mapping *mapping,
589 loff_t page_base, int page_offset,
590 char __user *user_data,
593 void __iomem *vaddr_atomic;
595 unsigned long unwritten;
597 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
598 /* We can use the cpu mem copy function because this is X86. */
599 vaddr = (char __force*)vaddr_atomic + page_offset;
600 unwritten = __copy_from_user_inatomic_nocache(vaddr,
602 io_mapping_unmap_atomic(vaddr_atomic);
608 i915_gem_gtt_write(struct drm_device *dev, struct drm_i915_gem_object *obj,
609 uint64_t data_ptr, uint64_t size, uint64_t offset, struct drm_file *file)
615 * Pass the unaligned physical address and size to pmap_mapdev_attr()
616 * so it can properly calculate whether an extra page needs to be
617 * mapped or not to cover the requested range. The function will
618 * add the page offset into the returned mkva for us.
620 mkva = (vm_offset_t)pmap_mapdev_attr(dev->agp->base +
621 i915_gem_obj_ggtt_offset(obj) + offset, size, PAT_WRITE_COMBINING);
622 ret = -copyin_nofault((void *)(uintptr_t)data_ptr, (char *)mkva, size);
623 pmap_unmapdev(mkva, size);
628 * This is the fast pwrite path, where we copy the data directly from the
629 * user into the GTT, uncached.
632 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
633 struct drm_i915_gem_object *obj,
634 struct drm_i915_gem_pwrite *args,
635 struct drm_file *file)
638 loff_t offset, page_base;
639 char __user *user_data;
640 int page_offset, page_length, ret;
642 ret = i915_gem_obj_ggtt_pin(obj, 0, true, true);
646 ret = i915_gem_object_set_to_gtt_domain(obj, true);
650 ret = i915_gem_object_put_fence(obj);
654 user_data = to_user_ptr(args->data_ptr);
657 offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
660 /* Operation in this page
662 * page_base = page offset within aperture
663 * page_offset = offset within page
664 * page_length = bytes to copy for this page
666 page_base = offset & ~PAGE_MASK;
667 page_offset = offset_in_page(offset);
668 page_length = remain;
669 if ((page_offset + remain) > PAGE_SIZE)
670 page_length = PAGE_SIZE - page_offset;
672 /* If we get a fault while copying data, then (presumably) our
673 * source page isn't available. Return the error and we'll
674 * retry in the slow path.
677 if (fast_user_write(dev_priv->gtt.mappable, page_base,
678 page_offset, user_data, page_length)) {
680 if (i915_gem_gtt_write(dev, obj, args->data_ptr, args->size, args->offset, file)) {
686 remain -= page_length;
687 user_data += page_length;
688 offset += page_length;
692 i915_gem_object_unpin(obj);
697 /* Per-page copy function for the shmem pwrite fastpath.
698 * Flushes invalid cachelines before writing to the target if
699 * needs_clflush_before is set and flushes out any written cachelines after
700 * writing if needs_clflush is set. */
702 shmem_pwrite_fast(struct vm_page *page, int shmem_page_offset, int page_length,
703 char __user *user_data,
704 bool page_do_bit17_swizzling,
705 bool needs_clflush_before,
706 bool needs_clflush_after)
711 if (unlikely(page_do_bit17_swizzling))
714 vaddr = kmap_atomic(page);
715 if (needs_clflush_before)
716 drm_clflush_virt_range(vaddr + shmem_page_offset,
718 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
721 if (needs_clflush_after)
722 drm_clflush_virt_range(vaddr + shmem_page_offset,
724 kunmap_atomic(vaddr);
726 return ret ? -EFAULT : 0;
729 /* Only difference to the fast-path function is that this can handle bit17
730 * and uses non-atomic copy and kmap functions. */
732 shmem_pwrite_slow(struct vm_page *page, int shmem_page_offset, int page_length,
733 char __user *user_data,
734 bool page_do_bit17_swizzling,
735 bool needs_clflush_before,
736 bool needs_clflush_after)
742 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
743 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
745 page_do_bit17_swizzling);
746 if (page_do_bit17_swizzling)
747 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
751 ret = __copy_from_user(vaddr + shmem_page_offset,
754 if (needs_clflush_after)
755 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
757 page_do_bit17_swizzling);
760 return ret ? -EFAULT : 0;
764 i915_gem_shmem_pwrite(struct drm_device *dev,
765 struct drm_i915_gem_object *obj,
766 struct drm_i915_gem_pwrite *args,
767 struct drm_file *file)
771 char __user *user_data;
772 int shmem_page_offset, page_length, ret = 0;
773 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
774 int hit_slowpath = 0;
775 int needs_clflush_after = 0;
776 int needs_clflush_before = 0;
779 user_data = to_user_ptr(args->data_ptr);
782 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
784 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
785 /* If we're not in the cpu write domain, set ourself into the gtt
786 * write domain and manually flush cachelines (if required). This
787 * optimizes for the case when the gpu will use the data
788 * right away and we therefore have to clflush anyway. */
789 needs_clflush_after = cpu_write_needs_clflush(obj);
790 ret = i915_gem_object_wait_rendering(obj, false);
794 /* Same trick applies to invalidate partially written cachelines read
796 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
797 needs_clflush_before =
798 !cpu_cache_is_coherent(dev, obj->cache_level);
800 ret = i915_gem_object_get_pages(obj);
804 i915_gem_object_pin_pages(obj);
806 offset = args->offset;
809 VM_OBJECT_LOCK(obj->base.vm_obj);
810 vm_object_pip_add(obj->base.vm_obj, 1);
811 for (i = 0; i < (obj->base.size >> PAGE_SHIFT); i++) {
812 struct vm_page *page = obj->pages[i];
813 int partial_cacheline_write;
815 if (i < offset >> PAGE_SHIFT)
821 /* Operation in this page
823 * shmem_page_offset = offset within page in shmem file
824 * page_length = bytes to copy for this page
826 shmem_page_offset = offset_in_page(offset);
828 page_length = remain;
829 if ((shmem_page_offset + page_length) > PAGE_SIZE)
830 page_length = PAGE_SIZE - shmem_page_offset;
832 /* If we don't overwrite a cacheline completely we need to be
833 * careful to have up-to-date data by first clflushing. Don't
834 * overcomplicate things and flush the entire patch. */
835 partial_cacheline_write = needs_clflush_before &&
836 ((shmem_page_offset | page_length)
837 & (cpu_clflush_line_size - 1));
839 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
840 (page_to_phys(page) & (1 << 17)) != 0;
842 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
843 user_data, page_do_bit17_swizzling,
844 partial_cacheline_write,
845 needs_clflush_after);
850 mutex_unlock(&dev->struct_mutex);
851 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
852 user_data, page_do_bit17_swizzling,
853 partial_cacheline_write,
854 needs_clflush_after);
856 mutex_lock(&dev->struct_mutex);
859 set_page_dirty(page);
860 mark_page_accessed(page);
865 remain -= page_length;
866 user_data += page_length;
867 offset += page_length;
869 vm_object_pip_wakeup(obj->base.vm_obj);
870 VM_OBJECT_UNLOCK(obj->base.vm_obj);
873 i915_gem_object_unpin_pages(obj);
877 * Fixup: Flush cpu caches in case we didn't flush the dirty
878 * cachelines in-line while writing and the object moved
879 * out of the cpu write domain while we've dropped the lock.
881 if (!needs_clflush_after &&
882 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
883 if (i915_gem_clflush_object(obj, obj->pin_display))
884 i915_gem_chipset_flush(dev);
888 if (needs_clflush_after)
889 i915_gem_chipset_flush(dev);
895 * Writes data to the object referenced by handle.
897 * On error, the contents of the buffer that were to be modified are undefined.
900 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
901 struct drm_file *file)
903 struct drm_i915_gem_pwrite *args = data;
904 struct drm_i915_gem_object *obj;
910 if (likely(!i915_prefault_disable)) {
911 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
917 ret = i915_mutex_lock_interruptible(dev);
921 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
922 if (&obj->base == NULL) {
927 /* Bounds check destination. */
928 if (args->offset > obj->base.size ||
929 args->size > obj->base.size - args->offset) {
934 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
937 /* We can only do the GTT pwrite on untiled buffers, as otherwise
938 * it would end up going through the fenced access, and we'll get
939 * different detiling behavior between reading and writing.
940 * pread/pwrite currently are reading and writing from the CPU
941 * perspective, requiring manual detiling by the client.
944 ret = i915_gem_phys_pwrite(dev, obj, args, file);
948 if (obj->tiling_mode == I915_TILING_NONE &&
949 obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
950 cpu_write_needs_clflush(obj)) {
951 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
952 /* Note that the gtt paths might fail with non-page-backed user
953 * pointers (e.g. gtt mappings when moving data between
954 * textures). Fallback to the shmem path in that case. */
957 if (ret == -EFAULT || ret == -ENOSPC)
958 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
961 drm_gem_object_unreference(&obj->base);
963 mutex_unlock(&dev->struct_mutex);
968 i915_gem_check_wedge(struct i915_gpu_error *error,
971 if (i915_reset_in_progress(error)) {
972 /* Non-interruptible callers can't handle -EAGAIN, hence return
973 * -EIO unconditionally for these. */
977 /* Recovery complete, but the reset failed ... */
978 if (i915_terminally_wedged(error))
988 * Compare seqno against outstanding lazy request. Emit a request if they are
992 i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
996 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
999 if (seqno == ring->outstanding_lazy_seqno)
1000 ret = i915_add_request(ring, NULL);
1006 static void fake_irq(unsigned long data)
1008 wake_up_process((struct task_struct *)data);
1011 static bool missed_irq(struct drm_i915_private *dev_priv,
1012 struct intel_ring_buffer *ring)
1014 return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1017 static bool can_wait_boost(struct drm_i915_file_private *file_priv)
1019 if (file_priv == NULL)
1022 return !atomic_xchg(&file_priv->rps_wait_boost, true);
1027 * __wait_seqno - wait until execution of seqno has finished
1028 * @ring: the ring expected to report seqno
1030 * @reset_counter: reset sequence associated with the given seqno
1031 * @interruptible: do an interruptible wait (normally yes)
1032 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1034 * Note: It is of utmost importance that the passed in seqno and reset_counter
1035 * values have been read by the caller in an smp safe manner. Where read-side
1036 * locks are involved, it is sufficient to read the reset_counter before
1037 * unlocking the lock that protects the seqno. For lockless tricks, the
1038 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1041 * Returns 0 if the seqno was found within the alloted time. Else returns the
1042 * errno with remaining time filled in timeout argument.
1044 static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
1045 unsigned reset_counter,
1046 bool interruptible, struct timespec *timeout)
1048 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1049 struct timespec before, now, wait_time={1,0};
1050 unsigned long timeout_jiffies;
1052 bool wait_forever = true;
1055 WARN(dev_priv->pc8.irqs_disabled, "IRQs disabled\n");
1057 if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1060 trace_i915_gem_request_wait_begin(ring, seqno);
1062 if (timeout != NULL) {
1063 wait_time = *timeout;
1064 wait_forever = false;
1067 timeout_jiffies = timespec_to_jiffies_timeout(&wait_time);
1069 if (WARN_ON(!ring->irq_get(ring)))
1072 /* Record current time in case interrupted by signal, or wedged * */
1073 getrawmonotonic(&before);
1076 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1077 i915_reset_in_progress(&dev_priv->gpu_error) || \
1078 reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1081 end = wait_event_interruptible_timeout(ring->irq_queue,
1085 end = wait_event_timeout(ring->irq_queue, EXIT_COND,
1088 /* We need to check whether any gpu reset happened in between
1089 * the caller grabbing the seqno and now ... */
1090 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1093 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1095 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1098 } while (end == 0 && wait_forever);
1100 getrawmonotonic(&now);
1102 ring->irq_put(ring);
1103 trace_i915_gem_request_wait_end(ring, seqno);
1107 struct timespec sleep_time = timespec_sub(now, before);
1108 *timeout = timespec_sub(*timeout, sleep_time);
1109 if (!timespec_valid(timeout)) /* i.e. negative time remains */
1110 set_normalized_timespec(timeout, 0, 0);
1115 case -EAGAIN: /* Wedged */
1116 case -ERESTARTSYS: /* Signal */
1118 case 0: /* Timeout */
1119 return -ETIMEDOUT; /* -ETIME on Linux */
1120 default: /* Completed */
1121 WARN_ON(end < 0); /* We're not aware of other errors */
1127 * Waits for a sequence number to be signaled, and cleans up the
1128 * request and object lists appropriately for that event.
1131 i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno)
1133 struct drm_device *dev = ring->dev;
1134 struct drm_i915_private *dev_priv = dev->dev_private;
1135 bool interruptible = dev_priv->mm.interruptible;
1138 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1141 ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1145 ret = i915_gem_check_olr(ring, seqno);
1149 return __wait_seqno(ring, seqno,
1150 atomic_read(&dev_priv->gpu_error.reset_counter),
1151 interruptible, NULL);
1155 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1156 struct intel_ring_buffer *ring)
1158 i915_gem_retire_requests_ring(ring);
1160 /* Manually manage the write flush as we may have not yet
1161 * retired the buffer.
1163 * Note that the last_write_seqno is always the earlier of
1164 * the two (read/write) seqno, so if we haved successfully waited,
1165 * we know we have passed the last write.
1167 obj->last_write_seqno = 0;
1168 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1174 * Ensures that all rendering to the object has completed and the object is
1175 * safe to unbind from the GTT or access from the CPU.
1177 static __must_check int
1178 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1181 struct intel_ring_buffer *ring = obj->ring;
1185 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1189 ret = i915_wait_seqno(ring, seqno);
1193 return i915_gem_object_wait_rendering__tail(obj, ring);
1196 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1197 * as the object state may change during this call.
1199 static __must_check int
1200 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1203 struct drm_device *dev = obj->base.dev;
1204 struct drm_i915_private *dev_priv = dev->dev_private;
1205 struct intel_ring_buffer *ring = obj->ring;
1206 unsigned reset_counter;
1210 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1211 BUG_ON(!dev_priv->mm.interruptible);
1213 seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1217 ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1221 ret = i915_gem_check_olr(ring, seqno);
1225 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1226 mutex_unlock(&dev->struct_mutex);
1227 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
1228 mutex_lock(&dev->struct_mutex);
1232 return i915_gem_object_wait_rendering__tail(obj, ring);
1236 * Called when user space prepares to use an object with the CPU, either
1237 * through the mmap ioctl's mapping or a GTT mapping.
1240 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1241 struct drm_file *file)
1243 struct drm_i915_gem_set_domain *args = data;
1244 struct drm_i915_gem_object *obj;
1245 uint32_t read_domains = args->read_domains;
1246 uint32_t write_domain = args->write_domain;
1249 /* Only handle setting domains to types used by the CPU. */
1250 if (write_domain & I915_GEM_GPU_DOMAINS)
1253 if (read_domains & I915_GEM_GPU_DOMAINS)
1256 /* Having something in the write domain implies it's in the read
1257 * domain, and only that read domain. Enforce that in the request.
1259 if (write_domain != 0 && read_domains != write_domain)
1262 ret = i915_mutex_lock_interruptible(dev);
1266 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1267 if (&obj->base == NULL) {
1272 /* Try to flush the object off the GPU without holding the lock.
1273 * We will repeat the flush holding the lock in the normal manner
1274 * to catch cases where we are gazumped.
1276 ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain);
1280 if (read_domains & I915_GEM_DOMAIN_GTT) {
1281 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1283 /* Silently promote "you're not bound, there was nothing to do"
1284 * to success, since the client was just asking us to
1285 * make sure everything was done.
1290 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1294 drm_gem_object_unreference(&obj->base);
1296 mutex_unlock(&dev->struct_mutex);
1301 * Called when user space has done writes to this buffer
1304 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1305 struct drm_file *file)
1307 struct drm_i915_gem_sw_finish *args = data;
1308 struct drm_i915_gem_object *obj;
1311 ret = i915_mutex_lock_interruptible(dev);
1315 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1316 if (&obj->base == NULL) {
1321 /* Pinned buffers may be scanout, so flush the cache */
1322 if (obj->pin_display)
1323 i915_gem_object_flush_cpu_write_domain(obj, true);
1325 drm_gem_object_unreference(&obj->base);
1327 mutex_unlock(&dev->struct_mutex);
1332 * Maps the contents of an object, returning the address it is mapped
1335 * While the mapping holds a reference on the contents of the object, it doesn't
1336 * imply a ref on the object itself.
1339 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1340 struct drm_file *file)
1342 struct drm_i915_gem_mmap *args = data;
1343 struct drm_gem_object *obj;
1345 struct proc *p = curproc;
1346 vm_map_t map = &p->p_vmspace->vm_map;
1350 obj = drm_gem_object_lookup(dev, file, args->handle);
1354 if (args->size == 0)
1357 size = round_page(args->size);
1358 if (map->size + size > p->p_rlimit[RLIMIT_VMEM].rlim_cur) {
1364 * Call hint to ensure that NULL is not returned as a valid address
1365 * and to reduce vm_map traversals.
1367 addr = vm_map_hint(p, 0, PROT_READ|PROT_WRITE);
1370 * Use 256KB alignment. It is unclear why this matters for a
1371 * virtual address but it appears to fix a number of application/X
1372 * crashes and kms console switching is much faster.
1374 vm_object_hold(obj->vm_obj);
1375 vm_object_reference_locked(obj->vm_obj);
1376 vm_object_drop(obj->vm_obj);
1378 rv = vm_map_find(map, obj->vm_obj, NULL,
1379 args->offset, &addr, args->size,
1380 256 * 1024, /* align */
1382 VM_MAPTYPE_NORMAL, /* maptype */
1383 VM_PROT_READ | VM_PROT_WRITE, /* prot */
1384 VM_PROT_READ | VM_PROT_WRITE, /* max */
1385 MAP_SHARED /* cow */);
1386 if (rv != KERN_SUCCESS) {
1387 vm_object_deallocate(obj->vm_obj);
1388 error = -vm_mmap_to_errno(rv);
1390 args->addr_ptr = (uint64_t)addr;
1393 drm_gem_object_unreference(obj);
1398 * i915_gem_fault - fault a page into the GTT
1399 * vma: VMA in question
1402 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1403 * from userspace. The fault handler takes care of binding the object to
1404 * the GTT (if needed), allocating and programming a fence register (again,
1405 * only if needed based on whether the old reg is still valid or the object
1406 * is tiled) and inserting a new PTE into the faulting process.
1408 * Note that the faulting process may involve evicting existing objects
1409 * from the GTT and/or fence registers to make room. So performance may
1410 * suffer if the GTT working set is large or there are few fence registers
1413 int i915_gem_fault(vm_object_t vm_obj, vm_ooffset_t offset, int prot, vm_page_t *mres)
1415 struct drm_i915_gem_object *obj = to_intel_bo(vm_obj->handle);
1416 struct drm_device *dev = obj->base.dev;
1417 drm_i915_private_t *dev_priv = dev->dev_private;
1418 unsigned long page_offset;
1419 vm_page_t m, oldm = NULL;
1421 bool write = !!(prot & VM_PROT_WRITE);
1423 intel_runtime_pm_get(dev_priv);
1425 /* We don't use vmf->pgoff since that has the fake offset */
1426 page_offset = (unsigned long)offset;
1428 /* Magic FreeBSD VM stuff */
1429 vm_object_pip_add(vm_obj, 1);
1432 * Remove the placeholder page inserted by vm_fault() from the
1433 * object before dropping the object lock. If
1434 * i915_gem_release_mmap() is active in parallel on this gem
1435 * object, then it owns the drm device sx and might find the
1436 * placeholder already. Then, since the page is busy,
1437 * i915_gem_release_mmap() sleeps waiting for the busy state
1438 * of the page cleared. We will be not able to acquire drm
1439 * device lock until i915_gem_release_mmap() is able to make a
1442 if (*mres != NULL) {
1444 vm_page_remove(oldm);
1449 VM_OBJECT_UNLOCK(vm_obj);
1454 mutex_lock(&dev->struct_mutex);
1457 * Since the object lock was dropped, other thread might have
1458 * faulted on the same GTT address and instantiated the
1459 * mapping for the page. Recheck.
1461 VM_OBJECT_LOCK(vm_obj);
1462 m = vm_page_lookup(vm_obj, OFF_TO_IDX(offset));
1464 if ((m->flags & PG_BUSY) != 0) {
1465 mutex_unlock(&dev->struct_mutex);
1470 VM_OBJECT_UNLOCK(vm_obj);
1471 /* End magic VM stuff */
1473 trace_i915_gem_object_fault(obj, page_offset, true, write);
1475 /* Access to snoopable pages through the GTT is incoherent. */
1476 if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1481 /* Now bind it into the GTT if needed */
1482 ret = i915_gem_obj_ggtt_pin(obj, 0, true, false);
1486 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1490 ret = i915_gem_object_get_fence(obj);
1494 obj->fault_mappable = true;
1496 VM_OBJECT_LOCK(vm_obj);
1497 m = vm_phys_fictitious_to_vm_page(dev->agp->base +
1498 i915_gem_obj_ggtt_offset(obj) + offset);
1503 KASSERT((m->flags & PG_FICTITIOUS) != 0,
1504 ("not fictitious %p", m));
1505 KASSERT(m->wire_count == 1, ("wire_count not 1 %p", m));
1507 if ((m->flags & PG_BUSY) != 0) {
1508 i915_gem_object_unpin(obj);
1509 mutex_unlock(&dev->struct_mutex);
1512 m->valid = VM_PAGE_BITS_ALL;
1514 /* Finally, remap it using the new GTT offset */
1515 vm_page_insert(m, vm_obj, OFF_TO_IDX(offset));
1518 vm_page_busy_try(m, false);
1520 i915_gem_object_unpin(obj);
1521 mutex_unlock(&dev->struct_mutex);
1525 vm_object_pip_wakeup(vm_obj);
1526 return (VM_PAGER_OK);
1529 i915_gem_object_unpin(obj);
1531 mutex_unlock(&dev->struct_mutex);
1533 KASSERT(ret != 0, ("i915_gem_pager_fault: wrong return"));
1538 goto unlocked_vmobj;
1540 VM_OBJECT_LOCK(vm_obj);
1541 vm_object_pip_wakeup(vm_obj);
1542 ret = VM_PAGER_ERROR;
1545 intel_runtime_pm_put(dev_priv);
1549 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1551 struct i915_vma *vma;
1554 * Only the global gtt is relevant for gtt memory mappings, so restrict
1555 * list traversal to objects bound into the global address space. Note
1556 * that the active list should be empty, but better safe than sorry.
1558 WARN_ON(!list_empty(&dev_priv->gtt.base.active_list));
1559 list_for_each_entry(vma, &dev_priv->gtt.base.active_list, mm_list)
1560 i915_gem_release_mmap(vma->obj);
1561 list_for_each_entry(vma, &dev_priv->gtt.base.inactive_list, mm_list)
1562 i915_gem_release_mmap(vma->obj);
1566 * i915_gem_release_mmap - remove physical page mappings
1567 * @obj: obj in question
1569 * Preserve the reservation of the mmapping with the DRM core code, but
1570 * relinquish ownership of the pages back to the system.
1572 * It is vital that we remove the page mapping if we have mapped a tiled
1573 * object through the GTT and then lose the fence register due to
1574 * resource pressure. Similarly if the object has been moved out of the
1575 * aperture, than pages mapped into userspace must be revoked. Removing the
1576 * mapping will then trigger a page fault on the next user access, allowing
1577 * fixup by i915_gem_fault().
1580 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1586 if (!obj->fault_mappable)
1589 devobj = cdev_pager_lookup(obj);
1590 if (devobj != NULL) {
1591 page_count = OFF_TO_IDX(obj->base.size);
1593 VM_OBJECT_LOCK(devobj);
1594 for (i = 0; i < page_count; i++) {
1595 m = vm_page_lookup_busy_wait(devobj, i, TRUE, "915unm");
1598 cdev_pager_free_page(devobj, m);
1600 VM_OBJECT_UNLOCK(devobj);
1601 vm_object_deallocate(devobj);
1604 obj->fault_mappable = false;
1608 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1612 if (INTEL_INFO(dev)->gen >= 4 ||
1613 tiling_mode == I915_TILING_NONE)
1616 /* Previous chips need a power-of-two fence region when tiling */
1617 if (INTEL_INFO(dev)->gen == 3)
1618 gtt_size = 1024*1024;
1620 gtt_size = 512*1024;
1622 while (gtt_size < size)
1629 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1630 * @obj: object to check
1632 * Return the required GTT alignment for an object, taking into account
1633 * potential fence register mapping.
1636 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1637 int tiling_mode, bool fenced)
1640 * Minimum alignment is 4k (GTT page size), but might be greater
1641 * if a fence register is needed for the object.
1643 if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1644 tiling_mode == I915_TILING_NONE)
1648 * Previous chips need to be aligned to the size of the smallest
1649 * fence register that can contain the object.
1651 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1654 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1656 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1660 if (drm_vma_node_has_offset(&obj->base.vma_node))
1664 dev_priv->mm.shrinker_no_lock_stealing = true;
1666 ret = drm_gem_create_mmap_offset(&obj->base);
1670 /* Badly fragmented mmap space? The only way we can recover
1671 * space is by destroying unwanted objects. We can't randomly release
1672 * mmap_offsets as userspace expects them to be persistent for the
1673 * lifetime of the objects. The closest we can is to release the
1674 * offsets on purgeable objects by truncating it and marking it purged,
1675 * which prevents userspace from ever using that object again.
1677 i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1678 ret = drm_gem_create_mmap_offset(&obj->base);
1682 i915_gem_shrink_all(dev_priv);
1683 ret = drm_gem_create_mmap_offset(&obj->base);
1685 dev_priv->mm.shrinker_no_lock_stealing = false;
1690 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1692 drm_gem_free_mmap_offset(&obj->base);
1696 i915_gem_mmap_gtt(struct drm_file *file,
1697 struct drm_device *dev,
1701 struct drm_i915_private *dev_priv = dev->dev_private;
1702 struct drm_i915_gem_object *obj;
1705 ret = i915_mutex_lock_interruptible(dev);
1709 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1710 if (&obj->base == NULL) {
1715 if (obj->base.size > dev_priv->gtt.mappable_end) {
1720 if (obj->madv != I915_MADV_WILLNEED) {
1721 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1726 ret = i915_gem_object_create_mmap_offset(obj);
1730 *offset = DRM_GEM_MAPPING_OFF(obj->base.map_list.key) |
1731 DRM_GEM_MAPPING_KEY;
1734 drm_gem_object_unreference(&obj->base);
1736 mutex_unlock(&dev->struct_mutex);
1741 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1743 * @data: GTT mapping ioctl data
1744 * @file: GEM object info
1746 * Simply returns the fake offset to userspace so it can mmap it.
1747 * The mmap call will end up in drm_gem_mmap(), which will set things
1748 * up so we can get faults in the handler above.
1750 * The fault handler will take care of binding the object into the GTT
1751 * (since it may have been evicted to make room for something), allocating
1752 * a fence register, and mapping the appropriate aperture address into
1756 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1757 struct drm_file *file)
1759 struct drm_i915_gem_mmap_gtt *args = data;
1761 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1764 /* Immediately discard the backing storage */
1766 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1770 vm_obj = obj->base.vm_obj;
1771 VM_OBJECT_LOCK(vm_obj);
1772 vm_object_page_remove(vm_obj, 0, 0, false);
1773 VM_OBJECT_UNLOCK(vm_obj);
1775 obj->madv = __I915_MADV_PURGED;
1779 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1781 return obj->madv == I915_MADV_DONTNEED;
1785 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1787 int page_count = obj->base.size / PAGE_SIZE;
1793 BUG_ON(obj->madv == __I915_MADV_PURGED);
1795 ret = i915_gem_object_set_to_cpu_domain(obj, true);
1797 /* In the event of a disaster, abandon all caches and
1798 * hope for the best.
1800 WARN_ON(ret != -EIO);
1801 i915_gem_clflush_object(obj, true);
1802 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1805 if (i915_gem_object_needs_bit17_swizzle(obj))
1806 i915_gem_object_save_bit_17_swizzle(obj);
1808 if (obj->madv == I915_MADV_DONTNEED)
1811 for (i = 0; i < page_count; i++) {
1812 struct vm_page *page = obj->pages[i];
1815 set_page_dirty(page);
1817 if (obj->madv == I915_MADV_WILLNEED)
1818 mark_page_accessed(page);
1820 vm_page_busy_wait(obj->pages[i], FALSE, "i915gem");
1821 vm_page_unwire(obj->pages[i], 1);
1822 vm_page_wakeup(obj->pages[i]);
1831 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1833 const struct drm_i915_gem_object_ops *ops = obj->ops;
1835 if (obj->pages == NULL)
1838 if (obj->pages_pin_count)
1841 BUG_ON(i915_gem_obj_bound_any(obj));
1843 /* ->put_pages might need to allocate memory for the bit17 swizzle
1844 * array, hence protect them from being reaped by removing them from gtt
1846 list_del(&obj->global_list);
1848 ops->put_pages(obj);
1851 if (i915_gem_object_is_purgeable(obj))
1852 i915_gem_object_truncate(obj);
1857 static unsigned long
1858 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1859 bool purgeable_only)
1861 struct drm_i915_gem_object *obj, *next;
1862 unsigned long count = 0;
1864 list_for_each_entry_safe(obj, next,
1865 &dev_priv->mm.unbound_list,
1867 if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) &&
1868 i915_gem_object_put_pages(obj) == 0) {
1869 count += obj->base.size >> PAGE_SHIFT;
1870 if (count >= target)
1875 list_for_each_entry_safe(obj, next, &dev_priv->mm.bound_list,
1877 struct i915_vma *vma, *v;
1879 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1882 list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link)
1883 if (i915_vma_unbind(vma))
1886 if (!i915_gem_object_put_pages(obj)) {
1887 count += obj->base.size >> PAGE_SHIFT;
1888 if (count >= target)
1896 static unsigned long
1897 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
1899 return __i915_gem_shrink(dev_priv, target, true);
1902 static unsigned long
1903 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
1905 struct drm_i915_gem_object *obj, *next;
1908 i915_gem_evict_everything(dev_priv->dev);
1910 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
1912 if (i915_gem_object_put_pages(obj) == 0)
1913 freed += obj->base.size >> PAGE_SHIFT;
1919 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
1921 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1922 int page_count, i, j;
1924 struct vm_page *page;
1926 /* Assert that the object is not currently in any GPU domain. As it
1927 * wasn't in the GTT, there shouldn't be any way it could have been in
1930 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
1931 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
1933 page_count = obj->base.size / PAGE_SIZE;
1934 obj->pages = kmalloc(page_count * sizeof(vm_page_t), M_DRM,
1937 /* Get the list of pages out of our struct file. They'll be pinned
1938 * at this point until we release them.
1940 * Fail silently without starting the shrinker
1942 vm_obj = obj->base.vm_obj;
1943 VM_OBJECT_LOCK(vm_obj);
1944 for (i = 0; i < page_count; i++) {
1945 page = shmem_read_mapping_page(vm_obj, i);
1947 i915_gem_purge(dev_priv, page_count);
1948 page = shmem_read_mapping_page(vm_obj, i);
1951 /* We've tried hard to allocate the memory by reaping
1952 * our own buffer, now let the real VM do its job and
1953 * go down in flames if truly OOM.
1956 i915_gem_shrink_all(dev_priv);
1957 page = shmem_read_mapping_page(vm_obj, i);
1961 #ifdef CONFIG_SWIOTLB
1962 if (swiotlb_nr_tbl()) {
1964 sg_set_page(sg, page, PAGE_SIZE, 0);
1969 obj->pages[i] = page;
1971 #ifdef CONFIG_SWIOTLB
1972 if (!swiotlb_nr_tbl())
1974 VM_OBJECT_UNLOCK(vm_obj);
1976 if (i915_gem_object_needs_bit17_swizzle(obj))
1977 i915_gem_object_do_bit_17_swizzle(obj);
1982 for (j = 0; j < i; j++) {
1983 page = obj->pages[j];
1984 vm_page_busy_wait(page, FALSE, "i915gem");
1985 vm_page_unwire(page, 0);
1986 vm_page_wakeup(page);
1988 VM_OBJECT_UNLOCK(vm_obj);
1994 /* Ensure that the associated pages are gathered from the backing storage
1995 * and pinned into our object. i915_gem_object_get_pages() may be called
1996 * multiple times before they are released by a single call to
1997 * i915_gem_object_put_pages() - once the pages are no longer referenced
1998 * either as a result of memory pressure (reaping pages under the shrinker)
1999 * or as the object is itself released.
2002 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2004 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2005 const struct drm_i915_gem_object_ops *ops = obj->ops;
2011 if (obj->madv != I915_MADV_WILLNEED) {
2012 DRM_ERROR("Attempting to obtain a purgeable object\n");
2016 BUG_ON(obj->pages_pin_count);
2018 ret = ops->get_pages(obj);
2022 list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2027 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2028 struct intel_ring_buffer *ring)
2030 struct drm_device *dev = obj->base.dev;
2031 struct drm_i915_private *dev_priv = dev->dev_private;
2032 u32 seqno = intel_ring_get_seqno(ring);
2034 BUG_ON(ring == NULL);
2035 if (obj->ring != ring && obj->last_write_seqno) {
2036 /* Keep the seqno relative to the current ring */
2037 obj->last_write_seqno = seqno;
2041 /* Add a reference if we're newly entering the active list. */
2043 drm_gem_object_reference(&obj->base);
2047 list_move_tail(&obj->ring_list, &ring->active_list);
2049 obj->last_read_seqno = seqno;
2051 if (obj->fenced_gpu_access) {
2052 obj->last_fenced_seqno = seqno;
2054 /* Bump MRU to take account of the delayed flush */
2055 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2056 struct drm_i915_fence_reg *reg;
2058 reg = &dev_priv->fence_regs[obj->fence_reg];
2059 list_move_tail(®->lru_list,
2060 &dev_priv->mm.fence_list);
2065 void i915_vma_move_to_active(struct i915_vma *vma,
2066 struct intel_ring_buffer *ring)
2068 list_move_tail(&vma->mm_list, &vma->vm->active_list);
2069 return i915_gem_object_move_to_active(vma->obj, ring);
2073 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2075 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2076 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
2077 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
2079 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2080 BUG_ON(!obj->active);
2082 list_move_tail(&vma->mm_list, &ggtt_vm->inactive_list);
2084 list_del_init(&obj->ring_list);
2087 obj->last_read_seqno = 0;
2088 obj->last_write_seqno = 0;
2089 obj->base.write_domain = 0;
2091 obj->last_fenced_seqno = 0;
2092 obj->fenced_gpu_access = false;
2095 drm_gem_object_unreference(&obj->base);
2097 WARN_ON(i915_verify_lists(dev));
2101 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2103 struct drm_i915_private *dev_priv = dev->dev_private;
2104 struct intel_ring_buffer *ring;
2107 /* Carefully retire all requests without writing to the rings */
2108 for_each_ring(ring, dev_priv, i) {
2109 ret = intel_ring_idle(ring);
2113 i915_gem_retire_requests(dev);
2115 /* Finally reset hw state */
2116 for_each_ring(ring, dev_priv, i) {
2117 intel_ring_init_seqno(ring, seqno);
2119 for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++)
2120 ring->sync_seqno[j] = 0;
2126 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2128 struct drm_i915_private *dev_priv = dev->dev_private;
2134 /* HWS page needs to be set less than what we
2135 * will inject to ring
2137 ret = i915_gem_init_seqno(dev, seqno - 1);
2141 /* Carefully set the last_seqno value so that wrap
2142 * detection still works
2144 dev_priv->next_seqno = seqno;
2145 dev_priv->last_seqno = seqno - 1;
2146 if (dev_priv->last_seqno == 0)
2147 dev_priv->last_seqno--;
2153 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2155 struct drm_i915_private *dev_priv = dev->dev_private;
2157 /* reserve 0 for non-seqno */
2158 if (dev_priv->next_seqno == 0) {
2159 int ret = i915_gem_init_seqno(dev, 0);
2163 dev_priv->next_seqno = 1;
2166 *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2170 int __i915_add_request(struct intel_ring_buffer *ring,
2171 struct drm_file *file,
2172 struct drm_i915_gem_object *obj,
2175 drm_i915_private_t *dev_priv = ring->dev->dev_private;
2176 struct drm_i915_gem_request *request;
2177 u32 request_ring_position, request_start;
2181 request_start = intel_ring_get_tail(ring);
2183 * Emit any outstanding flushes - execbuf can fail to emit the flush
2184 * after having emitted the batchbuffer command. Hence we need to fix
2185 * things up similar to emitting the lazy request. The difference here
2186 * is that the flush _must_ happen before the next request, no matter
2189 ret = intel_ring_flush_all_caches(ring);
2193 request = ring->preallocated_lazy_request;
2194 if (WARN_ON(request == NULL))
2197 /* Record the position of the start of the request so that
2198 * should we detect the updated seqno part-way through the
2199 * GPU processing the request, we never over-estimate the
2200 * position of the head.
2202 request_ring_position = intel_ring_get_tail(ring);
2204 ret = ring->add_request(ring);
2208 request->seqno = intel_ring_get_seqno(ring);
2209 request->ring = ring;
2210 request->head = request_start;
2211 request->tail = request_ring_position;
2213 /* Whilst this request exists, batch_obj will be on the
2214 * active_list, and so will hold the active reference. Only when this
2215 * request is retired will the the batch_obj be moved onto the
2216 * inactive_list and lose its active reference. Hence we do not need
2217 * to explicitly hold another reference here.
2219 request->batch_obj = obj;
2221 /* Hold a reference to the current context so that we can inspect
2222 * it later in case a hangcheck error event fires.
2224 request->ctx = ring->last_context;
2226 i915_gem_context_reference(request->ctx);
2228 request->emitted_jiffies = jiffies;
2229 was_empty = list_empty(&ring->request_list);
2230 list_add_tail(&request->list, &ring->request_list);
2231 request->file_priv = NULL;
2234 struct drm_i915_file_private *file_priv = file->driver_priv;
2236 spin_lock(&file_priv->mm.lock);
2237 request->file_priv = file_priv;
2238 list_add_tail(&request->client_list,
2239 &file_priv->mm.request_list);
2240 spin_unlock(&file_priv->mm.lock);
2243 trace_i915_gem_request_add(ring, request->seqno);
2244 ring->outstanding_lazy_seqno = 0;
2245 ring->preallocated_lazy_request = NULL;
2247 if (!dev_priv->ums.mm_suspended) {
2248 i915_queue_hangcheck(ring->dev);
2251 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
2252 queue_delayed_work(dev_priv->wq,
2253 &dev_priv->mm.retire_work,
2254 round_jiffies_up_relative(HZ));
2255 intel_mark_busy(dev_priv->dev);
2260 *out_seqno = request->seqno;
2265 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2267 struct drm_i915_file_private *file_priv = request->file_priv;
2272 spin_lock(&file_priv->mm.lock);
2273 if (request->file_priv) {
2274 list_del(&request->client_list);
2275 request->file_priv = NULL;
2277 spin_unlock(&file_priv->mm.lock);
2280 static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj,
2281 struct i915_address_space *vm)
2283 if (acthd >= i915_gem_obj_offset(obj, vm) &&
2284 acthd < i915_gem_obj_offset(obj, vm) + obj->base.size)
2290 static bool i915_head_inside_request(const u32 acthd_unmasked,
2291 const u32 request_start,
2292 const u32 request_end)
2294 const u32 acthd = acthd_unmasked & HEAD_ADDR;
2296 if (request_start < request_end) {
2297 if (acthd >= request_start && acthd < request_end)
2299 } else if (request_start > request_end) {
2300 if (acthd >= request_start || acthd < request_end)
2307 static struct i915_address_space *
2308 request_to_vm(struct drm_i915_gem_request *request)
2310 struct drm_i915_private *dev_priv = request->ring->dev->dev_private;
2311 struct i915_address_space *vm;
2313 vm = &dev_priv->gtt.base;
2318 static bool i915_request_guilty(struct drm_i915_gem_request *request,
2319 const u32 acthd, bool *inside)
2321 /* There is a possibility that unmasked head address
2322 * pointing inside the ring, matches the batch_obj address range.
2323 * However this is extremely unlikely.
2325 if (request->batch_obj) {
2326 if (i915_head_inside_object(acthd, request->batch_obj,
2327 request_to_vm(request))) {
2333 if (i915_head_inside_request(acthd, request->head, request->tail)) {
2341 static bool i915_context_is_banned(const struct i915_ctx_hang_stats *hs)
2343 const unsigned long elapsed = get_seconds() - hs->guilty_ts;
2348 if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
2349 DRM_ERROR("context hanging too fast, declaring banned!\n");
2356 static void i915_set_reset_status(struct intel_ring_buffer *ring,
2357 struct drm_i915_gem_request *request,
2360 struct i915_ctx_hang_stats *hs = NULL;
2361 bool inside, guilty;
2362 unsigned long offset = 0;
2364 /* Innocent until proven guilty */
2367 if (request->batch_obj)
2368 offset = i915_gem_obj_offset(request->batch_obj,
2369 request_to_vm(request));
2371 if (ring->hangcheck.action != HANGCHECK_WAIT &&
2372 i915_request_guilty(request, acthd, &inside)) {
2373 DRM_DEBUG("%s hung %s bo (0x%lx ctx %d) at 0x%x\n",
2375 inside ? "inside" : "flushing",
2377 request->ctx ? request->ctx->id : 0,
2383 /* If contexts are disabled or this is the default context, use
2384 * file_priv->reset_state
2386 if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID)
2387 hs = &request->ctx->hang_stats;
2388 else if (request->file_priv)
2389 hs = &request->file_priv->hang_stats;
2393 hs->banned = i915_context_is_banned(hs);
2395 hs->guilty_ts = get_seconds();
2397 hs->batch_pending++;
2402 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2404 list_del(&request->list);
2405 i915_gem_request_remove_from_client(request);
2408 i915_gem_context_unreference(request->ctx);
2413 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2414 struct intel_ring_buffer *ring)
2416 u32 completed_seqno = ring->get_seqno(ring, false);
2417 u32 acthd = intel_ring_get_active_head(ring);
2418 struct drm_i915_gem_request *request;
2420 list_for_each_entry(request, &ring->request_list, list) {
2421 if (i915_seqno_passed(completed_seqno, request->seqno))
2424 i915_set_reset_status(ring, request, acthd);
2428 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2429 struct intel_ring_buffer *ring)
2431 while (!list_empty(&ring->active_list)) {
2432 struct drm_i915_gem_object *obj;
2434 obj = list_first_entry(&ring->active_list,
2435 struct drm_i915_gem_object,
2438 i915_gem_object_move_to_inactive(obj);
2442 * We must free the requests after all the corresponding objects have
2443 * been moved off active lists. Which is the same order as the normal
2444 * retire_requests function does. This is important if object hold
2445 * implicit references on things like e.g. ppgtt address spaces through
2448 while (!list_empty(&ring->request_list)) {
2449 struct drm_i915_gem_request *request;
2451 request = list_first_entry(&ring->request_list,
2452 struct drm_i915_gem_request,
2455 i915_gem_free_request(request);
2459 void i915_gem_restore_fences(struct drm_device *dev)
2461 struct drm_i915_private *dev_priv = dev->dev_private;
2464 for (i = 0; i < dev_priv->num_fence_regs; i++) {
2465 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2468 * Commit delayed tiling changes if we have an object still
2469 * attached to the fence, otherwise just clear the fence.
2472 i915_gem_object_update_fence(reg->obj, reg,
2473 reg->obj->tiling_mode);
2475 i915_gem_write_fence(dev, i, NULL);
2480 void i915_gem_reset(struct drm_device *dev)
2482 struct drm_i915_private *dev_priv = dev->dev_private;
2483 struct intel_ring_buffer *ring;
2487 * Before we free the objects from the requests, we need to inspect
2488 * them for finding the guilty party. As the requests only borrow
2489 * their reference to the objects, the inspection must be done first.
2491 for_each_ring(ring, dev_priv, i)
2492 i915_gem_reset_ring_status(dev_priv, ring);
2494 for_each_ring(ring, dev_priv, i)
2495 i915_gem_reset_ring_cleanup(dev_priv, ring);
2497 i915_gem_cleanup_ringbuffer(dev);
2499 i915_gem_restore_fences(dev);
2503 * This function clears the request list as sequence numbers are passed.
2506 i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
2510 if (list_empty(&ring->request_list))
2513 WARN_ON(i915_verify_lists(ring->dev));
2515 seqno = ring->get_seqno(ring, true);
2517 while (!list_empty(&ring->request_list)) {
2518 struct drm_i915_gem_request *request;
2520 request = list_first_entry(&ring->request_list,
2521 struct drm_i915_gem_request,
2524 if (!i915_seqno_passed(seqno, request->seqno))
2527 trace_i915_gem_request_retire(ring, request->seqno);
2528 /* We know the GPU must have read the request to have
2529 * sent us the seqno + interrupt, so use the position
2530 * of tail of the request to update the last known position
2533 ring->last_retired_head = request->tail;
2535 i915_gem_free_request(request);
2538 /* Move any buffers on the active list that are no longer referenced
2539 * by the ringbuffer to the flushing/inactive lists as appropriate.
2541 while (!list_empty(&ring->active_list)) {
2542 struct drm_i915_gem_object *obj;
2544 obj = list_first_entry(&ring->active_list,
2545 struct drm_i915_gem_object,
2548 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2551 i915_gem_object_move_to_inactive(obj);
2554 if (unlikely(ring->trace_irq_seqno &&
2555 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2556 ring->irq_put(ring);
2557 ring->trace_irq_seqno = 0;
2560 WARN_ON(i915_verify_lists(ring->dev));
2564 i915_gem_retire_requests(struct drm_device *dev)
2566 drm_i915_private_t *dev_priv = dev->dev_private;
2567 struct intel_ring_buffer *ring;
2571 for_each_ring(ring, dev_priv, i) {
2572 i915_gem_retire_requests_ring(ring);
2573 idle &= list_empty(&ring->request_list);
2580 i915_gem_retire_work_handler(struct work_struct *work)
2582 drm_i915_private_t *dev_priv;
2583 struct drm_device *dev;
2584 struct intel_ring_buffer *ring;
2588 dev_priv = container_of(work, drm_i915_private_t,
2589 mm.retire_work.work);
2590 dev = dev_priv->dev;
2592 /* Come back later if the device is busy... */
2593 if (lockmgr(&dev->struct_mutex, LK_EXCLUSIVE|LK_NOWAIT)) {
2594 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2595 round_jiffies_up_relative(HZ));
2599 i915_gem_retire_requests(dev);
2601 /* Send a periodic flush down the ring so we don't hold onto GEM
2602 * objects indefinitely.
2605 for_each_ring(ring, dev_priv, i) {
2606 if (ring->gpu_caches_dirty)
2607 i915_add_request(ring, NULL);
2609 idle &= list_empty(&ring->request_list);
2612 if (!dev_priv->ums.mm_suspended && !idle)
2613 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2614 round_jiffies_up_relative(HZ));
2616 intel_mark_idle(dev);
2618 mutex_unlock(&dev->struct_mutex);
2622 i915_gem_idle_work_handler(struct work_struct *work)
2624 struct drm_i915_private *dev_priv =
2625 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2627 intel_mark_idle(dev_priv->dev);
2631 * Ensures that an object will eventually get non-busy by flushing any required
2632 * write domains, emitting any outstanding lazy request and retiring and
2633 * completed requests.
2636 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2641 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2645 i915_gem_retire_requests_ring(obj->ring);
2652 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2653 * @DRM_IOCTL_ARGS: standard ioctl arguments
2655 * Returns 0 if successful, else an error is returned with the remaining time in
2656 * the timeout parameter.
2657 * -ETIME: object is still busy after timeout
2658 * -ERESTARTSYS: signal interrupted the wait
2659 * -ENONENT: object doesn't exist
2660 * Also possible, but rare:
2661 * -EAGAIN: GPU wedged
2663 * -ENODEV: Internal IRQ fail
2664 * -E?: The add request failed
2666 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2667 * non-zero timeout parameter the wait ioctl will wait for the given number of
2668 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2669 * without holding struct_mutex the object may become re-busied before this
2670 * function completes. A similar but shorter * race condition exists in the busy
2674 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2676 drm_i915_private_t *dev_priv = dev->dev_private;
2677 struct drm_i915_gem_wait *args = data;
2678 struct drm_i915_gem_object *obj;
2679 struct intel_ring_buffer *ring = NULL;
2680 struct timespec timeout_stack, *timeout = NULL;
2681 unsigned reset_counter;
2685 if (args->timeout_ns >= 0) {
2686 timeout_stack = ns_to_timespec(args->timeout_ns);
2687 timeout = &timeout_stack;
2690 ret = i915_mutex_lock_interruptible(dev);
2694 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2695 if (&obj->base == NULL) {
2696 mutex_unlock(&dev->struct_mutex);
2700 /* Need to make sure the object gets inactive eventually. */
2701 ret = i915_gem_object_flush_active(obj);
2706 seqno = obj->last_read_seqno;
2713 /* Do this after OLR check to make sure we make forward progress polling
2714 * on this IOCTL with a 0 timeout (like busy ioctl)
2716 if (!args->timeout_ns) {
2721 drm_gem_object_unreference(&obj->base);
2722 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2723 mutex_unlock(&dev->struct_mutex);
2725 ret = __wait_seqno(ring, seqno, reset_counter, true, timeout);
2727 args->timeout_ns = timespec_to_ns(timeout);
2731 drm_gem_object_unreference(&obj->base);
2732 mutex_unlock(&dev->struct_mutex);
2737 * i915_gem_object_sync - sync an object to a ring.
2739 * @obj: object which may be in use on another ring.
2740 * @to: ring we wish to use the object on. May be NULL.
2742 * This code is meant to abstract object synchronization with the GPU.
2743 * Calling with NULL implies synchronizing the object with the CPU
2744 * rather than a particular GPU ring.
2746 * Returns 0 if successful, else propagates up the lower layer error.
2749 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2750 struct intel_ring_buffer *to)
2752 struct intel_ring_buffer *from = obj->ring;
2756 if (from == NULL || to == from)
2759 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2760 return i915_gem_object_wait_rendering(obj, false);
2762 idx = intel_ring_sync_index(from, to);
2764 seqno = obj->last_read_seqno;
2765 if (seqno <= from->sync_seqno[idx])
2768 ret = i915_gem_check_olr(obj->ring, seqno);
2772 trace_i915_gem_ring_sync_to(from, to, seqno);
2773 ret = to->sync_to(to, from, seqno);
2775 /* We use last_read_seqno because sync_to()
2776 * might have just caused seqno wrap under
2779 from->sync_seqno[idx] = obj->last_read_seqno;
2784 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2786 u32 old_write_domain, old_read_domains;
2788 /* Force a pagefault for domain tracking on next user access */
2789 i915_gem_release_mmap(obj);
2791 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2794 /* Wait for any direct GTT access to complete */
2797 old_read_domains = obj->base.read_domains;
2798 old_write_domain = obj->base.write_domain;
2800 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2801 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2803 trace_i915_gem_object_change_domain(obj,
2808 int i915_vma_unbind(struct i915_vma *vma)
2810 struct drm_i915_gem_object *obj = vma->obj;
2811 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2814 /* For now we only ever use 1 vma per object */
2816 WARN_ON(!list_is_singular(&obj->vma_list));
2819 if (list_empty(&vma->vma_link))
2822 if (!drm_mm_node_allocated(&vma->node)) {
2823 i915_gem_vma_destroy(vma);
2831 BUG_ON(obj->pages == NULL);
2833 ret = i915_gem_object_finish_gpu(obj);
2836 /* Continue on if we fail due to EIO, the GPU is hung so we
2837 * should be safe and we need to cleanup or else we might
2838 * cause memory corruption through use-after-free.
2841 i915_gem_object_finish_gtt(obj);
2843 /* release the fence reg _after_ flushing */
2844 ret = i915_gem_object_put_fence(obj);
2848 trace_i915_vma_unbind(vma);
2850 if (obj->has_global_gtt_mapping)
2851 i915_gem_gtt_unbind_object(obj);
2852 if (obj->has_aliasing_ppgtt_mapping) {
2853 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2854 obj->has_aliasing_ppgtt_mapping = 0;
2856 i915_gem_gtt_finish_object(obj);
2858 list_del(&vma->mm_list);
2859 /* Avoid an unnecessary call to unbind on rebind. */
2860 if (i915_is_ggtt(vma->vm))
2861 obj->map_and_fenceable = true;
2863 drm_mm_remove_node(&vma->node);
2864 i915_gem_vma_destroy(vma);
2866 /* Since the unbound list is global, only move to that list if
2867 * no more VMAs exist. */
2868 if (list_empty(&obj->vma_list))
2869 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2871 /* And finally now the object is completely decoupled from this vma,
2872 * we can drop its hold on the backing storage and allow it to be
2873 * reaped by the shrinker.
2875 i915_gem_object_unpin_pages(obj);
2881 * Unbinds an object from the global GTT aperture.
2884 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2886 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2887 struct i915_address_space *ggtt = &dev_priv->gtt.base;
2889 if (!i915_gem_obj_ggtt_bound(obj))
2895 BUG_ON(obj->pages == NULL);
2897 return i915_vma_unbind(i915_gem_obj_to_vma(obj, ggtt));
2900 int i915_gpu_idle(struct drm_device *dev)
2902 drm_i915_private_t *dev_priv = dev->dev_private;
2903 struct intel_ring_buffer *ring;
2906 /* Flush everything onto the inactive list. */
2907 for_each_ring(ring, dev_priv, i) {
2908 ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
2912 ret = intel_ring_idle(ring);
2920 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2921 struct drm_i915_gem_object *obj)
2923 drm_i915_private_t *dev_priv = dev->dev_private;
2925 int fence_pitch_shift;
2927 if (INTEL_INFO(dev)->gen >= 6) {
2928 fence_reg = FENCE_REG_SANDYBRIDGE_0;
2929 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
2931 fence_reg = FENCE_REG_965_0;
2932 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
2935 fence_reg += reg * 8;
2937 /* To w/a incoherency with non-atomic 64-bit register updates,
2938 * we split the 64-bit update into two 32-bit writes. In order
2939 * for a partial fence not to be evaluated between writes, we
2940 * precede the update with write to turn off the fence register,
2941 * and only enable the fence as the last step.
2943 * For extra levels of paranoia, we make sure each step lands
2944 * before applying the next step.
2946 I915_WRITE(fence_reg, 0);
2947 POSTING_READ(fence_reg);
2950 u32 size = i915_gem_obj_ggtt_size(obj);
2953 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
2955 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
2956 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
2957 if (obj->tiling_mode == I915_TILING_Y)
2958 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2959 val |= I965_FENCE_REG_VALID;
2961 I915_WRITE(fence_reg + 4, val >> 32);
2962 POSTING_READ(fence_reg + 4);
2964 I915_WRITE(fence_reg + 0, val);
2965 POSTING_READ(fence_reg);
2967 I915_WRITE(fence_reg + 4, 0);
2968 POSTING_READ(fence_reg + 4);
2972 static void i915_write_fence_reg(struct drm_device *dev, int reg,
2973 struct drm_i915_gem_object *obj)
2975 drm_i915_private_t *dev_priv = dev->dev_private;
2979 u32 size = i915_gem_obj_ggtt_size(obj);
2983 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
2984 (size & -size) != size ||
2985 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
2986 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2987 i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
2989 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2994 /* Note: pitch better be a power of two tile widths */
2995 pitch_val = obj->stride / tile_width;
2996 pitch_val = ffs(pitch_val) - 1;
2998 val = i915_gem_obj_ggtt_offset(obj);
2999 if (obj->tiling_mode == I915_TILING_Y)
3000 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3001 val |= I915_FENCE_SIZE_BITS(size);
3002 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3003 val |= I830_FENCE_REG_VALID;
3008 reg = FENCE_REG_830_0 + reg * 4;
3010 reg = FENCE_REG_945_8 + (reg - 8) * 4;
3012 I915_WRITE(reg, val);
3016 static void i830_write_fence_reg(struct drm_device *dev, int reg,
3017 struct drm_i915_gem_object *obj)
3019 drm_i915_private_t *dev_priv = dev->dev_private;
3023 u32 size = i915_gem_obj_ggtt_size(obj);
3026 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
3027 (size & -size) != size ||
3028 (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3029 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3030 i915_gem_obj_ggtt_offset(obj), size);
3032 pitch_val = obj->stride / 128;
3033 pitch_val = ffs(pitch_val) - 1;
3035 val = i915_gem_obj_ggtt_offset(obj);
3036 if (obj->tiling_mode == I915_TILING_Y)
3037 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3038 val |= I830_FENCE_SIZE_BITS(size);
3039 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3040 val |= I830_FENCE_REG_VALID;
3044 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3045 POSTING_READ(FENCE_REG_830_0 + reg * 4);
3048 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
3050 return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
3053 static void i915_gem_write_fence(struct drm_device *dev, int reg,
3054 struct drm_i915_gem_object *obj)
3056 struct drm_i915_private *dev_priv = dev->dev_private;
3058 /* Ensure that all CPU reads are completed before installing a fence
3059 * and all writes before removing the fence.
3061 if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3064 WARN(obj && (!obj->stride || !obj->tiling_mode),
3065 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3066 obj->stride, obj->tiling_mode);
3068 switch (INTEL_INFO(dev)->gen) {
3073 case 4: i965_write_fence_reg(dev, reg, obj); break;
3074 case 3: i915_write_fence_reg(dev, reg, obj); break;
3075 case 2: i830_write_fence_reg(dev, reg, obj); break;
3079 /* And similarly be paranoid that no direct access to this region
3080 * is reordered to before the fence is installed.
3082 if (i915_gem_object_needs_mb(obj))
3086 static inline int fence_number(struct drm_i915_private *dev_priv,
3087 struct drm_i915_fence_reg *fence)
3089 return fence - dev_priv->fence_regs;
3092 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3093 struct drm_i915_fence_reg *fence,
3096 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3097 int reg = fence_number(dev_priv, fence);
3099 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3102 obj->fence_reg = reg;
3104 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3106 obj->fence_reg = I915_FENCE_REG_NONE;
3108 list_del_init(&fence->lru_list);
3110 obj->fence_dirty = false;
3114 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3116 if (obj->last_fenced_seqno) {
3117 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
3121 obj->last_fenced_seqno = 0;
3124 obj->fenced_gpu_access = false;
3129 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3131 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3132 struct drm_i915_fence_reg *fence;
3135 ret = i915_gem_object_wait_fence(obj);
3139 if (obj->fence_reg == I915_FENCE_REG_NONE)
3142 fence = &dev_priv->fence_regs[obj->fence_reg];
3144 i915_gem_object_fence_lost(obj);
3145 i915_gem_object_update_fence(obj, fence, false);
3150 static struct drm_i915_fence_reg *
3151 i915_find_fence_reg(struct drm_device *dev)
3153 struct drm_i915_private *dev_priv = dev->dev_private;
3154 struct drm_i915_fence_reg *reg, *avail;
3157 /* First try to find a free reg */
3159 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3160 reg = &dev_priv->fence_regs[i];
3164 if (!reg->pin_count)
3171 /* None available, try to steal one or wait for a user to finish */
3172 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3180 /* Wait for completion of pending flips which consume fences */
3181 if (intel_has_pending_fb_unpin(dev))
3182 return ERR_PTR(-EAGAIN);
3184 return ERR_PTR(-EDEADLK);
3188 * i915_gem_object_get_fence - set up fencing for an object
3189 * @obj: object to map through a fence reg
3191 * When mapping objects through the GTT, userspace wants to be able to write
3192 * to them without having to worry about swizzling if the object is tiled.
3193 * This function walks the fence regs looking for a free one for @obj,
3194 * stealing one if it can't find any.
3196 * It then sets up the reg based on the object's properties: address, pitch
3197 * and tiling format.
3199 * For an untiled surface, this removes any existing fence.
3202 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3204 struct drm_device *dev = obj->base.dev;
3205 struct drm_i915_private *dev_priv = dev->dev_private;
3206 bool enable = obj->tiling_mode != I915_TILING_NONE;
3207 struct drm_i915_fence_reg *reg;
3210 /* Have we updated the tiling parameters upon the object and so
3211 * will need to serialise the write to the associated fence register?
3213 if (obj->fence_dirty) {
3214 ret = i915_gem_object_wait_fence(obj);
3219 /* Just update our place in the LRU if our fence is getting reused. */
3220 if (obj->fence_reg != I915_FENCE_REG_NONE) {
3221 reg = &dev_priv->fence_regs[obj->fence_reg];
3222 if (!obj->fence_dirty) {
3223 list_move_tail(®->lru_list,
3224 &dev_priv->mm.fence_list);
3227 } else if (enable) {
3228 reg = i915_find_fence_reg(dev);
3230 return PTR_ERR(reg);
3233 struct drm_i915_gem_object *old = reg->obj;
3235 ret = i915_gem_object_wait_fence(old);
3239 i915_gem_object_fence_lost(old);
3244 i915_gem_object_update_fence(obj, reg, enable);
3249 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
3250 struct drm_mm_node *gtt_space,
3251 unsigned long cache_level)
3253 struct drm_mm_node *other;
3255 /* On non-LLC machines we have to be careful when putting differing
3256 * types of snoopable memory together to avoid the prefetcher
3257 * crossing memory domains and dying.
3262 if (!drm_mm_node_allocated(gtt_space))
3265 if (list_empty(>t_space->node_list))
3268 other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3269 if (other->allocated && !other->hole_follows && other->color != cache_level)
3272 other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3273 if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3279 static void i915_gem_verify_gtt(struct drm_device *dev)
3282 struct drm_i915_private *dev_priv = dev->dev_private;
3283 struct drm_i915_gem_object *obj;
3286 list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3287 if (obj->gtt_space == NULL) {
3288 printk(KERN_ERR "object found on GTT list with no space reserved\n");
3293 if (obj->cache_level != obj->gtt_space->color) {
3294 printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3295 i915_gem_obj_ggtt_offset(obj),
3296 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3298 obj->gtt_space->color);
3303 if (!i915_gem_valid_gtt_space(dev,
3305 obj->cache_level)) {
3306 printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3307 i915_gem_obj_ggtt_offset(obj),
3308 i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3320 * Finds free space in the GTT aperture and binds the object there.
3323 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3324 struct i915_address_space *vm,
3326 bool map_and_fenceable,
3329 struct drm_device *dev = obj->base.dev;
3330 drm_i915_private_t *dev_priv = dev->dev_private;
3331 u32 size, fence_size, fence_alignment, unfenced_alignment;
3333 map_and_fenceable ? dev_priv->gtt.mappable_end : vm->total;
3334 struct i915_vma *vma;
3337 fence_size = i915_gem_get_gtt_size(dev,
3340 fence_alignment = i915_gem_get_gtt_alignment(dev,
3342 obj->tiling_mode, true);
3343 unfenced_alignment =
3344 i915_gem_get_gtt_alignment(dev,
3346 obj->tiling_mode, false);
3349 alignment = map_and_fenceable ? fence_alignment :
3351 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
3352 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
3356 size = map_and_fenceable ? fence_size : obj->base.size;
3358 /* If the object is bigger than the entire aperture, reject it early
3359 * before evicting everything in a vain attempt to find space.
3361 if (obj->base.size > gtt_max) {
3362 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3364 map_and_fenceable ? "mappable" : "total",
3369 ret = i915_gem_object_get_pages(obj);
3373 i915_gem_object_pin_pages(obj);
3375 BUG_ON(!i915_is_ggtt(vm));
3377 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3383 /* For now we only ever use 1 vma per object */
3385 WARN_ON(!list_is_singular(&obj->vma_list));
3389 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3391 obj->cache_level, 0, gtt_max,
3392 DRM_MM_SEARCH_DEFAULT);
3394 ret = i915_gem_evict_something(dev, vm, size, alignment,
3403 if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node,
3404 obj->cache_level))) {
3406 goto err_remove_node;
3409 ret = i915_gem_gtt_prepare_object(obj);
3411 goto err_remove_node;
3413 list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3414 list_add_tail(&vma->mm_list, &vm->inactive_list);
3416 if (i915_is_ggtt(vm)) {
3417 bool mappable, fenceable;
3419 fenceable = (vma->node.size == fence_size &&
3420 (vma->node.start & (fence_alignment - 1)) == 0);
3422 mappable = (vma->node.start + obj->base.size <=
3423 dev_priv->gtt.mappable_end);
3425 obj->map_and_fenceable = mappable && fenceable;
3428 WARN_ON(map_and_fenceable && !obj->map_and_fenceable);
3430 trace_i915_vma_bind(vma, map_and_fenceable);
3431 i915_gem_verify_gtt(dev);
3435 drm_mm_remove_node(&vma->node);
3437 i915_gem_vma_destroy(vma);
3439 i915_gem_object_unpin_pages(obj);
3444 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3447 /* If we don't have a page list set up, then we're not pinned
3448 * to GPU, and we can ignore the cache flush because it'll happen
3449 * again at bind time.
3451 if (obj->pages == NULL)
3455 * Stolen memory is always coherent with the GPU as it is explicitly
3456 * marked as wc by the system, or the system is cache-coherent.
3461 /* If the GPU is snooping the contents of the CPU cache,
3462 * we do not need to manually clear the CPU cache lines. However,
3463 * the caches are only snooped when the render cache is
3464 * flushed/invalidated. As we always have to emit invalidations
3465 * and flushes when moving into and out of the RENDER domain, correct
3466 * snooping behaviour occurs naturally as the result of our domain
3469 if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3472 trace_i915_gem_object_clflush(obj);
3473 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
3478 /** Flushes the GTT write domain for the object if it's dirty. */
3480 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3482 uint32_t old_write_domain;
3484 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3487 /* No actual flushing is required for the GTT write domain. Writes
3488 * to it immediately go to main memory as far as we know, so there's
3489 * no chipset flush. It also doesn't land in render cache.
3491 * However, we do have to enforce the order so that all writes through
3492 * the GTT land before any writes to the device, such as updates to
3497 old_write_domain = obj->base.write_domain;
3498 obj->base.write_domain = 0;
3500 trace_i915_gem_object_change_domain(obj,
3501 obj->base.read_domains,
3505 /** Flushes the CPU write domain for the object if it's dirty. */
3507 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3510 uint32_t old_write_domain;
3512 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3515 if (i915_gem_clflush_object(obj, force))
3516 i915_gem_chipset_flush(obj->base.dev);
3518 old_write_domain = obj->base.write_domain;
3519 obj->base.write_domain = 0;
3521 trace_i915_gem_object_change_domain(obj,
3522 obj->base.read_domains,
3527 * Moves a single object to the GTT read, and possibly write domain.
3529 * This function returns when the move is complete, including waiting on
3533 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3535 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
3536 uint32_t old_write_domain, old_read_domains;
3539 /* Not valid to be called on unbound objects. */
3540 if (!i915_gem_obj_bound_any(obj))
3543 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3546 ret = i915_gem_object_wait_rendering(obj, !write);
3550 i915_gem_object_flush_cpu_write_domain(obj, false);
3552 /* Serialise direct access to this object with the barriers for
3553 * coherent writes from the GPU, by effectively invalidating the
3554 * GTT domain upon first access.
3556 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3559 old_write_domain = obj->base.write_domain;
3560 old_read_domains = obj->base.read_domains;
3562 /* It should now be out of any other write domains, and we can update
3563 * the domain values for our changes.
3565 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3566 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3568 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3569 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3573 trace_i915_gem_object_change_domain(obj,
3577 /* And bump the LRU for this access */
3578 if (i915_gem_object_is_inactive(obj)) {
3579 struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
3581 list_move_tail(&vma->mm_list,
3582 &dev_priv->gtt.base.inactive_list);
3589 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3590 enum i915_cache_level cache_level)
3592 struct drm_device *dev = obj->base.dev;
3593 drm_i915_private_t *dev_priv = dev->dev_private;
3594 struct i915_vma *vma;
3597 if (obj->cache_level == cache_level)
3600 if (obj->pin_count) {
3601 DRM_DEBUG("can not change the cache level of pinned objects\n");
3605 list_for_each_entry(vma, &obj->vma_list, vma_link) {
3606 if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
3607 ret = i915_vma_unbind(vma);
3615 if (i915_gem_obj_bound_any(obj)) {
3616 ret = i915_gem_object_finish_gpu(obj);
3620 i915_gem_object_finish_gtt(obj);
3622 /* Before SandyBridge, you could not use tiling or fence
3623 * registers with snooped memory, so relinquish any fences
3624 * currently pointing to our region in the aperture.
3626 if (INTEL_INFO(dev)->gen < 6) {
3627 ret = i915_gem_object_put_fence(obj);
3632 if (obj->has_global_gtt_mapping)
3633 i915_gem_gtt_bind_object(obj, cache_level);
3634 if (obj->has_aliasing_ppgtt_mapping)
3635 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
3639 list_for_each_entry(vma, &obj->vma_list, vma_link)
3640 vma->node.color = cache_level;
3641 obj->cache_level = cache_level;
3643 if (cpu_write_needs_clflush(obj)) {
3644 u32 old_read_domains, old_write_domain;
3646 /* If we're coming from LLC cached, then we haven't
3647 * actually been tracking whether the data is in the
3648 * CPU cache or not, since we only allow one bit set
3649 * in obj->write_domain and have been skipping the clflushes.
3650 * Just set it to the CPU cache for now.
3652 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3654 old_read_domains = obj->base.read_domains;
3655 old_write_domain = obj->base.write_domain;
3657 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3658 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3660 trace_i915_gem_object_change_domain(obj,
3665 i915_gem_verify_gtt(dev);
3669 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3670 struct drm_file *file)
3672 struct drm_i915_gem_caching *args = data;
3673 struct drm_i915_gem_object *obj;
3676 ret = i915_mutex_lock_interruptible(dev);
3680 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3681 if (&obj->base == NULL) {
3686 switch (obj->cache_level) {
3687 case I915_CACHE_LLC:
3688 case I915_CACHE_L3_LLC:
3689 args->caching = I915_CACHING_CACHED;
3693 args->caching = I915_CACHING_DISPLAY;
3697 args->caching = I915_CACHING_NONE;
3701 drm_gem_object_unreference(&obj->base);
3703 mutex_unlock(&dev->struct_mutex);
3707 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3708 struct drm_file *file)
3710 struct drm_i915_gem_caching *args = data;
3711 struct drm_i915_gem_object *obj;
3712 enum i915_cache_level level;
3715 switch (args->caching) {
3716 case I915_CACHING_NONE:
3717 level = I915_CACHE_NONE;
3719 case I915_CACHING_CACHED:
3720 level = I915_CACHE_LLC;
3722 case I915_CACHING_DISPLAY:
3723 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3729 ret = i915_mutex_lock_interruptible(dev);
3733 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3734 if (&obj->base == NULL) {
3739 ret = i915_gem_object_set_cache_level(obj, level);
3741 drm_gem_object_unreference(&obj->base);
3743 mutex_unlock(&dev->struct_mutex);
3747 static bool is_pin_display(struct drm_i915_gem_object *obj)
3749 /* There are 3 sources that pin objects:
3750 * 1. The display engine (scanouts, sprites, cursors);
3751 * 2. Reservations for execbuffer;
3754 * We can ignore reservations as we hold the struct_mutex and
3755 * are only called outside of the reservation path. The user
3756 * can only increment pin_count once, and so if after
3757 * subtracting the potential reference by the user, any pin_count
3758 * remains, it must be due to another use by the display engine.
3760 return obj->pin_count - !!obj->user_pin_count;
3764 * Prepare buffer for display plane (scanout, cursors, etc).
3765 * Can be called from an uninterruptible phase (modesetting) and allows
3766 * any flushes to be pipelined (for pageflips).
3769 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3771 struct intel_ring_buffer *pipelined)
3773 u32 old_read_domains, old_write_domain;
3776 if (pipelined != obj->ring) {
3777 ret = i915_gem_object_sync(obj, pipelined);
3782 /* Mark the pin_display early so that we account for the
3783 * display coherency whilst setting up the cache domains.
3785 obj->pin_display = true;
3787 /* The display engine is not coherent with the LLC cache on gen6. As
3788 * a result, we make sure that the pinning that is about to occur is
3789 * done with uncached PTEs. This is lowest common denominator for all
3792 * However for gen6+, we could do better by using the GFDT bit instead
3793 * of uncaching, which would allow us to flush all the LLC-cached data
3794 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3796 ret = i915_gem_object_set_cache_level(obj,
3797 HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3799 goto err_unpin_display;
3801 /* As the user may map the buffer once pinned in the display plane
3802 * (e.g. libkms for the bootup splash), we have to ensure that we
3803 * always use map_and_fenceable for all scanout buffers.
3805 ret = i915_gem_obj_ggtt_pin(obj, alignment, true, false);
3807 goto err_unpin_display;
3809 i915_gem_object_flush_cpu_write_domain(obj, true);
3811 old_write_domain = obj->base.write_domain;
3812 old_read_domains = obj->base.read_domains;
3814 /* It should now be out of any other write domains, and we can update
3815 * the domain values for our changes.
3817 obj->base.write_domain = 0;
3818 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3820 trace_i915_gem_object_change_domain(obj,
3827 obj->pin_display = is_pin_display(obj);
3832 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
3834 i915_gem_object_unpin(obj);
3835 obj->pin_display = is_pin_display(obj);
3839 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3843 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3846 ret = i915_gem_object_wait_rendering(obj, false);
3850 /* Ensure that we invalidate the GPU's caches and TLBs. */
3851 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3856 * Moves a single object to the CPU read, and possibly write domain.
3858 * This function returns when the move is complete, including waiting on
3862 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3864 uint32_t old_write_domain, old_read_domains;
3867 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3870 ret = i915_gem_object_wait_rendering(obj, !write);
3874 i915_gem_object_flush_gtt_write_domain(obj);
3876 old_write_domain = obj->base.write_domain;
3877 old_read_domains = obj->base.read_domains;
3879 /* Flush the CPU cache if it's still invalid. */
3880 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3881 i915_gem_clflush_object(obj, false);
3883 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3886 /* It should now be out of any other write domains, and we can update
3887 * the domain values for our changes.
3889 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3891 /* If we're writing through the CPU, then the GPU read domains will
3892 * need to be invalidated at next use.
3895 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3896 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3899 trace_i915_gem_object_change_domain(obj,
3906 /* Throttle our rendering by waiting until the ring has completed our requests
3907 * emitted over 20 msec ago.
3909 * Note that if we were to use the current jiffies each time around the loop,
3910 * we wouldn't escape the function with any frames outstanding if the time to
3911 * render a frame was over 20ms.
3913 * This should get us reasonable parallelism between CPU and GPU but also
3914 * relatively low latency when blocking on a particular request to finish.
3917 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3919 struct drm_i915_private *dev_priv = dev->dev_private;
3920 struct drm_i915_file_private *file_priv = file->driver_priv;
3921 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3922 struct drm_i915_gem_request *request;
3923 struct intel_ring_buffer *ring = NULL;
3924 unsigned reset_counter;
3928 ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
3932 ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
3936 spin_lock(&file_priv->mm.lock);
3937 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3938 if (time_after_eq(request->emitted_jiffies, recent_enough))
3941 ring = request->ring;
3942 seqno = request->seqno;
3944 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
3945 spin_unlock(&file_priv->mm.lock);
3950 ret = __wait_seqno(ring, seqno, reset_counter, true, NULL);
3952 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3958 i915_gem_object_pin(struct drm_i915_gem_object *obj,
3959 struct i915_address_space *vm,
3961 bool map_and_fenceable,
3964 struct i915_vma *vma;
3967 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3970 WARN_ON(map_and_fenceable && !i915_is_ggtt(vm));
3972 vma = i915_gem_obj_to_vma(obj, vm);
3976 vma->node.start & (alignment - 1)) ||
3977 (map_and_fenceable && !obj->map_and_fenceable)) {
3978 WARN(obj->pin_count,
3979 "bo is already pinned with incorrect alignment:"
3980 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
3981 " obj->map_and_fenceable=%d\n",
3982 i915_gem_obj_offset(obj, vm), alignment,
3984 obj->map_and_fenceable);
3985 ret = i915_vma_unbind(vma);
3991 if (!i915_gem_obj_bound(obj, vm)) {
3992 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3994 ret = i915_gem_object_bind_to_vm(obj, vm, alignment,
4000 if (!dev_priv->mm.aliasing_ppgtt)
4001 i915_gem_gtt_bind_object(obj, obj->cache_level);
4004 if (!obj->has_global_gtt_mapping && map_and_fenceable)
4005 i915_gem_gtt_bind_object(obj, obj->cache_level);
4008 obj->pin_mappable |= map_and_fenceable;
4014 i915_gem_object_unpin(struct drm_i915_gem_object *obj)
4016 BUG_ON(obj->pin_count == 0);
4017 BUG_ON(!i915_gem_obj_bound_any(obj));
4019 if (--obj->pin_count == 0)
4020 obj->pin_mappable = false;
4024 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4025 struct drm_file *file)
4027 struct drm_i915_gem_pin *args = data;
4028 struct drm_i915_gem_object *obj;
4031 ret = i915_mutex_lock_interruptible(dev);
4035 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4036 if (&obj->base == NULL) {
4041 if (obj->madv != I915_MADV_WILLNEED) {
4042 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4047 if (obj->pin_filp != NULL && obj->pin_filp != file) {
4048 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4054 if (obj->user_pin_count == ULONG_MAX) {
4059 if (obj->user_pin_count == 0) {
4060 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, true, false);
4065 obj->user_pin_count++;
4066 obj->pin_filp = file;
4068 args->offset = i915_gem_obj_ggtt_offset(obj);
4070 drm_gem_object_unreference(&obj->base);
4072 mutex_unlock(&dev->struct_mutex);
4077 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4078 struct drm_file *file)
4080 struct drm_i915_gem_pin *args = data;
4081 struct drm_i915_gem_object *obj;
4084 ret = i915_mutex_lock_interruptible(dev);
4088 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4089 if (&obj->base == NULL) {
4094 if (obj->pin_filp != file) {
4095 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4100 obj->user_pin_count--;
4101 if (obj->user_pin_count == 0) {
4102 obj->pin_filp = NULL;
4103 i915_gem_object_unpin(obj);
4107 drm_gem_object_unreference(&obj->base);
4109 mutex_unlock(&dev->struct_mutex);
4114 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4115 struct drm_file *file)
4117 struct drm_i915_gem_busy *args = data;
4118 struct drm_i915_gem_object *obj;
4121 ret = i915_mutex_lock_interruptible(dev);
4125 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4126 if (&obj->base == NULL) {
4131 /* Count all active objects as busy, even if they are currently not used
4132 * by the gpu. Users of this interface expect objects to eventually
4133 * become non-busy without any further actions, therefore emit any
4134 * necessary flushes here.
4136 ret = i915_gem_object_flush_active(obj);
4138 args->busy = obj->active;
4140 args->busy |= intel_ring_flag(obj->ring) << 16;
4143 drm_gem_object_unreference(&obj->base);
4145 mutex_unlock(&dev->struct_mutex);
4150 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4151 struct drm_file *file_priv)
4153 return i915_gem_ring_throttle(dev, file_priv);
4157 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4158 struct drm_file *file_priv)
4160 struct drm_i915_gem_madvise *args = data;
4161 struct drm_i915_gem_object *obj;
4164 switch (args->madv) {
4165 case I915_MADV_DONTNEED:
4166 case I915_MADV_WILLNEED:
4172 ret = i915_mutex_lock_interruptible(dev);
4176 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4177 if (&obj->base == NULL) {
4182 if (obj->pin_count) {
4187 if (obj->madv != __I915_MADV_PURGED)
4188 obj->madv = args->madv;
4190 /* if the object is no longer attached, discard its backing storage */
4191 if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4192 i915_gem_object_truncate(obj);
4194 args->retained = obj->madv != __I915_MADV_PURGED;
4197 drm_gem_object_unreference(&obj->base);
4199 mutex_unlock(&dev->struct_mutex);
4203 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4204 const struct drm_i915_gem_object_ops *ops)
4206 INIT_LIST_HEAD(&obj->global_list);
4207 INIT_LIST_HEAD(&obj->ring_list);
4208 INIT_LIST_HEAD(&obj->obj_exec_link);
4209 INIT_LIST_HEAD(&obj->vma_list);
4213 obj->fence_reg = I915_FENCE_REG_NONE;
4214 obj->madv = I915_MADV_WILLNEED;
4215 /* Avoid an unnecessary call to unbind on the first bind. */
4216 obj->map_and_fenceable = true;
4218 i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4221 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4222 .get_pages = i915_gem_object_get_pages_gtt,
4223 .put_pages = i915_gem_object_put_pages_gtt,
4226 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4229 struct drm_i915_gem_object *obj;
4231 struct address_space *mapping;
4235 obj = i915_gem_object_alloc(dev);
4239 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4240 i915_gem_object_free(obj);
4245 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4246 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4247 /* 965gm cannot relocate objects above 4GiB. */
4248 mask &= ~__GFP_HIGHMEM;
4249 mask |= __GFP_DMA32;
4252 mapping = file_inode(obj->base.filp)->i_mapping;
4253 mapping_set_gfp_mask(mapping, mask);
4256 i915_gem_object_init(obj, &i915_gem_object_ops);
4258 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4259 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4262 /* On some devices, we can have the GPU use the LLC (the CPU
4263 * cache) for about a 10% performance improvement
4264 * compared to uncached. Graphics requests other than
4265 * display scanout are coherent with the CPU in
4266 * accessing this cache. This means in this mode we
4267 * don't need to clflush on the CPU side, and on the
4268 * GPU side we only need to flush internal caches to
4269 * get data visible to the CPU.
4271 * However, we maintain the display planes as UC, and so
4272 * need to rebind when first used as such.
4274 obj->cache_level = I915_CACHE_LLC;
4276 obj->cache_level = I915_CACHE_NONE;
4278 trace_i915_gem_object_create(obj);
4283 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4285 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4286 struct drm_device *dev = obj->base.dev;
4287 drm_i915_private_t *dev_priv = dev->dev_private;
4288 struct i915_vma *vma, *next;
4290 intel_runtime_pm_get(dev_priv);
4292 trace_i915_gem_object_destroy(obj);
4295 i915_gem_detach_phys_object(dev, obj);
4298 /* NB: 0 or 1 elements */
4300 WARN_ON(!list_empty(&obj->vma_list) &&
4301 !list_is_singular(&obj->vma_list));
4303 list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4304 int ret = i915_vma_unbind(vma);
4305 if (WARN_ON(ret == -ERESTARTSYS)) {
4306 bool was_interruptible;
4308 was_interruptible = dev_priv->mm.interruptible;
4309 dev_priv->mm.interruptible = false;
4311 WARN_ON(i915_vma_unbind(vma));
4313 dev_priv->mm.interruptible = was_interruptible;
4317 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4318 * before progressing. */
4320 i915_gem_object_unpin_pages(obj);
4322 if (WARN_ON(obj->pages_pin_count))
4323 obj->pages_pin_count = 0;
4324 i915_gem_object_put_pages(obj);
4325 i915_gem_object_free_mmap_offset(obj);
4330 if (obj->base.import_attach)
4331 drm_prime_gem_destroy(&obj->base, NULL);
4334 drm_gem_object_release(&obj->base);
4335 i915_gem_info_remove_obj(dev_priv, obj->base.size);
4338 i915_gem_object_free(obj);
4340 intel_runtime_pm_put(dev_priv);
4343 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4344 struct i915_address_space *vm)
4346 struct i915_vma *vma;
4347 list_for_each_entry(vma, &obj->vma_list, vma_link)
4354 static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj,
4355 struct i915_address_space *vm)
4357 struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL);
4359 return ERR_PTR(-ENOMEM);
4361 INIT_LIST_HEAD(&vma->vma_link);
4362 INIT_LIST_HEAD(&vma->mm_list);
4363 INIT_LIST_HEAD(&vma->exec_list);
4367 /* Keep GGTT vmas first to make debug easier */
4368 if (i915_is_ggtt(vm))
4369 list_add(&vma->vma_link, &obj->vma_list);
4371 list_add_tail(&vma->vma_link, &obj->vma_list);
4377 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
4378 struct i915_address_space *vm)
4380 struct i915_vma *vma;
4382 vma = i915_gem_obj_to_vma(obj, vm);
4384 vma = __i915_gem_vma_create(obj, vm);
4389 void i915_gem_vma_destroy(struct i915_vma *vma)
4391 WARN_ON(vma->node.allocated);
4393 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4394 if (!list_empty(&vma->exec_list))
4397 list_del(&vma->vma_link);
4403 i915_gem_suspend(struct drm_device *dev)
4405 drm_i915_private_t *dev_priv = dev->dev_private;
4408 mutex_lock(&dev->struct_mutex);
4409 if (dev_priv->ums.mm_suspended)
4412 ret = i915_gpu_idle(dev);
4416 i915_gem_retire_requests(dev);
4418 /* Under UMS, be paranoid and evict. */
4419 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4420 i915_gem_evict_everything(dev);
4422 i915_kernel_lost_context(dev);
4423 i915_gem_cleanup_ringbuffer(dev);
4425 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4426 * We need to replace this with a semaphore, or something.
4427 * And not confound ums.mm_suspended!
4429 dev_priv->ums.mm_suspended = !drm_core_check_feature(dev,
4431 mutex_unlock(&dev->struct_mutex);
4433 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4434 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4435 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
4440 mutex_unlock(&dev->struct_mutex);
4444 int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice)
4446 struct drm_device *dev = ring->dev;
4447 drm_i915_private_t *dev_priv = dev->dev_private;
4448 u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4449 u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4452 if (!HAS_L3_DPF(dev) || !remap_info)
4455 ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4460 * Note: We do not worry about the concurrent register cacheline hang
4461 * here because no other code should access these registers other than
4462 * at initialization time.
4464 for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4465 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4466 intel_ring_emit(ring, reg_base + i);
4467 intel_ring_emit(ring, remap_info[i/4]);
4470 intel_ring_advance(ring);
4475 void i915_gem_init_swizzling(struct drm_device *dev)
4477 drm_i915_private_t *dev_priv = dev->dev_private;
4479 if (INTEL_INFO(dev)->gen < 5 ||
4480 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4483 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4484 DISP_TILE_SURFACE_SWIZZLING);
4489 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4491 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4492 else if (IS_GEN7(dev))
4493 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4494 else if (IS_GEN8(dev))
4495 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4501 intel_enable_blt(struct drm_device *dev)
4508 /* The blitter was dysfunctional on early prototypes */
4509 revision = pci_read_config(dev->dev, PCIR_REVID, 1);
4510 if (IS_GEN6(dev) && revision < 8) {
4511 DRM_INFO("BLT not supported on this pre-production hardware;"
4512 " graphics performance will be degraded.\n");
4519 static int i915_gem_init_rings(struct drm_device *dev)
4521 struct drm_i915_private *dev_priv = dev->dev_private;
4524 ret = intel_init_render_ring_buffer(dev);
4529 ret = intel_init_bsd_ring_buffer(dev);
4531 goto cleanup_render_ring;
4534 if (intel_enable_blt(dev)) {
4535 ret = intel_init_blt_ring_buffer(dev);
4537 goto cleanup_bsd_ring;
4540 if (HAS_VEBOX(dev)) {
4541 ret = intel_init_vebox_ring_buffer(dev);
4543 goto cleanup_blt_ring;
4547 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4549 goto cleanup_vebox_ring;
4554 intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4556 intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4558 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4559 cleanup_render_ring:
4560 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4566 i915_gem_init_hw(struct drm_device *dev)
4568 drm_i915_private_t *dev_priv = dev->dev_private;
4572 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4576 if (dev_priv->ellc_size)
4577 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4579 if (IS_HASWELL(dev))
4580 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4581 LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4583 if (HAS_PCH_NOP(dev)) {
4584 u32 temp = I915_READ(GEN7_MSG_CTL);
4585 temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4586 I915_WRITE(GEN7_MSG_CTL, temp);
4589 i915_gem_init_swizzling(dev);
4591 ret = i915_gem_init_rings(dev);
4595 for (i = 0; i < NUM_L3_SLICES(dev); i++)
4596 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4599 * XXX: There was some w/a described somewhere suggesting loading
4600 * contexts before PPGTT.
4602 ret = i915_gem_context_init(dev);
4604 i915_gem_cleanup_ringbuffer(dev);
4605 DRM_ERROR("Context initialization failed %d\n", ret);
4609 if (dev_priv->mm.aliasing_ppgtt) {
4610 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
4612 i915_gem_cleanup_aliasing_ppgtt(dev);
4613 DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4620 int i915_gem_init(struct drm_device *dev)
4622 struct drm_i915_private *dev_priv = dev->dev_private;
4625 mutex_lock(&dev->struct_mutex);
4627 if (IS_VALLEYVIEW(dev)) {
4628 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4629 I915_WRITE(VLV_GTLC_WAKE_CTRL, 1);
4630 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10))
4631 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4634 i915_gem_init_global_gtt(dev);
4636 ret = i915_gem_init_hw(dev);
4637 mutex_unlock(&dev->struct_mutex);
4639 i915_gem_cleanup_aliasing_ppgtt(dev);
4643 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4644 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4645 dev_priv->dri1.allow_batchbuffer = 1;
4650 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4652 drm_i915_private_t *dev_priv = dev->dev_private;
4653 struct intel_ring_buffer *ring;
4656 for_each_ring(ring, dev_priv, i)
4657 intel_cleanup_ring_buffer(ring);
4661 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4662 struct drm_file *file_priv)
4664 struct drm_i915_private *dev_priv = dev->dev_private;
4667 if (drm_core_check_feature(dev, DRIVER_MODESET))
4670 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4671 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4672 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4675 mutex_lock(&dev->struct_mutex);
4676 dev_priv->ums.mm_suspended = 0;
4678 ret = i915_gem_init_hw(dev);
4680 mutex_unlock(&dev->struct_mutex);
4684 BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
4685 mutex_unlock(&dev->struct_mutex);
4687 ret = drm_irq_install(dev);
4689 goto cleanup_ringbuffer;
4694 mutex_lock(&dev->struct_mutex);
4695 i915_gem_cleanup_ringbuffer(dev);
4696 dev_priv->ums.mm_suspended = 1;
4697 mutex_unlock(&dev->struct_mutex);
4703 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4704 struct drm_file *file_priv)
4706 if (drm_core_check_feature(dev, DRIVER_MODESET))
4709 drm_irq_uninstall(dev);
4711 return i915_gem_suspend(dev);
4715 i915_gem_lastclose(struct drm_device *dev)
4719 if (drm_core_check_feature(dev, DRIVER_MODESET))
4722 ret = i915_gem_suspend(dev);
4724 DRM_ERROR("failed to idle hardware: %d\n", ret);
4728 init_ring_lists(struct intel_ring_buffer *ring)
4730 INIT_LIST_HEAD(&ring->active_list);
4731 INIT_LIST_HEAD(&ring->request_list);
4734 static void i915_init_vm(struct drm_i915_private *dev_priv,
4735 struct i915_address_space *vm)
4737 vm->dev = dev_priv->dev;
4738 INIT_LIST_HEAD(&vm->active_list);
4739 INIT_LIST_HEAD(&vm->inactive_list);
4740 INIT_LIST_HEAD(&vm->global_link);
4741 list_add(&vm->global_link, &dev_priv->vm_list);
4745 i915_gem_load(struct drm_device *dev)
4747 drm_i915_private_t *dev_priv = dev->dev_private;
4750 INIT_LIST_HEAD(&dev_priv->vm_list);
4751 i915_init_vm(dev_priv, &dev_priv->gtt.base);
4753 INIT_LIST_HEAD(&dev_priv->context_list);
4754 INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4755 INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4756 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4757 for (i = 0; i < I915_NUM_RINGS; i++)
4758 init_ring_lists(&dev_priv->ring[i]);
4759 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4760 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4761 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4762 i915_gem_retire_work_handler);
4763 INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
4764 i915_gem_idle_work_handler);
4765 init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4767 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4769 I915_WRITE(MI_ARB_STATE,
4770 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4773 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4775 /* Old X drivers will take 0-2 for front, back, depth buffers */
4776 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4777 dev_priv->fence_reg_start = 3;
4779 if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4780 dev_priv->num_fence_regs = 32;
4781 else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4782 dev_priv->num_fence_regs = 16;
4784 dev_priv->num_fence_regs = 8;
4786 /* Initialize fence registers to zero */
4787 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4788 i915_gem_restore_fences(dev);
4790 i915_gem_detect_bit_6_swizzle(dev);
4791 init_waitqueue_head(&dev_priv->pending_flip_queue);
4793 dev_priv->mm.interruptible = true;
4796 dev_priv->mm.inactive_shrinker.scan_objects = i915_gem_inactive_scan;
4797 dev_priv->mm.inactive_shrinker.count_objects = i915_gem_inactive_count;
4798 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4799 register_shrinker(&dev_priv->mm.inactive_shrinker);
4800 /* Old FreeBSD code */
4801 dev_priv->mm.inactive_shrinker = EVENTHANDLER_REGISTER(vm_lowmem,
4802 i915_gem_inactive_shrink, dev, EVENTHANDLER_PRI_ANY);
4807 * Create a physically contiguous memory object for this object
4808 * e.g. for cursor + overlay regs
4810 static int i915_gem_init_phys_object(struct drm_device *dev,
4811 int id, int size, int align)
4813 drm_i915_private_t *dev_priv = dev->dev_private;
4814 struct drm_i915_gem_phys_object *phys_obj;
4817 if (dev_priv->mm.phys_objs[id - 1] || !size)
4820 phys_obj = kzalloc(sizeof(*phys_obj), GFP_KERNEL);
4826 phys_obj->handle = drm_pci_alloc(dev, size, align);
4827 if (!phys_obj->handle) {
4832 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4834 pmap_change_attr((vm_offset_t)phys_obj->handle->vaddr,
4835 size / PAGE_SIZE, PAT_WRITE_COMBINING);
4837 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4845 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4847 drm_i915_private_t *dev_priv = dev->dev_private;
4848 struct drm_i915_gem_phys_object *phys_obj;
4850 if (!dev_priv->mm.phys_objs[id - 1])
4853 phys_obj = dev_priv->mm.phys_objs[id - 1];
4854 if (phys_obj->cur_obj) {
4855 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4859 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4861 drm_pci_free(dev, phys_obj->handle);
4863 dev_priv->mm.phys_objs[id - 1] = NULL;
4866 void i915_gem_free_all_phys_object(struct drm_device *dev)
4870 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4871 i915_gem_free_phys_object(dev, i);
4874 void i915_gem_detach_phys_object(struct drm_device *dev,
4875 struct drm_i915_gem_object *obj)
4877 struct vm_object *mapping = obj->base.vm_obj;
4884 vaddr = obj->phys_obj->handle->vaddr;
4886 page_count = obj->base.size / PAGE_SIZE;
4887 for (i = 0; i < page_count; i++) {
4888 struct vm_page *page = shmem_read_mapping_page(mapping, i);
4889 if (!IS_ERR(page)) {
4890 char *dst = kmap_atomic(page);
4891 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4894 drm_clflush_pages(&page, 1);
4896 set_page_dirty(page);
4897 mark_page_accessed(page);
4899 page_cache_release(page);
4901 vm_page_busy_wait(page, FALSE, "i915gem");
4902 vm_page_unwire(page, 0);
4903 vm_page_wakeup(page);
4906 i915_gem_chipset_flush(dev);
4908 obj->phys_obj->cur_obj = NULL;
4909 obj->phys_obj = NULL;
4913 i915_gem_attach_phys_object(struct drm_device *dev,
4914 struct drm_i915_gem_object *obj,
4918 struct vm_object *mapping = obj->base.vm_obj;
4919 drm_i915_private_t *dev_priv = dev->dev_private;
4924 if (id > I915_MAX_PHYS_OBJECT)
4927 if (obj->phys_obj) {
4928 if (obj->phys_obj->id == id)
4930 i915_gem_detach_phys_object(dev, obj);
4933 /* create a new object */
4934 if (!dev_priv->mm.phys_objs[id - 1]) {
4935 ret = i915_gem_init_phys_object(dev, id,
4936 obj->base.size, align);
4938 DRM_ERROR("failed to init phys object %d size: %zu\n",
4939 id, obj->base.size);
4944 /* bind to the object */
4945 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4946 obj->phys_obj->cur_obj = obj;
4948 page_count = obj->base.size / PAGE_SIZE;
4950 for (i = 0; i < page_count; i++) {
4951 struct vm_page *page;
4954 page = shmem_read_mapping_page(mapping, i);
4956 return PTR_ERR(page);
4958 src = kmap_atomic(page);
4959 dst = (char*)obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4960 memcpy(dst, src, PAGE_SIZE);
4963 mark_page_accessed(page);
4965 page_cache_release(page);
4967 vm_page_busy_wait(page, FALSE, "i915gem");
4968 vm_page_unwire(page, 0);
4969 vm_page_wakeup(page);
4976 i915_gem_phys_pwrite(struct drm_device *dev,
4977 struct drm_i915_gem_object *obj,
4978 struct drm_i915_gem_pwrite *args,
4979 struct drm_file *file_priv)
4981 void *vaddr = (char *)obj->phys_obj->handle->vaddr + args->offset;
4982 char __user *user_data = to_user_ptr(args->data_ptr);
4984 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4985 unsigned long unwritten;
4987 /* The physical object once assigned is fixed for the lifetime
4988 * of the obj, so we can safely drop the lock and continue
4991 mutex_unlock(&dev->struct_mutex);
4992 unwritten = copy_from_user(vaddr, user_data, args->size);
4993 mutex_lock(&dev->struct_mutex);
4998 i915_gem_chipset_flush(dev);
5002 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5004 struct drm_i915_file_private *file_priv = file->driver_priv;
5006 /* Clean up our request list when the client is going away, so that
5007 * later retire_requests won't dereference our soon-to-be-gone
5010 spin_lock(&file_priv->mm.lock);
5011 while (!list_empty(&file_priv->mm.request_list)) {
5012 struct drm_i915_gem_request *request;
5014 request = list_first_entry(&file_priv->mm.request_list,
5015 struct drm_i915_gem_request,
5017 list_del(&request->client_list);
5018 request->file_priv = NULL;
5020 spin_unlock(&file_priv->mm.lock);
5024 i915_gem_pager_ctor(void *handle, vm_ooffset_t size, vm_prot_t prot,
5025 vm_ooffset_t foff, struct ucred *cred, u_short *color)
5027 *color = 0; /* XXXKIB */
5032 i915_gem_pager_dtor(void *handle)
5034 struct drm_gem_object *obj;
5035 struct drm_device *dev;
5040 mutex_lock(&dev->struct_mutex);
5041 drm_gem_free_mmap_offset(obj);
5042 i915_gem_release_mmap(to_intel_bo(obj));
5043 drm_gem_object_unreference(obj);
5044 mutex_unlock(&dev->struct_mutex);
5048 i915_gem_file_idle_work_handler(struct work_struct *work)
5050 struct drm_i915_file_private *file_priv =
5051 container_of(work, typeof(*file_priv), mm.idle_work.work);
5053 atomic_set(&file_priv->rps_wait_boost, false);
5056 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5058 struct drm_i915_file_private *file_priv;
5060 DRM_DEBUG_DRIVER("\n");
5062 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5066 file->driver_priv = file_priv;
5067 file_priv->dev_priv = dev->dev_private;
5069 spin_init(&file_priv->mm.lock, "i915_priv");
5070 INIT_LIST_HEAD(&file_priv->mm.request_list);
5071 INIT_DELAYED_WORK(&file_priv->mm.idle_work,
5072 i915_gem_file_idle_work_handler);
5074 idr_init(&file_priv->context_idr);
5080 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
5082 if (!mutex_is_locked(mutex))
5085 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
5086 return mutex->owner == task;
5088 /* Since UP may be pre-empted, we cannot assume that we own the lock */
5095 static unsigned long
5096 i915_gem_inactive_count(struct shrinker *shrinker, struct shrink_control *sc)
5098 struct drm_i915_private *dev_priv =
5099 container_of(shrinker,
5100 struct drm_i915_private,
5101 mm.inactive_shrinker);
5102 struct drm_device *dev = dev_priv->dev;
5103 struct drm_i915_gem_object *obj;
5105 unsigned long count;
5107 if (!mutex_trylock(&dev->struct_mutex)) {
5108 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5111 if (dev_priv->mm.shrinker_no_lock_stealing)
5118 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
5119 if (obj->pages_pin_count == 0)
5120 count += obj->base.size >> PAGE_SHIFT;
5122 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5126 if (obj->pin_count == 0 && obj->pages_pin_count == 0)
5127 count += obj->base.size >> PAGE_SHIFT;
5131 mutex_unlock(&dev->struct_mutex);
5137 /* All the new VM stuff */
5138 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
5139 struct i915_address_space *vm)
5141 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5142 struct i915_vma *vma;
5144 if (vm == &dev_priv->mm.aliasing_ppgtt->base)
5145 vm = &dev_priv->gtt.base;
5147 BUG_ON(list_empty(&o->vma_list));
5148 list_for_each_entry(vma, &o->vma_list, vma_link) {
5150 return vma->node.start;
5156 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5157 struct i915_address_space *vm)
5159 struct i915_vma *vma;
5161 list_for_each_entry(vma, &o->vma_list, vma_link)
5162 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5168 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5170 struct i915_vma *vma;
5172 list_for_each_entry(vma, &o->vma_list, vma_link)
5173 if (drm_mm_node_allocated(&vma->node))
5179 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5180 struct i915_address_space *vm)
5182 struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5183 struct i915_vma *vma;
5185 if (vm == &dev_priv->mm.aliasing_ppgtt->base)
5186 vm = &dev_priv->gtt.base;
5188 BUG_ON(list_empty(&o->vma_list));
5190 list_for_each_entry(vma, &o->vma_list, vma_link)
5192 return vma->node.size;
5198 static unsigned long
5199 i915_gem_inactive_scan(struct shrinker *shrinker, struct shrink_control *sc)
5201 struct drm_i915_private *dev_priv =
5202 container_of(shrinker,
5203 struct drm_i915_private,
5204 mm.inactive_shrinker);
5205 struct drm_device *dev = dev_priv->dev;
5206 unsigned long freed;
5209 if (!mutex_trylock(&dev->struct_mutex)) {
5210 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5213 if (dev_priv->mm.shrinker_no_lock_stealing)
5219 freed = i915_gem_purge(dev_priv, sc->nr_to_scan);
5220 if (freed < sc->nr_to_scan)
5221 freed += __i915_gem_shrink(dev_priv,
5222 sc->nr_to_scan - freed,
5224 if (freed < sc->nr_to_scan)
5225 freed += i915_gem_shrink_all(dev_priv);
5228 mutex_unlock(&dev->struct_mutex);
5234 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5236 struct i915_vma *vma;
5238 if (WARN_ON(list_empty(&obj->vma_list)))
5241 vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link);
5242 if (WARN_ON(vma->vm != obj_to_ggtt(obj)))