2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk>
3 * and Duncan Barclay<dmlb@dmlb.org>
4 * Modifications for FreeBSD-stable by Edwin Groothuis
5 * <edwin at mavetju.org
6 * < http://lists.freebsd.org/mailman/listinfo/freebsd-bugs>>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * $FreeBSD: src/sys/dev/bfe/if_bfe.c 1.4.4.7 2004/03/02 08:41:33 julian Exp v
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/sockio.h>
38 #include <sys/malloc.h>
39 #include <sys/interrupt.h>
40 #include <sys/kernel.h>
41 #include <sys/socket.h>
42 #include <sys/queue.h>
45 #include <sys/thread2.h>
48 #include <net/ifq_var.h>
49 #include <net/if_arp.h>
50 #include <net/ethernet.h>
51 #include <net/if_dl.h>
52 #include <net/if_media.h>
56 #include <net/if_types.h>
57 #include <net/vlan/if_vlan_var.h>
59 #include <netinet/in_systm.h>
60 #include <netinet/in.h>
61 #include <netinet/ip.h>
63 #include <bus/pci/pcireg.h>
64 #include <bus/pci/pcivar.h>
65 #include <bus/pci/pcidevs.h>
67 #include <dev/netif/mii_layer/mii.h>
68 #include <dev/netif/mii_layer/miivar.h>
70 #include <dev/netif/bfe/if_bfereg.h>
72 MODULE_DEPEND(bfe, pci, 1, 1, 1);
73 MODULE_DEPEND(bfe, miibus, 1, 1, 1);
75 /* "controller miibus0" required. See GENERIC if you get errors here. */
76 #include "miibus_if.h"
78 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */
80 static struct bfe_type bfe_devs[] = {
81 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401,
82 "Broadcom BCM4401 Fast Ethernet" },
83 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401B0,
84 "Broadcom BCM4401-B0 Fast Ethernet" },
85 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4402,
86 "Broadcom BCM4402 Fast Ethernet" },
90 static int bfe_probe(device_t);
91 static int bfe_attach(device_t);
92 static int bfe_detach(device_t);
93 static void bfe_intr(void *);
94 static void bfe_start(struct ifnet *, struct ifaltq_subque *);
95 static int bfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
96 static void bfe_init(void *);
97 static void bfe_stop(struct bfe_softc *);
98 static void bfe_watchdog(struct ifnet *);
99 static void bfe_shutdown(device_t);
100 static void bfe_tick(void *);
101 static void bfe_txeof(struct bfe_softc *);
102 static void bfe_rxeof(struct bfe_softc *);
103 static void bfe_set_rx_mode(struct bfe_softc *);
104 static int bfe_list_rx_init(struct bfe_softc *);
105 static int bfe_newbuf(struct bfe_softc *, int, int);
106 static void bfe_setup_rxdesc(struct bfe_softc *, int);
107 static void bfe_rx_ring_free(struct bfe_softc *);
109 static void bfe_pci_setup(struct bfe_softc *, uint32_t);
110 static int bfe_ifmedia_upd(struct ifnet *);
111 static void bfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
112 static int bfe_miibus_readreg(device_t, int, int);
113 static int bfe_miibus_writereg(device_t, int, int, int);
114 static int bfe_wait_bit(struct bfe_softc *, uint32_t, uint32_t,
116 static void bfe_get_config(struct bfe_softc *sc);
117 static void bfe_read_eeprom(struct bfe_softc *, uint8_t *);
118 static void bfe_stats_update(struct bfe_softc *);
119 static void bfe_clear_stats (struct bfe_softc *);
120 static int bfe_readphy(struct bfe_softc *, uint32_t, uint32_t*);
121 static int bfe_writephy(struct bfe_softc *, uint32_t, uint32_t);
122 static int bfe_resetphy(struct bfe_softc *);
123 static int bfe_setupphy(struct bfe_softc *);
124 static void bfe_chip_reset(struct bfe_softc *);
125 static void bfe_chip_halt(struct bfe_softc *);
126 static void bfe_core_reset(struct bfe_softc *);
127 static void bfe_core_disable(struct bfe_softc *);
128 static int bfe_dma_alloc(device_t);
129 static void bfe_dma_free(struct bfe_softc *);
130 static void bfe_cam_write(struct bfe_softc *, u_char *, int);
132 static device_method_t bfe_methods[] = {
133 /* Device interface */
134 DEVMETHOD(device_probe, bfe_probe),
135 DEVMETHOD(device_attach, bfe_attach),
136 DEVMETHOD(device_detach, bfe_detach),
137 DEVMETHOD(device_shutdown, bfe_shutdown),
140 DEVMETHOD(bus_print_child, bus_generic_print_child),
141 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
144 DEVMETHOD(miibus_readreg, bfe_miibus_readreg),
145 DEVMETHOD(miibus_writereg, bfe_miibus_writereg),
150 static driver_t bfe_driver = {
153 sizeof(struct bfe_softc)
156 static devclass_t bfe_devclass;
158 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, NULL, NULL);
159 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, NULL, NULL);
162 * Probe for a Broadcom 4401 chip.
165 bfe_probe(device_t dev)
168 uint16_t vendor, product;
170 vendor = pci_get_vendor(dev);
171 product = pci_get_device(dev);
173 for (t = bfe_devs; t->bfe_name != NULL; t++) {
174 if (vendor == t->bfe_vid && product == t->bfe_did) {
175 device_set_desc(dev, t->bfe_name);
184 bfe_dma_alloc(device_t dev)
186 struct bfe_softc *sc = device_get_softc(dev);
188 int error, i, tx_pos = 0, rx_pos = 0;
191 * Parent tag. Apparently the chip cannot handle any DMA address
192 * greater than BFE_BUS_SPACE_MAXADDR (1GB).
194 error = bus_dma_tag_create(NULL, /* parent */
195 1, 0, /* alignment, boundary */
196 BFE_BUS_SPACE_MAXADDR, /* lowaddr */
197 BUS_SPACE_MAXADDR, /* highaddr */
198 NULL, NULL, /* filter, filterarg */
199 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
200 0, /* num of segments */
201 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */
203 &sc->bfe_parent_tag);
205 device_printf(dev, "could not allocate parent dma tag\n");
209 /* Allocate TX ring */
210 error = bus_dmamem_coherent(sc->bfe_parent_tag, PAGE_SIZE, 0,
211 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
213 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
215 device_printf(dev, "could not allocate TX list\n");
218 sc->bfe_tx_tag = dmem.dmem_tag;
219 sc->bfe_tx_map = dmem.dmem_map;
220 sc->bfe_tx_list = dmem.dmem_addr;
221 sc->bfe_tx_dma = dmem.dmem_busaddr;
223 /* Allocate RX ring */
224 error = bus_dmamem_coherent(sc->bfe_parent_tag, PAGE_SIZE, 0,
225 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
227 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
229 device_printf(dev, "could not allocate RX list\n");
232 sc->bfe_rx_tag = dmem.dmem_tag;
233 sc->bfe_rx_map = dmem.dmem_map;
234 sc->bfe_rx_list = dmem.dmem_addr;
235 sc->bfe_rx_dma = dmem.dmem_busaddr;
237 /* Tag for RX mbufs */
238 error = bus_dma_tag_create(sc->bfe_parent_tag, 1, 0,
239 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
241 MCLBYTES, 1, MCLBYTES,
242 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
245 device_printf(dev, "could not allocate dma tag for RX mbufs\n");
249 error = bus_dmamap_create(sc->bfe_rxbuf_tag, BUS_DMA_WAITOK,
252 device_printf(dev, "could not create RX mbuf tmp map\n");
253 bus_dma_tag_destroy(sc->bfe_rxbuf_tag);
254 sc->bfe_rxbuf_tag = NULL;
258 /* Allocate dma maps for RX list */
259 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
260 error = bus_dmamap_create(sc->bfe_rxbuf_tag, BUS_DMA_WAITOK,
261 &sc->bfe_rx_ring[i].bfe_map);
264 device_printf(dev, "cannot create DMA map for RX\n");
268 rx_pos = BFE_RX_LIST_CNT;
270 /* Tag for TX mbufs */
271 error = bus_dma_tag_create(sc->bfe_parent_tag, 1, 0,
272 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
274 MCLBYTES, BFE_MAXSEGS, MCLBYTES,
275 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
278 device_printf(dev, "could not allocate dma tag for TX mbufs\n");
282 /* Allocate dmamaps for TX list */
283 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
284 error = bus_dmamap_create(sc->bfe_txbuf_tag, BUS_DMA_WAITOK,
285 &sc->bfe_tx_ring[i].bfe_map);
288 device_printf(dev, "cannot create DMA map for TX\n");
296 if (sc->bfe_rxbuf_tag != NULL) {
297 for (i = 0; i < rx_pos; ++i) {
298 bus_dmamap_destroy(sc->bfe_rxbuf_tag,
299 sc->bfe_rx_ring[i].bfe_map);
301 bus_dmamap_destroy(sc->bfe_rxbuf_tag, sc->bfe_rx_tmpmap);
302 bus_dma_tag_destroy(sc->bfe_rxbuf_tag);
303 sc->bfe_rxbuf_tag = NULL;
306 if (sc->bfe_txbuf_tag != NULL) {
307 for (i = 0; i < tx_pos; ++i) {
308 bus_dmamap_destroy(sc->bfe_txbuf_tag,
309 sc->bfe_tx_ring[i].bfe_map);
311 bus_dma_tag_destroy(sc->bfe_txbuf_tag);
312 sc->bfe_txbuf_tag = NULL;
318 bfe_attach(device_t dev)
321 struct bfe_softc *sc;
324 sc = device_get_softc(dev);
327 callout_init(&sc->bfe_stat_timer);
331 * Handle power management nonsense.
333 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
334 uint32_t membase, irq;
336 /* Save important PCI config data. */
337 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4);
338 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4);
340 /* Reset the power state. */
341 device_printf(dev, "chip is in D%d power mode"
342 " -- setting to D0\n", pci_get_powerstate(dev));
344 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
346 /* Restore PCI config data. */
347 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4);
348 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4);
350 #endif /* !BURN_BRIDGE */
353 * Map control/status registers.
355 pci_enable_busmaster(dev);
358 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
360 if (sc->bfe_res == NULL) {
361 device_printf(dev, "couldn't map memory\n");
365 sc->bfe_btag = rman_get_bustag(sc->bfe_res);
366 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res);
368 /* Allocate interrupt */
371 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
372 RF_SHAREABLE | RF_ACTIVE);
373 if (sc->bfe_irq == NULL) {
374 device_printf(dev, "couldn't map interrupt\n");
379 error = bfe_dma_alloc(dev);
381 device_printf(dev, "failed to allocate DMA resources\n");
385 /* Set up ifnet structure */
386 ifp = &sc->arpcom.ac_if;
388 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
389 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
390 ifp->if_ioctl = bfe_ioctl;
391 ifp->if_start = bfe_start;
392 ifp->if_watchdog = bfe_watchdog;
393 ifp->if_init = bfe_init;
394 ifp->if_mtu = ETHERMTU;
395 ifp->if_baudrate = 100000000;
396 ifp->if_capabilities |= IFCAP_VLAN_MTU;
397 ifp->if_capenable |= IFCAP_VLAN_MTU;
398 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
399 ifq_set_maxlen(&ifp->if_snd, BFE_TX_QLEN);
400 ifq_set_ready(&ifp->if_snd);
404 /* Reset the chip and turn on the PHY */
407 if (mii_phy_probe(dev, &sc->bfe_miibus,
408 bfe_ifmedia_upd, bfe_ifmedia_sts)) {
409 device_printf(dev, "MII without any PHY!\n");
414 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL);
417 * Hook interrupt last to avoid having to lock softc
419 error = bus_setup_intr(dev, sc->bfe_irq, INTR_MPSAFE,
420 bfe_intr, sc, &sc->bfe_intrhand,
421 sc->arpcom.ac_if.if_serializer);
425 device_printf(dev, "couldn't set up irq\n");
429 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->bfe_irq));
437 bfe_detach(device_t dev)
439 struct bfe_softc *sc = device_get_softc(dev);
440 struct ifnet *ifp = &sc->arpcom.ac_if;
442 if (device_is_attached(dev)) {
443 lwkt_serialize_enter(ifp->if_serializer);
446 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand);
447 lwkt_serialize_exit(ifp->if_serializer);
451 if (sc->bfe_miibus != NULL)
452 device_delete_child(dev, sc->bfe_miibus);
453 bus_generic_detach(dev);
455 if (sc->bfe_irq != NULL)
456 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq);
458 if (sc->bfe_res != NULL) {
459 bus_release_resource(dev, SYS_RES_MEMORY, BFE_PCI_MEMLO,
468 * Stop all chip I/O so that the kernel's probe routines don't
469 * get confused by errant DMAs when rebooting.
472 bfe_shutdown(device_t dev)
474 struct bfe_softc *sc = device_get_softc(dev);
475 struct ifnet *ifp = &sc->arpcom.ac_if;
477 lwkt_serialize_enter(ifp->if_serializer);
479 lwkt_serialize_exit(ifp->if_serializer);
483 bfe_miibus_readreg(device_t dev, int phy, int reg)
485 struct bfe_softc *sc;
488 sc = device_get_softc(dev);
489 if (phy != sc->bfe_phyaddr)
491 bfe_readphy(sc, reg, &ret);
497 bfe_miibus_writereg(device_t dev, int phy, int reg, int val)
499 struct bfe_softc *sc;
501 sc = device_get_softc(dev);
502 if (phy != sc->bfe_phyaddr)
504 bfe_writephy(sc, reg, val);
510 bfe_tx_ring_free(struct bfe_softc *sc)
514 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
515 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) {
516 bus_dmamap_unload(sc->bfe_txbuf_tag,
517 sc->bfe_tx_ring[i].bfe_map);
518 m_freem(sc->bfe_tx_ring[i].bfe_mbuf);
519 sc->bfe_tx_ring[i].bfe_mbuf = NULL;
522 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
526 bfe_rx_ring_free(struct bfe_softc *sc)
530 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
531 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) {
532 bus_dmamap_unload(sc->bfe_rxbuf_tag,
533 sc->bfe_rx_ring[i].bfe_map);
534 m_freem(sc->bfe_rx_ring[i].bfe_mbuf);
535 sc->bfe_rx_ring[i].bfe_mbuf = NULL;
538 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
542 bfe_list_rx_init(struct bfe_softc *sc)
546 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
547 error = bfe_newbuf(sc, i, 1);
552 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc)));
560 bfe_newbuf(struct bfe_softc *sc, int c, int init)
564 bus_dma_segment_t seg;
568 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
571 m->m_len = m->m_pkthdr.len = MCLBYTES;
573 error = bus_dmamap_load_mbuf_segment(sc->bfe_rxbuf_tag,
574 sc->bfe_rx_tmpmap, m,
575 &seg, 1, &nsegs, BUS_DMA_NOWAIT);
579 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n");
583 KKASSERT(c >= 0 && c < BFE_RX_LIST_CNT);
584 r = &sc->bfe_rx_ring[c];
586 if (r->bfe_mbuf != NULL)
587 bus_dmamap_unload(sc->bfe_rxbuf_tag, r->bfe_map);
590 r->bfe_map = sc->bfe_rx_tmpmap;
591 sc->bfe_rx_tmpmap = map;
594 r->bfe_paddr = seg.ds_addr;
596 bfe_setup_rxdesc(sc, c);
601 bfe_setup_rxdesc(struct bfe_softc *sc, int c)
603 struct bfe_rxheader *rx_header;
609 KKASSERT(c >= 0 && c < BFE_RX_LIST_CNT);
610 r = &sc->bfe_rx_ring[c];
611 d = &sc->bfe_rx_list[c];
613 KKASSERT(r->bfe_mbuf != NULL && r->bfe_paddr != 0);
616 rx_header = mtod(m, struct bfe_rxheader *);
618 rx_header->flags = 0;
619 bus_dmamap_sync(sc->bfe_rxbuf_tag, r->bfe_map, BUS_DMASYNC_PREWRITE);
621 ctrl = ETHER_MAX_LEN + 32;
622 if (c == BFE_RX_LIST_CNT - 1)
623 ctrl |= BFE_DESC_EOT;
625 d->bfe_addr = r->bfe_paddr + BFE_PCI_DMA;
630 bfe_get_config(struct bfe_softc *sc)
634 bfe_read_eeprom(sc, eeprom);
636 sc->arpcom.ac_enaddr[0] = eeprom[79];
637 sc->arpcom.ac_enaddr[1] = eeprom[78];
638 sc->arpcom.ac_enaddr[2] = eeprom[81];
639 sc->arpcom.ac_enaddr[3] = eeprom[80];
640 sc->arpcom.ac_enaddr[4] = eeprom[83];
641 sc->arpcom.ac_enaddr[5] = eeprom[82];
643 sc->bfe_phyaddr = eeprom[90] & 0x1f;
644 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1;
646 sc->bfe_core_unit = 0;
647 sc->bfe_dma_offset = BFE_PCI_DMA;
651 bfe_pci_setup(struct bfe_softc *sc, uint32_t cores)
653 uint32_t bar_orig, pci_rev, val;
655 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
656 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
657 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK;
659 val = CSR_READ_4(sc, BFE_SBINTVEC);
661 CSR_WRITE_4(sc, BFE_SBINTVEC, val);
663 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
664 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
665 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
667 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
671 bfe_clear_stats(struct bfe_softc *sc)
675 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
676 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
678 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
683 bfe_resetphy(struct bfe_softc *sc)
687 bfe_writephy(sc, 0, BMCR_RESET);
689 bfe_readphy(sc, 0, &val);
690 if (val & BMCR_RESET) {
691 if_printf(&sc->arpcom.ac_if,
692 "PHY Reset would not complete.\n");
699 bfe_chip_halt(struct bfe_softc *sc)
701 /* disable interrupts - not that it actually does..*/
702 CSR_WRITE_4(sc, BFE_IMASK, 0);
703 CSR_READ_4(sc, BFE_IMASK);
705 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
706 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1);
708 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
709 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
714 bfe_chip_reset(struct bfe_softc *sc)
718 /* Set the interrupt vector for the enet core */
719 bfe_pci_setup(sc, BFE_INTVEC_ENET0);
722 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK);
723 if (val == BFE_CLOCK) {
724 /* It is, so shut it down */
725 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0);
726 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
727 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1);
728 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
729 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0;
730 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
731 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0);
732 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
740 * We want the phy registers to be accessible even when
741 * the driver is "downed" so initialize MDC preamble, frequency,
742 * and whether internal or external phy here.
745 /* 4402 has 62.5Mhz SB clock and internal phy */
746 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d);
748 /* Internal or external PHY? */
749 val = CSR_READ_4(sc, BFE_DEVCTRL);
750 if (!(val & BFE_IPP))
751 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL);
752 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {
753 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR);
757 /* Enable CRC32 generation and set proper LED modes */
758 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED);
760 /* Reset or clear powerdown control bit */
761 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN);
763 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
767 * We don't want lazy interrupts, so just send them at the end of a
770 BFE_OR(sc, BFE_RCV_LAZY, 0);
772 /* Set max lengths, accounting for VLAN tags */
773 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32);
774 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32);
776 /* Set watermark XXX - magic */
777 CSR_WRITE_4(sc, BFE_TX_WMARK, 56);
780 * Initialise DMA channels - not forgetting dma addresses need to be
781 * added to BFE_PCI_DMA
783 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
784 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA);
786 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
788 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA);
795 bfe_core_disable(struct bfe_softc *sc)
797 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
801 * Set reject, wait for it set, then wait for the core to stop being busy
802 * Then set reset and reject and enable the clocks
804 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
805 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0);
806 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1);
807 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT |
809 CSR_READ_4(sc, BFE_SBTMSLOW);
811 /* Leave reset and reject set */
812 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
817 bfe_core_reset(struct bfe_softc *sc)
821 /* Disable the core */
822 bfe_core_disable(sc);
824 /* and bring it back up */
825 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
826 CSR_READ_4(sc, BFE_SBTMSLOW);
829 /* Chip bug, clear SERR, IB and TO if they are set. */
830 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)
831 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);
832 val = CSR_READ_4(sc, BFE_SBIMSTATE);
833 if (val & (BFE_IBE | BFE_TO))
834 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
836 /* Clear reset and allow it to move through the core */
837 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
838 CSR_READ_4(sc, BFE_SBTMSLOW);
841 /* Leave the clock set */
842 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);
843 CSR_READ_4(sc, BFE_SBTMSLOW);
848 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
852 val = ((uint32_t) data[2]) << 24;
853 val |= ((uint32_t) data[3]) << 16;
854 val |= ((uint32_t) data[4]) << 8;
855 val |= ((uint32_t) data[5]);
856 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val);
857 val = (BFE_CAM_HI_VALID |
858 (((uint32_t) data[0]) << 8) |
859 (((uint32_t) data[1])));
860 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val);
861 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE |
862 ((uint32_t)index << BFE_CAM_INDEX_SHIFT)));
863 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1);
867 bfe_set_rx_mode(struct bfe_softc *sc)
869 struct ifnet *ifp = &sc->arpcom.ac_if;
870 struct ifmultiaddr *ifma;
874 val = CSR_READ_4(sc, BFE_RXCONF);
876 if (ifp->if_flags & IFF_PROMISC)
877 val |= BFE_RXCONF_PROMISC;
879 val &= ~BFE_RXCONF_PROMISC;
881 if (ifp->if_flags & IFF_BROADCAST)
882 val &= ~BFE_RXCONF_DBCAST;
884 val |= BFE_RXCONF_DBCAST;
887 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0);
888 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++);
890 if (ifp->if_flags & IFF_ALLMULTI) {
891 val |= BFE_RXCONF_ALLMULTI;
893 val &= ~BFE_RXCONF_ALLMULTI;
894 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
895 if (ifma->ifma_addr->sa_family != AF_LINK)
898 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++);
902 CSR_WRITE_4(sc, BFE_RXCONF, val);
903 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE);
907 bfe_dma_free(struct bfe_softc *sc)
911 if (sc->bfe_tx_tag != NULL) {
912 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map);
913 if (sc->bfe_tx_list != NULL) {
914 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list,
916 sc->bfe_tx_list = NULL;
918 bus_dma_tag_destroy(sc->bfe_tx_tag);
919 sc->bfe_tx_tag = NULL;
922 if (sc->bfe_rx_tag != NULL) {
923 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map);
924 if (sc->bfe_rx_list != NULL) {
925 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list,
927 sc->bfe_rx_list = NULL;
929 bus_dma_tag_destroy(sc->bfe_rx_tag);
930 sc->bfe_rx_tag = NULL;
933 if (sc->bfe_txbuf_tag != NULL) {
934 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
935 bus_dmamap_destroy(sc->bfe_txbuf_tag,
936 sc->bfe_tx_ring[i].bfe_map);
938 bus_dma_tag_destroy(sc->bfe_txbuf_tag);
939 sc->bfe_txbuf_tag = NULL;
942 if (sc->bfe_rxbuf_tag != NULL) {
943 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
944 bus_dmamap_destroy(sc->bfe_rxbuf_tag,
945 sc->bfe_rx_ring[i].bfe_map);
947 bus_dmamap_destroy(sc->bfe_rxbuf_tag, sc->bfe_rx_tmpmap);
948 bus_dma_tag_destroy(sc->bfe_rxbuf_tag);
949 sc->bfe_rxbuf_tag = NULL;
952 if (sc->bfe_parent_tag != NULL) {
953 bus_dma_tag_destroy(sc->bfe_parent_tag);
954 sc->bfe_parent_tag = NULL;
959 bfe_read_eeprom(struct bfe_softc *sc, uint8_t *data)
962 uint16_t *ptr = (uint16_t *)data;
964 for (i = 0; i < 128; i += 2)
965 ptr[i/2] = CSR_READ_4(sc, 4096 + i);
969 bfe_wait_bit(struct bfe_softc *sc, uint32_t reg, uint32_t bit,
970 u_long timeout, const int clear)
974 for (i = 0; i < timeout; i++) {
975 uint32_t val = CSR_READ_4(sc, reg);
977 if (clear && !(val & bit))
979 if (!clear && (val & bit))
984 if_printf(&sc->arpcom.ac_if,
985 "BUG! Timeout waiting for bit %08x of register "
986 "%x to %s.\n", bit, reg,
987 (clear ? "clear" : "set"));
994 bfe_readphy(struct bfe_softc *sc, uint32_t reg, uint32_t *val)
999 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1000 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1001 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) |
1002 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1003 (reg << BFE_MDIO_RA_SHIFT) |
1004 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT)));
1005 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1006 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;
1011 bfe_writephy(struct bfe_softc *sc, uint32_t reg, uint32_t val)
1015 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1016 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1017 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) |
1018 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1019 (reg << BFE_MDIO_RA_SHIFT) |
1020 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) |
1021 (val & BFE_MDIO_DATA_DATA)));
1022 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1028 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it
1032 bfe_setupphy(struct bfe_softc *sc)
1036 /* Enable activity LED */
1037 bfe_readphy(sc, 26, &val);
1038 bfe_writephy(sc, 26, val & 0x7fff);
1039 bfe_readphy(sc, 26, &val);
1041 /* Enable traffic meter LED mode */
1042 bfe_readphy(sc, 27, &val);
1043 bfe_writephy(sc, 27, val | (1 << 6));
1049 bfe_stats_update(struct bfe_softc *sc)
1054 val = &sc->bfe_hwstats.tx_good_octets;
1055 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
1056 *val++ += CSR_READ_4(sc, reg);
1057 val = &sc->bfe_hwstats.rx_good_octets;
1058 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
1059 *val++ += CSR_READ_4(sc, reg);
1063 bfe_txeof(struct bfe_softc *sc)
1065 struct ifnet *ifp = &sc->arpcom.ac_if;
1066 uint32_t i, chipidx;
1068 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;
1069 chipidx /= sizeof(struct bfe_desc);
1071 i = sc->bfe_tx_cons;
1073 /* Go through the mbufs and free those that have been transmitted */
1074 while (i != chipidx) {
1075 struct bfe_data *r = &sc->bfe_tx_ring[i];
1077 if (r->bfe_mbuf != NULL) {
1079 bus_dmamap_unload(sc->bfe_txbuf_tag, r->bfe_map);
1080 m_freem(r->bfe_mbuf);
1084 KKASSERT(sc->bfe_tx_cnt > 0);
1086 BFE_INC(i, BFE_TX_LIST_CNT);
1089 if (i != sc->bfe_tx_cons) {
1090 sc->bfe_tx_cons = i;
1092 if (sc->bfe_tx_cnt + BFE_SPARE_TXDESC < BFE_TX_LIST_CNT)
1093 ifq_clr_oactive(&ifp->if_snd);
1095 if (sc->bfe_tx_cnt == 0)
1099 /* Pass a received packet up the stack */
1101 bfe_rxeof(struct bfe_softc *sc)
1103 struct ifnet *ifp = &sc->arpcom.ac_if;
1105 struct bfe_rxheader *rxheader;
1107 uint32_t cons, status, current, len, flags;
1109 cons = sc->bfe_rx_cons;
1110 status = CSR_READ_4(sc, BFE_DMARX_STAT);
1111 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc);
1113 while (current != cons) {
1114 r = &sc->bfe_rx_ring[cons];
1115 bus_dmamap_sync(sc->bfe_rxbuf_tag, r->bfe_map,
1116 BUS_DMASYNC_POSTREAD);
1118 KKASSERT(r->bfe_mbuf != NULL);
1120 rxheader = mtod(m, struct bfe_rxheader*);
1121 len = rxheader->len - ETHER_CRC_LEN;
1122 flags = rxheader->flags;
1124 /* flag an error and try again */
1125 if (len > ETHER_MAX_LEN + 32 || (flags & BFE_RX_FLAG_ERRORS)) {
1127 if (flags & BFE_RX_FLAG_SERR)
1128 ifp->if_collisions++;
1130 bfe_setup_rxdesc(sc, cons);
1131 BFE_INC(cons, BFE_RX_LIST_CNT);
1135 /* Go past the rx header */
1136 if (bfe_newbuf(sc, cons, 0) != 0) {
1137 bfe_setup_rxdesc(sc, cons);
1139 BFE_INC(cons, BFE_RX_LIST_CNT);
1143 m_adj(m, BFE_RX_OFFSET);
1144 m->m_len = m->m_pkthdr.len = len;
1147 m->m_pkthdr.rcvif = ifp;
1149 ifp->if_input(ifp, m);
1150 BFE_INC(cons, BFE_RX_LIST_CNT);
1153 sc->bfe_rx_cons = cons;
1159 struct bfe_softc *sc = xsc;
1160 struct ifnet *ifp = &sc->arpcom.ac_if;
1161 uint32_t istat, imask, flag;
1163 istat = CSR_READ_4(sc, BFE_ISTAT);
1164 imask = CSR_READ_4(sc, BFE_IMASK);
1167 * Defer unsolicited interrupts - This is necessary because setting the
1168 * chips interrupt mask register to 0 doesn't actually stop the
1172 CSR_WRITE_4(sc, BFE_ISTAT, istat);
1173 CSR_READ_4(sc, BFE_ISTAT);
1175 /* not expecting this interrupt, disregard it */
1180 if (istat & BFE_ISTAT_ERRORS) {
1181 flag = CSR_READ_4(sc, BFE_DMATX_STAT);
1182 if (flag & BFE_STAT_EMASK)
1185 flag = CSR_READ_4(sc, BFE_DMARX_STAT);
1186 if (flag & BFE_RX_FLAG_ERRORS)
1189 ifp->if_flags &= ~IFF_RUNNING;
1193 /* A packet was received */
1194 if (istat & BFE_ISTAT_RX)
1197 /* A packet was sent */
1198 if (istat & BFE_ISTAT_TX)
1201 /* We have packets pending, fire them out */
1202 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd))
1207 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head, uint32_t *txidx)
1209 bus_dma_segment_t segs[BFE_MAXSEGS];
1211 int i, first_idx, last_idx, cur, error, maxsegs, nsegs;
1213 KKASSERT(sc->bfe_tx_cnt + BFE_SPARE_TXDESC < BFE_TX_LIST_CNT);
1214 maxsegs = BFE_TX_LIST_CNT - sc->bfe_tx_cnt - BFE_SPARE_TXDESC;
1215 if (maxsegs > BFE_MAXSEGS)
1216 maxsegs = BFE_MAXSEGS;
1219 map = sc->bfe_tx_ring[first_idx].bfe_map;
1221 error = bus_dmamap_load_mbuf_defrag(sc->bfe_txbuf_tag, map, m_head,
1222 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1225 bus_dmamap_sync(sc->bfe_txbuf_tag, map, BUS_DMASYNC_PREWRITE);
1229 for (i = 0; i < nsegs; ++i) {
1233 ctrl = BFE_DESC_LEN & segs[i].ds_len;
1234 ctrl |= BFE_DESC_IOC; /* always interrupt */
1235 if (cur == BFE_TX_LIST_CNT - 1) {
1237 * Tell the chip to wrap to the
1238 * start of the descriptor list.
1240 ctrl |= BFE_DESC_EOT;
1243 d = &sc->bfe_tx_list[cur];
1244 d->bfe_addr = segs[i].ds_addr + BFE_PCI_DMA;
1248 BFE_INC(cur, BFE_TX_LIST_CNT);
1250 KKASSERT(last_idx >= 0);
1252 /* End of the frame */
1253 sc->bfe_tx_list[last_idx].bfe_ctrl |= BFE_DESC_EOF;
1256 * Set start of the frame on the first fragment,
1257 * _after_ all of the fragments are setup.
1259 sc->bfe_tx_list[first_idx].bfe_ctrl |= BFE_DESC_SOF;
1261 sc->bfe_tx_ring[first_idx].bfe_map = sc->bfe_tx_ring[last_idx].bfe_map;
1262 sc->bfe_tx_ring[last_idx].bfe_map = map;
1263 sc->bfe_tx_ring[last_idx].bfe_mbuf = *m_head;
1266 sc->bfe_tx_cnt += nsegs;
1275 * Set up to transmit a packet
1278 bfe_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1280 struct bfe_softc *sc = ifp->if_softc;
1281 struct mbuf *m_head = NULL;
1282 int idx, need_trans;
1284 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
1285 ASSERT_SERIALIZED(ifp->if_serializer);
1288 * Not much point trying to send if the link is down
1289 * or we have nothing to send.
1291 if (!sc->bfe_link) {
1292 ifq_purge(&ifp->if_snd);
1296 if (ifq_is_oactive(&ifp->if_snd))
1299 idx = sc->bfe_tx_prod;
1302 while (!ifq_is_empty(&ifp->if_snd)) {
1303 if (sc->bfe_tx_cnt + BFE_SPARE_TXDESC >= BFE_TX_LIST_CNT) {
1304 ifq_set_oactive(&ifp->if_snd);
1308 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1313 * Pack the data into the tx ring. If we don't have
1314 * enough room, let the chip drain the ring.
1316 if (bfe_encap(sc, &m_head, &idx)) {
1317 /* m_head is freed by re_encap(), if we reach here */
1320 if (sc->bfe_tx_cnt > 0) {
1321 ifq_set_oactive(&ifp->if_snd);
1325 * ifq_set_oactive could not be called under
1326 * this situation, since except up/down,
1327 * nothing will call ifq_clr_oactive.
1329 * Let's just keep draining the ifq ...
1337 * If there's a BPF listener, bounce a copy of this frame
1340 BPF_MTAP(ifp, m_head);
1346 sc->bfe_tx_prod = idx;
1348 /* Transmit - twice due to apparent hardware bug */
1349 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1350 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1353 * Set a timeout in case the chip goes out to lunch.
1361 struct bfe_softc *sc = (struct bfe_softc*)xsc;
1362 struct ifnet *ifp = &sc->arpcom.ac_if;
1364 ASSERT_SERIALIZED(ifp->if_serializer);
1366 if (ifp->if_flags & IFF_RUNNING)
1372 if (bfe_list_rx_init(sc) == ENOBUFS) {
1373 if_printf(ifp, "bfe_init failed. "
1374 " Not enough memory for list buffers\n");
1379 bfe_set_rx_mode(sc);
1381 /* Enable the chip and core */
1382 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE);
1383 /* Enable interrupts */
1384 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF);
1386 bfe_ifmedia_upd(ifp);
1387 ifp->if_flags |= IFF_RUNNING;
1388 ifq_clr_oactive(&ifp->if_snd);
1390 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc);
1394 * Set media options.
1397 bfe_ifmedia_upd(struct ifnet *ifp)
1399 struct bfe_softc *sc = ifp->if_softc;
1400 struct mii_data *mii;
1402 ASSERT_SERIALIZED(ifp->if_serializer);
1404 mii = device_get_softc(sc->bfe_miibus);
1406 if (mii->mii_instance) {
1407 struct mii_softc *miisc;
1408 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1409 miisc = LIST_NEXT(miisc, mii_list))
1410 mii_phy_reset(miisc);
1420 * Report current media status.
1423 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1425 struct bfe_softc *sc = ifp->if_softc;
1426 struct mii_data *mii;
1428 ASSERT_SERIALIZED(ifp->if_serializer);
1430 mii = device_get_softc(sc->bfe_miibus);
1432 ifmr->ifm_active = mii->mii_media_active;
1433 ifmr->ifm_status = mii->mii_media_status;
1437 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1439 struct bfe_softc *sc = ifp->if_softc;
1440 struct ifreq *ifr = (struct ifreq *) data;
1441 struct mii_data *mii;
1444 ASSERT_SERIALIZED(ifp->if_serializer);
1448 if (ifp->if_flags & IFF_UP)
1449 if (ifp->if_flags & IFF_RUNNING)
1450 bfe_set_rx_mode(sc);
1453 else if (ifp->if_flags & IFF_RUNNING)
1458 if (ifp->if_flags & IFF_RUNNING)
1459 bfe_set_rx_mode(sc);
1463 mii = device_get_softc(sc->bfe_miibus);
1464 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
1468 error = ether_ioctl(ifp, command, data);
1475 bfe_watchdog(struct ifnet *ifp)
1477 struct bfe_softc *sc = ifp->if_softc;
1479 ASSERT_SERIALIZED(ifp->if_serializer);
1481 if_printf(ifp, "watchdog timeout -- resetting\n");
1483 ifp->if_flags &= ~IFF_RUNNING;
1492 struct bfe_softc *sc = xsc;
1493 struct mii_data *mii;
1494 struct ifnet *ifp = &sc->arpcom.ac_if;
1496 mii = device_get_softc(sc->bfe_miibus);
1498 lwkt_serialize_enter(ifp->if_serializer);
1500 bfe_stats_update(sc);
1501 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc);
1503 if (sc->bfe_link == 0) {
1505 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE &&
1506 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1512 lwkt_serialize_exit(ifp->if_serializer);
1516 * Stop the adapter and free any mbufs allocated to the
1520 bfe_stop(struct bfe_softc *sc)
1522 struct ifnet *ifp = &sc->arpcom.ac_if;
1524 ASSERT_SERIALIZED(ifp->if_serializer);
1526 callout_stop(&sc->bfe_stat_timer);
1529 bfe_tx_ring_free(sc);
1530 bfe_rx_ring_free(sc);
1532 ifp->if_flags &= ~IFF_RUNNING;
1533 ifq_clr_oactive(&ifp->if_snd);