2 * Copyright (c) 1995 HD Associates, Inc.
7 * Pepperell, MA 01463-0276
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11 * modification, are permitted provided that the following conditions
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19 * must display the following acknowledgement:
20 * This product includes software developed by HD Associates, Inc.
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22 * may not be used to endorse or promote products derived from this software
23 * without specific prior written permission.
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41 * $FreeBSD: src/sys/i386/isa/labpc.c,v 1.35 1999/09/25 18:24:08 phk Exp $
45 #include "use_labpc.h"
46 #include "opt_debug_outb.h"
47 #include <sys/param.h>
49 #include <sys/systm.h>
51 #include <sys/kernel.h>
52 #include <sys/malloc.h>
54 #define bio_actf bio_act.tqe_next
55 #include <sys/dataacq.h>
57 #include <sys/thread2.h>
60 #include <machine/clock.h>
63 #include <bus/isa/isa_device.h>
70 #define LABPC_MIN_TMO (hz)
73 #ifndef LABPC_DEFAULT_HERTZ
74 #define LABPC_DEFAULT_HERTZ 500
80 * S: SCAN bit for scan enable.
81 * I: INTERVAL for interval support
82 * D: 1: Digital I/O, 0: Analog I/O
85 * input: channel must be 0 to 7.
86 * output: channel must be 0 to 2
89 * 2: Alternate channel 0 then 1
92 * input: Channel must be 0 to 2.
93 * output: Channel must be 0 to 2.
99 #define UNIT(dev) (((minor(dev) & 0xB0) >> 6) & 0x3)
101 #define SCAN(dev) ((minor(dev) & 0x20) >> 5)
102 #define INTERVAL(dev) ((minor(dev) & 0x10) >> 4)
103 #define DIGITAL(dev) ((minor(dev) & 0x08) >> 3)
108 #define CHAN(dev) (minor(dev) & 0x7)
110 /* History: Derived from "dt2811.c" March 1995
116 #define DROPPED_INPUT 0x100
120 #define BUSY 0x00000001
126 struct bio start_queue; /* Start queue */
127 struct bio *last; /* End of start queue */
131 long tmo; /* Timeout in Hertz */
132 long min_tmo; /* Timeout in Hertz */
137 cdev_t dev; /* Copy of device */
139 void (*starter)(struct ctlr *ctlr, long count);
140 void (*stop)(struct ctlr *ctlr);
141 void (*intr)(struct ctlr *ctlr);
143 /* Digital I/O support. Copy of Data Control Register for 8255:
145 u_char dcr_val, dcr_is;
148 * Handle for canceling our timeout.
152 /* Device configuration structure:
157 /* loutb is a slow outb for debugging. The overrun test may fail
158 * with this for some slower processors.
161 loutb(int port, u_char val)
167 #define loutb(port, val) outb(port, val)
170 static struct ctlr **labpcs; /* XXX: Should be dynamic */
172 /* CR_EXPR: A macro that sets the shadow register in addition to
173 * sending out the data.
175 #define CR_EXPR(LABPC, CR, EXPR) do { \
176 (LABPC)->cr_image[CR - 1] EXPR ; \
177 loutb(((LABPC)->base + ( (CR == 4) ? (0x0F) : (CR - 1))), ((LABPC)->cr_image[(CR - 1)])); \
180 #define CR_CLR(LABPC, CR) CR_EXPR(LABPC, CR, &=0)
181 #define CR_REFRESH(LABPC, CR) CR_EXPR(LABPC, CR, &=0xff)
182 #define CR_SET(LABPC, CR, EXPR) CR_EXPR(LABPC, CR, = EXPR)
184 /* Configuration and Status Register Group.
186 #define CR1(LABPC) ((LABPC)->base + 0x00) /* Page 4-5 */
188 #define GAINMASK 0x70
189 #define GAIN(LABPC, SEL) do { \
190 (LABPC)->cr_image[1 - 1] &= ~GAINMASK; \
191 (LABPC)->cr_image[1 - 1] |= (SEL << 4); \
192 loutb((LABPC)->base + (1 - 1), (LABPC)->cr_image[(1 - 1)]); \
197 #define MA(LABPC, SEL) do { \
198 (LABPC)->cr_image[1 - 1] &= ~MAMASK; \
199 (LABPC)->cr_image[1 - 1] |= SEL; \
200 loutb((LABPC)->base + (1 - 1), (LABPC)->cr_image[(1 - 1)]); \
203 #define STATUS(LABPC) ((LABPC)->base + 0x00) /* Page 4-7 */
204 #define LABPCPLUS 0x80
205 #define EXTGATA0 0x40
209 #define OVERFLOW 0x04
213 #define CR2(LABPC) ((LABPC)->base + 0x01) /* Page 4-9 */
222 #define SWTRIGGERRED(LABPC) ((LABPC->cr_image[1]) & SWTRIG)
224 #define CR3(LABPC) ((LABPC)->base + 0x02) /* Page 4-11 */
225 #define FIFOINTEN 0x20
226 #define ERRINTEN 0x10
227 #define CNTINTEN 0x08
229 #define DIOINTEN 0x02
232 #define ALLINTEN 0x3E
233 #define FIFOINTENABLED(LABPC) ((LABPC->cr_image[2]) & FIFOINTEN)
235 #define CR4(LABPC) ((LABPC)->base + 0x0F) /* Page 4-13 */
242 /* Analog Input Register Group
244 #define ADFIFO(LABPC) ((LABPC)->base + 0x0A) /* Page 4-16 */
245 #define ADCLEAR(LABPC) ((LABPC)->base + 0x08) /* Page 4-18 */
246 #define ADSTART(LABPC) ((LABPC)->base + 0x03) /* Page 4-19 */
247 #define DMATCICLR(LABPC) ((LABPC)->base + 0x0A) /* Page 4-20 */
249 /* Analog Output Register Group
251 #define DAC0L(LABPC) ((LABPC)->base + 0x04) /* Page 4-22 */
252 #define DAC0H(LABPC) ((LABPC)->base + 0x05) /* Page 4-22 */
253 #define DAC1L(LABPC) ((LABPC)->base + 0x06) /* Page 4-22 */
254 #define DAC1H(LABPC) ((LABPC)->base + 0x07) /* Page 4-22 */
258 #define A0DATA(LABPC) ((LABPC)->base + 0x14)
259 #define A1DATA(LABPC) ((LABPC)->base + 0x15)
260 #define A2DATA(LABPC) ((LABPC)->base + 0x16)
261 #define AMODE(LABPC) ((LABPC)->base + 0x17)
263 #define TICR(LABPC) ((LABPC)->base + 0x0c)
265 #define B0DATA(LABPC) ((LABPC)->base + 0x18)
266 #define B1DATA(LABPC) ((LABPC)->base + 0x19)
267 #define B2DATA(LABPC) ((LABPC)->base + 0x1A)
268 #define BMODE(LABPC) ((LABPC)->base + 0x1B)
273 #define PORTX(LABPC, X) ((LABPC)->base + 0x10 + X)
275 #define PORTA(LABPC) PORTX(LABPC, 0)
276 #define PORTB(LABPC) PORTX(LABPC, 1)
277 #define PORTC(LABPC) PORTX(LABPC, 2)
279 #define DCR(LABPC) ((LABPC)->base + 0x13)
281 static int labpcattach(struct isa_device *dev);
282 static int labpcprobe(struct isa_device *dev);
283 struct isa_driver labpcdriver =
284 { labpcprobe, labpcattach, "labpc", 0 };
286 static d_open_t labpcopen;
287 static d_close_t labpcclose;
288 static d_ioctl_t labpcioctl;
289 static d_strategy_t labpcstrategy;
291 static struct dev_ops labpc_ops = {
294 .d_close = labpcclose,
296 .d_write = physwrite,
297 .d_ioctl = labpcioctl,
298 .d_strategy = labpcstrategy,
301 static void labpcintr(void *);
302 static void start(struct ctlr *ctlr);
305 bp_done(struct bio *bio, int err)
307 struct buf *bp = bio->bio_buf;
309 if (err || bp->b_resid)
310 bp->b_flags |= B_ERROR;
314 static void tmo_stop(void *p);
317 done_and_start_next(struct ctlr *ctlr, struct bio *bio, int err)
319 struct buf *bp = bio->bio_buf;
321 bp->b_resid = ctlr->data_end - ctlr->data;
325 ctlr->start_queue.bio_actf = bio->bio_actf;
328 callout_stop(&ctlr->ch);
334 ad_clear(struct ctlr *ctlr)
337 loutb(ADCLEAR(ctlr), 0);
338 for (i = 0; i < 10000 && (inb(STATUS(ctlr)) & GATA0); i++)
340 (void)inb(ADFIFO(ctlr));
341 (void)inb(ADFIFO(ctlr));
344 /* reset: Reset the board following the sequence on page 5-1
347 reset(struct ctlr *ctlr)
350 CR_CLR(ctlr, 3); /* Turn off interrupts first */
357 loutb(AMODE(ctlr), 0x34);
358 loutb(A0DATA(ctlr),0x0A);
359 loutb(A0DATA(ctlr),0x00);
361 loutb(DMATCICLR(ctlr), 0x00);
362 loutb(TICR(ctlr), 0x00);
366 loutb(DAC0L(ctlr), 0);
367 loutb(DAC0H(ctlr), 0);
368 loutb(DAC1L(ctlr), 0);
369 loutb(DAC1H(ctlr), 0);
374 /* overrun: slam the start convert register and OVERRUN should get set:
377 overrun(struct ctlr *ctlr)
381 u_char status = inb(STATUS(ctlr));
382 for (i = 0; ((status & OVERRUN) == 0) && i < 100; i++)
384 loutb(ADSTART(ctlr), 1);
385 status = inb(STATUS(ctlr));
394 if (NLABPC > MAX_UNITS)
397 labpcs = kmalloc(NLABPC * sizeof(struct ctlr *), M_DEVBUF,
403 labpcprobe(struct isa_device *dev)
406 struct ctlr scratch, *ctlr, *l;
411 if (labpcinit() == 0)
413 kprintf("labpcprobe: init failed\n");
420 kprintf("Too many LAB-PCs. Reconfigure O/S.\n");
423 ctlr = &scratch; /* Need somebody with the right base for the macros */
424 ctlr->base = dev->id_iobase;
426 /* XXX: There really isn't a perfect way to probe this board.
427 * Here is my best attempt:
431 /* After reset none of these bits should be set:
433 status = inb(STATUS(ctlr));
434 if (status & (GATA0 | OVERFLOW | DAVAIL | OVERRUN))
437 /* Now try to overrun the board FIFO and get the overrun bit set:
439 status = overrun(ctlr);
441 if ((status & OVERRUN) == 0) /* No overrun bit set? */
444 /* Assume we have a board.
448 l = kmalloc(sizeof(struct ctlr), M_DEVBUF, M_WAITOK | M_ZERO);
449 l->base = ctlr->base;
452 dev->id_unit = l->unit;
458 /* attach: Set things in a normal state.
461 labpcattach(struct isa_device *dev)
463 struct ctlr *ctlr = labpcs[dev->id_unit];
465 dev->id_intr = (inthand2_t *)labpcintr;
466 callout_init(&ctlr->ch);
467 ctlr->sample_us = (1000000.0 / (double)LABPC_DEFAULT_HERTZ) + .50;
470 ctlr->min_tmo = LABPC_MIN_TMO;
472 ctlr->dcr_val = 0x80;
474 loutb(DCR(ctlr), ctlr->dcr_val);
476 make_dev(&labpc_ops, dev->id_unit, 0, 0, 0600,
477 "labpc%d", dev->id_unit);
483 static void null_intr (struct ctlr *ctlr) { }
484 static void null_start(struct ctlr *ctlr, long count) { }
485 static void null_stop (struct ctlr *ctlr) { }
488 trigger(struct ctlr *ctlr)
490 CR_EXPR(ctlr, 2, |= SWTRIG);
494 ad_start(struct ctlr *ctlr, long count)
496 if (!SWTRIGGERRED(ctlr)) {
497 int chan = CHAN(ctlr->dev);
498 CR_EXPR(ctlr, 1, &= ~SCANEN);
499 CR_EXPR(ctlr, 2, &= ~TBSEL);
502 GAIN(ctlr, ctlr->gains[chan]);
505 CR_EXPR(ctlr, 1, |= SCANEN);
507 loutb(AMODE(ctlr), 0x34);
508 loutb(A0DATA(ctlr), (u_char)((ctlr->sample_us & 0xff)));
509 loutb(A0DATA(ctlr), (u_char)((ctlr->sample_us >> 8)&0xff));
510 loutb(AMODE(ctlr), 0x70);
516 ctlr->tmo = ((count + 16) * (long)ctlr->sample_us * hz) / 1000000 +
521 ad_interval_start(struct ctlr *ctlr, long count)
523 int chan = CHAN(ctlr->dev);
524 int n_frames = count / (chan + 1);
526 if (!SWTRIGGERRED(ctlr)) {
527 CR_EXPR(ctlr, 1, &= ~SCANEN);
528 CR_EXPR(ctlr, 2, &= ~TBSEL);
531 GAIN(ctlr, ctlr->gains[chan]);
533 /* XXX: Is it really possible that you clear INTSCAN as
534 * the documentation says? That seems pretty unlikely.
536 CR_EXPR(ctlr, 4, &= ~INTSCAN); /* XXX: Is this possible? */
538 /* Program the sample interval counter to run as fast as
541 loutb(AMODE(ctlr), 0x34);
542 loutb(A0DATA(ctlr), (u_char)(0x02));
543 loutb(A0DATA(ctlr), (u_char)(0x00));
544 loutb(AMODE(ctlr), 0x70);
546 /* Program the interval scanning counter to run at the sample
549 loutb(BMODE(ctlr), 0x74);
550 loutb(B1DATA(ctlr), (u_char)((ctlr->sample_us & 0xff)));
551 loutb(B1DATA(ctlr), (u_char)((ctlr->sample_us >> 8)&0xff));
552 CR_EXPR(ctlr, 1, |= SCANEN);
558 /* Each frame time takes two microseconds per channel times
559 * the number of channels being sampled plus the sample period.
561 ctlr->tmo = ((n_frames + 16) *
562 ((long)ctlr->sample_us + (chan + 1 ) * 2 ) * hz) / 1000000 +
567 all_stop(struct ctlr *ctlr)
575 struct ctlr *ctlr = (struct ctlr *)p;
582 kprintf("labpc?: Null ctlr struct?\n");
587 kprintf("labpc%d: timeout", ctlr->unit);
591 bio = ctlr->start_queue.bio_actf;
594 kprintf(", Null bp.\n");
601 done_and_start_next(ctlr, bio, ETIMEDOUT);
606 static void ad_intr(struct ctlr *ctlr)
610 if (ctlr->cr_image[2] == 0)
612 if (ctlr->cleared_intr)
614 ctlr->cleared_intr = 0;
618 kprintf("ad_intr (should not happen) interrupt with interrupts off\n");
619 kprintf("status %x, cr3 %x\n", inb(STATUS(ctlr)), ctlr->cr_image[2]);
623 while ( (status = (inb(STATUS(ctlr)) & (DAVAIL|OVERRUN|OVERFLOW)) ) )
625 if ((status & (OVERRUN|OVERFLOW)))
627 struct bio *bio = ctlr->start_queue.bio_actf;
629 kprintf("ad_intr: error: bp %p, data %p, status %x",
630 bio->bio_buf, ctlr->data, status);
632 if (status & OVERRUN)
633 kprintf(" Conversion overrun (multiple A-D trigger)");
635 if (status & OVERFLOW)
636 kprintf(" FIFO overflow");
641 done_and_start_next(ctlr, bio, EIO);
644 kprintf("ad_intr: (should not happen) error between records\n");
645 ctlr->err = status; /* Set overrun condition */
649 else /* FIFO interrupt */
651 struct bio *bio = ctlr->start_queue.bio_actf;
654 *ctlr->data++ = inb(ADFIFO(ctlr));
655 if (ctlr->data == ctlr->data_end) {
656 /* Normal completion */
657 done_and_start_next(ctlr, bio, 0);
661 /* Interrupt with no where to put the data. */
662 kprintf("ad_intr: (should not happen) dropped input.\n");
663 (void)inb(ADFIFO(ctlr));
665 kprintf("bp %p, status %x, cr3 %x\n",
666 bio->bio_buf, status, ctlr->cr_image[2]);
667 ctlr->err = DROPPED_INPUT;
678 struct ctlr *ctlr = labpcs[unit];
682 /* lockout_multiple_opens: Return whether or not we can open again, or
683 * if the new mode is inconsistent with an already opened mode.
684 * We only permit multiple opens for digital I/O now.
688 lockout_multiple_open(cdev_t current, cdev_t next)
690 return ! (DIGITAL(current) && DIGITAL(next));
694 labpcopen(struct dev_open_args *ap)
696 cdev_t dev = ap->a_head.a_dev;
697 u_short unit = UNIT(dev);
701 if (unit >= MAX_UNITS)
709 /* Don't allow another open if we have to change modes.
712 if ( (ctlr->flags & BUSY) == 0)
721 ctlr->intr = null_intr;
722 ctlr->starter = null_start;
723 ctlr->stop = null_stop;
725 else if (lockout_multiple_open(ctlr->dev, dev))
732 labpcclose(struct dev_close_args *ap)
734 cdev_t dev = ap->a_head.a_dev;
735 struct ctlr *ctlr = labpcs[UNIT(dev)];
739 ctlr->flags &= ~BUSY;
745 * Start: Start a frame going in or out.
748 start(struct ctlr *ctlr)
753 if ((bio = ctlr->start_queue.bio_actf) == NULL) {
754 /* We must turn off FIFO interrupts when there is no
755 * place to put the data. We have to get back to
756 * reading before the FIFO overflows.
758 CR_EXPR(ctlr, 3, &= ~(FIFOINTEN|ERRINTEN));
759 ctlr->cleared_intr = 1;
765 ctlr->data = (u_char *)bp->b_data;
766 ctlr->data_end = ctlr->data + bp->b_bcount;
770 kprintf("labpc start: (should not happen) error between records.\n");
771 done_and_start_next(ctlr, bio, EIO);
777 kprintf("labpc start: (should not happen) NULL data pointer.\n");
778 done_and_start_next(ctlr, bio, EIO);
782 (*ctlr->starter)(ctlr, bp->b_bcount);
784 if (!FIFOINTENABLED(ctlr)) /* We can store the data again */
786 CR_EXPR(ctlr, 3, |= (FIFOINTEN|ERRINTEN));
788 /* Don't wait for the interrupts to fill things up.
793 callout_reset(&ctlr->ch, ctlr->tmo, tmo_stop, ctlr);
797 ad_strategy(struct bio *bio, struct ctlr *ctlr)
800 bio->bio_actf = NULL;
803 ctlr->last->bio_actf = bio;
807 ctlr->start_queue.bio_actf = bio;
814 /* da_strategy: Send data to the D-A. The CHAN field should be
817 * 2: Alternate port 0 then port 1
821 * 1. There is no state for CHAN field 2:
822 * the first sample in each buffer goes to channel 0.
824 * 2. No interrupt support yet.
827 da_strategy(struct bio *bio, struct ctlr *ctlr)
829 struct buf *bp = bio->bio_buf;
830 cdev_t dev = bio->bio_driver_info;
846 case 2: /* Device 2 handles both ports interleaved. */
847 if (bp->b_bcount <= 2)
853 len = bp->b_bcount / 2;
854 data = (u_char *)bp->b_data;
856 for (i = 0; i < len; i++)
858 loutb(DAC0H(ctlr), *data++);
859 loutb(DAC0L(ctlr), *data++);
860 loutb(DAC1H(ctlr), *data++);
861 loutb(DAC1L(ctlr), *data++);
864 bp->b_resid = bp->b_bcount & 3;
873 /* Port 0 or 1 falls through to here.
875 if (bp->b_bcount & 1) /* Odd transfers are illegal */
879 data = (u_char *)bp->b_data;
881 for (i = 0; i < len; i++)
883 loutb(port + 1, *data++);
884 loutb(port, *data++);
892 /* Input masks for MODE 0 of the ports treating PC as a single
893 * 8 bit port. Set these bits to set the port to input.
895 /* A B lowc highc combined */
896 static u_char set_input[] = { 0x10, 0x02, 0x01, 0x08, 0x09 };
898 static void flush_dcr(struct ctlr *ctlr)
900 if (ctlr->dcr_is != ctlr->dcr_val)
902 loutb(DCR(ctlr), ctlr->dcr_val);
903 ctlr->dcr_is = ctlr->dcr_val;
907 /* do: Digital output
910 digital_out_strategy(struct bio *bio, struct ctlr *ctlr)
912 struct buf *bp = bio->bio_buf;
913 cdev_t dev = bio->bio_driver_info;
918 int chan = CHAN(dev);
920 ctlr->dcr_val &= ~set_input[chan]; /* Digital out: Clear bit */
923 port = PORTX(ctlr, chan);
926 data = (u_char *)bp->b_data;
928 for (i = 0; i < len; i++)
930 loutb(port, *data++);
938 /* digital_in_strategy: Digital input
941 digital_in_strategy(struct bio *bio, struct ctlr *ctlr)
943 struct buf *bp = bio->bio_buf;
944 cdev_t dev = bio->bio_driver_info;
949 int chan = CHAN(dev);
951 ctlr->dcr_val |= set_input[chan]; /* Digital in: Set bit */
953 port = PORTX(ctlr, chan);
956 data = (u_char *)bp->b_data;
958 for (i = 0; i < len; i++)
970 labpcstrategy(struct dev_strategy_args *ap)
972 cdev_t dev = ap->a_head.a_dev;
973 struct bio *bio = ap->a_bio;
974 struct buf *bp = bio->bio_buf;
975 struct ctlr *ctlr = labpcs[UNIT(dev)];
977 bio->bio_driver_info = dev;
980 if (bp->b_cmd == BUF_CMD_READ) {
981 ctlr->starter = null_start;
982 ctlr->stop = all_stop;
983 ctlr->intr = null_intr;
984 digital_in_strategy(bio, ctlr);
988 ctlr->starter = null_start;
989 ctlr->stop = all_stop;
990 ctlr->intr = null_intr;
991 digital_out_strategy(bio, ctlr);
995 if (bp->b_cmd == BUF_CMD_READ) {
997 ctlr->starter = INTERVAL(ctlr->dev) ? ad_interval_start : ad_start;
998 ctlr->stop = all_stop;
999 ctlr->intr = ad_intr;
1000 ad_strategy(bio, ctlr);
1004 ctlr->starter = null_start;
1005 ctlr->stop = all_stop;
1006 ctlr->intr = null_intr;
1007 da_strategy(bio, ctlr);
1014 labpcioctl(struct dev_ioctl_args *ap)
1016 cdev_t dev = ap->a_head.a_dev;
1017 caddr_t arg = ap->a_data;
1018 struct ctlr *ctlr = labpcs[UNIT(dev)];
1022 case AD_MICRO_PERIOD_SET:
1024 /* XXX I'm only supporting what I have to, which is
1025 * no slow periods. You can't get any slower than 15 Hz
1026 * with the current setup. To go slower you'll need to
1027 * support TCINTEN in CR3.
1030 long sample_us = *(long *)arg;
1032 if (sample_us > 65535)
1035 ctlr->sample_us = sample_us;
1039 case AD_MICRO_PERIOD_GET:
1040 *(long *)arg = ctlr->sample_us;
1051 case AD_SUPPORTED_GAINS:
1053 static double gains[] = {1., 1.25, 2., 5., 10., 20., 50., 100.};
1054 copyout(gains, *(caddr_t *)arg, sizeof(gains));
1061 copyin(*(caddr_t *)arg, ctlr->gains, sizeof(ctlr->gains));
1067 copyout(ctlr->gains, *(caddr_t *)arg, sizeof(ctlr->gains));