sys/dev/netif/bce/if_bce.c

   1 /*-
   2  * Copyright (c) 2006-2007 Broadcom Corporation
   3  *      David Christensen <davidch@broadcom.com>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the name of Broadcom Corporation nor the name of its contributors
  15  *    may be used to endorse or promote products derived from this software
  16  *    without specific prior written consent.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
  19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
  22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  28  * THE POSSIBILITY OF SUCH DAMAGE.
  29  *
  30  * $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $
  31  */
  32
  33 /*
  34  * The following controllers are supported by this driver:
  35  *   BCM5706C A2, A3
  36  *   BCM5706S A2, A3
  37  *   BCM5708C B1, B2
  38  *   BCM5708S B1, B2
  39  *   BCM5709C A1, C0
  40  *   BCM5716  C0
  41  *
  42  * The following controllers are not supported by this driver:
  43  *   BCM5706C A0, A1
  44  *   BCM5706S A0, A1
  45  *   BCM5708C A0, B0
  46  *   BCM5708S A0, B0
  47  *   BCM5709C A0, B0, B1
  48  *   BCM5709S A0, A1, B0, B1, B2, C0
  49  */
  50
  51 #include "opt_bce.h"
  52 #include "opt_polling.h"
  53
  54 #include <sys/param.h>
  55 #include <sys/bus.h>
  56 #include <sys/endian.h>
  57 #include <sys/kernel.h>
  58 #include <sys/interrupt.h>
  59 #include <sys/mbuf.h>
  60 #include <sys/malloc.h>
  61 #include <sys/queue.h>
  62 #ifdef BCE_DEBUG
  63 #include <sys/random.h>
  64 #endif
  65 #include <sys/rman.h>
  66 #include <sys/serialize.h>
  67 #include <sys/socket.h>
  68 #include <sys/sockio.h>
  69 #include <sys/sysctl.h>
  70
  71 #include <net/bpf.h>
  72 #include <net/ethernet.h>
  73 #include <net/if.h>
  74 #include <net/if_arp.h>
  75 #include <net/if_dl.h>
  76 #include <net/if_media.h>
  77 #include <net/if_types.h>
  78 #include <net/ifq_var.h>
  79 #include <net/vlan/if_vlan_var.h>
  80 #include <net/vlan/if_vlan_ether.h>
  81
  82 #include <dev/netif/mii_layer/mii.h>
  83 #include <dev/netif/mii_layer/miivar.h>
  84 #include <dev/netif/mii_layer/brgphyreg.h>
  85
  86 #include <bus/pci/pcireg.h>
  87 #include <bus/pci/pcivar.h>
  88
  89 #include "miibus_if.h"
  90
  91 #include <dev/netif/bce/if_bcereg.h>
  92 #include <dev/netif/bce/if_bcefw.h>
  93
  94 /****************************************************************************/
  95 /* BCE Debug Options                                                        */
  96 /****************************************************************************/
  97 #ifdef BCE_DEBUG
  98
  99 static uint32_t bce_debug = BCE_WARN;
 100
 101 /*
 102  *          0 = Never
 103  *          1 = 1 in 2,147,483,648
 104  *        256 = 1 in     8,388,608
 105  *       2048 = 1 in     1,048,576
 106  *      65536 = 1 in        32,768
 107  *    1048576 = 1 in         2,048
 108  *  268435456 = 1 in             8
 109  *  536870912 = 1 in             4
 110  * 1073741824 = 1 in             2
 111  *
 112  * bce_debug_l2fhdr_status_check:
 113  *     How often the l2_fhdr frame error check will fail.
 114  *
 115  * bce_debug_unexpected_attention:
 116  *     How often the unexpected attention check will fail.
 117  *
 118  * bce_debug_mbuf_allocation_failure:
 119  *     How often to simulate an mbuf allocation failure.
 120  *
 121  * bce_debug_dma_map_addr_failure:
 122  *     How often to simulate a DMA mapping failure.
 123  *
 124  * bce_debug_bootcode_running_failure:
 125  *     How often to simulate a bootcode failure.
 126  */
 127 static int      bce_debug_l2fhdr_status_check = 0;
 128 static int      bce_debug_unexpected_attention = 0;
 129 static int      bce_debug_mbuf_allocation_failure = 0;
 130 static int      bce_debug_dma_map_addr_failure = 0;
 131 static int      bce_debug_bootcode_running_failure = 0;
 132
 133 #endif  /* BCE_DEBUG */
 134
 135
 136 /****************************************************************************/
 137 /* PCI Device ID Table                                                      */
 138 /*                                                                          */
 139 /* Used by bce_probe() to identify the devices supported by this driver.    */
 140 /****************************************************************************/
 141 #define BCE_DEVDESC_MAX         64
 142
 143 static struct bce_type bce_devs[] = {
 144         /* BCM5706C Controllers and OEM boards. */
 145         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3101,
 146                 "HP NC370T Multifunction Gigabit Server Adapter" },
 147         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3106,
 148                 "HP NC370i Multifunction Gigabit Server Adapter" },
 149         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3070,
 150                 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
 151         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x1709,
 152                 "HP NC371i Multifunction Gigabit Server Adapter" },
 153         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  PCI_ANY_ID,  PCI_ANY_ID,
 154                 "Broadcom NetXtreme II BCM5706 1000Base-T" },
 155
 156         /* BCM5706S controllers and OEM boards. */
 157         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
 158                 "HP NC370F Multifunction Gigabit Server Adapter" },
 159         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID,  PCI_ANY_ID,
 160                 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
 161
 162         /* BCM5708C controllers and OEM boards. */
 163         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7037,
 164                 "HP NC373T PCIe Multifunction Gig Server Adapter" },
 165         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7038,
 166                 "HP NC373i Multifunction Gigabit Server Adapter" },
 167         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7045,
 168                 "HP NC374m PCIe Multifunction Adapter" },
 169         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  PCI_ANY_ID,  PCI_ANY_ID,
 170                 "Broadcom NetXtreme II BCM5708 1000Base-T" },
 171
 172         /* BCM5708S controllers and OEM boards. */
 173         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x1706,
 174                 "HP NC373m Multifunction Gigabit Server Adapter" },
 175         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703b,
 176                 "HP NC373i Multifunction Gigabit Server Adapter" },
 177         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703d,
 178                 "HP NC373F PCIe Multifunc Giga Server Adapter" },
 179         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  PCI_ANY_ID,  PCI_ANY_ID,
 180                 "Broadcom NetXtreme II BCM5708S 1000Base-T" },
 181
 182         /* BCM5709C controllers and OEM boards. */
 183         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7055,
 184                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 185         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7059,
 186                 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
 187         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  PCI_ANY_ID,  PCI_ANY_ID,
 188                 "Broadcom NetXtreme II BCM5709 1000Base-T" },
 189
 190         /* BCM5709S controllers and OEM boards. */
 191         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x171d,
 192                 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
 193         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x7056,
 194                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 195         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  PCI_ANY_ID,  PCI_ANY_ID,
 196                 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
 197
 198         /* BCM5716 controllers and OEM boards. */
 199         { BRCM_VENDORID, BRCM_DEVICEID_BCM5716,   PCI_ANY_ID,  PCI_ANY_ID,
 200                 "Broadcom NetXtreme II BCM5716 1000Base-T" },
 201
 202         { 0, 0, 0, 0, NULL }
 203 };
 204
 205
 206 /****************************************************************************/
 207 /* Supported Flash NVRAM device data.                                       */
 208 /****************************************************************************/
 209 static const struct flash_spec flash_table[] =
 210 {
 211 #define BUFFERED_FLAGS          (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
 212 #define NONBUFFERED_FLAGS       (BCE_NV_WREN)
 213
 214         /* Slow EEPROM */
 215         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 216          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 217          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 218          "EEPROM - slow"},
 219         /* Expansion entry 0001 */
 220         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 221          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 222          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 223          "Entry 0001"},
 224         /* Saifun SA25F010 (non-buffered flash) */
 225         /* strap, cfg1, & write1 need updates */
 226         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 227          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 228          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 229          "Non-buffered flash (128kB)"},
 230         /* Saifun SA25F020 (non-buffered flash) */
 231         /* strap, cfg1, & write1 need updates */
 232         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 233          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 234          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 235          "Non-buffered flash (256kB)"},
 236         /* Expansion entry 0100 */
 237         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 238          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 239          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 240          "Entry 0100"},
 241         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 242         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 243          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 244          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 245          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 246         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 247         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 248          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 249          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 250          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 251         /* Saifun SA25F005 (non-buffered flash) */
 252         /* strap, cfg1, & write1 need updates */
 253         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 254          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 255          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 256          "Non-buffered flash (64kB)"},
 257         /* Fast EEPROM */
 258         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 259          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 260          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 261          "EEPROM - fast"},
 262         /* Expansion entry 1001 */
 263         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 264          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 265          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 266          "Entry 1001"},
 267         /* Expansion entry 1010 */
 268         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 269          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 270          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 271          "Entry 1010"},
 272         /* ATMEL AT45DB011B (buffered flash) */
 273         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 274          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 275          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 276          "Buffered flash (128kB)"},
 277         /* Expansion entry 1100 */
 278         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 279          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 280          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 281          "Entry 1100"},
 282         /* Expansion entry 1101 */
 283         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 284          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 285          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 286          "Entry 1101"},
 287         /* Ateml Expansion entry 1110 */
 288         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 289          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 290          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 291          "Entry 1110 (Atmel)"},
 292         /* ATMEL AT45DB021B (buffered flash) */
 293         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 294          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 295          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 296          "Buffered flash (256kB)"},
 297 };
 298
 299 /*
 300  * The BCM5709 controllers transparently handle the
 301  * differences between Atmel 264 byte pages and all
 302  * flash devices which use 256 byte pages, so no
 303  * logical-to-physical mapping is required in the
 304  * driver.
 305  */
 306 static struct flash_spec flash_5709 = {
 307         .flags          = BCE_NV_BUFFERED,
 308         .page_bits      = BCM5709_FLASH_PAGE_BITS,
 309         .page_size      = BCM5709_FLASH_PAGE_SIZE,
 310         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
 311         .total_size     = BUFFERED_FLASH_TOTAL_SIZE * 2,
 312         .name           = "5709/5716 buffered flash (256kB)",
 313 };
 314
 315
 316 /****************************************************************************/
 317 /* DragonFly device entry points.                                           */
 318 /****************************************************************************/
 319 static int      bce_probe(device_t);
 320 static int      bce_attach(device_t);
 321 static int      bce_detach(device_t);
 322 static void     bce_shutdown(device_t);
 323
 324 /****************************************************************************/
 325 /* BCE Debug Data Structure Dump Routines                                   */
 326 /****************************************************************************/
 327 #ifdef BCE_DEBUG
 328 static void     bce_dump_mbuf(struct bce_softc *, struct mbuf *);
 329 static void     bce_dump_tx_mbuf_chain(struct bce_softc *, int, int);
 330 static void     bce_dump_rx_mbuf_chain(struct bce_softc *, int, int);
 331 static void     bce_dump_txbd(struct bce_softc *, int, struct tx_bd *);
 332 static void     bce_dump_rxbd(struct bce_softc *, int, struct rx_bd *);
 333 static void     bce_dump_l2fhdr(struct bce_softc *, int,
 334                                 struct l2_fhdr *) __unused;
 335 static void     bce_dump_tx_chain(struct bce_softc *, int, int);
 336 static void     bce_dump_rx_chain(struct bce_softc *, int, int);
 337 static void     bce_dump_status_block(struct bce_softc *);
 338 static void     bce_dump_driver_state(struct bce_softc *);
 339 static void     bce_dump_stats_block(struct bce_softc *) __unused;
 340 static void     bce_dump_hw_state(struct bce_softc *);
 341 static void     bce_dump_txp_state(struct bce_softc *);
 342 static void     bce_dump_rxp_state(struct bce_softc *) __unused;
 343 static void     bce_dump_tpat_state(struct bce_softc *) __unused;
 344 static void     bce_freeze_controller(struct bce_softc *) __unused;
 345 static void     bce_unfreeze_controller(struct bce_softc *) __unused;
 346 static void     bce_breakpoint(struct bce_softc *);
 347 #endif  /* BCE_DEBUG */
 348
 349
 350 /****************************************************************************/
 351 /* BCE Register/Memory Access Routines                                      */
 352 /****************************************************************************/
 353 static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t);
 354 static void     bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t);
 355 static void     bce_shmem_wr(struct bce_softc *, uint32_t, uint32_t);
 356 static uint32_t bce_shmem_rd(struct bce_softc *, u32);
 357 static void     bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t);
 358 static int      bce_miibus_read_reg(device_t, int, int);
 359 static int      bce_miibus_write_reg(device_t, int, int, int);
 360 static void     bce_miibus_statchg(device_t);
 361
 362
 363 /****************************************************************************/
 364 /* BCE NVRAM Access Routines                                                */
 365 /****************************************************************************/
 366 static int      bce_acquire_nvram_lock(struct bce_softc *);
 367 static int      bce_release_nvram_lock(struct bce_softc *);
 368 static void     bce_enable_nvram_access(struct bce_softc *);
 369 static void     bce_disable_nvram_access(struct bce_softc *);
 370 static int      bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *,
 371                                      uint32_t);
 372 static int      bce_init_nvram(struct bce_softc *);
 373 static int      bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int);
 374 static int      bce_nvram_test(struct bce_softc *);
 375
 376 /****************************************************************************/
 377 /* BCE DMA Allocate/Free Routines                                           */
 378 /****************************************************************************/
 379 static int      bce_dma_alloc(struct bce_softc *);
 380 static void     bce_dma_free(struct bce_softc *);
 381 static void     bce_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 382
 383 /****************************************************************************/
 384 /* BCE Firmware Synchronization and Load                                    */
 385 /****************************************************************************/
 386 static int      bce_fw_sync(struct bce_softc *, uint32_t);
 387 static void     bce_load_rv2p_fw(struct bce_softc *, uint32_t *,
 388                                  uint32_t, uint32_t);
 389 static void     bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *,
 390                                 struct fw_info *);
 391 static void     bce_start_cpu(struct bce_softc *, struct cpu_reg *);
 392 static void     bce_halt_cpu(struct bce_softc *, struct cpu_reg *);
 393 static void     bce_start_rxp_cpu(struct bce_softc *);
 394 static void     bce_init_rxp_cpu(struct bce_softc *);
 395 static void     bce_init_txp_cpu(struct bce_softc *);
 396 static void     bce_init_tpat_cpu(struct bce_softc *);
 397 static void     bce_init_cp_cpu(struct bce_softc *);
 398 static void     bce_init_com_cpu(struct bce_softc *);
 399 static void     bce_init_cpus(struct bce_softc *);
 400
 401 static void     bce_stop(struct bce_softc *);
 402 static int      bce_reset(struct bce_softc *, uint32_t);
 403 static int      bce_chipinit(struct bce_softc *);
 404 static int      bce_blockinit(struct bce_softc *);
 405 static int      bce_newbuf_std(struct bce_softc *, uint16_t *, uint16_t *,
 406                                uint32_t *, int);
 407 static void     bce_setup_rxdesc_std(struct bce_softc *, uint16_t, uint32_t *);
 408 static void     bce_probe_pci_caps(struct bce_softc *);
 409 static void     bce_print_adapter_info(struct bce_softc *);
 410 static void     bce_get_media(struct bce_softc *);
 411
 412 static void     bce_init_tx_context(struct bce_softc *);
 413 static int      bce_init_tx_chain(struct bce_softc *);
 414 static void     bce_init_rx_context(struct bce_softc *);
 415 static int      bce_init_rx_chain(struct bce_softc *);
 416 static void     bce_free_rx_chain(struct bce_softc *);
 417 static void     bce_free_tx_chain(struct bce_softc *);
 418
 419 static int      bce_encap(struct bce_softc *, struct mbuf **);
 420 static void     bce_start(struct ifnet *);
 421 static int      bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 422 static void     bce_watchdog(struct ifnet *);
 423 static int      bce_ifmedia_upd(struct ifnet *);
 424 static void     bce_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 425 static void     bce_init(void *);
 426 static void     bce_mgmt_init(struct bce_softc *);
 427
 428 static int      bce_init_ctx(struct bce_softc *);
 429 static void     bce_get_mac_addr(struct bce_softc *);
 430 static void     bce_set_mac_addr(struct bce_softc *);
 431 static void     bce_phy_intr(struct bce_softc *);
 432 static void     bce_rx_intr(struct bce_softc *, int);
 433 static void     bce_tx_intr(struct bce_softc *);
 434 static void     bce_disable_intr(struct bce_softc *);
 435 static void     bce_enable_intr(struct bce_softc *, int);
 436
 437 #ifdef DEVICE_POLLING
 438 static void     bce_poll(struct ifnet *, enum poll_cmd, int);
 439 #endif
 440 static void     bce_intr(struct bce_softc *);
 441 static void     bce_intr_legacy(void *);
 442 static void     bce_intr_msi(void *);
 443 static void     bce_intr_msi_oneshot(void *);
 444 static void     bce_set_rx_mode(struct bce_softc *);
 445 static void     bce_stats_update(struct bce_softc *);
 446 static void     bce_tick(void *);
 447 static void     bce_tick_serialized(struct bce_softc *);
 448 static void     bce_pulse(void *);
 449 static void     bce_pulse_check_msi(struct bce_softc *);
 450 static void     bce_add_sysctls(struct bce_softc *);
 451
 452 static void     bce_coal_change(struct bce_softc *);
 453 static int      bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS);
 454 static int      bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS);
 455 static int      bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS);
 456 static int      bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS);
 457 static int      bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS);
 458 static int      bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS);
 459 static int      bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS);
 460 static int      bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS);
 461 static int      bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS,
 462                                        uint32_t *, uint32_t);
 463
 464 /*
 465  * NOTE:
 466  * Don't set bce_tx_ticks_int/bce_tx_ticks to 1023.  Linux's bnx2
 467  * takes 1023 as the TX ticks limit.  However, using 1023 will
 468  * cause 5708(B2) to generate extra interrupts (~2000/s) even when
 469  * there is _no_ network activity on the NIC.
 470  */
 471 static uint32_t bce_tx_bds_int = 255;           /* bcm: 20 */
 472 static uint32_t bce_tx_bds = 255;               /* bcm: 20 */
 473 static uint32_t bce_tx_ticks_int = 1022;        /* bcm: 80 */
 474 static uint32_t bce_tx_ticks = 1022;            /* bcm: 80 */
 475 static uint32_t bce_rx_bds_int = 128;           /* bcm: 6 */
 476 static uint32_t bce_rx_bds = 128;               /* bcm: 6 */
 477 static uint32_t bce_rx_ticks_int = 125;         /* bcm: 18 */
 478 static uint32_t bce_rx_ticks = 125;             /* bcm: 18 */
 479
 480 static int      bce_msi_enable = 1;
 481
 482 static int      bce_rx_pages = RX_PAGES_DEFAULT;
 483 static int      bce_tx_pages = TX_PAGES_DEFAULT;
 484
 485 TUNABLE_INT("hw.bce.tx_bds_int", &bce_tx_bds_int);
 486 TUNABLE_INT("hw.bce.tx_bds", &bce_tx_bds);
 487 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
 488 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
 489 TUNABLE_INT("hw.bce.rx_bds_int", &bce_rx_bds_int);
 490 TUNABLE_INT("hw.bce.rx_bds", &bce_rx_bds);
 491 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
 492 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
 493 TUNABLE_INT("hw.bce.msi.enable", &bce_msi_enable);
 494 TUNABLE_INT("hw.bce.rx_pages", &bce_rx_pages);
 495 TUNABLE_INT("hw.bce.tx_pages", &bce_tx_pages);
 496
 497 /****************************************************************************/
 498 /* DragonFly device dispatch table.                                         */
 499 /****************************************************************************/
 500 static device_method_t bce_methods[] = {
 501         /* Device interface */
 502         DEVMETHOD(device_probe,         bce_probe),
 503         DEVMETHOD(device_attach,        bce_attach),
 504         DEVMETHOD(device_detach,        bce_detach),
 505         DEVMETHOD(device_shutdown,      bce_shutdown),
 506
 507         /* bus interface */
 508         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 509         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 510
 511         /* MII interface */
 512         DEVMETHOD(miibus_readreg,       bce_miibus_read_reg),
 513         DEVMETHOD(miibus_writereg,      bce_miibus_write_reg),
 514         DEVMETHOD(miibus_statchg,       bce_miibus_statchg),
 515
 516         { 0, 0 }
 517 };
 518
 519 static driver_t bce_driver = {
 520         "bce",
 521         bce_methods,
 522         sizeof(struct bce_softc)
 523 };
 524
 525 static devclass_t bce_devclass;
 526
 527
 528 DECLARE_DUMMY_MODULE(if_bce);
 529 MODULE_DEPEND(bce, miibus, 1, 1, 1);
 530 DRIVER_MODULE(if_bce, pci, bce_driver, bce_devclass, NULL, NULL);
 531 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
 532
 533
 534 /****************************************************************************/
 535 /* Device probe function.                                                   */
 536 /*                                                                          */
 537 /* Compares the device to the driver's list of supported devices and        */
 538 /* reports back to the OS whether this is the right driver for the device.  */
 539 /*                                                                          */
 540 /* Returns:                                                                 */
 541 /*   BUS_PROBE_DEFAULT on success, positive value on failure.               */
 542 /****************************************************************************/
 543 static int
 544 bce_probe(device_t dev)
 545 {
 546         struct bce_type *t;
 547         uint16_t vid, did, svid, sdid;
 548
 549         /* Get the data for the device to be probed. */
 550         vid  = pci_get_vendor(dev);
 551         did  = pci_get_device(dev);
 552         svid = pci_get_subvendor(dev);
 553         sdid = pci_get_subdevice(dev);
 554
 555         /* Look through the list of known devices for a match. */
 556         for (t = bce_devs; t->bce_name != NULL; ++t) {
 557                 if (vid == t->bce_vid && did == t->bce_did &&
 558                     (svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) &&
 559                     (sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) {
 560                         uint32_t revid = pci_read_config(dev, PCIR_REVID, 4);
 561                         char *descbuf;
 562
 563                         descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK);
 564
 565                         /* Print out the device identity. */
 566                         ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
 567                                   t->bce_name,
 568                                   ((revid & 0xf0) >> 4) + 'A', revid & 0xf);
 569
 570                         device_set_desc_copy(dev, descbuf);
 571                         kfree(descbuf, M_TEMP);
 572                         return 0;
 573                 }
 574         }
 575         return ENXIO;
 576 }
 577
 578
 579 /****************************************************************************/
 580 /* PCI Capabilities Probe Function.                                         */
 581 /*                                                                          */
 582 /* Walks the PCI capabiites list for the device to find what features are   */
 583 /* supported.                                                               */
 584 /*                                                                          */
 585 /* Returns:                                                                 */
 586 /*   None.                                                                  */
 587 /****************************************************************************/
 588 static void
 589 bce_print_adapter_info(struct bce_softc *sc)
 590 {
 591         device_printf(sc->bce_dev, "ASIC (0x%08X); ", sc->bce_chipid);
 592
 593         kprintf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
 594                 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
 595
 596         /* Bus info. */
 597         if (sc->bce_flags & BCE_PCIE_FLAG) {
 598                 kprintf("Bus (PCIe x%d, ", sc->link_width);
 599                 switch (sc->link_speed) {
 600                 case 1:
 601                         kprintf("2.5Gbps); ");
 602                         break;
 603                 case 2:
 604                         kprintf("5Gbps); ");
 605                         break;
 606                 default:
 607                         kprintf("Unknown link speed); ");
 608                         break;
 609                 }
 610         } else {
 611                 kprintf("Bus (PCI%s, %s, %dMHz); ",
 612                     ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
 613                     ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
 614                     sc->bus_speed_mhz);
 615         }
 616
 617         /* Firmware version and device features. */
 618         kprintf("B/C (%s)", sc->bce_bc_ver);
 619
 620         if ((sc->bce_flags & BCE_MFW_ENABLE_FLAG) ||
 621             (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
 622                 kprintf("; Flags(");
 623                 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
 624                         kprintf("MFW[%s]", sc->bce_mfw_ver);
 625                 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
 626                         kprintf(" 2.5G");
 627                 kprintf(")");
 628         }
 629         kprintf("\n");
 630 }
 631
 632
 633 /****************************************************************************/
 634 /* PCI Capabilities Probe Function.                                         */
 635 /*                                                                          */
 636 /* Walks the PCI capabiites list for the device to find what features are   */
 637 /* supported.                                                               */
 638 /*                                                                          */
 639 /* Returns:                                                                 */
 640 /*   None.                                                                  */
 641 /****************************************************************************/
 642 static void
 643 bce_probe_pci_caps(struct bce_softc *sc)
 644 {
 645         device_t dev = sc->bce_dev;
 646         uint8_t ptr;
 647
 648         if (pci_is_pcix(dev))
 649                 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
 650
 651         ptr = pci_get_pciecap_ptr(dev);
 652         if (ptr) {
 653                 uint16_t link_status = pci_read_config(dev, ptr + 0x12, 2);
 654
 655                 sc->link_speed = link_status & 0xf;
 656                 sc->link_width = (link_status >> 4) & 0x3f;
 657                 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
 658                 sc->bce_flags |= BCE_PCIE_FLAG;
 659         }
 660 }
 661
 662
 663 /****************************************************************************/
 664 /* Device attach function.                                                  */
 665 /*                                                                          */
 666 /* Allocates device resources, performs secondary chip identification,      */
 667 /* resets and initializes the hardware, and initializes driver instance     */
 668 /* variables.                                                               */
 669 /*                                                                          */
 670 /* Returns:                                                                 */
 671 /*   0 on success, positive value on failure.                               */
 672 /****************************************************************************/
 673 static int
 674 bce_attach(device_t dev)
 675 {
 676         struct bce_softc *sc = device_get_softc(dev);
 677         struct ifnet *ifp = &sc->arpcom.ac_if;
 678         uint32_t val;
 679         u_int irq_flags;
 680         void (*irq_handle)(void *);
 681         int rid, rc = 0;
 682         int i, j;
 683         struct mii_probe_args mii_args;
 684         uintptr_t mii_priv = 0;
 685
 686         sc->bce_dev = dev;
 687         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 688
 689         pci_enable_busmaster(dev);
 690
 691         bce_probe_pci_caps(sc);
 692
 693         /* Allocate PCI memory resources. */
 694         rid = PCIR_BAR(0);
 695         sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 696                                                  RF_ACTIVE | PCI_RF_DENSE);
 697         if (sc->bce_res_mem == NULL) {
 698                 device_printf(dev, "PCI memory allocation failed\n");
 699                 return ENXIO;
 700         }
 701         sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
 702         sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
 703
 704         /* Allocate PCI IRQ resources. */
 705         sc->bce_irq_type = pci_alloc_1intr(dev, bce_msi_enable,
 706             &sc->bce_irq_rid, &irq_flags);
 707
 708         sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
 709             &sc->bce_irq_rid, irq_flags);
 710         if (sc->bce_res_irq == NULL) {
 711                 device_printf(dev, "PCI map interrupt failed\n");
 712                 rc = ENXIO;
 713                 goto fail;
 714         }
 715
 716         /*
 717          * Configure byte swap and enable indirect register access.
 718          * Rely on CPU to do target byte swapping on big endian systems.
 719          * Access to registers outside of PCI configurtion space are not
 720          * valid until this is done.
 721          */
 722         pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
 723                          BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
 724                          BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
 725
 726         /* Save ASIC revsion info. */
 727         sc->bce_chipid =  REG_RD(sc, BCE_MISC_ID);
 728
 729         /* Weed out any non-production controller revisions. */
 730         switch (BCE_CHIP_ID(sc)) {
 731         case BCE_CHIP_ID_5706_A0:
 732         case BCE_CHIP_ID_5706_A1:
 733         case BCE_CHIP_ID_5708_A0:
 734         case BCE_CHIP_ID_5708_B0:
 735         case BCE_CHIP_ID_5709_A0:
 736         case BCE_CHIP_ID_5709_B0:
 737         case BCE_CHIP_ID_5709_B1:
 738 #ifdef foo
 739         /* 5709C B2 seems to work fine */
 740         case BCE_CHIP_ID_5709_B2:
 741 #endif
 742                 device_printf(dev, "Unsupported chip id 0x%08x!\n",
 743                               BCE_CHIP_ID(sc));
 744                 rc = ENODEV;
 745                 goto fail;
 746         }
 747
 748         mii_priv |= BRGPHY_FLAG_WIRESPEED;
 749         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
 750                 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax ||
 751                     BCE_CHIP_REV(sc) == BCE_CHIP_REV_Bx)
 752                         mii_priv |= BRGPHY_FLAG_NO_EARLYDAC;
 753         } else {
 754                 mii_priv |= BRGPHY_FLAG_BER_BUG;
 755         }
 756
 757         if (sc->bce_irq_type == PCI_INTR_TYPE_LEGACY) {
 758                 irq_handle = bce_intr_legacy;
 759         } else if (sc->bce_irq_type == PCI_INTR_TYPE_MSI) {
 760                 irq_handle = bce_intr_msi;
 761                 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
 762                         irq_handle = bce_intr_msi_oneshot;
 763                         sc->bce_flags |= BCE_ONESHOT_MSI_FLAG;
 764                 }
 765         } else {
 766                 panic("%s: unsupported intr type %d",
 767                     device_get_nameunit(dev), sc->bce_irq_type);
 768         }
 769
 770         /*
 771          * Find the base address for shared memory access.
 772          * Newer versions of bootcode use a signature and offset
 773          * while older versions use a fixed address.
 774          */
 775         val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
 776         if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) ==
 777             BCE_SHM_HDR_SIGNATURE_SIG) {
 778                 /* Multi-port devices use different offsets in shared memory. */
 779                 sc->bce_shmem_base = REG_RD_IND(sc,
 780                     BCE_SHM_HDR_ADDR_0 + (pci_get_function(sc->bce_dev) << 2));
 781         } else {
 782                 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
 783         }
 784         DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base);
 785
 786         /* Fetch the bootcode revision. */
 787         val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
 788         for (i = 0, j = 0; i < 3; i++) {
 789                 uint8_t num;
 790                 int k, skip0;
 791
 792                 num = (uint8_t)(val >> (24 - (i * 8)));
 793                 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
 794                         if (num >= k || !skip0 || k == 1) {
 795                                 sc->bce_bc_ver[j++] = (num / k) + '0';
 796                                 skip0 = 0;
 797                         }
 798                 }
 799                 if (i != 2)
 800                         sc->bce_bc_ver[j++] = '.';
 801         }
 802
 803         /* Check if any management firwmare is running. */
 804         val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
 805         if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
 806                 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
 807
 808                 /* Allow time for firmware to enter the running state. */
 809                 for (i = 0; i < 30; i++) {
 810                         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
 811                         if (val & BCE_CONDITION_MFW_RUN_MASK)
 812                                 break;
 813                         DELAY(10000);
 814                 }
 815         }
 816
 817         /* Check the current bootcode state. */
 818         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION) &
 819             BCE_CONDITION_MFW_RUN_MASK;
 820         if (val != BCE_CONDITION_MFW_RUN_UNKNOWN &&
 821             val != BCE_CONDITION_MFW_RUN_NONE) {
 822                 uint32_t addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
 823
 824                 for (i = 0, j = 0; j < 3; j++) {
 825                         val = bce_reg_rd_ind(sc, addr + j * 4);
 826                         val = bswap32(val);
 827                         memcpy(&sc->bce_mfw_ver[i], &val, 4);
 828                         i += 4;
 829                 }
 830         }
 831
 832         /* Get PCI bus information (speed and type). */
 833         val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
 834         if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
 835                 uint32_t clkreg;
 836
 837                 sc->bce_flags |= BCE_PCIX_FLAG;
 838
 839                 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) &
 840                          BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
 841                 switch (clkreg) {
 842                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
 843                         sc->bus_speed_mhz = 133;
 844                         break;
 845
 846                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
 847                         sc->bus_speed_mhz = 100;
 848                         break;
 849
 850                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
 851                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
 852                         sc->bus_speed_mhz = 66;
 853                         break;
 854
 855                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
 856                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
 857                         sc->bus_speed_mhz = 50;
 858                         break;
 859
 860                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
 861                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
 862                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
 863                         sc->bus_speed_mhz = 33;
 864                         break;
 865                 }
 866         } else {
 867                 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
 868                         sc->bus_speed_mhz = 66;
 869                 else
 870                         sc->bus_speed_mhz = 33;
 871         }
 872
 873         if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
 874                 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
 875
 876         /* Reset the controller. */
 877         rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
 878         if (rc != 0)
 879                 goto fail;
 880
 881         /* Initialize the controller. */
 882         rc = bce_chipinit(sc);
 883         if (rc != 0) {
 884                 device_printf(dev, "Controller initialization failed!\n");
 885                 goto fail;
 886         }
 887
 888         /* Perform NVRAM test. */
 889         rc = bce_nvram_test(sc);
 890         if (rc != 0) {
 891                 device_printf(dev, "NVRAM test failed!\n");
 892                 goto fail;
 893         }
 894
 895         /* Fetch the permanent Ethernet MAC address. */
 896         bce_get_mac_addr(sc);
 897
 898         /*
 899          * Trip points control how many BDs
 900          * should be ready before generating an
 901          * interrupt while ticks control how long
 902          * a BD can sit in the chain before
 903          * generating an interrupt.  Set the default
 904          * values for the RX and TX rings.
 905          */
 906
 907 #ifdef BCE_DRBUG
 908         /* Force more frequent interrupts. */
 909         sc->bce_tx_quick_cons_trip_int = 1;
 910         sc->bce_tx_quick_cons_trip     = 1;
 911         sc->bce_tx_ticks_int           = 0;
 912         sc->bce_tx_ticks               = 0;
 913
 914         sc->bce_rx_quick_cons_trip_int = 1;
 915         sc->bce_rx_quick_cons_trip     = 1;
 916         sc->bce_rx_ticks_int           = 0;
 917         sc->bce_rx_ticks               = 0;
 918 #else
 919         sc->bce_tx_quick_cons_trip_int = bce_tx_bds_int;
 920         sc->bce_tx_quick_cons_trip     = bce_tx_bds;
 921         sc->bce_tx_ticks_int           = bce_tx_ticks_int;
 922         sc->bce_tx_ticks               = bce_tx_ticks;
 923
 924         sc->bce_rx_quick_cons_trip_int = bce_rx_bds_int;
 925         sc->bce_rx_quick_cons_trip     = bce_rx_bds;
 926         sc->bce_rx_ticks_int           = bce_rx_ticks_int;
 927         sc->bce_rx_ticks               = bce_rx_ticks;
 928 #endif
 929
 930         /* Update statistics once every second. */
 931         sc->bce_stats_ticks = 1000000 & 0xffff00;
 932
 933         /* Find the media type for the adapter. */
 934         bce_get_media(sc);
 935
 936         /* Allocate DMA memory resources. */
 937         rc = bce_dma_alloc(sc);
 938         if (rc != 0) {
 939                 device_printf(dev, "DMA resource allocation failed!\n");
 940                 goto fail;
 941         }
 942
 943         /* Initialize the ifnet interface. */
 944         ifp->if_softc = sc;
 945         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 946         ifp->if_ioctl = bce_ioctl;
 947         ifp->if_start = bce_start;
 948         ifp->if_init = bce_init;
 949         ifp->if_watchdog = bce_watchdog;
 950 #ifdef DEVICE_POLLING
 951         ifp->if_poll = bce_poll;
 952 #endif
 953         ifp->if_mtu = ETHERMTU;
 954         ifp->if_hwassist = BCE_IF_HWASSIST;
 955         ifp->if_capabilities = BCE_IF_CAPABILITIES;
 956         ifp->if_capenable = ifp->if_capabilities;
 957         ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD(sc));
 958         ifq_set_ready(&ifp->if_snd);
 959
 960         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
 961                 ifp->if_baudrate = IF_Gbps(2.5);
 962         else
 963                 ifp->if_baudrate = IF_Gbps(1);
 964
 965         /* Assume a standard 1500 byte MTU size for mbuf allocations. */
 966         sc->mbuf_alloc_size  = MCLBYTES;
 967
 968         /*
 969          * Look for our PHY.
 970          */
 971         mii_probe_args_init(&mii_args, bce_ifmedia_upd, bce_ifmedia_sts);
 972         mii_args.mii_probemask = 1 << sc->bce_phy_addr;
 973         mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
 974         mii_args.mii_priv = mii_priv;
 975
 976         rc = mii_probe(dev, &sc->bce_miibus, &mii_args);
 977         if (rc != 0) {
 978                 device_printf(dev, "PHY probe failed!\n");
 979                 goto fail;
 980         }
 981
 982         /* Attach to the Ethernet interface list. */
 983         ether_ifattach(ifp, sc->eaddr, NULL);
 984
 985         callout_init_mp(&sc->bce_tick_callout);
 986         callout_init_mp(&sc->bce_pulse_callout);
 987
 988         /* Hookup IRQ last. */
 989         rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_MPSAFE, irq_handle, sc,
 990                             &sc->bce_intrhand, ifp->if_serializer);
 991         if (rc != 0) {
 992                 device_printf(dev, "Failed to setup IRQ!\n");
 993                 ether_ifdetach(ifp);
 994                 goto fail;
 995         }
 996
 997         ifp->if_cpuid = rman_get_cpuid(sc->bce_res_irq);
 998         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
 999
1000         /* Print some important debugging info. */
1001         DBRUN(BCE_INFO, bce_dump_driver_state(sc));
1002
1003         /* Add the supported sysctls to the kernel. */
1004         bce_add_sysctls(sc);
1005
1006         /*
1007          * The chip reset earlier notified the bootcode that
1008          * a driver is present.  We now need to start our pulse
1009          * routine so that the bootcode is reminded that we're
1010          * still running.
1011          */
1012         bce_pulse(sc);
1013
1014         /* Get the firmware running so IPMI still works */
1015         bce_mgmt_init(sc);
1016
1017         if (bootverbose)
1018                 bce_print_adapter_info(sc);
1019
1020         return 0;
1021 fail:
1022         bce_detach(dev);
1023         return(rc);
1024 }
1025
1026
1027 /****************************************************************************/
1028 /* Device detach function.                                                  */
1029 /*                                                                          */
1030 /* Stops the controller, resets the controller, and releases resources.     */
1031 /*                                                                          */
1032 /* Returns:                                                                 */
1033 /*   0 on success, positive value on failure.                               */
1034 /****************************************************************************/
1035 static int
1036 bce_detach(device_t dev)
1037 {
1038         struct bce_softc *sc = device_get_softc(dev);
1039
1040         if (device_is_attached(dev)) {
1041                 struct ifnet *ifp = &sc->arpcom.ac_if;
1042                 uint32_t msg;
1043
1044                 /* Stop and reset the controller. */
1045                 lwkt_serialize_enter(ifp->if_serializer);
1046                 callout_stop(&sc->bce_pulse_callout);
1047                 bce_stop(sc);
1048                 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1049                         msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1050                 else
1051                         msg = BCE_DRV_MSG_CODE_UNLOAD;
1052                 bce_reset(sc, msg);
1053                 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
1054                 lwkt_serialize_exit(ifp->if_serializer);
1055
1056                 ether_ifdetach(ifp);
1057         }
1058
1059         /* If we have a child device on the MII bus remove it too. */
1060         if (sc->bce_miibus)
1061                 device_delete_child(dev, sc->bce_miibus);
1062         bus_generic_detach(dev);
1063
1064         if (sc->bce_res_irq != NULL) {
1065                 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid,
1066                     sc->bce_res_irq);
1067         }
1068
1069         if (sc->bce_irq_type == PCI_INTR_TYPE_MSI)
1070                 pci_release_msi(dev);
1071
1072         if (sc->bce_res_mem != NULL) {
1073                 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
1074                                      sc->bce_res_mem);
1075         }
1076
1077         bce_dma_free(sc);
1078
1079         if (sc->bce_sysctl_tree != NULL)
1080                 sysctl_ctx_free(&sc->bce_sysctl_ctx);
1081
1082         return 0;
1083 }
1084
1085
1086 /****************************************************************************/
1087 /* Device shutdown function.                                                */
1088 /*                                                                          */
1089 /* Stops and resets the controller.                                         */
1090 /*                                                                          */
1091 /* Returns:                                                                 */
1092 /*   Nothing                                                                */
1093 /****************************************************************************/
1094 static void
1095 bce_shutdown(device_t dev)
1096 {
1097         struct bce_softc *sc = device_get_softc(dev);
1098         struct ifnet *ifp = &sc->arpcom.ac_if;
1099         uint32_t msg;
1100
1101         lwkt_serialize_enter(ifp->if_serializer);
1102         bce_stop(sc);
1103         if (sc->bce_flags & BCE_NO_WOL_FLAG)
1104                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1105         else
1106                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1107         bce_reset(sc, msg);
1108         lwkt_serialize_exit(ifp->if_serializer);
1109 }
1110
1111
1112 /****************************************************************************/
1113 /* Indirect register read.                                                  */
1114 /*                                                                          */
1115 /* Reads NetXtreme II registers using an index/data register pair in PCI    */
1116 /* configuration space.  Using this mechanism avoids issues with posted     */
1117 /* reads but is much slower than memory-mapped I/O.                         */
1118 /*                                                                          */
1119 /* Returns:                                                                 */
1120 /*   The value of the register.                                             */
1121 /****************************************************************************/
1122 static uint32_t
1123 bce_reg_rd_ind(struct bce_softc *sc, uint32_t offset)
1124 {
1125         device_t dev = sc->bce_dev;
1126
1127         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1128 #ifdef BCE_DEBUG
1129         {
1130                 uint32_t val;
1131                 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1132                 DBPRINT(sc, BCE_EXCESSIVE,
1133                         "%s(); offset = 0x%08X, val = 0x%08X\n",
1134                         __func__, offset, val);
1135                 return val;
1136         }
1137 #else
1138         return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1139 #endif
1140 }
1141
1142
1143 /****************************************************************************/
1144 /* Indirect register write.                                                 */
1145 /*                                                                          */
1146 /* Writes NetXtreme II registers using an index/data register pair in PCI   */
1147 /* configuration space.  Using this mechanism avoids issues with posted     */
1148 /* writes but is muchh slower than memory-mapped I/O.                       */
1149 /*                                                                          */
1150 /* Returns:                                                                 */
1151 /*   Nothing.                                                               */
1152 /****************************************************************************/
1153 static void
1154 bce_reg_wr_ind(struct bce_softc *sc, uint32_t offset, uint32_t val)
1155 {
1156         device_t dev = sc->bce_dev;
1157
1158         DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
1159                 __func__, offset, val);
1160
1161         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1162         pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1163 }
1164
1165
1166 /****************************************************************************/
1167 /* Shared memory write.                                                     */
1168 /*                                                                          */
1169 /* Writes NetXtreme II shared memory region.                                */
1170 /*                                                                          */
1171 /* Returns:                                                                 */
1172 /*   Nothing.                                                               */
1173 /****************************************************************************/
1174 static void
1175 bce_shmem_wr(struct bce_softc *sc, uint32_t offset, uint32_t val)
1176 {
1177         bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1178 }
1179
1180
1181 /****************************************************************************/
1182 /* Shared memory read.                                                      */
1183 /*                                                                          */
1184 /* Reads NetXtreme II shared memory region.                                 */
1185 /*                                                                          */
1186 /* Returns:                                                                 */
1187 /*   The 32 bit value read.                                                 */
1188 /****************************************************************************/
1189 static u32
1190 bce_shmem_rd(struct bce_softc *sc, uint32_t offset)
1191 {
1192         return bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1193 }
1194
1195
1196 /****************************************************************************/
1197 /* Context memory write.                                                    */
1198 /*                                                                          */
1199 /* The NetXtreme II controller uses context memory to track connection      */
1200 /* information for L2 and higher network protocols.                         */
1201 /*                                                                          */
1202 /* Returns:                                                                 */
1203 /*   Nothing.                                                               */
1204 /****************************************************************************/
1205 static void
1206 bce_ctx_wr(struct bce_softc *sc, uint32_t cid_addr, uint32_t ctx_offset,
1207     uint32_t ctx_val)
1208 {
1209         uint32_t idx, offset = ctx_offset + cid_addr;
1210         uint32_t val, retry_cnt = 5;
1211
1212         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1213             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1214                 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1215                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1216
1217                 for (idx = 0; idx < retry_cnt; idx++) {
1218                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1219                         if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1220                                 break;
1221                         DELAY(5);
1222                 }
1223
1224                 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) {
1225                         device_printf(sc->bce_dev,
1226                             "Unable to write CTX memory: "
1227                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1228                             cid_addr, ctx_offset);
1229                 }
1230         } else {
1231                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1232                 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1233         }
1234 }
1235
1236
1237 /****************************************************************************/
1238 /* PHY register read.                                                       */
1239 /*                                                                          */
1240 /* Implements register reads on the MII bus.                                */
1241 /*                                                                          */
1242 /* Returns:                                                                 */
1243 /*   The value of the register.                                             */
1244 /****************************************************************************/
1245 static int
1246 bce_miibus_read_reg(device_t dev, int phy, int reg)
1247 {
1248         struct bce_softc *sc = device_get_softc(dev);
1249         uint32_t val;
1250         int i;
1251
1252         /* Make sure we are accessing the correct PHY address. */
1253         KASSERT(phy == sc->bce_phy_addr,
1254             ("invalid phyno %d, should be %d\n", phy, sc->bce_phy_addr));
1255
1256         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1257                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1258                 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1259
1260                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1261                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1262
1263                 DELAY(40);
1264         }
1265
1266         val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1267               BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1268               BCE_EMAC_MDIO_COMM_START_BUSY;
1269         REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1270
1271         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1272                 DELAY(10);
1273
1274                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1275                 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1276                         DELAY(5);
1277
1278                         val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1279                         val &= BCE_EMAC_MDIO_COMM_DATA;
1280                         break;
1281                 }
1282         }
1283
1284         if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1285                 if_printf(&sc->arpcom.ac_if,
1286                           "Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
1287                           phy, reg);
1288                 val = 0x0;
1289         } else {
1290                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1291         }
1292
1293         DBPRINT(sc, BCE_EXCESSIVE,
1294                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1295                 __func__, phy, (uint16_t)reg & 0xffff, (uint16_t) val & 0xffff);
1296
1297         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1298                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1299                 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1300
1301                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1302                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1303
1304                 DELAY(40);
1305         }
1306         return (val & 0xffff);
1307 }
1308
1309
1310 /****************************************************************************/
1311 /* PHY register write.                                                      */
1312 /*                                                                          */
1313 /* Implements register writes on the MII bus.                               */
1314 /*                                                                          */
1315 /* Returns:                                                                 */
1316 /*   The value of the register.                                             */
1317 /****************************************************************************/
1318 static int
1319 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1320 {
1321         struct bce_softc *sc = device_get_softc(dev);
1322         uint32_t val1;
1323         int i;
1324
1325         /* Make sure we are accessing the correct PHY address. */
1326         KASSERT(phy == sc->bce_phy_addr,
1327             ("invalid phyno %d, should be %d\n", phy, sc->bce_phy_addr));
1328
1329         DBPRINT(sc, BCE_EXCESSIVE,
1330                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1331                 __func__, phy, (uint16_t)(reg & 0xffff),
1332                 (uint16_t)(val & 0xffff));
1333
1334         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1335                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1336                 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1337
1338                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1339                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1340
1341                 DELAY(40);
1342         }
1343
1344         val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1345                 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1346                 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1347         REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1348
1349         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1350                 DELAY(10);
1351
1352                 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1353                 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1354                         DELAY(5);
1355                         break;
1356                 }
1357         }
1358
1359         if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1360                 if_printf(&sc->arpcom.ac_if, "PHY write timeout!\n");
1361
1362         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1363                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1364                 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1365
1366                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1367                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1368
1369                 DELAY(40);
1370         }
1371         return 0;
1372 }
1373
1374
1375 /****************************************************************************/
1376 /* MII bus status change.                                                   */
1377 /*                                                                          */
1378 /* Called by the MII bus driver when the PHY establishes link to set the    */
1379 /* MAC interface registers.                                                 */
1380 /*                                                                          */
1381 /* Returns:                                                                 */
1382 /*   Nothing.                                                               */
1383 /****************************************************************************/
1384 static void
1385 bce_miibus_statchg(device_t dev)
1386 {
1387         struct bce_softc *sc = device_get_softc(dev);
1388         struct mii_data *mii = device_get_softc(sc->bce_miibus);
1389
1390         DBPRINT(sc, BCE_INFO, "mii_media_active = 0x%08X\n",
1391                 mii->mii_media_active);
1392
1393 #ifdef BCE_DEBUG
1394         /* Decode the interface media flags. */
1395         if_printf(&sc->arpcom.ac_if, "Media: ( ");
1396         switch(IFM_TYPE(mii->mii_media_active)) {
1397         case IFM_ETHER:
1398                 kprintf("Ethernet )");
1399                 break;
1400         default:
1401                 kprintf("Unknown )");
1402                 break;
1403         }
1404
1405         kprintf(" Media Options: ( ");
1406         switch(IFM_SUBTYPE(mii->mii_media_active)) {
1407         case IFM_AUTO:
1408                 kprintf("Autoselect )");
1409                 break;
1410         case IFM_MANUAL:
1411                 kprintf("Manual )");
1412                 break;
1413         case IFM_NONE:
1414                 kprintf("None )");
1415                 break;
1416         case IFM_10_T:
1417                 kprintf("10Base-T )");
1418                 break;
1419         case IFM_100_TX:
1420                 kprintf("100Base-TX )");
1421                 break;
1422         case IFM_1000_SX:
1423                 kprintf("1000Base-SX )");
1424                 break;
1425         case IFM_1000_T:
1426                 kprintf("1000Base-T )");
1427                 break;
1428         default:
1429                 kprintf("Other )");
1430                 break;
1431         }
1432
1433         kprintf(" Global Options: (");
1434         if (mii->mii_media_active & IFM_FDX)
1435                 kprintf(" FullDuplex");
1436         if (mii->mii_media_active & IFM_HDX)
1437                 kprintf(" HalfDuplex");
1438         if (mii->mii_media_active & IFM_LOOP)
1439                 kprintf(" Loopback");
1440         if (mii->mii_media_active & IFM_FLAG0)
1441                 kprintf(" Flag0");
1442         if (mii->mii_media_active & IFM_FLAG1)
1443                 kprintf(" Flag1");
1444         if (mii->mii_media_active & IFM_FLAG2)
1445                 kprintf(" Flag2");
1446         kprintf(" )\n");
1447 #endif
1448
1449         BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT);
1450
1451         /*
1452          * Set MII or GMII interface based on the speed negotiated
1453          * by the PHY.
1454          */
1455         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1456             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
1457                 DBPRINT(sc, BCE_INFO, "Setting GMII interface.\n");
1458                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII);
1459         } else {
1460                 DBPRINT(sc, BCE_INFO, "Setting MII interface.\n");
1461                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII);
1462         }
1463
1464         /*
1465          * Set half or full duplex based on the duplicity negotiated
1466          * by the PHY.
1467          */
1468         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1469                 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n");
1470                 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1471         } else {
1472                 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n");
1473                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1474         }
1475 }
1476
1477
1478 /****************************************************************************/
1479 /* Acquire NVRAM lock.                                                      */
1480 /*                                                                          */
1481 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock.  */
1482 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1483 /* for use by the driver.                                                   */
1484 /*                                                                          */
1485 /* Returns:                                                                 */
1486 /*   0 on success, positive value on failure.                               */
1487 /****************************************************************************/
1488 static int
1489 bce_acquire_nvram_lock(struct bce_softc *sc)
1490 {
1491         uint32_t val;
1492         int j;
1493
1494         DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n");
1495
1496         /* Request access to the flash interface. */
1497         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1498         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1499                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1500                 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1501                         break;
1502
1503                 DELAY(5);
1504         }
1505
1506         if (j >= NVRAM_TIMEOUT_COUNT) {
1507                 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1508                 return EBUSY;
1509         }
1510         return 0;
1511 }
1512
1513
1514 /****************************************************************************/
1515 /* Release NVRAM lock.                                                      */
1516 /*                                                                          */
1517 /* When the caller is finished accessing NVRAM the lock must be released.   */
1518 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1519 /* for use by the driver.                                                   */
1520 /*                                                                          */
1521 /* Returns:                                                                 */
1522 /*   0 on success, positive value on failure.                               */
1523 /****************************************************************************/
1524 static int
1525 bce_release_nvram_lock(struct bce_softc *sc)
1526 {
1527         int j;
1528         uint32_t val;
1529
1530         DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n");
1531
1532         /*
1533          * Relinquish nvram interface.
1534          */
1535         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1536
1537         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1538                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1539                 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1540                         break;
1541
1542                 DELAY(5);
1543         }
1544
1545         if (j >= NVRAM_TIMEOUT_COUNT) {
1546                 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n");
1547                 return EBUSY;
1548         }
1549         return 0;
1550 }
1551
1552
1553 /****************************************************************************/
1554 /* Enable NVRAM access.                                                     */
1555 /*                                                                          */
1556 /* Before accessing NVRAM for read or write operations the caller must      */
1557 /* enabled NVRAM access.                                                    */
1558 /*                                                                          */
1559 /* Returns:                                                                 */
1560 /*   Nothing.                                                               */
1561 /****************************************************************************/
1562 static void
1563 bce_enable_nvram_access(struct bce_softc *sc)
1564 {
1565         uint32_t val;
1566
1567         DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n");
1568
1569         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1570         /* Enable both bits, even on read. */
1571         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1572                val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1573 }
1574
1575
1576 /****************************************************************************/
1577 /* Disable NVRAM access.                                                    */
1578 /*                                                                          */
1579 /* When the caller is finished accessing NVRAM access must be disabled.     */
1580 /*                                                                          */
1581 /* Returns:                                                                 */
1582 /*   Nothing.                                                               */
1583 /****************************************************************************/
1584 static void
1585 bce_disable_nvram_access(struct bce_softc *sc)
1586 {
1587         uint32_t val;
1588
1589         DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n");
1590
1591         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1592
1593         /* Disable both bits, even after read. */
1594         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1595                val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1596 }
1597
1598
1599 /****************************************************************************/
1600 /* Read a dword (32 bits) from NVRAM.                                       */
1601 /*                                                                          */
1602 /* Read a 32 bit word from NVRAM.  The caller is assumed to have already    */
1603 /* obtained the NVRAM lock and enabled the controller for NVRAM access.     */
1604 /*                                                                          */
1605 /* Returns:                                                                 */
1606 /*   0 on success and the 32 bit value read, positive value on failure.     */
1607 /****************************************************************************/
1608 static int
1609 bce_nvram_read_dword(struct bce_softc *sc, uint32_t offset, uint8_t *ret_val,
1610                      uint32_t cmd_flags)
1611 {
1612         uint32_t cmd;
1613         int i, rc = 0;
1614
1615         /* Build the command word. */
1616         cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1617
1618         /* Calculate the offset for buffered flash. */
1619         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
1620                 offset = ((offset / sc->bce_flash_info->page_size) <<
1621                           sc->bce_flash_info->page_bits) +
1622                          (offset % sc->bce_flash_info->page_size);
1623         }
1624
1625         /*
1626          * Clear the DONE bit separately, set the address to read,
1627          * and issue the read.
1628          */
1629         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1630         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1631         REG_WR(sc, BCE_NVM_COMMAND, cmd);
1632
1633         /* Wait for completion. */
1634         for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1635                 uint32_t val;
1636
1637                 DELAY(5);
1638
1639                 val = REG_RD(sc, BCE_NVM_COMMAND);
1640                 if (val & BCE_NVM_COMMAND_DONE) {
1641                         val = REG_RD(sc, BCE_NVM_READ);
1642
1643                         val = be32toh(val);
1644                         memcpy(ret_val, &val, 4);
1645                         break;
1646                 }
1647         }
1648
1649         /* Check for errors. */
1650         if (i >= NVRAM_TIMEOUT_COUNT) {
1651                 if_printf(&sc->arpcom.ac_if,
1652                           "Timeout error reading NVRAM at offset 0x%08X!\n",
1653                           offset);
1654                 rc = EBUSY;
1655         }
1656         return rc;
1657 }
1658
1659
1660 /****************************************************************************/
1661 /* Initialize NVRAM access.                                                 */
1662 /*                                                                          */
1663 /* Identify the NVRAM device in use and prepare the NVRAM interface to      */
1664 /* access that device.                                                      */
1665 /*                                                                          */
1666 /* Returns:                                                                 */
1667 /*   0 on success, positive value on failure.                               */
1668 /****************************************************************************/
1669 static int
1670 bce_init_nvram(struct bce_softc *sc)
1671 {
1672         uint32_t val;
1673         int j, entry_count, rc = 0;
1674         const struct flash_spec *flash;
1675
1676         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
1677
1678         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1679             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1680                 sc->bce_flash_info = &flash_5709;
1681                 goto bce_init_nvram_get_flash_size;
1682         }
1683
1684         /* Determine the selected interface. */
1685         val = REG_RD(sc, BCE_NVM_CFG1);
1686
1687         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1688
1689         /*
1690          * Flash reconfiguration is required to support additional
1691          * NVRAM devices not directly supported in hardware.
1692          * Check if the flash interface was reconfigured
1693          * by the bootcode.
1694          */
1695
1696         if (val & 0x40000000) {
1697                 /* Flash interface reconfigured by bootcode. */
1698
1699                 DBPRINT(sc, BCE_INFO_LOAD,
1700                         "%s(): Flash WAS reconfigured.\n", __func__);
1701
1702                 for (j = 0, flash = flash_table; j < entry_count;
1703                      j++, flash++) {
1704                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
1705                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1706                                 sc->bce_flash_info = flash;
1707                                 break;
1708                         }
1709                 }
1710         } else {
1711                 /* Flash interface not yet reconfigured. */
1712                 uint32_t mask;
1713
1714                 DBPRINT(sc, BCE_INFO_LOAD,
1715                         "%s(): Flash was NOT reconfigured.\n", __func__);
1716
1717                 if (val & (1 << 23))
1718                         mask = FLASH_BACKUP_STRAP_MASK;
1719                 else
1720                         mask = FLASH_STRAP_MASK;
1721
1722                 /* Look for the matching NVRAM device configuration data. */
1723                 for (j = 0, flash = flash_table; j < entry_count;
1724                      j++, flash++) {
1725                         /* Check if the device matches any of the known devices. */
1726                         if ((val & mask) == (flash->strapping & mask)) {
1727                                 /* Found a device match. */
1728                                 sc->bce_flash_info = flash;
1729
1730                                 /* Request access to the flash interface. */
1731                                 rc = bce_acquire_nvram_lock(sc);
1732                                 if (rc != 0)
1733                                         return rc;
1734
1735                                 /* Reconfigure the flash interface. */
1736                                 bce_enable_nvram_access(sc);
1737                                 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
1738                                 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
1739                                 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
1740                                 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
1741                                 bce_disable_nvram_access(sc);
1742                                 bce_release_nvram_lock(sc);
1743                                 break;
1744                         }
1745                 }
1746         }
1747
1748         /* Check if a matching device was found. */
1749         if (j == entry_count) {
1750                 sc->bce_flash_info = NULL;
1751                 if_printf(&sc->arpcom.ac_if, "Unknown Flash NVRAM found!\n");
1752                 return ENODEV;
1753         }
1754
1755 bce_init_nvram_get_flash_size:
1756         /* Write the flash config data to the shared memory interface. */
1757         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2) &
1758             BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
1759         if (val)
1760                 sc->bce_flash_size = val;
1761         else
1762                 sc->bce_flash_size = sc->bce_flash_info->total_size;
1763
1764         DBPRINT(sc, BCE_INFO_LOAD, "%s() flash->total_size = 0x%08X\n",
1765                 __func__, sc->bce_flash_info->total_size);
1766
1767         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
1768
1769         return rc;
1770 }
1771
1772
1773 /****************************************************************************/
1774 /* Read an arbitrary range of data from NVRAM.                              */
1775 /*                                                                          */
1776 /* Prepares the NVRAM interface for access and reads the requested data     */
1777 /* into the supplied buffer.                                                */
1778 /*                                                                          */
1779 /* Returns:                                                                 */
1780 /*   0 on success and the data read, positive value on failure.             */
1781 /****************************************************************************/
1782 static int
1783 bce_nvram_read(struct bce_softc *sc, uint32_t offset, uint8_t *ret_buf,
1784                int buf_size)
1785 {
1786         uint32_t cmd_flags, offset32, len32, extra;
1787         int rc = 0;
1788
1789         if (buf_size == 0)
1790                 return 0;
1791
1792         /* Request access to the flash interface. */
1793         rc = bce_acquire_nvram_lock(sc);
1794         if (rc != 0)
1795                 return rc;
1796
1797         /* Enable access to flash interface */
1798         bce_enable_nvram_access(sc);
1799
1800         len32 = buf_size;
1801         offset32 = offset;
1802         extra = 0;
1803
1804         cmd_flags = 0;
1805
1806         /* XXX should we release nvram lock if read_dword() fails? */
1807         if (offset32 & 3) {
1808                 uint8_t buf[4];
1809                 uint32_t pre_len;
1810
1811                 offset32 &= ~3;
1812                 pre_len = 4 - (offset & 3);
1813
1814                 if (pre_len >= len32) {
1815                         pre_len = len32;
1816                         cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
1817                 } else {
1818                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1819                 }
1820
1821                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1822                 if (rc)
1823                         return rc;
1824
1825                 memcpy(ret_buf, buf + (offset & 3), pre_len);
1826
1827                 offset32 += 4;
1828                 ret_buf += pre_len;
1829                 len32 -= pre_len;
1830         }
1831
1832         if (len32 & 3) {
1833                 extra = 4 - (len32 & 3);
1834                 len32 = (len32 + 4) & ~3;
1835         }
1836
1837         if (len32 == 4) {
1838                 uint8_t buf[4];
1839
1840                 if (cmd_flags)
1841                         cmd_flags = BCE_NVM_COMMAND_LAST;
1842                 else
1843                         cmd_flags = BCE_NVM_COMMAND_FIRST |
1844                                     BCE_NVM_COMMAND_LAST;
1845
1846                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1847
1848                 memcpy(ret_buf, buf, 4 - extra);
1849         } else if (len32 > 0) {
1850                 uint8_t buf[4];
1851
1852                 /* Read the first word. */
1853                 if (cmd_flags)
1854                         cmd_flags = 0;
1855                 else
1856                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1857
1858                 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
1859
1860                 /* Advance to the next dword. */
1861                 offset32 += 4;
1862                 ret_buf += 4;
1863                 len32 -= 4;
1864
1865                 while (len32 > 4 && rc == 0) {
1866                         rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
1867
1868                         /* Advance to the next dword. */
1869                         offset32 += 4;
1870                         ret_buf += 4;
1871                         len32 -= 4;
1872                 }
1873
1874                 if (rc)
1875                         goto bce_nvram_read_locked_exit;
1876
1877                 cmd_flags = BCE_NVM_COMMAND_LAST;
1878                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1879
1880                 memcpy(ret_buf, buf, 4 - extra);
1881         }
1882
1883 bce_nvram_read_locked_exit:
1884         /* Disable access to flash interface and release the lock. */
1885         bce_disable_nvram_access(sc);
1886         bce_release_nvram_lock(sc);
1887
1888         return rc;
1889 }
1890
1891
1892 /****************************************************************************/
1893 /* Verifies that NVRAM is accessible and contains valid data.               */
1894 /*                                                                          */
1895 /* Reads the configuration data from NVRAM and verifies that the CRC is     */
1896 /* correct.                                                                 */
1897 /*                                                                          */
1898 /* Returns:                                                                 */
1899 /*   0 on success, positive value on failure.                               */
1900 /****************************************************************************/
1901 static int
1902 bce_nvram_test(struct bce_softc *sc)
1903 {
1904         uint32_t buf[BCE_NVRAM_SIZE / 4];
1905         uint32_t magic, csum;
1906         uint8_t *data = (uint8_t *)buf;
1907         int rc = 0;
1908
1909         /*
1910          * Check that the device NVRAM is valid by reading
1911          * the magic value at offset 0.
1912          */
1913         rc = bce_nvram_read(sc, 0, data, 4);
1914         if (rc != 0)
1915                 return rc;
1916
1917         magic = be32toh(buf[0]);
1918         if (magic != BCE_NVRAM_MAGIC) {
1919                 if_printf(&sc->arpcom.ac_if,
1920                           "Invalid NVRAM magic value! Expected: 0x%08X, "
1921                           "Found: 0x%08X\n", BCE_NVRAM_MAGIC, magic);
1922                 return ENODEV;
1923         }
1924
1925         /*
1926          * Verify that the device NVRAM includes valid
1927          * configuration data.
1928          */
1929         rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE);
1930         if (rc != 0)
1931                 return rc;
1932
1933         csum = ether_crc32_le(data, 0x100);
1934         if (csum != BCE_CRC32_RESIDUAL) {
1935                 if_printf(&sc->arpcom.ac_if,
1936                           "Invalid Manufacturing Information NVRAM CRC! "
1937                           "Expected: 0x%08X, Found: 0x%08X\n",
1938                           BCE_CRC32_RESIDUAL, csum);
1939                 return ENODEV;
1940         }
1941
1942         csum = ether_crc32_le(data + 0x100, 0x100);
1943         if (csum != BCE_CRC32_RESIDUAL) {
1944                 if_printf(&sc->arpcom.ac_if,
1945                           "Invalid Feature Configuration Information "
1946                           "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
1947                           BCE_CRC32_RESIDUAL, csum);
1948                 rc = ENODEV;
1949         }
1950         return rc;
1951 }
1952
1953
1954 /****************************************************************************/
1955 /* Identifies the current media type of the controller and sets the PHY     */
1956 /* address.                                                                 */
1957 /*                                                                          */
1958 /* Returns:                                                                 */
1959 /*   Nothing.                                                               */
1960 /****************************************************************************/
1961 static void
1962 bce_get_media(struct bce_softc *sc)
1963 {
1964         uint32_t val;
1965
1966         sc->bce_phy_addr = 1;
1967
1968         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1969             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1970                 uint32_t val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
1971                 uint32_t bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
1972                 uint32_t strap;
1973
1974                 /*
1975                  * The BCM5709S is software configurable
1976                  * for Copper or SerDes operation.
1977                  */
1978                 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
1979                         return;
1980                 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
1981                         sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1982                         return;
1983                 }
1984
1985                 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) {
1986                         strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
1987                 } else {
1988                         strap =
1989                         (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
1990                 }
1991
1992                 if (pci_get_function(sc->bce_dev) == 0) {
1993                         switch (strap) {
1994                         case 0x4:
1995                         case 0x5:
1996                         case 0x6:
1997                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1998                                 break;
1999                         }
2000                 } else {
2001                         switch (strap) {
2002                         case 0x1:
2003                         case 0x2:
2004                         case 0x4:
2005                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2006                                 break;
2007                         }
2008                 }
2009         } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
2010                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2011         }
2012
2013         if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
2014                 sc->bce_flags |= BCE_NO_WOL_FLAG;
2015                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
2016                         sc->bce_phy_addr = 2;
2017                         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
2018                         if (val & BCE_SHARED_HW_CFG_PHY_2_5G)
2019                                 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
2020                 }
2021         } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
2022             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) {
2023                 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
2024         }
2025 }
2026
2027
2028 /****************************************************************************/
2029 /* Free any DMA memory owned by the driver.                                 */
2030 /*                                                                          */
2031 /* Scans through each data structre that requires DMA memory and frees      */
2032 /* the memory if allocated.                                                 */
2033 /*                                                                          */
2034 /* Returns:                                                                 */
2035 /*   Nothing.                                                               */
2036 /****************************************************************************/
2037 static void
2038 bce_dma_free(struct bce_softc *sc)
2039 {
2040         int i;
2041
2042         /* Destroy the status block. */
2043         if (sc->status_tag != NULL) {
2044                 if (sc->status_block != NULL) {
2045                         bus_dmamap_unload(sc->status_tag, sc->status_map);
2046                         bus_dmamem_free(sc->status_tag, sc->status_block,
2047                                         sc->status_map);
2048                 }
2049                 bus_dma_tag_destroy(sc->status_tag);
2050         }
2051
2052         /* Destroy the statistics block. */
2053         if (sc->stats_tag != NULL) {
2054                 if (sc->stats_block != NULL) {
2055                         bus_dmamap_unload(sc->stats_tag, sc->stats_map);
2056                         bus_dmamem_free(sc->stats_tag, sc->stats_block,
2057                                         sc->stats_map);
2058                 }
2059                 bus_dma_tag_destroy(sc->stats_tag);
2060         }
2061
2062         /* Destroy the CTX DMA stuffs. */
2063         if (sc->ctx_tag != NULL) {
2064                 for (i = 0; i < sc->ctx_pages; i++) {
2065                         if (sc->ctx_block[i] != NULL) {
2066                                 bus_dmamap_unload(sc->ctx_tag, sc->ctx_map[i]);
2067                                 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2068                                                 sc->ctx_map[i]);
2069                         }
2070                 }
2071                 bus_dma_tag_destroy(sc->ctx_tag);
2072         }
2073
2074         /* Destroy the TX buffer descriptor DMA stuffs. */
2075         if (sc->tx_bd_chain_tag != NULL) {
2076                 for (i = 0; i < sc->tx_pages; i++) {
2077                         if (sc->tx_bd_chain[i] != NULL) {
2078                                 bus_dmamap_unload(sc->tx_bd_chain_tag,
2079                                                   sc->tx_bd_chain_map[i]);
2080                                 bus_dmamem_free(sc->tx_bd_chain_tag,
2081                                                 sc->tx_bd_chain[i],
2082                                                 sc->tx_bd_chain_map[i]);
2083                         }
2084                 }
2085                 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
2086         }
2087
2088         /* Destroy the RX buffer descriptor DMA stuffs. */
2089         if (sc->rx_bd_chain_tag != NULL) {
2090                 for (i = 0; i < sc->rx_pages; i++) {
2091                         if (sc->rx_bd_chain[i] != NULL) {
2092                                 bus_dmamap_unload(sc->rx_bd_chain_tag,
2093                                                   sc->rx_bd_chain_map[i]);
2094                                 bus_dmamem_free(sc->rx_bd_chain_tag,
2095                                                 sc->rx_bd_chain[i],
2096                                                 sc->rx_bd_chain_map[i]);
2097                         }
2098                 }
2099                 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
2100         }
2101
2102         /* Destroy the TX mbuf DMA stuffs. */
2103         if (sc->tx_mbuf_tag != NULL) {
2104                 for (i = 0; i < TOTAL_TX_BD(sc); i++) {
2105                         /* Must have been unloaded in bce_stop() */
2106                         KKASSERT(sc->tx_mbuf_ptr[i] == NULL);
2107                         bus_dmamap_destroy(sc->tx_mbuf_tag,
2108                                            sc->tx_mbuf_map[i]);
2109                 }
2110                 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2111         }
2112
2113         /* Destroy the RX mbuf DMA stuffs. */
2114         if (sc->rx_mbuf_tag != NULL) {
2115                 for (i = 0; i < TOTAL_RX_BD(sc); i++) {
2116                         /* Must have been unloaded in bce_stop() */
2117                         KKASSERT(sc->rx_mbuf_ptr[i] == NULL);
2118                         bus_dmamap_destroy(sc->rx_mbuf_tag,
2119                                            sc->rx_mbuf_map[i]);
2120                 }
2121                 bus_dmamap_destroy(sc->rx_mbuf_tag, sc->rx_mbuf_tmpmap);
2122                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2123         }
2124
2125         /* Destroy the parent tag */
2126         if (sc->parent_tag != NULL)
2127                 bus_dma_tag_destroy(sc->parent_tag);
2128
2129         if (sc->tx_bd_chain_map != NULL)
2130                 kfree(sc->tx_bd_chain_map, M_DEVBUF);
2131         if (sc->tx_bd_chain != NULL)
2132                 kfree(sc->tx_bd_chain, M_DEVBUF);
2133         if (sc->tx_bd_chain_paddr != NULL)
2134                 kfree(sc->tx_bd_chain_paddr, M_DEVBUF);
2135
2136         if (sc->rx_bd_chain_map != NULL)
2137                 kfree(sc->rx_bd_chain_map, M_DEVBUF);
2138         if (sc->rx_bd_chain != NULL)
2139                 kfree(sc->rx_bd_chain, M_DEVBUF);
2140         if (sc->rx_bd_chain_paddr != NULL)
2141                 kfree(sc->rx_bd_chain_paddr, M_DEVBUF);
2142
2143         if (sc->tx_mbuf_map != NULL)
2144                 kfree(sc->tx_mbuf_map, M_DEVBUF);
2145         if (sc->tx_mbuf_ptr != NULL)
2146                 kfree(sc->tx_mbuf_ptr, M_DEVBUF);
2147
2148         if (sc->rx_mbuf_map != NULL)
2149                 kfree(sc->rx_mbuf_map, M_DEVBUF);
2150         if (sc->rx_mbuf_ptr != NULL)
2151                 kfree(sc->rx_mbuf_ptr, M_DEVBUF);
2152         if (sc->rx_mbuf_paddr != NULL)
2153                 kfree(sc->rx_mbuf_paddr, M_DEVBUF);
2154 }
2155
2156
2157 /****************************************************************************/
2158 /* Get DMA memory from the OS.                                              */
2159 /*                                                                          */
2160 /* Validates that the OS has provided DMA buffers in response to a          */
2161 /* bus_dmamap_load() call and saves the physical address of those buffers.  */
2162 /* When the callback is used the OS will return 0 for the mapping function  */
2163 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any  */
2164 /* failures back to the caller.                                             */
2165 /*                                                                          */
2166 /* Returns:                                                                 */
2167 /*   Nothing.                                                               */
2168 /****************************************************************************/
2169 static void
2170 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2171 {
2172         bus_addr_t *busaddr = arg;
2173
2174         /*
2175          * Simulate a mapping failure.
2176          * XXX not correct.
2177          */
2178         DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2179                 kprintf("bce: %s(%d): Simulating DMA mapping error.\n",
2180                         __FILE__, __LINE__);
2181                 error = ENOMEM);
2182
2183         /* Check for an error and signal the caller that an error occurred. */
2184         if (error)
2185                 return;
2186
2187         KASSERT(nseg == 1, ("only one segment is allowed"));
2188         *busaddr = segs->ds_addr;
2189 }
2190
2191
2192 /****************************************************************************/
2193 /* Allocate any DMA memory needed by the driver.                            */
2194 /*                                                                          */
2195 /* Allocates DMA memory needed for the various global structures needed by  */
2196 /* hardware.                                                                */
2197 /*                                                                          */
2198 /* Memory alignment requirements:                                           */
2199 /* -----------------+----------+----------+----------+----------+           */
2200 /*  Data Structure  |   5706   |   5708   |   5709   |   5716   |           */
2201 /* -----------------+----------+----------+----------+----------+           */
2202 /* Status Block     | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |           */
2203 /* Statistics Block | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |           */
2204 /* RX Buffers       | 16 bytes | 16 bytes | 16 bytes | 16 bytes |           */
2205 /* PG Buffers       |   none   |   none   |   none   |   none   |           */
2206 /* TX Buffers       |   none   |   none   |   none   |   none   |           */
2207 /* Chain Pages(1)   |   4KiB   |   4KiB   |   4KiB   |   4KiB   |           */
2208 /* Context Pages(1) |   N/A    |   N/A    |   4KiB   |   4KiB   |           */
2209 /* -----------------+----------+----------+----------+----------+           */
2210 /*                                                                          */
2211 /* (1) Must align with CPU page size (BCM_PAGE_SZIE).                       */
2212 /*                                                                          */
2213 /* Returns:                                                                 */
2214 /*   0 for success, positive value for failure.                             */
2215 /****************************************************************************/
2216 static int
2217 bce_dma_alloc(struct bce_softc *sc)
2218 {
2219         struct ifnet *ifp = &sc->arpcom.ac_if;
2220         int i, j, rc = 0, pages;
2221         bus_addr_t busaddr, max_busaddr;
2222         bus_size_t status_align, stats_align;
2223
2224         pages = device_getenv_int(sc->bce_dev, "rx_pages", bce_rx_pages);
2225         if (pages <= 0 || pages > RX_PAGES_MAX || !powerof2(pages)) {
2226                 device_printf(sc->bce_dev, "invalid # of RX pages\n");
2227                 pages = RX_PAGES_DEFAULT;
2228         }
2229         sc->rx_pages = pages;
2230
2231         pages = device_getenv_int(sc->bce_dev, "tx_pages", bce_tx_pages);
2232         if (pages <= 0 || pages > TX_PAGES_MAX || !powerof2(pages)) {
2233                 device_printf(sc->bce_dev, "invalid # of TX pages\n");
2234                 pages = TX_PAGES_DEFAULT;
2235         }
2236         sc->tx_pages = pages;
2237
2238         sc->tx_bd_chain_map = kmalloc(sizeof(bus_dmamap_t) * sc->tx_pages,
2239             M_DEVBUF, M_WAITOK | M_ZERO);
2240         sc->tx_bd_chain = kmalloc(sizeof(struct tx_bd *) * sc->tx_pages,
2241             M_DEVBUF, M_WAITOK | M_ZERO);
2242         sc->tx_bd_chain_paddr = kmalloc(sizeof(bus_addr_t) * sc->tx_pages,
2243             M_DEVBUF, M_WAITOK | M_ZERO);
2244
2245         sc->rx_bd_chain_map = kmalloc(sizeof(bus_dmamap_t) * sc->rx_pages,
2246             M_DEVBUF, M_WAITOK | M_ZERO);
2247         sc->rx_bd_chain = kmalloc(sizeof(struct rx_bd *) * sc->rx_pages,
2248             M_DEVBUF, M_WAITOK | M_ZERO);
2249         sc->rx_bd_chain_paddr = kmalloc(sizeof(bus_addr_t) * sc->rx_pages,
2250             M_DEVBUF, M_WAITOK | M_ZERO);
2251
2252         sc->tx_mbuf_map = kmalloc(sizeof(bus_dmamap_t) * TOTAL_TX_BD(sc),
2253             M_DEVBUF, M_WAITOK | M_ZERO);
2254         sc->tx_mbuf_ptr = kmalloc(sizeof(struct mbuf *) * TOTAL_TX_BD(sc),
2255             M_DEVBUF, M_WAITOK | M_ZERO);
2256
2257         sc->rx_mbuf_map = kmalloc(sizeof(bus_dmamap_t) * TOTAL_RX_BD(sc),
2258             M_DEVBUF, M_WAITOK | M_ZERO);
2259         sc->rx_mbuf_ptr = kmalloc(sizeof(struct mbuf *) * TOTAL_RX_BD(sc),
2260             M_DEVBUF, M_WAITOK | M_ZERO);
2261         sc->rx_mbuf_paddr = kmalloc(sizeof(bus_addr_t) * TOTAL_RX_BD(sc),
2262             M_DEVBUF, M_WAITOK | M_ZERO);
2263
2264         /*
2265          * The embedded PCIe to PCI-X bridge (EPB)
2266          * in the 5708 cannot address memory above
2267          * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
2268          */
2269         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
2270                 max_busaddr = BCE_BUS_SPACE_MAXADDR;
2271         else
2272                 max_busaddr = BUS_SPACE_MAXADDR;
2273
2274         /*
2275          * BCM5709 and BCM5716 uses host memory as cache for context memory.
2276          */
2277         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2278             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2279                 sc->ctx_pages = BCE_CTX_BLK_SZ / BCM_PAGE_SIZE;
2280                 if (sc->ctx_pages == 0)
2281                         sc->ctx_pages = 1;
2282                 if (sc->ctx_pages > BCE_CTX_PAGES) {
2283                         device_printf(sc->bce_dev, "excessive ctx pages %d\n",
2284                             sc->ctx_pages);
2285                         return ENOMEM;
2286                 }
2287                 status_align = 16;
2288                 stats_align = 16;
2289         } else {
2290                 status_align = 8;
2291                 stats_align = 8;
2292         }
2293
2294         /*
2295          * Allocate the parent bus DMA tag appropriate for PCI.
2296          */
2297         rc = bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY,
2298                                 max_busaddr, BUS_SPACE_MAXADDR,
2299                                 NULL, NULL,
2300                                 BUS_SPACE_MAXSIZE_32BIT, 0,
2301                                 BUS_SPACE_MAXSIZE_32BIT,
2302                                 0, &sc->parent_tag);
2303         if (rc != 0) {
2304                 if_printf(ifp, "Could not allocate parent DMA tag!\n");
2305                 return rc;
2306         }
2307
2308         /*
2309          * Allocate status block.
2310          */
2311         sc->status_block = bus_dmamem_coherent_any(sc->parent_tag,
2312                                 status_align, BCE_STATUS_BLK_SZ,
2313                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2314                                 &sc->status_tag, &sc->status_map,
2315                                 &sc->status_block_paddr);
2316         if (sc->status_block == NULL) {
2317                 if_printf(ifp, "Could not allocate status block!\n");
2318                 return ENOMEM;
2319         }
2320
2321         /*
2322          * Allocate statistics block.
2323          */
2324         sc->stats_block = bus_dmamem_coherent_any(sc->parent_tag,
2325                                 stats_align, BCE_STATS_BLK_SZ,
2326                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2327                                 &sc->stats_tag, &sc->stats_map,
2328                                 &sc->stats_block_paddr);
2329         if (sc->stats_block == NULL) {
2330                 if_printf(ifp, "Could not allocate statistics block!\n");
2331                 return ENOMEM;
2332         }
2333
2334         /*
2335          * Allocate context block, if needed
2336          */
2337         if (sc->ctx_pages != 0) {
2338                 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2339                                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2340                                         NULL, NULL,
2341                                         BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
2342                                         0, &sc->ctx_tag);
2343                 if (rc != 0) {
2344                         if_printf(ifp, "Could not allocate "
2345                                   "context block DMA tag!\n");
2346                         return rc;
2347                 }
2348
2349                 for (i = 0; i < sc->ctx_pages; i++) {
2350                         rc = bus_dmamem_alloc(sc->ctx_tag,
2351                                               (void **)&sc->ctx_block[i],
2352                                               BUS_DMA_WAITOK | BUS_DMA_ZERO |
2353                                               BUS_DMA_COHERENT,
2354                                               &sc->ctx_map[i]);
2355                         if (rc != 0) {
2356                                 if_printf(ifp, "Could not allocate %dth context "
2357                                           "DMA memory!\n", i);
2358                                 return rc;
2359                         }
2360
2361                         rc = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
2362                                              sc->ctx_block[i], BCM_PAGE_SIZE,
2363                                              bce_dma_map_addr, &busaddr,
2364                                              BUS_DMA_WAITOK);
2365                         if (rc != 0) {
2366                                 if (rc == EINPROGRESS) {
2367                                         panic("%s coherent memory loading "
2368                                               "is still in progress!", ifp->if_xname);
2369                                 }
2370                                 if_printf(ifp, "Could not map %dth context "
2371                                           "DMA memory!\n", i);
2372                                 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2373                                                 sc->ctx_map[i]);
2374                                 sc->ctx_block[i] = NULL;
2375                                 return rc;
2376                         }
2377                         sc->ctx_paddr[i] = busaddr;
2378                 }
2379         }
2380
2381         /*
2382          * Create a DMA tag for the TX buffer descriptor chain,
2383          * allocate and clear the  memory, and fetch the
2384          * physical address of the block.
2385          */
2386         rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2387                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2388                                 NULL, NULL,
2389                                 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ,
2390                                 0, &sc->tx_bd_chain_tag);
2391         if (rc != 0) {
2392                 if_printf(ifp, "Could not allocate "
2393                           "TX descriptor chain DMA tag!\n");
2394                 return rc;
2395         }
2396
2397         for (i = 0; i < sc->tx_pages; i++) {
2398                 rc = bus_dmamem_alloc(sc->tx_bd_chain_tag,
2399                                       (void **)&sc->tx_bd_chain[i],
2400                                       BUS_DMA_WAITOK | BUS_DMA_ZERO |
2401                                       BUS_DMA_COHERENT,
2402                                       &sc->tx_bd_chain_map[i]);
2403                 if (rc != 0) {
2404                         if_printf(ifp, "Could not allocate %dth TX descriptor "
2405                                   "chain DMA memory!\n", i);
2406                         return rc;
2407                 }
2408
2409                 rc = bus_dmamap_load(sc->tx_bd_chain_tag,
2410                                      sc->tx_bd_chain_map[i],
2411                                      sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ,
2412                                      bce_dma_map_addr, &busaddr,
2413                                      BUS_DMA_WAITOK);
2414                 if (rc != 0) {
2415                         if (rc == EINPROGRESS) {
2416                                 panic("%s coherent memory loading "
2417                                       "is still in progress!", ifp->if_xname);
2418                         }
2419                         if_printf(ifp, "Could not map %dth TX descriptor "
2420                                   "chain DMA memory!\n", i);
2421                         bus_dmamem_free(sc->tx_bd_chain_tag,
2422                                         sc->tx_bd_chain[i],
2423                                         sc->tx_bd_chain_map[i]);
2424                         sc->tx_bd_chain[i] = NULL;
2425                         return rc;
2426                 }
2427
2428                 sc->tx_bd_chain_paddr[i] = busaddr;
2429                 /* DRC - Fix for 64 bit systems. */
2430                 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n",
2431                         i, (uint32_t)sc->tx_bd_chain_paddr[i]);
2432         }
2433
2434         /* Create a DMA tag for TX mbufs. */
2435         rc = bus_dma_tag_create(sc->parent_tag, 1, 0,
2436                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2437                                 NULL, NULL,
2438                                 /* BCE_MAX_JUMBO_ETHER_MTU_VLAN */MCLBYTES,
2439                                 BCE_MAX_SEGMENTS, MCLBYTES,
2440                                 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
2441                                 BUS_DMA_ONEBPAGE,
2442                                 &sc->tx_mbuf_tag);
2443         if (rc != 0) {
2444                 if_printf(ifp, "Could not allocate TX mbuf DMA tag!\n");
2445                 return rc;
2446         }
2447
2448         /* Create DMA maps for the TX mbufs clusters. */
2449         for (i = 0; i < TOTAL_TX_BD(sc); i++) {
2450                 rc = bus_dmamap_create(sc->tx_mbuf_tag,
2451                                        BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2452                                        &sc->tx_mbuf_map[i]);
2453                 if (rc != 0) {
2454                         for (j = 0; j < i; ++j) {
2455                                 bus_dmamap_destroy(sc->tx_mbuf_tag,
2456                                                    sc->tx_mbuf_map[i]);
2457                         }
2458                         bus_dma_tag_destroy(sc->tx_mbuf_tag);
2459                         sc->tx_mbuf_tag = NULL;
2460
2461                         if_printf(ifp, "Unable to create "
2462                                   "%dth TX mbuf DMA map!\n", i);
2463                         return rc;
2464                 }
2465         }
2466
2467         /*
2468          * Create a DMA tag for the RX buffer descriptor chain,
2469          * allocate and clear the  memory, and fetch the physical
2470          * address of the blocks.
2471          */
2472         rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2473                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2474                                 NULL, NULL,
2475                                 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
2476                                 0, &sc->rx_bd_chain_tag);
2477         if (rc != 0) {
2478                 if_printf(ifp, "Could not allocate "
2479                           "RX descriptor chain DMA tag!\n");
2480                 return rc;
2481         }
2482
2483         for (i = 0; i < sc->rx_pages; i++) {
2484                 rc = bus_dmamem_alloc(sc->rx_bd_chain_tag,
2485                                       (void **)&sc->rx_bd_chain[i],
2486                                       BUS_DMA_WAITOK | BUS_DMA_ZERO |
2487                                       BUS_DMA_COHERENT,
2488                                       &sc->rx_bd_chain_map[i]);
2489                 if (rc != 0) {
2490                         if_printf(ifp, "Could not allocate %dth RX descriptor "
2491                                   "chain DMA memory!\n", i);
2492                         return rc;
2493                 }
2494
2495                 rc = bus_dmamap_load(sc->rx_bd_chain_tag,
2496                                      sc->rx_bd_chain_map[i],
2497                                      sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ,
2498                                      bce_dma_map_addr, &busaddr,
2499                                      BUS_DMA_WAITOK);
2500                 if (rc != 0) {
2501                         if (rc == EINPROGRESS) {
2502                                 panic("%s coherent memory loading "
2503                                       "is still in progress!", ifp->if_xname);
2504                         }
2505                         if_printf(ifp, "Could not map %dth RX descriptor "
2506                                   "chain DMA memory!\n", i);
2507                         bus_dmamem_free(sc->rx_bd_chain_tag,
2508                                         sc->rx_bd_chain[i],
2509                                         sc->rx_bd_chain_map[i]);
2510                         sc->rx_bd_chain[i] = NULL;
2511                         return rc;
2512                 }
2513
2514                 sc->rx_bd_chain_paddr[i] = busaddr;
2515                 /* DRC - Fix for 64 bit systems. */
2516                 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n",
2517                         i, (uint32_t)sc->rx_bd_chain_paddr[i]);
2518         }
2519
2520         /* Create a DMA tag for RX mbufs. */
2521         rc = bus_dma_tag_create(sc->parent_tag, BCE_DMA_RX_ALIGN, 0,
2522                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2523                                 NULL, NULL,
2524                                 MCLBYTES, 1, MCLBYTES,
2525                                 BUS_DMA_ALLOCNOW | BUS_DMA_ALIGNED |
2526                                 BUS_DMA_WAITOK,
2527                                 &sc->rx_mbuf_tag);
2528         if (rc != 0) {
2529                 if_printf(ifp, "Could not allocate RX mbuf DMA tag!\n");
2530                 return rc;
2531         }
2532
2533         /* Create tmp DMA map for RX mbuf clusters. */
2534         rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2535                                &sc->rx_mbuf_tmpmap);
2536         if (rc != 0) {
2537                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2538                 sc->rx_mbuf_tag = NULL;
2539
2540                 if_printf(ifp, "Could not create RX mbuf tmp DMA map!\n");
2541                 return rc;
2542         }
2543
2544         /* Create DMA maps for the RX mbuf clusters. */
2545         for (i = 0; i < TOTAL_RX_BD(sc); i++) {
2546                 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2547                                        &sc->rx_mbuf_map[i]);
2548                 if (rc != 0) {
2549                         for (j = 0; j < i; ++j) {
2550                                 bus_dmamap_destroy(sc->rx_mbuf_tag,
2551                                                    sc->rx_mbuf_map[j]);
2552                         }
2553                         bus_dma_tag_destroy(sc->rx_mbuf_tag);
2554                         sc->rx_mbuf_tag = NULL;
2555
2556                         if_printf(ifp, "Unable to create "
2557                                   "%dth RX mbuf DMA map!\n", i);
2558                         return rc;
2559                 }
2560         }
2561         return 0;
2562 }
2563
2564
2565 /****************************************************************************/
2566 /* Firmware synchronization.                                                */
2567 /*                                                                          */
2568 /* Before performing certain events such as a chip reset, synchronize with  */
2569 /* the firmware first.                                                      */
2570 /*                                                                          */
2571 /* Returns:                                                                 */
2572 /*   0 for success, positive value for failure.                             */
2573 /****************************************************************************/
2574 static int
2575 bce_fw_sync(struct bce_softc *sc, uint32_t msg_data)
2576 {
2577         int i, rc = 0;
2578         uint32_t val;
2579
2580         /* Don't waste any time if we've timed out before. */
2581         if (sc->bce_fw_timed_out)
2582                 return EBUSY;
2583
2584         /* Increment the message sequence number. */
2585         sc->bce_fw_wr_seq++;
2586         msg_data |= sc->bce_fw_wr_seq;
2587
2588         DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data);
2589
2590         /* Send the message to the bootcode driver mailbox. */
2591         bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2592
2593         /* Wait for the bootcode to acknowledge the message. */
2594         for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2595                 /* Check for a response in the bootcode firmware mailbox. */
2596                 val = bce_shmem_rd(sc, BCE_FW_MB);
2597                 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
2598                         break;
2599                 DELAY(1000);
2600         }
2601
2602         /* If we've timed out, tell the bootcode that we've stopped waiting. */
2603         if ((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ) &&
2604             (msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0) {
2605                 if_printf(&sc->arpcom.ac_if,
2606                           "Firmware synchronization timeout! "
2607                           "msg_data = 0x%08X\n", msg_data);
2608
2609                 msg_data &= ~BCE_DRV_MSG_CODE;
2610                 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
2611
2612                 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2613
2614                 sc->bce_fw_timed_out = 1;
2615                 rc = EBUSY;
2616         }
2617         return rc;
2618 }
2619
2620
2621 /****************************************************************************/
2622 /* Load Receive Virtual 2 Physical (RV2P) processor firmware.               */
2623 /*                                                                          */
2624 /* Returns:                                                                 */
2625 /*   Nothing.                                                               */
2626 /****************************************************************************/
2627 static void
2628 bce_load_rv2p_fw(struct bce_softc *sc, uint32_t *rv2p_code,
2629                  uint32_t rv2p_code_len, uint32_t rv2p_proc)
2630 {
2631         int i;
2632         uint32_t val;
2633
2634         for (i = 0; i < rv2p_code_len; i += 8) {
2635                 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
2636                 rv2p_code++;
2637                 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
2638                 rv2p_code++;
2639
2640                 if (rv2p_proc == RV2P_PROC1) {
2641                         val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
2642                         REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
2643                 } else {
2644                         val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
2645                         REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
2646                 }
2647         }
2648
2649         /* Reset the processor, un-stall is done later. */
2650         if (rv2p_proc == RV2P_PROC1)
2651                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
2652         else
2653                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
2654 }
2655
2656
2657 /****************************************************************************/
2658 /* Load RISC processor firmware.                                            */
2659 /*                                                                          */
2660 /* Loads firmware from the file if_bcefw.h into the scratchpad memory       */
2661 /* associated with a particular processor.                                  */
2662 /*                                                                          */
2663 /* Returns:                                                                 */
2664 /*   Nothing.                                                               */
2665 /****************************************************************************/
2666 static void
2667 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
2668                 struct fw_info *fw)
2669 {
2670         uint32_t offset;
2671         int j;
2672
2673         bce_halt_cpu(sc, cpu_reg);
2674
2675         /* Load the Text area. */
2676         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2677         if (fw->text) {
2678                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4)
2679                         REG_WR_IND(sc, offset, fw->text[j]);
2680         }
2681
2682         /* Load the Data area. */
2683         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2684         if (fw->data) {
2685                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4)
2686                         REG_WR_IND(sc, offset, fw->data[j]);
2687         }
2688
2689         /* Load the SBSS area. */
2690         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2691         if (fw->sbss) {
2692                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4)
2693                         REG_WR_IND(sc, offset, fw->sbss[j]);
2694         }
2695
2696         /* Load the BSS area. */
2697         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2698         if (fw->bss) {
2699                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4)
2700                         REG_WR_IND(sc, offset, fw->bss[j]);
2701         }
2702
2703         /* Load the Read-Only area. */
2704         offset = cpu_reg->spad_base +
2705                 (fw->rodata_addr - cpu_reg->mips_view_base);
2706         if (fw->rodata) {
2707                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4)
2708                         REG_WR_IND(sc, offset, fw->rodata[j]);
2709         }
2710
2711         /* Clear the pre-fetch instruction and set the FW start address. */
2712         REG_WR_IND(sc, cpu_reg->inst, 0);
2713         REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
2714 }
2715
2716
2717 /****************************************************************************/
2718 /* Starts the RISC processor.                                               */
2719 /*                                                                          */
2720 /* Assumes the CPU starting address has already been set.                   */
2721 /*                                                                          */
2722 /* Returns:                                                                 */
2723 /*   Nothing.                                                               */
2724 /****************************************************************************/
2725 static void
2726 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2727 {
2728         uint32_t val;
2729
2730         /* Start the CPU. */
2731         val = REG_RD_IND(sc, cpu_reg->mode);
2732         val &= ~cpu_reg->mode_value_halt;
2733         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2734         REG_WR_IND(sc, cpu_reg->mode, val);
2735 }
2736
2737
2738 /****************************************************************************/
2739 /* Halts the RISC processor.                                                */
2740 /*                                                                          */
2741 /* Returns:                                                                 */
2742 /*   Nothing.                                                               */
2743 /****************************************************************************/
2744 static void
2745 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2746 {
2747         uint32_t val;
2748
2749         /* Halt the CPU. */
2750         val = REG_RD_IND(sc, cpu_reg->mode);
2751         val |= cpu_reg->mode_value_halt;
2752         REG_WR_IND(sc, cpu_reg->mode, val);
2753         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2754 }
2755
2756
2757 /****************************************************************************/
2758 /* Start the RX CPU.                                                        */
2759 /*                                                                          */
2760 /* Returns:                                                                 */
2761 /*   Nothing.                                                               */
2762 /****************************************************************************/
2763 static void
2764 bce_start_rxp_cpu(struct bce_softc *sc)
2765 {
2766         struct cpu_reg cpu_reg;
2767
2768         cpu_reg.mode = BCE_RXP_CPU_MODE;
2769         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2770         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2771         cpu_reg.state = BCE_RXP_CPU_STATE;
2772         cpu_reg.state_value_clear = 0xffffff;
2773         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2774         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2775         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2776         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2777         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2778         cpu_reg.spad_base = BCE_RXP_SCRATCH;
2779         cpu_reg.mips_view_base = 0x8000000;
2780
2781         bce_start_cpu(sc, &cpu_reg);
2782 }
2783
2784
2785 /****************************************************************************/
2786 /* Initialize the RX CPU.                                                   */
2787 /*                                                                          */
2788 /* Returns:                                                                 */
2789 /*   Nothing.                                                               */
2790 /****************************************************************************/
2791 static void
2792 bce_init_rxp_cpu(struct bce_softc *sc)
2793 {
2794         struct cpu_reg cpu_reg;
2795         struct fw_info fw;
2796
2797         cpu_reg.mode = BCE_RXP_CPU_MODE;
2798         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2799         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2800         cpu_reg.state = BCE_RXP_CPU_STATE;
2801         cpu_reg.state_value_clear = 0xffffff;
2802         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2803         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2804         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2805         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2806         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2807         cpu_reg.spad_base = BCE_RXP_SCRATCH;
2808         cpu_reg.mips_view_base = 0x8000000;
2809
2810         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2811             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2812                 fw.ver_major = bce_RXP_b09FwReleaseMajor;
2813                 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
2814                 fw.ver_fix = bce_RXP_b09FwReleaseFix;
2815                 fw.start_addr = bce_RXP_b09FwStartAddr;
2816
2817                 fw.text_addr = bce_RXP_b09FwTextAddr;
2818                 fw.text_len = bce_RXP_b09FwTextLen;
2819                 fw.text_index = 0;
2820                 fw.text = bce_RXP_b09FwText;
2821
2822                 fw.data_addr = bce_RXP_b09FwDataAddr;
2823                 fw.data_len = bce_RXP_b09FwDataLen;
2824                 fw.data_index = 0;
2825                 fw.data = bce_RXP_b09FwData;
2826
2827                 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
2828                 fw.sbss_len = bce_RXP_b09FwSbssLen;
2829                 fw.sbss_index = 0;
2830                 fw.sbss = bce_RXP_b09FwSbss;
2831
2832                 fw.bss_addr = bce_RXP_b09FwBssAddr;
2833                 fw.bss_len = bce_RXP_b09FwBssLen;
2834                 fw.bss_index = 0;
2835                 fw.bss = bce_RXP_b09FwBss;
2836
2837                 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
2838                 fw.rodata_len = bce_RXP_b09FwRodataLen;
2839                 fw.rodata_index = 0;
2840                 fw.rodata = bce_RXP_b09FwRodata;
2841         } else {
2842                 fw.ver_major = bce_RXP_b06FwReleaseMajor;
2843                 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
2844                 fw.ver_fix = bce_RXP_b06FwReleaseFix;
2845                 fw.start_addr = bce_RXP_b06FwStartAddr;
2846
2847                 fw.text_addr = bce_RXP_b06FwTextAddr;
2848                 fw.text_len = bce_RXP_b06FwTextLen;
2849                 fw.text_index = 0;
2850                 fw.text = bce_RXP_b06FwText;
2851
2852                 fw.data_addr = bce_RXP_b06FwDataAddr;
2853                 fw.data_len = bce_RXP_b06FwDataLen;
2854                 fw.data_index = 0;
2855                 fw.data = bce_RXP_b06FwData;
2856
2857                 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
2858                 fw.sbss_len = bce_RXP_b06FwSbssLen;
2859                 fw.sbss_index = 0;
2860                 fw.sbss = bce_RXP_b06FwSbss;
2861
2862                 fw.bss_addr = bce_RXP_b06FwBssAddr;
2863                 fw.bss_len = bce_RXP_b06FwBssLen;
2864                 fw.bss_index = 0;
2865                 fw.bss = bce_RXP_b06FwBss;
2866
2867                 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
2868                 fw.rodata_len = bce_RXP_b06FwRodataLen;
2869                 fw.rodata_index = 0;
2870                 fw.rodata = bce_RXP_b06FwRodata;
2871         }
2872
2873         DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
2874         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2875         /* Delay RXP start until initialization is complete. */
2876 }
2877
2878
2879 /****************************************************************************/
2880 /* Initialize the TX CPU.                                                   */
2881 /*                                                                          */
2882 /* Returns:                                                                 */
2883 /*   Nothing.                                                               */
2884 /****************************************************************************/
2885 static void
2886 bce_init_txp_cpu(struct bce_softc *sc)
2887 {
2888         struct cpu_reg cpu_reg;
2889         struct fw_info fw;
2890
2891         cpu_reg.mode = BCE_TXP_CPU_MODE;
2892         cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
2893         cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
2894         cpu_reg.state = BCE_TXP_CPU_STATE;
2895         cpu_reg.state_value_clear = 0xffffff;
2896         cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
2897         cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
2898         cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
2899         cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
2900         cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
2901         cpu_reg.spad_base = BCE_TXP_SCRATCH;
2902         cpu_reg.mips_view_base = 0x8000000;
2903
2904         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2905             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2906                 fw.ver_major = bce_TXP_b09FwReleaseMajor;
2907                 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
2908                 fw.ver_fix = bce_TXP_b09FwReleaseFix;
2909                 fw.start_addr = bce_TXP_b09FwStartAddr;
2910
2911                 fw.text_addr = bce_TXP_b09FwTextAddr;
2912                 fw.text_len = bce_TXP_b09FwTextLen;
2913                 fw.text_index = 0;
2914                 fw.text = bce_TXP_b09FwText;
2915
2916                 fw.data_addr = bce_TXP_b09FwDataAddr;
2917                 fw.data_len = bce_TXP_b09FwDataLen;
2918                 fw.data_index = 0;
2919                 fw.data = bce_TXP_b09FwData;
2920
2921                 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
2922                 fw.sbss_len = bce_TXP_b09FwSbssLen;
2923                 fw.sbss_index = 0;
2924                 fw.sbss = bce_TXP_b09FwSbss;
2925
2926                 fw.bss_addr = bce_TXP_b09FwBssAddr;
2927                 fw.bss_len = bce_TXP_b09FwBssLen;
2928                 fw.bss_index = 0;
2929                 fw.bss = bce_TXP_b09FwBss;
2930
2931                 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
2932                 fw.rodata_len = bce_TXP_b09FwRodataLen;
2933                 fw.rodata_index = 0;
2934                 fw.rodata = bce_TXP_b09FwRodata;
2935         } else {
2936                 fw.ver_major = bce_TXP_b06FwReleaseMajor;
2937                 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
2938                 fw.ver_fix = bce_TXP_b06FwReleaseFix;
2939                 fw.start_addr = bce_TXP_b06FwStartAddr;
2940
2941                 fw.text_addr = bce_TXP_b06FwTextAddr;
2942                 fw.text_len = bce_TXP_b06FwTextLen;
2943                 fw.text_index = 0;
2944                 fw.text = bce_TXP_b06FwText;
2945
2946                 fw.data_addr = bce_TXP_b06FwDataAddr;
2947                 fw.data_len = bce_TXP_b06FwDataLen;
2948                 fw.data_index = 0;
2949                 fw.data = bce_TXP_b06FwData;
2950
2951                 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
2952                 fw.sbss_len = bce_TXP_b06FwSbssLen;
2953                 fw.sbss_index = 0;
2954                 fw.sbss = bce_TXP_b06FwSbss;
2955
2956                 fw.bss_addr = bce_TXP_b06FwBssAddr;
2957                 fw.bss_len = bce_TXP_b06FwBssLen;
2958                 fw.bss_index = 0;
2959                 fw.bss = bce_TXP_b06FwBss;
2960
2961                 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
2962                 fw.rodata_len = bce_TXP_b06FwRodataLen;
2963                 fw.rodata_index = 0;
2964                 fw.rodata = bce_TXP_b06FwRodata;
2965         }
2966
2967         DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
2968         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2969         bce_start_cpu(sc, &cpu_reg);
2970 }
2971
2972
2973 /****************************************************************************/
2974 /* Initialize the TPAT CPU.                                                 */
2975 /*                                                                          */
2976 /* Returns:                                                                 */
2977 /*   Nothing.                                                               */
2978 /****************************************************************************/
2979 static void
2980 bce_init_tpat_cpu(struct bce_softc *sc)
2981 {
2982         struct cpu_reg cpu_reg;
2983         struct fw_info fw;
2984
2985         cpu_reg.mode = BCE_TPAT_CPU_MODE;
2986         cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
2987         cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
2988         cpu_reg.state = BCE_TPAT_CPU_STATE;
2989         cpu_reg.state_value_clear = 0xffffff;
2990         cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
2991         cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
2992         cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
2993         cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
2994         cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
2995         cpu_reg.spad_base = BCE_TPAT_SCRATCH;
2996         cpu_reg.mips_view_base = 0x8000000;
2997
2998         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2999             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3000                 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
3001                 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
3002                 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
3003                 fw.start_addr = bce_TPAT_b09FwStartAddr;
3004
3005                 fw.text_addr = bce_TPAT_b09FwTextAddr;
3006                 fw.text_len = bce_TPAT_b09FwTextLen;
3007                 fw.text_index = 0;
3008                 fw.text = bce_TPAT_b09FwText;
3009
3010                 fw.data_addr = bce_TPAT_b09FwDataAddr;
3011                 fw.data_len = bce_TPAT_b09FwDataLen;
3012                 fw.data_index = 0;
3013                 fw.data = bce_TPAT_b09FwData;
3014
3015                 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
3016                 fw.sbss_len = bce_TPAT_b09FwSbssLen;
3017                 fw.sbss_index = 0;
3018                 fw.sbss = bce_TPAT_b09FwSbss;
3019
3020                 fw.bss_addr = bce_TPAT_b09FwBssAddr;
3021                 fw.bss_len = bce_TPAT_b09FwBssLen;
3022                 fw.bss_index = 0;
3023                 fw.bss = bce_TPAT_b09FwBss;
3024
3025                 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
3026                 fw.rodata_len = bce_TPAT_b09FwRodataLen;
3027                 fw.rodata_index = 0;
3028                 fw.rodata = bce_TPAT_b09FwRodata;
3029         } else {
3030                 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
3031                 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
3032                 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
3033                 fw.start_addr = bce_TPAT_b06FwStartAddr;
3034
3035                 fw.text_addr = bce_TPAT_b06FwTextAddr;
3036                 fw.text_len = bce_TPAT_b06FwTextLen;
3037                 fw.text_index = 0;
3038                 fw.text = bce_TPAT_b06FwText;
3039
3040                 fw.data_addr = bce_TPAT_b06FwDataAddr;
3041                 fw.data_len = bce_TPAT_b06FwDataLen;
3042                 fw.data_index = 0;
3043                 fw.data = bce_TPAT_b06FwData;
3044
3045                 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
3046                 fw.sbss_len = bce_TPAT_b06FwSbssLen;
3047                 fw.sbss_index = 0;
3048                 fw.sbss = bce_TPAT_b06FwSbss;
3049
3050                 fw.bss_addr = bce_TPAT_b06FwBssAddr;
3051                 fw.bss_len = bce_TPAT_b06FwBssLen;
3052                 fw.bss_index = 0;
3053                 fw.bss = bce_TPAT_b06FwBss;
3054
3055                 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
3056                 fw.rodata_len = bce_TPAT_b06FwRodataLen;
3057                 fw.rodata_index = 0;
3058                 fw.rodata = bce_TPAT_b06FwRodata;
3059         }
3060
3061         DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
3062         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3063         bce_start_cpu(sc, &cpu_reg);
3064 }
3065
3066
3067 /****************************************************************************/
3068 /* Initialize the CP CPU.                                                   */
3069 /*                                                                          */
3070 /* Returns:                                                                 */
3071 /*   Nothing.                                                               */
3072 /****************************************************************************/
3073 static void
3074 bce_init_cp_cpu(struct bce_softc *sc)
3075 {
3076         struct cpu_reg cpu_reg;
3077         struct fw_info fw;
3078
3079         cpu_reg.mode = BCE_CP_CPU_MODE;
3080         cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
3081         cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
3082         cpu_reg.state = BCE_CP_CPU_STATE;
3083         cpu_reg.state_value_clear = 0xffffff;
3084         cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
3085         cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
3086         cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
3087         cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
3088         cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
3089         cpu_reg.spad_base = BCE_CP_SCRATCH;
3090         cpu_reg.mips_view_base = 0x8000000;
3091
3092         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3093             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3094                 fw.ver_major = bce_CP_b09FwReleaseMajor;
3095                 fw.ver_minor = bce_CP_b09FwReleaseMinor;
3096                 fw.ver_fix = bce_CP_b09FwReleaseFix;
3097                 fw.start_addr = bce_CP_b09FwStartAddr;
3098
3099                 fw.text_addr = bce_CP_b09FwTextAddr;
3100                 fw.text_len = bce_CP_b09FwTextLen;
3101                 fw.text_index = 0;
3102                 fw.text = bce_CP_b09FwText;
3103
3104                 fw.data_addr = bce_CP_b09FwDataAddr;
3105                 fw.data_len = bce_CP_b09FwDataLen;
3106                 fw.data_index = 0;
3107                 fw.data = bce_CP_b09FwData;
3108
3109                 fw.sbss_addr = bce_CP_b09FwSbssAddr;
3110                 fw.sbss_len = bce_CP_b09FwSbssLen;
3111                 fw.sbss_index = 0;
3112                 fw.sbss = bce_CP_b09FwSbss;
3113
3114                 fw.bss_addr = bce_CP_b09FwBssAddr;
3115                 fw.bss_len = bce_CP_b09FwBssLen;
3116                 fw.bss_index = 0;
3117                 fw.bss = bce_CP_b09FwBss;
3118
3119                 fw.rodata_addr = bce_CP_b09FwRodataAddr;
3120                 fw.rodata_len = bce_CP_b09FwRodataLen;
3121                 fw.rodata_index = 0;
3122                 fw.rodata = bce_CP_b09FwRodata;
3123         } else {
3124                 fw.ver_major = bce_CP_b06FwReleaseMajor;
3125                 fw.ver_minor = bce_CP_b06FwReleaseMinor;
3126                 fw.ver_fix = bce_CP_b06FwReleaseFix;
3127                 fw.start_addr = bce_CP_b06FwStartAddr;
3128
3129                 fw.text_addr = bce_CP_b06FwTextAddr;
3130                 fw.text_len = bce_CP_b06FwTextLen;
3131                 fw.text_index = 0;
3132                 fw.text = bce_CP_b06FwText;
3133
3134                 fw.data_addr = bce_CP_b06FwDataAddr;
3135                 fw.data_len = bce_CP_b06FwDataLen;
3136                 fw.data_index = 0;
3137                 fw.data = bce_CP_b06FwData;
3138
3139                 fw.sbss_addr = bce_CP_b06FwSbssAddr;
3140                 fw.sbss_len = bce_CP_b06FwSbssLen;
3141                 fw.sbss_index = 0;
3142                 fw.sbss = bce_CP_b06FwSbss;
3143
3144                 fw.bss_addr = bce_CP_b06FwBssAddr;
3145                 fw.bss_len = bce_CP_b06FwBssLen;
3146                 fw.bss_index = 0;
3147                 fw.bss = bce_CP_b06FwBss;
3148
3149                 fw.rodata_addr = bce_CP_b06FwRodataAddr;
3150                 fw.rodata_len = bce_CP_b06FwRodataLen;
3151                 fw.rodata_index = 0;
3152                 fw.rodata = bce_CP_b06FwRodata;
3153         }
3154
3155         DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
3156         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3157         bce_start_cpu(sc, &cpu_reg);
3158 }
3159
3160
3161 /****************************************************************************/
3162 /* Initialize the COM CPU.                                                 */
3163 /*                                                                          */
3164 /* Returns:                                                                 */
3165 /*   Nothing.                                                               */
3166 /****************************************************************************/
3167 static void
3168 bce_init_com_cpu(struct bce_softc *sc)
3169 {
3170         struct cpu_reg cpu_reg;
3171         struct fw_info fw;
3172
3173         cpu_reg.mode = BCE_COM_CPU_MODE;
3174         cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
3175         cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
3176         cpu_reg.state = BCE_COM_CPU_STATE;
3177         cpu_reg.state_value_clear = 0xffffff;
3178         cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
3179         cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
3180         cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
3181         cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
3182         cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
3183         cpu_reg.spad_base = BCE_COM_SCRATCH;
3184         cpu_reg.mips_view_base = 0x8000000;
3185
3186         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3187             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3188                 fw.ver_major = bce_COM_b09FwReleaseMajor;
3189                 fw.ver_minor = bce_COM_b09FwReleaseMinor;
3190                 fw.ver_fix = bce_COM_b09FwReleaseFix;
3191                 fw.start_addr = bce_COM_b09FwStartAddr;
3192
3193                 fw.text_addr = bce_COM_b09FwTextAddr;
3194                 fw.text_len = bce_COM_b09FwTextLen;
3195                 fw.text_index = 0;
3196                 fw.text = bce_COM_b09FwText;
3197
3198                 fw.data_addr = bce_COM_b09FwDataAddr;
3199                 fw.data_len = bce_COM_b09FwDataLen;
3200                 fw.data_index = 0;
3201                 fw.data = bce_COM_b09FwData;
3202
3203                 fw.sbss_addr = bce_COM_b09FwSbssAddr;
3204                 fw.sbss_len = bce_COM_b09FwSbssLen;
3205                 fw.sbss_index = 0;
3206                 fw.sbss = bce_COM_b09FwSbss;
3207
3208                 fw.bss_addr = bce_COM_b09FwBssAddr;
3209                 fw.bss_len = bce_COM_b09FwBssLen;
3210                 fw.bss_index = 0;
3211                 fw.bss = bce_COM_b09FwBss;
3212
3213                 fw.rodata_addr = bce_COM_b09FwRodataAddr;
3214                 fw.rodata_len = bce_COM_b09FwRodataLen;
3215                 fw.rodata_index = 0;
3216                 fw.rodata = bce_COM_b09FwRodata;
3217         } else {
3218                 fw.ver_major = bce_COM_b06FwReleaseMajor;
3219                 fw.ver_minor = bce_COM_b06FwReleaseMinor;
3220                 fw.ver_fix = bce_COM_b06FwReleaseFix;
3221                 fw.start_addr = bce_COM_b06FwStartAddr;
3222
3223                 fw.text_addr = bce_COM_b06FwTextAddr;
3224                 fw.text_len = bce_COM_b06FwTextLen;
3225                 fw.text_index = 0;
3226                 fw.text = bce_COM_b06FwText;
3227
3228                 fw.data_addr = bce_COM_b06FwDataAddr;
3229                 fw.data_len = bce_COM_b06FwDataLen;
3230                 fw.data_index = 0;
3231                 fw.data = bce_COM_b06FwData;
3232
3233                 fw.sbss_addr = bce_COM_b06FwSbssAddr;
3234                 fw.sbss_len = bce_COM_b06FwSbssLen;
3235                 fw.sbss_index = 0;
3236                 fw.sbss = bce_COM_b06FwSbss;
3237
3238                 fw.bss_addr = bce_COM_b06FwBssAddr;
3239                 fw.bss_len = bce_COM_b06FwBssLen;
3240                 fw.bss_index = 0;
3241                 fw.bss = bce_COM_b06FwBss;
3242
3243                 fw.rodata_addr = bce_COM_b06FwRodataAddr;
3244                 fw.rodata_len = bce_COM_b06FwRodataLen;
3245                 fw.rodata_index = 0;
3246                 fw.rodata = bce_COM_b06FwRodata;
3247         }
3248
3249         DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
3250         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3251         bce_start_cpu(sc, &cpu_reg);
3252 }
3253
3254
3255 /****************************************************************************/
3256 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs.                     */
3257 /*                                                                          */
3258 /* Loads the firmware for each CPU and starts the CPU.                      */
3259 /*                                                                          */
3260 /* Returns:                                                                 */
3261 /*   Nothing.                                                               */
3262 /****************************************************************************/
3263 static void
3264 bce_init_cpus(struct bce_softc *sc)
3265 {
3266         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3267             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3268                 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax) {
3269                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
3270                             sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
3271                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
3272                             sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
3273                 } else {
3274                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
3275                             sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
3276                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
3277                             sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
3278                 }
3279         } else {
3280                 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
3281                     sizeof(bce_rv2p_proc1), RV2P_PROC1);
3282                 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
3283                     sizeof(bce_rv2p_proc2), RV2P_PROC2);
3284         }
3285
3286         bce_init_rxp_cpu(sc);
3287         bce_init_txp_cpu(sc);
3288         bce_init_tpat_cpu(sc);
3289         bce_init_com_cpu(sc);
3290         bce_init_cp_cpu(sc);
3291 }
3292
3293
3294 /****************************************************************************/
3295 /* Initialize context memory.                                               */
3296 /*                                                                          */
3297 /* Clears the memory associated with each Context ID (CID).                 */
3298 /*                                                                          */
3299 /* Returns:                                                                 */
3300 /*   Nothing.                                                               */
3301 /****************************************************************************/
3302 static int
3303 bce_init_ctx(struct bce_softc *sc)
3304 {
3305         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3306             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3307                 /* DRC: Replace this constant value with a #define. */
3308                 int i, retry_cnt = 10;
3309                 uint32_t val;
3310
3311                 /*
3312                  * BCM5709 context memory may be cached
3313                  * in host memory so prepare the host memory
3314                  * for access.
3315                  */
3316                 val = BCE_CTX_COMMAND_ENABLED | BCE_CTX_COMMAND_MEM_INIT |
3317                     (1 << 12);
3318                 val |= (BCM_PAGE_BITS - 8) << 16;
3319                 REG_WR(sc, BCE_CTX_COMMAND, val);
3320
3321                 /* Wait for mem init command to complete. */
3322                 for (i = 0; i < retry_cnt; i++) {
3323                         val = REG_RD(sc, BCE_CTX_COMMAND);
3324                         if (!(val & BCE_CTX_COMMAND_MEM_INIT))
3325                                 break;
3326                         DELAY(2);
3327                 }
3328                 if (i == retry_cnt) {
3329                         device_printf(sc->bce_dev,
3330                             "Context memory initialization failed!\n");
3331                         return ETIMEDOUT;
3332                 }
3333
3334                 for (i = 0; i < sc->ctx_pages; i++) {
3335                         int j;
3336
3337                         /*
3338                          * Set the physical address of the context
3339                          * memory cache.
3340                          */
3341                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
3342                             BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
3343                             BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
3344                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
3345                             BCE_ADDR_HI(sc->ctx_paddr[i]));
3346                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL,
3347                             i | BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
3348
3349                         /*
3350                          * Verify that the context memory write was successful.
3351                          */
3352                         for (j = 0; j < retry_cnt; j++) {
3353                                 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
3354                                 if ((val &
3355                                     BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
3356                                         break;
3357                                 DELAY(5);
3358                         }
3359                         if (j == retry_cnt) {
3360                                 device_printf(sc->bce_dev,
3361                                     "Failed to initialize context page!\n");
3362                                 return ETIMEDOUT;
3363                         }
3364                 }
3365         } else {
3366                 uint32_t vcid_addr, offset;
3367
3368                 /*
3369                  * For the 5706/5708, context memory is local to
3370                  * the controller, so initialize the controller
3371                  * context memory.
3372                  */
3373
3374                 vcid_addr = GET_CID_ADDR(96);
3375                 while (vcid_addr) {
3376                         vcid_addr -= PHY_CTX_SIZE;
3377
3378                         REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
3379                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3380
3381                         for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
3382                                 CTX_WR(sc, 0x00, offset, 0);
3383
3384                         REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
3385                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3386                 }
3387         }
3388         return 0;
3389 }
3390
3391
3392 /****************************************************************************/
3393 /* Fetch the permanent MAC address of the controller.                       */
3394 /*                                                                          */
3395 /* Returns:                                                                 */
3396 /*   Nothing.                                                               */
3397 /****************************************************************************/
3398 static void
3399 bce_get_mac_addr(struct bce_softc *sc)
3400 {
3401         uint32_t mac_lo = 0, mac_hi = 0;
3402
3403         /*
3404          * The NetXtreme II bootcode populates various NIC
3405          * power-on and runtime configuration items in a
3406          * shared memory area.  The factory configured MAC
3407          * address is available from both NVRAM and the
3408          * shared memory area so we'll read the value from
3409          * shared memory for speed.
3410          */
3411
3412         mac_hi = bce_shmem_rd(sc,  BCE_PORT_HW_CFG_MAC_UPPER);
3413         mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
3414
3415         if (mac_lo == 0 && mac_hi == 0) {
3416                 if_printf(&sc->arpcom.ac_if, "Invalid Ethernet address!\n");
3417         } else {
3418                 sc->eaddr[0] = (u_char)(mac_hi >> 8);
3419                 sc->eaddr[1] = (u_char)(mac_hi >> 0);
3420                 sc->eaddr[2] = (u_char)(mac_lo >> 24);
3421                 sc->eaddr[3] = (u_char)(mac_lo >> 16);
3422                 sc->eaddr[4] = (u_char)(mac_lo >> 8);
3423                 sc->eaddr[5] = (u_char)(mac_lo >> 0);
3424         }
3425
3426         DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %6D\n", sc->eaddr, ":");
3427 }
3428
3429
3430 /****************************************************************************/
3431 /* Program the MAC address.                                                 */
3432 /*                                                                          */
3433 /* Returns:                                                                 */
3434 /*   Nothing.                                                               */
3435 /****************************************************************************/
3436 static void
3437 bce_set_mac_addr(struct bce_softc *sc)
3438 {
3439         const uint8_t *mac_addr = sc->eaddr;
3440         uint32_t val;
3441
3442         DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %6D\n",
3443                 sc->eaddr, ":");
3444
3445         val = (mac_addr[0] << 8) | mac_addr[1];
3446         REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
3447
3448         val = (mac_addr[2] << 24) |
3449               (mac_addr[3] << 16) |
3450               (mac_addr[4] << 8) |
3451               mac_addr[5];
3452         REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
3453 }
3454
3455
3456 /****************************************************************************/
3457 /* Stop the controller.                                                     */
3458 /*                                                                          */
3459 /* Returns:                                                                 */
3460 /*   Nothing.                                                               */
3461 /****************************************************************************/
3462 static void
3463 bce_stop(struct bce_softc *sc)
3464 {
3465         struct ifnet *ifp = &sc->arpcom.ac_if;
3466
3467         ASSERT_SERIALIZED(ifp->if_serializer);
3468
3469         callout_stop(&sc->bce_tick_callout);
3470
3471         /* Disable the transmit/receive blocks. */
3472         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
3473         REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3474         DELAY(20);
3475
3476         bce_disable_intr(sc);
3477
3478         /* Free the RX lists. */
3479         bce_free_rx_chain(sc);
3480
3481         /* Free TX buffers. */
3482         bce_free_tx_chain(sc);
3483
3484         sc->bce_link = 0;
3485         sc->bce_coalchg_mask = 0;
3486
3487         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3488         ifp->if_timer = 0;
3489 }
3490
3491
3492 static int
3493 bce_reset(struct bce_softc *sc, uint32_t reset_code)
3494 {
3495         uint32_t val;
3496         int i, rc = 0;
3497
3498         /* Wait for pending PCI transactions to complete. */
3499         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
3500                BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3501                BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3502                BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3503                BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3504         val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3505         DELAY(5);
3506
3507         /* Disable DMA */
3508         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3509             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3510                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3511                 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3512                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3513         }
3514
3515         /* Assume bootcode is running. */
3516         sc->bce_fw_timed_out = 0;
3517         sc->bce_drv_cardiac_arrest = 0;
3518
3519         /* Give the firmware a chance to prepare for the reset. */
3520         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
3521         if (rc) {
3522                 if_printf(&sc->arpcom.ac_if,
3523                           "Firmware is not ready for reset\n");
3524                 return rc;
3525         }
3526
3527         /* Set a firmware reminder that this is a soft reset. */
3528         bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE,
3529             BCE_DRV_RESET_SIGNATURE_MAGIC);
3530
3531         /* Dummy read to force the chip to complete all current transactions. */
3532         val = REG_RD(sc, BCE_MISC_ID);
3533
3534         /* Chip reset. */
3535         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3536             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3537                 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
3538                 REG_RD(sc, BCE_MISC_COMMAND);
3539                 DELAY(5);
3540
3541                 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3542                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3543
3544                 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
3545         } else {
3546                 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3547                     BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3548                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3549                 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
3550
3551                 /* Allow up to 30us for reset to complete. */
3552                 for (i = 0; i < 10; i++) {
3553                         val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
3554                         if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3555                             BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3556                                 break;
3557                         DELAY(10);
3558                 }
3559
3560                 /* Check that reset completed successfully. */
3561                 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3562                     BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3563                         if_printf(&sc->arpcom.ac_if, "Reset failed!\n");
3564                         return EBUSY;
3565                 }
3566         }
3567
3568         /* Make sure byte swapping is properly configured. */
3569         val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
3570         if (val != 0x01020304) {
3571                 if_printf(&sc->arpcom.ac_if, "Byte swap is incorrect!\n");
3572                 return ENODEV;
3573         }
3574
3575         /* Just completed a reset, assume that firmware is running again. */
3576         sc->bce_fw_timed_out = 0;
3577         sc->bce_drv_cardiac_arrest = 0;
3578
3579         /* Wait for the firmware to finish its initialization. */
3580         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
3581         if (rc) {
3582                 if_printf(&sc->arpcom.ac_if,
3583                           "Firmware did not complete initialization!\n");
3584         }
3585         return rc;
3586 }
3587
3588
3589 static int
3590 bce_chipinit(struct bce_softc *sc)
3591 {
3592         uint32_t val;
3593         int rc = 0;
3594
3595         /* Make sure the interrupt is not active. */
3596         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
3597         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
3598
3599         /*
3600          * Initialize DMA byte/word swapping, configure the number of DMA
3601          * channels and PCI clock compensation delay.
3602          */
3603         val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
3604               BCE_DMA_CONFIG_DATA_WORD_SWAP |
3605 #if BYTE_ORDER == BIG_ENDIAN
3606               BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
3607 #endif
3608               BCE_DMA_CONFIG_CNTL_WORD_SWAP |
3609               DMA_READ_CHANS << 12 |
3610               DMA_WRITE_CHANS << 16;
3611
3612         val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
3613
3614         if ((sc->bce_flags & BCE_PCIX_FLAG) && sc->bus_speed_mhz == 133)
3615                 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
3616
3617         /*
3618          * This setting resolves a problem observed on certain Intel PCI
3619          * chipsets that cannot handle multiple outstanding DMA operations.
3620          * See errata E9_5706A1_65.
3621          */
3622         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706 &&
3623             BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0 &&
3624             !(sc->bce_flags & BCE_PCIX_FLAG))
3625                 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
3626
3627         REG_WR(sc, BCE_DMA_CONFIG, val);
3628
3629         /* Enable the RX_V2P and Context state machines before access. */
3630         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3631                BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3632                BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3633                BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3634
3635         /* Initialize context mapping and zero out the quick contexts. */
3636         rc = bce_init_ctx(sc);
3637         if (rc != 0)
3638                 return rc;
3639
3640         /* Initialize the on-boards CPUs */
3641         bce_init_cpus(sc);
3642
3643         /* Enable management frames (NC-SI) to flow to the MCP. */
3644         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3645                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) |
3646                     BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3647                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3648         }
3649
3650         /* Prepare NVRAM for access. */
3651         rc = bce_init_nvram(sc);
3652         if (rc != 0)
3653                 return rc;
3654
3655         /* Set the kernel bypass block size */
3656         val = REG_RD(sc, BCE_MQ_CONFIG);
3657         val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3658         val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3659
3660         /* Enable bins used on the 5709/5716. */
3661         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3662             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3663                 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
3664                 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
3665                         val |= BCE_MQ_CONFIG_HALT_DIS;
3666         }
3667
3668         REG_WR(sc, BCE_MQ_CONFIG, val);
3669
3670         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3671         REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
3672         REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
3673
3674         /* Set the page size and clear the RV2P processor stall bits. */
3675         val = (BCM_PAGE_BITS - 8) << 24;
3676         REG_WR(sc, BCE_RV2P_CONFIG, val);
3677
3678         /* Configure page size. */
3679         val = REG_RD(sc, BCE_TBDR_CONFIG);
3680         val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
3681         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3682         REG_WR(sc, BCE_TBDR_CONFIG, val);
3683
3684         /* Set the perfect match control register to default. */
3685         REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
3686
3687         return 0;
3688 }
3689
3690
3691 /****************************************************************************/
3692 /* Initialize the controller in preparation to send/receive traffic.        */
3693 /*                                                                          */
3694 /* Returns:                                                                 */
3695 /*   0 for success, positive value for failure.                             */
3696 /****************************************************************************/
3697 static int
3698 bce_blockinit(struct bce_softc *sc)
3699 {
3700         uint32_t reg, val;
3701         int rc = 0;
3702
3703         /* Load the hardware default MAC address. */
3704         bce_set_mac_addr(sc);
3705
3706         /* Set the Ethernet backoff seed value */
3707         val = sc->eaddr[0] + (sc->eaddr[1] << 8) + (sc->eaddr[2] << 16) +
3708               sc->eaddr[3] + (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);
3709         REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
3710
3711         sc->last_status_idx = 0;
3712         sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
3713
3714         sc->pulse_check_status_idx = 0xffff;
3715
3716         /* Set up link change interrupt generation. */
3717         REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
3718
3719         /* Program the physical address of the status block. */
3720         REG_WR(sc, BCE_HC_STATUS_ADDR_L, BCE_ADDR_LO(sc->status_block_paddr));
3721         REG_WR(sc, BCE_HC_STATUS_ADDR_H, BCE_ADDR_HI(sc->status_block_paddr));
3722
3723         /* Program the physical address of the statistics block. */
3724         REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
3725                BCE_ADDR_LO(sc->stats_block_paddr));
3726         REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
3727                BCE_ADDR_HI(sc->stats_block_paddr));
3728
3729         /* Program various host coalescing parameters. */
3730         REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
3731                (sc->bce_tx_quick_cons_trip_int << 16) |
3732                sc->bce_tx_quick_cons_trip);
3733         REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
3734                (sc->bce_rx_quick_cons_trip_int << 16) |
3735                sc->bce_rx_quick_cons_trip);
3736         REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
3737                (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
3738         REG_WR(sc, BCE_HC_TX_TICKS,
3739                (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
3740         REG_WR(sc, BCE_HC_RX_TICKS,
3741                (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
3742         REG_WR(sc, BCE_HC_COM_TICKS,
3743                (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
3744         REG_WR(sc, BCE_HC_CMD_TICKS,
3745                (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
3746         REG_WR(sc, BCE_HC_STATS_TICKS, (sc->bce_stats_ticks & 0xffff00));
3747         REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8);   /* 3ms */
3748
3749         val = BCE_HC_CONFIG_TX_TMR_MODE | BCE_HC_CONFIG_COLLECT_STATS;
3750         if (sc->bce_flags & BCE_ONESHOT_MSI_FLAG) {
3751                 if (bootverbose)
3752                         if_printf(&sc->arpcom.ac_if, "oneshot MSI\n");
3753                 val |= BCE_HC_CONFIG_ONE_SHOT | BCE_HC_CONFIG_USE_INT_PARAM;
3754         }
3755         REG_WR(sc, BCE_HC_CONFIG, val);
3756
3757         /* Clear the internal statistics counters. */
3758         REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
3759
3760         /* Verify that bootcode is running. */
3761         reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE);
3762
3763         DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure),
3764                 if_printf(&sc->arpcom.ac_if,
3765                           "%s(%d): Simulating bootcode failure.\n",
3766                           __FILE__, __LINE__);
3767                 reg = 0);
3768
3769         if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
3770             BCE_DEV_INFO_SIGNATURE_MAGIC) {
3771                 if_printf(&sc->arpcom.ac_if,
3772                           "Bootcode not running! Found: 0x%08X, "
3773                           "Expected: 08%08X\n",
3774                           reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK,
3775                           BCE_DEV_INFO_SIGNATURE_MAGIC);
3776                 return ENODEV;
3777         }
3778
3779         /* Enable DMA */
3780         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3781             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3782                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3783                 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3784                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3785         }
3786
3787         /* Allow bootcode to apply any additional fixes before enabling MAC. */
3788         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET);
3789
3790         /* Enable link state change interrupt generation. */
3791         REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3792
3793         /* Enable the RXP. */
3794         bce_start_rxp_cpu(sc);
3795
3796         /* Disable management frames (NC-SI) from flowing to the MCP. */
3797         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3798                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) &
3799                     ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3800                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3801         }
3802
3803         /* Enable all remaining blocks in the MAC. */
3804         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3805             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3806                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3807                     BCE_MISC_ENABLE_DEFAULT_XI);
3808         } else {
3809                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
3810         }
3811         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
3812         DELAY(20);
3813
3814         /* Save the current host coalescing block settings. */
3815         sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
3816
3817         return 0;
3818 }
3819
3820
3821 /****************************************************************************/
3822 /* Encapsulate an mbuf cluster into the rx_bd chain.                        */
3823 /*                                                                          */
3824 /* The NetXtreme II can support Jumbo frames by using multiple rx_bd's.     */
3825 /* This routine will map an mbuf cluster into 1 or more rx_bd's as          */
3826 /* necessary.                                                               */
3827 /*                                                                          */
3828 /* Returns:                                                                 */
3829 /*   0 for success, positive value for failure.                             */
3830 /****************************************************************************/
3831 static int
3832 bce_newbuf_std(struct bce_softc *sc, uint16_t *prod, uint16_t *chain_prod,
3833                uint32_t *prod_bseq, int init)
3834 {
3835         bus_dmamap_t map;
3836         bus_dma_segment_t seg;
3837         struct mbuf *m_new;
3838         int error, nseg;
3839 #ifdef BCE_DEBUG
3840         uint16_t debug_chain_prod = *chain_prod;
3841 #endif
3842
3843         /* Make sure the inputs are valid. */
3844         DBRUNIF((*chain_prod > MAX_RX_BD(sc)),
3845                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3846                           "RX producer out of range: 0x%04X > 0x%04X\n",
3847                           __FILE__, __LINE__,
3848                           *chain_prod, (uint16_t)MAX_RX_BD(sc)));
3849
3850         DBPRINT(sc, BCE_VERBOSE_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, "
3851                 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3852
3853         DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure),
3854                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3855                           "Simulating mbuf allocation failure.\n",
3856                           __FILE__, __LINE__);
3857                 sc->mbuf_alloc_failed++;
3858                 return ENOBUFS);
3859
3860         /* This is a new mbuf allocation. */
3861         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
3862         if (m_new == NULL)
3863                 return ENOBUFS;
3864         DBRUNIF(1, sc->rx_mbuf_alloc++);
3865
3866         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
3867
3868         /* Map the mbuf cluster into device memory. */
3869         error = bus_dmamap_load_mbuf_segment(sc->rx_mbuf_tag,
3870                         sc->rx_mbuf_tmpmap, m_new, &seg, 1, &nseg,
3871                         BUS_DMA_NOWAIT);
3872         if (error) {
3873                 m_freem(m_new);
3874                 if (init) {
3875                         if_printf(&sc->arpcom.ac_if,
3876                                   "Error mapping mbuf into RX chain!\n");
3877                 }
3878                 DBRUNIF(1, sc->rx_mbuf_alloc--);
3879                 return error;
3880         }
3881
3882         if (sc->rx_mbuf_ptr[*chain_prod] != NULL) {
3883                 bus_dmamap_unload(sc->rx_mbuf_tag,
3884                                   sc->rx_mbuf_map[*chain_prod]);
3885         }
3886
3887         map = sc->rx_mbuf_map[*chain_prod];
3888         sc->rx_mbuf_map[*chain_prod] = sc->rx_mbuf_tmpmap;
3889         sc->rx_mbuf_tmpmap = map;
3890
3891         /* Watch for overflow. */
3892         DBRUNIF((sc->free_rx_bd > USABLE_RX_BD(sc)),
3893                 if_printf(&sc->arpcom.ac_if, "%s(%d): "
3894                           "Too many free rx_bd (0x%04X > 0x%04X)!\n",
3895                           __FILE__, __LINE__, sc->free_rx_bd,
3896                           (uint16_t)USABLE_RX_BD(sc)));
3897
3898         /* Update some debug statistic counters */
3899         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
3900                 sc->rx_low_watermark = sc->free_rx_bd);
3901         DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
3902
3903         /* Save the mbuf and update our counter. */
3904         sc->rx_mbuf_ptr[*chain_prod] = m_new;
3905         sc->rx_mbuf_paddr[*chain_prod] = seg.ds_addr;
3906         sc->free_rx_bd--;
3907
3908         bce_setup_rxdesc_std(sc, *chain_prod, prod_bseq);
3909
3910         DBRUN(BCE_VERBOSE_RECV,
3911               bce_dump_rx_mbuf_chain(sc, debug_chain_prod, 1));
3912
3913         DBPRINT(sc, BCE_VERBOSE_RECV, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, "
3914                 "prod_bseq = 0x%08X\n", __func__, *prod, *chain_prod, *prod_bseq);
3915
3916         return 0;
3917 }
3918
3919
3920 static void
3921 bce_setup_rxdesc_std(struct bce_softc *sc, uint16_t chain_prod, uint32_t *prod_bseq)
3922 {
3923         struct rx_bd *rxbd;
3924         bus_addr_t paddr;
3925         int len;
3926
3927         paddr = sc->rx_mbuf_paddr[chain_prod];
3928         len = sc->rx_mbuf_ptr[chain_prod]->m_len;
3929
3930         /* Setup the rx_bd for the first segment. */
3931         rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)];
3932
3933         rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(paddr));
3934         rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(paddr));
3935         rxbd->rx_bd_len = htole32(len);
3936         rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START);
3937         *prod_bseq += len;
3938
3939         rxbd->rx_bd_flags |= htole32(RX_BD_FLAGS_END);
3940 }
3941
3942
3943 /****************************************************************************/
3944 /* Initialize the TX context memory.                                        */
3945 /*                                                                          */
3946 /* Returns:                                                                 */
3947 /*   Nothing                                                                */
3948 /****************************************************************************/
3949 static void
3950 bce_init_tx_context(struct bce_softc *sc)
3951 {
3952         uint32_t val;
3953
3954         /* Initialize the context ID for an L2 TX chain. */
3955         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3956             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3957                 /* Set the CID type to support an L2 connection. */
3958                 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3959                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val);
3960                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3961                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE_XI, val);
3962
3963                 /* Point the hardware to the first page in the chain. */
3964                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3965                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3966                     BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val);
3967                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3968                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3969                     BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val);
3970         } else {
3971                 /* Set the CID type to support an L2 connection. */
3972                 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
3973                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val);
3974                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
3975                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val);
3976
3977                 /* Point the hardware to the first page in the chain. */
3978                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
3979                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3980                     BCE_L2CTX_TX_TBDR_BHADDR_HI, val);
3981                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
3982                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
3983                     BCE_L2CTX_TX_TBDR_BHADDR_LO, val);
3984         }
3985 }
3986
3987
3988 /****************************************************************************/
3989 /* Allocate memory and initialize the TX data structures.                   */
3990 /*                                                                          */
3991 /* Returns:                                                                 */
3992 /*   0 for success, positive value for failure.                             */
3993 /****************************************************************************/
3994 static int
3995 bce_init_tx_chain(struct bce_softc *sc)
3996 {
3997         struct tx_bd *txbd;
3998         int i, rc = 0;
3999
4000         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4001
4002         /* Set the initial TX producer/consumer indices. */
4003         sc->tx_prod = 0;
4004         sc->tx_cons = 0;
4005         sc->tx_prod_bseq   = 0;
4006         sc->used_tx_bd = 0;
4007         sc->max_tx_bd = USABLE_TX_BD(sc);
4008         DBRUNIF(1, sc->tx_hi_watermark = USABLE_TX_BD(sc));
4009         DBRUNIF(1, sc->tx_full_count = 0);
4010
4011         /*
4012          * The NetXtreme II supports a linked-list structre called
4013          * a Buffer Descriptor Chain (or BD chain).  A BD chain
4014          * consists of a series of 1 or more chain pages, each of which
4015          * consists of a fixed number of BD entries.
4016          * The last BD entry on each page is a pointer to the next page
4017          * in the chain, and the last pointer in the BD chain
4018          * points back to the beginning of the chain.
4019          */
4020
4021         /* Set the TX next pointer chain entries. */
4022         for (i = 0; i < sc->tx_pages; i++) {
4023                 int j;
4024
4025                 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
4026
4027                 /* Check if we've reached the last page. */
4028                 if (i == (sc->tx_pages - 1))
4029                         j = 0;
4030                 else
4031                         j = i + 1;
4032
4033                 txbd->tx_bd_haddr_hi =
4034                         htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
4035                 txbd->tx_bd_haddr_lo =
4036                         htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
4037         }
4038         bce_init_tx_context(sc);
4039
4040         return(rc);
4041 }
4042
4043
4044 /****************************************************************************/
4045 /* Free memory and clear the TX data structures.                            */
4046 /*                                                                          */
4047 /* Returns:                                                                 */
4048 /*   Nothing.                                                               */
4049 /****************************************************************************/
4050 static void
4051 bce_free_tx_chain(struct bce_softc *sc)
4052 {
4053         int i;
4054
4055         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4056
4057         /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
4058         for (i = 0; i < TOTAL_TX_BD(sc); i++) {
4059                 if (sc->tx_mbuf_ptr[i] != NULL) {
4060                         bus_dmamap_unload(sc->tx_mbuf_tag, sc->tx_mbuf_map[i]);
4061                         m_freem(sc->tx_mbuf_ptr[i]);
4062                         sc->tx_mbuf_ptr[i] = NULL;
4063                         DBRUNIF(1, sc->tx_mbuf_alloc--);
4064                 }
4065         }
4066
4067         /* Clear each TX chain page. */
4068         for (i = 0; i < sc->tx_pages; i++)
4069                 bzero(sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
4070         sc->used_tx_bd = 0;
4071
4072         /* Check if we lost any mbufs in the process. */
4073         DBRUNIF((sc->tx_mbuf_alloc),
4074                 if_printf(&sc->arpcom.ac_if,
4075                           "%s(%d): Memory leak! "
4076                           "Lost %d mbufs from tx chain!\n",
4077                           __FILE__, __LINE__, sc->tx_mbuf_alloc));
4078
4079         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
4080 }
4081
4082
4083 /****************************************************************************/
4084 /* Initialize the RX context memory.                                        */
4085 /*                                                                          */
4086 /* Returns:                                                                 */
4087 /*   Nothing                                                                */
4088 /****************************************************************************/
4089 static void
4090 bce_init_rx_context(struct bce_softc *sc)
4091 {
4092         uint32_t val;
4093
4094         /* Initialize the context ID for an L2 RX chain. */
4095         val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
4096             BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
4097
4098         /*
4099          * Set the level for generating pause frames
4100          * when the number of available rx_bd's gets
4101          * too low (the low watermark) and the level
4102          * when pause frames can be stopped (the high
4103          * watermark).
4104          */
4105         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4106             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4107                 uint32_t lo_water, hi_water;
4108
4109                 lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT;
4110                 hi_water = USABLE_RX_BD(sc) / 4;
4111
4112                 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE;
4113                 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE;
4114
4115                 if (hi_water > 0xf)
4116                         hi_water = 0xf;
4117                 else if (hi_water == 0)
4118                         lo_water = 0;
4119                 val |= lo_water |
4120                     (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT);
4121         }
4122
4123         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val);
4124
4125         /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */
4126         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4127             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4128                 val = REG_RD(sc, BCE_MQ_MAP_L2_5);
4129                 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
4130         }
4131
4132         /* Point the hardware to the first page in the chain. */
4133         val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
4134         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val);
4135         val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
4136         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val);
4137 }
4138
4139
4140 /****************************************************************************/
4141 /* Allocate memory and initialize the RX data structures.                   */
4142 /*                                                                          */
4143 /* Returns:                                                                 */
4144 /*   0 for success, positive value for failure.                             */
4145 /****************************************************************************/
4146 static int
4147 bce_init_rx_chain(struct bce_softc *sc)
4148 {
4149         struct rx_bd *rxbd;
4150         int i, rc = 0;
4151         uint16_t prod, chain_prod;
4152         uint32_t prod_bseq;
4153
4154         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4155
4156         /* Initialize the RX producer and consumer indices. */
4157         sc->rx_prod = 0;
4158         sc->rx_cons = 0;
4159         sc->rx_prod_bseq = 0;
4160         sc->free_rx_bd = USABLE_RX_BD(sc);
4161         sc->max_rx_bd = USABLE_RX_BD(sc);
4162         DBRUNIF(1, sc->rx_low_watermark = USABLE_RX_BD(sc));
4163         DBRUNIF(1, sc->rx_empty_count = 0);
4164
4165         /* Initialize the RX next pointer chain entries. */
4166         for (i = 0; i < sc->rx_pages; i++) {
4167                 int j;
4168
4169                 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
4170
4171                 /* Check if we've reached the last page. */
4172                 if (i == (sc->rx_pages - 1))
4173                         j = 0;
4174                 else
4175                         j = i + 1;
4176
4177                 /* Setup the chain page pointers. */
4178                 rxbd->rx_bd_haddr_hi =
4179                         htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
4180                 rxbd->rx_bd_haddr_lo =
4181                         htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
4182         }
4183
4184         /* Allocate mbuf clusters for the rx_bd chain. */
4185         prod = prod_bseq = 0;
4186         while (prod < TOTAL_RX_BD(sc)) {
4187                 chain_prod = RX_CHAIN_IDX(sc, prod);
4188                 if (bce_newbuf_std(sc, &prod, &chain_prod, &prod_bseq, 1)) {
4189                         if_printf(&sc->arpcom.ac_if,
4190                                   "Error filling RX chain: rx_bd[0x%04X]!\n",
4191                                   chain_prod);
4192                         rc = ENOBUFS;
4193                         break;
4194                 }
4195                 prod = NEXT_RX_BD(prod);
4196         }
4197
4198         /* Save the RX chain producer index. */
4199         sc->rx_prod = prod;
4200         sc->rx_prod_bseq = prod_bseq;
4201
4202         /* Tell the chip about the waiting rx_bd's. */
4203         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
4204             sc->rx_prod);
4205         REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
4206             sc->rx_prod_bseq);
4207
4208         bce_init_rx_context(sc);
4209
4210         return(rc);
4211 }
4212
4213
4214 /****************************************************************************/
4215 /* Free memory and clear the RX data structures.                            */
4216 /*                                                                          */
4217 /* Returns:                                                                 */
4218 /*   Nothing.                                                               */
4219 /****************************************************************************/
4220 static void
4221 bce_free_rx_chain(struct bce_softc *sc)
4222 {
4223         int i;
4224
4225         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
4226
4227         /* Free any mbufs still in the RX mbuf chain. */
4228         for (i = 0; i < TOTAL_RX_BD(sc); i++) {
4229                 if (sc->rx_mbuf_ptr[i] != NULL) {
4230                         bus_dmamap_unload(sc->rx_mbuf_tag, sc->rx_mbuf_map[i]);
4231                         m_freem(sc->rx_mbuf_ptr[i]);
4232                         sc->rx_mbuf_ptr[i] = NULL;
4233                         DBRUNIF(1, sc->rx_mbuf_alloc--);
4234                 }
4235         }
4236
4237         /* Clear each RX chain page. */
4238         for (i = 0; i < sc->rx_pages; i++)
4239                 bzero(sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ);
4240
4241         /* Check if we lost any mbufs in the process. */
4242         DBRUNIF((sc->rx_mbuf_alloc),
4243                 if_printf(&sc->arpcom.ac_if,
4244                           "%s(%d): Memory leak! "
4245                           "Lost %d mbufs from rx chain!\n",
4246                           __FILE__, __LINE__, sc->rx_mbuf_alloc));
4247
4248         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
4249 }
4250
4251
4252 /****************************************************************************/
4253 /* Set media options.                                                       */
4254 /*                                                                          */
4255 /* Returns:                                                                 */
4256 /*   0 for success, positive value for failure.                             */
4257 /****************************************************************************/
4258 static int
4259 bce_ifmedia_upd(struct ifnet *ifp)
4260 {
4261         struct bce_softc *sc = ifp->if_softc;
4262         struct mii_data *mii = device_get_softc(sc->bce_miibus);
4263         int error = 0;
4264
4265         /*
4266          * 'mii' will be NULL, when this function is called on following
4267          * code path: bce_attach() -> bce_mgmt_init()
4268          */
4269         if (mii != NULL) {
4270                 /* Make sure the MII bus has been enumerated. */
4271                 sc->bce_link = 0;
4272                 if (mii->mii_instance) {
4273                         struct mii_softc *miisc;
4274
4275                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
4276                                 mii_phy_reset(miisc);
4277                 }
4278                 error = mii_mediachg(mii);
4279         }
4280         return error;
4281 }
4282
4283
4284 /****************************************************************************/
4285 /* Reports current media status.                                            */
4286 /*                                                                          */
4287 /* Returns:                                                                 */
4288 /*   Nothing.                                                               */
4289 /****************************************************************************/
4290 static void
4291 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
4292 {
4293         struct bce_softc *sc = ifp->if_softc;
4294         struct mii_data *mii = device_get_softc(sc->bce_miibus);
4295
4296         mii_pollstat(mii);
4297         ifmr->ifm_active = mii->mii_media_active;
4298         ifmr->ifm_status = mii->mii_media_status;
4299 }
4300
4301
4302 /****************************************************************************/
4303 /* Handles PHY generated interrupt events.                                  */
4304 /*                                                                          */
4305 /* Returns:                                                                 */
4306 /*   Nothing.                                                               */
4307 /****************************************************************************/
4308 static void
4309 bce_phy_intr(struct bce_softc *sc)
4310 {
4311         uint32_t new_link_state, old_link_state;
4312         struct ifnet *ifp = &sc->arpcom.ac_if;
4313
4314         ASSERT_SERIALIZED(ifp->if_serializer);
4315
4316         new_link_state = sc->status_block->status_attn_bits &
4317                          STATUS_ATTN_BITS_LINK_STATE;
4318         old_link_state = sc->status_block->status_attn_bits_ack &
4319                          STATUS_ATTN_BITS_LINK_STATE;
4320
4321         /* Handle any changes if the link state has changed. */
4322         if (new_link_state != old_link_state) { /* XXX redundant? */
4323                 DBRUN(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
4324
4325                 /* Update the status_attn_bits_ack field in the status block. */
4326                 if (new_link_state) {
4327                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
4328                                STATUS_ATTN_BITS_LINK_STATE);
4329                         if (bootverbose)
4330                                 if_printf(ifp, "Link is now UP.\n");
4331                 } else {
4332                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
4333                                STATUS_ATTN_BITS_LINK_STATE);
4334                         if (bootverbose)
4335                                 if_printf(ifp, "Link is now DOWN.\n");
4336                 }
4337
4338                 /*
4339                  * Assume link is down and allow tick routine to
4340                  * update the state based on the actual media state.
4341                  */
4342                 sc->bce_link = 0;
4343                 callout_stop(&sc->bce_tick_callout);
4344                 bce_tick_serialized(sc);
4345         }
4346
4347         /* Acknowledge the link change interrupt. */
4348         REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
4349 }
4350
4351
4352 /****************************************************************************/
4353 /* Reads the receive consumer value from the status block (skipping over    */
4354 /* chain page pointer if necessary).                                        */
4355 /*                                                                          */
4356 /* Returns:                                                                 */
4357 /*   hw_cons                                                                */
4358 /****************************************************************************/
4359 static __inline uint16_t
4360 bce_get_hw_rx_cons(struct bce_softc *sc)
4361 {
4362         uint16_t hw_cons = sc->status_block->status_rx_quick_consumer_index0;
4363
4364         if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
4365                 hw_cons++;
4366         return hw_cons;
4367 }
4368
4369
4370 /****************************************************************************/
4371 /* Handles received frame interrupt events.                                 */
4372 /*                                                                          */
4373 /* Returns:                                                                 */
4374 /*   Nothing.                                                               */
4375 /****************************************************************************/
4376 static void
4377 bce_rx_intr(struct bce_softc *sc, int count)
4378 {
4379         struct ifnet *ifp = &sc->arpcom.ac_if;
4380         uint16_t hw_cons, sw_cons, sw_chain_cons, sw_prod, sw_chain_prod;
4381         uint32_t sw_prod_bseq;
4382
4383         ASSERT_SERIALIZED(ifp->if_serializer);
4384
4385         DBRUNIF(1, sc->rx_interrupts++);
4386
4387         /* Get the hardware's view of the RX consumer index. */
4388         hw_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
4389
4390         /* Get working copies of the driver's view of the RX indices. */
4391         sw_cons = sc->rx_cons;
4392         sw_prod = sc->rx_prod;
4393         sw_prod_bseq = sc->rx_prod_bseq;
4394
4395         DBPRINT(sc, BCE_INFO_RECV, "%s(enter): sw_prod = 0x%04X, "
4396                 "sw_cons = 0x%04X, sw_prod_bseq = 0x%08X\n",
4397                 __func__, sw_prod, sw_cons, sw_prod_bseq);
4398
4399         /* Prevent speculative reads from getting ahead of the status block. */
4400         bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4401                           BUS_SPACE_BARRIER_READ);
4402
4403         /* Update some debug statistics counters */
4404         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
4405                 sc->rx_low_watermark = sc->free_rx_bd);
4406         DBRUNIF((sc->free_rx_bd == 0), sc->rx_empty_count++);
4407
4408         /* Scan through the receive chain as long as there is work to do. */
4409         while (sw_cons != hw_cons) {
4410                 struct mbuf *m = NULL;
4411                 struct l2_fhdr *l2fhdr = NULL;
4412                 struct rx_bd *rxbd;
4413                 unsigned int len;
4414                 uint32_t status = 0;
4415
4416 #ifdef DEVICE_POLLING
4417                 if (count >= 0 && count-- == 0) {
4418                         sc->hw_rx_cons = sw_cons;
4419                         break;
4420                 }
4421 #endif
4422
4423                 /*
4424                  * Convert the producer/consumer indices
4425                  * to an actual rx_bd index.
4426                  */
4427                 sw_chain_cons = RX_CHAIN_IDX(sc, sw_cons);
4428                 sw_chain_prod = RX_CHAIN_IDX(sc, sw_prod);
4429
4430                 /* Get the used rx_bd. */
4431                 rxbd = &sc->rx_bd_chain[RX_PAGE(sw_chain_cons)]
4432                                        [RX_IDX(sw_chain_cons)];
4433                 sc->free_rx_bd++;
4434
4435                 DBRUN(BCE_VERBOSE_RECV,
4436                       if_printf(ifp, "%s(): ", __func__);
4437                       bce_dump_rxbd(sc, sw_chain_cons, rxbd));
4438
4439                 /* The mbuf is stored with the last rx_bd entry of a packet. */
4440                 if (sc->rx_mbuf_ptr[sw_chain_cons] != NULL) {
4441                         /* Validate that this is the last rx_bd. */
4442                         DBRUNIF((!(rxbd->rx_bd_flags & RX_BD_FLAGS_END)),
4443                                 if_printf(ifp, "%s(%d): "
4444                                 "Unexpected mbuf found in rx_bd[0x%04X]!\n",
4445                                 __FILE__, __LINE__, sw_chain_cons);
4446                                 bce_breakpoint(sc));
4447
4448                         if (sw_chain_cons != sw_chain_prod) {
4449                                 if_printf(ifp, "RX cons(%d) != prod(%d), "
4450                                           "drop!\n", sw_chain_cons,
4451                                           sw_chain_prod);
4452                                 ifp->if_ierrors++;
4453
4454                                 bce_setup_rxdesc_std(sc, sw_chain_cons,
4455                                                      &sw_prod_bseq);
4456                                 m = NULL;
4457                                 goto bce_rx_int_next_rx;
4458                         }
4459
4460                         /* Unmap the mbuf from DMA space. */
4461                         bus_dmamap_sync(sc->rx_mbuf_tag,
4462                                         sc->rx_mbuf_map[sw_chain_cons],
4463                                         BUS_DMASYNC_POSTREAD);
4464
4465                         /* Save the mbuf from the driver's chain. */
4466                         m = sc->rx_mbuf_ptr[sw_chain_cons];
4467
4468                         /*
4469                          * Frames received on the NetXteme II are prepended
4470                          * with an l2_fhdr structure which provides status
4471                          * information about the received frame (including
4472                          * VLAN tags and checksum info).  The frames are also
4473                          * automatically adjusted to align the IP header
4474                          * (i.e. two null bytes are inserted before the
4475                          * Ethernet header).  As a result the data DMA'd by
4476                          * the controller into the mbuf is as follows:
4477                          *
4478                          * +---------+-----+---------------------+-----+
4479                          * | l2_fhdr | pad | packet data         | FCS |
4480                          * +---------+-----+---------------------+-----+
4481                          *
4482                          * The l2_fhdr needs to be checked and skipped and the
4483                          * FCS needs to be stripped before sending the packet
4484                          * up the stack.
4485                          */
4486                         l2fhdr = mtod(m, struct l2_fhdr *);
4487
4488                         len = l2fhdr->l2_fhdr_pkt_len;
4489                         status = l2fhdr->l2_fhdr_status;
4490
4491                         DBRUNIF(DB_RANDOMTRUE(bce_debug_l2fhdr_status_check),
4492                                 if_printf(ifp,
4493                                 "Simulating l2_fhdr status error.\n");
4494                                 status = status | L2_FHDR_ERRORS_PHY_DECODE);
4495
4496                         /* Watch for unusual sized frames. */
4497                         DBRUNIF((len < BCE_MIN_MTU ||
4498                                  len > BCE_MAX_JUMBO_ETHER_MTU_VLAN),
4499                                 if_printf(ifp,
4500                                 "%s(%d): Unusual frame size found. "
4501                                 "Min(%d), Actual(%d), Max(%d)\n",
4502                                 __FILE__, __LINE__,
4503                                 (int)BCE_MIN_MTU, len,
4504                                 (int)BCE_MAX_JUMBO_ETHER_MTU_VLAN);
4505                                 bce_dump_mbuf(sc, m);
4506                                 bce_breakpoint(sc));
4507
4508                         len -= ETHER_CRC_LEN;
4509
4510                         /* Check the received frame for errors. */
4511                         if (status & (L2_FHDR_ERRORS_BAD_CRC |
4512                                       L2_FHDR_ERRORS_PHY_DECODE |
4513                                       L2_FHDR_ERRORS_ALIGNMENT |
4514                                       L2_FHDR_ERRORS_TOO_SHORT |
4515                                       L2_FHDR_ERRORS_GIANT_FRAME)) {
4516                                 ifp->if_ierrors++;
4517                                 DBRUNIF(1, sc->l2fhdr_status_errors++);
4518
4519                                 /* Reuse the mbuf for a new frame. */
4520                                 bce_setup_rxdesc_std(sc, sw_chain_prod,
4521                                                      &sw_prod_bseq);
4522                                 m = NULL;
4523                                 goto bce_rx_int_next_rx;
4524                         }
4525
4526                         /*
4527                          * Get a new mbuf for the rx_bd.   If no new
4528                          * mbufs are available then reuse the current mbuf,
4529                          * log an ierror on the interface, and generate
4530                          * an error in the system log.
4531                          */
4532                         if (bce_newbuf_std(sc, &sw_prod, &sw_chain_prod,
4533                                            &sw_prod_bseq, 0)) {
4534                                 DBRUN(BCE_WARN,
4535                                       if_printf(ifp,
4536                                       "%s(%d): Failed to allocate new mbuf, "
4537                                       "incoming frame dropped!\n",
4538                                       __FILE__, __LINE__));
4539
4540                                 ifp->if_ierrors++;
4541
4542                                 /* Try and reuse the exisitng mbuf. */
4543                                 bce_setup_rxdesc_std(sc, sw_chain_prod,
4544                                                      &sw_prod_bseq);
4545                                 m = NULL;
4546                                 goto bce_rx_int_next_rx;
4547                         }
4548
4549                         /*
4550                          * Skip over the l2_fhdr when passing
4551                          * the data up the stack.
4552                          */
4553                         m_adj(m, sizeof(struct l2_fhdr) + ETHER_ALIGN);
4554
4555                         m->m_pkthdr.len = m->m_len = len;
4556                         m->m_pkthdr.rcvif = ifp;
4557
4558                         DBRUN(BCE_VERBOSE_RECV,
4559                               struct ether_header *eh;
4560                               eh = mtod(m, struct ether_header *);
4561                               if_printf(ifp, "%s(): to: %6D, from: %6D, "
4562                                         "type: 0x%04X\n", __func__,
4563                                         eh->ether_dhost, ":",
4564                                         eh->ether_shost, ":",
4565                                         htons(eh->ether_type)));
4566
4567                         /* Validate the checksum if offload enabled. */
4568                         if (ifp->if_capenable & IFCAP_RXCSUM) {
4569                                 /* Check for an IP datagram. */
4570                                 if (status & L2_FHDR_STATUS_IP_DATAGRAM) {
4571                                         m->m_pkthdr.csum_flags |=
4572                                                 CSUM_IP_CHECKED;
4573
4574                                         /* Check if the IP checksum is valid. */
4575                                         if ((l2fhdr->l2_fhdr_ip_xsum ^
4576                                              0xffff) == 0) {
4577                                                 m->m_pkthdr.csum_flags |=
4578                                                         CSUM_IP_VALID;
4579                                         } else {
4580                                                 DBPRINT(sc, BCE_WARN_RECV,
4581                                                         "%s(): Invalid IP checksum = 0x%04X!\n",
4582                                                         __func__, l2fhdr->l2_fhdr_ip_xsum);
4583                                         }
4584                                 }
4585
4586                                 /* Check for a valid TCP/UDP frame. */
4587                                 if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
4588                                               L2_FHDR_STATUS_UDP_DATAGRAM)) {
4589
4590                                         /* Check for a good TCP/UDP checksum. */
4591                                         if ((status &
4592                                              (L2_FHDR_ERRORS_TCP_XSUM |
4593                                               L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
4594                                                 m->m_pkthdr.csum_data =
4595                                                 l2fhdr->l2_fhdr_tcp_udp_xsum;
4596                                                 m->m_pkthdr.csum_flags |=
4597                                                         CSUM_DATA_VALID |
4598                                                         CSUM_PSEUDO_HDR;
4599                                         } else {
4600                                                 DBPRINT(sc, BCE_WARN_RECV,
4601                                                         "%s(): Invalid TCP/UDP checksum = 0x%04X!\n",
4602                                                         __func__, l2fhdr->l2_fhdr_tcp_udp_xsum);
4603                                         }
4604                                 }
4605                         }
4606
4607                         ifp->if_ipackets++;
4608 bce_rx_int_next_rx:
4609                         sw_prod = NEXT_RX_BD(sw_prod);
4610                 }
4611
4612                 sw_cons = NEXT_RX_BD(sw_cons);
4613
4614                 /* If we have a packet, pass it up the stack */
4615                 if (m) {
4616                         DBPRINT(sc, BCE_VERBOSE_RECV,
4617                                 "%s(): Passing received frame up.\n", __func__);
4618
4619                         if (status & L2_FHDR_STATUS_L2_VLAN_TAG) {
4620                                 m->m_flags |= M_VLANTAG;
4621                                 m->m_pkthdr.ether_vlantag =
4622                                         l2fhdr->l2_fhdr_vlan_tag;
4623                         }
4624                         ifp->if_input(ifp, m);
4625
4626                         DBRUNIF(1, sc->rx_mbuf_alloc--);
4627                 }
4628
4629                 /*
4630                  * If polling(4) is not enabled, refresh hw_cons to see
4631                  * whether there's new work.
4632                  *
4633                  * If polling(4) is enabled, i.e count >= 0, refreshing
4634                  * should not be performed, so that we would not spend
4635                  * too much time in RX processing.
4636                  */
4637                 if (count < 0 && sw_cons == hw_cons)
4638                         hw_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
4639
4640                 /*
4641                  * Prevent speculative reads from getting ahead
4642                  * of the status block.
4643                  */
4644                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4645                                   BUS_SPACE_BARRIER_READ);
4646         }
4647
4648         sc->rx_cons = sw_cons;
4649         sc->rx_prod = sw_prod;
4650         sc->rx_prod_bseq = sw_prod_bseq;
4651
4652         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX,
4653             sc->rx_prod);
4654         REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ,
4655             sc->rx_prod_bseq);
4656
4657         DBPRINT(sc, BCE_INFO_RECV, "%s(exit): rx_prod = 0x%04X, "
4658                 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
4659                 __func__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
4660 }
4661
4662
4663 /****************************************************************************/
4664 /* Reads the transmit consumer value from the status block (skipping over   */
4665 /* chain page pointer if necessary).                                        */
4666 /*                                                                          */
4667 /* Returns:                                                                 */
4668 /*   hw_cons                                                                */
4669 /****************************************************************************/
4670 static __inline uint16_t
4671 bce_get_hw_tx_cons(struct bce_softc *sc)
4672 {
4673         uint16_t hw_cons = sc->status_block->status_tx_quick_consumer_index0;
4674
4675         if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
4676                 hw_cons++;
4677         return hw_cons;
4678 }
4679
4680
4681 /****************************************************************************/
4682 /* Handles transmit completion interrupt events.                            */
4683 /*                                                                          */
4684 /* Returns:                                                                 */
4685 /*   Nothing.                                                               */
4686 /****************************************************************************/
4687 static void
4688 bce_tx_intr(struct bce_softc *sc)
4689 {
4690         struct ifnet *ifp = &sc->arpcom.ac_if;
4691         uint16_t hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
4692
4693         ASSERT_SERIALIZED(ifp->if_serializer);
4694
4695         DBRUNIF(1, sc->tx_interrupts++);
4696
4697         /* Get the hardware's view of the TX consumer index. */
4698         hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
4699         sw_tx_cons = sc->tx_cons;
4700
4701         /* Prevent speculative reads from getting ahead of the status block. */
4702         bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4703                           BUS_SPACE_BARRIER_READ);
4704
4705         /* Cycle through any completed TX chain page entries. */
4706         while (sw_tx_cons != hw_tx_cons) {
4707 #ifdef BCE_DEBUG
4708                 struct tx_bd *txbd = NULL;
4709 #endif
4710                 sw_tx_chain_cons = TX_CHAIN_IDX(sc, sw_tx_cons);
4711
4712                 DBPRINT(sc, BCE_INFO_SEND,
4713                         "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, "
4714                         "sw_tx_chain_cons = 0x%04X\n",
4715                         __func__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons);
4716
4717                 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD(sc)),
4718                         if_printf(ifp, "%s(%d): "
4719                                   "TX chain consumer out of range! "
4720                                   " 0x%04X > 0x%04X\n",
4721                                   __FILE__, __LINE__, sw_tx_chain_cons,
4722                                   (int)MAX_TX_BD(sc));
4723                         bce_breakpoint(sc));
4724
4725                 DBRUNIF(1, txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)]
4726                                 [TX_IDX(sw_tx_chain_cons)]);
4727
4728                 DBRUNIF((txbd == NULL),
4729                         if_printf(ifp, "%s(%d): "
4730                                   "Unexpected NULL tx_bd[0x%04X]!\n",
4731                                   __FILE__, __LINE__, sw_tx_chain_cons);
4732                         bce_breakpoint(sc));
4733
4734                 DBRUN(BCE_INFO_SEND,
4735                       if_printf(ifp, "%s(): ", __func__);
4736                       bce_dump_txbd(sc, sw_tx_chain_cons, txbd));
4737
4738                 /*
4739                  * Free the associated mbuf. Remember
4740                  * that only the last tx_bd of a packet
4741                  * has an mbuf pointer and DMA map.
4742                  */
4743                 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
4744                         /* Validate that this is the last tx_bd. */
4745                         DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)),
4746                                 if_printf(ifp, "%s(%d): "
4747                                 "tx_bd END flag not set but "
4748                                 "txmbuf == NULL!\n", __FILE__, __LINE__);
4749                                 bce_breakpoint(sc));
4750
4751                         DBRUN(BCE_INFO_SEND,
4752                               if_printf(ifp, "%s(): Unloading map/freeing mbuf "
4753                                         "from tx_bd[0x%04X]\n", __func__,
4754                                         sw_tx_chain_cons));
4755
4756                         /* Unmap the mbuf. */
4757                         bus_dmamap_unload(sc->tx_mbuf_tag,
4758                                           sc->tx_mbuf_map[sw_tx_chain_cons]);
4759
4760                         /* Free the mbuf. */
4761                         m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
4762                         sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
4763                         DBRUNIF(1, sc->tx_mbuf_alloc--);
4764
4765                         ifp->if_opackets++;
4766                 }
4767
4768                 sc->used_tx_bd--;
4769                 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
4770
4771                 if (sw_tx_cons == hw_tx_cons) {
4772                         /* Refresh hw_cons to see if there's new work. */
4773                         hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
4774                 }
4775
4776                 /*
4777                  * Prevent speculative reads from getting
4778                  * ahead of the status block.
4779                  */
4780                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4781                                   BUS_SPACE_BARRIER_READ);
4782         }
4783
4784         if (sc->used_tx_bd == 0) {
4785                 /* Clear the TX timeout timer. */
4786                 ifp->if_timer = 0;
4787         }
4788
4789         /* Clear the tx hardware queue full flag. */
4790         if (sc->max_tx_bd - sc->used_tx_bd >= BCE_TX_SPARE_SPACE) {
4791                 DBRUNIF((ifp->if_flags & IFF_OACTIVE),
4792                         DBPRINT(sc, BCE_WARN_SEND,
4793                                 "%s(): Open TX chain! %d/%d (used/total)\n",
4794                                 __func__, sc->used_tx_bd, sc->max_tx_bd));
4795                 ifp->if_flags &= ~IFF_OACTIVE;
4796         }
4797         sc->tx_cons = sw_tx_cons;
4798 }
4799
4800
4801 /****************************************************************************/
4802 /* Disables interrupt generation.                                           */
4803 /*                                                                          */
4804 /* Returns:                                                                 */
4805 /*   Nothing.                                                               */
4806 /****************************************************************************/
4807 static void
4808 bce_disable_intr(struct bce_softc *sc)
4809 {
4810         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
4811         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
4812         lwkt_serialize_handler_disable(sc->arpcom.ac_if.if_serializer);
4813 }
4814
4815
4816 /****************************************************************************/
4817 /* Enables interrupt generation.                                            */
4818 /*                                                                          */
4819 /* Returns:                                                                 */
4820 /*   Nothing.                                                               */
4821 /****************************************************************************/
4822 static void
4823 bce_enable_intr(struct bce_softc *sc, int coal_now)
4824 {
4825         lwkt_serialize_handler_enable(sc->arpcom.ac_if.if_serializer);
4826
4827         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4828                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
4829                BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
4830
4831         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
4832                BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
4833
4834         if (coal_now) {
4835                 REG_WR(sc, BCE_HC_COMMAND,
4836                     sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
4837         }
4838 }
4839
4840
4841 /****************************************************************************/
4842 /* Handles controller initialization.                                       */
4843 /*                                                                          */
4844 /* Returns:                                                                 */
4845 /*   Nothing.                                                               */
4846 /****************************************************************************/
4847 static void
4848 bce_init(void *xsc)
4849 {
4850         struct bce_softc *sc = xsc;
4851         struct ifnet *ifp = &sc->arpcom.ac_if;
4852         uint32_t ether_mtu;
4853         int error;
4854
4855         ASSERT_SERIALIZED(ifp->if_serializer);
4856
4857         /* Check if the driver is still running and bail out if it is. */
4858         if (ifp->if_flags & IFF_RUNNING)
4859                 return;
4860
4861         bce_stop(sc);
4862
4863         error = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
4864         if (error) {
4865                 if_printf(ifp, "Controller reset failed!\n");
4866                 goto back;
4867         }
4868
4869         error = bce_chipinit(sc);
4870         if (error) {
4871                 if_printf(ifp, "Controller initialization failed!\n");
4872                 goto back;
4873         }
4874
4875         error = bce_blockinit(sc);
4876         if (error) {
4877                 if_printf(ifp, "Block initialization failed!\n");
4878                 goto back;
4879         }
4880
4881         /* Load our MAC address. */
4882         bcopy(IF_LLADDR(ifp), sc->eaddr, ETHER_ADDR_LEN);
4883         bce_set_mac_addr(sc);
4884
4885         /* Calculate and program the Ethernet MTU size. */
4886         ether_mtu = ETHER_HDR_LEN + EVL_ENCAPLEN + ifp->if_mtu + ETHER_CRC_LEN;
4887
4888         DBPRINT(sc, BCE_INFO, "%s(): setting mtu = %d\n", __func__, ether_mtu);
4889
4890         /*
4891          * Program the mtu, enabling jumbo frame
4892          * support if necessary.  Also set the mbuf
4893          * allocation count for RX frames.
4894          */
4895         if (ether_mtu > ETHER_MAX_LEN + EVL_ENCAPLEN) {
4896 #ifdef notyet
4897                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
4898                        min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
4899                        BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
4900                 sc->mbuf_alloc_size = MJUM9BYTES;
4901 #else
4902                 panic("jumbo buffer is not supported yet");
4903 #endif
4904         } else {
4905                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
4906                 sc->mbuf_alloc_size = MCLBYTES;
4907         }
4908
4909         /* Calculate the RX Ethernet frame size for rx_bd's. */
4910         sc->max_frame_size = sizeof(struct l2_fhdr) + 2 + ether_mtu + 8;
4911
4912         DBPRINT(sc, BCE_INFO,
4913                 "%s(): mclbytes = %d, mbuf_alloc_size = %d, "
4914                 "max_frame_size = %d\n",
4915                 __func__, (int)MCLBYTES, sc->mbuf_alloc_size,
4916                 sc->max_frame_size);
4917
4918         /* Program appropriate promiscuous/multicast filtering. */
4919         bce_set_rx_mode(sc);
4920
4921         /* Init RX buffer descriptor chain. */
4922         bce_init_rx_chain(sc);  /* XXX return value */
4923
4924         /* Init TX buffer descriptor chain. */
4925         bce_init_tx_chain(sc);  /* XXX return value */
4926
4927 #ifdef DEVICE_POLLING
4928         /* Disable interrupts if we are polling. */
4929         if (ifp->if_flags & IFF_POLLING) {
4930                 bce_disable_intr(sc);
4931
4932                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4933                        (1 << 16) | sc->bce_rx_quick_cons_trip);
4934                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4935                        (1 << 16) | sc->bce_tx_quick_cons_trip);
4936         } else
4937 #endif
4938         /* Enable host interrupts. */
4939         bce_enable_intr(sc, 1);
4940
4941         bce_ifmedia_upd(ifp);
4942
4943         ifp->if_flags |= IFF_RUNNING;
4944         ifp->if_flags &= ~IFF_OACTIVE;
4945
4946         callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
4947 back:
4948         if (error)
4949                 bce_stop(sc);
4950 }
4951
4952
4953 /****************************************************************************/
4954 /* Initialize the controller just enough so that any management firmware    */
4955 /* running on the device will continue to operate corectly.                 */
4956 /*                                                                          */
4957 /* Returns:                                                                 */
4958 /*   Nothing.                                                               */
4959 /****************************************************************************/
4960 static void
4961 bce_mgmt_init(struct bce_softc *sc)
4962 {
4963         struct ifnet *ifp = &sc->arpcom.ac_if;
4964
4965         /* Bail out if management firmware is not running. */
4966         if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
4967                 return;
4968
4969         /* Enable all critical blocks in the MAC. */
4970         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
4971             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
4972                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
4973                     BCE_MISC_ENABLE_DEFAULT_XI);
4974         } else {
4975                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
4976         }
4977         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
4978         DELAY(20);
4979
4980         bce_ifmedia_upd(ifp);
4981 }
4982
4983
4984 /****************************************************************************/
4985 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
4986 /* memory visible to the controller.                                        */
4987 /*                                                                          */
4988 /* Returns:                                                                 */
4989 /*   0 for success, positive value for failure.                             */
4990 /****************************************************************************/
4991 static int
4992 bce_encap(struct bce_softc *sc, struct mbuf **m_head)
4993 {
4994         bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
4995         bus_dmamap_t map, tmp_map;
4996         struct mbuf *m0 = *m_head;
4997         struct tx_bd *txbd = NULL;
4998         uint16_t vlan_tag = 0, flags = 0;
4999         uint16_t chain_prod, chain_prod_start, prod;
5000         uint32_t prod_bseq;
5001         int i, error, maxsegs, nsegs;
5002 #ifdef BCE_DEBUG
5003         uint16_t debug_prod;
5004 #endif
5005
5006         /* Transfer any checksum offload flags to the bd. */
5007         if (m0->m_pkthdr.csum_flags) {
5008                 if (m0->m_pkthdr.csum_flags & CSUM_IP)
5009                         flags |= TX_BD_FLAGS_IP_CKSUM;
5010                 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
5011                         flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
5012         }
5013
5014         /* Transfer any VLAN tags to the bd. */
5015         if (m0->m_flags & M_VLANTAG) {
5016                 flags |= TX_BD_FLAGS_VLAN_TAG;
5017                 vlan_tag = m0->m_pkthdr.ether_vlantag;
5018         }
5019
5020         prod = sc->tx_prod;
5021         chain_prod_start = chain_prod = TX_CHAIN_IDX(sc, prod);
5022
5023         /* Map the mbuf into DMAable memory. */
5024         map = sc->tx_mbuf_map[chain_prod_start];
5025
5026         maxsegs = sc->max_tx_bd - sc->used_tx_bd;
5027         KASSERT(maxsegs >= BCE_TX_SPARE_SPACE,
5028                 ("not enough segments %d", maxsegs));
5029         if (maxsegs > BCE_MAX_SEGMENTS)
5030                 maxsegs = BCE_MAX_SEGMENTS;
5031
5032         /* Map the mbuf into our DMA address space. */
5033         error = bus_dmamap_load_mbuf_defrag(sc->tx_mbuf_tag, map, m_head,
5034                         segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
5035         if (error)
5036                 goto back;
5037         bus_dmamap_sync(sc->tx_mbuf_tag, map, BUS_DMASYNC_PREWRITE);
5038
5039         /* Reset m0 */
5040         m0 = *m_head;
5041
5042         /* prod points to an empty tx_bd at this point. */
5043         prod_bseq  = sc->tx_prod_bseq;
5044
5045 #ifdef BCE_DEBUG
5046         debug_prod = chain_prod;
5047 #endif
5048
5049         DBPRINT(sc, BCE_INFO_SEND,
5050                 "%s(): Start: prod = 0x%04X, chain_prod = %04X, "
5051                 "prod_bseq = 0x%08X\n",
5052                 __func__, prod, chain_prod, prod_bseq);
5053
5054         /*
5055          * Cycle through each mbuf segment that makes up
5056          * the outgoing frame, gathering the mapping info
5057          * for that segment and creating a tx_bd to for
5058          * the mbuf.
5059          */
5060         for (i = 0; i < nsegs; i++) {
5061                 chain_prod = TX_CHAIN_IDX(sc, prod);
5062                 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)][TX_IDX(chain_prod)];
5063
5064                 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[i].ds_addr));
5065                 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[i].ds_addr));
5066                 txbd->tx_bd_mss_nbytes = htole16(segs[i].ds_len);
5067                 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
5068                 txbd->tx_bd_flags = htole16(flags);
5069                 prod_bseq += segs[i].ds_len;
5070                 if (i == 0)
5071                         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
5072                 prod = NEXT_TX_BD(prod);
5073         }
5074
5075         /* Set the END flag on the last TX buffer descriptor. */
5076         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
5077
5078         DBRUN(BCE_EXCESSIVE_SEND,
5079               bce_dump_tx_chain(sc, debug_prod, nsegs));
5080
5081         DBPRINT(sc, BCE_INFO_SEND,
5082                 "%s(): End: prod = 0x%04X, chain_prod = %04X, "
5083                 "prod_bseq = 0x%08X\n",
5084                 __func__, prod, chain_prod, prod_bseq);
5085
5086         /*
5087          * Ensure that the mbuf pointer for this transmission
5088          * is placed at the array index of the last
5089          * descriptor in this chain.  This is done
5090          * because a single map is used for all
5091          * segments of the mbuf and we don't want to
5092          * unload the map before all of the segments
5093          * have been freed.
5094          */
5095         sc->tx_mbuf_ptr[chain_prod] = m0;
5096
5097         tmp_map = sc->tx_mbuf_map[chain_prod];
5098         sc->tx_mbuf_map[chain_prod] = map;
5099         sc->tx_mbuf_map[chain_prod_start] = tmp_map;
5100
5101         sc->used_tx_bd += nsegs;
5102
5103         /* Update some debug statistic counters */
5104         DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
5105                 sc->tx_hi_watermark = sc->used_tx_bd);
5106         DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
5107         DBRUNIF(1, sc->tx_mbuf_alloc++);
5108
5109         DBRUN(BCE_VERBOSE_SEND,
5110               bce_dump_tx_mbuf_chain(sc, chain_prod, nsegs));
5111
5112         /* prod points to the next free tx_bd at this point. */
5113         sc->tx_prod = prod;
5114         sc->tx_prod_bseq = prod_bseq;
5115 back:
5116         if (error) {
5117                 m_freem(*m_head);
5118                 *m_head = NULL;
5119         }
5120         return error;
5121 }
5122
5123
5124 /****************************************************************************/
5125 /* Main transmit routine when called from another routine with a lock.      */
5126 /*                                                                          */
5127 /* Returns:                                                                 */
5128 /*   Nothing.                                                               */
5129 /****************************************************************************/
5130 static void
5131 bce_start(struct ifnet *ifp)
5132 {
5133         struct bce_softc *sc = ifp->if_softc;
5134         int count = 0;
5135
5136         ASSERT_SERIALIZED(ifp->if_serializer);
5137
5138         /* If there's no link or the transmit queue is empty then just exit. */
5139         if (!sc->bce_link) {
5140                 ifq_purge(&ifp->if_snd);
5141                 return;
5142         }
5143
5144         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
5145                 return;
5146
5147         DBPRINT(sc, BCE_INFO_SEND,
5148                 "%s(): Start: tx_prod = 0x%04X, tx_chain_prod = %04zX, "
5149                 "tx_prod_bseq = 0x%08X\n",
5150                 __func__,
5151                 sc->tx_prod, TX_CHAIN_IDX(sc, sc->tx_prod), sc->tx_prod_bseq);
5152
5153         for (;;) {
5154                 struct mbuf *m_head;
5155
5156                 /*
5157                  * We keep BCE_TX_SPARE_SPACE entries, so bce_encap() is
5158                  * unlikely to fail.
5159                  */
5160                 if (sc->max_tx_bd - sc->used_tx_bd < BCE_TX_SPARE_SPACE) {
5161                         ifp->if_flags |= IFF_OACTIVE;
5162                         break;
5163                 }
5164
5165                 /* Check for any frames to send. */
5166                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
5167                 if (m_head == NULL)
5168                         break;
5169
5170                 /*
5171                  * Pack the data into the transmit ring. If we
5172                  * don't have room, place the mbuf back at the
5173                  * head of the queue and set the OACTIVE flag
5174                  * to wait for the NIC to drain the chain.
5175                  */
5176                 if (bce_encap(sc, &m_head)) {
5177                         ifp->if_oerrors++;
5178                         if (sc->used_tx_bd == 0) {
5179                                 continue;
5180                         } else {
5181                                 ifp->if_flags |= IFF_OACTIVE;
5182                                 break;
5183                         }
5184                 }
5185
5186                 count++;
5187
5188                 /* Send a copy of the frame to any BPF listeners. */
5189                 ETHER_BPF_MTAP(ifp, m_head);
5190         }
5191
5192         if (count == 0) {
5193                 /* no packets were dequeued */
5194                 DBPRINT(sc, BCE_VERBOSE_SEND,
5195                         "%s(): No packets were dequeued\n", __func__);
5196                 return;
5197         }
5198
5199         DBPRINT(sc, BCE_INFO_SEND,
5200                 "%s(): End: tx_prod = 0x%04X, tx_chain_prod = 0x%04zX, "
5201                 "tx_prod_bseq = 0x%08X\n",
5202                 __func__,
5203                 sc->tx_prod, TX_CHAIN_IDX(sc, sc->tx_prod), sc->tx_prod_bseq);
5204
5205         REG_WR(sc, BCE_MQ_COMMAND,
5206             REG_RD(sc, BCE_MQ_COMMAND) | BCE_MQ_COMMAND_NO_MAP_ERROR);
5207
5208         /* Start the transmit. */
5209         REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BIDX, sc->tx_prod);
5210         REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq);
5211
5212         /* Set the tx timeout. */
5213         ifp->if_timer = BCE_TX_TIMEOUT;
5214 }
5215
5216
5217 /****************************************************************************/
5218 /* Handles any IOCTL calls from the operating system.                       */
5219 /*                                                                          */
5220 /* Returns:                                                                 */
5221 /*   0 for success, positive value for failure.                             */
5222 /****************************************************************************/
5223 static int
5224 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
5225 {
5226         struct bce_softc *sc = ifp->if_softc;
5227         struct ifreq *ifr = (struct ifreq *)data;
5228         struct mii_data *mii;
5229         int mask, error = 0;
5230
5231         ASSERT_SERIALIZED(ifp->if_serializer);
5232
5233         switch(command) {
5234         case SIOCSIFMTU:
5235                 /* Check that the MTU setting is supported. */
5236                 if (ifr->ifr_mtu < BCE_MIN_MTU ||
5237 #ifdef notyet
5238                     ifr->ifr_mtu > BCE_MAX_JUMBO_MTU
5239 #else
5240                     ifr->ifr_mtu > ETHERMTU
5241 #endif
5242                    ) {
5243                         error = EINVAL;
5244                         break;
5245                 }
5246
5247                 DBPRINT(sc, BCE_INFO, "Setting new MTU of %d\n", ifr->ifr_mtu);
5248
5249                 ifp->if_mtu = ifr->ifr_mtu;
5250                 ifp->if_flags &= ~IFF_RUNNING;  /* Force reinitialize */
5251                 bce_init(sc);
5252                 break;
5253
5254         case SIOCSIFFLAGS:
5255                 if (ifp->if_flags & IFF_UP) {
5256                         if (ifp->if_flags & IFF_RUNNING) {
5257                                 mask = ifp->if_flags ^ sc->bce_if_flags;
5258
5259                                 if (mask & (IFF_PROMISC | IFF_ALLMULTI))
5260                                         bce_set_rx_mode(sc);
5261                         } else {
5262                                 bce_init(sc);
5263                         }
5264                 } else if (ifp->if_flags & IFF_RUNNING) {
5265                         bce_stop(sc);
5266
5267                         /* If MFW is running, restart the controller a bit. */
5268                         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5269                                 bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
5270                                 bce_chipinit(sc);
5271                                 bce_mgmt_init(sc);
5272                         }
5273                 }
5274                 sc->bce_if_flags = ifp->if_flags;
5275                 break;
5276
5277         case SIOCADDMULTI:
5278         case SIOCDELMULTI:
5279                 if (ifp->if_flags & IFF_RUNNING)
5280                         bce_set_rx_mode(sc);
5281                 break;
5282
5283         case SIOCSIFMEDIA:
5284         case SIOCGIFMEDIA:
5285                 DBPRINT(sc, BCE_VERBOSE, "bce_phy_flags = 0x%08X\n",
5286                         sc->bce_phy_flags);
5287                 DBPRINT(sc, BCE_VERBOSE, "Copper media set/get\n");
5288
5289                 mii = device_get_softc(sc->bce_miibus);
5290                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
5291                 break;
5292
5293         case SIOCSIFCAP:
5294                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
5295                 DBPRINT(sc, BCE_INFO, "Received SIOCSIFCAP = 0x%08X\n",
5296                         (uint32_t) mask);
5297
5298                 if (mask & IFCAP_HWCSUM) {
5299                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
5300                         if (IFCAP_HWCSUM & ifp->if_capenable)
5301                                 ifp->if_hwassist = BCE_IF_HWASSIST;
5302                         else
5303                                 ifp->if_hwassist = 0;
5304                 }
5305                 break;
5306
5307         default:
5308                 error = ether_ioctl(ifp, command, data);
5309                 break;
5310         }
5311         return error;
5312 }
5313
5314
5315 /****************************************************************************/
5316 /* Transmit timeout handler.                                                */
5317 /*                                                                          */
5318 /* Returns:                                                                 */
5319 /*   Nothing.                                                               */
5320 /****************************************************************************/
5321 static void
5322 bce_watchdog(struct ifnet *ifp)
5323 {
5324         struct bce_softc *sc = ifp->if_softc;
5325
5326         ASSERT_SERIALIZED(ifp->if_serializer);
5327
5328         DBRUN(BCE_VERBOSE_SEND,
5329               bce_dump_driver_state(sc);
5330               bce_dump_status_block(sc));
5331
5332         /*
5333          * If we are in this routine because of pause frames, then
5334          * don't reset the hardware.
5335          */
5336         if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED)
5337                 return;
5338
5339         if_printf(ifp, "Watchdog timeout occurred, resetting!\n");
5340
5341         /* DBRUN(BCE_FATAL, bce_breakpoint(sc)); */
5342
5343         ifp->if_flags &= ~IFF_RUNNING;  /* Force reinitialize */
5344         bce_init(sc);
5345
5346         ifp->if_oerrors++;
5347
5348         if (!ifq_is_empty(&ifp->if_snd))
5349                 if_devstart(ifp);
5350 }
5351
5352
5353 #ifdef DEVICE_POLLING
5354
5355 static void
5356 bce_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
5357 {
5358         struct bce_softc *sc = ifp->if_softc;
5359         struct status_block *sblk = sc->status_block;
5360         uint16_t hw_tx_cons, hw_rx_cons;
5361
5362         ASSERT_SERIALIZED(ifp->if_serializer);
5363
5364         switch (cmd) {
5365         case POLL_REGISTER:
5366                 bce_disable_intr(sc);
5367
5368                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5369                        (1 << 16) | sc->bce_rx_quick_cons_trip);
5370                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5371                        (1 << 16) | sc->bce_tx_quick_cons_trip);
5372                 return;
5373         case POLL_DEREGISTER:
5374                 bce_enable_intr(sc, 1);
5375
5376                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5377                        (sc->bce_tx_quick_cons_trip_int << 16) |
5378                        sc->bce_tx_quick_cons_trip);
5379                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5380                        (sc->bce_rx_quick_cons_trip_int << 16) |
5381                        sc->bce_rx_quick_cons_trip);
5382                 return;
5383         default:
5384                 break;
5385         }
5386
5387         if (cmd == POLL_AND_CHECK_STATUS) {
5388                 uint32_t status_attn_bits;
5389
5390                 status_attn_bits = sblk->status_attn_bits;
5391
5392                 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
5393                         if_printf(ifp,
5394                         "Simulating unexpected status attention bit set.");
5395                         status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
5396
5397                 /* Was it a link change interrupt? */
5398                 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5399                     (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
5400                         bce_phy_intr(sc);
5401
5402                 /* Clear any transient status updates during link state change. */
5403                 REG_WR(sc, BCE_HC_COMMAND,
5404                     sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5405                 REG_RD(sc, BCE_HC_COMMAND);
5406
5407                 /*
5408                  * If any other attention is asserted then
5409                  * the chip is toast.
5410                  */
5411                 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5412                      (sblk->status_attn_bits_ack &
5413                       ~STATUS_ATTN_BITS_LINK_STATE)) {
5414                         DBRUN(1, sc->unexpected_attentions++);
5415
5416                         if_printf(ifp, "Fatal attention detected: 0x%08X\n",
5417                                   sblk->status_attn_bits);
5418
5419                         DBRUN(BCE_FATAL,
5420                         if (bce_debug_unexpected_attention == 0)
5421                                 bce_breakpoint(sc));
5422
5423                         bce_init(sc);
5424                         return;
5425                 }
5426         }
5427
5428         hw_rx_cons = bce_get_hw_rx_cons(sc);
5429         hw_tx_cons = bce_get_hw_tx_cons(sc);
5430
5431         /* Check for any completed RX frames. */
5432         if (hw_rx_cons != sc->hw_rx_cons)
5433                 bce_rx_intr(sc, count);
5434
5435         /* Check for any completed TX frames. */
5436         if (hw_tx_cons != sc->hw_tx_cons)
5437                 bce_tx_intr(sc);
5438
5439         /* Check for new frames to transmit. */
5440         if (!ifq_is_empty(&ifp->if_snd))
5441                 if_devstart(ifp);
5442 }
5443
5444 #endif  /* DEVICE_POLLING */
5445
5446
5447 /*
5448  * Interrupt handler.
5449  */
5450 /****************************************************************************/
5451 /* Main interrupt entry point.  Verifies that the controller generated the  */
5452 /* interrupt and then calls a separate routine for handle the various       */
5453 /* interrupt causes (PHY, TX, RX).                                          */
5454 /*                                                                          */
5455 /* Returns:                                                                 */
5456 /*   0 for success, positive value for failure.                             */
5457 /****************************************************************************/
5458 static void
5459 bce_intr(struct bce_softc *sc)
5460 {
5461         struct ifnet *ifp = &sc->arpcom.ac_if;
5462         struct status_block *sblk;
5463         uint16_t hw_rx_cons, hw_tx_cons;
5464
5465         ASSERT_SERIALIZED(ifp->if_serializer);
5466
5467         DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
5468         DBRUNIF(1, sc->interrupts_generated++);
5469
5470         sblk = sc->status_block;
5471
5472         /* Check if the hardware has finished any work. */
5473         hw_rx_cons = bce_get_hw_rx_cons(sc);
5474         hw_tx_cons = bce_get_hw_tx_cons(sc);
5475
5476         /* Keep processing data as long as there is work to do. */
5477         for (;;) {
5478                 uint32_t status_attn_bits;
5479
5480                 status_attn_bits = sblk->status_attn_bits;
5481
5482                 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
5483                         if_printf(ifp,
5484                         "Simulating unexpected status attention bit set.");
5485                         status_attn_bits |= STATUS_ATTN_BITS_PARITY_ERROR);
5486
5487                 /* Was it a link change interrupt? */
5488                 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5489                     (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) {
5490                         bce_phy_intr(sc);
5491
5492                         /*
5493                          * Clear any transient status updates during link state
5494                          * change.
5495                          */
5496                         REG_WR(sc, BCE_HC_COMMAND,
5497                             sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
5498                         REG_RD(sc, BCE_HC_COMMAND);
5499                 }
5500
5501                 /*
5502                  * If any other attention is asserted then
5503                  * the chip is toast.
5504                  */
5505                 if ((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5506                      (sblk->status_attn_bits_ack &
5507                       ~STATUS_ATTN_BITS_LINK_STATE)) {
5508                         DBRUN(1, sc->unexpected_attentions++);
5509
5510                         if_printf(ifp, "Fatal attention detected: 0x%08X\n",
5511                                   sblk->status_attn_bits);
5512
5513                         DBRUN(BCE_FATAL,
5514                         if (bce_debug_unexpected_attention == 0)
5515                                 bce_breakpoint(sc));
5516
5517                         bce_init(sc);
5518                         return;
5519                 }
5520
5521                 /* Check for any completed RX frames. */
5522                 if (hw_rx_cons != sc->hw_rx_cons)
5523                         bce_rx_intr(sc, -1);
5524
5525                 /* Check for any completed TX frames. */
5526                 if (hw_tx_cons != sc->hw_tx_cons)
5527                         bce_tx_intr(sc);
5528
5529                 /*
5530                  * Save the status block index value
5531                  * for use during the next interrupt.
5532                  */
5533                 sc->last_status_idx = sblk->status_idx;
5534
5535                 /*
5536                  * Prevent speculative reads from getting
5537                  * ahead of the status block.
5538                  */
5539                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
5540                                   BUS_SPACE_BARRIER_READ);
5541
5542                 /*
5543                  * If there's no work left then exit the
5544                  * interrupt service routine.
5545                  */
5546                 hw_rx_cons = bce_get_hw_rx_cons(sc);
5547                 hw_tx_cons = bce_get_hw_tx_cons(sc);
5548                 if ((hw_rx_cons == sc->hw_rx_cons) && (hw_tx_cons == sc->hw_tx_cons))
5549                         break;
5550         }
5551
5552         /* Re-enable interrupts. */
5553         bce_enable_intr(sc, 0);
5554
5555         if (sc->bce_coalchg_mask)
5556                 bce_coal_change(sc);
5557
5558         /* Handle any frames that arrived while handling the interrupt. */
5559         if (!ifq_is_empty(&ifp->if_snd))
5560                 if_devstart(ifp);
5561 }
5562
5563 static void
5564 bce_intr_legacy(void *xsc)
5565 {
5566         struct bce_softc *sc = xsc;
5567         struct status_block *sblk;
5568
5569         sblk = sc->status_block;
5570
5571         /*
5572          * If the hardware status block index matches the last value
5573          * read by the driver and we haven't asserted our interrupt
5574          * then there's nothing to do.
5575          */
5576         if (sblk->status_idx == sc->last_status_idx &&
5577             (REG_RD(sc, BCE_PCICFG_MISC_STATUS) &
5578              BCE_PCICFG_MISC_STATUS_INTA_VALUE))
5579                 return;
5580
5581         /* Ack the interrupt and stop others from occuring. */
5582         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5583                BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
5584                BCE_PCICFG_INT_ACK_CMD_MASK_INT);
5585
5586         /*
5587          * Read back to deassert IRQ immediately to avoid too
5588          * many spurious interrupts.
5589          */
5590         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
5591
5592         bce_intr(sc);
5593 }
5594
5595 static void
5596 bce_intr_msi(void *xsc)
5597 {
5598         struct bce_softc *sc = xsc;
5599
5600         /* Ack the interrupt and stop others from occuring. */
5601         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5602                BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
5603                BCE_PCICFG_INT_ACK_CMD_MASK_INT);
5604
5605         bce_intr(sc);
5606 }
5607
5608 static void
5609 bce_intr_msi_oneshot(void *xsc)
5610 {
5611         bce_intr(xsc);
5612 }
5613
5614
5615 /****************************************************************************/
5616 /* Programs the various packet receive modes (broadcast and multicast).     */
5617 /*                                                                          */
5618 /* Returns:                                                                 */
5619 /*   Nothing.                                                               */
5620 /****************************************************************************/
5621 static void
5622 bce_set_rx_mode(struct bce_softc *sc)
5623 {
5624         struct ifnet *ifp = &sc->arpcom.ac_if;
5625         struct ifmultiaddr *ifma;
5626         uint32_t hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
5627         uint32_t rx_mode, sort_mode;
5628         int h, i;
5629
5630         ASSERT_SERIALIZED(ifp->if_serializer);
5631
5632         /* Initialize receive mode default settings. */
5633         rx_mode = sc->rx_mode &
5634                   ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
5635                     BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
5636         sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
5637
5638         /*
5639          * ASF/IPMI/UMP firmware requires that VLAN tag stripping
5640          * be enbled.
5641          */
5642         if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
5643             !(sc->bce_flags & BCE_MFW_ENABLE_FLAG))
5644                 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
5645
5646         /*
5647          * Check for promiscuous, all multicast, or selected
5648          * multicast address filtering.
5649          */
5650         if (ifp->if_flags & IFF_PROMISC) {
5651                 DBPRINT(sc, BCE_INFO, "Enabling promiscuous mode.\n");
5652
5653                 /* Enable promiscuous mode. */
5654                 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
5655                 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
5656         } else if (ifp->if_flags & IFF_ALLMULTI) {
5657                 DBPRINT(sc, BCE_INFO, "Enabling all multicast mode.\n");
5658
5659                 /* Enable all multicast addresses. */
5660                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5661                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5662                                0xffffffff);
5663                 }
5664                 sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
5665         } else {
5666                 /* Accept one or more multicast(s). */
5667                 DBPRINT(sc, BCE_INFO, "Enabling selective multicast mode.\n");
5668
5669                 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
5670                         if (ifma->ifma_addr->sa_family != AF_LINK)
5671                                 continue;
5672                         h = ether_crc32_le(
5673                             LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
5674                             ETHER_ADDR_LEN) & 0xFF;
5675                         hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
5676                 }
5677
5678                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
5679                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
5680                                hashes[i]);
5681                 }
5682                 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
5683         }
5684
5685         /* Only make changes if the recive mode has actually changed. */
5686         if (rx_mode != sc->rx_mode) {
5687                 DBPRINT(sc, BCE_VERBOSE, "Enabling new receive mode: 0x%08X\n",
5688                         rx_mode);
5689
5690                 sc->rx_mode = rx_mode;
5691                 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
5692         }
5693
5694         /* Disable and clear the exisitng sort before enabling a new sort. */
5695         REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
5696         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
5697         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
5698 }
5699
5700
5701 /****************************************************************************/
5702 /* Called periodically to updates statistics from the controllers           */
5703 /* statistics block.                                                        */
5704 /*                                                                          */
5705 /* Returns:                                                                 */
5706 /*   Nothing.                                                               */
5707 /****************************************************************************/
5708 static void
5709 bce_stats_update(struct bce_softc *sc)
5710 {
5711         struct ifnet *ifp = &sc->arpcom.ac_if;
5712         struct statistics_block *stats = sc->stats_block;
5713
5714         DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __func__);
5715
5716         ASSERT_SERIALIZED(ifp->if_serializer);
5717
5718         /*
5719          * Certain controllers don't report carrier sense errors correctly.
5720          * See errata E11_5708CA0_1165.
5721          */
5722         if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
5723             !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0)) {
5724                 ifp->if_oerrors +=
5725                         (u_long)stats->stat_Dot3StatsCarrierSenseErrors;
5726         }
5727
5728         /*
5729          * Update the sysctl statistics from the hardware statistics.
5730          */
5731         sc->stat_IfHCInOctets =
5732                 ((uint64_t)stats->stat_IfHCInOctets_hi << 32) +
5733                  (uint64_t)stats->stat_IfHCInOctets_lo;
5734
5735         sc->stat_IfHCInBadOctets =
5736                 ((uint64_t)stats->stat_IfHCInBadOctets_hi << 32) +
5737                  (uint64_t)stats->stat_IfHCInBadOctets_lo;
5738
5739         sc->stat_IfHCOutOctets =
5740                 ((uint64_t)stats->stat_IfHCOutOctets_hi << 32) +
5741                  (uint64_t)stats->stat_IfHCOutOctets_lo;
5742
5743         sc->stat_IfHCOutBadOctets =
5744                 ((uint64_t)stats->stat_IfHCOutBadOctets_hi << 32) +
5745                  (uint64_t)stats->stat_IfHCOutBadOctets_lo;
5746
5747         sc->stat_IfHCInUcastPkts =
5748                 ((uint64_t)stats->stat_IfHCInUcastPkts_hi << 32) +
5749                  (uint64_t)stats->stat_IfHCInUcastPkts_lo;
5750
5751         sc->stat_IfHCInMulticastPkts =
5752                 ((uint64_t)stats->stat_IfHCInMulticastPkts_hi << 32) +
5753                  (uint64_t)stats->stat_IfHCInMulticastPkts_lo;
5754
5755         sc->stat_IfHCInBroadcastPkts =
5756                 ((uint64_t)stats->stat_IfHCInBroadcastPkts_hi << 32) +
5757                  (uint64_t)stats->stat_IfHCInBroadcastPkts_lo;
5758
5759         sc->stat_IfHCOutUcastPkts =
5760                 ((uint64_t)stats->stat_IfHCOutUcastPkts_hi << 32) +
5761                  (uint64_t)stats->stat_IfHCOutUcastPkts_lo;
5762
5763         sc->stat_IfHCOutMulticastPkts =
5764                 ((uint64_t)stats->stat_IfHCOutMulticastPkts_hi << 32) +
5765                  (uint64_t)stats->stat_IfHCOutMulticastPkts_lo;
5766
5767         sc->stat_IfHCOutBroadcastPkts =
5768                 ((uint64_t)stats->stat_IfHCOutBroadcastPkts_hi << 32) +
5769                  (uint64_t)stats->stat_IfHCOutBroadcastPkts_lo;
5770
5771         sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
5772                 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
5773
5774         sc->stat_Dot3StatsCarrierSenseErrors =
5775                 stats->stat_Dot3StatsCarrierSenseErrors;
5776
5777         sc->stat_Dot3StatsFCSErrors =
5778                 stats->stat_Dot3StatsFCSErrors;
5779
5780         sc->stat_Dot3StatsAlignmentErrors =
5781                 stats->stat_Dot3StatsAlignmentErrors;
5782
5783         sc->stat_Dot3StatsSingleCollisionFrames =
5784                 stats->stat_Dot3StatsSingleCollisionFrames;
5785
5786         sc->stat_Dot3StatsMultipleCollisionFrames =
5787                 stats->stat_Dot3StatsMultipleCollisionFrames;
5788
5789         sc->stat_Dot3StatsDeferredTransmissions =
5790                 stats->stat_Dot3StatsDeferredTransmissions;
5791
5792         sc->stat_Dot3StatsExcessiveCollisions =
5793                 stats->stat_Dot3StatsExcessiveCollisions;
5794
5795         sc->stat_Dot3StatsLateCollisions =
5796                 stats->stat_Dot3StatsLateCollisions;
5797
5798         sc->stat_EtherStatsCollisions =
5799                 stats->stat_EtherStatsCollisions;
5800
5801         sc->stat_EtherStatsFragments =
5802                 stats->stat_EtherStatsFragments;
5803
5804         sc->stat_EtherStatsJabbers =
5805                 stats->stat_EtherStatsJabbers;
5806
5807         sc->stat_EtherStatsUndersizePkts =
5808                 stats->stat_EtherStatsUndersizePkts;
5809
5810         sc->stat_EtherStatsOverrsizePkts =
5811                 stats->stat_EtherStatsOverrsizePkts;
5812
5813         sc->stat_EtherStatsPktsRx64Octets =
5814                 stats->stat_EtherStatsPktsRx64Octets;
5815
5816         sc->stat_EtherStatsPktsRx65Octetsto127Octets =
5817                 stats->stat_EtherStatsPktsRx65Octetsto127Octets;
5818
5819         sc->stat_EtherStatsPktsRx128Octetsto255Octets =
5820                 stats->stat_EtherStatsPktsRx128Octetsto255Octets;
5821
5822         sc->stat_EtherStatsPktsRx256Octetsto511Octets =
5823                 stats->stat_EtherStatsPktsRx256Octetsto511Octets;
5824
5825         sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
5826                 stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
5827
5828         sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
5829                 stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
5830
5831         sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
5832                 stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
5833
5834         sc->stat_EtherStatsPktsTx64Octets =
5835                 stats->stat_EtherStatsPktsTx64Octets;
5836
5837         sc->stat_EtherStatsPktsTx65Octetsto127Octets =
5838                 stats->stat_EtherStatsPktsTx65Octetsto127Octets;
5839
5840         sc->stat_EtherStatsPktsTx128Octetsto255Octets =
5841                 stats->stat_EtherStatsPktsTx128Octetsto255Octets;
5842
5843         sc->stat_EtherStatsPktsTx256Octetsto511Octets =
5844                 stats->stat_EtherStatsPktsTx256Octetsto511Octets;
5845
5846         sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
5847                 stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
5848
5849         sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
5850                 stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
5851
5852         sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
5853                 stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
5854
5855         sc->stat_XonPauseFramesReceived =
5856                 stats->stat_XonPauseFramesReceived;
5857
5858         sc->stat_XoffPauseFramesReceived =
5859                 stats->stat_XoffPauseFramesReceived;
5860
5861         sc->stat_OutXonSent =
5862                 stats->stat_OutXonSent;
5863
5864         sc->stat_OutXoffSent =
5865                 stats->stat_OutXoffSent;
5866
5867         sc->stat_FlowControlDone =
5868                 stats->stat_FlowControlDone;
5869
5870         sc->stat_MacControlFramesReceived =
5871                 stats->stat_MacControlFramesReceived;
5872
5873         sc->stat_XoffStateEntered =
5874                 stats->stat_XoffStateEntered;
5875
5876         sc->stat_IfInFramesL2FilterDiscards =
5877                 stats->stat_IfInFramesL2FilterDiscards;
5878
5879         sc->stat_IfInRuleCheckerDiscards =
5880                 stats->stat_IfInRuleCheckerDiscards;
5881
5882         sc->stat_IfInFTQDiscards =
5883                 stats->stat_IfInFTQDiscards;
5884
5885         sc->stat_IfInMBUFDiscards =
5886                 stats->stat_IfInMBUFDiscards;
5887
5888         sc->stat_IfInRuleCheckerP4Hit =
5889                 stats->stat_IfInRuleCheckerP4Hit;
5890
5891         sc->stat_CatchupInRuleCheckerDiscards =
5892                 stats->stat_CatchupInRuleCheckerDiscards;
5893
5894         sc->stat_CatchupInFTQDiscards =
5895                 stats->stat_CatchupInFTQDiscards;
5896
5897         sc->stat_CatchupInMBUFDiscards =
5898                 stats->stat_CatchupInMBUFDiscards;
5899
5900         sc->stat_CatchupInRuleCheckerP4Hit =
5901                 stats->stat_CatchupInRuleCheckerP4Hit;
5902
5903         sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
5904
5905         /*
5906          * Update the interface statistics from the
5907          * hardware statistics.
5908          */
5909         ifp->if_collisions = (u_long)sc->stat_EtherStatsCollisions;
5910
5911         ifp->if_ierrors = (u_long)sc->stat_EtherStatsUndersizePkts +
5912             (u_long)sc->stat_EtherStatsOverrsizePkts +
5913             (u_long)sc->stat_IfInMBUFDiscards +
5914             (u_long)sc->stat_Dot3StatsAlignmentErrors +
5915             (u_long)sc->stat_Dot3StatsFCSErrors +
5916             (u_long)sc->stat_IfInRuleCheckerDiscards +
5917             (u_long)sc->stat_IfInFTQDiscards +
5918             (u_long)sc->com_no_buffers;
5919
5920         ifp->if_oerrors =
5921             (u_long)sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
5922             (u_long)sc->stat_Dot3StatsExcessiveCollisions +
5923             (u_long)sc->stat_Dot3StatsLateCollisions;
5924
5925         DBPRINT(sc, BCE_EXCESSIVE, "Exiting %s()\n", __func__);
5926 }
5927
5928
5929 /****************************************************************************/
5930 /* Periodic function to notify the bootcode that the driver is still        */
5931 /* present.                                                                 */
5932 /*                                                                          */
5933 /* Returns:                                                                 */
5934 /*   Nothing.                                                               */
5935 /****************************************************************************/
5936 static void
5937 bce_pulse(void *xsc)
5938 {
5939         struct bce_softc *sc = xsc;
5940         struct ifnet *ifp = &sc->arpcom.ac_if;
5941         uint32_t msg;
5942
5943         lwkt_serialize_enter(ifp->if_serializer);
5944
5945         if (ifp->if_flags & IFF_RUNNING) {
5946                 if (sc->bce_irq_type == PCI_INTR_TYPE_MSI &&
5947                     (sc->bce_flags & BCE_ONESHOT_MSI_FLAG) == 0)
5948                         bce_pulse_check_msi(sc);
5949         }
5950
5951         /* Tell the firmware that the driver is still running. */
5952         msg = (uint32_t)++sc->bce_fw_drv_pulse_wr_seq;
5953         bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg);
5954
5955         /* Update the bootcode condition. */
5956         sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
5957
5958         /* Report whether the bootcode still knows the driver is running. */
5959         if (!sc->bce_drv_cardiac_arrest) {
5960                 if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) {
5961                         sc->bce_drv_cardiac_arrest = 1;
5962                         if_printf(ifp, "Bootcode lost the driver pulse! "
5963                             "(bc_state = 0x%08X)\n", sc->bc_state);
5964                 }
5965         } else {
5966                 /*
5967                  * Not supported by all bootcode versions.
5968                  * (v5.0.11+ and v5.2.1+)  Older bootcode
5969                  * will require the driver to reset the
5970                  * controller to clear this condition.
5971                  */
5972                 if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) {
5973                         sc->bce_drv_cardiac_arrest = 0;
5974                         if_printf(ifp, "Bootcode found the driver pulse! "
5975                             "(bc_state = 0x%08X)\n", sc->bc_state);
5976                 }
5977         }
5978
5979         /* Schedule the next pulse. */
5980         callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc);
5981
5982         lwkt_serialize_exit(ifp->if_serializer);
5983 }
5984
5985 static void
5986 bce_pulse_check_msi(struct bce_softc *sc)
5987 {
5988         int check = 0;
5989
5990         if (bce_get_hw_rx_cons(sc) != sc->hw_rx_cons) {
5991                 check = 1;
5992         } else if (bce_get_hw_tx_cons(sc) != sc->hw_tx_cons) {
5993                 check = 1;
5994         } else {
5995                 struct status_block *sblk = sc->status_block;
5996
5997                 if ((sblk->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5998                     (sblk->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
5999                         check = 1;
6000         }
6001
6002         if (check) {
6003                 uint32_t msi_ctrl;
6004
6005                 msi_ctrl = REG_RD(sc, BCE_PCICFG_MSI_CONTROL);
6006                 if ((msi_ctrl & BCE_PCICFG_MSI_CONTROL_ENABLE) == 0)
6007                         return;
6008
6009                 if (sc->pulse_check_status_idx == sc->last_status_idx) {
6010                         if_printf(&sc->arpcom.ac_if, "missing MSI\n");
6011
6012                         REG_WR(sc, BCE_PCICFG_MSI_CONTROL,
6013                             msi_ctrl & ~BCE_PCICFG_MSI_CONTROL_ENABLE);
6014                         REG_WR(sc, BCE_PCICFG_MSI_CONTROL, msi_ctrl);
6015
6016                         bce_intr_msi(sc);
6017                 }
6018         }
6019         sc->pulse_check_status_idx = sc->last_status_idx;
6020 }
6021
6022 /****************************************************************************/
6023 /* Periodic function to perform maintenance tasks.                          */
6024 /*                                                                          */
6025 /* Returns:                                                                 */
6026 /*   Nothing.                                                               */
6027 /****************************************************************************/
6028 static void
6029 bce_tick_serialized(struct bce_softc *sc)
6030 {
6031         struct ifnet *ifp = &sc->arpcom.ac_if;
6032         struct mii_data *mii;
6033
6034         ASSERT_SERIALIZED(ifp->if_serializer);
6035
6036         /* Update the statistics from the hardware statistics block. */
6037         bce_stats_update(sc);
6038
6039         /* Schedule the next tick. */
6040         callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
6041
6042         /* If link is up already up then we're done. */
6043         if (sc->bce_link)
6044                 return;
6045
6046         mii = device_get_softc(sc->bce_miibus);
6047         mii_tick(mii);
6048
6049         /* Check if the link has come up. */
6050         if ((mii->mii_media_status & IFM_ACTIVE) &&
6051             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6052                 sc->bce_link++;
6053                 /* Now that link is up, handle any outstanding TX traffic. */
6054                 if (!ifq_is_empty(&ifp->if_snd))
6055                         if_devstart(ifp);
6056         }
6057 }
6058
6059
6060 static void
6061 bce_tick(void *xsc)
6062 {
6063         struct bce_softc *sc = xsc;
6064         struct ifnet *ifp = &sc->arpcom.ac_if;
6065
6066         lwkt_serialize_enter(ifp->if_serializer);
6067         bce_tick_serialized(sc);
6068         lwkt_serialize_exit(ifp->if_serializer);
6069 }
6070
6071
6072 #ifdef BCE_DEBUG
6073 /****************************************************************************/
6074 /* Allows the driver state to be dumped through the sysctl interface.       */
6075 /*                                                                          */
6076 /* Returns:                                                                 */
6077 /*   0 for success, positive value for failure.                             */
6078 /****************************************************************************/
6079 static int
6080 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
6081 {
6082         int error;
6083         int result;
6084         struct bce_softc *sc;
6085
6086         result = -1;
6087         error = sysctl_handle_int(oidp, &result, 0, req);
6088
6089         if (error || !req->newptr)
6090                 return (error);
6091
6092         if (result == 1) {
6093                 sc = (struct bce_softc *)arg1;
6094                 bce_dump_driver_state(sc);
6095         }
6096
6097         return error;
6098 }
6099
6100
6101 /****************************************************************************/
6102 /* Allows the hardware state to be dumped through the sysctl interface.     */
6103 /*                                                                          */
6104 /* Returns:                                                                 */
6105 /*   0 for success, positive value for failure.                             */
6106 /****************************************************************************/
6107 static int
6108 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
6109 {
6110         int error;
6111         int result;
6112         struct bce_softc *sc;
6113
6114         result = -1;
6115         error = sysctl_handle_int(oidp, &result, 0, req);
6116
6117         if (error || !req->newptr)
6118                 return (error);
6119
6120         if (result == 1) {
6121                 sc = (struct bce_softc *)arg1;
6122                 bce_dump_hw_state(sc);
6123         }
6124
6125         return error;
6126 }
6127
6128
6129 /****************************************************************************/
6130 /* Provides a sysctl interface to allows dumping the RX chain.              */
6131 /*                                                                          */
6132 /* Returns:                                                                 */
6133 /*   0 for success, positive value for failure.                             */
6134 /****************************************************************************/
6135 static int
6136 bce_sysctl_dump_rx_chain(SYSCTL_HANDLER_ARGS)
6137 {
6138         int error;
6139         int result;
6140         struct bce_softc *sc;
6141
6142         result = -1;
6143         error = sysctl_handle_int(oidp, &result, 0, req);
6144
6145         if (error || !req->newptr)
6146                 return (error);
6147
6148         if (result == 1) {
6149                 sc = (struct bce_softc *)arg1;
6150                 bce_dump_rx_chain(sc, 0, USABLE_RX_BD(sc));
6151         }
6152
6153         return error;
6154 }
6155
6156
6157 /****************************************************************************/
6158 /* Provides a sysctl interface to allows dumping the TX chain.              */
6159 /*                                                                          */
6160 /* Returns:                                                                 */
6161 /*   0 for success, positive value for failure.                             */
6162 /****************************************************************************/
6163 static int
6164 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
6165 {
6166         int error;
6167         int result;
6168         struct bce_softc *sc;
6169
6170         result = -1;
6171         error = sysctl_handle_int(oidp, &result, 0, req);
6172
6173         if (error || !req->newptr)
6174                 return (error);
6175
6176         if (result == 1) {
6177                 sc = (struct bce_softc *)arg1;
6178                 bce_dump_tx_chain(sc, 0, USABLE_TX_BD(sc));
6179         }
6180
6181         return error;
6182 }
6183
6184
6185 /****************************************************************************/
6186 /* Provides a sysctl interface to allow reading arbitrary registers in the  */
6187 /* device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                            */
6188 /*                                                                          */
6189 /* Returns:                                                                 */
6190 /*   0 for success, positive value for failure.                             */
6191 /****************************************************************************/
6192 static int
6193 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
6194 {
6195         struct bce_softc *sc;
6196         int error;
6197         uint32_t val, result;
6198
6199         result = -1;
6200         error = sysctl_handle_int(oidp, &result, 0, req);
6201         if (error || (req->newptr == NULL))
6202                 return (error);
6203
6204         /* Make sure the register is accessible. */
6205         if (result < 0x8000) {
6206                 sc = (struct bce_softc *)arg1;
6207                 val = REG_RD(sc, result);
6208                 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
6209                           result, val);
6210         } else if (result < 0x0280000) {
6211                 sc = (struct bce_softc *)arg1;
6212                 val = REG_RD_IND(sc, result);
6213                 if_printf(&sc->arpcom.ac_if, "reg 0x%08X = 0x%08X\n",
6214                           result, val);
6215         }
6216         return (error);
6217 }
6218
6219
6220 /****************************************************************************/
6221 /* Provides a sysctl interface to allow reading arbitrary PHY registers in  */
6222 /* the device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                        */
6223 /*                                                                          */
6224 /* Returns:                                                                 */
6225 /*   0 for success, positive value for failure.                             */
6226 /****************************************************************************/
6227 static int
6228 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)
6229 {
6230         struct bce_softc *sc;
6231         device_t dev;
6232         int error, result;
6233         uint16_t val;
6234
6235         result = -1;
6236         error = sysctl_handle_int(oidp, &result, 0, req);
6237         if (error || (req->newptr == NULL))
6238                 return (error);
6239
6240         /* Make sure the register is accessible. */
6241         if (result < 0x20) {
6242                 sc = (struct bce_softc *)arg1;
6243                 dev = sc->bce_dev;
6244                 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
6245                 if_printf(&sc->arpcom.ac_if,
6246                           "phy 0x%02X = 0x%04X\n", result, val);
6247         }
6248         return (error);
6249 }
6250
6251
6252 /****************************************************************************/
6253 /* Provides a sysctl interface to forcing the driver to dump state and      */
6254 /* enter the debugger.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                */
6255 /*                                                                          */
6256 /* Returns:                                                                 */
6257 /*   0 for success, positive value for failure.                             */
6258 /****************************************************************************/
6259 static int
6260 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
6261 {
6262         int error;
6263         int result;
6264         struct bce_softc *sc;
6265
6266         result = -1;
6267         error = sysctl_handle_int(oidp, &result, 0, req);
6268
6269         if (error || !req->newptr)
6270                 return (error);
6271
6272         if (result == 1) {
6273                 sc = (struct bce_softc *)arg1;
6274                 bce_breakpoint(sc);
6275         }
6276
6277         return error;
6278 }
6279 #endif
6280
6281
6282 /****************************************************************************/
6283 /* Adds any sysctl parameters for tuning or debugging purposes.             */
6284 /*                                                                          */
6285 /* Returns:                                                                 */
6286 /*   0 for success, positive value for failure.                             */
6287 /****************************************************************************/
6288 static void
6289 bce_add_sysctls(struct bce_softc *sc)
6290 {
6291         struct sysctl_ctx_list *ctx;
6292         struct sysctl_oid_list *children;
6293
6294         sysctl_ctx_init(&sc->bce_sysctl_ctx);
6295         sc->bce_sysctl_tree = SYSCTL_ADD_NODE(&sc->bce_sysctl_ctx,
6296                                               SYSCTL_STATIC_CHILDREN(_hw),
6297                                               OID_AUTO,
6298                                               device_get_nameunit(sc->bce_dev),
6299                                               CTLFLAG_RD, 0, "");
6300         if (sc->bce_sysctl_tree == NULL) {
6301                 device_printf(sc->bce_dev, "can't add sysctl node\n");
6302                 return;
6303         }
6304
6305         ctx = &sc->bce_sysctl_ctx;
6306         children = SYSCTL_CHILDREN(sc->bce_sysctl_tree);
6307
6308         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds_int",
6309                         CTLTYPE_INT | CTLFLAG_RW,
6310                         sc, 0, bce_sysctl_tx_bds_int, "I",
6311                         "Send max coalesced BD count during interrupt");
6312         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_bds",
6313                         CTLTYPE_INT | CTLFLAG_RW,
6314                         sc, 0, bce_sysctl_tx_bds, "I",
6315                         "Send max coalesced BD count");
6316         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks_int",
6317                         CTLTYPE_INT | CTLFLAG_RW,
6318                         sc, 0, bce_sysctl_tx_ticks_int, "I",
6319                         "Send coalescing ticks during interrupt");
6320         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_ticks",
6321                         CTLTYPE_INT | CTLFLAG_RW,
6322                         sc, 0, bce_sysctl_tx_ticks, "I",
6323                         "Send coalescing ticks");
6324
6325         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds_int",
6326                         CTLTYPE_INT | CTLFLAG_RW,
6327                         sc, 0, bce_sysctl_rx_bds_int, "I",
6328                         "Receive max coalesced BD count during interrupt");
6329         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_bds",
6330                         CTLTYPE_INT | CTLFLAG_RW,
6331                         sc, 0, bce_sysctl_rx_bds, "I",
6332                         "Receive max coalesced BD count");
6333         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks_int",
6334                         CTLTYPE_INT | CTLFLAG_RW,
6335                         sc, 0, bce_sysctl_rx_ticks_int, "I",
6336                         "Receive coalescing ticks during interrupt");
6337         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_ticks",
6338                         CTLTYPE_INT | CTLFLAG_RW,
6339                         sc, 0, bce_sysctl_rx_ticks, "I",
6340                         "Receive coalescing ticks");
6341
6342         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_pages",
6343                 CTLFLAG_RD, &sc->rx_pages, 0, "# of RX pages");
6344         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_pages",
6345                 CTLFLAG_RD, &sc->tx_pages, 0, "# of TX pages");
6346
6347 #ifdef BCE_DEBUG
6348         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6349                 "rx_low_watermark",
6350                 CTLFLAG_RD, &sc->rx_low_watermark,
6351                 0, "Lowest level of free rx_bd's");
6352
6353         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6354                 "rx_empty_count",
6355                 CTLFLAG_RD, &sc->rx_empty_count,
6356                 0, "Number of times the RX chain was empty");
6357
6358         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6359                 "tx_hi_watermark",
6360                 CTLFLAG_RD, &sc->tx_hi_watermark,
6361                 0, "Highest level of used tx_bd's");
6362
6363         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6364                 "tx_full_count",
6365                 CTLFLAG_RD, &sc->tx_full_count,
6366                 0, "Number of times the TX chain was full");
6367
6368         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6369                 "l2fhdr_status_errors",
6370                 CTLFLAG_RD, &sc->l2fhdr_status_errors,
6371                 0, "l2_fhdr status errors");
6372
6373         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6374                 "unexpected_attentions",
6375                 CTLFLAG_RD, &sc->unexpected_attentions,
6376                 0, "unexpected attentions");
6377
6378         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6379                 "lost_status_block_updates",
6380                 CTLFLAG_RD, &sc->lost_status_block_updates,
6381                 0, "lost status block updates");
6382
6383         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6384                 "mbuf_alloc_failed",
6385                 CTLFLAG_RD, &sc->mbuf_alloc_failed,
6386                 0, "mbuf cluster allocation failures");
6387 #endif
6388
6389         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6390                 "stat_IfHCInOctets",
6391                 CTLFLAG_RD, &sc->stat_IfHCInOctets,
6392                 "Bytes received");
6393
6394         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6395                 "stat_IfHCInBadOctets",
6396                 CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
6397                 "Bad bytes received");
6398
6399         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6400                 "stat_IfHCOutOctets",
6401                 CTLFLAG_RD, &sc->stat_IfHCOutOctets,
6402                 "Bytes sent");
6403
6404         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6405                 "stat_IfHCOutBadOctets",
6406                 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
6407                 "Bad bytes sent");
6408
6409         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6410                 "stat_IfHCInUcastPkts",
6411                 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
6412                 "Unicast packets received");
6413
6414         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6415                 "stat_IfHCInMulticastPkts",
6416                 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
6417                 "Multicast packets received");
6418
6419         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6420                 "stat_IfHCInBroadcastPkts",
6421                 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
6422                 "Broadcast packets received");
6423
6424         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6425                 "stat_IfHCOutUcastPkts",
6426                 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
6427                 "Unicast packets sent");
6428
6429         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6430                 "stat_IfHCOutMulticastPkts",
6431                 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
6432                 "Multicast packets sent");
6433
6434         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6435                 "stat_IfHCOutBroadcastPkts",
6436                 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
6437                 "Broadcast packets sent");
6438
6439         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6440                 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
6441                 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
6442                 0, "Internal MAC transmit errors");
6443
6444         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6445                 "stat_Dot3StatsCarrierSenseErrors",
6446                 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
6447                 0, "Carrier sense errors");
6448
6449         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6450                 "stat_Dot3StatsFCSErrors",
6451                 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
6452                 0, "Frame check sequence errors");
6453
6454         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6455                 "stat_Dot3StatsAlignmentErrors",
6456                 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
6457                 0, "Alignment errors");
6458
6459         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6460                 "stat_Dot3StatsSingleCollisionFrames",
6461                 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
6462                 0, "Single Collision Frames");
6463
6464         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6465                 "stat_Dot3StatsMultipleCollisionFrames",
6466                 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
6467                 0, "Multiple Collision Frames");
6468
6469         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6470                 "stat_Dot3StatsDeferredTransmissions",
6471                 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
6472                 0, "Deferred Transmissions");
6473
6474         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6475                 "stat_Dot3StatsExcessiveCollisions",
6476                 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
6477                 0, "Excessive Collisions");
6478
6479         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6480                 "stat_Dot3StatsLateCollisions",
6481                 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
6482                 0, "Late Collisions");
6483
6484         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6485                 "stat_EtherStatsCollisions",
6486                 CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
6487                 0, "Collisions");
6488
6489         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6490                 "stat_EtherStatsFragments",
6491                 CTLFLAG_RD, &sc->stat_EtherStatsFragments,
6492                 0, "Fragments");
6493
6494         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6495                 "stat_EtherStatsJabbers",
6496                 CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
6497                 0, "Jabbers");
6498
6499         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6500                 "stat_EtherStatsUndersizePkts",
6501                 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
6502                 0, "Undersize packets");
6503
6504         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6505                 "stat_EtherStatsOverrsizePkts",
6506                 CTLFLAG_RD, &sc->stat_EtherStatsOverrsizePkts,
6507                 0, "stat_EtherStatsOverrsizePkts");
6508
6509         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6510                 "stat_EtherStatsPktsRx64Octets",
6511                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
6512                 0, "Bytes received in 64 byte packets");
6513
6514         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6515                 "stat_EtherStatsPktsRx65Octetsto127Octets",
6516                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
6517                 0, "Bytes received in 65 to 127 byte packets");
6518
6519         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6520                 "stat_EtherStatsPktsRx128Octetsto255Octets",
6521                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
6522                 0, "Bytes received in 128 to 255 byte packets");
6523
6524         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6525                 "stat_EtherStatsPktsRx256Octetsto511Octets",
6526                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
6527                 0, "Bytes received in 256 to 511 byte packets");
6528
6529         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6530                 "stat_EtherStatsPktsRx512Octetsto1023Octets",
6531                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
6532                 0, "Bytes received in 512 to 1023 byte packets");
6533
6534         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6535                 "stat_EtherStatsPktsRx1024Octetsto1522Octets",
6536                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
6537                 0, "Bytes received in 1024 t0 1522 byte packets");
6538
6539         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6540                 "stat_EtherStatsPktsRx1523Octetsto9022Octets",
6541                 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
6542                 0, "Bytes received in 1523 to 9022 byte packets");
6543
6544         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6545                 "stat_EtherStatsPktsTx64Octets",
6546                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
6547                 0, "Bytes sent in 64 byte packets");
6548
6549         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6550                 "stat_EtherStatsPktsTx65Octetsto127Octets",
6551                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
6552                 0, "Bytes sent in 65 to 127 byte packets");
6553
6554         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6555                 "stat_EtherStatsPktsTx128Octetsto255Octets",
6556                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
6557                 0, "Bytes sent in 128 to 255 byte packets");
6558
6559         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6560                 "stat_EtherStatsPktsTx256Octetsto511Octets",
6561                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
6562                 0, "Bytes sent in 256 to 511 byte packets");
6563
6564         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6565                 "stat_EtherStatsPktsTx512Octetsto1023Octets",
6566                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
6567                 0, "Bytes sent in 512 to 1023 byte packets");
6568
6569         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6570                 "stat_EtherStatsPktsTx1024Octetsto1522Octets",
6571                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
6572                 0, "Bytes sent in 1024 to 1522 byte packets");
6573
6574         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6575                 "stat_EtherStatsPktsTx1523Octetsto9022Octets",
6576                 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
6577                 0, "Bytes sent in 1523 to 9022 byte packets");
6578
6579         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6580                 "stat_XonPauseFramesReceived",
6581                 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
6582                 0, "XON pause frames receved");
6583
6584         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6585                 "stat_XoffPauseFramesReceived",
6586                 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
6587                 0, "XOFF pause frames received");
6588
6589         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6590                 "stat_OutXonSent",
6591                 CTLFLAG_RD, &sc->stat_OutXonSent,
6592                 0, "XON pause frames sent");
6593
6594         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6595                 "stat_OutXoffSent",
6596                 CTLFLAG_RD, &sc->stat_OutXoffSent,
6597                 0, "XOFF pause frames sent");
6598
6599         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6600                 "stat_FlowControlDone",
6601                 CTLFLAG_RD, &sc->stat_FlowControlDone,
6602                 0, "Flow control done");
6603
6604         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6605                 "stat_MacControlFramesReceived",
6606                 CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
6607                 0, "MAC control frames received");
6608
6609         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6610                 "stat_XoffStateEntered",
6611                 CTLFLAG_RD, &sc->stat_XoffStateEntered,
6612                 0, "XOFF state entered");
6613
6614         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6615                 "stat_IfInFramesL2FilterDiscards",
6616                 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
6617                 0, "Received L2 packets discarded");
6618
6619         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6620                 "stat_IfInRuleCheckerDiscards",
6621                 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
6622                 0, "Received packets discarded by rule");
6623
6624         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6625                 "stat_IfInFTQDiscards",
6626                 CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
6627                 0, "Received packet FTQ discards");
6628
6629         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6630                 "stat_IfInMBUFDiscards",
6631                 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
6632                 0, "Received packets discarded due to lack of controller buffer memory");
6633
6634         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6635                 "stat_IfInRuleCheckerP4Hit",
6636                 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
6637                 0, "Received packets rule checker hits");
6638
6639         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6640                 "stat_CatchupInRuleCheckerDiscards",
6641                 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
6642                 0, "Received packets discarded in Catchup path");
6643
6644         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6645                 "stat_CatchupInFTQDiscards",
6646                 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
6647                 0, "Received packets discarded in FTQ in Catchup path");
6648
6649         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6650                 "stat_CatchupInMBUFDiscards",
6651                 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
6652                 0, "Received packets discarded in controller buffer memory in Catchup path");
6653
6654         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6655                 "stat_CatchupInRuleCheckerP4Hit",
6656                 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
6657                 0, "Received packets rule checker hits in Catchup path");
6658
6659         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6660                 "com_no_buffers",
6661                 CTLFLAG_RD, &sc->com_no_buffers,
6662                 0, "Valid packets received but no RX buffers available");
6663
6664 #ifdef BCE_DEBUG
6665         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6666                 "driver_state", CTLTYPE_INT | CTLFLAG_RW,
6667                 (void *)sc, 0,
6668                 bce_sysctl_driver_state, "I", "Drive state information");
6669
6670         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6671                 "hw_state", CTLTYPE_INT | CTLFLAG_RW,
6672                 (void *)sc, 0,
6673                 bce_sysctl_hw_state, "I", "Hardware state information");
6674
6675         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6676                 "dump_rx_chain", CTLTYPE_INT | CTLFLAG_RW,
6677                 (void *)sc, 0,
6678                 bce_sysctl_dump_rx_chain, "I", "Dump rx_bd chain");
6679
6680         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6681                 "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW,
6682                 (void *)sc, 0,
6683                 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
6684
6685         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6686                 "breakpoint", CTLTYPE_INT | CTLFLAG_RW,
6687                 (void *)sc, 0,
6688                 bce_sysctl_breakpoint, "I", "Driver breakpoint");
6689
6690         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6691                 "reg_read", CTLTYPE_INT | CTLFLAG_RW,
6692                 (void *)sc, 0,
6693                 bce_sysctl_reg_read, "I", "Register read");
6694
6695         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
6696                 "phy_read", CTLTYPE_INT | CTLFLAG_RW,
6697                 (void *)sc, 0,
6698                 bce_sysctl_phy_read, "I", "PHY register read");
6699
6700 #endif
6701
6702 }
6703
6704
6705 /****************************************************************************/
6706 /* BCE Debug Routines                                                       */
6707 /****************************************************************************/
6708 #ifdef BCE_DEBUG
6709
6710 /****************************************************************************/
6711 /* Freezes the controller to allow for a cohesive state dump.               */
6712 /*                                                                          */
6713 /* Returns:                                                                 */
6714 /*   Nothing.                                                               */
6715 /****************************************************************************/
6716 static void
6717 bce_freeze_controller(struct bce_softc *sc)
6718 {
6719         uint32_t val;
6720
6721         val = REG_RD(sc, BCE_MISC_COMMAND);
6722         val |= BCE_MISC_COMMAND_DISABLE_ALL;
6723         REG_WR(sc, BCE_MISC_COMMAND, val);
6724 }
6725
6726
6727 /****************************************************************************/
6728 /* Unfreezes the controller after a freeze operation.  This may not always  */
6729 /* work and the controller will require a reset!                            */
6730 /*                                                                          */
6731 /* Returns:                                                                 */
6732 /*   Nothing.                                                               */
6733 /****************************************************************************/
6734 static void
6735 bce_unfreeze_controller(struct bce_softc *sc)
6736 {
6737         uint32_t val;
6738
6739         val = REG_RD(sc, BCE_MISC_COMMAND);
6740         val |= BCE_MISC_COMMAND_ENABLE_ALL;
6741         REG_WR(sc, BCE_MISC_COMMAND, val);
6742 }
6743
6744
6745 /****************************************************************************/
6746 /* Prints out information about an mbuf.                                    */
6747 /*                                                                          */
6748 /* Returns:                                                                 */
6749 /*   Nothing.                                                               */
6750 /****************************************************************************/
6751 static void
6752 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
6753 {
6754         struct ifnet *ifp = &sc->arpcom.ac_if;
6755         uint32_t val_hi, val_lo;
6756         struct mbuf *mp = m;
6757
6758         if (m == NULL) {
6759                 /* Index out of range. */
6760                 if_printf(ifp, "mbuf: null pointer\n");
6761                 return;
6762         }
6763
6764         while (mp) {
6765                 val_hi = BCE_ADDR_HI(mp);
6766                 val_lo = BCE_ADDR_LO(mp);
6767                 if_printf(ifp, "mbuf: vaddr = 0x%08X:%08X, m_len = %d, "
6768                           "m_flags = ( ", val_hi, val_lo, mp->m_len);
6769
6770                 if (mp->m_flags & M_EXT)
6771                         kprintf("M_EXT ");
6772                 if (mp->m_flags & M_PKTHDR)
6773                         kprintf("M_PKTHDR ");
6774                 if (mp->m_flags & M_EOR)
6775                         kprintf("M_EOR ");
6776 #ifdef M_RDONLY
6777                 if (mp->m_flags & M_RDONLY)
6778                         kprintf("M_RDONLY ");
6779 #endif
6780
6781                 val_hi = BCE_ADDR_HI(mp->m_data);
6782                 val_lo = BCE_ADDR_LO(mp->m_data);
6783                 kprintf(") m_data = 0x%08X:%08X\n", val_hi, val_lo);
6784
6785                 if (mp->m_flags & M_PKTHDR) {
6786                         if_printf(ifp, "- m_pkthdr: flags = ( ");
6787                         if (mp->m_flags & M_BCAST)
6788                                 kprintf("M_BCAST ");
6789                         if (mp->m_flags & M_MCAST)
6790                                 kprintf("M_MCAST ");
6791                         if (mp->m_flags & M_FRAG)
6792                                 kprintf("M_FRAG ");
6793                         if (mp->m_flags & M_FIRSTFRAG)
6794                                 kprintf("M_FIRSTFRAG ");
6795                         if (mp->m_flags & M_LASTFRAG)
6796                                 kprintf("M_LASTFRAG ");
6797 #ifdef M_VLANTAG
6798                         if (mp->m_flags & M_VLANTAG)
6799                                 kprintf("M_VLANTAG ");
6800 #endif
6801 #ifdef M_PROMISC
6802                         if (mp->m_flags & M_PROMISC)
6803                                 kprintf("M_PROMISC ");
6804 #endif
6805                         kprintf(") csum_flags = ( ");
6806                         if (mp->m_pkthdr.csum_flags & CSUM_IP)
6807                                 kprintf("CSUM_IP ");
6808                         if (mp->m_pkthdr.csum_flags & CSUM_TCP)
6809                                 kprintf("CSUM_TCP ");
6810                         if (mp->m_pkthdr.csum_flags & CSUM_UDP)
6811                                 kprintf("CSUM_UDP ");
6812                         if (mp->m_pkthdr.csum_flags & CSUM_IP_FRAGS)
6813                                 kprintf("CSUM_IP_FRAGS ");
6814                         if (mp->m_pkthdr.csum_flags & CSUM_FRAGMENT)
6815                                 kprintf("CSUM_FRAGMENT ");
6816 #ifdef CSUM_TSO
6817                         if (mp->m_pkthdr.csum_flags & CSUM_TSO)
6818                                 kprintf("CSUM_TSO ");
6819 #endif
6820                         if (mp->m_pkthdr.csum_flags & CSUM_IP_CHECKED)
6821                                 kprintf("CSUM_IP_CHECKED ");
6822                         if (mp->m_pkthdr.csum_flags & CSUM_IP_VALID)
6823                                 kprintf("CSUM_IP_VALID ");
6824                         if (mp->m_pkthdr.csum_flags & CSUM_DATA_VALID)
6825                                 kprintf("CSUM_DATA_VALID ");
6826                         kprintf(")\n");
6827                 }
6828
6829                 if (mp->m_flags & M_EXT) {
6830                         val_hi = BCE_ADDR_HI(mp->m_ext.ext_buf);
6831                         val_lo = BCE_ADDR_LO(mp->m_ext.ext_buf);
6832                         if_printf(ifp, "- m_ext: vaddr = 0x%08X:%08X, "
6833                                   "ext_size = %d\n",
6834                                   val_hi, val_lo, mp->m_ext.ext_size);
6835                 }
6836                 mp = mp->m_next;
6837         }
6838 }
6839
6840
6841 /****************************************************************************/
6842 /* Prints out the mbufs in the TX mbuf chain.                               */
6843 /*                                                                          */
6844 /* Returns:                                                                 */
6845 /*   Nothing.                                                               */
6846 /****************************************************************************/
6847 static void
6848 bce_dump_tx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6849 {
6850         struct ifnet *ifp = &sc->arpcom.ac_if;
6851         int i;
6852
6853         if_printf(ifp,
6854         "----------------------------"
6855         "  tx mbuf data  "
6856         "----------------------------\n");
6857
6858         for (i = 0; i < count; i++) {
6859                 if_printf(ifp, "txmbuf[%d]\n", chain_prod);
6860                 bce_dump_mbuf(sc, sc->tx_mbuf_ptr[chain_prod]);
6861                 chain_prod = TX_CHAIN_IDX(sc, NEXT_TX_BD(chain_prod));
6862         }
6863
6864         if_printf(ifp,
6865         "----------------------------"
6866         "----------------"
6867         "----------------------------\n");
6868 }
6869
6870
6871 /****************************************************************************/
6872 /* Prints out the mbufs in the RX mbuf chain.                               */
6873 /*                                                                          */
6874 /* Returns:                                                                 */
6875 /*   Nothing.                                                               */
6876 /****************************************************************************/
6877 static void
6878 bce_dump_rx_mbuf_chain(struct bce_softc *sc, int chain_prod, int count)
6879 {
6880         struct ifnet *ifp = &sc->arpcom.ac_if;
6881         int i;
6882
6883         if_printf(ifp,
6884         "----------------------------"
6885         "  rx mbuf data  "
6886         "----------------------------\n");
6887
6888         for (i = 0; i < count; i++) {
6889                 if_printf(ifp, "rxmbuf[0x%04X]\n", chain_prod);
6890                 bce_dump_mbuf(sc, sc->rx_mbuf_ptr[chain_prod]);
6891                 chain_prod = RX_CHAIN_IDX(sc, NEXT_RX_BD(chain_prod));
6892         }
6893
6894         if_printf(ifp,
6895         "----------------------------"
6896         "----------------"
6897         "----------------------------\n");
6898 }
6899
6900
6901 /****************************************************************************/
6902 /* Prints out a tx_bd structure.                                            */
6903 /*                                                                          */
6904 /* Returns:                                                                 */
6905 /*   Nothing.                                                               */
6906 /****************************************************************************/
6907 static void
6908 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
6909 {
6910         struct ifnet *ifp = &sc->arpcom.ac_if;
6911
6912         if (idx > MAX_TX_BD(sc)) {
6913                 /* Index out of range. */
6914                 if_printf(ifp, "tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
6915         } else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) {
6916                 /* TX Chain page pointer. */
6917                 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6918                           "chain page pointer\n",
6919                           idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo);
6920         } else {
6921                 /* Normal tx_bd entry. */
6922                 if_printf(ifp, "tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6923                           "nbytes = 0x%08X, "
6924                           "vlan tag= 0x%04X, flags = 0x%04X (",
6925                           idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo,
6926                           txbd->tx_bd_mss_nbytes,
6927                           txbd->tx_bd_vlan_tag, txbd->tx_bd_flags);
6928
6929                 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT)
6930                         kprintf(" CONN_FAULT");
6931
6932                 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM)
6933                         kprintf(" TCP_UDP_CKSUM");
6934
6935                 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM)
6936                         kprintf(" IP_CKSUM");
6937
6938                 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG)
6939                         kprintf("  VLAN");
6940
6941                 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW)
6942                         kprintf(" COAL_NOW");
6943
6944                 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC)
6945                         kprintf(" DONT_GEN_CRC");
6946
6947                 if (txbd->tx_bd_flags & TX_BD_FLAGS_START)
6948                         kprintf(" START");
6949
6950                 if (txbd->tx_bd_flags & TX_BD_FLAGS_END)
6951                         kprintf(" END");
6952
6953                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO)
6954                         kprintf(" LSO");
6955
6956                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD)
6957                         kprintf(" OPTION_WORD");
6958
6959                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS)
6960                         kprintf(" FLAGS");
6961
6962                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP)
6963                         kprintf(" SNAP");
6964
6965                 kprintf(" )\n");
6966         }
6967 }
6968
6969
6970 /****************************************************************************/
6971 /* Prints out a rx_bd structure.                                            */
6972 /*                                                                          */
6973 /* Returns:                                                                 */
6974 /*   Nothing.                                                               */
6975 /****************************************************************************/
6976 static void
6977 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
6978 {
6979         struct ifnet *ifp = &sc->arpcom.ac_if;
6980
6981         if (idx > MAX_RX_BD(sc)) {
6982                 /* Index out of range. */
6983                 if_printf(ifp, "rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
6984         } else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE) {
6985                 /* TX Chain page pointer. */
6986                 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6987                           "chain page pointer\n",
6988                           idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo);
6989         } else {
6990                 /* Normal tx_bd entry. */
6991                 if_printf(ifp, "rx_bd[0x%04X]: haddr = 0x%08X:%08X, "
6992                           "nbytes = 0x%08X, flags = 0x%08X\n",
6993                           idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo,
6994                           rxbd->rx_bd_len, rxbd->rx_bd_flags);
6995         }
6996 }
6997
6998
6999 /****************************************************************************/
7000 /* Prints out a l2_fhdr structure.                                          */
7001 /*                                                                          */
7002 /* Returns:                                                                 */
7003 /*   Nothing.                                                               */
7004 /****************************************************************************/
7005 static void
7006 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
7007 {
7008         if_printf(&sc->arpcom.ac_if, "l2_fhdr[0x%04X]: status = 0x%08X, "
7009                   "pkt_len = 0x%04X, vlan = 0x%04x, "
7010                   "ip_xsum = 0x%04X, tcp_udp_xsum = 0x%04X\n",
7011                   idx, l2fhdr->l2_fhdr_status,
7012                   l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
7013                   l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
7014 }
7015
7016
7017 /****************************************************************************/
7018 /* Prints out the tx chain.                                                 */
7019 /*                                                                          */
7020 /* Returns:                                                                 */
7021 /*   Nothing.                                                               */
7022 /****************************************************************************/
7023 static void
7024 bce_dump_tx_chain(struct bce_softc *sc, int tx_prod, int count)
7025 {
7026         struct ifnet *ifp = &sc->arpcom.ac_if;
7027         int i;
7028
7029         /* First some info about the tx_bd chain structure. */
7030         if_printf(ifp,
7031         "----------------------------"
7032         "  tx_bd  chain  "
7033         "----------------------------\n");
7034
7035         if_printf(ifp, "page size      = 0x%08X, "
7036                   "tx chain pages        = 0x%08X\n",
7037                   (uint32_t)BCM_PAGE_SIZE, (uint32_t)sc->tx_pages);
7038
7039         if_printf(ifp, "tx_bd per page = 0x%08X, "
7040                   "usable tx_bd per page = 0x%08X\n",
7041                   (uint32_t)TOTAL_TX_BD_PER_PAGE,
7042                   (uint32_t)USABLE_TX_BD_PER_PAGE);
7043
7044         if_printf(ifp, "total tx_bd    = 0x%08X\n", (uint32_t)TOTAL_TX_BD(sc));
7045
7046         if_printf(ifp,
7047         "----------------------------"
7048         "  tx_bd data    "
7049         "----------------------------\n");
7050
7051         /* Now print out the tx_bd's themselves. */
7052         for (i = 0; i < count; i++) {
7053                 struct tx_bd *txbd;
7054
7055                 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
7056                 bce_dump_txbd(sc, tx_prod, txbd);
7057                 tx_prod = TX_CHAIN_IDX(sc, NEXT_TX_BD(tx_prod));
7058         }
7059
7060         if_printf(ifp,
7061         "----------------------------"
7062         "----------------"
7063         "----------------------------\n");
7064 }
7065
7066
7067 /****************************************************************************/
7068 /* Prints out the rx chain.                                                 */
7069 /*                                                                          */
7070 /* Returns:                                                                 */
7071 /*   Nothing.                                                               */
7072 /****************************************************************************/
7073 static void
7074 bce_dump_rx_chain(struct bce_softc *sc, int rx_prod, int count)
7075 {
7076         struct ifnet *ifp = &sc->arpcom.ac_if;
7077         int i;
7078
7079         /* First some info about the tx_bd chain structure. */
7080         if_printf(ifp,
7081         "----------------------------"
7082         "  rx_bd  chain  "
7083         "----------------------------\n");
7084
7085         if_printf(ifp, "page size      = 0x%08X, "
7086                   "rx chain pages        = 0x%08X\n",
7087                   (uint32_t)BCM_PAGE_SIZE, (uint32_t)sc->rx_pages);
7088
7089         if_printf(ifp, "rx_bd per page = 0x%08X, "
7090                   "usable rx_bd per page = 0x%08X\n",
7091                   (uint32_t)TOTAL_RX_BD_PER_PAGE,
7092                   (uint32_t)USABLE_RX_BD_PER_PAGE);
7093
7094         if_printf(ifp, "total rx_bd    = 0x%08X\n", (uint32_t)TOTAL_RX_BD(sc));
7095
7096         if_printf(ifp,
7097         "----------------------------"
7098         "   rx_bd data   "
7099         "----------------------------\n");
7100
7101         /* Now print out the rx_bd's themselves. */
7102         for (i = 0; i < count; i++) {
7103                 struct rx_bd *rxbd;
7104
7105                 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
7106                 bce_dump_rxbd(sc, rx_prod, rxbd);
7107                 rx_prod = RX_CHAIN_IDX(sc, NEXT_RX_BD(rx_prod));
7108         }
7109
7110         if_printf(ifp,
7111         "----------------------------"
7112         "----------------"
7113         "----------------------------\n");
7114 }
7115
7116
7117 /****************************************************************************/
7118 /* Prints out the status block from host memory.                            */
7119 /*                                                                          */
7120 /* Returns:                                                                 */
7121 /*   Nothing.                                                               */
7122 /****************************************************************************/
7123 static void
7124 bce_dump_status_block(struct bce_softc *sc)
7125 {
7126         struct status_block *sblk = sc->status_block;
7127         struct ifnet *ifp = &sc->arpcom.ac_if;
7128
7129         if_printf(ifp,
7130         "----------------------------"
7131         "  Status Block  "
7132         "----------------------------\n");
7133
7134         if_printf(ifp, "    0x%08X - attn_bits\n", sblk->status_attn_bits);
7135
7136         if_printf(ifp, "    0x%08X - attn_bits_ack\n",
7137                   sblk->status_attn_bits_ack);
7138
7139         if_printf(ifp, "0x%04X(0x%04X) - rx_cons0\n",
7140             sblk->status_rx_quick_consumer_index0,
7141             (uint16_t)RX_CHAIN_IDX(sc, sblk->status_rx_quick_consumer_index0));
7142
7143         if_printf(ifp, "0x%04X(0x%04X) - tx_cons0\n",
7144             sblk->status_tx_quick_consumer_index0,
7145             (uint16_t)TX_CHAIN_IDX(sc, sblk->status_tx_quick_consumer_index0));
7146
7147         if_printf(ifp, "        0x%04X - status_idx\n", sblk->status_idx);
7148
7149         /* Theses indices are not used for normal L2 drivers. */
7150         if (sblk->status_rx_quick_consumer_index1) {
7151                 if_printf(ifp, "0x%04X(0x%04X) - rx_cons1\n",
7152                 sblk->status_rx_quick_consumer_index1,
7153                 (uint16_t)RX_CHAIN_IDX(sc,
7154                     sblk->status_rx_quick_consumer_index1));
7155         }
7156
7157         if (sblk->status_tx_quick_consumer_index1) {
7158                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons1\n",
7159                 sblk->status_tx_quick_consumer_index1,
7160                 (uint16_t)TX_CHAIN_IDX(sc,
7161                     sblk->status_tx_quick_consumer_index1));
7162         }
7163
7164         if (sblk->status_rx_quick_consumer_index2) {
7165                 if_printf(ifp, "0x%04X(0x%04X)- rx_cons2\n",
7166                 sblk->status_rx_quick_consumer_index2,
7167                 (uint16_t)RX_CHAIN_IDX(sc,
7168                     sblk->status_rx_quick_consumer_index2));
7169         }
7170
7171         if (sblk->status_tx_quick_consumer_index2) {
7172                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons2\n",
7173                 sblk->status_tx_quick_consumer_index2,
7174                 (uint16_t)TX_CHAIN_IDX(sc,
7175                     sblk->status_tx_quick_consumer_index2));
7176         }
7177
7178         if (sblk->status_rx_quick_consumer_index3) {
7179                 if_printf(ifp, "0x%04X(0x%04X) - rx_cons3\n",
7180                 sblk->status_rx_quick_consumer_index3,
7181                 (uint16_t)RX_CHAIN_IDX(sc,
7182                     sblk->status_rx_quick_consumer_index3));
7183         }
7184
7185         if (sblk->status_tx_quick_consumer_index3) {
7186                 if_printf(ifp, "0x%04X(0x%04X) - tx_cons3\n",
7187                 sblk->status_tx_quick_consumer_index3,
7188                 (uint16_t)TX_CHAIN_IDX(sc,
7189                     sblk->status_tx_quick_consumer_index3));
7190         }
7191
7192         if (sblk->status_rx_quick_consumer_index4 ||
7193             sblk->status_rx_quick_consumer_index5) {
7194                 if_printf(ifp, "rx_cons4  = 0x%08X, rx_cons5      = 0x%08X\n",
7195                           sblk->status_rx_quick_consumer_index4,
7196                           sblk->status_rx_quick_consumer_index5);
7197         }
7198
7199         if (sblk->status_rx_quick_consumer_index6 ||
7200             sblk->status_rx_quick_consumer_index7) {
7201                 if_printf(ifp, "rx_cons6  = 0x%08X, rx_cons7      = 0x%08X\n",
7202                           sblk->status_rx_quick_consumer_index6,
7203                           sblk->status_rx_quick_consumer_index7);
7204         }
7205
7206         if (sblk->status_rx_quick_consumer_index8 ||
7207             sblk->status_rx_quick_consumer_index9) {
7208                 if_printf(ifp, "rx_cons8  = 0x%08X, rx_cons9      = 0x%08X\n",
7209                           sblk->status_rx_quick_consumer_index8,
7210                           sblk->status_rx_quick_consumer_index9);
7211         }
7212
7213         if (sblk->status_rx_quick_consumer_index10 ||
7214             sblk->status_rx_quick_consumer_index11) {
7215                 if_printf(ifp, "rx_cons10 = 0x%08X, rx_cons11     = 0x%08X\n",
7216                           sblk->status_rx_quick_consumer_index10,
7217                           sblk->status_rx_quick_consumer_index11);
7218         }
7219
7220         if (sblk->status_rx_quick_consumer_index12 ||
7221             sblk->status_rx_quick_consumer_index13) {
7222                 if_printf(ifp, "rx_cons12 = 0x%08X, rx_cons13     = 0x%08X\n",
7223                           sblk->status_rx_quick_consumer_index12,
7224                           sblk->status_rx_quick_consumer_index13);
7225         }
7226
7227         if (sblk->status_rx_quick_consumer_index14 ||
7228             sblk->status_rx_quick_consumer_index15) {
7229                 if_printf(ifp, "rx_cons14 = 0x%08X, rx_cons15     = 0x%08X\n",
7230                           sblk->status_rx_quick_consumer_index14,
7231                           sblk->status_rx_quick_consumer_index15);
7232         }
7233
7234         if (sblk->status_completion_producer_index ||
7235             sblk->status_cmd_consumer_index) {
7236                 if_printf(ifp, "com_prod  = 0x%08X, cmd_cons      = 0x%08X\n",
7237                           sblk->status_completion_producer_index,
7238                           sblk->status_cmd_consumer_index);
7239         }
7240
7241         if_printf(ifp,
7242         "----------------------------"
7243         "----------------"
7244         "----------------------------\n");
7245 }
7246
7247
7248 /****************************************************************************/
7249 /* Prints out the statistics block.                                         */
7250 /*                                                                          */
7251 /* Returns:                                                                 */
7252 /*   Nothing.                                                               */
7253 /****************************************************************************/
7254 static void
7255 bce_dump_stats_block(struct bce_softc *sc)
7256 {
7257         struct statistics_block *sblk = sc->stats_block;
7258         struct ifnet *ifp = &sc->arpcom.ac_if;
7259
7260         if_printf(ifp,
7261         "---------------"
7262         " Stats Block  (All Stats Not Shown Are 0) "
7263         "---------------\n");
7264
7265         if (sblk->stat_IfHCInOctets_hi || sblk->stat_IfHCInOctets_lo) {
7266                 if_printf(ifp, "0x%08X:%08X : IfHcInOctets\n",
7267                           sblk->stat_IfHCInOctets_hi,
7268                           sblk->stat_IfHCInOctets_lo);
7269         }
7270
7271         if (sblk->stat_IfHCInBadOctets_hi || sblk->stat_IfHCInBadOctets_lo) {
7272                 if_printf(ifp, "0x%08X:%08X : IfHcInBadOctets\n",
7273                           sblk->stat_IfHCInBadOctets_hi,
7274                           sblk->stat_IfHCInBadOctets_lo);
7275         }
7276
7277         if (sblk->stat_IfHCOutOctets_hi || sblk->stat_IfHCOutOctets_lo) {
7278                 if_printf(ifp, "0x%08X:%08X : IfHcOutOctets\n",
7279                           sblk->stat_IfHCOutOctets_hi,
7280                           sblk->stat_IfHCOutOctets_lo);
7281         }
7282
7283         if (sblk->stat_IfHCOutBadOctets_hi || sblk->stat_IfHCOutBadOctets_lo) {
7284                 if_printf(ifp, "0x%08X:%08X : IfHcOutBadOctets\n",
7285                           sblk->stat_IfHCOutBadOctets_hi,
7286                           sblk->stat_IfHCOutBadOctets_lo);
7287         }
7288
7289         if (sblk->stat_IfHCInUcastPkts_hi || sblk->stat_IfHCInUcastPkts_lo) {
7290                 if_printf(ifp, "0x%08X:%08X : IfHcInUcastPkts\n",
7291                           sblk->stat_IfHCInUcastPkts_hi,
7292                           sblk->stat_IfHCInUcastPkts_lo);
7293         }
7294
7295         if (sblk->stat_IfHCInBroadcastPkts_hi ||
7296             sblk->stat_IfHCInBroadcastPkts_lo) {
7297                 if_printf(ifp, "0x%08X:%08X : IfHcInBroadcastPkts\n",
7298                           sblk->stat_IfHCInBroadcastPkts_hi,
7299                           sblk->stat_IfHCInBroadcastPkts_lo);
7300         }
7301
7302         if (sblk->stat_IfHCInMulticastPkts_hi ||
7303             sblk->stat_IfHCInMulticastPkts_lo) {
7304                 if_printf(ifp, "0x%08X:%08X : IfHcInMulticastPkts\n",
7305                           sblk->stat_IfHCInMulticastPkts_hi,
7306                           sblk->stat_IfHCInMulticastPkts_lo);
7307         }
7308
7309         if (sblk->stat_IfHCOutUcastPkts_hi || sblk->stat_IfHCOutUcastPkts_lo) {
7310                 if_printf(ifp, "0x%08X:%08X : IfHcOutUcastPkts\n",
7311                           sblk->stat_IfHCOutUcastPkts_hi,
7312                           sblk->stat_IfHCOutUcastPkts_lo);
7313         }
7314
7315         if (sblk->stat_IfHCOutBroadcastPkts_hi ||
7316             sblk->stat_IfHCOutBroadcastPkts_lo) {
7317                 if_printf(ifp, "0x%08X:%08X : IfHcOutBroadcastPkts\n",
7318                           sblk->stat_IfHCOutBroadcastPkts_hi,
7319                           sblk->stat_IfHCOutBroadcastPkts_lo);
7320         }
7321
7322         if (sblk->stat_IfHCOutMulticastPkts_hi ||
7323             sblk->stat_IfHCOutMulticastPkts_lo) {
7324                 if_printf(ifp, "0x%08X:%08X : IfHcOutMulticastPkts\n",
7325                           sblk->stat_IfHCOutMulticastPkts_hi,
7326                           sblk->stat_IfHCOutMulticastPkts_lo);
7327         }
7328
7329         if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors) {
7330                 if_printf(ifp, "         0x%08X : "
7331                 "emac_tx_stat_dot3statsinternalmactransmiterrors\n",
7332                 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
7333         }
7334
7335         if (sblk->stat_Dot3StatsCarrierSenseErrors) {
7336                 if_printf(ifp, "         0x%08X : "
7337                           "Dot3StatsCarrierSenseErrors\n",
7338                           sblk->stat_Dot3StatsCarrierSenseErrors);
7339         }
7340
7341         if (sblk->stat_Dot3StatsFCSErrors) {
7342                 if_printf(ifp, "         0x%08X : Dot3StatsFCSErrors\n",
7343                           sblk->stat_Dot3StatsFCSErrors);
7344         }
7345
7346         if (sblk->stat_Dot3StatsAlignmentErrors) {
7347                 if_printf(ifp, "         0x%08X : Dot3StatsAlignmentErrors\n",
7348                           sblk->stat_Dot3StatsAlignmentErrors);
7349         }
7350
7351         if (sblk->stat_Dot3StatsSingleCollisionFrames) {
7352                 if_printf(ifp, "         0x%08X : "
7353                           "Dot3StatsSingleCollisionFrames\n",
7354                           sblk->stat_Dot3StatsSingleCollisionFrames);
7355         }
7356
7357         if (sblk->stat_Dot3StatsMultipleCollisionFrames) {
7358                 if_printf(ifp, "         0x%08X : "
7359                           "Dot3StatsMultipleCollisionFrames\n",
7360                           sblk->stat_Dot3StatsMultipleCollisionFrames);
7361         }
7362
7363         if (sblk->stat_Dot3StatsDeferredTransmissions) {
7364                 if_printf(ifp, "         0x%08X : "
7365                           "Dot3StatsDeferredTransmissions\n",
7366                           sblk->stat_Dot3StatsDeferredTransmissions);
7367         }
7368
7369         if (sblk->stat_Dot3StatsExcessiveCollisions) {
7370                 if_printf(ifp, "         0x%08X : "
7371                           "Dot3StatsExcessiveCollisions\n",
7372                           sblk->stat_Dot3StatsExcessiveCollisions);
7373         }
7374
7375         if (sblk->stat_Dot3StatsLateCollisions) {
7376                 if_printf(ifp, "         0x%08X : Dot3StatsLateCollisions\n",
7377                           sblk->stat_Dot3StatsLateCollisions);
7378         }
7379
7380         if (sblk->stat_EtherStatsCollisions) {
7381                 if_printf(ifp, "         0x%08X : EtherStatsCollisions\n",
7382                           sblk->stat_EtherStatsCollisions);
7383         }
7384
7385         if (sblk->stat_EtherStatsFragments)  {
7386                 if_printf(ifp, "         0x%08X : EtherStatsFragments\n",
7387                           sblk->stat_EtherStatsFragments);
7388         }
7389
7390         if (sblk->stat_EtherStatsJabbers) {
7391                 if_printf(ifp, "         0x%08X : EtherStatsJabbers\n",
7392                           sblk->stat_EtherStatsJabbers);
7393         }
7394
7395         if (sblk->stat_EtherStatsUndersizePkts) {
7396                 if_printf(ifp, "         0x%08X : EtherStatsUndersizePkts\n",
7397                           sblk->stat_EtherStatsUndersizePkts);
7398         }
7399
7400         if (sblk->stat_EtherStatsOverrsizePkts) {
7401                 if_printf(ifp, "         0x%08X : EtherStatsOverrsizePkts\n",
7402                           sblk->stat_EtherStatsOverrsizePkts);
7403         }
7404
7405         if (sblk->stat_EtherStatsPktsRx64Octets) {
7406                 if_printf(ifp, "         0x%08X : EtherStatsPktsRx64Octets\n",
7407                           sblk->stat_EtherStatsPktsRx64Octets);
7408         }
7409
7410         if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets) {
7411                 if_printf(ifp, "         0x%08X : "
7412                           "EtherStatsPktsRx65Octetsto127Octets\n",
7413                           sblk->stat_EtherStatsPktsRx65Octetsto127Octets);
7414         }
7415
7416         if (sblk->stat_EtherStatsPktsRx128Octetsto255Octets) {
7417                 if_printf(ifp, "         0x%08X : "
7418                           "EtherStatsPktsRx128Octetsto255Octets\n",
7419                           sblk->stat_EtherStatsPktsRx128Octetsto255Octets);
7420         }
7421
7422         if (sblk->stat_EtherStatsPktsRx256Octetsto511Octets) {
7423                 if_printf(ifp, "         0x%08X : "
7424                           "EtherStatsPktsRx256Octetsto511Octets\n",
7425                           sblk->stat_EtherStatsPktsRx256Octetsto511Octets);
7426         }
7427
7428         if (sblk->stat_EtherStatsPktsRx512Octetsto1023Octets) {
7429                 if_printf(ifp, "         0x%08X : "
7430                           "EtherStatsPktsRx512Octetsto1023Octets\n",
7431                           sblk->stat_EtherStatsPktsRx512Octetsto1023Octets);
7432         }
7433
7434         if (sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets) {
7435                 if_printf(ifp, "         0x%08X : "
7436                           "EtherStatsPktsRx1024Octetsto1522Octets\n",
7437                           sblk->stat_EtherStatsPktsRx1024Octetsto1522Octets);
7438         }
7439
7440         if (sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets) {
7441                 if_printf(ifp, "         0x%08X : "
7442                           "EtherStatsPktsRx1523Octetsto9022Octets\n",
7443                           sblk->stat_EtherStatsPktsRx1523Octetsto9022Octets);
7444         }
7445
7446         if (sblk->stat_EtherStatsPktsTx64Octets) {
7447                 if_printf(ifp, "         0x%08X : EtherStatsPktsTx64Octets\n",
7448                           sblk->stat_EtherStatsPktsTx64Octets);
7449         }
7450
7451         if (sblk->stat_EtherStatsPktsTx65Octetsto127Octets) {
7452                 if_printf(ifp, "         0x%08X : "
7453                           "EtherStatsPktsTx65Octetsto127Octets\n",
7454                           sblk->stat_EtherStatsPktsTx65Octetsto127Octets);
7455         }
7456
7457         if (sblk->stat_EtherStatsPktsTx128Octetsto255Octets) {
7458                 if_printf(ifp, "         0x%08X : "
7459                           "EtherStatsPktsTx128Octetsto255Octets\n",
7460                           sblk->stat_EtherStatsPktsTx128Octetsto255Octets);
7461         }
7462
7463         if (sblk->stat_EtherStatsPktsTx256Octetsto511Octets) {
7464                 if_printf(ifp, "         0x%08X : "
7465                           "EtherStatsPktsTx256Octetsto511Octets\n",
7466                           sblk->stat_EtherStatsPktsTx256Octetsto511Octets);
7467         }
7468
7469         if (sblk->stat_EtherStatsPktsTx512Octetsto1023Octets) {
7470                 if_printf(ifp, "         0x%08X : "
7471                           "EtherStatsPktsTx512Octetsto1023Octets\n",
7472                           sblk->stat_EtherStatsPktsTx512Octetsto1023Octets);
7473         }
7474
7475         if (sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets) {
7476                 if_printf(ifp, "         0x%08X : "
7477                           "EtherStatsPktsTx1024Octetsto1522Octets\n",
7478                           sblk->stat_EtherStatsPktsTx1024Octetsto1522Octets);
7479         }
7480
7481         if (sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets) {
7482                 if_printf(ifp, "         0x%08X : "
7483                           "EtherStatsPktsTx1523Octetsto9022Octets\n",
7484                           sblk->stat_EtherStatsPktsTx1523Octetsto9022Octets);
7485         }
7486
7487         if (sblk->stat_XonPauseFramesReceived) {
7488                 if_printf(ifp, "         0x%08X : XonPauseFramesReceived\n",
7489                           sblk->stat_XonPauseFramesReceived);
7490         }
7491
7492         if (sblk->stat_XoffPauseFramesReceived) {
7493                 if_printf(ifp, "          0x%08X : XoffPauseFramesReceived\n",
7494                           sblk->stat_XoffPauseFramesReceived);
7495         }
7496
7497         if (sblk->stat_OutXonSent) {
7498                 if_printf(ifp, "         0x%08X : OutXoffSent\n",
7499                           sblk->stat_OutXonSent);
7500         }
7501
7502         if (sblk->stat_OutXoffSent) {
7503                 if_printf(ifp, "         0x%08X : OutXoffSent\n",
7504                           sblk->stat_OutXoffSent);
7505         }
7506
7507         if (sblk->stat_FlowControlDone) {
7508                 if_printf(ifp, "         0x%08X : FlowControlDone\n",
7509                           sblk->stat_FlowControlDone);
7510         }
7511
7512         if (sblk->stat_MacControlFramesReceived) {
7513                 if_printf(ifp, "         0x%08X : MacControlFramesReceived\n",
7514                           sblk->stat_MacControlFramesReceived);
7515         }
7516
7517         if (sblk->stat_XoffStateEntered) {
7518                 if_printf(ifp, "         0x%08X : XoffStateEntered\n",
7519                           sblk->stat_XoffStateEntered);
7520         }
7521
7522         if (sblk->stat_IfInFramesL2FilterDiscards) {
7523                 if_printf(ifp, "         0x%08X : IfInFramesL2FilterDiscards\n",                          sblk->stat_IfInFramesL2FilterDiscards);
7524         }
7525
7526         if (sblk->stat_IfInRuleCheckerDiscards) {
7527                 if_printf(ifp, "         0x%08X : IfInRuleCheckerDiscards\n",
7528                           sblk->stat_IfInRuleCheckerDiscards);
7529         }
7530
7531         if (sblk->stat_IfInFTQDiscards) {
7532                 if_printf(ifp, "         0x%08X : IfInFTQDiscards\n",
7533                           sblk->stat_IfInFTQDiscards);
7534         }
7535
7536         if (sblk->stat_IfInMBUFDiscards) {
7537                 if_printf(ifp, "         0x%08X : IfInMBUFDiscards\n",
7538                           sblk->stat_IfInMBUFDiscards);
7539         }
7540
7541         if (sblk->stat_IfInRuleCheckerP4Hit) {
7542                 if_printf(ifp, "         0x%08X : IfInRuleCheckerP4Hit\n",
7543                           sblk->stat_IfInRuleCheckerP4Hit);
7544         }
7545
7546         if (sblk->stat_CatchupInRuleCheckerDiscards) {
7547                 if_printf(ifp, "         0x%08X : "
7548                           "CatchupInRuleCheckerDiscards\n",
7549                           sblk->stat_CatchupInRuleCheckerDiscards);
7550         }
7551
7552         if (sblk->stat_CatchupInFTQDiscards) {
7553                 if_printf(ifp, "         0x%08X : CatchupInFTQDiscards\n",
7554                           sblk->stat_CatchupInFTQDiscards);
7555         }
7556
7557         if (sblk->stat_CatchupInMBUFDiscards) {
7558                 if_printf(ifp, "         0x%08X : CatchupInMBUFDiscards\n",
7559                           sblk->stat_CatchupInMBUFDiscards);
7560         }
7561
7562         if (sblk->stat_CatchupInRuleCheckerP4Hit) {
7563                 if_printf(ifp, "         0x%08X : CatchupInRuleCheckerP4Hit\n",
7564                           sblk->stat_CatchupInRuleCheckerP4Hit);
7565         }
7566
7567         if_printf(ifp,
7568         "----------------------------"
7569         "----------------"
7570         "----------------------------\n");
7571 }
7572
7573
7574 /****************************************************************************/
7575 /* Prints out a summary of the driver state.                                */
7576 /*                                                                          */
7577 /* Returns:                                                                 */
7578 /*   Nothing.                                                               */
7579 /****************************************************************************/
7580 static void
7581 bce_dump_driver_state(struct bce_softc *sc)
7582 {
7583         struct ifnet *ifp = &sc->arpcom.ac_if;
7584         uint32_t val_hi, val_lo;
7585
7586         if_printf(ifp,
7587         "-----------------------------"
7588         " Driver State "
7589         "-----------------------------\n");
7590
7591         val_hi = BCE_ADDR_HI(sc);
7592         val_lo = BCE_ADDR_LO(sc);
7593         if_printf(ifp, "0x%08X:%08X - (sc) driver softc structure "
7594                   "virtual address\n", val_hi, val_lo);
7595
7596         val_hi = BCE_ADDR_HI(sc->status_block);
7597         val_lo = BCE_ADDR_LO(sc->status_block);
7598         if_printf(ifp, "0x%08X:%08X - (sc->status_block) status block "
7599                   "virtual address\n", val_hi, val_lo);
7600
7601         val_hi = BCE_ADDR_HI(sc->stats_block);
7602         val_lo = BCE_ADDR_LO(sc->stats_block);
7603         if_printf(ifp, "0x%08X:%08X - (sc->stats_block) statistics block "
7604                   "virtual address\n", val_hi, val_lo);
7605
7606         val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
7607         val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
7608         if_printf(ifp, "0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
7609                   "virtual adddress\n", val_hi, val_lo);
7610
7611         val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
7612         val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
7613         if_printf(ifp, "0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
7614                   "virtual address\n", val_hi, val_lo);
7615
7616         val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
7617         val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
7618         if_printf(ifp, "0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
7619                   "virtual address\n", val_hi, val_lo);
7620
7621         val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
7622         val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
7623         if_printf(ifp, "0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
7624                   "virtual address\n", val_hi, val_lo);
7625
7626         if_printf(ifp, "         0x%08X - (sc->interrupts_generated) "
7627                   "h/w intrs\n", sc->interrupts_generated);
7628
7629         if_printf(ifp, "         0x%08X - (sc->rx_interrupts) "
7630                   "rx interrupts handled\n", sc->rx_interrupts);
7631
7632         if_printf(ifp, "         0x%08X - (sc->tx_interrupts) "
7633                   "tx interrupts handled\n", sc->tx_interrupts);
7634
7635         if_printf(ifp, "         0x%08X - (sc->last_status_idx) "
7636                   "status block index\n", sc->last_status_idx);
7637
7638         if_printf(ifp, "     0x%04X(0x%04X) - (sc->tx_prod) "
7639                   "tx producer index\n",
7640                   sc->tx_prod, (uint16_t)TX_CHAIN_IDX(sc, sc->tx_prod));
7641
7642         if_printf(ifp, "     0x%04X(0x%04X) - (sc->tx_cons) "
7643                   "tx consumer index\n",
7644                   sc->tx_cons, (uint16_t)TX_CHAIN_IDX(sc, sc->tx_cons));
7645
7646         if_printf(ifp, "         0x%08X - (sc->tx_prod_bseq) "
7647                   "tx producer bseq index\n", sc->tx_prod_bseq);
7648
7649         if_printf(ifp, "     0x%04X(0x%04X) - (sc->rx_prod) "
7650                   "rx producer index\n",
7651                   sc->rx_prod, (uint16_t)RX_CHAIN_IDX(sc, sc->rx_prod));
7652
7653         if_printf(ifp, "     0x%04X(0x%04X) - (sc->rx_cons) "
7654                   "rx consumer index\n",
7655                   sc->rx_cons, (uint16_t)RX_CHAIN_IDX(sc, sc->rx_cons));
7656
7657         if_printf(ifp, "         0x%08X - (sc->rx_prod_bseq) "
7658                   "rx producer bseq index\n", sc->rx_prod_bseq);
7659
7660         if_printf(ifp, "         0x%08X - (sc->rx_mbuf_alloc) "
7661                   "rx mbufs allocated\n", sc->rx_mbuf_alloc);
7662
7663         if_printf(ifp, "         0x%08X - (sc->free_rx_bd) "
7664                   "free rx_bd's\n", sc->free_rx_bd);
7665
7666         if_printf(ifp, "0x%08X/%08X - (sc->rx_low_watermark) rx "
7667                   "low watermark\n", sc->rx_low_watermark, sc->max_rx_bd);
7668
7669         if_printf(ifp, "         0x%08X - (sc->txmbuf_alloc) "
7670                   "tx mbufs allocated\n", sc->tx_mbuf_alloc);
7671
7672         if_printf(ifp, "         0x%08X - (sc->rx_mbuf_alloc) "
7673                   "rx mbufs allocated\n", sc->rx_mbuf_alloc);
7674
7675         if_printf(ifp, "         0x%08X - (sc->used_tx_bd) used tx_bd's\n",
7676                   sc->used_tx_bd);
7677
7678         if_printf(ifp, "0x%08X/%08X - (sc->tx_hi_watermark) tx hi watermark\n",
7679                   sc->tx_hi_watermark, sc->max_tx_bd);
7680
7681         if_printf(ifp, "         0x%08X - (sc->mbuf_alloc_failed) "
7682                   "failed mbuf alloc\n", sc->mbuf_alloc_failed);
7683
7684         if_printf(ifp,
7685         "----------------------------"
7686         "----------------"
7687         "----------------------------\n");
7688 }
7689
7690
7691 /****************************************************************************/
7692 /* Prints out the hardware state through a summary of important registers,  */
7693 /* followed by a complete register dump.                                    */
7694 /*                                                                          */
7695 /* Returns:                                                                 */
7696 /*   Nothing.                                                               */
7697 /****************************************************************************/
7698 static void
7699 bce_dump_hw_state(struct bce_softc *sc)
7700 {
7701         struct ifnet *ifp = &sc->arpcom.ac_if;
7702         uint32_t val1;
7703         int i;
7704
7705         if_printf(ifp,
7706         "----------------------------"
7707         " Hardware State "
7708         "----------------------------\n");
7709
7710         if_printf(ifp, "%s - bootcode version\n", sc->bce_bc_ver);
7711
7712         val1 = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
7713         if_printf(ifp, "0x%08X - (0x%06X) misc_enable_status_bits\n",
7714                   val1, BCE_MISC_ENABLE_STATUS_BITS);
7715
7716         val1 = REG_RD(sc, BCE_DMA_STATUS);
7717         if_printf(ifp, "0x%08X - (0x%04X) dma_status\n", val1, BCE_DMA_STATUS);
7718
7719         val1 = REG_RD(sc, BCE_CTX_STATUS);
7720         if_printf(ifp, "0x%08X - (0x%04X) ctx_status\n", val1, BCE_CTX_STATUS);
7721
7722         val1 = REG_RD(sc, BCE_EMAC_STATUS);
7723         if_printf(ifp, "0x%08X - (0x%04X) emac_status\n",
7724                   val1, BCE_EMAC_STATUS);
7725
7726         val1 = REG_RD(sc, BCE_RPM_STATUS);
7727         if_printf(ifp, "0x%08X - (0x%04X) rpm_status\n", val1, BCE_RPM_STATUS);
7728
7729         val1 = REG_RD(sc, BCE_TBDR_STATUS);
7730         if_printf(ifp, "0x%08X - (0x%04X) tbdr_status\n",
7731                   val1, BCE_TBDR_STATUS);
7732
7733         val1 = REG_RD(sc, BCE_TDMA_STATUS);
7734         if_printf(ifp, "0x%08X - (0x%04X) tdma_status\n",
7735                   val1, BCE_TDMA_STATUS);
7736
7737         val1 = REG_RD(sc, BCE_HC_STATUS);
7738         if_printf(ifp, "0x%08X - (0x%06X) hc_status\n", val1, BCE_HC_STATUS);
7739
7740         val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7741         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7742                   val1, BCE_TXP_CPU_STATE);
7743
7744         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7745         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7746                   val1, BCE_TPAT_CPU_STATE);
7747
7748         val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7749         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7750                   val1, BCE_RXP_CPU_STATE);
7751
7752         val1 = REG_RD_IND(sc, BCE_COM_CPU_STATE);
7753         if_printf(ifp, "0x%08X - (0x%06X) com_cpu_state\n",
7754                   val1, BCE_COM_CPU_STATE);
7755
7756         val1 = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
7757         if_printf(ifp, "0x%08X - (0x%06X) mcp_cpu_state\n",
7758                   val1, BCE_MCP_CPU_STATE);
7759
7760         val1 = REG_RD_IND(sc, BCE_CP_CPU_STATE);
7761         if_printf(ifp, "0x%08X - (0x%06X) cp_cpu_state\n",
7762                   val1, BCE_CP_CPU_STATE);
7763
7764         if_printf(ifp,
7765         "----------------------------"
7766         "----------------"
7767         "----------------------------\n");
7768
7769         if_printf(ifp,
7770         "----------------------------"
7771         " Register  Dump "
7772         "----------------------------\n");
7773
7774         for (i = 0x400; i < 0x8000; i += 0x10) {
7775                 if_printf(ifp, "0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7776                           REG_RD(sc, i),
7777                           REG_RD(sc, i + 0x4),
7778                           REG_RD(sc, i + 0x8),
7779                           REG_RD(sc, i + 0xc));
7780         }
7781
7782         if_printf(ifp,
7783         "----------------------------"
7784         "----------------"
7785         "----------------------------\n");
7786 }
7787
7788
7789 /****************************************************************************/
7790 /* Prints out the TXP state.                                                */
7791 /*                                                                          */
7792 /* Returns:                                                                 */
7793 /*   Nothing.                                                               */
7794 /****************************************************************************/
7795 static void
7796 bce_dump_txp_state(struct bce_softc *sc)
7797 {
7798         struct ifnet *ifp = &sc->arpcom.ac_if;
7799         uint32_t val1;
7800         int i;
7801
7802         if_printf(ifp,
7803         "----------------------------"
7804         "   TXP  State   "
7805         "----------------------------\n");
7806
7807         val1 = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
7808         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_mode\n",
7809                   val1, BCE_TXP_CPU_MODE);
7810
7811         val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
7812         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_state\n",
7813                   val1, BCE_TXP_CPU_STATE);
7814
7815         val1 = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
7816         if_printf(ifp, "0x%08X - (0x%06X) txp_cpu_event_mask\n",
7817                   val1, BCE_TXP_CPU_EVENT_MASK);
7818
7819         if_printf(ifp,
7820         "----------------------------"
7821         " Register  Dump "
7822         "----------------------------\n");
7823
7824         for (i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
7825                 /* Skip the big blank spaces */
7826                 if (i < 0x454000 && i > 0x5ffff) {
7827                         if_printf(ifp, "0x%04X: "
7828                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7829                                   REG_RD_IND(sc, i),
7830                                   REG_RD_IND(sc, i + 0x4),
7831                                   REG_RD_IND(sc, i + 0x8),
7832                                   REG_RD_IND(sc, i + 0xc));
7833                 }
7834         }
7835
7836         if_printf(ifp,
7837         "----------------------------"
7838         "----------------"
7839         "----------------------------\n");
7840 }
7841
7842
7843 /****************************************************************************/
7844 /* Prints out the RXP state.                                                */
7845 /*                                                                          */
7846 /* Returns:                                                                 */
7847 /*   Nothing.                                                               */
7848 /****************************************************************************/
7849 static void
7850 bce_dump_rxp_state(struct bce_softc *sc)
7851 {
7852         struct ifnet *ifp = &sc->arpcom.ac_if;
7853         uint32_t val1;
7854         int i;
7855
7856         if_printf(ifp,
7857         "----------------------------"
7858         "   RXP  State   "
7859         "----------------------------\n");
7860
7861         val1 = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
7862         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_mode\n",
7863                   val1, BCE_RXP_CPU_MODE);
7864
7865         val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
7866         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_state\n",
7867                   val1, BCE_RXP_CPU_STATE);
7868
7869         val1 = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
7870         if_printf(ifp, "0x%08X - (0x%06X) rxp_cpu_event_mask\n",
7871                   val1, BCE_RXP_CPU_EVENT_MASK);
7872
7873         if_printf(ifp,
7874         "----------------------------"
7875         " Register  Dump "
7876         "----------------------------\n");
7877
7878         for (i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
7879                 /* Skip the big blank sapces */
7880                 if (i < 0xc5400 && i > 0xdffff) {
7881                         if_printf(ifp, "0x%04X: "
7882                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7883                                   REG_RD_IND(sc, i),
7884                                   REG_RD_IND(sc, i + 0x4),
7885                                   REG_RD_IND(sc, i + 0x8),
7886                                   REG_RD_IND(sc, i + 0xc));
7887                 }
7888         }
7889
7890         if_printf(ifp,
7891         "----------------------------"
7892         "----------------"
7893         "----------------------------\n");
7894 }
7895
7896
7897 /****************************************************************************/
7898 /* Prints out the TPAT state.                                               */
7899 /*                                                                          */
7900 /* Returns:                                                                 */
7901 /*   Nothing.                                                               */
7902 /****************************************************************************/
7903 static void
7904 bce_dump_tpat_state(struct bce_softc *sc)
7905 {
7906         struct ifnet *ifp = &sc->arpcom.ac_if;
7907         uint32_t val1;
7908         int i;
7909
7910         if_printf(ifp,
7911         "----------------------------"
7912         "   TPAT State   "
7913         "----------------------------\n");
7914
7915         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
7916         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_mode\n",
7917                   val1, BCE_TPAT_CPU_MODE);
7918
7919         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
7920         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_state\n",
7921                   val1, BCE_TPAT_CPU_STATE);
7922
7923         val1 = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
7924         if_printf(ifp, "0x%08X - (0x%06X) tpat_cpu_event_mask\n",
7925                   val1, BCE_TPAT_CPU_EVENT_MASK);
7926
7927         if_printf(ifp,
7928         "----------------------------"
7929         " Register  Dump "
7930         "----------------------------\n");
7931
7932         for (i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
7933                 /* Skip the big blank spaces */
7934                 if (i < 0x854000 && i > 0x9ffff) {
7935                         if_printf(ifp, "0x%04X: "
7936                                   "0x%08X 0x%08X 0x%08X 0x%08X\n", i,
7937                                   REG_RD_IND(sc, i),
7938                                   REG_RD_IND(sc, i + 0x4),
7939                                   REG_RD_IND(sc, i + 0x8),
7940                                   REG_RD_IND(sc, i + 0xc));
7941                 }
7942         }
7943
7944         if_printf(ifp,
7945         "----------------------------"
7946         "----------------"
7947         "----------------------------\n");
7948 }
7949
7950
7951 /****************************************************************************/
7952 /* Prints out the driver state and then enters the debugger.                */
7953 /*                                                                          */
7954 /* Returns:                                                                 */
7955 /*   Nothing.                                                               */
7956 /****************************************************************************/
7957 static void
7958 bce_breakpoint(struct bce_softc *sc)
7959 {
7960 #if 0
7961         bce_freeze_controller(sc);
7962 #endif
7963
7964         bce_dump_driver_state(sc);
7965         bce_dump_status_block(sc);
7966         bce_dump_tx_chain(sc, 0, TOTAL_TX_BD(sc));
7967         bce_dump_hw_state(sc);
7968         bce_dump_txp_state(sc);
7969
7970 #if 0
7971         bce_unfreeze_controller(sc);
7972 #endif
7973
7974         /* Call the debugger. */
7975         breakpoint();
7976 }
7977
7978 #endif  /* BCE_DEBUG */
7979
7980 static int
7981 bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS)
7982 {
7983         struct bce_softc *sc = arg1;
7984
7985         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7986                         &sc->bce_tx_quick_cons_trip_int,
7987                         BCE_COALMASK_TX_BDS_INT);
7988 }
7989
7990 static int
7991 bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS)
7992 {
7993         struct bce_softc *sc = arg1;
7994
7995         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
7996                         &sc->bce_tx_quick_cons_trip,
7997                         BCE_COALMASK_TX_BDS);
7998 }
7999
8000 static int
8001 bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS)
8002 {
8003         struct bce_softc *sc = arg1;
8004
8005         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
8006                         &sc->bce_tx_ticks_int,
8007                         BCE_COALMASK_TX_TICKS_INT);
8008 }
8009
8010 static int
8011 bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS)
8012 {
8013         struct bce_softc *sc = arg1;
8014
8015         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
8016                         &sc->bce_tx_ticks,
8017                         BCE_COALMASK_TX_TICKS);
8018 }
8019
8020 static int
8021 bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS)
8022 {
8023         struct bce_softc *sc = arg1;
8024
8025         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
8026                         &sc->bce_rx_quick_cons_trip_int,
8027                         BCE_COALMASK_RX_BDS_INT);
8028 }
8029
8030 static int
8031 bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS)
8032 {
8033         struct bce_softc *sc = arg1;
8034
8035         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
8036                         &sc->bce_rx_quick_cons_trip,
8037                         BCE_COALMASK_RX_BDS);
8038 }
8039
8040 static int
8041 bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS)
8042 {
8043         struct bce_softc *sc = arg1;
8044
8045         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
8046                         &sc->bce_rx_ticks_int,
8047                         BCE_COALMASK_RX_TICKS_INT);
8048 }
8049
8050 static int
8051 bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS)
8052 {
8053         struct bce_softc *sc = arg1;
8054
8055         return bce_sysctl_coal_change(oidp, arg1, arg2, req,
8056                         &sc->bce_rx_ticks,
8057                         BCE_COALMASK_RX_TICKS);
8058 }
8059
8060 static int
8061 bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS, uint32_t *coal,
8062                        uint32_t coalchg_mask)
8063 {
8064         struct bce_softc *sc = arg1;
8065         struct ifnet *ifp = &sc->arpcom.ac_if;
8066         int error = 0, v;
8067
8068         lwkt_serialize_enter(ifp->if_serializer);
8069
8070         v = *coal;
8071         error = sysctl_handle_int(oidp, &v, 0, req);
8072         if (!error && req->newptr != NULL) {
8073                 if (v < 0) {
8074                         error = EINVAL;
8075                 } else {
8076                         *coal = v;
8077                         sc->bce_coalchg_mask |= coalchg_mask;
8078                 }
8079         }
8080
8081         lwkt_serialize_exit(ifp->if_serializer);
8082         return error;
8083 }
8084
8085 static void
8086 bce_coal_change(struct bce_softc *sc)
8087 {
8088         struct ifnet *ifp = &sc->arpcom.ac_if;
8089
8090         ASSERT_SERIALIZED(ifp->if_serializer);
8091
8092         if ((ifp->if_flags & IFF_RUNNING) == 0) {
8093                 sc->bce_coalchg_mask = 0;
8094                 return;
8095         }
8096
8097         if (sc->bce_coalchg_mask &
8098             (BCE_COALMASK_TX_BDS | BCE_COALMASK_TX_BDS_INT)) {
8099                 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
8100                        (sc->bce_tx_quick_cons_trip_int << 16) |
8101                        sc->bce_tx_quick_cons_trip);
8102                 if (bootverbose) {
8103                         if_printf(ifp, "tx_bds %u, tx_bds_int %u\n",
8104                                   sc->bce_tx_quick_cons_trip,
8105                                   sc->bce_tx_quick_cons_trip_int);
8106                 }
8107         }
8108
8109         if (sc->bce_coalchg_mask &
8110             (BCE_COALMASK_TX_TICKS | BCE_COALMASK_TX_TICKS_INT)) {
8111                 REG_WR(sc, BCE_HC_TX_TICKS,
8112                        (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
8113                 if (bootverbose) {
8114                         if_printf(ifp, "tx_ticks %u, tx_ticks_int %u\n",
8115                                   sc->bce_tx_ticks, sc->bce_tx_ticks_int);
8116                 }
8117         }
8118
8119         if (sc->bce_coalchg_mask &
8120             (BCE_COALMASK_RX_BDS | BCE_COALMASK_RX_BDS_INT)) {
8121                 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
8122                        (sc->bce_rx_quick_cons_trip_int << 16) |
8123                        sc->bce_rx_quick_cons_trip);
8124                 if (bootverbose) {
8125                         if_printf(ifp, "rx_bds %u, rx_bds_int %u\n",
8126                                   sc->bce_rx_quick_cons_trip,
8127                                   sc->bce_rx_quick_cons_trip_int);
8128                 }
8129         }
8130
8131         if (sc->bce_coalchg_mask &
8132             (BCE_COALMASK_RX_TICKS | BCE_COALMASK_RX_TICKS_INT)) {
8133                 REG_WR(sc, BCE_HC_RX_TICKS,
8134                        (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
8135                 if (bootverbose) {
8136                         if_printf(ifp, "rx_ticks %u, rx_ticks_int %u\n",
8137                                   sc->bce_rx_ticks, sc->bce_rx_ticks_int);
8138                 }
8139         }
8140
8141         sc->bce_coalchg_mask = 0;
8142 }