drm/radeon: Sync gpu driver code with Linux 3.11
authorzrj <rimvydas.jasinskas@gmail.com>
Wed, 3 Jun 2015 12:01:30 +0000 (15:01 +0300)
committerFrançois Tigeot <ftigeot@wolfpond.org>
Sat, 6 Jun 2015 11:46:26 +0000 (13:46 +0200)
Little to none functional change.

Use kzalloc()/kfree()/kcalloc() wrappers.
Also use mb() and rmb().

Use linux compat macros:
  udelay, mdelay
  wake_up
  printk
  ARRAY_SIZE
  ALIGN, round_up
  BUG, BUG_ON, BUILD_BUG_ON, WARN

While there, reduce whitespace diffs with Linux 3.11

82 files changed:
sys/dev/drm/radeon/ObjectID.h
sys/dev/drm/radeon/atom.c
sys/dev/drm/radeon/atombios_dp.c
sys/dev/drm/radeon/atombios_encoders.c
sys/dev/drm/radeon/btc_dpm.c
sys/dev/drm/radeon/cayman_blit_shaders.c
sys/dev/drm/radeon/cik.c
sys/dev/drm/radeon/cypress_dpm.c
sys/dev/drm/radeon/evergreen.c
sys/dev/drm/radeon/evergreen_blit_kms.c
sys/dev/drm/radeon/evergreen_blit_shaders.c
sys/dev/drm/radeon/evergreen_cs.c
sys/dev/drm/radeon/evergreen_hdmi.c
sys/dev/drm/radeon/ni.c
sys/dev/drm/radeon/ni_dpm.c
sys/dev/drm/radeon/r100.c
sys/dev/drm/radeon/r200.c
sys/dev/drm/radeon/r300.c
sys/dev/drm/radeon/r420.c
sys/dev/drm/radeon/r520.c
sys/dev/drm/radeon/r600.c
sys/dev/drm/radeon/r600_audio.c
sys/dev/drm/radeon/r600_blit.c
sys/dev/drm/radeon/r600_blit_kms.c
sys/dev/drm/radeon/r600_blit_shaders.c
sys/dev/drm/radeon/r600_cp.c
sys/dev/drm/radeon/r600_cs.c
sys/dev/drm/radeon/r600_dpm.c
sys/dev/drm/radeon/r600_hdmi.c
sys/dev/drm/radeon/radeon.h
sys/dev/drm/radeon/radeon_acpi.c
sys/dev/drm/radeon/radeon_acpi.h
sys/dev/drm/radeon/radeon_asic.c
sys/dev/drm/radeon/radeon_asic.h
sys/dev/drm/radeon/radeon_atombios.c
sys/dev/drm/radeon/radeon_bios.c
sys/dev/drm/radeon/radeon_clocks.c
sys/dev/drm/radeon/radeon_combios.c
sys/dev/drm/radeon/radeon_connectors.c
sys/dev/drm/radeon/radeon_cp.c
sys/dev/drm/radeon/radeon_cs.c
sys/dev/drm/radeon/radeon_cursor.c
sys/dev/drm/radeon/radeon_device.c
sys/dev/drm/radeon/radeon_display.c
sys/dev/drm/radeon/radeon_drv.c
sys/dev/drm/radeon/radeon_drv.h
sys/dev/drm/radeon/radeon_fb.c
sys/dev/drm/radeon/radeon_fence.c
sys/dev/drm/radeon/radeon_gart.c
sys/dev/drm/radeon/radeon_gem.c
sys/dev/drm/radeon/radeon_i2c.c
sys/dev/drm/radeon/radeon_kms.c
sys/dev/drm/radeon/radeon_legacy_crtc.c
sys/dev/drm/radeon/radeon_legacy_encoders.c
sys/dev/drm/radeon/radeon_legacy_tv.c
sys/dev/drm/radeon/radeon_mem.c
sys/dev/drm/radeon/radeon_object.c
sys/dev/drm/radeon/radeon_pm.c
sys/dev/drm/radeon/radeon_ring.c
sys/dev/drm/radeon/radeon_sa.c
sys/dev/drm/radeon/radeon_semaphore.c
sys/dev/drm/radeon/radeon_state.c
sys/dev/drm/radeon/radeon_test.c
sys/dev/drm/radeon/radeon_ttm.c
sys/dev/drm/radeon/radeon_uvd.c
sys/dev/drm/radeon/rs400.c
sys/dev/drm/radeon/rs600.c
sys/dev/drm/radeon/rs690.c
sys/dev/drm/radeon/rs780_dpm.c
sys/dev/drm/radeon/rv515.c
sys/dev/drm/radeon/rv6xx_dpm.c
sys/dev/drm/radeon/rv770.c
sys/dev/drm/radeon/rv770_dpm.c
sys/dev/drm/radeon/rv770_smc.c
sys/dev/drm/radeon/si.c
sys/dev/drm/radeon/si_blit_shaders.c
sys/dev/drm/radeon/si_dpm.c
sys/dev/drm/radeon/si_smc.c
sys/dev/drm/radeon/sumo_dpm.c
sys/dev/drm/radeon/sumo_smc.c
sys/dev/drm/radeon/trinity_dpm.c
sys/dev/drm/radeon/trinity_smc.c

index 73a9155..0619269 100644 (file)
@@ -18,8 +18,6 @@
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
-*
-* $FreeBSD: head/sys/dev/drm2/radeon/ObjectID.h 254885 2013-08-25 19:37:15Z dumbbell $
 */
 /* based on stg/asic_reg/drivers/inc/asic_reg/ObjectID.h ver 23 */
 
index 1b0aaf9..8c98f62 100644 (file)
@@ -661,9 +661,9 @@ static void atom_op_delay(atom_exec_context *ctx, int *ptr, int arg)
        unsigned count = U8((*ptr)++);
        ATOM_SDEBUG_PRINT("   count: %d\n", count);
        if (arg == ATOM_UNIT_MICROSEC)
-               DRM_UDELAY(count);
+               udelay(count);
        else if (!drm_can_sleep())
-               DRM_MDELAY(count);
+               mdelay(count);
        else
                msleep(count);
 }
@@ -1178,7 +1178,7 @@ static int atom_execute_table_locked(struct atom_context *ctx, int index, uint32
        ectx.abort = false;
        ectx.last_jump = 0;
        if (ws)
-               ectx.ws = kmalloc(4 * ws, M_DRM, M_ZERO | M_WAITOK);
+               ectx.ws = kzalloc(4 * ws, GFP_KERNEL);
        else
                ectx.ws = NULL;
 
@@ -1210,7 +1210,7 @@ static int atom_execute_table_locked(struct atom_context *ctx, int index, uint32
 
 free:
        if (ws)
-               drm_free(ectx.ws, M_DRM);
+               kfree(ectx.ws);
        return ret;
 }
 
@@ -1239,7 +1239,7 @@ static int atom_iio_len[] = { 1, 2, 3, 3, 3, 3, 4, 4, 4, 3 };
 
 static void atom_index_iio(struct atom_context *ctx, int base)
 {
-       ctx->iio = kmalloc(2 * 256, M_DRM, M_ZERO | M_WAITOK);
+       ctx->iio = kzalloc(2 * 256, GFP_KERNEL);
        if (!ctx->iio)
                return;
        while (CU8(base) == ATOM_IIO_START) {
@@ -1255,8 +1255,7 @@ struct atom_context *atom_parse(struct card_info *card, void *bios)
 {
        int base;
        struct atom_context *ctx =
-           kmalloc(sizeof(struct atom_context), M_DRM,
-                   M_ZERO | M_WAITOK);
+           kzalloc(sizeof(struct atom_context), GFP_KERNEL);
        char *str;
        char name[512];
        int i;
@@ -1269,14 +1268,14 @@ struct atom_context *atom_parse(struct card_info *card, void *bios)
 
        if (CU16(0) != ATOM_BIOS_MAGIC) {
                DRM_INFO("Invalid BIOS magic.\n");
-               drm_free(ctx, M_DRM);
+               kfree(ctx);
                return NULL;
        }
        if (strncmp
            (CSTR(ATOM_ATI_MAGIC_PTR), ATOM_ATI_MAGIC,
             strlen(ATOM_ATI_MAGIC))) {
                DRM_INFO("Invalid ATI magic.\n");
-               drm_free(ctx, M_DRM);
+               kfree(ctx);
                return NULL;
        }
 
@@ -1285,7 +1284,7 @@ struct atom_context *atom_parse(struct card_info *card, void *bios)
            (CSTR(base + ATOM_ROM_MAGIC_PTR), ATOM_ROM_MAGIC,
             strlen(ATOM_ROM_MAGIC))) {
                DRM_INFO("Invalid ATOM magic.\n");
-               drm_free(ctx, M_DRM);
+               kfree(ctx);
                return NULL;
        }
 
@@ -1344,8 +1343,8 @@ int atom_asic_init(struct atom_context *ctx)
 
 void atom_destroy(struct atom_context *ctx)
 {
-       drm_free(ctx->iio, M_DRM);
-       drm_free(ctx, M_DRM);
+       kfree(ctx->iio);
+       kfree(ctx);
 }
 
 bool atom_parse_data_header(struct atom_context *ctx, int index,
@@ -1406,7 +1405,7 @@ int atom_allocate_fb_scratch(struct atom_context *ctx)
        if (usage_bytes == 0)
                usage_bytes = 20 * 1024;
        /* allocate some scratch memory */
-       ctx->scratch = kmalloc(usage_bytes, M_DRM, M_ZERO | M_WAITOK);
+       ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
        if (!ctx->scratch)
                return -ENOMEM;
        ctx->scratch_size_bytes = usage_bytes;
index 51a7428..8a3bb52 100644 (file)
  * Authors: Dave Airlie
  *          Alex Deucher
  *          Jerome Glisse
- *
- * $FreeBSD: head/sys/dev/drm2/radeon/atombios_dp.c 254885 2013-08-25 19:37:15Z dumbbell $
  */
-
 #include <drm/drmP.h>
 #include <uapi_drm/radeon_drm.h>
 #include "radeon.h"
@@ -175,7 +172,7 @@ static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
                if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
                        return send_bytes;
                else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
-                       DRM_UDELAY(400);
+                       udelay(400);
                else
                        return -EIO;
        }
@@ -209,7 +206,7 @@ static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
                if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
                        return ret;
                else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
-                       DRM_UDELAY(400);
+                       udelay(400);
                else if (ret == 0)
                        return -EPROTO;
                else
@@ -297,7 +294,7 @@ int radeon_dp_i2c_aux_ch(device_t dev, int mode, u8 write_byte, u8 *read_byte)
                        return -EREMOTEIO;
                case DP_AUX_NATIVE_REPLY_DEFER:
                        DRM_DEBUG_KMS("aux_ch native defer\n");
-                       DRM_UDELAY(400);
+                       udelay(400);
                        continue;
                default:
                        DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack);
@@ -314,7 +311,7 @@ int radeon_dp_i2c_aux_ch(device_t dev, int mode, u8 write_byte, u8 *read_byte)
                        return -EREMOTEIO;
                case DP_AUX_I2C_REPLY_DEFER:
                        DRM_DEBUG_KMS("aux_i2c defer\n");
-                       DRM_UDELAY(400);
+                       udelay(400);
                        break;
                default:
                        DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack);
@@ -721,7 +718,7 @@ static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
 
 static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
 {
-       DRM_UDELAY(400);
+       udelay(400);
 
        /* disable the training pattern on the sink */
        radeon_write_dpcd_reg(dp_info->radeon_connector,
@@ -749,7 +746,7 @@ static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
        memset(dp_info->train_set, 0, 4);
        radeon_dp_update_vs_emph(dp_info);
 
-       DRM_UDELAY(400);
+       udelay(400);
 
        /* clock recovery loop */
        clock_recovery = false;
index 91df95f..fd822a2 100644 (file)
@@ -238,7 +238,7 @@ void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
        return;
 
 error:
-       drm_free(pdata, M_DRM);
+       kfree(pdata);
        return;
 }
 
@@ -267,7 +267,7 @@ static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
 
                pdata = bl_get_data(bd);
                backlight_device_unregister(bd);
-               drm_free(pdata, M_DRM);
+               kfree(pdata);
 
                DRM_INFO("radeon atom LVDS backlight unloaded\n");
        }
@@ -1370,7 +1370,7 @@ atombios_set_edp_panel_power(struct drm_connector *connector, int action)
                for (i = 0; i < 300; i++) {
                        if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
                                return true;
-                       DRM_MDELAY(1);
+                       mdelay(1);
                }
                return false;
        }
@@ -2535,9 +2535,9 @@ void radeon_enc_destroy(struct drm_encoder *encoder)
        struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
        if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
                radeon_atom_backlight_exit(radeon_encoder);
-       drm_free(radeon_encoder->enc_priv, M_DRM);
+       kfree(radeon_encoder->enc_priv);
        drm_encoder_cleanup(encoder);
-       drm_free(radeon_encoder, M_DRM);
+       kfree(radeon_encoder);
 }
 
 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
@@ -2549,9 +2549,7 @@ radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
 {
        struct drm_device *dev = radeon_encoder->base.dev;
        struct radeon_device *rdev = dev->dev_private;
-       struct radeon_encoder_atom_dac *dac = kmalloc(sizeof(struct radeon_encoder_atom_dac),
-                                                     M_DRM,
-                                                     M_ZERO | M_WAITOK);
+       struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
 
        if (!dac)
                return NULL;
@@ -2564,9 +2562,7 @@ static struct radeon_encoder_atom_dig *
 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
 {
        int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
-       struct radeon_encoder_atom_dig *dig = kmalloc(sizeof(struct radeon_encoder_atom_dig),
-                                                     M_DRM,
-                                                     M_ZERO | M_WAITOK);
+       struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
 
        if (!dig)
                return NULL;
@@ -2604,8 +2600,7 @@ radeon_add_atom_encoder(struct drm_device *dev,
        }
 
        /* add a new one */
-       radeon_encoder = kmalloc(sizeof(struct radeon_encoder),
-                                M_DRM, M_ZERO | M_WAITOK);
+       radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
        if (!radeon_encoder)
                return;
 
index ee58a8b..176d119 100644 (file)
@@ -1333,7 +1333,7 @@ static void btc_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev,
 
                                tmp |= LC_CLR_FAILED_SPD_CHANGE_CNT;
                                WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
-                               DRM_UDELAY(10);
+                               udelay(10);
                                tmp &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
                                WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
                        }
@@ -1725,9 +1725,9 @@ static void btc_stop_smc(struct radeon_device *rdev)
        for (i = 0; i < rdev->usec_timeout; i++) {
                if (((RREG32(LB_SYNC_RESET_SEL) & LB_SYNC_RESET_SEL_MASK) >> LB_SYNC_RESET_SEL_SHIFT) != 1)
                        break;
-               DRM_UDELAY(1);
+               udelay(1);
        }
-       DRM_UDELAY(100);
+       udelay(100);
 
        r7xx_stop_smc(rdev);
 }
index 6b36b06..19a0114 100644 (file)
@@ -24,7 +24,9 @@
  *     Alex Deucher <alexander.deucher@amd.com>
  */
 
-#include <drm/drmP.h>
+#include <linux/bug.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
 
 /*
  * evergreen cards need to use the 3D engine to blit data which requires
@@ -367,6 +369,6 @@ const u32 cayman_ps[] =
        0x00000000,
 };
 
-const u32 cayman_ps_size = DRM_ARRAY_SIZE(cayman_ps);
-const u32 cayman_vs_size = DRM_ARRAY_SIZE(cayman_vs);
-const u32 cayman_default_size = DRM_ARRAY_SIZE(cayman_default_state);
+const u32 cayman_ps_size = ARRAY_SIZE(cayman_ps);
+const u32 cayman_vs_size = ARRAY_SIZE(cayman_vs);
+const u32 cayman_default_size = ARRAY_SIZE(cayman_default_state);
index 4447003..a1cc1c2 100644 (file)
@@ -706,12 +706,12 @@ static __unused int ci_mc_load_microcode(struct radeon_device *rdev)
                for (i = 0; i < rdev->usec_timeout; i++) {
                        if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
                                break;
-                       DRM_UDELAY(1);
+                       udelay(1);
                }
                for (i = 0; i < rdev->usec_timeout; i++) {
                        if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
                                break;
-                       DRM_UDELAY(1);
+                       udelay(1);
                }
 
                if (running)
@@ -1352,37 +1352,37 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
                                        break;
                                case 16:
                                        gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-                                                       MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-                                                       PIPE_CONFIG(ADDR_SURF_P4_8x16) |
-                                                       SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+                                                        MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+                                                        PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+                                                        SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
                                        break;
                                case 17:
                                        gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
-                                                       MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-                                                       PIPE_CONFIG(ADDR_SURF_P4_8x16) |
-                                                       SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+                                                        MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+                                                        PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+                                                        SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
                                        break;
                                case 27:
                                        gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-                                                       MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
+                                                        MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
                                        break;
                                case 28:
                                        gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
-                                                       MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-                                                       PIPE_CONFIG(ADDR_SURF_P4_8x16) |
-                                                       SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+                                                        MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+                                                        PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+                                                        SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
                                        break;
                                case 29:
                                        gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-                                                       MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-                                                       PIPE_CONFIG(ADDR_SURF_P4_8x16) |
-                                                       SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+                                                        MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+                                                        PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+                                                        SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
                                        break;
                                case 30:
                                        gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
-                                                       MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-                                                       PIPE_CONFIG(ADDR_SURF_P4_8x16) |
-                                                       SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+                                                        MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+                                                        PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+                                                        SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
                                        break;
                                default:
                                        gb_tile_moden = 0;
@@ -1394,310 +1394,310 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
                }
                for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
                        switch (reg_offset) {
-                               case 0:
-                                       gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                       BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-                                                       MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-                                                       NUM_BANKS(ADDR_SURF_16_BANK));
-                                       break;
-                               case 1:
-                                       gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                       BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-                                                       MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-                                                       NUM_BANKS(ADDR_SURF_16_BANK));
-                                       break;
-                               case 2:
-                                       gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                       BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-                                                       MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-                                                       NUM_BANKS(ADDR_SURF_16_BANK));
-                                       break;
-                               case 3:
-                                       gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                       BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-                                                       MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-                                                       NUM_BANKS(ADDR_SURF_16_BANK));
-                                       break;
-                               case 4:
-                                       gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                       BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-                                                       MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-                                                       NUM_BANKS(ADDR_SURF_16_BANK));
-                                       break;
-                               case 5:
-                                       gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                       BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-                                                       MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-                                                       NUM_BANKS(ADDR_SURF_8_BANK));
-                                       break;
-                               case 6:
-                                       gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                       BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-                                                       MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-                                                       NUM_BANKS(ADDR_SURF_4_BANK));
-                                       break;
-                               case 8:
-                                       gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-                                                       BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
-                                                       MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-                                                       NUM_BANKS(ADDR_SURF_16_BANK));
-                                       break;
-                               case 9:
-                                       gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-                                                       BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-                                                       MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-                                                       NUM_BANKS(ADDR_SURF_16_BANK));
-                                       break;
-                               case 10:
-                                       gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                       BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-                                                       MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-                                                       NUM_BANKS(ADDR_SURF_16_BANK));
-                                       break;
-                               case 11:
-                                       gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                       BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-                                                       MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-                                                       NUM_BANKS(ADDR_SURF_16_BANK));
-                                       break;
-                               case 12:
-                                       gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                       BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-                                                       MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-                                                       NUM_BANKS(ADDR_SURF_16_BANK));
-                                       break;
-                               case 13:
-                                       gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                       BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-                                                       MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-                                                       NUM_BANKS(ADDR_SURF_8_BANK));
-                                       break;
-                               case 14:
-                                       gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                       BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-                                                       MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-                                                       NUM_BANKS(ADDR_SURF_4_BANK));
-                                       break;
-                               default:
-                                       gb_tile_moden = 0;
-                                       break;
+                       case 0:
+                               gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+                                                NUM_BANKS(ADDR_SURF_16_BANK));
+                               break;
+                       case 1:
+                               gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+                                                NUM_BANKS(ADDR_SURF_16_BANK));
+                               break;
+                       case 2:
+                               gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+                                                NUM_BANKS(ADDR_SURF_16_BANK));
+                               break;
+                       case 3:
+                               gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+                                                NUM_BANKS(ADDR_SURF_16_BANK));
+                               break;
+                       case 4:
+                               gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+                                                NUM_BANKS(ADDR_SURF_16_BANK));
+                               break;
+                       case 5:
+                               gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+                                                NUM_BANKS(ADDR_SURF_8_BANK));
+                               break;
+                       case 6:
+                               gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+                                                NUM_BANKS(ADDR_SURF_4_BANK));
+                               break;
+                       case 8:
+                               gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+                                                NUM_BANKS(ADDR_SURF_16_BANK));
+                               break;
+                       case 9:
+                               gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+                                                NUM_BANKS(ADDR_SURF_16_BANK));
+                               break;
+                       case 10:
+                               gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+                                                NUM_BANKS(ADDR_SURF_16_BANK));
+                               break;
+                       case 11:
+                               gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+                                                NUM_BANKS(ADDR_SURF_16_BANK));
+                               break;
+                       case 12:
+                               gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+                                                NUM_BANKS(ADDR_SURF_16_BANK));
+                               break;
+                       case 13:
+                               gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+                                                NUM_BANKS(ADDR_SURF_8_BANK));
+                               break;
+                       case 14:
+                               gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+                                                NUM_BANKS(ADDR_SURF_4_BANK));
+                               break;
+                       default:
+                               gb_tile_moden = 0;
+                               break;
                        }
                        WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
                }
        } else if (num_pipe_configs == 2) {
                for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
                        switch (reg_offset) {
-                               case 0:
-                                       gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                       MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
-                                                       PIPE_CONFIG(ADDR_SURF_P2) |
-                                                       TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
-                                       break;
-                               case 1:
-                                       gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                       MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
-                                                       PIPE_CONFIG(ADDR_SURF_P2) |
-                                                       TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
-                                       break;
-                               case 2:
-                                       gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                       MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
-                                                       PIPE_CONFIG(ADDR_SURF_P2) |
-                                                       TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
-                                       break;
-                               case 3:
-                                       gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                       MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
-                                                       PIPE_CONFIG(ADDR_SURF_P2) |
-                                                       TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
-                                       break;
-                               case 4:
-                                       gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                       MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
-                                                       PIPE_CONFIG(ADDR_SURF_P2) |
-                                                       TILE_SPLIT(split_equal_to_row_size));
-                                       break;
-                               case 5:
-                                       gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-                                                       MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
-                                       break;
-                               case 6:
-                                       gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
-                                                       MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
-                                                       PIPE_CONFIG(ADDR_SURF_P2) |
-                                                       TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
-                                       break;
-                               case 7:
-                                       gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
-                                                       MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
-                                                       PIPE_CONFIG(ADDR_SURF_P2) |
-                                                       TILE_SPLIT(split_equal_to_row_size));
-                                       break;
-                               case 8:
-                                       gb_tile_moden = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
-                                       break;
-                               case 9:
-                                       gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-                                                       MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
-                                       break;
-                               case 10:
-                                       gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                       MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-                                                       PIPE_CONFIG(ADDR_SURF_P2) |
-                                                       SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-                                       break;
-                               case 11:
-                                       gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-                                                       MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-                                                       PIPE_CONFIG(ADDR_SURF_P2) |
-                                                       SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-                                       break;
-                               case 12:
-                                       gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
-                                                       MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
-                                                       PIPE_CONFIG(ADDR_SURF_P2) |
-                                                       SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-                                       break;
-                               case 13:
-                                       gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-                                                       MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
-                                       break;
-                               case 14:
-                                       gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-                                                       MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-                                                       PIPE_CONFIG(ADDR_SURF_P2) |
-                                                       SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-                                       break;
-                               case 16:
-                                       gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-                                                       MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-                                                       PIPE_CONFIG(ADDR_SURF_P2) |
-                                                       SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-                                       break;
-                               case 17:
-                                       gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
-                                                       MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
-                                                       PIPE_CONFIG(ADDR_SURF_P2) |
-                                                       SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-                                       break;
-                               case 27:
-                                       gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-                                                       MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
-                                       break;
-                               case 28:
-                                       gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
-                                                       MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-                                                       PIPE_CONFIG(ADDR_SURF_P2) |
-                                                       SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-                                       break;
-                               case 29:
-                                       gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
-                                                       MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-                                                       PIPE_CONFIG(ADDR_SURF_P2) |
-                                                       SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-                                       break;
-                               case 30:
-                                       gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
-                                                       MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
-                                                       PIPE_CONFIG(ADDR_SURF_P2) |
-                                                       SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
-                                       break;
-                               default:
-                                       gb_tile_moden = 0;
-                                       break;
+                       case 0:
+                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
+                               break;
+                       case 1:
+                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
+                               break;
+                       case 2:
+                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
+                               break;
+                       case 3:
+                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
+                               break;
+                       case 4:
+                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                TILE_SPLIT(split_equal_to_row_size));
+                               break;
+                       case 5:
+                               gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+                               break;
+                       case 6:
+                               gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
+                               break;
+                       case 7:
+                               gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                TILE_SPLIT(split_equal_to_row_size));
+                               break;
+                       case 8:
+                               gb_tile_moden = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
+                               break;
+                       case 9:
+                               gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
+                               break;
+                       case 10:
+                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+                               break;
+                       case 11:
+                               gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+                               break;
+                       case 12:
+                               gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+                               break;
+                       case 13:
+                               gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
+                               break;
+                       case 14:
+                               gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+                               break;
+                       case 16:
+                               gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+                               break;
+                       case 17:
+                               gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+                               break;
+                       case 27:
+                               gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
+                               break;
+                       case 28:
+                               gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+                               break;
+                       case 29:
+                               gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+                               break;
+                       case 30:
+                               gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+                               break;
+                       default:
+                               gb_tile_moden = 0;
+                               break;
                        }
                        rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
                        WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
                }
                for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
                        switch (reg_offset) {
-                               case 0:
-                                       gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-                                                       BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-                                                       MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-                                                       NUM_BANKS(ADDR_SURF_16_BANK));
-                                       break;
-                               case 1:
-                                       gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-                                                       BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-                                                       MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-                                                       NUM_BANKS(ADDR_SURF_16_BANK));
-                                       break;
-                               case 2:
-                                       gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                       BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-                                                       MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-                                                       NUM_BANKS(ADDR_SURF_16_BANK));
-                                       break;
-                               case 3:
-                                       gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                       BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-                                                       MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-                                                       NUM_BANKS(ADDR_SURF_16_BANK));
-                                       break;
-                               case 4:
-                                       gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                       BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-                                                       MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-                                                       NUM_BANKS(ADDR_SURF_16_BANK));
-                                       break;
-                               case 5:
-                                       gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                       BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-                                                       MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-                                                       NUM_BANKS(ADDR_SURF_16_BANK));
-                                       break;
-                               case 6:
-                                       gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                       BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-                                                       MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-                                                       NUM_BANKS(ADDR_SURF_8_BANK));
-                                       break;
-                               case 8:
-                                       gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
-                                                       BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
-                                                       MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-                                                       NUM_BANKS(ADDR_SURF_16_BANK));
-                                       break;
-                               case 9:
-                                       gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
-                                                       BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-                                                       MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-                                                       NUM_BANKS(ADDR_SURF_16_BANK));
-                                       break;
-                               case 10:
-                                       gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-                                                       BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-                                                       MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-                                                       NUM_BANKS(ADDR_SURF_16_BANK));
-                                       break;
-                               case 11:
-                                       gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-                                                       BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-                                                       MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-                                                       NUM_BANKS(ADDR_SURF_16_BANK));
-                                       break;
-                               case 12:
-                                       gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                       BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-                                                       MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-                                                       NUM_BANKS(ADDR_SURF_16_BANK));
-                                       break;
-                               case 13:
-                                       gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                       BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-                                                       MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-                                                       NUM_BANKS(ADDR_SURF_16_BANK));
-                                       break;
-                               case 14:
-                                       gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-                                                       BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-                                                       MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-                                                       NUM_BANKS(ADDR_SURF_8_BANK));
-                                       break;
-                               default:
-                                       gb_tile_moden = 0;
-                                       break;
+                       case 0:
+                               gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+                                                NUM_BANKS(ADDR_SURF_16_BANK));
+                               break;
+                       case 1:
+                               gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+                                                NUM_BANKS(ADDR_SURF_16_BANK));
+                               break;
+                       case 2:
+                               gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+                                                NUM_BANKS(ADDR_SURF_16_BANK));
+                               break;
+                       case 3:
+                               gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+                                                NUM_BANKS(ADDR_SURF_16_BANK));
+                               break;
+                       case 4:
+                               gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+                                                NUM_BANKS(ADDR_SURF_16_BANK));
+                               break;
+                       case 5:
+                               gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+                                                NUM_BANKS(ADDR_SURF_16_BANK));
+                               break;
+                       case 6:
+                               gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+                                                NUM_BANKS(ADDR_SURF_8_BANK));
+                               break;
+                       case 8:
+                               gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+                                                NUM_BANKS(ADDR_SURF_16_BANK));
+                               break;
+                       case 9:
+                               gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+                                                NUM_BANKS(ADDR_SURF_16_BANK));
+                               break;
+                       case 10:
+                               gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+                                                NUM_BANKS(ADDR_SURF_16_BANK));
+                               break;
+                       case 11:
+                               gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+                                                NUM_BANKS(ADDR_SURF_16_BANK));
+                               break;
+                       case 12:
+                               gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+                                                NUM_BANKS(ADDR_SURF_16_BANK));
+                               break;
+                       case 13:
+                               gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+                                                NUM_BANKS(ADDR_SURF_16_BANK));
+                               break;
+                       case 14:
+                               gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+                                                NUM_BANKS(ADDR_SURF_8_BANK));
+                               break;
+                       default:
+                               gb_tile_moden = 0;
+                               break;
                        }
                        WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
                }
@@ -1717,7 +1717,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
  * broadcast to all SEs or SHs (CIK).
  */
 static void cik_select_se_sh(struct radeon_device *rdev,
-               u32 se_num, u32 sh_num)
+                            u32 se_num, u32 sh_num)
 {
        u32 data = INSTANCE_BROADCAST_WRITES;
 
@@ -1763,8 +1763,8 @@ static u32 cik_create_bitmask(u32 bit_width)
  * Returns the disabled RB bitmask.
  */
 static u32 cik_get_rb_disabled(struct radeon_device *rdev,
-               u32 max_rb_num, u32 se_num,
-               u32 sh_per_se)
+                             u32 max_rb_num, u32 se_num,
+                             u32 sh_per_se)
 {
        u32 data, mask;
 
@@ -1793,8 +1793,8 @@ static u32 cik_get_rb_disabled(struct radeon_device *rdev,
  * Configures per-SE/SH RB registers (CIK).
  */
 static void cik_setup_rb(struct radeon_device *rdev,
-               u32 se_num, u32 sh_per_se,
-               u32 max_rb_num)
+                        u32 se_num, u32 sh_per_se,
+                        u32 max_rb_num)
 {
        int i, j;
        u32 data, mask;
@@ -1822,16 +1822,16 @@ static void cik_setup_rb(struct radeon_device *rdev,
                data = 0;
                for (j = 0; j < sh_per_se; j++) {
                        switch (enabled_rbs & 3) {
-                               case 1:
-                                       data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
-                                       break;
-                               case 2:
-                                       data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
-                                       break;
-                               case 3:
-                               default:
-                                       data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
-                                       break;
+                       case 1:
+                               data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
+                               break;
+                       case 2:
+                               data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
+                               break;
+                       case 3:
+                       default:
+                               data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
+                               break;
                        }
                        enabled_rbs >>= 2;
                }
@@ -1857,44 +1857,44 @@ static __unused void cik_gpu_init(struct radeon_device *rdev)
        int i, j;
 
        switch (rdev->family) {
-               case CHIP_BONAIRE:
-                       rdev->config.cik.max_shader_engines = 2;
-                       rdev->config.cik.max_tile_pipes = 4;
-                       rdev->config.cik.max_cu_per_sh = 7;
-                       rdev->config.cik.max_sh_per_se = 1;
-                       rdev->config.cik.max_backends_per_se = 2;
-                       rdev->config.cik.max_texture_channel_caches = 4;
-                       rdev->config.cik.max_gprs = 256;
-                       rdev->config.cik.max_gs_threads = 32;
-                       rdev->config.cik.max_hw_contexts = 8;
-
-                       rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
-                       rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
-                       rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
-                       rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
-                       gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
-                       break;
-               case CHIP_KAVERI:
-                       /* TODO */
-                       break;
-               case CHIP_KABINI:
-               default:
-                       rdev->config.cik.max_shader_engines = 1;
-                       rdev->config.cik.max_tile_pipes = 2;
-                       rdev->config.cik.max_cu_per_sh = 2;
-                       rdev->config.cik.max_sh_per_se = 1;
-                       rdev->config.cik.max_backends_per_se = 1;
-                       rdev->config.cik.max_texture_channel_caches = 2;
-                       rdev->config.cik.max_gprs = 256;
-                       rdev->config.cik.max_gs_threads = 16;
-                       rdev->config.cik.max_hw_contexts = 8;
-
-                       rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
-                       rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
-                       rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
-                       rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
-                       gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
-                       break;
+       case CHIP_BONAIRE:
+               rdev->config.cik.max_shader_engines = 2;
+               rdev->config.cik.max_tile_pipes = 4;
+               rdev->config.cik.max_cu_per_sh = 7;
+               rdev->config.cik.max_sh_per_se = 1;
+               rdev->config.cik.max_backends_per_se = 2;
+               rdev->config.cik.max_texture_channel_caches = 4;
+               rdev->config.cik.max_gprs = 256;
+               rdev->config.cik.max_gs_threads = 32;
+               rdev->config.cik.max_hw_contexts = 8;
+
+               rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
+               rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
+               rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
+               rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
+               gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
+               break;
+       case CHIP_KAVERI:
+               /* TODO */
+               break;
+       case CHIP_KABINI:
+       default:
+               rdev->config.cik.max_shader_engines = 1;
+               rdev->config.cik.max_tile_pipes = 2;
+               rdev->config.cik.max_cu_per_sh = 2;
+               rdev->config.cik.max_sh_per_se = 1;
+               rdev->config.cik.max_backends_per_se = 1;
+               rdev->config.cik.max_texture_channel_caches = 2;
+               rdev->config.cik.max_gprs = 256;
+               rdev->config.cik.max_gs_threads = 16;
+               rdev->config.cik.max_hw_contexts = 8;
+
+               rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
+               rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
+               rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
+               rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
+               gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
+               break;
        }
 
        /* Initialize HDP */
@@ -1927,16 +1927,16 @@ static __unused void cik_gpu_init(struct radeon_device *rdev)
        /* fix up row size */
        gb_addr_config &= ~ROW_SIZE_MASK;
        switch (rdev->config.cik.mem_row_size_in_kb) {
-               case 1:
-               default:
-                       gb_addr_config |= ROW_SIZE(0);
-                       break;
-               case 2:
-                       gb_addr_config |= ROW_SIZE(1);
-                       break;
-               case 4:
-                       gb_addr_config |= ROW_SIZE(2);
-                       break;
+       case 1:
+       default:
+               gb_addr_config |= ROW_SIZE(0);
+               break;
+       case 2:
+               gb_addr_config |= ROW_SIZE(1);
+               break;
+       case 4:
+               gb_addr_config |= ROW_SIZE(2);
+               break;
        }
 
        /* setup tiling info dword.  gb_addr_config is not adequate since it does
@@ -1948,20 +1948,20 @@ static __unused void cik_gpu_init(struct radeon_device *rdev)
         */
        rdev->config.cik.tile_config = 0;
        switch (rdev->config.cik.num_tile_pipes) {
-               case 1:
-                       rdev->config.cik.tile_config |= (0 << 0);
-                       break;
-               case 2:
-                       rdev->config.cik.tile_config |= (1 << 0);
-                       break;
-               case 4:
-                       rdev->config.cik.tile_config |= (2 << 0);
-                       break;
-               case 8:
-               default:
-                       /* XXX what about 12? */
-                       rdev->config.cik.tile_config |= (3 << 0);
-                       break;
+       case 1:
+               rdev->config.cik.tile_config |= (0 << 0);
+               break;
+       case 2:
+               rdev->config.cik.tile_config |= (1 << 0);
+               break;
+       case 4:
+               rdev->config.cik.tile_config |= (2 << 0);
+               break;
+       case 8:
+       default:
+               /* XXX what about 12? */
+               rdev->config.cik.tile_config |= (3 << 0);
+               break;
        }
        if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
                rdev->config.cik.tile_config |= 1 << 4;
@@ -1984,8 +1984,8 @@ static __unused void cik_gpu_init(struct radeon_device *rdev)
        cik_tiling_mode_table_init(rdev);
 
        cik_setup_rb(rdev, rdev->config.cik.max_shader_engines,
-                       rdev->config.cik.max_sh_per_se,
-                       rdev->config.cik.max_backends_per_se);
+                    rdev->config.cik.max_sh_per_se,
+                    rdev->config.cik.max_backends_per_se);
 
        /* set HW defaults for 3D engine */
        WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
@@ -2017,9 +2017,9 @@ static __unused void cik_gpu_init(struct radeon_device *rdev)
        WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
 
        WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_frontend) |
-                               SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_backend) |
-                               SC_HIZ_TILE_FIFO_SIZE(rdev->config.cik.sc_hiz_tile_fifo_size) |
-                               SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cik.sc_earlyz_tile_fifo_size)));
+                                SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_backend) |
+                                SC_HIZ_TILE_FIFO_SIZE(rdev->config.cik.sc_hiz_tile_fifo_size) |
+                                SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cik.sc_earlyz_tile_fifo_size)));
 
        WREG32(VGT_NUM_INSTANCES, 1);
 
@@ -2028,10 +2028,10 @@ static __unused void cik_gpu_init(struct radeon_device *rdev)
        WREG32(SQ_CONFIG, 0);
 
        WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
-                               FORCE_EOV_MAX_REZ_CNT(255)));
+                                         FORCE_EOV_MAX_REZ_CNT(255)));
 
        WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
-                       AUTO_INVLD_EN(ES_AND_GS_AUTO));
+              AUTO_INVLD_EN(ES_AND_GS_AUTO));
 
        WREG32(VGT_GS_VERTEX_REUSE, 16);
        WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
@@ -2046,7 +2046,7 @@ static __unused void cik_gpu_init(struct radeon_device *rdev)
        WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
        WREG32(PA_SC_ENHANCE, ENABLE_PA_SC_OUT_OF_ORDER);
 
-       DRM_UDELAY(50);
+       udelay(50);
 }
 
 /*
@@ -2375,7 +2375,7 @@ static void cik_cp_gfx_enable(struct radeon_device *rdev, bool enable)
                WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
                rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
        }
-       DRM_UDELAY(50);
+       udelay(50);
 }
 
 /**
@@ -2552,7 +2552,7 @@ static int cik_cp_gfx_resume(struct radeon_device *rdev)
        if (!rdev->wb.enabled)
                tmp |= RB_NO_UPDATE;
 
-       DRM_MDELAY(1);
+       mdelay(1);
        WREG32(CP_RB0_CNTL, tmp);
 
        rb_addr = ring->gpu_addr >> 8;
@@ -2635,7 +2635,7 @@ static void cik_cp_compute_enable(struct radeon_device *rdev, bool enable)
                WREG32(CP_MEC_CNTL, 0);
        else
                WREG32(CP_MEC_CNTL, (MEC_ME1_HALT | MEC_ME2_HALT));
-       DRM_UDELAY(50);
+       udelay(50);
 }
 
 /**
@@ -3002,7 +3002,7 @@ static int cik_cp_compute_resume(struct radeon_device *rdev)
                        for (i = 0; i < rdev->usec_timeout; i++) {
                                if (!(RREG32(CP_HQD_ACTIVE) & 1))
                                        break;
-                               DRM_UDELAY(1);
+                               udelay(1);
                        }
                        WREG32(CP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request);
                        WREG32(CP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr);
@@ -3148,7 +3148,7 @@ static int cik_cp_resume(struct radeon_device *rdev)
        /* Reset all cp blocks */
        WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
        RREG32(GRBM_SOFT_RESET);
-       DRM_MDELAY(15);
+       mdelay(15);
        WREG32(GRBM_SOFT_RESET, 0);
        RREG32(GRBM_SOFT_RESET);
 
@@ -3501,7 +3501,7 @@ static __unused int cik_sdma_resume(struct radeon_device *rdev)
        /* Reset dma */
        WREG32(SRBM_SOFT_RESET, SOFT_RESET_SDMA | SOFT_RESET_SDMA1);
        RREG32(SRBM_SOFT_RESET);
-       DRM_UDELAY(50);
+       udelay(50);
        WREG32(SRBM_SOFT_RESET, 0);
        RREG32(SRBM_SOFT_RESET);
 
@@ -3742,21 +3742,21 @@ int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
 static void cik_print_gpu_status_regs(struct radeon_device *rdev)
 {
        dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
-                       RREG32(GRBM_STATUS));
+               RREG32(GRBM_STATUS));
        dev_info(rdev->dev, "  GRBM_STATUS2=0x%08X\n",
-                       RREG32(GRBM_STATUS2));
+               RREG32(GRBM_STATUS2));
        dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
-                       RREG32(GRBM_STATUS_SE0));
+               RREG32(GRBM_STATUS_SE0));
        dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
-                       RREG32(GRBM_STATUS_SE1));
+               RREG32(GRBM_STATUS_SE1));
        dev_info(rdev->dev, "  GRBM_STATUS_SE2=0x%08X\n",
-                       RREG32(GRBM_STATUS_SE2));
+               RREG32(GRBM_STATUS_SE2));
        dev_info(rdev->dev, "  GRBM_STATUS_SE3=0x%08X\n",
-                       RREG32(GRBM_STATUS_SE3));
+               RREG32(GRBM_STATUS_SE3));
        dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
-                       RREG32(SRBM_STATUS));
+               RREG32(SRBM_STATUS));
        dev_info(rdev->dev, "  SRBM_STATUS2=0x%08X\n",
-                       RREG32(SRBM_STATUS2));
+               RREG32(SRBM_STATUS2));
        dev_info(rdev->dev, "  SDMA0_STATUS_REG   = 0x%08X\n",
                RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET));
        dev_info(rdev->dev, "  SDMA1_STATUS_REG   = 0x%08X\n",
@@ -3911,6 +3911,7 @@ static void cik_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
        if (evergreen_mc_wait_for_idle(rdev)) {
                dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
        }
+
        if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP))
                grbm_soft_reset = SOFT_RESET_CP | SOFT_RESET_GFX;
 
@@ -3956,7 +3957,7 @@ static void cik_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
                WREG32(GRBM_SOFT_RESET, tmp);
                tmp = RREG32(GRBM_SOFT_RESET);
 
-               DRM_UDELAY(50);
+               udelay(50);
 
                tmp &= ~grbm_soft_reset;
                WREG32(GRBM_SOFT_RESET, tmp);
@@ -3970,7 +3971,7 @@ static void cik_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
                WREG32(SRBM_SOFT_RESET, tmp);
                tmp = RREG32(SRBM_SOFT_RESET);
 
-               DRM_UDELAY(50);
+               udelay(50);
 
                tmp &= ~srbm_soft_reset;
                WREG32(SRBM_SOFT_RESET, tmp);
@@ -3978,10 +3979,10 @@ static void cik_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
        }
 
        /* Wait a little for things to settle down */
-       DRM_UDELAY(50);
+       udelay(50);
 
        evergreen_mc_resume(rdev, &save);
-       DRM_UDELAY(50);
+       udelay(50);
 
        cik_print_gpu_status_regs(rdev);
 }
@@ -4099,11 +4100,11 @@ static __unused void cik_mc_program(struct radeon_device *rdev)
        WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
        /* Update configuration */
        WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
-                       rdev->mc.vram_start >> 12);
+              rdev->mc.vram_start >> 12);
        WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
-                       rdev->mc.vram_end >> 12);
+              rdev->mc.vram_end >> 12);
        WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
-                       rdev->vram_scratch.gpu_addr >> 12);
+              rdev->vram_scratch.gpu_addr >> 12);
        tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
        tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
        WREG32(MC_VM_FB_LOCATION, tmp);
@@ -4147,34 +4148,34 @@ static __unused int cik_mc_init(struct radeon_device *rdev)
        }
        tmp = RREG32(MC_SHARED_CHMAP);
        switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
-               case 0:
-               default:
-                       numchan = 1;
-                       break;
-               case 1:
-                       numchan = 2;
-                       break;
-               case 2:
-                       numchan = 4;
-                       break;
-               case 3:
-                       numchan = 8;
-                       break;
-               case 4:
-                       numchan = 3;
-                       break;
-               case 5:
-                       numchan = 6;
-                       break;
-               case 6:
-                       numchan = 10;
-                       break;
-               case 7:
-                       numchan = 12;
-                       break;
-               case 8:
-                       numchan = 16;
-                       break;
+       case 0:
+       default:
+               numchan = 1;
+               break;
+       case 1:
+               numchan = 2;
+               break;
+       case 2:
+               numchan = 4;
+               break;
+       case 3:
+               numchan = 8;
+               break;
+       case 4:
+               numchan = 3;
+               break;
+       case 5:
+               numchan = 6;
+               break;
+       case 6:
+               numchan = 10;
+               break;
+       case 7:
+               numchan = 12;
+               break;
+       case 8:
+               numchan = 16;
+               break;
        }
        rdev->mc.vram_width = numchan * chansize;
        /* Could aper size report 0 ? */
@@ -4767,7 +4768,7 @@ static void cik_rlc_stop(struct radeon_device *rdev)
                        for (k = 0; k < rdev->usec_timeout; k++) {
                                if (RREG32(RLC_SERDES_CU_MASTER_BUSY) == 0)
                                        break;
-                               DRM_UDELAY(1);
+                               udelay(1);
                        }
                }
        }
@@ -4777,7 +4778,7 @@ static void cik_rlc_stop(struct radeon_device *rdev)
        for (k = 0; k < rdev->usec_timeout; k++) {
                if ((RREG32(RLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
                        break;
-               DRM_UDELAY(1);
+               udelay(1);
        }
 }
 
@@ -4798,7 +4799,7 @@ static void cik_rlc_start(struct radeon_device *rdev)
        tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
        WREG32(CP_INT_CNTL_RING0, tmp);
 
-       DRM_UDELAY(50);
+       udelay(50);
 }
 
 /**
@@ -4836,10 +4837,10 @@ static __unused int cik_rlc_resume(struct radeon_device *rdev)
 
        WREG32(GRBM_SOFT_RESET, SOFT_RESET_RLC);
        RREG32(GRBM_SOFT_RESET);
-       DRM_UDELAY(50);
+       udelay(50);
        WREG32(GRBM_SOFT_RESET, 0);
        RREG32(GRBM_SOFT_RESET);
-       DRM_UDELAY(50);
+       udelay(50);
 
        WREG32(RLC_LB_CNTR_INIT, 0);
        WREG32(RLC_LB_CNTR_MAX, 0x00008000);
@@ -5411,7 +5412,7 @@ static void cik_irq_disable(struct radeon_device *rdev)
 {
        cik_disable_interrupts(rdev);
        /* Wait and acknowledge irq */
-       DRM_MDELAY(1);
+       mdelay(1);
        cik_irq_ack(rdev);
        cik_disable_interrupt_state(rdev);
 }
@@ -5539,7 +5540,7 @@ restart_ih:
        DRM_DEBUG("cik_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
 
        /* Order reading of wptr vs. reading of IH ring data */
-       cpu_lfence();
+       rmb();
 
        /* display interrupts */
        cik_irq_ack(rdev);
@@ -6952,7 +6953,7 @@ static int cik_set_uvd_clock(struct radeon_device *rdev, u32 clock,
        for (i = 0; i < 100; i++) {
                if (RREG32_SMC(status_reg) & DCLK_STATUS)
                        break;
-               DRM_MDELAY(10);
+               mdelay(10);
        }
        if (i == 100)
                return -ETIMEDOUT;
index 41ffdb1..3f87c61 100644 (file)
@@ -68,7 +68,7 @@ static void cypress_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev,
 
                                tmp |= LC_CLR_FAILED_SPD_CHANGE_CNT;
                                WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
-                               DRM_UDELAY(10);
+                               udelay(10);
                                tmp &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
                                WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
                        }
@@ -111,7 +111,7 @@ static int cypress_enter_ulp_state(struct radeon_device *rdev)
        WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower),
                 ~HOST_SMC_MSG_MASK);
 
-       DRM_UDELAY(7000);
+       udelay(7000);
 
        return 0;
 }
@@ -304,7 +304,7 @@ static int cypress_pcie_performance_request(struct radeon_device *rdev,
        struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
        u32 tmp;
 
-       DRM_UDELAY(10);
+       udelay(10);
        tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
        if ((perf_req == PCIE_PERF_REQ_PECI_GEN1) && (tmp & LC_CURRENT_DATA_RATE))
                return 0;
@@ -1107,7 +1107,7 @@ static void cypress_wait_for_mc_sequencer(struct radeon_device *rdev, u8 value)
                for (j = 0; j < rdev->usec_timeout; j++) {
                        if (((RREG32(MC_SEQ_CG) & CG_SEQ_RESP_MASK) >> CG_SEQ_RESP_SHIFT) == value)
                                break;
-                       DRM_UDELAY(1);
+                       udelay(1);
                }
        }
 }
@@ -1151,7 +1151,7 @@ static void cypress_force_mc_use_s1(struct radeon_device *rdev,
        for (i = 0; i < rdev->usec_timeout; i++) {
                if (RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE)
                        break;
-               DRM_UDELAY(1);
+               udelay(1);
        }
 
        mc_seq_cg &= ~CG_SEQ_REQ_MASK;
@@ -1209,7 +1209,7 @@ static void cypress_force_mc_use_s0(struct radeon_device *rdev,
        for (i = 0; i < rdev->usec_timeout; i++) {
                if (!(RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE))
                        break;
-               DRM_UDELAY(1);
+               udelay(1);
        }
 
        mc_seq_cg &= ~CG_SEQ_REQ_MASK;
index f7fc7a8..2081483 100644 (file)
@@ -23,7 +23,7 @@
  *
  * $FreeBSD: head/sys/dev/drm2/radeon/evergreen.c 254885 2013-08-25 19:37:15Z dumbbell $
  */
-
+#include <linux/firmware.h>
 #include <drm/drmP.h>
 #include "radeon.h"
 #include "radeon_asic.h"
@@ -1040,7 +1040,7 @@ static int sumo_set_uvd_clock(struct radeon_device *rdev, u32 clock,
        for (i = 0; i < 100; i++) {
                if (RREG32(status_reg) & DCLK_STATUS)
                        break;
-               DRM_MDELAY(10);
+               mdelay(10);
        }
        if (i == 100)
                return -ETIMEDOUT;
@@ -1107,7 +1107,7 @@ int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
        /* deassert UPLL_RESET */
        WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
 
-       DRM_MDELAY(1);
+       mdelay(1);
 
        r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
        if (r)
@@ -1136,12 +1136,12 @@ int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
                ~(UPLL_PDIV_A_MASK | UPLL_PDIV_B_MASK));
 
        /* give the PLL some time to settle */
-       DRM_MDELAY(15);
+       mdelay(15);
 
        /* deassert PLL_RESET */
        WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
 
-       DRM_MDELAY(15);
+       mdelay(15);
 
        /* switch from bypass mode to normal mode */
        WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
@@ -1155,7 +1155,7 @@ int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
                VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
                ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
 
-       DRM_MDELAY(100);
+       mdelay(100);
 
        return 0;
 }
@@ -1310,7 +1310,7 @@ u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
        for (i = 0; i < rdev->usec_timeout; i++) {
                if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)
                        break;
-               DRM_UDELAY(1);
+               udelay(1);
        }
        DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 
@@ -2322,7 +2322,7 @@ int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
                tmp = RREG32(SRBM_STATUS) & 0x1F00;
                if (!tmp)
                        return 0;
-               DRM_UDELAY(1);
+               udelay(1);
        }
        return -1;
 }
@@ -2343,13 +2343,13 @@ void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
                tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
                tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
                if (tmp == 2) {
-                       DRM_ERROR("[drm] r600 flush TLB failed\n");
+                       printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
                        return;
                }
                if (tmp) {
                        return;
                }
-               DRM_UDELAY(1);
+               udelay(1);
        }
 }
 
@@ -2511,7 +2511,7 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
                        for (j = 0; j < rdev->usec_timeout; j++) {
                                if (radeon_get_vblank_counter(rdev, i) != frame_count)
                                        break;
-                               DRM_UDELAY(1);
+                               udelay(1);
                        }
 
                        /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
@@ -2538,7 +2538,7 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
                WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
        }
        /* wait for the MC to settle */
-       DRM_UDELAY(100);
+       udelay(100);
 
        /* lock double buffered regs */
        for (i = 0; i < rdev->num_crtc; i++) {
@@ -2601,7 +2601,7 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s
                                tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
                                if ((tmp & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) == 0)
                                        break;
-                               DRM_UDELAY(1);
+                               udelay(1);
                        }
                }
        }
@@ -2633,14 +2633,14 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s
                        for (j = 0; j < rdev->usec_timeout; j++) {
                                if (radeon_get_vblank_counter(rdev, i) != frame_count)
                                        break;
-                               DRM_UDELAY(1);
+                               udelay(1);
                        }
                }
        }
        if (!ASIC_IS_NODCE(rdev)) {
                /* Unlock vga access */
                WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
-               DRM_MDELAY(1);
+               mdelay(1);
                WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
        }
 }
@@ -2873,7 +2873,7 @@ static int evergreen_cp_resume(struct radeon_device *rdev)
                                 SOFT_RESET_SPI |
                                 SOFT_RESET_SX));
        RREG32(GRBM_SOFT_RESET);
-       DRM_MDELAY(15);
+       mdelay(15);
        WREG32(GRBM_SOFT_RESET, 0);
        RREG32(GRBM_SOFT_RESET);
 
@@ -2909,7 +2909,7 @@ static int evergreen_cp_resume(struct radeon_device *rdev)
                WREG32(SCRATCH_UMSK, 0);
        }
 
-       DRM_MDELAY(1);
+       mdelay(1);
        WREG32(CP_RB_CNTL, tmp);
 
        WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
@@ -3490,7 +3490,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
 
        WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
 
-       DRM_UDELAY(50);
+       udelay(50);
 
 }
 
@@ -3604,7 +3604,7 @@ bool evergreen_is_display_hung(struct radeon_device *rdev)
                }
                if (crtc_hung == 0)
                        return false;
-               DRM_UDELAY(100);
+               udelay(100);
        }
 
        return true;
@@ -3702,7 +3702,7 @@ static void evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
                WREG32(DMA_RB_CNTL, tmp);
        }
 
-       DRM_UDELAY(50);
+       udelay(50);
 
        evergreen_mc_stop(rdev, &save);
        if (evergreen_mc_wait_for_idle(rdev)) {
@@ -3763,7 +3763,7 @@ static void evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
                WREG32(GRBM_SOFT_RESET, tmp);
                tmp = RREG32(GRBM_SOFT_RESET);
 
-               DRM_UDELAY(50);
+               udelay(50);
 
                tmp &= ~grbm_soft_reset;
                WREG32(GRBM_SOFT_RESET, tmp);
@@ -3777,7 +3777,7 @@ static void evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
                WREG32(SRBM_SOFT_RESET, tmp);
                tmp = RREG32(SRBM_SOFT_RESET);
 
-               DRM_UDELAY(50);
+               udelay(50);
 
                tmp &= ~srbm_soft_reset;
                WREG32(SRBM_SOFT_RESET, tmp);
@@ -3785,10 +3785,10 @@ static void evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
        }
 
        /* Wait a little for things to settle down */
-       DRM_UDELAY(50);
+       udelay(50);
 
        evergreen_mc_resume(rdev, &save);
-       DRM_UDELAY(50);
+       udelay(50);
 
        evergreen_print_gpu_status_regs(rdev);
 }
@@ -4545,7 +4545,7 @@ static void evergreen_irq_disable(struct radeon_device *rdev)
 {
        r600_disable_interrupts(rdev);
        /* Wait and acknowledge irq */
-       DRM_MDELAY(1);
+       mdelay(1);
        evergreen_irq_ack(rdev);
        evergreen_disable_interrupt_state(rdev);
 }
@@ -4605,7 +4605,7 @@ restart_ih:
        DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
 
        /* Order reading of wptr vs. reading of IH ring data */
-       cpu_lfence();
+       rmb();
 
        /* display interrupts */
        evergreen_irq_ack(rdev);
@@ -4624,7 +4624,7 @@ restart_ih:
                                        if (rdev->irq.crtc_vblank_int[0]) {
                                                drm_handle_vblank(rdev->ddev, 0);
                                                rdev->pm.vblank_sync = true;
-                                               DRM_WAKEUP(&rdev->irq.vblank_queue);
+                                               wake_up(&rdev->irq.vblank_queue);
                                        }
                                        if (atomic_read(&rdev->irq.pflip[0]))
                                                radeon_crtc_handle_flip(rdev, 0);
@@ -4650,7 +4650,7 @@ restart_ih:
                                        if (rdev->irq.crtc_vblank_int[1]) {
                                                drm_handle_vblank(rdev->ddev, 1);
                                                rdev->pm.vblank_sync = true;
-                                               DRM_WAKEUP(&rdev->irq.vblank_queue);
+                                               wake_up(&rdev->irq.vblank_queue);
                                        }
                                        if (atomic_read(&rdev->irq.pflip[1]))
                                                radeon_crtc_handle_flip(rdev, 1);
@@ -4676,7 +4676,7 @@ restart_ih:
                                        if (rdev->irq.crtc_vblank_int[2]) {
                                                drm_handle_vblank(rdev->ddev, 2);
                                                rdev->pm.vblank_sync = true;
-                                               DRM_WAKEUP(&rdev->irq.vblank_queue);
+                                               wake_up(&rdev->irq.vblank_queue);
                                        }
                                        if (atomic_read(&rdev->irq.pflip[2]))
                                                radeon_crtc_handle_flip(rdev, 2);
@@ -4702,7 +4702,7 @@ restart_ih:
                                        if (rdev->irq.crtc_vblank_int[3]) {
                                                drm_handle_vblank(rdev->ddev, 3);
                                                rdev->pm.vblank_sync = true;
-                                               DRM_WAKEUP(&rdev->irq.vblank_queue);
+                                               wake_up(&rdev->irq.vblank_queue);
                                        }
                                        if (atomic_read(&rdev->irq.pflip[3]))
                                                radeon_crtc_handle_flip(rdev, 3);
@@ -4728,7 +4728,7 @@ restart_ih:
                                        if (rdev->irq.crtc_vblank_int[4]) {
                                                drm_handle_vblank(rdev->ddev, 4);
                                                rdev->pm.vblank_sync = true;
-                                               DRM_WAKEUP(&rdev->irq.vblank_queue);
+                                               wake_up(&rdev->irq.vblank_queue);
                                        }
                                        if (atomic_read(&rdev->irq.pflip[4]))
                                                radeon_crtc_handle_flip(rdev, 4);
@@ -4754,7 +4754,7 @@ restart_ih:
                                        if (rdev->irq.crtc_vblank_int[5]) {
                                                drm_handle_vblank(rdev->ddev, 5);
                                                rdev->pm.vblank_sync = true;
-                                               DRM_WAKEUP(&rdev->irq.vblank_queue);
+                                               wake_up(&rdev->irq.vblank_queue);
                                        }
                                        if (atomic_read(&rdev->irq.pflip[5]))
                                                radeon_crtc_handle_flip(rdev, 5);
@@ -4948,7 +4948,6 @@ restart_ih:
                taskqueue_enqueue(rdev->tq, &rdev->audio_work);
        if (queue_thermal && rdev->pm.dpm_enabled)
                taskqueue_enqueue(rdev->tq, &rdev->pm.dpm.thermal.work);
-
        rdev->ih.rptr = rptr;
        WREG32(IH_RB_RPTR, rdev->ih.rptr);
        atomic_set(&rdev->ih.lock, 0);
@@ -5444,7 +5443,7 @@ void evergreen_fini(struct radeon_device *rdev)
                ni_fini_microcode(rdev);
        else
                r600_fini_microcode(rdev);
-       drm_free(rdev->bios, M_DRM);
+       kfree(rdev->bios);
        rdev->bios = NULL;
 }
 
index 1b22ec3..9297b81 100644 (file)
@@ -43,7 +43,7 @@ set_render_target(struct radeon_device *rdev, int format,
        u32 cb_color_info;
        int pitch, slice;
 
-       h = roundup2(h, 8);
+       h = ALIGN(h, 8);
        if (h < 8)
                h = 8;
 
@@ -596,7 +596,7 @@ set_default_state(struct radeon_device *rdev)
        radeon_ring_write(ring, 1);
 
        /* emit an IB pointing at default state */
-       dwords = roundup2(rdev->r600_blit.state_len, 0x10);
+       dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
        gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
        radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
        radeon_ring_write(ring, gpu_addr & 0xFFFFFFFC);
@@ -648,21 +648,21 @@ int evergreen_blit_init(struct radeon_device *rdev)
        }
 
        obj_size = dwords * 4;
-       obj_size = roundup2(obj_size, 256);
+       obj_size = ALIGN(obj_size, 256);
 
        rdev->r600_blit.vs_offset = obj_size;
        if (rdev->family < CHIP_CAYMAN)
                obj_size += evergreen_vs_size * 4;
        else
                obj_size += cayman_vs_size * 4;
-       obj_size = roundup2(obj_size, 256);
+       obj_size = ALIGN(obj_size, 256);
 
        rdev->r600_blit.ps_offset = obj_size;
        if (rdev->family < CHIP_CAYMAN)
                obj_size += evergreen_ps_size * 4;
        else
                obj_size += cayman_ps_size * 4;
-       obj_size = roundup2(obj_size, 256);
+       obj_size = ALIGN(obj_size, 256);
 
        /* pin copy shader into vram if not already initialized */
        if (!rdev->r600_blit.shader_obj) {
index 39a4b02..f85c0af 100644 (file)
@@ -24,7 +24,9 @@
  *     Alex Deucher <alexander.deucher@amd.com>
  */
 
-#include <drm/drmP.h>
+#include <linux/bug.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
 
 /*
  * evergreen cards need to use the 3D engine to blit data which requires
@@ -350,6 +352,6 @@ const u32 evergreen_ps[] =
        0x00000000,
 };
 
-const u32 evergreen_ps_size = DRM_ARRAY_SIZE(evergreen_ps);
-const u32 evergreen_vs_size = DRM_ARRAY_SIZE(evergreen_vs);
-const u32 evergreen_default_size = DRM_ARRAY_SIZE(evergreen_default_state);
+const u32 evergreen_ps_size = ARRAY_SIZE(evergreen_ps);
+const u32 evergreen_vs_size = ARRAY_SIZE(evergreen_vs);
+const u32 evergreen_default_size = ARRAY_SIZE(evergreen_default_state);
index 03c4db8..79bd1a4 100644 (file)
@@ -504,9 +504,9 @@ static int evergreen_cs_track_validate_htile(struct radeon_cs_parser *p,
 
        if (G_028ABC_LINEAR(track->htile_surface)) {
                /* pitch must be 16 htiles aligned == 16 * 8 pixel aligned */
-               nbx = roundup(nbx, 16 * 8);
+               nbx = round_up(nbx, 16 * 8);
                /* height is npipes htiles aligned == npipes * 8 pixel aligned */
-               nby = roundup(nby, track->npipes * 8);
+               nby = round_up(nby, track->npipes * 8);
        } else {
                /* always assume 8x8 htile */
                /* align is htile align * 8, htile align vary according to
@@ -515,23 +515,23 @@ static int evergreen_cs_track_validate_htile(struct radeon_cs_parser *p,
                switch (track->npipes) {
                case 8:
                        /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
-                       nbx = roundup(nbx, 64 * 8);
-                       nby = roundup(nby, 64 * 8);
+                       nbx = round_up(nbx, 64 * 8);
+                       nby = round_up(nby, 64 * 8);
                        break;
                case 4:
                        /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
-                       nbx = roundup(nbx, 64 * 8);
-                       nby = roundup(nby, 32 * 8);
+                       nbx = round_up(nbx, 64 * 8);
+                       nby = round_up(nby, 32 * 8);
                        break;
                case 2:
                        /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
-                       nbx = roundup(nbx, 32 * 8);
-                       nby = roundup(nby, 32 * 8);
+                       nbx = round_up(nbx, 32 * 8);
+                       nby = round_up(nby, 32 * 8);
                        break;
                case 1:
                        /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
-                       nbx = roundup(nbx, 32 * 8);
-                       nby = roundup(nby, 16 * 8);
+                       nbx = round_up(nbx, 32 * 8);
+                       nby = round_up(nby, 16 * 8);
                        break;
                default:
                        dev_warn(p->dev, "%s:%d invalid num pipes %d\n",
@@ -820,7 +820,7 @@ static int evergreen_cs_track_validate_texture(struct radeon_cs_parser *p,
 
        /* align height */
        evergreen_surface_check(p, &surf, NULL);
-       surf.nby = roundup(surf.nby, surf.halign);
+       surf.nby = ALIGN(surf.nby, surf.halign);
 
        r = evergreen_surface_check(p, &surf, "texture");
        if (r) {
@@ -893,8 +893,8 @@ static int evergreen_cs_track_validate_texture(struct radeon_cs_parser *p,
                                 __func__, __LINE__, surf.mode);
                        return -EINVAL;
                }
-               surf.nbx = roundup(surf.nbx, surf.palign);
-               surf.nby = roundup(surf.nby, surf.halign);
+               surf.nbx = ALIGN(surf.nbx, surf.palign);
+               surf.nby = ALIGN(surf.nby, surf.halign);
 
                r = evergreen_surface_check(p, &surf, "mipmap");
                if (r) {
@@ -1055,7 +1055,7 @@ static int evergreen_packet0_check(struct radeon_cs_parser *p,
                }
                break;
        default:
-               DRM_ERROR("Forbidden register 0x%04X in cs at %d\n",
+               printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
                       reg, idx);
                return -EINVAL;
        }
@@ -1099,9 +1099,9 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
        int r;
 
        if (p->rdev->family >= CHIP_CAYMAN)
-               last_reg = DRM_ARRAY_SIZE(cayman_reg_safe_bm);
+               last_reg = ARRAY_SIZE(cayman_reg_safe_bm);
        else
-               last_reg = DRM_ARRAY_SIZE(evergreen_reg_safe_bm);
+               last_reg = ARRAY_SIZE(evergreen_reg_safe_bm);
 
        i = (reg >> 7);
        if (i >= last_reg) {
@@ -1767,9 +1767,9 @@ static bool evergreen_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
        u32 last_reg, m, i;
 
        if (p->rdev->family >= CHIP_CAYMAN)
-               last_reg = DRM_ARRAY_SIZE(cayman_reg_safe_bm);
+               last_reg = ARRAY_SIZE(cayman_reg_safe_bm);
        else
-               last_reg = DRM_ARRAY_SIZE(evergreen_reg_safe_bm);
+               last_reg = ARRAY_SIZE(evergreen_reg_safe_bm);
 
        i = (reg >> 7);
        if (i >= last_reg) {
@@ -2569,8 +2569,7 @@ int evergreen_cs_parse(struct radeon_cs_parser *p)
 
        if (p->track == NULL) {
                /* initialize tracker, we are in kms */
-               track = kmalloc(sizeof(*track), M_DRM,
-                               M_ZERO | M_WAITOK);
+               track = kzalloc(sizeof(*track), GFP_KERNEL);
                if (track == NULL)
                        return -ENOMEM;
                evergreen_cs_track_init(track);
@@ -2636,7 +2635,7 @@ int evergreen_cs_parse(struct radeon_cs_parser *p)
        do {
                r = radeon_cs_packet_parse(p, &pkt, p->idx);
                if (r) {
-                       drm_free(p->track, M_DRM);
+                       kfree(p->track);
                        p->track = NULL;
                        return r;
                }
@@ -2652,12 +2651,12 @@ int evergreen_cs_parse(struct radeon_cs_parser *p)
                        break;
                default:
                        DRM_ERROR("Unknown packet type %d !\n", pkt.type);
-                       drm_free(p->track, M_DRM);
+                       kfree(p->track);
                        p->track = NULL;
                        return -EINVAL;
                }
                if (r) {
-                       drm_free(p->track, M_DRM);
+                       kfree(p->track);
                        p->track = NULL;
                        return r;
                }
@@ -2668,7 +2667,7 @@ int evergreen_cs_parse(struct radeon_cs_parser *p)
                mdelay(1);
        }
 #endif
-       drm_free(p->track, M_DRM);
+       kfree(p->track);
        p->track = NULL;
        return 0;
 }
index c45f862..39d4ac5 100644 (file)
@@ -128,7 +128,6 @@ static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder,
        struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
        uint32_t offset = dig->afmt->offset;
        uint8_t *frame = (uint8_t*)buffer + 3;
-
        uint8_t *header = buffer;
 
        WREG32(AFMT_AVI_INFO0 + offset,
index 45f6c36..4ca80d0 100644 (file)
@@ -20,7 +20,6 @@
  * OTHER DEALINGS IN THE SOFTWARE.
  *
  * Authors: Alex Deucher
- * $FreeBSD: head/sys/dev/drm2/radeon/ni.c 254885 2013-08-25 19:37:15Z dumbbell $
  */
 #include <linux/firmware.h>
 #include <linux/module.h>
@@ -185,6 +184,7 @@ MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
 MODULE_FIRMWARE("radeon/ARUBA_me.bin");
 MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");
 
+
 static const u32 cayman_golden_registers2[] =
 {
        0x3e5c, 0xffffffff, 0x00000000,
@@ -656,7 +656,7 @@ int ni_mc_load_microcode(struct radeon_device *rdev)
                for (i = 0; i < rdev->usec_timeout; i++) {
                        if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
                                break;
-                       DRM_UDELAY(1);
+                       udelay(1);
                }
 
                if (running)
@@ -723,7 +723,7 @@ int ni_init_microcode(struct radeon_device *rdev)
                rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4;
                mc_req_size = 0;
                break;
-       default: panic("%s: Unsupported family %d", __func__, rdev->family);
+       default: BUG();
        }
 
        DRM_INFO("Loading %s Microcode\n", chip_name);
@@ -733,7 +733,7 @@ int ni_init_microcode(struct radeon_device *rdev)
        if (err)
                goto out;
        if (rdev->pfp_fw->datasize != pfp_req_size) {
-               DRM_ERROR(
+               printk(KERN_ERR
                       "ni_pfp: Bogus length %zu in firmware \"%s\"\n",
                       rdev->pfp_fw->datasize, fw_name);
                err = -EINVAL;
@@ -745,7 +745,7 @@ int ni_init_microcode(struct radeon_device *rdev)
        if (err)
                goto out;
        if (rdev->me_fw->datasize != me_req_size) {
-               DRM_ERROR(
+               printk(KERN_ERR
                       "ni_me: Bogus length %zu in firmware \"%s\"\n",
                       rdev->me_fw->datasize, fw_name);
                err = -EINVAL;
@@ -757,7 +757,7 @@ int ni_init_microcode(struct radeon_device *rdev)
        if (err)
                goto out;
        if (rdev->rlc_fw->datasize != rlc_req_size) {
-               DRM_ERROR(
+               printk(KERN_ERR
                       "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
                       rdev->rlc_fw->datasize, fw_name);
                err = -EINVAL;
@@ -770,7 +770,7 @@ int ni_init_microcode(struct radeon_device *rdev)
                if (err)
                        goto out;
                if (rdev->mc_fw->datasize != mc_req_size) {
-                       DRM_ERROR(
+                       printk(KERN_ERR
                               "ni_mc: Bogus length %zu in firmware \"%s\"\n",
                               rdev->mc_fw->datasize, fw_name);
                        err = -EINVAL;
@@ -797,7 +797,7 @@ int ni_init_microcode(struct radeon_device *rdev)
 out:
        if (err) {
                if (err != -EINVAL)
-                       DRM_ERROR(
+                       printk(KERN_ERR
                               "ni_cp: Failed to load firmware \"%s\"\n",
                               fw_name);
                release_firmware(rdev->pfp_fw);
@@ -1176,7 +1176,7 @@ static void cayman_gpu_init(struct radeon_device *rdev)
 
        WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
 
-       DRM_UDELAY(50);
+       udelay(50);
 
        /* set clockgating golden values on TN */
        if (rdev->family == CHIP_ARUBA) {
@@ -1550,7 +1550,7 @@ static int cayman_cp_resume(struct radeon_device *rdev)
                                 SOFT_RESET_SPI |
                                 SOFT_RESET_SX));
        RREG32(GRBM_SOFT_RESET);
-       DRM_MDELAY(15);
+       mdelay(15);
        WREG32(GRBM_SOFT_RESET, 0);
        RREG32(GRBM_SOFT_RESET);
 
@@ -1600,7 +1600,7 @@ static int cayman_cp_resume(struct radeon_device *rdev)
                WREG32(ring->rptr_reg, ring->rptr);
                WREG32(ring->wptr_reg, ring->wptr);
 
-               DRM_MDELAY(1);
+               mdelay(1);
                WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA);
        }
 
@@ -1714,7 +1714,7 @@ int cayman_dma_resume(struct radeon_device *rdev)
        /* Reset dma */
        WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1);
        RREG32(SRBM_SOFT_RESET);
-       DRM_UDELAY(50);
+       udelay(50);
        WREG32(SRBM_SOFT_RESET, 0);
 
        for (i = 0; i < 2; i++) {
@@ -1916,7 +1916,7 @@ static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
                WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
        }
 
-       DRM_UDELAY(50);
+       udelay(50);
 
        evergreen_mc_stop(rdev, &save);
        if (evergreen_mc_wait_for_idle(rdev)) {
@@ -1980,7 +1980,7 @@ static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
                WREG32(GRBM_SOFT_RESET, tmp);
                tmp = RREG32(GRBM_SOFT_RESET);
 
-               DRM_UDELAY(50);
+               udelay(50);
 
                tmp &= ~grbm_soft_reset;
                WREG32(GRBM_SOFT_RESET, tmp);
@@ -1994,7 +1994,7 @@ static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
                WREG32(SRBM_SOFT_RESET, tmp);
                tmp = RREG32(SRBM_SOFT_RESET);
 
-               DRM_UDELAY(50);
+               udelay(50);
 
                tmp &= ~srbm_soft_reset;
                WREG32(SRBM_SOFT_RESET, tmp);
@@ -2002,10 +2002,10 @@ static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
        }
 
        /* Wait a little for things to settle down */
-       DRM_UDELAY(50);
+       udelay(50);
 
        evergreen_mc_resume(rdev, &save);
-       DRM_UDELAY(50);
+       udelay(50);
 
        evergreen_print_gpu_status_regs(rdev);
 }
@@ -2440,7 +2440,7 @@ void cayman_fini(struct radeon_device *rdev)
        radeon_bo_fini(rdev);
        radeon_atombios_fini(rdev);
        ni_fini_microcode(rdev);
-       drm_free(rdev->bios, M_DRM);
+       kfree(rdev->bios);
        rdev->bios = NULL;
 }
 
index 51e5839..001d6d7 100644 (file)
@@ -1092,10 +1092,10 @@ static void ni_stop_smc(struct radeon_device *rdev)
                tmp = RREG32(LB_SYNC_RESET_SEL) & LB_SYNC_RESET_SEL_MASK;
                if (tmp != 1)
                        break;
-               DRM_UDELAY(1);
+               udelay(1);
        }
 
-       DRM_UDELAY(100);
+       udelay(100);
 
        r7xx_stop_smc(rdev);
 }
@@ -1217,7 +1217,7 @@ static int ni_enter_ulp_state(struct radeon_device *rdev)
        WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower),
                  ~HOST_SMC_MSG_MASK);
 
-       DRM_UDELAY(25000);
+       udelay(25000);
 
        return 0;
 }
@@ -3483,7 +3483,7 @@ static void ni_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev,
 
                        tmp |= LC_CLR_FAILED_SPD_CHANGE_CNT;
                        WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
-                       DRM_UDELAY(10);
+                       udelay(10);
                        tmp &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
                        WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
                } else {
index d333984..2723307 100644 (file)
@@ -27,7 +27,6 @@
  *
  * $FreeBSD: head/sys/dev/drm2/radeon/r100.c 255573 2013-09-14 17:24:41Z dumbbell $
  */
-
 #include <drm/drmP.h>
 #include <uapi_drm/radeon_drm.h>
 #include "radeon_reg.h"
@@ -199,7 +198,7 @@ u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
        for (i = 0; i < rdev->usec_timeout; i++) {
                if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
                        break;
-               DRM_UDELAY(1);
+               udelay(1);
        }
        DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 
@@ -374,7 +373,7 @@ void r100_pm_misc(struct radeon_device *rdev)
                                tmp &= ~(voltage->gpio.mask);
                        WREG32(voltage->gpio.reg, tmp);
                        if (voltage->delay)
-                               DRM_UDELAY(voltage->delay);
+                               udelay(voltage->delay);
                } else {
                        tmp = RREG32(voltage->gpio.reg);
                        if (voltage->active_high)
@@ -383,7 +382,7 @@ void r100_pm_misc(struct radeon_device *rdev)
                                tmp |= voltage->gpio.mask;
                        WREG32(voltage->gpio.reg, tmp);
                        if (voltage->delay)
-                               DRM_UDELAY(voltage->delay);
+                               udelay(voltage->delay);
                }
        }
 
@@ -651,7 +650,7 @@ int r100_pci_gart_init(struct radeon_device *rdev)
        int r;
 
        if (rdev->gart.ptr) {
-               DRM_ERROR("R100 PCI GART already initialized\n");
+               WARN(1, "R100 PCI GART already initialized\n");
                return 0;
        }
        /* Initialize common gart structure */
@@ -721,7 +720,7 @@ int r100_irq_set(struct radeon_device *rdev)
        uint32_t tmp = 0;
 
        if (!rdev->irq.installed) {
-               DRM_ERROR("Can't enable IRQ/MSI because no handler is installed\n");
+               WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
                WREG32(R_000040_GEN_INT_CNTL, 0);
                return -EINVAL;
        }
@@ -752,7 +751,7 @@ void r100_irq_disable(struct radeon_device *rdev)
 
        WREG32(R_000040_GEN_INT_CNTL, 0);
        /* Wait and acknowledge irq */
-       DRM_MDELAY(1);
+       mdelay(1);
        tmp = RREG32(R_000044_GEN_INT_STATUS);
        WREG32(R_000044_GEN_INT_STATUS, tmp);
 }
@@ -792,7 +791,7 @@ irqreturn_t r100_irq_process(struct radeon_device *rdev)
                        if (rdev->irq.crtc_vblank_int[0]) {
                                drm_handle_vblank(rdev->ddev, 0);
                                rdev->pm.vblank_sync = true;
-                               DRM_WAKEUP(&rdev->irq.vblank_queue);
+                               wake_up(&rdev->irq.vblank_queue);
                        }
                        if (atomic_read(&rdev->irq.pflip[0]))
                                radeon_crtc_handle_flip(rdev, 0);
@@ -801,7 +800,7 @@ irqreturn_t r100_irq_process(struct radeon_device *rdev)
                        if (rdev->irq.crtc_vblank_int[1]) {
                                drm_handle_vblank(rdev->ddev, 1);
                                rdev->pm.vblank_sync = true;
-                               DRM_WAKEUP(&rdev->irq.vblank_queue);
+                               wake_up(&rdev->irq.vblank_queue);
                        }
                        if (atomic_read(&rdev->irq.pflip[1]))
                                radeon_crtc_handle_flip(rdev, 1);
@@ -876,7 +875,7 @@ void r100_semaphore_ring_emit(struct radeon_device *rdev,
                              bool emit_wait)
 {
        /* Unused on older asics, since we don't have semaphores or multiple rings */
-       panic("%s: Unused on older asics", __func__);
+       BUG();
 }
 
 int r100_copy_blit(struct radeon_device *rdev,
@@ -963,7 +962,7 @@ static int r100_cp_wait_for_idle(struct radeon_device *rdev)
                if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
                        return 0;
                }
-               DRM_UDELAY(1);
+               udelay(1);
        }
        return -1;
 }
@@ -1037,10 +1036,10 @@ static int r100_cp_init_microcode(struct radeon_device *rdev)
 
        err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
        if (err) {
-               DRM_ERROR("radeon_cp: Failed to load firmware \"%s\"\n",
+               printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
                       fw_name);
        } else if (rdev->me_fw->datasize % 8) {
-               DRM_ERROR(
+               printk(KERN_ERR
                       "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
                       rdev->me_fw->datasize, fw_name);
                err = -EINVAL;
@@ -1070,7 +1069,7 @@ static void r100_cp_load_microcode(struct radeon_device *rdev)
        int i, size;
 
        if (r100_gui_wait_for_idle(rdev)) {
-               DRM_ERROR("Failed to wait GUI idle while "
+               printk(KERN_WARNING "Failed to wait GUI idle while "
                       "programming pipes. Bad things might happen.\n");
        }
 
@@ -1177,7 +1176,7 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
        }
 
        WREG32(RADEON_CP_RB_CNTL, tmp);
-       DRM_UDELAY(10);
+       udelay(10);
        ring->rptr = RREG32(RADEON_CP_RB_RPTR);
        /* Set cp mode to bus mastering & enable cp*/
        WREG32(RADEON_CP_CSQ_MODE,
@@ -1231,7 +1230,7 @@ void r100_cp_disable(struct radeon_device *rdev)
        WREG32(RADEON_CP_CSQ_CNTL, 0);
        WREG32(R_000770_SCRATCH_UMSK, 0);
        if (r100_gui_wait_for_idle(rdev)) {
-               DRM_ERROR("Failed to wait GUI idle while "
+               printk(KERN_WARNING "Failed to wait GUI idle while "
                       "programming pipes. Bad things might happen.\n");
        }
 }
@@ -1868,7 +1867,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
                track->tex_dirty = true;
                break;
        default:
-               DRM_ERROR("Forbidden register 0x%04X in cs at %d\n",
+               printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
                       reg, idx);
                return -EINVAL;
        }
@@ -2020,7 +2019,7 @@ int r100_cs_parse(struct radeon_cs_parser *p)
        struct r100_cs_track *track;
        int r;
 
-       track = kmalloc(sizeof(*track), M_DRM, M_ZERO | M_WAITOK);
+       track = kzalloc(sizeof(*track), GFP_KERNEL);
        if (!track)
                return -ENOMEM;
        r100_cs_track_clear(p->rdev, track);
@@ -2028,7 +2027,7 @@ int r100_cs_parse(struct radeon_cs_parser *p)
        do {
                r = radeon_cs_packet_parse(p, &pkt, p->idx);
                if (r) {
-                       drm_free(p->track, M_DRM);
+                       kfree(p->track);
                        p->track = NULL;
                        return r;
                }
@@ -2054,17 +2053,17 @@ int r100_cs_parse(struct radeon_cs_parser *p)
                default:
                        DRM_ERROR("Unknown packet type %d !\n",
                                  pkt.type);
-                       drm_free(p->track, M_DRM);
+                       kfree(p->track);
                        p->track = NULL;
                        return -EINVAL;
                }
                if (r) {
-                       drm_free(p->track, M_DRM);
+                       kfree(p->track);
                        p->track = NULL;
                        return r;
                }
        } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
-       drm_free(p->track, M_DRM);
+       kfree(p->track);
        p->track = NULL;
        return 0;
 }
@@ -2482,7 +2481,7 @@ int r100_gui_wait_for_idle(struct radeon_device *rdev)
        uint32_t tmp;
 
        if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
-               DRM_ERROR("radeon: wait for empty RBBM fifo failed !"
+               printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
                       " Bad things might happen.\n");
        }
        for (i = 0; i < rdev->usec_timeout; i++) {
@@ -2541,14 +2540,14 @@ void r100_bm_disable(struct radeon_device *rdev)
        /* disable bus mastering */
        tmp = RREG32(R_000030_BUS_CNTL);
        WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
-       DRM_MDELAY(1);
+       mdelay(1);
        WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
-       DRM_MDELAY(1);
+       mdelay(1);
        WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
        tmp = RREG32(RADEON_BUS_CNTL);
-       DRM_MDELAY(1);
+       mdelay(1);
        pci_disable_busmaster(rdev->dev);
-       DRM_MDELAY(1);
+       mdelay(1);
 }
 
 int r100_asic_reset(struct radeon_device *rdev)
@@ -2580,17 +2579,17 @@ int r100_asic_reset(struct radeon_device *rdev)
                                        S_0000F0_SOFT_RESET_PP(1) |
                                        S_0000F0_SOFT_RESET_RB(1));
        RREG32(R_0000F0_RBBM_SOFT_RESET);
-       DRM_MDELAY(500);
+       mdelay(500);
        WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
-       DRM_MDELAY(1);
+       mdelay(1);
        status = RREG32(R_000E40_RBBM_STATUS);
        dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
        /* reset CP */
        WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
        RREG32(R_0000F0_RBBM_SOFT_RESET);
-       DRM_MDELAY(500);
+       mdelay(500);
        WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
-       DRM_MDELAY(1);
+       mdelay(1);
        status = RREG32(R_000E40_RBBM_STATUS);
        dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
        /* restore PCI & busmastering */
@@ -2856,7 +2855,7 @@ static void r100_pll_errata_after_data(struct radeon_device *rdev)
         * or the chip could hang on a subsequent access
         */
        if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
-               DRM_MDELAY(5);
+               mdelay(5);
        }
 
        /* This function is required to workaround a hardware bug in some (all?)
@@ -2898,10 +2897,10 @@ static void r100_set_safe_registers(struct radeon_device *rdev)
 {
        if (ASIC_IS_RN50(rdev)) {
                rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
-               rdev->config.r100.reg_safe_bm_size = DRM_ARRAY_SIZE(rn50_reg_safe_bm);
+               rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
        } else if (rdev->family < CHIP_R200) {
                rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
-               rdev->config.r100.reg_safe_bm_size = DRM_ARRAY_SIZE(r100_reg_safe_bm);
+               rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
        } else {
                r200_set_safe_registers(rdev);
        }
@@ -3959,7 +3958,7 @@ void r100_fini(struct radeon_device *rdev)
        radeon_bo_fini(rdev);
        radeon_atombios_fini(rdev);
        r100_cp_fini_microcode(rdev);
-       drm_free(rdev->bios, M_DRM);
+       kfree(rdev->bios);
        rdev->bios = NULL;
 }
 
index c3c3579..34aa4fa 100644 (file)
@@ -534,7 +534,7 @@ int r200_packet0_check(struct radeon_cs_parser *p,
                track->tex_dirty = true;
                break;
        default:
-               DRM_ERROR("Forbidden register 0x%04X in cs at %d\n",
+               printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
                       reg, idx);
                return -EINVAL;
        }
@@ -544,5 +544,5 @@ int r200_packet0_check(struct radeon_cs_parser *p,
 void r200_set_safe_registers(struct radeon_device *rdev)
 {
        rdev->config.r100.reg_safe_bm = r200_reg_safe_bm;
-       rdev->config.r100.reg_safe_bm_size = DRM_ARRAY_SIZE(r200_reg_safe_bm);
+       rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r200_reg_safe_bm);
 }
index a034b16..a1c77e7 100644 (file)
@@ -27,7 +27,6 @@
  *
  * $FreeBSD: head/sys/dev/drm2/radeon/r300.c 255573 2013-09-14 17:24:41Z dumbbell $
  */
-
 #include <drm/drmP.h>
 #include <uapi_drm/drm.h>
 #include <drm/drm_crtc_helper.h>
@@ -67,7 +66,7 @@ void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
                (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
                WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
        }
-       cpu_mfence();
+       mb();
 }
 
 #define R300_PTE_WRITEABLE (1 << 2)
@@ -96,7 +95,7 @@ int rv370_pcie_gart_init(struct radeon_device *rdev)
        int r;
 
        if (rdev->gart.robj) {
-               DRM_ERROR("RV370 PCIE GART already initialized\n");
+               WARN(1, "RV370 PCIE GART already initialized\n");
                return 0;
        }
        /* Initialize common gart structure */
@@ -356,7 +355,7 @@ static void r300_gpu_init(struct radeon_device *rdev)
        WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
 
        if (r100_gui_wait_for_idle(rdev)) {
-               DRM_ERROR("Failed to wait GUI idle while "
+               printk(KERN_WARNING "Failed to wait GUI idle while "
                       "programming pipes. Bad things might happen.\n");
        }
 
@@ -368,11 +367,11 @@ static void r300_gpu_init(struct radeon_device *rdev)
               R300_DC_DC_DISABLE_IGNORE_PE);
 
        if (r100_gui_wait_for_idle(rdev)) {
-               DRM_ERROR("Failed to wait GUI idle while "
+               printk(KERN_WARNING "Failed to wait GUI idle while "
                       "programming pipes. Bad things might happen.\n");
        }
        if (r300_mc_wait_for_idle(rdev)) {
-               DRM_ERROR("Failed to wait MC idle while "
+               printk(KERN_WARNING "Failed to wait MC idle while "
                       "programming pipes. Bad things might happen.\n");
        }
        DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
@@ -406,9 +405,9 @@ int r300_asic_reset(struct radeon_device *rdev)
        WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
                                        S_0000F0_SOFT_RESET_GA(1));
        RREG32(R_0000F0_RBBM_SOFT_RESET);
-       DRM_MDELAY(500);
+       mdelay(500);
        WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
-       DRM_MDELAY(1);
+       mdelay(1);
        status = RREG32(R_000E40_RBBM_STATUS);
        dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
        /* resetting the CP seems to be problematic sometimes it end up
@@ -418,9 +417,9 @@ int r300_asic_reset(struct radeon_device *rdev)
         */
        WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
        RREG32(R_0000F0_RBBM_SOFT_RESET);
-       DRM_MDELAY(500);
+       mdelay(500);
        WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
-       DRM_MDELAY(1);
+       mdelay(1);
        status = RREG32(R_000E40_RBBM_STATUS);
        dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
        /* restore PCI & busmastering */
@@ -1134,7 +1133,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
        }
        return 0;
 fail:
-       DRM_ERROR("Forbidden register 0x%04X in cs at %d (val=%08x)\n",
+       printk(KERN_ERR "Forbidden register 0x%04X in cs at %d (val=%08x)\n",
               reg, idx, idx_value);
        return -EINVAL;
 }
@@ -1253,7 +1252,7 @@ int r300_cs_parse(struct radeon_cs_parser *p)
        struct r100_cs_track *track;
        int r;
 
-       track = kmalloc(sizeof(*track), M_DRM, M_ZERO | M_WAITOK);
+       track = kzalloc(sizeof(*track), GFP_KERNEL);
        if (track == NULL)
                return -ENOMEM;
        r100_cs_track_clear(p->rdev, track);
@@ -1261,7 +1260,7 @@ int r300_cs_parse(struct radeon_cs_parser *p)
        do {
                r = radeon_cs_packet_parse(p, &pkt, p->idx);
                if (r) {
-                       drm_free(p->track, M_DRM);
+                       kfree(p->track);
                        p->track = NULL;
                        return r;
                }
@@ -1280,17 +1279,17 @@ int r300_cs_parse(struct radeon_cs_parser *p)
                        break;
                default:
                        DRM_ERROR("Unknown packet type %d !\n", pkt.type);
-                       drm_free(p->track, M_DRM);
+                       kfree(p->track);
                        p->track = NULL;
                        return -EINVAL;
                }
                if (r) {
-                       drm_free(p->track, M_DRM);
+                       kfree(p->track);
                        p->track = NULL;
                        return r;
                }
        } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
-       drm_free(p->track, M_DRM);
+       kfree(p->track);
        p->track = NULL;
        return 0;
 }
@@ -1298,7 +1297,7 @@ int r300_cs_parse(struct radeon_cs_parser *p)
 void r300_set_reg_safe(struct radeon_device *rdev)
 {
        rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
-       rdev->config.r300.reg_safe_bm_size = DRM_ARRAY_SIZE(r300_reg_safe_bm);
+       rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
 }
 
 void r300_mc_program(struct radeon_device *rdev)
@@ -1475,7 +1474,7 @@ void r300_fini(struct radeon_device *rdev)
        radeon_fence_driver_fini(rdev);
        radeon_bo_fini(rdev);
        radeon_atombios_fini(rdev);
-       drm_free(rdev->bios, M_DRM);
+       kfree(rdev->bios);
        rdev->bios = NULL;
 }
 
index 87f1b3b..659883c 100644 (file)
@@ -27,7 +27,6 @@
  *
  * $FreeBSD: head/sys/dev/drm2/radeon/r420.c 254885 2013-08-25 19:37:15Z dumbbell $
  */
-
 #include <drm/drmP.h>
 #include "radeon_reg.h"
 #include "radeon.h"
@@ -79,7 +78,7 @@ void r420_pm_init_profile(struct radeon_device *rdev)
 static void r420_set_reg_safe(struct radeon_device *rdev)
 {
        rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
-       rdev->config.r300.reg_safe_bm_size = DRM_ARRAY_SIZE(r420_reg_safe_bm);
+       rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
 }
 
 void r420_pipes_init(struct radeon_device *rdev)
@@ -93,7 +92,7 @@ void r420_pipes_init(struct radeon_device *rdev)
               (1 << 2) | (1 << 3));
        /* add idle wait as per freedesktop.org bug 24041 */
        if (r100_gui_wait_for_idle(rdev)) {
-               DRM_ERROR("Failed to wait GUI idle while "
+               printk(KERN_WARNING "Failed to wait GUI idle while "
                       "programming pipes. Bad things might happen.\n");
        }
        /* get max number of pipes */
@@ -129,7 +128,7 @@ void r420_pipes_init(struct radeon_device *rdev)
        tmp |= R300_TILE_SIZE_16 | R300_ENABLE_TILING;
        WREG32(R300_GB_TILE_CONFIG, tmp);
        if (r100_gui_wait_for_idle(rdev)) {
-               DRM_ERROR("Failed to wait GUI idle while "
+               printk(KERN_WARNING "Failed to wait GUI idle while "
                       "programming pipes. Bad things might happen.\n");
        }
 
@@ -142,7 +141,7 @@ void r420_pipes_init(struct radeon_device *rdev)
               R300_DC_DC_DISABLE_IGNORE_PE);
 
        if (r100_gui_wait_for_idle(rdev)) {
-               DRM_ERROR("Failed to wait GUI idle while "
+               printk(KERN_WARNING "Failed to wait GUI idle while "
                       "programming pipes. Bad things might happen.\n");
        }
 
@@ -359,7 +358,7 @@ void r420_fini(struct radeon_device *rdev)
        } else {
                radeon_combios_fini(rdev);
        }
-       drm_free(rdev->bios, M_DRM);
+       kfree(rdev->bios);
        rdev->bios = NULL;
 }
 
index 73722a7..e1aece7 100644 (file)
@@ -86,7 +86,7 @@ static void r520_gpu_init(struct radeon_device *rdev)
              (((gb_pipe_select >> 8) & 0xF) << 4);
        WREG32_PLL(0x000D, tmp);
        if (r520_mc_wait_for_idle(rdev)) {
-               DRM_ERROR("Failed to wait MC idle while "
+               printk(KERN_WARNING "Failed to wait MC idle while "
                       "programming pipes. Bad things might happen.\n");
        }
 }
index 03b8a96..5383ab1 100644 (file)
@@ -27,6 +27,7 @@
  *
  * $FreeBSD: head/sys/dev/drm2/radeon/r600.c 254885 2013-08-25 19:37:15Z dumbbell $
  */
+#include <linux/seq_file.h>
 #include <linux/firmware.h>
 #include <linux/module.h>
 #include <drm/drmP.h>
@@ -873,13 +874,13 @@ void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
                tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
                tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
                if (tmp == 2) {
-                       DRM_ERROR("[drm] r600 flush TLB failed\n");
+                       printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
                        return;
                }
                if (tmp) {
                        return;
                }
-               DRM_UDELAY(1);
+               udelay(1);
        }
 }
 
@@ -888,7 +889,7 @@ int r600_pcie_gart_init(struct radeon_device *rdev)
        int r;
 
        if (rdev->gart.robj) {
-               DRM_ERROR("R600 PCIE GART already initialized\n");
+               WARN(1, "R600 PCIE GART already initialized\n");
                return 0;
        }
        /* Initialize common gart structure */
@@ -1040,7 +1041,7 @@ int r600_mc_wait_for_idle(struct radeon_device *rdev)
                tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
                if (!tmp)
                        return 0;
-               DRM_UDELAY(1);
+               udelay(1);
        }
        return -1;
 }
@@ -1377,7 +1378,7 @@ static bool r600_is_display_hung(struct radeon_device *rdev)
                }
                if (crtc_hung == 0)
                        return false;
-               DRM_UDELAY(100);
+               udelay(100);
        }
 
        return true;
@@ -1481,7 +1482,7 @@ static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
                WREG32(DMA_RB_CNTL, tmp);
        }
 
-       DRM_MDELAY(50);
+       mdelay(50);
 
        rv515_mc_stop(rdev, &save);
        if (r600_mc_wait_for_idle(rdev)) {
@@ -1558,7 +1559,7 @@ static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
                WREG32(R_008020_GRBM_SOFT_RESET, tmp);
                tmp = RREG32(R_008020_GRBM_SOFT_RESET);
 
-               DRM_UDELAY(50);
+               udelay(50);
 
                tmp &= ~grbm_soft_reset;
                WREG32(R_008020_GRBM_SOFT_RESET, tmp);
@@ -1572,7 +1573,7 @@ static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
                WREG32(SRBM_SOFT_RESET, tmp);
                tmp = RREG32(SRBM_SOFT_RESET);
 
-               DRM_UDELAY(50);
+               udelay(50);
 
                tmp &= ~srbm_soft_reset;
                WREG32(SRBM_SOFT_RESET, tmp);
@@ -1580,10 +1581,10 @@ static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
        }
 
        /* Wait a little for things to settle down */
-       DRM_MDELAY(1);
+       mdelay(1);
 
        rv515_mc_resume(rdev, &save);
-       DRM_UDELAY(50);
+       udelay(50);
 
        r600_print_gpu_status_regs(rdev);
 }
@@ -1672,7 +1673,7 @@ u32 r6xx_remap_render_backend(struct radeon_device *rdev,
 
        rendering_pipe_num = 1 << tiling_pipe_num;
        req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);
-       KASSERT(rendering_pipe_num >= req_rb_num, ("rendering_pipe_num < req_rb_num"));
+       BUG_ON(rendering_pipe_num < req_rb_num);
 
        pipe_rb_ratio = rendering_pipe_num / req_rb_num;
        pipe_rb_remain = rendering_pipe_num - pipe_rb_ratio * req_rb_num;
@@ -2252,7 +2253,7 @@ int r600_init_microcode(struct radeon_device *rdev)
                chip_name = "SUMO2";
                rlc_chip_name = "SUMO";
                break;
-       default: panic("%s: Unsupported family %d", __func__, rdev->family);
+       default: BUG();
        }
 
        if (rdev->family >= CHIP_CEDAR) {
@@ -2276,7 +2277,7 @@ int r600_init_microcode(struct radeon_device *rdev)
        if (err)
                goto out;
        if (rdev->pfp_fw->datasize != pfp_req_size) {
-               DRM_ERROR(
+               printk(KERN_ERR
                       "r600_cp: Bogus length %zu in firmware \"%s\"\n",
                       rdev->pfp_fw->datasize, fw_name);
                err = -EINVAL;
@@ -2288,7 +2289,7 @@ int r600_init_microcode(struct radeon_device *rdev)
        if (err)
                goto out;
        if (rdev->me_fw->datasize != me_req_size) {
-               DRM_ERROR(
+               printk(KERN_ERR
                       "r600_cp: Bogus length %zu in firmware \"%s\"\n",
                       rdev->me_fw->datasize, fw_name);
                err = -EINVAL;
@@ -2299,7 +2300,7 @@ int r600_init_microcode(struct radeon_device *rdev)
        if (err)
                goto out;
        if (rdev->rlc_fw->datasize != rlc_req_size) {
-               DRM_ERROR(
+               printk(KERN_ERR
                       "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
                       rdev->rlc_fw->datasize, fw_name);
                err = -EINVAL;
@@ -2325,7 +2326,7 @@ int r600_init_microcode(struct radeon_device *rdev)
 out:
        if (err) {
                if (err != -EINVAL)
-                       DRM_ERROR(
+                       printk(KERN_ERR
                               "r600_cp: Failed to load firmware \"%s\"\n",
                               fw_name);
                release_firmware(rdev->pfp_fw);
@@ -2379,7 +2380,7 @@ static int r600_cp_load_microcode(struct radeon_device *rdev)
        /* Reset cp */
        WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
        RREG32(GRBM_SOFT_RESET);
-       DRM_MDELAY(15);
+       mdelay(15);
        WREG32(GRBM_SOFT_RESET, 0);
 
        WREG32(CP_ME_RAM_WADDR, 0);
@@ -2442,7 +2443,7 @@ int r600_cp_resume(struct radeon_device *rdev)
        /* Reset cp */
        WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
        RREG32(GRBM_SOFT_RESET);
-       DRM_MDELAY(15);
+       mdelay(15);
        WREG32(GRBM_SOFT_RESET, 0);
 
        /* Set ring buffer size */
@@ -2476,7 +2477,7 @@ int r600_cp_resume(struct radeon_device *rdev)
                WREG32(SCRATCH_UMSK, 0);
        }
 
-       DRM_MDELAY(1);
+       mdelay(1);
        WREG32(CP_RB_CNTL, tmp);
 
        WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
@@ -2573,7 +2574,7 @@ int r600_dma_resume(struct radeon_device *rdev)
        else
                WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
        RREG32(SRBM_SOFT_RESET);
-       DRM_UDELAY(50);
+       udelay(50);
        WREG32(SRBM_SOFT_RESET, 0);
 
        WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL, 0);
@@ -2740,11 +2741,11 @@ void r600_uvd_stop(struct radeon_device *rdev)
        /* Stall UMC and register bus before resetting VCPU */
        WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
        WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3));
-       DRM_MDELAY(1);
+       mdelay(1);
 
        /* put VCPU into reset */
        WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET);
-       DRM_MDELAY(5);
+       mdelay(5);
 
        /* disable VCPU clock */
        WREG32(UVD_VCPU_CNTL, 0x0);
@@ -2775,17 +2776,17 @@ int r600_uvd_init(struct radeon_device *rdev)
        /* Stall UMC and register bus before resetting VCPU */
        WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8));
        WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3));
-       DRM_MDELAY(1);
+       mdelay(1);
 
        /* put LMI, VCPU, RBC etc... into reset */
        WREG32(UVD_SOFT_RESET, LMI_SOFT_RESET | VCPU_SOFT_RESET |
               LBSI_SOFT_RESET | RBC_SOFT_RESET | CSM_SOFT_RESET |
               CXW_SOFT_RESET | TAP_SOFT_RESET | LMI_UMC_SOFT_RESET);
-       DRM_MDELAY(5);
+       mdelay(5);
 
        /* take UVD block out of reset */
        WREG32_P(SRBM_SOFT_RESET, 0, ~SOFT_RESET_UVD);
-       DRM_MDELAY(5);
+       mdelay(5);
 
        /* initialize UVD memory controller */
        WREG32(UVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
@@ -2808,7 +2809,7 @@ int r600_uvd_init(struct radeon_device *rdev)
 
        /* take all subblocks out of reset, except VCPU */
        WREG32(UVD_SOFT_RESET, VCPU_SOFT_RESET);
-       DRM_MDELAY(5);
+       mdelay(5);
 
        /* enable VCPU clock */
        WREG32(UVD_VCPU_CNTL,  1 << 9);
@@ -2818,7 +2819,7 @@ int r600_uvd_init(struct radeon_device *rdev)
 
        /* boot up the VCPU */
        WREG32(UVD_SOFT_RESET, 0);
-       DRM_MDELAY(10);
+       mdelay(10);
 
        WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3));
 
@@ -2828,7 +2829,7 @@ int r600_uvd_init(struct radeon_device *rdev)
                        status = RREG32(UVD_STATUS);
                        if (status & 2)
                                break;
-                       DRM_MDELAY(10);
+                       mdelay(10);
                }
                r = 0;
                if (status & 2)
@@ -2836,9 +2837,9 @@ int r600_uvd_init(struct radeon_device *rdev)
 
                DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n");
                WREG32_P(UVD_SOFT_RESET, VCPU_SOFT_RESET, ~VCPU_SOFT_RESET);
-               DRM_MDELAY(10);
+               mdelay(10);
                WREG32_P(UVD_SOFT_RESET, 0, ~VCPU_SOFT_RESET);
-               DRM_MDELAY(10);
+               mdelay(10);
                r = -1;
        }
 
@@ -3618,7 +3619,7 @@ void r600_fini(struct radeon_device *rdev)
        radeon_bo_fini(rdev);
        radeon_atombios_fini(rdev);
        r600_fini_microcode(rdev);
-       drm_free(rdev->bios, M_DRM);
+       kfree(rdev->bios);
        rdev->bios = NULL;
 }
 
@@ -3944,7 +3945,7 @@ void r600_rlc_stop(struct radeon_device *rdev)
                /* r7xx asics need to soft reset RLC before halting */
                WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
                RREG32(SRBM_SOFT_RESET);
-               DRM_MDELAY(15);
+               mdelay(15);
                WREG32(SRBM_SOFT_RESET, 0);
                RREG32(SRBM_SOFT_RESET);
        }
@@ -4179,7 +4180,7 @@ int r600_irq_set(struct radeon_device *rdev)
        u32 thermal_int = 0;
 
        if (!rdev->irq.installed) {
-               DRM_ERROR("Can't enable IRQ/MSI because no handler is installed\n");
+               WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
                return -EINVAL;
        }
        /* don't enable anything if the ih is disabled */
@@ -4436,7 +4437,7 @@ void r600_irq_disable(struct radeon_device *rdev)
 {
        r600_disable_interrupts(rdev);
        /* Wait and acknowledge irq */
-       DRM_MDELAY(1);
+       mdelay(1);
        r600_irq_ack(rdev);
        r600_disable_interrupt_state(rdev);
 }
@@ -4523,7 +4524,7 @@ restart_ih:
        DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
 
        /* Order reading of wptr vs. reading of IH ring data */
-       cpu_lfence();
+       rmb();
 
        /* display interrupts */
        r600_irq_ack(rdev);
@@ -4542,7 +4543,7 @@ restart_ih:
                                        if (rdev->irq.crtc_vblank_int[0]) {
                                                drm_handle_vblank(rdev->ddev, 0);
                                                rdev->pm.vblank_sync = true;
-                                               DRM_WAKEUP(&rdev->irq.vblank_queue);
+                                               wake_up(&rdev->irq.vblank_queue);
                                        }
                                        if (atomic_read(&rdev->irq.pflip[0]))
                                                radeon_crtc_handle_flip(rdev, 0);
@@ -4568,7 +4569,7 @@ restart_ih:
                                        if (rdev->irq.crtc_vblank_int[1]) {
                                                drm_handle_vblank(rdev->ddev, 1);
                                                rdev->pm.vblank_sync = true;
-                                               DRM_WAKEUP(&rdev->irq.vblank_queue);
+                                               wake_up(&rdev->irq.vblank_queue);
                                        }
                                        if (atomic_read(&rdev->irq.pflip[1]))
                                                radeon_crtc_handle_flip(rdev, 1);
@@ -4699,7 +4700,6 @@ restart_ih:
                taskqueue_enqueue(rdev->tq, &rdev->audio_work);
        if (queue_thermal && rdev->pm.dpm_enabled)
                taskqueue_enqueue(rdev->tq, &rdev->pm.dpm.thermal.work);
-
        rdev->ih.rptr = rptr;
        WREG32(IH_RB_RPTR, rdev->ih.rptr);
        atomic_set(&rdev->ih.lock, 0);
index 88e8b54..58fc091 100644 (file)
  * OTHER DEALINGS IN THE SOFTWARE.
  *
  * Authors: Christian König
- *
- * $FreeBSD: head/sys/dev/drm2/radeon/r600_audio.c 254885 2013-08-25 19:37:15Z dumbbell $
  */
-
 #include <drm/drmP.h>
 #include "radeon.h"
 #include "radeon_reg.h"
index 895d952..cc30fd0 100644 (file)
  *     Alex Deucher <alexander.deucher@amd.com>
  *
  * ------------------------ This file is DEPRECATED! -------------------------
- *
- * $FreeBSD: head/sys/dev/drm2/radeon/r600_blit.c 254885 2013-08-25 19:37:15Z dumbbell $
  */
-
 #include <drm/drmP.h>
 #include <uapi_drm/radeon_drm.h>
 #include "radeon_drv.h"
@@ -53,7 +50,7 @@ set_render_target(drm_radeon_private_t *dev_priv, int format, int w, int h, u64
        RING_LOCALS;
        DRM_DEBUG("\n");
 
-       h = roundup2(h, 8);
+       h = ALIGN(h, 8);
        if (h < 8)
                h = 8;
 
index 0e8ac6f..c9aa85b 100644 (file)
@@ -21,7 +21,6 @@
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  * DEALINGS IN THE SOFTWARE.
  *
- * $FreeBSD: head/sys/dev/drm2/radeon/r600_blit_kms.c 254885 2013-08-25 19:37:15Z dumbbell $
  */
 
 #include <drm/drmP.h>
@@ -73,7 +72,7 @@ set_render_target(struct radeon_device *rdev, int format,
        u32 cb_color_info;
        int pitch, slice;
 
-       h = roundup2(h, 8);
+       h = ALIGN(h, 8);
        if (h < 8)
                h = 8;
 
@@ -465,7 +464,7 @@ set_default_state(struct radeon_device *rdev)
                                    NUM_ES_STACK_ENTRIES(num_es_stack_entries));
 
        /* emit an IB pointing at default state */
-       dwords = roundup2(rdev->r600_blit.state_len, 0x10);
+       dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
        gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
        radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
        radeon_ring_write(ring,
@@ -530,15 +529,15 @@ int r600_blit_init(struct radeon_device *rdev)
        }
 
        obj_size = dwords * 4;
-       obj_size = roundup2(obj_size, 256);
+       obj_size = ALIGN(obj_size, 256);
 
        rdev->r600_blit.vs_offset = obj_size;
        obj_size += r6xx_vs_size * 4;
-       obj_size = roundup2(obj_size, 256);
+       obj_size = ALIGN(obj_size, 256);
 
        rdev->r600_blit.ps_offset = obj_size;
        obj_size += r6xx_ps_size * 4;
-       obj_size = roundup2(obj_size, 256);
+       obj_size = ALIGN(obj_size, 256);
 
        /* pin copy shader into vram if not already initialized */
        if (rdev->r600_blit.shader_obj == NULL) {
@@ -624,7 +623,7 @@ static unsigned r600_blit_create_rect(unsigned num_gpu_pages,
                h = 0;
                w = 0;
                pages = 0;
-               DRM_ERROR("%s: called with no pages", __func__);
+               WARN_ON(1);
        } else {
                int rect_order = 2;
                h = RECT_UNIT_H;
@@ -642,7 +641,7 @@ static unsigned r600_blit_create_rect(unsigned num_gpu_pages,
                w = (pages * RECT_UNIT_W * RECT_UNIT_H) / h;
                w = (w / RECT_UNIT_W) * RECT_UNIT_W;
                pages = (w * h) / (RECT_UNIT_W * RECT_UNIT_H);
-               KASSERT(pages != 0, ("r600_blit_create_rect: pages == 0"));
+               BUG_ON(pages == 0);
        }
 
 
index 64599cd..34c8b23 100644 (file)
@@ -24,7 +24,9 @@
  *     Alex Deucher <alexander.deucher@amd.com>
  */
 
-#include <drm/drmP.h>
+#include <linux/bug.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
 
 /*
  * R6xx+ cards need to use the 3D engine to blit data which requires
@@ -711,7 +713,7 @@ const u32 r6xx_ps[] =
        0x00000000,
 };
 
-const u32 r6xx_ps_size = DRM_ARRAY_SIZE(r6xx_ps);
-const u32 r6xx_vs_size = DRM_ARRAY_SIZE(r6xx_vs);
-const u32 r6xx_default_size = DRM_ARRAY_SIZE(r6xx_default_state);
-const u32 r7xx_default_size = DRM_ARRAY_SIZE(r7xx_default_state);
+const u32 r6xx_ps_size = ARRAY_SIZE(r6xx_ps);
+const u32 r6xx_vs_size = ARRAY_SIZE(r6xx_vs);
+const u32 r6xx_default_size = ARRAY_SIZE(r6xx_default_state);
+const u32 r7xx_default_size = ARRAY_SIZE(r7xx_default_state);
index 54b5e5e..c45a9d8 100644 (file)
@@ -345,7 +345,7 @@ static int r600_cp_init_microcode(drm_radeon_private_t *dev_priv)
        case CHIP_RV730:
        case CHIP_RV740: chip_name = "RV730"; break;
        case CHIP_RV710: chip_name = "RV710"; break;
-       default:         panic("%s: Unsupported family %d", __func__, dev_priv->flags & RADEON_FAMILY_MASK);
+       default:         BUG();
        }
 
        if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
@@ -363,7 +363,7 @@ static int r600_cp_init_microcode(drm_radeon_private_t *dev_priv)
        if (err)
                goto out;
        if (dev_priv->pfp_fw->datasize != pfp_req_size) {
-               DRM_ERROR(
+               printk(KERN_ERR
                       "r600_cp: Bogus length %zu in firmware \"%s\"\n",
                       dev_priv->pfp_fw->datasize, fw_name);
                err = -EINVAL;
@@ -375,7 +375,7 @@ static int r600_cp_init_microcode(drm_radeon_private_t *dev_priv)
        if (err)
                goto out;
        if (dev_priv->me_fw->datasize != me_req_size) {
-               DRM_ERROR(
+               printk(KERN_ERR
                       "r600_cp: Bogus length %zu in firmware \"%s\"\n",
                       dev_priv->me_fw->datasize, fw_name);
                err = -EINVAL;
@@ -383,7 +383,7 @@ static int r600_cp_init_microcode(drm_radeon_private_t *dev_priv)
 out:
        if (err) {
                if (err != -EINVAL)
-                       DRM_ERROR(
+                       printk(KERN_ERR
                               "r600_cp: Failed to load firmware \"%s\"\n",
                               fw_name);
                release_firmware(dev_priv->pfp_fw);
@@ -414,7 +414,7 @@ static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
 
        RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
        RADEON_READ(R600_GRBM_SOFT_RESET);
-       DRM_MDELAY(15);
+       mdelay(15);
        RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
 
        fw_data = (const __be32 *)dev_priv->me_fw->data;
@@ -507,7 +507,7 @@ static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
 
        RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
        RADEON_READ(R600_GRBM_SOFT_RESET);
-       DRM_MDELAY(15);
+       mdelay(15);
        RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
 
        fw_data = (const __be32 *)dev_priv->pfp_fw->data;
@@ -1799,7 +1799,7 @@ static void r600_cp_init_ring_buffer(struct drm_device *dev,
 
        RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
        RADEON_READ(R600_GRBM_SOFT_RESET);
-       DRM_MDELAY(15);
+       mdelay(15);
        RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
 
 
index 9b2ced2..54a1d29 100644 (file)
@@ -179,7 +179,7 @@ static const struct gpu_formats color_formats_table[] = {
 
 bool r600_fmt_is_valid_color(u32 format)
 {
-       if (format >= DRM_ARRAY_SIZE(color_formats_table))
+       if (format >= ARRAY_SIZE(color_formats_table))
                return false;
 
        if (color_formats_table[format].valid_color)
@@ -190,7 +190,7 @@ bool r600_fmt_is_valid_color(u32 format)
 
 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family)
 {
-       if (format >= DRM_ARRAY_SIZE(color_formats_table))
+       if (format >= ARRAY_SIZE(color_formats_table))
                return false;
 
        if (family < color_formats_table[format].min_family)
@@ -204,7 +204,7 @@ bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family)
 
 int r600_fmt_get_blocksize(u32 format)
 {
-       if (format >= DRM_ARRAY_SIZE(color_formats_table))
+       if (format >= ARRAY_SIZE(color_formats_table))
                return 0;
 
        return color_formats_table[format].blocksize;
@@ -214,7 +214,7 @@ int r600_fmt_get_nblocksx(u32 format, u32 w)
 {
        unsigned bw;
 
-       if (format >= DRM_ARRAY_SIZE(color_formats_table))
+       if (format >= ARRAY_SIZE(color_formats_table))
                return 0;
 
        bw = color_formats_table[format].blockwidth;
@@ -228,7 +228,7 @@ int r600_fmt_get_nblocksy(u32 format, u32 h)
 {
        unsigned bh;
 
-       if (format >= DRM_ARRAY_SIZE(color_formats_table))
+       if (format >= ARRAY_SIZE(color_formats_table))
                return 0;
 
        bh = color_formats_table[format].blockheight;
@@ -651,9 +651,9 @@ static int r600_cs_track_validate_db(struct radeon_cs_parser *p)
                nby = height;
                if (G_028D24_LINEAR(track->htile_surface)) {
                        /* nbx must be 16 htiles aligned == 16 * 8 pixel aligned */
-                       nbx = roundup2(nbx, 16 * 8);
+                       nbx = round_up(nbx, 16 * 8);
                        /* nby is npipes htiles aligned == npipes * 8 pixel aligned */
-                       nby = roundup(nby, track->npipes * 8);
+                       nby = round_up(nby, track->npipes * 8);
                } else {
                        /* always assume 8x8 htile */
                        /* align is htile align * 8, htile align vary according to
@@ -662,23 +662,23 @@ static int r600_cs_track_validate_db(struct radeon_cs_parser *p)
                        switch (track->npipes) {
                        case 8:
                                /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
-                               nbx = roundup2(nbx, 64 * 8);
-                               nby = roundup2(nby, 64 * 8);
+                               nbx = round_up(nbx, 64 * 8);
+                               nby = round_up(nby, 64 * 8);
                                break;
                        case 4:
                                /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
-                               nbx = roundup2(nbx, 64 * 8);
-                               nby = roundup2(nby, 32 * 8);
+                               nbx = round_up(nbx, 64 * 8);
+                               nby = round_up(nby, 32 * 8);
                                break;
                        case 2:
                                /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
-                               nbx = roundup2(nbx, 32 * 8);
-                               nby = roundup2(nby, 32 * 8);
+                               nbx = round_up(nbx, 32 * 8);
+                               nby = round_up(nby, 32 * 8);
                                break;
                        case 1:
                                /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
-                               nbx = roundup2(nbx, 32 * 8);
-                               nby = roundup2(nby, 16 * 8);
+                               nbx = round_up(nbx, 32 * 8);
+                               nby = round_up(nby, 16 * 8);
                                break;
                        default:
                                dev_warn(p->dev, "%s:%d invalid num pipes %d\n",
@@ -933,7 +933,7 @@ static int r600_packet0_check(struct radeon_cs_parser *p,
                }
                break;
        default:
-               DRM_ERROR("Forbidden register 0x%04X in cs at %d\n",
+               printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
                       reg, idx);
                return -EINVAL;
        }
@@ -976,7 +976,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
        int r;
 
        i = (reg >> 7);
-       if (i >= DRM_ARRAY_SIZE(r600_reg_safe_bm)) {
+       if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {
                dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
                return -EINVAL;
        }
@@ -1415,11 +1415,11 @@ static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel,
                width = r600_mip_minify(w0, i);
                nbx = r600_fmt_get_nblocksx(format, width);
 
-               nbx = roundup(nbx, block_align);
+               nbx = round_up(nbx, block_align);
 
                height = r600_mip_minify(h0, i);
                nby = r600_fmt_get_nblocksy(format, height);
-               nby = roundup(nby, height_align);
+               nby = round_up(nby, height_align);
 
                depth = r600_mip_minify(d0, i);
 
@@ -1433,7 +1433,7 @@ static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel,
                        *l0_size = size;
 
                if (i == 0 || i == 1)
-                       offset = roundup(offset, base_align);
+                       offset = round_up(offset, base_align);
 
                offset += size;
        }
@@ -1600,7 +1600,7 @@ static bool r600_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
        u32 m, i;
 
        i = (reg >> 7);
-       if (i >= DRM_ARRAY_SIZE(r600_reg_safe_bm)) {
+       if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {
                dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
                return false;
        }
@@ -2261,8 +2261,7 @@ int r600_cs_parse(struct radeon_cs_parser *p)
 
        if (p->track == NULL) {
                /* initialize tracker, we are in kms */
-               track = kmalloc(sizeof(*track), M_DRM,
-                               M_ZERO | M_WAITOK);
+               track = kzalloc(sizeof(*track), GFP_KERNEL);
                if (track == NULL)
                        return -ENOMEM;
                r600_cs_track_init(track);
@@ -2280,7 +2279,7 @@ int r600_cs_parse(struct radeon_cs_parser *p)
        do {
                r = radeon_cs_packet_parse(p, &pkt, p->idx);
                if (r) {
-                       drm_free(p->track, M_DRM);
+                       kfree(p->track);
                        p->track = NULL;
                        return r;
                }
@@ -2296,12 +2295,12 @@ int r600_cs_parse(struct radeon_cs_parser *p)
                        break;
                default:
                        DRM_ERROR("Unknown packet type %d !\n", pkt.type);
-                       drm_free(p->track, M_DRM);
+                       kfree(p->track);
                        p->track = NULL;
                        return -EINVAL;
                }
                if (r) {
-                       drm_free(p->track, M_DRM);
+                       kfree(p->track);
                        p->track = NULL;
                        return r;
                }
@@ -2309,10 +2308,10 @@ int r600_cs_parse(struct radeon_cs_parser *p)
 #if 0
        for (r = 0; r < p->ib.length_dw; r++) {
                DRM_INFO("%05d  0x%08X\n", r, p->ib.ptr[r]);
-               DRM_MDELAY(1);
+               mdelay(1);
        }
 #endif
-       drm_free(p->track, M_DRM);
+       kfree(p->track);
        p->track = NULL;
        return 0;
 }
@@ -2331,17 +2330,17 @@ static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
 {
        unsigned i;
 
-       drm_free(parser->relocs, M_DRM);
+       kfree(parser->relocs);
        for (i = 0; i < parser->nchunks; i++) {
-               drm_free(parser->chunks[i].kdata, M_DRM);
+               kfree(parser->chunks[i].kdata);
                if (parser->rdev && (parser->rdev->flags & RADEON_IS_AGP)) {
-                       drm_free(parser->chunks[i].kpage[0], M_DRM);
-                       drm_free(parser->chunks[i].kpage[1], M_DRM);
+                       kfree(parser->chunks[i].kpage[0]);
+                       kfree(parser->chunks[i].kpage[1]);
                }
        }
-       drm_free(parser->chunks, M_DRM);
-       drm_free(parser->chunks_array, M_DRM);
-       drm_free(parser->track, M_DRM);
+       kfree(parser->chunks);
+       kfree(parser->chunks_array);
+       kfree(parser->track);
 }
 
 static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
@@ -2365,7 +2364,7 @@ int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
        int r;
 
        /* initialize tracker */
-       track = kmalloc(sizeof(*track), M_DRM, M_ZERO | M_WAITOK);
+       track = kzalloc(sizeof(*track), GFP_KERNEL);
        if (track == NULL)
                return -ENOMEM;
        r600_cs_track_init(track);
@@ -2619,7 +2618,7 @@ int r600_dma_cs_parse(struct radeon_cs_parser *p)
 #if 0
        for (r = 0; r < p->ib->length_dw; r++) {
                DRM_INFO("%05d  0x%08X\n", r, p->ib.ptr[r]);
-               DRM_MDELAY(1);
+               mdelay(1);
        }
 #endif
        return 0;
index 444fc2e..b972413 100644 (file)
@@ -229,7 +229,7 @@ void r600_gfx_clockgating_enable(struct radeon_device *rdev, bool enable)
                for (i = 0; i < rdev->usec_timeout; i++) {
                        if (((RREG32(CG_RLC_REQ_AND_RSP) & CG_RLC_RSP_TYPE_MASK) >> CG_RLC_RSP_TYPE_SHIFT) == 1)
                                break;
-                       DRM_UDELAY(1);
+                       udelay(1);
                }
 
                WREG32(CG_RLC_REQ_AND_RSP, 0x0);
@@ -307,7 +307,7 @@ void r600_wait_for_spll_change(struct radeon_device *rdev)
        for (i = 0; i < rdev->usec_timeout; i++) {
                if (RREG32(CG_SPLL_FUNC_CNTL) & SPLL_CHG_STATUS)
                        break;
-               DRM_UDELAY(1);
+               udelay(1);
        }
 }
 
@@ -630,13 +630,13 @@ void r600_wait_for_power_level_unequal(struct radeon_device *rdev,
        for (i = 0; i < rdev->usec_timeout; i++) {
                if (r600_power_level_get_target_index(rdev) != index)
                        break;
-               DRM_UDELAY(1);
+               udelay(1);
        }
 
        for (i = 0; i < rdev->usec_timeout; i++) {
                if (r600_power_level_get_current_index(rdev) != index)
                        break;
-               DRM_UDELAY(1);
+               udelay(1);
        }
 }
 
@@ -648,13 +648,13 @@ void r600_wait_for_power_level(struct radeon_device *rdev,
        for (i = 0; i < rdev->usec_timeout; i++) {
                if (r600_power_level_get_target_index(rdev) == index)
                        break;
-               DRM_UDELAY(1);
+               udelay(1);
        }
 
        for (i = 0; i < rdev->usec_timeout; i++) {
                if (r600_power_level_get_current_index(rdev) == index)
                        break;
-               DRM_UDELAY(1);
+               udelay(1);
        }
 }
 
index 553cd83..e1b1053 100644 (file)
@@ -133,7 +133,6 @@ static void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder,
        struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
        uint32_t offset = dig->afmt->offset;
        uint8_t *frame = (uint8_t*)buffer + 3;
-
        uint8_t *header = buffer;
 
        WREG32(HDMI0_AVI_INFO0 + offset,
index ecdca5b..6cd33ac 100644 (file)
@@ -330,7 +330,7 @@ static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a,
                return a;
        }
 
-       KASSERT(a->ring == b->ring, ("\"a\" and \"b\" belongs to different rings"));
+       BUG_ON(a->ring != b->ring);
 
        if (a->seq > b->seq) {
                return a;
@@ -350,7 +350,7 @@ static inline bool radeon_fence_is_earlier(struct radeon_fence *a,
                return true;
        }
 
-       KASSERT(a->ring == b->ring, ("\"a\" and \"b\" belongs to different rings"));
+       BUG_ON(a->ring != b->ring);
 
        return a->seq < b->seq;
 }
index 04ef85d..fc5cc15 100644 (file)
@@ -554,6 +554,7 @@ int radeon_acpi_pcie_notify_device_ready(struct radeon_device *rdev)
                return -EIO;
 
        kfree(info);
+
        return 0;
 #else
        return -EINVAL;
@@ -631,7 +632,7 @@ int radeon_acpi_pcie_performance_request(struct radeon_device *rdev,
                case ATCS_REQUEST_COMPLETE:
                        return 0;
                case ATCS_REQUEST_IN_PROGRESS:
-                       DRM_UDELAY(10);
+                       udelay(10);
                        break;
                }
        }
index d4e7e05..43ae111 100644 (file)
@@ -19,7 +19,6 @@
  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  * OTHER DEALINGS IN THE SOFTWARE.
  *
- * $FreeBSD: head/sys/dev/drm2/radeon/radeon_acpi.h 254885 2013-08-25 19:37:15Z dumbbell $
  */
 
 #ifndef RADEON_ACPI_H
index 160108b..e2b8e1a 100644 (file)
@@ -24,8 +24,6 @@
  * Authors: Dave Airlie
  *          Alex Deucher
  *          Jerome Glisse
- *
- * $FreeBSD: head/sys/dev/drm2/radeon/radeon_asic.c 254885 2013-08-25 19:37:15Z dumbbell $
  */
 
 #include <drm/drmP.h>
@@ -53,7 +51,8 @@
  */
 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
 {
-       panic("Invalid callback to read register 0x%04X\n", reg);
+       DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
+       BUG_ON(1);
        return 0;
 }
 
@@ -69,8 +68,9 @@ static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
  */
 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
 {
-       panic("Invalid callback to write register 0x%04X with 0x%08X\n",
+       DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
                  reg, v);
+       BUG_ON(1);
 }
 
 /**
index 5ff9b0f..ad65a2f 100644 (file)
  * Authors: Dave Airlie
  *          Alex Deucher
  *          Jerome Glisse
- *
- * $FreeBSD: head/sys/dev/drm2/radeon/radeon_asic.h 254885 2013-08-25 19:37:15Z dumbbell $
  */
-
 #ifndef __RADEON_ASIC_H__
 #define __RADEON_ASIC_H__
 
index 2a74a0c..49578fa 100644 (file)
@@ -899,13 +899,13 @@ bool radeon_get_atom_connector_info_from_supported_devices_table(struct
        router.ddc_valid = false;
        router.cd_valid = false;
 
-       bios_connectors = kmalloc(bc_size, M_DRM, M_WAITOK | M_ZERO);
+       bios_connectors = kzalloc(bc_size, GFP_KERNEL);
        if (!bios_connectors)
                return false;
 
        if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
                                    &data_offset)) {
-               drm_free(bios_connectors, M_DRM);
+               kfree(bios_connectors);
                return false;
        }
 
@@ -1077,7 +1077,7 @@ bool radeon_get_atom_connector_info_from_supported_devices_table(struct
 
        radeon_link_encoder_connector(dev);
 
-       drm_free(bios_connectors, M_DRM);
+       kfree(bios_connectors);
        return true;
 }
 
@@ -1551,8 +1551,7 @@ struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
                lvds_info =
                        (union lvds_info *)((char *)mode_info->atom_context->bios + data_offset);
                lvds =
-                   kmalloc(sizeof(struct radeon_encoder_atom_dig),
-                       M_DRM, M_WAITOK | M_ZERO);
+                   kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
 
                if (!lvds)
                        return NULL;
@@ -1648,8 +1647,7 @@ struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
                                                                rdev->mode_info.bios_hardcoded_edid = edid;
                                                                rdev->mode_info.bios_hardcoded_edid_size = edid_size;
                                                        } else
-                                                               drm_free(edid,
-                                                                        M_DRM);
+                                                               kfree(edid);
                                                }
                                        }
                                        record += sizeof(ATOM_FAKE_EDID_PATCH_RECORD);
@@ -1691,8 +1689,7 @@ radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
                dac_info = (struct _COMPASSIONATE_DATA *)
                        ((char *)mode_info->atom_context->bios + data_offset);
 
-               p_dac = kmalloc(sizeof(struct radeon_encoder_primary_dac),
-                   M_DRM, M_WAITOK | M_ZERO);
+               p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
 
                if (!p_dac)
                        return NULL;
@@ -1877,8 +1874,7 @@ radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
                dac_info = (struct _COMPASSIONATE_DATA *)
                        ((char *)mode_info->atom_context->bios + data_offset);
 
-               tv_dac = kmalloc(sizeof(struct radeon_encoder_tv_dac),
-                   M_DRM, M_WAITOK | M_ZERO);
+               tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
 
                if (!tv_dac)
                        return NULL;
@@ -2015,7 +2011,7 @@ static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
 
        /* add the i2c bus for thermal/fan chip */
        if ((power_info->info.ucOverdriveThermalController > 0) &&
-           (power_info->info.ucOverdriveThermalController < DRM_ARRAY_SIZE(thermal_controller_names))) {
+           (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) {
                DRM_INFO("Possible %s thermal controller at 0x%02x\n",
                         thermal_controller_names[power_info->info.ucOverdriveThermalController],
                         power_info->info.ucOverdriveControllerAddress >> 1);
@@ -2037,15 +2033,13 @@ static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
                num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
        if (num_modes == 0)
                return state_index;
-       rdev->pm.power_state = kmalloc(sizeof(struct radeon_power_state) * num_modes,
-           M_DRM, M_WAITOK | M_ZERO);
+       rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
        if (!rdev->pm.power_state)
                return state_index;
        /* last mode is usually default, array is low to high */
        for (i = 0; i < num_modes; i++) {
                rdev->pm.power_state[state_index].clock_info =
-                       kmalloc(sizeof(struct radeon_pm_clock_info) * 1,
-                           M_DRM, M_WAITOK | M_ZERO);
+                       kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
                if (!rdev->pm.power_state[state_index].clock_info)
                        return state_index;
                rdev->pm.power_state[state_index].num_clock_modes = 1;
@@ -2230,7 +2224,7 @@ static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *r
                           (controller->ucType ==
                            ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL)) {
                        DRM_INFO("Special thermal controller config\n");
-               } else if (controller->ucType < DRM_ARRAY_SIZE(pp_lib_thermal_controller_names)) {
+               } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
                        DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
                                 pp_lib_thermal_controller_names[controller->ucType],
                                 controller->ucI2cAddress >> 1,
@@ -2477,9 +2471,8 @@ static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
        radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
        if (power_info->pplib.ucNumStates == 0)
                return state_index;
-       rdev->pm.power_state = kmalloc(sizeof(struct radeon_power_state) *
-                                      power_info->pplib.ucNumStates,
-                                      M_DRM, M_WAITOK | M_ZERO);
+       rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
+                                      power_info->pplib.ucNumStates, GFP_KERNEL);
        if (!rdev->pm.power_state)
                return state_index;
        /* first mode is usually default, followed by low to high */
@@ -2494,10 +2487,10 @@ static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
                         le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
                         (power_state->v1.ucNonClockStateIndex *
                          power_info->pplib.ucNonClockSize));
-               rdev->pm.power_state[i].clock_info = kmalloc(sizeof(struct radeon_pm_clock_info) *
+               rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
                                                             ((power_info->pplib.ucStateEntrySize - 1) ?
                                                              (power_info->pplib.ucStateEntrySize - 1) : 1),
-                                                            M_DRM, M_WAITOK | M_ZERO);
+                                                            GFP_KERNEL);
                if (!rdev->pm.power_state[i].clock_info)
                        return state_index;
                if (power_info->pplib.ucStateEntrySize - 1) {
@@ -2579,9 +2572,8 @@ static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
                 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
        if (state_array->ucNumEntries == 0)
                return state_index;
-       rdev->pm.power_state = kmalloc(sizeof(struct radeon_power_state) *
-                                      state_array->ucNumEntries,
-                                      M_DRM, M_WAITOK | M_ZERO);
+       rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
+                                      state_array->ucNumEntries, GFP_KERNEL);
        if (!rdev->pm.power_state)
                return state_index;
        power_state_offset = (u8 *)state_array->states;
@@ -2591,10 +2583,10 @@ static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
                non_clock_array_index = power_state->v2.nonClockInfoIndex;
                non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
                        &non_clock_info_array->nonClockInfo[non_clock_array_index];
-               rdev->pm.power_state[i].clock_info = kmalloc(sizeof(struct radeon_pm_clock_info) *
+               rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
                                                             (power_state->v2.ucNumDPMLevels ?
                                                              power_state->v2.ucNumDPMLevels : 1),
-                                                            M_DRM, M_WAITOK | M_ZERO);
+                                                            GFP_KERNEL);
                if (!rdev->pm.power_state[i].clock_info)
                        return state_index;
                if (power_state->v2.ucNumDPMLevels) {
@@ -2671,12 +2663,10 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
        }
 
        if (state_index == 0) {
-               rdev->pm.power_state = kmalloc(sizeof(struct radeon_power_state),
-                   M_DRM, M_WAITOK | M_ZERO);
+               rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
                if (rdev->pm.power_state) {
                        rdev->pm.power_state[0].clock_info =
-                               kmalloc(sizeof(struct radeon_pm_clock_info) * 1,
-                                   M_DRM, M_WAITOK | M_ZERO);
+                               kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
                        if (rdev->pm.power_state[0].clock_info) {
                                /* add the default mode */
                                rdev->pm.power_state[state_index].type =
index d4280da..b719c43 100644 (file)
@@ -33,6 +33,7 @@
 #include "radeon.h"
 #include "atom.h"
 
+#include <linux/slab.h>
 /*
  * BIOS.
  */
@@ -195,7 +196,7 @@ static int radeon_atrm_call(ACPI_HANDLE atrm_handle, uint8_t *bios,
 
        status = AcpiEvaluateObject(atrm_handle, NULL, &atrm_arg, &buffer);
        if (ACPI_FAILURE(status)) {
-               DRM_ERROR("failed to evaluate ATRM got %s\n", AcpiFormatException(status));
+               printk("failed to evaluate ATRM got %s\n", AcpiFormatException(status));
                return -ENODEV;
        }
 
@@ -285,7 +286,7 @@ static bool radeon_atrm_get_bios(struct radeon_device *rdev)
                        DRM_INFO("%s: Incorrect BIOS signature: 0x%02X%02X\n",
                            __func__, rdev->bios[0], rdev->bios[1]);
                }
-               drm_free(rdev->bios, M_DRM);
+               kfree(rdev->bios);
                return false;
        }
        return true;
@@ -735,7 +736,7 @@ bool radeon_get_bios(struct radeon_device *rdev)
                return false;
        }
        if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
-               DRM_ERROR("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
+               printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
                goto free_bios;
        }
 
@@ -760,7 +761,7 @@ bool radeon_get_bios(struct radeon_device *rdev)
        DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
        return true;
 free_bios:
-       drm_free(rdev->bios, M_DRM);
+       kfree(rdev->bios);
        rdev->bios = NULL;
        return false;
 }
index 6020ff7..14d673f 100644 (file)
  * Authors: Dave Airlie
  *          Alex Deucher
  *          Jerome Glisse
- *
- * $FreeBSD: head/sys/dev/drm2/radeon/radeon_clocks.c 254885 2013-08-25 19:37:15Z dumbbell $
  */
-
 #include <drm/drmP.h>
 #include <uapi_drm/radeon_drm.h>
 #include "radeon_reg.h"
@@ -404,19 +401,19 @@ void radeon_legacy_set_engine_clock(struct radeon_device *rdev,
        tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
        WREG32_PLL(RADEON_SCLK_CNTL, tmp);
 
-       DRM_UDELAY(10);
+       udelay(10);
 
        tmp = RREG32_PLL(RADEON_SPLL_CNTL);
        tmp |= RADEON_SPLL_SLEEP;
        WREG32_PLL(RADEON_SPLL_CNTL, tmp);
 
-       DRM_UDELAY(2);
+       udelay(2);
 
        tmp = RREG32_PLL(RADEON_SPLL_CNTL);
        tmp |= RADEON_SPLL_RESET;
        WREG32_PLL(RADEON_SPLL_CNTL, tmp);
 
-       DRM_UDELAY(200);
+       udelay(200);
 
        tmp = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV);
        tmp &= ~(RADEON_SPLL_FB_DIV_MASK << RADEON_SPLL_FB_DIV_SHIFT);
@@ -436,13 +433,13 @@ void radeon_legacy_set_engine_clock(struct radeon_device *rdev,
        tmp &= ~RADEON_SPLL_SLEEP;
        WREG32_PLL(RADEON_SPLL_CNTL, tmp);
 
-       DRM_UDELAY(2);
+       udelay(2);
 
        tmp = RREG32_PLL(RADEON_SPLL_CNTL);
        tmp &= ~RADEON_SPLL_RESET;
        WREG32_PLL(RADEON_SPLL_CNTL, tmp);
 
-       DRM_UDELAY(200);
+       udelay(200);
 
        tmp = RREG32_PLL(RADEON_SCLK_CNTL);
        tmp &= ~RADEON_SCLK_SRC_SEL_MASK;
@@ -463,13 +460,13 @@ void radeon_legacy_set_engine_clock(struct radeon_device *rdev,
        }
        WREG32_PLL(RADEON_SCLK_CNTL, tmp);
 
-       DRM_UDELAY(20);
+       udelay(20);
 
        tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
        tmp |= RADEON_DONT_USE_XTALIN;
        WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
 
-       DRM_UDELAY(10);
+       udelay(10);
 }
 
 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
@@ -637,7 +634,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
                                tmp &= ~(R300_SCLK_FORCE_VAP);
                                tmp |= RADEON_SCLK_FORCE_CP;
                                WREG32_PLL(RADEON_SCLK_CNTL, tmp);
-                               DRM_MDELAY(15);
+                               mdelay(15);
 
                                tmp = RREG32_PLL(R300_SCLK_CNTL2);
                                tmp &= ~(R300_SCLK_FORCE_TCL |
@@ -655,12 +652,12 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
                        tmp |= (RADEON_ENGIN_DYNCLK_MODE |
                                (0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT));
                        WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp);
-                       DRM_MDELAY(15);
+                       mdelay(15);
 
                        tmp = RREG32_PLL(RADEON_CLK_PIN_CNTL);
                        tmp |= RADEON_SCLK_DYN_START_CNTL;
                        WREG32_PLL(RADEON_CLK_PIN_CNTL, tmp);
-                       DRM_MDELAY(15);
+                       mdelay(15);
 
                        /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200
                           to lockup randomly, leave them as set by BIOS.
@@ -700,7 +697,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
                                        tmp |= RADEON_SCLK_MORE_FORCEON;
                                }
                                WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
-                               DRM_MDELAY(15);
+                               mdelay(15);
                        }
 
                        /* RV200::A11 A12, RV250::A11 A12 */
@@ -713,7 +710,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
                                tmp |= RADEON_TCL_BYPASS_DISABLE;
                                WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
                        }
-                       DRM_MDELAY(15);
+                       mdelay(15);
 
                        /*enable dynamic mode for display clocks (PIXCLK and PIX2CLK) */
                        tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
@@ -726,14 +723,14 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
                                RADEON_PIXCLK_TMDS_ALWAYS_ONb);
 
                        WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
-                       DRM_MDELAY(15);
+                       mdelay(15);
 
                        tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
                        tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
                                RADEON_PIXCLK_DAC_ALWAYS_ONb);
 
                        WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
-                       DRM_MDELAY(15);
+                       mdelay(15);
                }
        } else {
                /* Turn everything OFF (ForceON to everything) */
@@ -865,7 +862,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
                        }
                        WREG32_PLL(RADEON_SCLK_CNTL, tmp);
 
-                       DRM_MDELAY(16);
+                       mdelay(16);
 
                        if ((rdev->family == CHIP_R300) ||
                            (rdev->family == CHIP_R350)) {
@@ -874,7 +871,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
                                        R300_SCLK_FORCE_GA |
                                        R300_SCLK_FORCE_CBA);
                                WREG32_PLL(R300_SCLK_CNTL2, tmp);
-                               DRM_MDELAY(16);
+                               mdelay(16);
                        }
 
                        if (rdev->flags & RADEON_IS_IGP) {
@@ -882,7 +879,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
                                tmp &= ~(RADEON_FORCEON_MCLKA |
                                         RADEON_FORCEON_YCLKA);
                                WREG32_PLL(RADEON_MCLK_CNTL, tmp);
-                               DRM_MDELAY(16);
+                               mdelay(16);
                        }
 
                        if ((rdev->family == CHIP_RV200) ||
@@ -891,7 +888,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
                                tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL);
                                tmp |= RADEON_SCLK_MORE_FORCEON;
                                WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp);
-                               DRM_MDELAY(16);
+                               mdelay(16);
                        }
 
                        tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL);
@@ -904,7 +901,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
                                 RADEON_PIXCLK_TMDS_ALWAYS_ONb);
 
                        WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
-                       DRM_MDELAY(16);
+                       mdelay(16);
 
                        tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
                        tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb |
index 29898f5..c89c83e 100644 (file)
@@ -383,7 +383,7 @@ bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
        memcpy((unsigned char *)edid, raw, size);
 
        if (!drm_edid_is_valid(edid)) {
-               drm_free(edid, M_DRM);
+               kfree(edid);
                return false;
        }
 
@@ -866,8 +866,8 @@ struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct
        struct radeon_encoder_primary_dac *p_dac = NULL;
        int found = 0;
 
-       p_dac = kmalloc(sizeof(struct radeon_encoder_primary_dac),
-                       M_DRM, M_WAITOK | M_ZERO);
+       p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),
+                       GFP_KERNEL);
 
        if (!p_dac)
                return NULL;
@@ -1017,8 +1017,7 @@ struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct
        struct radeon_encoder_tv_dac *tv_dac = NULL;
        int found = 0;
 
-       tv_dac = kmalloc(sizeof(struct radeon_encoder_tv_dac),
-                        M_DRM, M_WAITOK | M_ZERO);
+       tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
        if (!tv_dac)
                return NULL;
 
@@ -1106,8 +1105,7 @@ static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
        uint32_t ppll_div_sel, ppll_val;
        uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
 
-       lvds = kmalloc(sizeof(struct radeon_encoder_lvds), M_DRM,
-                      M_WAITOK | M_ZERO);
+       lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
 
        if (!lvds)
                return NULL;
@@ -1182,8 +1180,7 @@ struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
        lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);
 
        if (lcd_info) {
-               lvds = kmalloc(sizeof(struct radeon_encoder_lvds),
-                              M_DRM, M_WAITOK | M_ZERO);
+               lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);
 
                if (!lvds)
                        return NULL;
@@ -2640,16 +2637,13 @@ void radeon_combios_get_power_modes(struct radeon_device *rdev)
        rdev->pm.default_power_state_index = -1;
 
        /* allocate 2 power states */
-       rdev->pm.power_state = kmalloc(sizeof(struct radeon_power_state) * 2,
-                                      M_DRM, M_WAITOK | M_ZERO);
+       rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * 2, GFP_KERNEL);
        if (rdev->pm.power_state) {
                /* allocate 1 clock mode per state */
                rdev->pm.power_state[0].clock_info =
-                       kmalloc(sizeof(struct radeon_pm_clock_info) * 1,
-                               M_DRM, M_WAITOK | M_ZERO);
+                       kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
                rdev->pm.power_state[1].clock_info =
-                       kmalloc(sizeof(struct radeon_pm_clock_info) * 1,
-                               M_DRM, M_WAITOK | M_ZERO);
+                       kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
                if (!rdev->pm.power_state[0].clock_info ||
                    !rdev->pm.power_state[1].clock_info)
                        goto pm_failed;
@@ -2925,12 +2919,12 @@ bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
                                        case 3:
                                                val = RBIOS16(index);
                                                index += 2;
-                                               DRM_UDELAY(val);
+                                               udelay(val);
                                                break;
                                        case 4:
                                                val = RBIOS16(index);
                                                index += 2;
-                                               DRM_MDELAY(val);
+                                               mdelay(val);
                                                break;
                                        case 6:
                                                slave_addr = id & 0xff;
@@ -2979,7 +2973,7 @@ bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)
                                case 4:
                                        val = RBIOS16(index);
                                        index += 2;
-                                       DRM_UDELAY(val);
+                                       udelay(val);
                                        break;
                                case 5:
                                        reg = id & 0x1fff;
@@ -3057,7 +3051,7 @@ static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)
                        case 4:
                                val = RBIOS16(offset);
                                offset += 2;
-                               DRM_UDELAY(val);
+                               udelay(val);
                                break;
                        case 5:
                                val = RBIOS16(offset);
@@ -3126,10 +3120,10 @@ static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
                                tmp = 1000;
                                switch (addr) {
                                case 1:
-                                       DRM_UDELAY(150);
+                                       udelay(150);
                                        break;
                                case 2:
-                                       DRM_MDELAY(1);
+                                       mdelay(1);
                                        break;
                                case 3:
                                        while (tmp--) {
@@ -3160,13 +3154,13 @@ static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)
                                                /*mclk_cntl |= 0x00001111;*//* ??? */
                                                WREG32_PLL(RADEON_MCLK_CNTL,
                                                           mclk_cntl);
-                                               DRM_MDELAY(10);
+                                               mdelay(10);
 #endif
                                                WREG32_PLL
                                                    (RADEON_CLK_PWRMGT_CNTL,
                                                     tmp &
                                                     ~RADEON_CG_NO1_DEBUG_0);
-                                               DRM_MDELAY(10);
+                                               mdelay(10);
                                        }
                                        break;
                                default:
index 4baddc4..926863e 100644 (file)
@@ -638,13 +638,13 @@ static void radeon_connector_destroy(struct drm_connector *connector)
        struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 
        if (radeon_connector->edid)
-               drm_free(radeon_connector->edid, M_DRM);
-       drm_free(radeon_connector->con_priv, M_DRM);
+               kfree(radeon_connector->edid);
+       kfree(radeon_connector->con_priv);
 #ifdef DUMBBELL_WIP
        drm_sysfs_connector_remove(connector);
 #endif /* DUMBBELL_WIP */
        drm_connector_cleanup(connector);
-       drm_free(connector, M_DRM);
+       kfree(connector);
 }
 
 static int radeon_lvds_set_property(struct drm_connector *connector,
@@ -741,7 +741,7 @@ radeon_vga_detect(struct drm_connector *connector, bool force)
        if (dret) {
                radeon_connector->detected_by_load = false;
                if (radeon_connector->edid) {
-                       drm_free(radeon_connector->edid, M_DRM);
+                       kfree(radeon_connector->edid);
                        radeon_connector->edid = NULL;
                }
                radeon_connector->edid = drm_get_edid(&radeon_connector->base, radeon_connector->ddc_bus->adapter);
@@ -757,7 +757,7 @@ radeon_vga_detect(struct drm_connector *connector, bool force)
                         * with a shared ddc line (often vga + hdmi)
                         */
                        if (radeon_connector->use_digital && radeon_connector->shared_ddc) {
-                               drm_free(radeon_connector->edid, M_DRM);
+                               kfree(radeon_connector->edid);
                                radeon_connector->edid = NULL;
                                ret = connector_status_disconnected;
                        } else
@@ -947,7 +947,7 @@ radeon_dvi_detect(struct drm_connector *connector, bool force)
        if (dret) {
                radeon_connector->detected_by_load = false;
                if (radeon_connector->edid) {
-                       drm_free(radeon_connector->edid, M_DRM);
+                       kfree(radeon_connector->edid);
                        radeon_connector->edid = NULL;
                }
                radeon_connector->edid = drm_get_edid(&radeon_connector->base, radeon_connector->ddc_bus->adapter);
@@ -972,7 +972,7 @@ radeon_dvi_detect(struct drm_connector *connector, bool force)
                         * with a shared ddc line (often vga + hdmi)
                         */
                        if ((!radeon_connector->use_digital) && radeon_connector->shared_ddc) {
-                               drm_free(radeon_connector->edid, M_DRM);
+                               kfree(radeon_connector->edid);
                                radeon_connector->edid = NULL;
                                ret = connector_status_disconnected;
                        } else
@@ -997,8 +997,7 @@ radeon_dvi_detect(struct drm_connector *connector, bool force)
                                                if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
                                                        /* hpd is our only option in this case */
                                                        if (!radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) {
-                                                               drm_free(radeon_connector->edid,
-                                                                        M_DRM);
+                                                               kfree(radeon_connector->edid);
                                                                radeon_connector->edid = NULL;
                                                                ret = connector_status_disconnected;
                                                        }
@@ -1207,15 +1206,15 @@ static void radeon_dp_connector_destroy(struct drm_connector *connector)
        struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
 
        if (radeon_connector->edid)
-               drm_free(radeon_connector->edid, M_DRM);
+               kfree(radeon_connector->edid);
        if (radeon_dig_connector->dp_i2c_bus)
                radeon_i2c_destroy(radeon_dig_connector->dp_i2c_bus);
-       drm_free(radeon_connector->con_priv, M_DRM);
+       kfree(radeon_connector->con_priv);
 #ifdef DUMBBELL_WIP
        drm_sysfs_connector_remove(connector);
 #endif /* DUMBBELL_WIP */
        drm_connector_cleanup(connector);
-       drm_free(connector, M_DRM);
+       kfree(connector);
 }
 
 static int radeon_dp_get_modes(struct drm_connector *connector)
@@ -1366,7 +1365,7 @@ radeon_dp_detect(struct drm_connector *connector, bool force)
                return connector->status;
 
        if (radeon_connector->edid) {
-               drm_free(radeon_connector->edid, M_DRM);
+               kfree(radeon_connector->edid);
                radeon_connector->edid = NULL;
        }
 
@@ -1554,8 +1553,7 @@ radeon_add_atom_connector(struct drm_device *dev,
                }
        }
 
-       radeon_connector = kmalloc(sizeof(struct radeon_connector),
-                                  M_DRM, M_ZERO | M_WAITOK);
+       radeon_connector = kzalloc(sizeof(struct radeon_connector), GFP_KERNEL);
        if (!radeon_connector)
                return;
 
@@ -1575,8 +1573,7 @@ radeon_add_atom_connector(struct drm_device *dev,
        }
 
        if (is_dp_bridge) {
-               radeon_dig_connector = kmalloc(sizeof(struct radeon_connector_atom_dig),
-                                                       M_DRM, M_ZERO | M_WAITOK);
+               radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
                if (!radeon_dig_connector)
                        goto failed;
                radeon_dig_connector->igp_lane_info = igp_lane_info;
@@ -1682,8 +1679,7 @@ radeon_add_atom_connector(struct drm_device *dev,
                        break;
                case DRM_MODE_CONNECTOR_DVII:
                case DRM_MODE_CONNECTOR_DVID:
-                       radeon_dig_connector = kmalloc(sizeof(struct radeon_connector_atom_dig),
-                                                              M_DRM, M_ZERO | M_WAITOK);
+                       radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
                        if (!radeon_dig_connector)
                                goto failed;
                        radeon_dig_connector->igp_lane_info = igp_lane_info;
@@ -1724,8 +1720,7 @@ radeon_add_atom_connector(struct drm_device *dev,
                        break;
                case DRM_MODE_CONNECTOR_HDMIA:
                case DRM_MODE_CONNECTOR_HDMIB:
-                       radeon_dig_connector = kmalloc(sizeof(struct radeon_connector_atom_dig),
-                                                               M_DRM, M_ZERO | M_WAITOK);
+                       radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
                        if (!radeon_dig_connector)
                                goto failed;
                        radeon_dig_connector->igp_lane_info = igp_lane_info;
@@ -1759,8 +1754,7 @@ radeon_add_atom_connector(struct drm_device *dev,
                                connector->doublescan_allowed = false;
                        break;
                case DRM_MODE_CONNECTOR_DisplayPort:
-                       radeon_dig_connector = kmalloc(sizeof(struct radeon_connector_atom_dig),
-                                                      M_DRM, M_ZERO | M_WAITOK);
+                       radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
                        if (!radeon_dig_connector)
                                goto failed;
                        radeon_dig_connector->igp_lane_info = igp_lane_info;
@@ -1796,8 +1790,7 @@ radeon_add_atom_connector(struct drm_device *dev,
                        connector->doublescan_allowed = false;
                        break;
                case DRM_MODE_CONNECTOR_eDP:
-                       radeon_dig_connector = kmalloc(sizeof(struct radeon_connector_atom_dig),
-                                                               M_DRM, M_ZERO | M_WAITOK);
+                       radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
                        if (!radeon_dig_connector)
                                goto failed;
                        radeon_dig_connector->igp_lane_info = igp_lane_info;
@@ -1838,9 +1831,7 @@ radeon_add_atom_connector(struct drm_device *dev,
                        connector->doublescan_allowed = false;
                        break;
                case DRM_MODE_CONNECTOR_LVDS:
-                       radeon_dig_connector = kmalloc(sizeof(struct radeon_connector_atom_dig),
-                                                      M_DRM,
-                                                      M_ZERO | M_WAITOK);
+                       radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
                        if (!radeon_dig_connector)
                                goto failed;
                        radeon_dig_connector->igp_lane_info = igp_lane_info;
@@ -1912,8 +1903,7 @@ radeon_add_legacy_connector(struct drm_device *dev,
                }
        }
 
-       radeon_connector = kmalloc(sizeof(struct radeon_connector),
-                                  M_DRM, M_ZERO | M_WAITOK);
+       radeon_connector = kzalloc(sizeof(struct radeon_connector), GFP_KERNEL);
        if (!radeon_connector)
                return;
 
index ca08d65..e86f95a 100644 (file)
@@ -529,10 +529,10 @@ static int radeon_cp_init_microcode(drm_radeon_private_t *dev_priv)
 
        err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev);
        if (err) {
-               DRM_ERROR("radeon_cp: Failed to load firmware \"%s\"\n",
+               printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
                       fw_name);
        } else if (dev_priv->me_fw->datasize % 8) {
-               DRM_ERROR(
+               printk(KERN_ERR
                       "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
                       dev_priv->me_fw->datasize, fw_name);
                err = -EINVAL;
@@ -2069,8 +2069,7 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
        drm_radeon_private_t *dev_priv;
        int ret = 0;
 
-       dev_priv = kmalloc(sizeof(drm_radeon_private_t), M_DRM,
-                          M_ZERO | M_WAITOK);
+       dev_priv = kzalloc(sizeof(drm_radeon_private_t), GFP_KERNEL);
        if (dev_priv == NULL)
                return -ENOMEM;
 
@@ -2129,8 +2128,7 @@ int radeon_master_create(struct drm_device *dev, struct drm_master *master)
        unsigned long sareapage;
        int ret;
 
-       master_priv = kmalloc(sizeof(*master_priv), M_DRM,
-                             M_ZERO | M_WAITOK);
+       master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
        if (!master_priv)
                return -ENOMEM;
 
@@ -2140,7 +2138,7 @@ int radeon_master_create(struct drm_device *dev, struct drm_master *master)
                         &master_priv->sarea);
        if (ret) {
                DRM_ERROR("SAREA setup failed\n");
-               drm_free(master_priv, M_DRM);
+               kfree(master_priv);
                return ret;
        }
        master_priv->sarea_priv = (drm_radeon_sarea_t *)((char *)master_priv->sarea->handle) +
@@ -2170,7 +2168,7 @@ void radeon_master_destroy(struct drm_device *dev, struct drm_master *master)
                drm_rmmap(dev, master_priv->sarea);
 #endif
 
-       drm_free(master_priv, M_DRM);
+       kfree(master_priv);
 
        master->driver_priv = NULL;
 }
@@ -2204,7 +2202,7 @@ int radeon_driver_unload(struct drm_device *dev)
 
        drm_rmmap(dev, dev_priv->mmio);
 
-       drm_free(dev_priv, M_DRM);
+       kfree(dev_priv);
 
        dev->dev_private = NULL;
        return 0;
index 36ceace..54dab4b 100644 (file)
@@ -46,13 +46,11 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
        p->dma_reloc_idx = 0;
        /* FIXME: we assume that each relocs use 4 dwords */
        p->nrelocs = chunk->length_dw / 4;
-       p->relocs_ptr = kmalloc(p->nrelocs * sizeof(void *), M_DRM,
-                               M_ZERO | M_WAITOK);
+       p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
        if (p->relocs_ptr == NULL) {
                return -ENOMEM;
        }
-       p->relocs = kmalloc(p->nrelocs * sizeof(struct radeon_cs_reloc),
-                           M_DRM, M_ZERO | M_WAITOK);
+       p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
        if (p->relocs == NULL) {
                return -ENOMEM;
        }
@@ -188,8 +186,7 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
        p->chunk_relocs_idx = -1;
        p->chunk_flags_idx = -1;
        p->chunk_const_ib_idx = -1;
-       p->chunks_array = kmalloc(cs->num_chunks * sizeof(uint64_t),
-                                 M_DRM, M_ZERO | M_WAITOK);
+       p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
        if (p->chunks_array == NULL) {
                return -ENOMEM;
        }
@@ -200,8 +197,7 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
        }
        p->cs_flags = 0;
        p->nchunks = cs->num_chunks;
-       p->chunks = kmalloc(p->nchunks * sizeof(struct radeon_cs_chunk),
-                           M_DRM, M_ZERO | M_WAITOK);
+       p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
        if (p->chunks == NULL) {
                return -ENOMEM;
        }
@@ -301,10 +297,8 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
                                                                      M_WAITOK);
                        if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL ||
                            p->chunks[p->chunk_ib_idx].kpage[1] == NULL) {
-                               drm_free(p->chunks[p->chunk_ib_idx].kpage[0],
-                                        M_DRM);
-                               drm_free(p->chunks[p->chunk_ib_idx].kpage[1],
-                                        M_DRM);
+                               kfree(p->chunks[p->chunk_ib_idx].kpage[0]);
+                               kfree(p->chunks[p->chunk_ib_idx].kpage[1]);
                                p->chunks[p->chunk_ib_idx].kpage[0] = NULL;
                                p->chunks[p->chunk_ib_idx].kpage[1] = NULL;
                                return -ENOMEM;
@@ -345,18 +339,18 @@ static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
                                drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
                }
        }
-       drm_free(parser->track, M_DRM);
-       drm_free(parser->relocs, M_DRM);
-       drm_free(parser->relocs_ptr, M_DRM);
+       kfree(parser->track);
+       kfree(parser->relocs);
+       kfree(parser->relocs_ptr);
        for (i = 0; i < parser->nchunks; i++) {
-               drm_free(parser->chunks[i].kdata, M_DRM);
+               kfree(parser->chunks[i].kdata);
                if ((parser->rdev->flags & RADEON_IS_AGP)) {
-                       drm_free(parser->chunks[i].kpage[0], M_DRM);
-                       drm_free(parser->chunks[i].kpage[1], M_DRM);
+                       kfree(parser->chunks[i].kpage[0]);
+                       kfree(parser->chunks[i].kpage[1]);
                }
        }
-       drm_free(parser->chunks, M_DRM);
-       drm_free(parser->chunks_array, M_DRM);
+       kfree(parser->chunks);
+       kfree(parser->chunks_array);
        radeon_ib_free(parser->rdev, &parser->ib);
        radeon_ib_free(parser->rdev, &parser->const_ib);
 }
index 883f674..8f81175 100644 (file)
  *
  * Authors: Dave Airlie
  *          Alex Deucher
- *
- * $FreeBSD: head/sys/dev/drm2/radeon/radeon_cursor.c 254885 2013-08-25 19:37:15Z dumbbell $
  */
-
 #include <drm/drmP.h>
 #include <uapi_drm/radeon_drm.h>
 #include "radeon.h"
@@ -278,9 +275,7 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc,
                                cursor_end = x - xorigin + w;
                                if (!(cursor_end & 0x7f)) {
                                        x--;
-                                       if (x < 0) {
-                                               DRM_ERROR("%s: x(%d) < 0", __func__, x);
-                                       }
+                                       WARN_ON_ONCE(x < 0);
                                }
                        }
                }
index 6e02607..d404638 100644 (file)
@@ -27,7 +27,6 @@
  *
  * $FreeBSD: head/sys/dev/drm2/radeon/radeon_device.c 255573 2013-09-14 17:24:41Z dumbbell $
  */
-
 #include <drm/drmP.h>
 #include <drm/drm_crtc_helper.h>
 #include <uapi_drm/radeon_drm.h>
@@ -860,8 +859,7 @@ static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
 int radeon_atombios_init(struct radeon_device *rdev)
 {
        struct card_info *atom_card_info =
-           kmalloc(sizeof(struct card_info), M_DRM,
-                   M_ZERO | M_WAITOK);
+           kzalloc(sizeof(struct card_info), GFP_KERNEL);
 
        if (!atom_card_info)
                return -ENOMEM;
@@ -909,11 +907,11 @@ int radeon_atombios_init(struct radeon_device *rdev)
 void radeon_atombios_fini(struct radeon_device *rdev)
 {
        if (rdev->mode_info.atom_context) {
-               drm_free(rdev->mode_info.atom_context->scratch, M_DRM);
+               kfree(rdev->mode_info.atom_context->scratch);
        }
-       drm_free(rdev->mode_info.atom_context, M_DRM);
+       kfree(rdev->mode_info.atom_context);
        rdev->mode_info.atom_context = NULL;
-       drm_free(rdev->mode_info.atom_card_info, M_DRM);
+       kfree(rdev->mode_info.atom_card_info);
        rdev->mode_info.atom_card_info = NULL;
 }
 
@@ -1638,7 +1636,7 @@ retry:
        } else {
                radeon_fence_driver_force_completion(rdev);
                for (i = 0; i < RADEON_NUM_RINGS; ++i) {
-                       drm_free(ring_data[i], M_DRM);
+                       kfree(ring_data[i]);
                }
        }
 
index e48b22b..416b98c 100644 (file)
@@ -249,7 +249,7 @@ static void radeon_crtc_destroy(struct drm_crtc *crtc)
        struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 
        drm_crtc_cleanup(crtc);
-       drm_free(radeon_crtc, M_DRM);
+       kfree(radeon_crtc);
 }
 
 /*
@@ -272,7 +272,7 @@ static void radeon_unpin_work_func(void *arg, int pending)
                DRM_ERROR("failed to reserve buffer after flip\n");
 
        drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
-       drm_free(work, M_DRM);
+       kfree(work);
 }
 
 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
@@ -361,7 +361,7 @@ static int radeon_crtc_page_flip(struct drm_crtc *crtc,
        u64 base;
        int r;
 
-       work = kmalloc(sizeof *work, M_DRM, M_WAITOK | M_ZERO);
+       work = kzalloc(sizeof *work, GFP_KERNEL);
        if (work == NULL)
                return -ENOMEM;
 
@@ -489,7 +489,7 @@ unlock_free:
        lockmgr(&dev->event_lock, LK_RELEASE);
        drm_gem_object_unreference_unlocked(old_radeon_fb->obj);
        radeon_fence_unref(&work->fence);
-       drm_free(work, M_DRM);
+       kfree(work);
 
        return r;
 }
@@ -509,8 +509,7 @@ static void radeon_crtc_init(struct drm_device *dev, int index)
        struct radeon_crtc *radeon_crtc;
        int i;
 
-       radeon_crtc = kmalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)),
-                             M_DRM, M_WAITOK | M_ZERO);
+       radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
        if (radeon_crtc == NULL)
                return;
 
@@ -1074,7 +1073,7 @@ static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
                drm_gem_object_unreference_unlocked(radeon_fb->obj);
        }
        drm_framebuffer_cleanup(fb);
-       drm_free(radeon_fb, M_DRM);
+       kfree(radeon_fb);
 }
 
 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
@@ -1124,8 +1123,7 @@ radeon_user_framebuffer_create(struct drm_device *dev,
                return ERR_PTR(-ENOENT);
        }
 
-       radeon_fb = kmalloc(sizeof(*radeon_fb), M_DRM,
-                           M_WAITOK | M_ZERO);
+       radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
        if (radeon_fb == NULL) {
                drm_gem_object_unreference_unlocked(obj);
                return ERR_PTR(-ENOMEM);
@@ -1186,7 +1184,7 @@ static int radeon_modeset_create_props(struct radeon_device *rdev)
        }
 
        if (!ASIC_IS_AVIVO(rdev)) {
-               sz = DRM_ARRAY_SIZE(radeon_tmds_pll_enum_list);
+               sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
                rdev->mode_info.tmds_pll_property =
                        drm_property_create_enum(rdev->ddev, 0,
                                            "tmds_pll",
@@ -1200,13 +1198,13 @@ static int radeon_modeset_create_props(struct radeon_device *rdev)
 
        drm_mode_create_scaling_mode_property(rdev->ddev);
 
-       sz = DRM_ARRAY_SIZE(radeon_tv_std_enum_list);
+       sz = ARRAY_SIZE(radeon_tv_std_enum_list);
        rdev->mode_info.tv_std_property =
                drm_property_create_enum(rdev->ddev, 0,
                                    "tv standard",
                                    radeon_tv_std_enum_list, sz);
 
-       sz = DRM_ARRAY_SIZE(radeon_underscan_enum_list);
+       sz = ARRAY_SIZE(radeon_underscan_enum_list);
        rdev->mode_info.underscan_property =
                drm_property_create_enum(rdev->ddev, 0,
                                    "underscan",
@@ -1262,45 +1260,33 @@ static void radeon_afmt_init(struct radeon_device *rdev)
        } else if (ASIC_IS_DCE4(rdev)) {
                /* DCE4/5 has 6 audio blocks tied to DIG encoders */
                /* DCE4.1 has 2 audio blocks tied to DIG encoders */
-               rdev->mode_info.afmt[0] = kmalloc(sizeof(struct radeon_afmt),
-                                                 M_DRM,
-                                                 M_WAITOK | M_ZERO);
+               rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
                if (rdev->mode_info.afmt[0]) {
                        rdev->mode_info.afmt[0]->offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
                        rdev->mode_info.afmt[0]->id = 0;
                }
-               rdev->mode_info.afmt[1] = kmalloc(sizeof(struct radeon_afmt),
-                                                 M_DRM,
-                                                 M_WAITOK | M_ZERO);
+               rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
                if (rdev->mode_info.afmt[1]) {
                        rdev->mode_info.afmt[1]->offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
                        rdev->mode_info.afmt[1]->id = 1;
                }
                if (!ASIC_IS_DCE41(rdev)) {
-                       rdev->mode_info.afmt[2] = kmalloc(sizeof(struct radeon_afmt),
-                                                         M_DRM,
-                                                         M_WAITOK | M_ZERO);
+                       rdev->mode_info.afmt[2] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
                        if (rdev->mode_info.afmt[2]) {
                                rdev->mode_info.afmt[2]->offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
                                rdev->mode_info.afmt[2]->id = 2;
                        }
-                       rdev->mode_info.afmt[3] = kmalloc(sizeof(struct radeon_afmt),
-                                                         M_DRM,
-                                                         M_WAITOK | M_ZERO);
+                       rdev->mode_info.afmt[3] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
                        if (rdev->mode_info.afmt[3]) {
                                rdev->mode_info.afmt[3]->offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
                                rdev->mode_info.afmt[3]->id = 3;
                        }
-                       rdev->mode_info.afmt[4] = kmalloc(sizeof(struct radeon_afmt),
-                                                         M_DRM,
-                                                         M_WAITOK | M_ZERO);
+                       rdev->mode_info.afmt[4] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
                        if (rdev->mode_info.afmt[4]) {
                                rdev->mode_info.afmt[4]->offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
                                rdev->mode_info.afmt[4]->id = 4;
                        }
-                       rdev->mode_info.afmt[5] = kmalloc(sizeof(struct radeon_afmt),
-                                                         M_DRM,
-                                                         M_WAITOK | M_ZERO);
+                       rdev->mode_info.afmt[5] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
                        if (rdev->mode_info.afmt[5]) {
                                rdev->mode_info.afmt[5]->offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
                                rdev->mode_info.afmt[5]->id = 5;
@@ -1308,34 +1294,26 @@ static void radeon_afmt_init(struct radeon_device *rdev)
                }
        } else if (ASIC_IS_DCE3(rdev)) {
                /* DCE3.x has 2 audio blocks tied to DIG encoders */
-               rdev->mode_info.afmt[0] = kmalloc(sizeof(struct radeon_afmt),
-                                                 M_DRM,
-                                                 M_WAITOK | M_ZERO);
+               rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
                if (rdev->mode_info.afmt[0]) {
                        rdev->mode_info.afmt[0]->offset = DCE3_HDMI_OFFSET0;
                        rdev->mode_info.afmt[0]->id = 0;
                }
-               rdev->mode_info.afmt[1] = kmalloc(sizeof(struct radeon_afmt),
-                                                 M_DRM,
-                                                 M_WAITOK | M_ZERO);
+               rdev->mode_info.afmt[1] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
                if (rdev->mode_info.afmt[1]) {
                        rdev->mode_info.afmt[1]->offset = DCE3_HDMI_OFFSET1;
                        rdev->mode_info.afmt[1]->id = 1;
                }
        } else if (ASIC_IS_DCE2(rdev)) {
                /* DCE2 has at least 1 routable audio block */
-               rdev->mode_info.afmt[0] = kmalloc(sizeof(struct radeon_afmt),
-                                                 M_DRM,
-                                                 M_WAITOK | M_ZERO);
+               rdev->mode_info.afmt[0] = kzalloc(sizeof(struct radeon_afmt), GFP_KERNEL);
                if (rdev->mode_info.afmt[0]) {
                        rdev->mode_info.afmt[0]->offset = DCE2_HDMI_OFFSET0;
              &nbs