From 345bb66db3d808671c811aa59e09450cdf5bf368 Mon Sep 17 00:00:00 2001 From: Sepherosa Ziehau Date: Thu, 13 Jul 2006 08:46:40 +0000 Subject: [PATCH] Initial import of Atheros Hardware Access Layer (HAL) version 0.9.16.16 --- sys/contrib/dev/ath/COPYRIGHT | 42 + sys/contrib/dev/ath/README | 54 + sys/contrib/dev/ath/ah.h | 841 +++ sys/contrib/dev/ath/ah_desc.h | 181 + sys/contrib/dev/ath/ah_devid.h | 93 + sys/contrib/dev/ath/dragonfly/ah_if.m | 90 + sys/contrib/dev/ath/dragonfly/ah_osdep.c | 417 ++ sys/contrib/dev/ath/dragonfly/ah_osdep.h | 127 + sys/contrib/dev/ath/public/amd64-elf.hal.o.uu | 5791 +++++++++++++++++ sys/contrib/dev/ath/public/amd64-elf.inc | 63 + sys/contrib/dev/ath/public/amd64-elf.opt_ah.h | 7 + sys/contrib/dev/ath/public/i386-elf.hal.o.uu | 4420 +++++++++++++ sys/contrib/dev/ath/public/i386-elf.inc | 58 + sys/contrib/dev/ath/public/i386-elf.opt_ah.h | 7 + sys/contrib/dev/ath/version.h | 38 + 15 files changed, 12229 insertions(+) create mode 100644 sys/contrib/dev/ath/COPYRIGHT create mode 100644 sys/contrib/dev/ath/README create mode 100644 sys/contrib/dev/ath/ah.h create mode 100644 sys/contrib/dev/ath/ah_desc.h create mode 100644 sys/contrib/dev/ath/ah_devid.h create mode 100644 sys/contrib/dev/ath/dragonfly/ah_if.m create mode 100644 sys/contrib/dev/ath/dragonfly/ah_osdep.c create mode 100644 sys/contrib/dev/ath/dragonfly/ah_osdep.h create mode 100644 sys/contrib/dev/ath/public/amd64-elf.hal.o.uu create mode 100644 sys/contrib/dev/ath/public/amd64-elf.inc create mode 100644 sys/contrib/dev/ath/public/amd64-elf.opt_ah.h create mode 100644 sys/contrib/dev/ath/public/i386-elf.hal.o.uu create mode 100644 sys/contrib/dev/ath/public/i386-elf.inc create mode 100644 sys/contrib/dev/ath/public/i386-elf.opt_ah.h create mode 100644 sys/contrib/dev/ath/version.h diff --git a/sys/contrib/dev/ath/COPYRIGHT b/sys/contrib/dev/ath/COPYRIGHT new file mode 100644 index 0000000000..6eb7b76a52 --- /dev/null +++ b/sys/contrib/dev/ath/COPYRIGHT @@ -0,0 +1,42 @@ +All files contained in this distribution are covered by the following +copyright unless explicitly identified otherwise. Note that this +copyright does _NOT_ contain a "or GPL" clause and does _NOT_ permit +redistribution with changes. + +/*- + * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting, Atheros + * Communications, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the following conditions are met: + * 1. The materials contained herein are unmodified and are used + * unmodified. + * 2. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following NO + * ''WARRANTY'' disclaimer below (''Disclaimer''), without + * modification. + * 3. Redistributions in binary form must reproduce at minimum a + * disclaimer similar to the Disclaimer below and any redistribution + * must be conditioned upon including a substantially similar + * Disclaimer requirement for further binary redistribution. + * 4. Neither the names of the above-listed copyright holders nor the + * names of any contributors may be used to endorse or promote + * product derived from this software without specific prior written + * permission. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, + * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE + * FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGES. + * + * $Id: //depot/sw/linuxsrc/src/802_11/madwifi/hal/main/COPYRIGHT#5 $ + */ diff --git a/sys/contrib/dev/ath/README b/sys/contrib/dev/ath/README new file mode 100644 index 0000000000..027e48f341 --- /dev/null +++ b/sys/contrib/dev/ath/README @@ -0,0 +1,54 @@ +$Id: //depot/sw/linuxsrc/src/802_11/madwifi/hal/main/README#5 $ + + +Atheros Hardware Access Layer (HAL) +=================================== + +* Copyright (c) 2002-2006 Sam Leffler. +* Copyright (c) 2002-2006 Atheros Communications, Inc. +* All rights reserved. + +Read the file COPYRIGHT for the complete copyright. + +This code manages much of the chip-specific operation of the Atheros +driver. The HAL is provided in a binary-only form in order to +comply with local regulatory agency rules. In the United States +the FCC requires that a radio transmitter only be operated at power +levels and on frequency channels for which it is approved. The FCC +requires that a software-defined radio cannot be configured by a +user to operate outside the approved power levels and frequency +channels. This makes it difficult to open-source code that enforces +limits on the power levels, frequency channels and other parameters +of the radio transmitter. See + +http://ftp.fcc.gov/Bureaus/Engineering_Technology/Orders/2001/fcc01264.pdf + +for the specific FCC regulation. Because the module is provided +in a binary-only form it is marked "Proprietary" on Linux; this +means when you load it you will see messages that your system is +now "tainted". + +If you wish to use this driver on a platform for which an ath_hal +module is not already provided please contact the author. Note that +this is only necessary for new _architectures_; the HAL is not tied to +any specific version of your operating system. + + +Atheros Hardware +================ +There are many generations of Atheros 802.11 wireless devices that +are typically referred to by their programming model: + +5210 supports 11a only +5211 supports both 11a and 11b +5212 supports 11a, 11b, and 11g + +These parts have been incorporated in a variety of retail products +including cardbus cards and mini-pci cards. In addition many laptop +vendors use Atheros mini-pci cards for their builtin wireless +support. + +The Atheors PCI vendor id is 0x168c. The file ah_devid.h lists most +known PCI device id's but is not exhaustive. Some vendors program +their own vendor and/or device id's to aid in BIOS-locking mini-pci +cards in laptops. diff --git a/sys/contrib/dev/ath/ah.h b/sys/contrib/dev/ath/ah.h new file mode 100644 index 0000000000..72380b7ce5 --- /dev/null +++ b/sys/contrib/dev/ath/ah.h @@ -0,0 +1,841 @@ +/*- + * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting, Atheros + * Communications, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the following conditions are met: + * 1. The materials contained herein are unmodified and are used + * unmodified. + * 2. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following NO + * ''WARRANTY'' disclaimer below (''Disclaimer''), without + * modification. + * 3. Redistributions in binary form must reproduce at minimum a + * disclaimer similar to the Disclaimer below and any redistribution + * must be conditioned upon including a substantially similar + * Disclaimer requirement for further binary redistribution. + * 4. Neither the names of the above-listed copyright holders nor the + * names of any contributors may be used to endorse or promote + * product derived from this software without specific prior written + * permission. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, + * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE + * FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGES. + * + * $Id: //depot/sw/linuxsrc/src/802_11/madwifi/hal/main/ah.h#134 $ + */ + +#ifndef _ATH_AH_H_ +#define _ATH_AH_H_ +/* + * Atheros Hardware Access Layer + * + * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal + * structure for use with the device. Hardware-related operations that + * follow must call back into the HAL through interface, supplying the + * reference as the first parameter. + */ +#include "ah_osdep.h" + +/* + * __ahdecl is analogous to _cdecl; it defines the calling + * convention used within the HAL. For most systems this + * can just default to be empty and the compiler will (should) + * use _cdecl. For systems where _cdecl is not compatible this + * must be defined. See linux/ah_osdep.h for an example. + */ +#ifndef __ahdecl +#define __ahdecl +#endif + +/* + * Status codes that may be returned by the HAL. Note that + * interfaces that return a status code set it only when an + * error occurs--i.e. you cannot check it for success. + */ +typedef enum { + HAL_OK = 0, /* No error */ + HAL_ENXIO = 1, /* No hardware present */ + HAL_ENOMEM = 2, /* Memory allocation failed */ + HAL_EIO = 3, /* Hardware didn't respond as expected */ + HAL_EEMAGIC = 4, /* EEPROM magic number invalid */ + HAL_EEVERSION = 5, /* EEPROM version invalid */ + HAL_EELOCKED = 6, /* EEPROM unreadable */ + HAL_EEBADSUM = 7, /* EEPROM checksum invalid */ + HAL_EEREAD = 8, /* EEPROM read problem */ + HAL_EEBADMAC = 9, /* EEPROM mac address invalid */ + HAL_EESIZE = 10, /* EEPROM size not supported */ + HAL_EEWRITE = 11, /* Attempt to change write-locked EEPROM */ + HAL_EINVAL = 12, /* Invalid parameter to function */ + HAL_ENOTSUPP = 13, /* Hardware revision not supported */ + HAL_ESELFTEST = 14, /* Hardware self-test failed */ + HAL_EINPROGRESS = 15, /* Operation incomplete */ +} HAL_STATUS; + +typedef enum { + AH_FALSE = 0, /* NB: lots of code assumes false is zero */ + AH_TRUE = 1, +} HAL_BOOL; + +typedef enum { + HAL_CAP_REG_DMN = 0, /* current regulatory domain */ + HAL_CAP_CIPHER = 1, /* hardware supports cipher */ + HAL_CAP_TKIP_MIC = 2, /* handle TKIP MIC in hardware */ + HAL_CAP_TKIP_SPLIT = 3, /* hardware TKIP uses split keys */ + HAL_CAP_PHYCOUNTERS = 4, /* hardware PHY error counters */ + HAL_CAP_DIVERSITY = 5, /* hardware supports fast diversity */ + HAL_CAP_KEYCACHE_SIZE = 6, /* number of entries in key cache */ + HAL_CAP_NUM_TXQUEUES = 7, /* number of hardware xmit queues */ + HAL_CAP_VEOL = 9, /* hardware supports virtual EOL */ + HAL_CAP_PSPOLL = 10, /* hardware has working PS-Poll support */ + HAL_CAP_DIAG = 11, /* hardware diagnostic support */ + HAL_CAP_COMPRESSION = 12, /* hardware supports compression */ + HAL_CAP_BURST = 13, /* hardware supports packet bursting */ + HAL_CAP_FASTFRAME = 14, /* hardware supoprts fast frames */ + HAL_CAP_TXPOW = 15, /* global tx power limit */ + HAL_CAP_TPC = 16, /* per-packet tx power control */ + HAL_CAP_PHYDIAG = 17, /* hardware phy error diagnostic */ + HAL_CAP_BSSIDMASK = 18, /* hardware supports bssid mask */ + HAL_CAP_MCAST_KEYSRCH = 19, /* hardware has multicast key search */ + HAL_CAP_TSF_ADJUST = 20, /* hardware has beacon tsf adjust */ + HAL_CAP_XR = 21, /* hardware has XR support */ + HAL_CAP_WME_TKIPMIC = 22, /* hardware can support TKIP MIC when WMM is turned on */ + HAL_CAP_CHAN_HALFRATE = 23, /* hardware can support half rate channels */ + HAL_CAP_CHAN_QUARTERRATE = 24, /* hardware can support quarter rate channels */ + HAL_CAP_RFSILENT = 25, /* hardware has rfsilent support */ + HAL_CAP_TPC_ACK = 26, /* ack txpower with per-packet tpc */ + HAL_CAP_TPC_CTS = 27, /* cts txpower with per-packet tpc */ + HAL_CAP_11D = 28, /* 11d beacon support for changing cc */ +} HAL_CAPABILITY_TYPE; + +/* + * "States" for setting the LED. These correspond to + * the possible 802.11 operational states and there may + * be a many-to-one mapping between these states and the + * actual hardware state for the LED's (i.e. the hardware + * may have fewer states). + */ +typedef enum { + HAL_LED_INIT = 0, + HAL_LED_SCAN = 1, + HAL_LED_AUTH = 2, + HAL_LED_ASSOC = 3, + HAL_LED_RUN = 4 +} HAL_LED_STATE; + +/* + * Transmit queue types/numbers. These are used to tag + * each transmit queue in the hardware and to identify a set + * of transmit queues for operations such as start/stop dma. + */ +typedef enum { + HAL_TX_QUEUE_INACTIVE = 0, /* queue is inactive/unused */ + HAL_TX_QUEUE_DATA = 1, /* data xmit q's */ + HAL_TX_QUEUE_BEACON = 2, /* beacon xmit q */ + HAL_TX_QUEUE_CAB = 3, /* "crap after beacon" xmit q */ + HAL_TX_QUEUE_UAPSD = 4, /* u-apsd power save xmit q */ +} HAL_TX_QUEUE; + +#define HAL_NUM_TX_QUEUES 10 /* max possible # of queues */ + +/* + * Transmit queue subtype. These map directly to + * WME Access Categories (except for UPSD). Refer + * to Table 5 of the WME spec. + */ +typedef enum { + HAL_WME_AC_BK = 0, /* background access category */ + HAL_WME_AC_BE = 1, /* best effort access category*/ + HAL_WME_AC_VI = 2, /* video access category */ + HAL_WME_AC_VO = 3, /* voice access category */ + HAL_WME_UPSD = 4, /* uplink power save */ + HAL_XR_DATA = 5, /* uplink power save */ +} HAL_TX_QUEUE_SUBTYPE; + +/* + * Transmit queue flags that control various + * operational parameters. + */ +typedef enum { + /* + * Per queue interrupt enables. When set the associated + * interrupt may be delivered for packets sent through + * the queue. Without these enabled no interrupts will + * be delivered for transmits through the queue. + */ + HAL_TXQ_TXOKINT_ENABLE = 0x0001, /* enable TXOK interrupt */ + HAL_TXQ_TXERRINT_ENABLE = 0x0001, /* enable TXERR interrupt */ + HAL_TXQ_TXDESCINT_ENABLE = 0x0002, /* enable TXDESC interrupt */ + HAL_TXQ_TXEOLINT_ENABLE = 0x0004, /* enable TXEOL interrupt */ + HAL_TXQ_TXURNINT_ENABLE = 0x0008, /* enable TXURN interrupt */ + /* + * Enable hardware compression for packets sent through + * the queue. The compression buffer must be setup and + * packets must have a key entry marked in the tx descriptor. + */ + HAL_TXQ_COMPRESSION_ENABLE = 0x0010, /* enable h/w compression */ + /* + * Disable queue when veol is hit or ready time expires. + * By default the queue is disabled only on reaching the + * physical end of queue (i.e. a null link ptr in the + * descriptor chain). + */ + HAL_TXQ_RDYTIME_EXP_POLICY_ENABLE = 0x0020, + /* + * Schedule frames on delivery of a DBA (DMA Beacon Alert) + * event. Frames will be transmitted only when this timer + * fires, e.g to transmit a beacon in ap or adhoc modes. + */ + HAL_TXQ_DBA_GATED = 0x0040, /* schedule based on DBA */ + /* + * Each transmit queue has a counter that is incremented + * each time the queue is enabled and decremented when + * the list of frames to transmit is traversed (or when + * the ready time for the queue expires). This counter + * must be non-zero for frames to be scheduled for + * transmission. The following controls disable bumping + * this counter under certain conditions. Typically this + * is used to gate frames based on the contents of another + * queue (e.g. CAB traffic may only follow a beacon frame). + * These are meaningful only when frames are scheduled + * with a non-ASAP policy (e.g. DBA-gated). + */ + HAL_TXQ_CBR_DIS_QEMPTY = 0x0080, /* disable on this q empty */ + HAL_TXQ_CBR_DIS_BEMPTY = 0x0100, /* disable on beacon q empty */ + + /* + * Fragment burst backoff policy. Normally the no backoff + * is done after a successful transmission, the next fragment + * is sent at SIFS. If this flag is set backoff is done + * after each fragment, regardless whether it was ack'd or + * not, after the backoff count reaches zero a normal channel + * access procedure is done before the next transmit (i.e. + * wait AIFS instead of SIFS). + */ + HAL_TXQ_FRAG_BURST_BACKOFF_ENABLE = 0x00800000, + /* + * Disable post-tx backoff following each frame. + */ + HAL_TXQ_BACKOFF_DISABLE = 0x00010000, /* disable post backoff */ + /* + * DCU arbiter lockout control. This controls how + * lower priority tx queues are handled with respect to + * to a specific queue when multiple queues have frames + * to send. No lockout means lower priority queues arbitrate + * concurrently with this queue. Intra-frame lockout + * means lower priority queues are locked out until the + * current frame transmits (e.g. including backoffs and bursting). + * Global lockout means nothing lower can arbitrary so + * long as there is traffic activity on this queue (frames, + * backoff, etc). + */ + HAL_TXQ_ARB_LOCKOUT_INTRA = 0x00020000, /* intra-frame lockout */ + HAL_TXQ_ARB_LOCKOUT_GLOBAL = 0x00040000, /* full lockout s */ + + HAL_TXQ_IGNORE_VIRTCOL = 0x00080000, /* ignore virt collisions */ + HAL_TXQ_SEQNUM_INC_DIS = 0x00100000, /* disable seqnum increment */ +} HAL_TX_QUEUE_FLAGS; + +typedef struct { + u_int32_t tqi_ver; /* hal TXQ version */ + HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* subtype if applicable */ + HAL_TX_QUEUE_FLAGS tqi_qflags; /* flags (see above) */ + u_int32_t tqi_priority; /* (not used) */ + u_int32_t tqi_aifs; /* aifs */ + u_int32_t tqi_cwmin; /* cwMin */ + u_int32_t tqi_cwmax; /* cwMax */ + u_int16_t tqi_shretry; /* rts retry limit */ + u_int16_t tqi_lgretry; /* long retry limit (not used)*/ + u_int32_t tqi_cbrPeriod; /* CBR period (us) */ + u_int32_t tqi_cbrOverflowLimit; /* threshold for CBROVF int */ + u_int32_t tqi_burstTime; /* max burst duration (us) */ + u_int32_t tqi_readyTime; /* frame schedule time (us) */ + u_int32_t tqi_compBuf; /* comp buffer phys addr */ +} HAL_TXQ_INFO; + +#define HAL_TQI_NONVAL 0xffff + +/* token to use for aifs, cwmin, cwmax */ +#define HAL_TXQ_USEDEFAULT ((u_int32_t) -1) + +/* compression definitions */ +#define HAL_COMP_BUF_MAX_SIZE 9216 /* 9K */ +#define HAL_COMP_BUF_ALIGN_SIZE 512 +#define HAL_DECOMP_MASK_SIZE 128 + + +/* + * Transmit packet types. This belongs in ah_desc.h, but + * is here so we can give a proper type to various parameters + * (and not require everyone include the file). + * + * NB: These values are intentionally assigned for + * direct use when setting up h/w descriptors. + */ +typedef enum { + HAL_PKT_TYPE_NORMAL = 0, + HAL_PKT_TYPE_ATIM = 1, + HAL_PKT_TYPE_PSPOLL = 2, + HAL_PKT_TYPE_BEACON = 3, + HAL_PKT_TYPE_PROBE_RESP = 4, + HAL_PKT_TYPE_CHIRP = 5, + HAL_PKT_TYPE_GRP_POLL = 6, +} HAL_PKT_TYPE; + +/* Rx Filter Frame Types */ +typedef enum { + HAL_RX_FILTER_UCAST = 0x00000001, /* Allow unicast frames */ + HAL_RX_FILTER_MCAST = 0x00000002, /* Allow multicast frames */ + HAL_RX_FILTER_BCAST = 0x00000004, /* Allow broadcast frames */ + HAL_RX_FILTER_CONTROL = 0x00000008, /* Allow control frames */ + HAL_RX_FILTER_BEACON = 0x00000010, /* Allow beacon frames */ + HAL_RX_FILTER_PROM = 0x00000020, /* Promiscuous mode */ + HAL_RX_FILTER_XRPOLL = 0x00000040, /* Allow XR poll frmae */ + HAL_RX_FILTER_PROBEREQ = 0x00000080, /* Allow probe request frames */ + HAL_RX_FILTER_PHYERR = 0x00000100, /* Allow phy errors */ + HAL_RX_FILTER_PHYRADAR = 0x00000200, /* Allow phy radar errors*/ +} HAL_RX_FILTER; + +typedef enum { + HAL_PM_AWAKE = 0, + HAL_PM_FULL_SLEEP = 1, + HAL_PM_NETWORK_SLEEP = 2, + HAL_PM_UNDEFINED = 3 +} HAL_POWER_MODE; + +/* + * NOTE WELL: + * These are mapped to take advantage of the common locations for many of + * the bits on all of the currently supported MAC chips. This is to make + * the ISR as efficient as possible, while still abstracting HW differences. + * When new hardware breaks this commonality this enumerated type, as well + * as the HAL functions using it, must be modified. All values are directly + * mapped unless commented otherwise. + */ +typedef enum { + HAL_INT_RX = 0x00000001, /* Non-common mapping */ + HAL_INT_RXDESC = 0x00000002, + HAL_INT_RXNOFRM = 0x00000008, + HAL_INT_RXEOL = 0x00000010, + HAL_INT_RXORN = 0x00000020, + HAL_INT_TX = 0x00000040, /* Non-common mapping */ + HAL_INT_TXDESC = 0x00000080, + HAL_INT_TXURN = 0x00000800, + HAL_INT_MIB = 0x00001000, + HAL_INT_RXPHY = 0x00004000, + HAL_INT_RXKCM = 0x00008000, + HAL_INT_SWBA = 0x00010000, + HAL_INT_BMISS = 0x00040000, + HAL_INT_BNR = 0x00100000, /* Non-common mapping */ + HAL_INT_TIM = 0x00200000, /* Non-common mapping */ + HAL_INT_DTIM = 0x00400000, /* Non-common mapping */ + HAL_INT_DTIMSYNC= 0x00800000, /* Non-common mapping */ + HAL_INT_GPIO = 0x01000000, + HAL_INT_CABEND = 0x02000000, /* Non-common mapping */ + HAL_INT_FATAL = 0x40000000, /* Non-common mapping */ + HAL_INT_GLOBAL = 0x80000000, /* Set/clear IER */ + HAL_INT_BMISC = HAL_INT_TIM + | HAL_INT_DTIM + | HAL_INT_DTIMSYNC + | HAL_INT_CABEND, + + /* Interrupt bits that map directly to ISR/IMR bits */ + HAL_INT_COMMON = HAL_INT_RXNOFRM + | HAL_INT_RXDESC + | HAL_INT_RXEOL + | HAL_INT_RXORN + | HAL_INT_TXURN + | HAL_INT_TXDESC + | HAL_INT_MIB + | HAL_INT_RXPHY + | HAL_INT_RXKCM + | HAL_INT_SWBA + | HAL_INT_BMISS + | HAL_INT_GPIO, + HAL_INT_NOCARD = 0xffffffff /* To signal the card was removed */ +} HAL_INT; + +typedef enum { + HAL_RFGAIN_INACTIVE = 0, + HAL_RFGAIN_READ_REQUESTED = 1, + HAL_RFGAIN_NEED_CHANGE = 2 +} HAL_RFGAIN; + +/* + * Channels are specified by frequency. + */ +typedef struct { + u_int16_t channel; /* setting in Mhz */ + u_int16_t channelFlags; /* see below */ + u_int8_t privFlags; + int8_t maxRegTxPower; /* max regulatory tx power in dBm */ + int8_t maxTxPower; /* max true tx power in 0.25 dBm */ + int8_t minTxPower; /* min true tx power in 0.25 dBm */ +} HAL_CHANNEL; + +/* channelFlags */ +#define CHANNEL_CW_INT 0x0002 /* CW interference detected on channel */ +#define CHANNEL_TURBO 0x0010 /* Turbo Channel */ +#define CHANNEL_CCK 0x0020 /* CCK channel */ +#define CHANNEL_OFDM 0x0040 /* OFDM channel */ +#define CHANNEL_2GHZ 0x0080 /* 2 GHz spectrum channel. */ +#define CHANNEL_5GHZ 0x0100 /* 5 GHz spectrum channel */ +#define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed in the channel */ +#define CHANNEL_DYN 0x0400 /* dynamic CCK-OFDM channel */ +#define CHANNEL_XR 0x0800 /* XR channel */ +#define CHANNEL_STURBO 0x2000 /* Static turbo, no 11a-only usage */ +#define CHANNEL_HALF 0x4000 /* Half rate channel */ +#define CHANNEL_QUARTER 0x8000 /* Quarter rate channel */ + +/* privFlags */ +#define CHANNEL_INTERFERENCE 0x01 /* Software use: channel interference + used for as AR as well as RADAR + interference detection */ +#define CHANNEL_DFS 0x02 /* DFS required on channel */ +#define CHANNEL_4MS_LIMIT 0x04 /* 4msec packet limit on this channel */ +#define CHANNEL_DFS_CLEAR 0x08 /* if channel has been checked for DFS */ + +#define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) +#define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) +#define CHANNEL_PUREG (CHANNEL_2GHZ|CHANNEL_OFDM) +#ifdef notdef +#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_DYN) +#else +#define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) +#endif +#define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO) +#define CHANNEL_ST (CHANNEL_T|CHANNEL_STURBO) +#define CHANNEL_108G (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO) +#define CHANNEL_108A CHANNEL_T +#define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) +#define CHANNEL_ALL \ + (CHANNEL_OFDM|CHANNEL_CCK| CHANNEL_2GHZ | CHANNEL_5GHZ | CHANNEL_TURBO) +#define CHANNEL_ALL_NOTURBO (CHANNEL_ALL &~ CHANNEL_TURBO) + +#define HAL_ANTENNA_MIN_MODE 0 +#define HAL_ANTENNA_FIXED_A 1 +#define HAL_ANTENNA_FIXED_B 2 +#define HAL_ANTENNA_MAX_MODE 3 + +typedef struct { + u_int32_t ackrcv_bad; + u_int32_t rts_bad; + u_int32_t rts_good; + u_int32_t fcs_bad; + u_int32_t beacons; +} HAL_MIB_STATS; + +typedef u_int16_t HAL_CTRY_CODE; /* country code */ +typedef u_int16_t HAL_REG_DOMAIN; /* regulatory domain code */ + +enum { + CTRY_DEBUG = 0x1ff, /* debug country code */ + CTRY_DEFAULT = 0 /* default country code */ +}; + +enum { + HAL_MODE_11A = 0x001, /* 11a channels */ + HAL_MODE_TURBO = 0x002, /* 11a turbo-only channels */ + HAL_MODE_11B = 0x004, /* 11b channels */ + HAL_MODE_PUREG = 0x008, /* 11g channels (OFDM only) */ +#ifdef notdef + HAL_MODE_11G = 0x010, /* 11g channels (OFDM/CCK) */ +#else + HAL_MODE_11G = 0x008, /* XXX historical */ +#endif + HAL_MODE_108G = 0x020, /* 11a+Turbo channels */ + HAL_MODE_108A = 0x040, /* 11g+Turbo channels */ + HAL_MODE_XR = 0x100, /* XR channels */ + HAL_MODE_11A_HALF_RATE = 0x200, /* 11A half rate channels */ + HAL_MODE_11A_QUARTER_RATE = 0x400, /* 11A quarter rate channels */ + HAL_MODE_ALL = 0xfff +}; + +typedef struct { + int rateCount; /* NB: for proper padding */ + u_int8_t rateCodeToIndex[32]; /* back mapping */ + struct { + u_int8_t valid; /* valid for rate control use */ + u_int8_t phy; /* CCK/OFDM/XR */ + u_int16_t rateKbps; /* transfer rate in kbs */ + u_int8_t rateCode; /* rate for h/w descriptors */ + u_int8_t shortPreamble; /* mask for enabling short + * preamble in CCK rate code */ + u_int8_t dot11Rate; /* value for supported rates + * info element of MLME */ + u_int8_t controlRate; /* index of next lower basic + * rate; used for dur. calcs */ + u_int16_t lpAckDuration; /* long preamble ACK duration */ + u_int16_t spAckDuration; /* short preamble ACK duration*/ + } info[32]; +} HAL_RATE_TABLE; + +typedef struct { + u_int rs_count; /* number of valid entries */ + u_int8_t rs_rates[32]; /* rates */ +} HAL_RATE_SET; + +typedef enum { + HAL_ANT_VARIABLE = 0, /* variable by programming */ + HAL_ANT_FIXED_A = 1, /* fixed to 11a frequencies */ + HAL_ANT_FIXED_B = 2, /* fixed to 11b frequencies */ +} HAL_ANT_SETTING; + +typedef enum { + HAL_M_STA = 1, /* infrastructure station */ + HAL_M_IBSS = 0, /* IBSS (adhoc) station */ + HAL_M_HOSTAP = 6, /* Software Access Point */ + HAL_M_MONITOR = 8 /* Monitor mode */ +} HAL_OPMODE; + +typedef struct { + u_int8_t kv_type; /* one of HAL_CIPHER */ + u_int8_t kv_pad; + u_int16_t kv_len; /* length in bits */ + u_int8_t kv_val[16]; /* enough for 128-bit keys */ + u_int8_t kv_mic[8]; /* TKIP MIC key */ +} HAL_KEYVAL; + +typedef enum { + HAL_CIPHER_WEP = 0, + HAL_CIPHER_AES_OCB = 1, + HAL_CIPHER_AES_CCM = 2, + HAL_CIPHER_CKIP = 3, + HAL_CIPHER_TKIP = 4, + HAL_CIPHER_CLR = 5, /* no encryption */ + + HAL_CIPHER_MIC = 127 /* TKIP-MIC, not a cipher */ +} HAL_CIPHER; + +enum { + HAL_SLOT_TIME_9 = 9, + HAL_SLOT_TIME_20 = 20, +}; + +/* + * Per-station beacon timer state. Note that the specified + * beacon interval (given in TU's) can also include flags + * to force a TSF reset and to enable the beacon xmit logic. + * If bs_cfpmaxduration is non-zero the hardware is setup to + * coexist with a PCF-capable AP. + */ +typedef struct { + u_int32_t bs_nexttbtt; /* next beacon in TU */ + u_int32_t bs_nextdtim; /* next DTIM in TU */ + u_int32_t bs_intval; /* beacon interval+flags */ +#define HAL_BEACON_PERIOD 0x0000ffff /* beacon interval period */ +#define HAL_BEACON_ENA 0x00800000 /* beacon xmit enable */ +#define HAL_BEACON_RESET_TSF 0x01000000 /* clear TSF */ + u_int32_t bs_dtimperiod; + u_int16_t bs_cfpperiod; /* CFP period in TU */ + u_int16_t bs_cfpmaxduration; /* max CFP duration in TU */ + u_int32_t bs_cfpnext; /* next CFP in TU */ + u_int16_t bs_timoffset; /* byte offset to TIM bitmap */ + u_int16_t bs_bmissthreshold; /* beacon miss threshold */ + u_int32_t bs_sleepduration; /* max sleep duration */ +} HAL_BEACON_STATE; + +/* + * Per-node statistics maintained by the driver for use in + * optimizing signal quality and other operational aspects. + */ +typedef struct { + u_int32_t ns_avgbrssi; /* average beacon rssi */ + u_int32_t ns_avgrssi; /* average data rssi */ + u_int32_t ns_avgtxrssi; /* average tx rssi */ +} HAL_NODE_STATS; + +#define HAL_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */ + +struct ath_desc; + +/* + * Hardware Access Layer (HAL) API. + * + * Clients of the HAL call ath_hal_attach to obtain a reference to an + * ath_hal structure for use with the device. Hardware-related operations + * that follow must call back into the HAL through interface, supplying + * the reference as the first parameter. Note that before using the + * reference returned by ath_hal_attach the caller should verify the + * ABI version number. + */ +struct ath_hal { + u_int32_t ah_magic; /* consistency check magic number */ + u_int32_t ah_abi; /* HAL ABI version */ +#define HAL_ABI_VERSION 0x05122200 /* YYMMDDnn */ + u_int16_t ah_devid; /* PCI device ID */ + u_int16_t ah_subvendorid; /* PCI subvendor ID */ + HAL_SOFTC ah_sc; /* back pointer to driver/os state */ + HAL_BUS_TAG ah_st; /* params for register r+w */ + HAL_BUS_HANDLE ah_sh; + HAL_CTRY_CODE ah_countryCode; + + u_int32_t ah_macVersion; /* MAC version id */ + u_int16_t ah_macRev; /* MAC revision */ + u_int16_t ah_phyRev; /* PHY revision */ + /* NB: when only one radio is present the rev is in 5Ghz */ + u_int16_t ah_analog5GhzRev;/* 5GHz radio revision */ + u_int16_t ah_analog2GhzRev;/* 2GHz radio revision */ + u_int8_t ah_decompMask[HAL_DECOMP_MASK_SIZE]; /* decomp mask array */ + const HAL_RATE_TABLE *__ahdecl(*ah_getRateTable)(struct ath_hal *, + u_int mode); + void __ahdecl(*ah_detach)(struct ath_hal*); + + /* Reset functions */ + HAL_BOOL __ahdecl(*ah_reset)(struct ath_hal *, HAL_OPMODE, + HAL_CHANNEL *, HAL_BOOL bChannelChange, + HAL_STATUS *status); + HAL_BOOL __ahdecl(*ah_phyDisable)(struct ath_hal *); + void __ahdecl(*ah_setPCUConfig)(struct ath_hal *); + HAL_BOOL __ahdecl(*ah_perCalibration)(struct ath_hal*, HAL_CHANNEL *, HAL_BOOL *); + HAL_BOOL __ahdecl(*ah_setTxPowerLimit)(struct ath_hal *, u_int32_t); + + void __ahdecl(*ah_arEnable)(struct ath_hal *); + void __ahdecl(*ah_arDisable)(struct ath_hal *); + void __ahdecl(*ah_arReset)(struct ath_hal *); + HAL_BOOL __ahdecl(*ah_radarHaveEvent)(struct ath_hal *); + HAL_BOOL __ahdecl(*ah_processDfs)(struct ath_hal *, HAL_CHANNEL *); + u_int32_t __ahdecl(*ah_dfsNolCheck)(struct ath_hal *, HAL_CHANNEL *, u_int32_t); + HAL_BOOL __ahdecl(*ah_radarWait)(struct ath_hal *, HAL_CHANNEL *); + + /* Transmit functions */ + HAL_BOOL __ahdecl(*ah_updateTxTrigLevel)(struct ath_hal*, + HAL_BOOL incTrigLevel); + int __ahdecl(*ah_setupTxQueue)(struct ath_hal *, HAL_TX_QUEUE, + const HAL_TXQ_INFO *qInfo); + HAL_BOOL __ahdecl(*ah_setTxQueueProps)(struct ath_hal *, int q, + const HAL_TXQ_INFO *qInfo); + HAL_BOOL __ahdecl(*ah_getTxQueueProps)(struct ath_hal *, int q, + HAL_TXQ_INFO *qInfo); + HAL_BOOL __ahdecl(*ah_releaseTxQueue)(struct ath_hal *ah, u_int q); + HAL_BOOL __ahdecl(*ah_resetTxQueue)(struct ath_hal *ah, u_int q); + u_int32_t __ahdecl(*ah_getTxDP)(struct ath_hal*, u_int); + HAL_BOOL __ahdecl(*ah_setTxDP)(struct ath_hal*, u_int, u_int32_t txdp); + u_int32_t __ahdecl(*ah_numTxPending)(struct ath_hal *, u_int q); + HAL_BOOL __ahdecl(*ah_startTxDma)(struct ath_hal*, u_int); + HAL_BOOL __ahdecl(*ah_stopTxDma)(struct ath_hal*, u_int); + HAL_BOOL __ahdecl(*ah_setupTxDesc)(struct ath_hal *, struct ath_desc *, + u_int pktLen, u_int hdrLen, + HAL_PKT_TYPE type, u_int txPower, + u_int txRate0, u_int txTries0, + u_int keyIx, u_int antMode, u_int flags, + u_int rtsctsRate, u_int rtsctsDuration, + u_int compicvLen, u_int compivLen, + u_int comp); + HAL_BOOL __ahdecl(*ah_setupXTxDesc)(struct ath_hal *, struct ath_desc*, + u_int txRate1, u_int txTries1, + u_int txRate2, u_int txTries2, + u_int txRate3, u_int txTries3); + HAL_BOOL __ahdecl(*ah_fillTxDesc)(struct ath_hal *, struct ath_desc *, + u_int segLen, HAL_BOOL firstSeg, + HAL_BOOL lastSeg, const struct ath_desc *); + HAL_STATUS __ahdecl(*ah_procTxDesc)(struct ath_hal *, struct ath_desc*); + void __ahdecl(*ah_getTxIntrQueue)(struct ath_hal *, u_int32_t *); + void __ahdecl(*ah_reqTxIntrDesc)(struct ath_hal *, struct ath_desc*); + + /* Receive Functions */ + u_int32_t __ahdecl(*ah_getRxDP)(struct ath_hal*); + void __ahdecl(*ah_setRxDP)(struct ath_hal*, u_int32_t rxdp); + void __ahdecl(*ah_enableReceive)(struct ath_hal*); + HAL_BOOL __ahdecl(*ah_stopDmaReceive)(struct ath_hal*); + void __ahdecl(*ah_startPcuReceive)(struct ath_hal*); + void __ahdecl(*ah_stopPcuReceive)(struct ath_hal*); + void __ahdecl(*ah_setMulticastFilter)(struct ath_hal*, + u_int32_t filter0, u_int32_t filter1); + HAL_BOOL __ahdecl(*ah_setMulticastFilterIndex)(struct ath_hal*, + u_int32_t index); + HAL_BOOL __ahdecl(*ah_clrMulticastFilterIndex)(struct ath_hal*, + u_int32_t index); + u_int32_t __ahdecl(*ah_getRxFilter)(struct ath_hal*); + void __ahdecl(*ah_setRxFilter)(struct ath_hal*, u_int32_t); + HAL_BOOL __ahdecl(*ah_setupRxDesc)(struct ath_hal *, struct ath_desc *, + u_int32_t size, u_int flags); + HAL_STATUS __ahdecl(*ah_procRxDesc)(struct ath_hal *, struct ath_desc *, + u_int32_t phyAddr, struct ath_desc *next, + u_int64_t tsf); + void __ahdecl(*ah_rxMonitor)(struct ath_hal *, + const HAL_NODE_STATS *, HAL_CHANNEL *); + void __ahdecl(*ah_procMibEvent)(struct ath_hal *, + const HAL_NODE_STATS *); + + /* Misc Functions */ + HAL_STATUS __ahdecl(*ah_getCapability)(struct ath_hal *, + HAL_CAPABILITY_TYPE, u_int32_t capability, + u_int32_t *result); + HAL_BOOL __ahdecl(*ah_setCapability)(struct ath_hal *, + HAL_CAPABILITY_TYPE, u_int32_t capability, + u_int32_t setting, HAL_STATUS *); + HAL_BOOL __ahdecl(*ah_getDiagState)(struct ath_hal *, int request, + const void *args, u_int32_t argsize, + void **result, u_int32_t *resultsize); + void __ahdecl(*ah_getMacAddress)(struct ath_hal *, u_int8_t *); + HAL_BOOL __ahdecl(*ah_setMacAddress)(struct ath_hal *, const u_int8_t*); + void __ahdecl(*ah_getBssIdMask)(struct ath_hal *, u_int8_t *); + HAL_BOOL __ahdecl(*ah_setBssIdMask)(struct ath_hal *, const u_int8_t*); + HAL_BOOL __ahdecl(*ah_setRegulatoryDomain)(struct ath_hal*, + u_int16_t, HAL_STATUS *); + void __ahdecl(*ah_setLedState)(struct ath_hal*, HAL_LED_STATE); + void __ahdecl(*ah_writeAssocid)(struct ath_hal*, + const u_int8_t *bssid, u_int16_t assocId); + HAL_BOOL __ahdecl(*ah_gpioCfgOutput)(struct ath_hal *, u_int32_t gpio); + HAL_BOOL __ahdecl(*ah_gpioCfgInput)(struct ath_hal *, u_int32_t gpio); + u_int32_t __ahdecl(*ah_gpioGet)(struct ath_hal *, u_int32_t gpio); + HAL_BOOL __ahdecl(*ah_gpioSet)(struct ath_hal *, + u_int32_t gpio, u_int32_t val); + void __ahdecl(*ah_gpioSetIntr)(struct ath_hal*, u_int, u_int32_t); + u_int32_t __ahdecl(*ah_getTsf32)(struct ath_hal*); + u_int64_t __ahdecl(*ah_getTsf64)(struct ath_hal*); + void __ahdecl(*ah_resetTsf)(struct ath_hal*); + HAL_BOOL __ahdecl(*ah_detectCardPresent)(struct ath_hal*); + void __ahdecl(*ah_updateMibCounters)(struct ath_hal*, + HAL_MIB_STATS*); + HAL_RFGAIN __ahdecl(*ah_getRfGain)(struct ath_hal*); + u_int __ahdecl(*ah_getDefAntenna)(struct ath_hal*); + void __ahdecl(*ah_setDefAntenna)(struct ath_hal*, u_int); + HAL_BOOL __ahdecl(*ah_setSlotTime)(struct ath_hal*, u_int); + u_int __ahdecl(*ah_getSlotTime)(struct ath_hal*); + HAL_BOOL __ahdecl(*ah_setAckTimeout)(struct ath_hal*, u_int); + u_int __ahdecl(*ah_getAckTimeout)(struct ath_hal*); + HAL_BOOL __ahdecl(*ah_setCTSTimeout)(struct ath_hal*, u_int); + u_int __ahdecl(*ah_getCTSTimeout)(struct ath_hal*); + HAL_BOOL __ahdecl(*ah_setDecompMask)(struct ath_hal*, u_int16_t, int); + void __ahdecl(*ah_setCoverageClass)(struct ath_hal*, u_int8_t, int); + + + /* Key Cache Functions */ + u_int32_t __ahdecl(*ah_getKeyCacheSize)(struct ath_hal*); + HAL_BOOL __ahdecl(*ah_resetKeyCacheEntry)(struct ath_hal*, u_int16_t); + HAL_BOOL __ahdecl(*ah_isKeyCacheEntryValid)(struct ath_hal *, + u_int16_t); + HAL_BOOL __ahdecl(*ah_setKeyCacheEntry)(struct ath_hal*, + u_int16_t, const HAL_KEYVAL *, + const u_int8_t *, int); + HAL_BOOL __ahdecl(*ah_setKeyCacheEntryMac)(struct ath_hal*, + u_int16_t, const u_int8_t *); + + /* Power Management Functions */ + HAL_BOOL __ahdecl(*ah_setPowerMode)(struct ath_hal*, + HAL_POWER_MODE mode, int setChip); + HAL_POWER_MODE __ahdecl(*ah_getPowerMode)(struct ath_hal*); + int16_t __ahdecl(*ah_getChanNoise)(struct ath_hal *, HAL_CHANNEL *); + + + /* Beacon Management Functions */ + void __ahdecl(*ah_beaconInit)(struct ath_hal *, + u_int32_t nexttbtt, u_int32_t intval); + void __ahdecl(*ah_setStationBeaconTimers)(struct ath_hal*, + const HAL_BEACON_STATE *); + void __ahdecl(*ah_resetStationBeaconTimers)(struct ath_hal*); + HAL_BOOL __ahdecl(*ah_waitForBeaconDone)(struct ath_hal *, + HAL_BUS_ADDR); + + /* Interrupt functions */ + HAL_BOOL __ahdecl(*ah_isInterruptPending)(struct ath_hal*); + HAL_BOOL __ahdecl(*ah_getPendingInterrupts)(struct ath_hal*, HAL_INT*); + HAL_INT __ahdecl(*ah_getInterrupts)(struct ath_hal*); + HAL_INT __ahdecl(*ah_setInterrupts)(struct ath_hal*, HAL_INT); +}; + +/* + * Check the PCI vendor ID and device ID against Atheros' values + * and return a printable description for any Atheros hardware. + * AH_NULL is returned if the ID's do not describe Atheros hardware. + */ +extern const char *__ahdecl ath_hal_probe(u_int16_t vendorid, u_int16_t devid); + +/* + * Attach the HAL for use with the specified device. The device is + * defined by the PCI device ID. The caller provides an opaque pointer + * to an upper-layer data structure (HAL_SOFTC) that is stored in the + * HAL state block for later use. Hardware register accesses are done + * using the specified bus tag and handle. On successful return a + * reference to a state block is returned that must be supplied in all + * subsequent HAL calls. Storage associated with this reference is + * dynamically allocated and must be freed by calling the ah_detach + * method when the client is done. If the attach operation fails a + * null (AH_NULL) reference will be returned and a status code will + * be returned if the status parameter is non-zero. + */ +extern struct ath_hal * __ahdecl ath_hal_attach(u_int16_t devid, HAL_SOFTC, + HAL_BUS_TAG, HAL_BUS_HANDLE, HAL_STATUS* status); + +/* + * Set the Vendor ID for Vendor SKU's which can modify the + * channel properties returned by ath_hal_init_channels. + * Return AH_TRUE if set succeeds + */ + +extern HAL_BOOL __ahdecl ath_hal_setvendor(struct ath_hal *, u_int32_t ); + +/* + * Return a list of channels available for use with the hardware. + * The list is based on what the hardware is capable of, the specified + * country code, the modeSelect mask, and whether or not outdoor + * channels are to be permitted. + * + * The channel list is returned in the supplied array. maxchans + * defines the maximum size of this array. nchans contains the actual + * number of channels returned. If a problem occurred or there were + * no channels that met the criteria then AH_FALSE is returned. + */ +extern HAL_BOOL __ahdecl ath_hal_init_channels(struct ath_hal *, + HAL_CHANNEL *chans, u_int maxchans, u_int *nchans, + u_int8_t *regclassids, u_int maxregids, u_int *nregids, + HAL_CTRY_CODE cc, u_int16_t modeSelect, + HAL_BOOL enableOutdoor, HAL_BOOL enableExtendedChannels); + +/* + * Calibrate noise floor data following a channel scan or similar. + * This must be called prior retrieving noise floor data. + */ +extern void __ahdecl ath_hal_process_noisefloor(struct ath_hal *ah); + +/* + * Return bit mask of wireless modes supported by the hardware. + */ +extern u_int __ahdecl ath_hal_getwirelessmodes(struct ath_hal*, HAL_CTRY_CODE); + +/* + * Return rate table for specified mode (11a, 11b, 11g, etc). + */ +extern const HAL_RATE_TABLE * __ahdecl ath_hal_getratetable(struct ath_hal *, + u_int mode); + +/* + * Calculate the transmit duration of a frame. + */ +extern u_int16_t __ahdecl ath_hal_computetxtime(struct ath_hal *, + const HAL_RATE_TABLE *rates, u_int32_t frameLen, + u_int16_t rateix, HAL_BOOL shortPreamble); + +/* + * Return if device is public safety. + */ +extern HAL_BOOL __ahdecl ath_hal_ispublicsafetysku(struct ath_hal *); + +/* + * Convert between IEEE channel number and channel frequency + * using the specified channel flags; e.g. CHANNEL_2GHZ. + */ +extern int __ahdecl ath_hal_mhz2ieee(struct ath_hal *, u_int mhz, u_int flags); + +/* + * Return a version string for the HAL release. + */ +extern char ath_hal_version[]; +/* + * Return a NULL-terminated array of build/configuration options. + */ +extern const char* ath_hal_buildopts[]; +#endif /* _ATH_AH_H_ */ diff --git a/sys/contrib/dev/ath/ah_desc.h b/sys/contrib/dev/ath/ah_desc.h new file mode 100644 index 0000000000..6431487b7a --- /dev/null +++ b/sys/contrib/dev/ath/ah_desc.h @@ -0,0 +1,181 @@ +/*- + * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting, Atheros + * Communications, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the following conditions are met: + * 1. The materials contained herein are unmodified and are used + * unmodified. + * 2. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following NO + * ''WARRANTY'' disclaimer below (''Disclaimer''), without + * modification. + * 3. Redistributions in binary form must reproduce at minimum a + * disclaimer similar to the Disclaimer below and any redistribution + * must be conditioned upon including a substantially similar + * Disclaimer requirement for further binary redistribution. + * 4. Neither the names of the above-listed copyright holders nor the + * names of any contributors may be used to endorse or promote + * product derived from this software without specific prior written + * permission. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, + * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE + * FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGES. + * + * $Id: //depot/sw/linuxsrc/src/802_11/madwifi/hal/main/ah_desc.h#23 $ + */ + +#ifndef _DEV_ATH_DESC_H +#define _DEV_ATH_DESC_H + +/* + * Transmit descriptor status. This structure is filled + * in only after the tx descriptor process method finds a + * ``done'' descriptor; at which point it returns something + * other than HAL_EINPROGRESS. + * + * Note that ts_antenna may not be valid for all h/w. It + * should be used only if non-zero. + */ +struct ath_tx_status { + u_int16_t ts_seqnum; /* h/w assigned sequence number */ + u_int16_t ts_tstamp; /* h/w assigned timestamp */ + u_int8_t ts_status; /* frame status, 0 => xmit ok */ + u_int8_t ts_rate; /* h/w transmit rate index */ +#define HAL_TXSTAT_ALTRATE 0x80 /* alternate xmit rate used */ + int8_t ts_rssi; /* tx ack RSSI */ + u_int8_t ts_shortretry; /* # short retries */ + u_int8_t ts_longretry; /* # long retries */ + u_int8_t ts_virtcol; /* virtual collision count */ + u_int8_t ts_antenna; /* antenna information */ +}; + +#define HAL_TXERR_XRETRY 0x01 /* excessive retries */ +#define HAL_TXERR_FILT 0x02 /* blocked by tx filtering */ +#define HAL_TXERR_FIFO 0x04 /* fifo underrun */ + +/* + * Receive descriptor status. This structure is filled + * in only after the rx descriptor process method finds a + * ``done'' descriptor; at which point it returns something + * other than HAL_EINPROGRESS. + * + * If rx_status is zero, then the frame was received ok; + * otherwise the error information is indicated and rs_phyerr + * contains a phy error code if HAL_RXERR_PHY is set. In general + * the frame contents is undefined when an error occurred thought + * for some errors (e.g. a decryption error), it may be meaningful. + * + * Note that the receive timestamp is expanded using the TSF to + * 15 bits (regardless of what the h/w provides directly). + * + * rx_rssi is in units of dbm above the noise floor. This value + * is measured during the preamble and PLCP; i.e. with the initial + * 4us of detection. The noise floor is typically a consistent + * -96dBm absolute power in a 20MHz channel. + */ +struct ath_rx_status { + u_int16_t rs_datalen; /* rx frame length */ + u_int16_t rs_tstamp; /* h/w assigned timestamp */ + u_int8_t rs_status; /* rx status, 0 => recv ok */ + u_int8_t rs_phyerr; /* phy error code */ + int8_t rs_rssi; /* rx frame RSSI */ + u_int8_t rs_keyix; /* key cache index */ + u_int8_t rs_rate; /* h/w receive rate index */ + u_int8_t rs_antenna; /* antenna information */ + u_int8_t rs_more; /* more descriptors follow */ +}; + +#define HAL_RXERR_CRC 0x01 /* CRC error on frame */ +#define HAL_RXERR_PHY 0x02 /* PHY error, rs_phyerr is valid */ +#define HAL_RXERR_FIFO 0x04 /* fifo overrun */ +#define HAL_RXERR_DECRYPT 0x08 /* non-Michael decrypt error */ +#define HAL_RXERR_MIC 0x10 /* Michael MIC decrypt error */ + +enum { + HAL_PHYERR_UNDERRUN = 0, /* Transmit underrun */ + HAL_PHYERR_TIMING = 1, /* Timing error */ + HAL_PHYERR_PARITY = 2, /* Illegal parity */ + HAL_PHYERR_RATE = 3, /* Illegal rate */ + HAL_PHYERR_LENGTH = 4, /* Illegal length */ + HAL_PHYERR_RADAR = 5, /* Radar detect */ + HAL_PHYERR_SERVICE = 6, /* Illegal service */ + HAL_PHYERR_TOR = 7, /* Transmit override receive */ + /* NB: these are specific to the 5212 */ + HAL_PHYERR_OFDM_TIMING = 17, /* */ + HAL_PHYERR_OFDM_SIGNAL_PARITY = 18, /* */ + HAL_PHYERR_OFDM_RATE_ILLEGAL = 19, /* */ + HAL_PHYERR_OFDM_LENGTH_ILLEGAL = 20, /* */ + HAL_PHYERR_OFDM_POWER_DROP = 21, /* */ + HAL_PHYERR_OFDM_SERVICE = 22, /* */ + HAL_PHYERR_OFDM_RESTART = 23, /* */ + HAL_PHYERR_CCK_TIMING = 25, /* */ + HAL_PHYERR_CCK_HEADER_CRC = 26, /* */ + HAL_PHYERR_CCK_RATE_ILLEGAL = 27, /* */ + HAL_PHYERR_CCK_SERVICE = 30, /* */ + HAL_PHYERR_CCK_RESTART = 31, /* */ +}; + +/* value found in rs_keyix to mark invalid entries */ +#define HAL_RXKEYIX_INVALID ((u_int8_t) -1) +/* value used to specify no encryption key for xmit */ +#define HAL_TXKEYIX_INVALID ((u_int) -1) + +/* XXX rs_antenna definitions */ + +/* + * Definitions for the software frame/packet descriptors used by + * the Atheros HAL. This definition obscures hardware-specific + * details from the driver. Drivers are expected to fillin the + * portions of a descriptor that are not opaque then use HAL calls + * to complete the work. Status for completed frames is returned + * in a device-independent format. + */ +struct ath_desc { + /* + * The following definitions are passed directly + * the hardware and managed by the HAL. Drivers + * should not touch those elements marked opaque. + */ + u_int32_t ds_link; /* phys address of next descriptor */ + u_int32_t ds_data; /* phys address of data buffer */ + u_int32_t ds_ctl0; /* opaque DMA control 0 */ + u_int32_t ds_ctl1; /* opaque DMA control 1 */ + u_int32_t ds_hw[4]; /* opaque h/w region */ + /* + * The remaining definitions are managed by software; + * these are valid only after the rx/tx process descriptor + * methods return a non-EINPROGRESS code. + */ + union { + struct ath_tx_status tx;/* xmit status */ + struct ath_rx_status rx;/* recv status */ + } ds_us; + void *ds_vdata; /* virtual addr of data buffer */ +} __packed; + +#define ds_txstat ds_us.tx +#define ds_rxstat ds_us.rx + +/* flags passed to tx descriptor setup methods */ +#define HAL_TXDESC_CLRDMASK 0x0001 /* clear destination filter mask */ +#define HAL_TXDESC_NOACK 0x0002 /* don't wait for ACK */ +#define HAL_TXDESC_RTSENA 0x0004 /* enable RTS */ +#define HAL_TXDESC_CTSENA 0x0008 /* enable CTS */ +#define HAL_TXDESC_INTREQ 0x0010 /* enable per-descriptor interrupt */ +#define HAL_TXDESC_VEOL 0x0020 /* mark virtual EOL */ + +/* flags passed to rx descriptor setup methods */ +#define HAL_RXDESC_INTREQ 0x0020 /* enable per-descriptor interrupt */ +#endif /* _DEV_ATH_AR521XDMA_H */ diff --git a/sys/contrib/dev/ath/ah_devid.h b/sys/contrib/dev/ath/ah_devid.h new file mode 100644 index 0000000000..09c59534b6 --- /dev/null +++ b/sys/contrib/dev/ath/ah_devid.h @@ -0,0 +1,93 @@ +/*- + * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting, Atheros + * Communications, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the following conditions are met: + * 1. The materials contained herein are unmodified and are used + * unmodified. + * 2. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following NO + * ''WARRANTY'' disclaimer below (''Disclaimer''), without + * modification. + * 3. Redistributions in binary form must reproduce at minimum a + * disclaimer similar to the Disclaimer below and any redistribution + * must be conditioned upon including a substantially similar + * Disclaimer requirement for further binary redistribution. + * 4. Neither the names of the above-listed copyright holders nor the + * names of any contributors may be used to endorse or promote + * product derived from this software without specific prior written + * permission. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, + * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE + * FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGES. + * + * $Id: //depot/sw/linuxsrc/src/802_11/madwifi/hal/main/ah_devid.h#19 $ + */ + +#ifndef _DEV_ATH_DEVID_H_ +#define _DEV_ATH_DEVID_H_ + +#define ATHEROS_VENDOR_ID 0x168c /* Atheros PCI vendor ID */ +/* + * NB: all Atheros-based devices should have a PCI vendor ID + * of 0x168c, but some vendors, in their infinite wisdom + * do not follow this so we must handle them specially. + */ +#define ATHEROS_3COM_VENDOR_ID 0xa727 /* 3Com 3CRPAG175 vendor ID */ +#define ATHEROS_3COM2_VENDOR_ID 0x10b7 /* 3Com 3CRDAG675 vendor ID */ + +/* AR5210 (for reference) */ +#define AR5210_DEFAULT 0x1107 /* No eeprom HW default */ +#define AR5210_PROD 0x0007 /* Final device ID */ +#define AR5210_AP 0x0207 /* Early AP11s */ + +/* AR5211 */ +#define AR5211_DEFAULT 0x1112 /* No eeprom HW default */ +#define AR5311_DEVID 0x0011 /* Final ar5311 devid */ +#define AR5211_DEVID 0x0012 /* Final ar5211 devid */ +#define AR5211_LEGACY 0xff12 /* Original emulation board */ +#define AR5211_FPGA11B 0xf11b /* 11b emulation board */ + +/* AR5212 */ +#define AR5212_DEFAULT 0x1113 /* No eeprom HW default */ +#define AR5212_DEVID 0x0013 /* Final ar5212 devid */ +#define AR5212_FPGA 0xf013 /* Emulation board */ +#define AR5212_DEVID_IBM 0x1014 /* IBM minipci ID */ +#define AR5212_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */ +#define AR5212_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ +#define AR5212_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */ +#define AR5212_AR2315_REV6 0x0086 /* AR2315 WMAC (AP51-Light) */ +#define AR5212_AR2315_REV7 0x0087 /* AR2315 WMAC (AP51-Full) */ +#define AR5212_AR2317_REV1 0x0091 /* AR2317 WMAC (AP61) */ + +/* AR5212 compatible devid's also attach to 5212 */ +#define AR5212_DEVID_0014 0x0014 +#define AR5212_DEVID_0015 0x0015 +#define AR5212_DEVID_0016 0x0016 +#define AR5212_DEVID_0017 0x0017 +#define AR5212_DEVID_0018 0x0018 +#define AR5212_DEVID_0019 0x0019 +#define AR5212_AR2413 0x001a /* AR2413 aka Griffin-lite */ +#define AR5212_AR5413 0x001b /* Eagle */ +#define AR5212_AR5424 0x001c /* Condor (PCI express) */ +#define AR5212_DEVID_FF19 0xff19 /* XXX PCI express */ + +/* AR5213 */ +#define AR5213_SREV_1_0 0x0055 +#define AR5213_SREV_REG 0x4020 + +#define AR_SUBVENDOR_ID_NOG 0x0e11 /* No 11G subvendor ID */ +#define AR_SUBVENDOR_ID_NEW_A 0x7065 /* Update device to new RD */ +#endif /* _DEV_ATH_DEVID_H */ diff --git a/sys/contrib/dev/ath/dragonfly/ah_if.m b/sys/contrib/dev/ath/dragonfly/ah_if.m new file mode 100644 index 0000000000..0bcc6b8231 --- /dev/null +++ b/sys/contrib/dev/ath/dragonfly/ah_if.m @@ -0,0 +1,90 @@ +# +# Copyright (c) 2002-2006 Sam Leffler, Errno Consulting, Atheros +# Communications, Inc. All rights reserved. +# +# Redistribution and use in source and binary forms are permitted +# provided that the following conditions are met: +# 1. The materials contained herein are unmodified and are used +# unmodified. +# 2. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following NO +# ''WARRANTY'' disclaimer below (''Disclaimer''), without +# modification. +# 3. Redistributions in binary form must reproduce at minimum a +# disclaimer similar to the Disclaimer below and any redistribution +# must be conditioned upon including a substantially similar +# Disclaimer requirement for further binary redistribution. +# 4. Neither the names of the above-listed copyright holders nor the +# names of any contributors may be used to endorse or promote +# product derived from this software without specific prior written +# permission. +# +# NO WARRANTY +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, +# MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +# IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE +# FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT +# OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +# SUCH DAMAGES. +# +# $Id: //depot/sw/linuxsrc/src/802_11/madwifi/hal/main/freebsd/ah_if.m#6 $ +# + +INTERFACE ath_hal; + +METHOD const char* ath_hal_probe { + u_int16_t vendorID; + u_int16_ deviceID; +}; + +METHOD struct ath_hal* ath_hal_attach { + u_int16_t deviceID; + HAL_SOFTC sc; + HAL_BUS_TAG st; + HAL_BUS_HANDLE sh; + HAL_STATUS* error; +}; + +METHOD u_int ath_hal_init_channels { + struct ath_hal* ah; + HAL_CHANNEL* chans; + u_int maxchans; + u_int* nchans; + HAL_CTRY_CODE cc; + u_int16_t modeSelect; + int enableOutdoor; +}; + +METHOD u_int ath_hal_getwirelessmodes { + struct ath_hal* ah; + HAL_CTRY_CODE cc; +}; + +METHOD const HAL_RATE_TABLE* ath_hal_getratetable { + struct ath_hal* ah; + u_int mode; +}; + +METHOD u_int16_t ath_hal_computetxtime { + struct ath_hal* ah; + const HAL_RATE_TABLE* rates; + u_int32_t frameLength; + u_int16_t rateIndex; + HAL_BOOL shortPreamble; +}; + +METHOD u_int ath_hal_mhz2ieee { + u_int mhz; + u_int flags; +}; + +METHOD u_int ath_hal_ieee2mhz { + u_int ieee; + u_int flags; +}; diff --git a/sys/contrib/dev/ath/dragonfly/ah_osdep.c b/sys/contrib/dev/ath/dragonfly/ah_osdep.c new file mode 100644 index 0000000000..f421d13d25 --- /dev/null +++ b/sys/contrib/dev/ath/dragonfly/ah_osdep.c @@ -0,0 +1,417 @@ +/*- + * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting, Atheros + * Communications, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the following conditions are met: + * 1. The materials contained herein are unmodified and are used + * unmodified. + * 2. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following NO + * ''WARRANTY'' disclaimer below (''Disclaimer''), without + * modification. + * 3. Redistributions in binary form must reproduce at minimum a + * disclaimer similar to the Disclaimer below and any redistribution + * must be conditioned upon including a substantially similar + * Disclaimer requirement for further binary redistribution. + * 4. Neither the names of the above-listed copyright holders nor the + * names of any contributors may be used to endorse or promote + * product derived from this software without specific prior written + * permission. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, + * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE + * FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGES. + * + * $Id: //depot/sw/linuxsrc/src/802_11/madwifi/hal/main/freebsd/ah_osdep.c#39 $ + */ +#include "opt_ah.h" + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include /* XXX for ether_sprintf */ + +#include + +extern void ath_hal_printf(struct ath_hal *, const char*, ...) + __printflike(2,3); +extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list) + __printflike(2, 0); +extern const char* ath_hal_ether_sprintf(const u_int8_t *mac); +extern void *ath_hal_malloc(size_t); +extern void ath_hal_free(void *); +#ifdef AH_ASSERT +extern void ath_hal_assert_failed(const char* filename, + int lineno, const char* msg); +#endif +#ifdef AH_DEBUG +extern void HALDEBUG(struct ath_hal *ah, const char* fmt, ...); +extern void HALDEBUGn(struct ath_hal *ah, u_int level, const char* fmt, ...); +#endif /* AH_DEBUG */ + +/* NB: put this here instead of the driver to avoid circular references */ +SYSCTL_NODE(_hw, OID_AUTO, ath, CTLFLAG_RD, 0, "Atheros driver parameters"); +SYSCTL_NODE(_hw_ath, OID_AUTO, hal, CTLFLAG_RD, 0, "Atheros HAL parameters"); + +#ifdef AH_DEBUG +static int ath_hal_debug = 0; +SYSCTL_INT(_hw_ath_hal, OID_AUTO, debug, CTLFLAG_RW, &ath_hal_debug, + 0, "Atheros HAL debugging printfs"); +TUNABLE_INT("hw.ath.hal.debug", &ath_hal_debug); +#endif /* AH_DEBUG */ + +SYSCTL_STRING(_hw_ath_hal, OID_AUTO, version, CTLFLAG_RD, ath_hal_version, 0, + "Atheros HAL version"); + +int ath_hal_dma_beacon_response_time = 2; /* in TU's */ +SYSCTL_INT(_hw_ath_hal, OID_AUTO, dma_brt, CTLFLAG_RW, + &ath_hal_dma_beacon_response_time, 0, + "Atheros HAL DMA beacon response time"); +int ath_hal_sw_beacon_response_time = 10; /* in TU's */ +SYSCTL_INT(_hw_ath_hal, OID_AUTO, sw_brt, CTLFLAG_RW, + &ath_hal_sw_beacon_response_time, 0, + "Atheros HAL software beacon response time"); +int ath_hal_additional_swba_backoff = 0; /* in TU's */ +SYSCTL_INT(_hw_ath_hal, OID_AUTO, swba_backoff, CTLFLAG_RW, + &ath_hal_additional_swba_backoff, 0, + "Atheros HAL additional SWBA backoff time"); + +MALLOC_DEFINE(M_ATH_HAL, "ath_hal", "ath hal data"); + +void* +ath_hal_malloc(size_t size) +{ + return malloc(size, M_ATH_HAL, M_NOWAIT | M_ZERO); +} + +void +ath_hal_free(void* p) +{ + return free(p, M_ATH_HAL); +} + +void +ath_hal_vprintf(struct ath_hal *ah, const char* fmt, va_list ap) +{ + vprintf(fmt, ap); +} + +void +ath_hal_printf(struct ath_hal *ah, const char* fmt, ...) +{ + va_list ap; + va_start(ap, fmt); + ath_hal_vprintf(ah, fmt, ap); + va_end(ap); +} + +const char* +ath_hal_ether_sprintf(const u_int8_t *mac) +{ + return ether_sprintf(mac); +} + +#ifdef AH_DEBUG +void +HALDEBUG(struct ath_hal *ah, const char* fmt, ...) +{ + if (ath_hal_debug) { + __va_list ap; + va_start(ap, fmt); + ath_hal_vprintf(ah, fmt, ap); + va_end(ap); + } +} + +void +HALDEBUGn(struct ath_hal *ah, u_int level, const char* fmt, ...) +{ + if (ath_hal_debug >= level) { + __va_list ap; + va_start(ap, fmt); + ath_hal_vprintf(ah, fmt, ap); + va_end(ap); + } +} +#endif /* AH_DEBUG */ + +#ifdef AH_DEBUG_ALQ +/* + * ALQ register tracing support. + * + * Setting hw.ath.hal.alq=1 enables tracing of all register reads and + * writes to the file /tmp/ath_hal.log. The file format is a simple + * fixed-size array of records. When done logging set hw.ath.hal.alq=0 + * and then decode the file with the arcode program (that is part of the + * HAL). If you start+stop tracing the data will be appended to an + * existing file. + * + * NB: doesn't handle multiple devices properly; only one DEVICE record + * is emitted and the different devices are not identified. + */ +#include +#include +#include + +static struct alq *ath_hal_alq; +static int ath_hal_alq_emitdev; /* need to emit DEVICE record */ +static u_int ath_hal_alq_lost; /* count of lost records */ +static const char *ath_hal_logfile = "/tmp/ath_hal.log"; +static u_int ath_hal_alq_qsize = 64*1024; + +static int +ath_hal_setlogging(int enable) +{ + int error; + + if (enable) { + error = suser(curthread); + if (error == 0) { + error = alq_open(&ath_hal_alq, ath_hal_logfile, + curthread->td_ucred, ALQ_DEFAULT_CMODE, + sizeof (struct athregrec), ath_hal_alq_qsize); + ath_hal_alq_lost = 0; + ath_hal_alq_emitdev = 1; + printf("ath_hal: logging to %s enabled\n", + ath_hal_logfile); + } + } else { + if (ath_hal_alq) + alq_close(ath_hal_alq); + ath_hal_alq = NULL; + printf("ath_hal: logging disabled\n"); + error = 0; + } + return (error); +} + +static int +sysctl_hw_ath_hal_log(SYSCTL_HANDLER_ARGS) +{ + int error, enable; + + enable = (ath_hal_alq != NULL); + error = sysctl_handle_int(oidp, &enable, 0, req); + if (error || !req->newptr) + return (error); + else + return (ath_hal_setlogging(enable)); +} +SYSCTL_PROC(_hw_ath_hal, OID_AUTO, alq, CTLTYPE_INT|CTLFLAG_RW, + 0, 0, sysctl_hw_ath_hal_log, "I", "Enable HAL register logging"); +SYSCTL_INT(_hw_ath_hal, OID_AUTO, alq_size, CTLFLAG_RW, + &ath_hal_alq_qsize, 0, "In-memory log size (#records)"); +SYSCTL_INT(_hw_ath_hal, OID_AUTO, alq_lost, CTLFLAG_RW, + &ath_hal_alq_lost, 0, "Register operations not logged"); + +static struct ale * +ath_hal_alq_get(struct ath_hal *ah) +{ + struct ale *ale; + + if (ath_hal_alq_emitdev) { + ale = alq_get(ath_hal_alq, ALQ_NOWAIT); + if (ale) { + struct athregrec *r = + (struct athregrec *) ale->ae_data; + r->op = OP_DEVICE; + r->reg = 0; + r->val = ah->ah_devid; + alq_post(ath_hal_alq, ale); + ath_hal_alq_emitdev = 0; + } else + ath_hal_alq_lost++; + } + ale = alq_get(ath_hal_alq, ALQ_NOWAIT); + if (!ale) + ath_hal_alq_lost++; + return ale; +} + +void +ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val) +{ + if (ath_hal_alq) { + struct ale *ale = ath_hal_alq_get(ah); + if (ale) { + struct athregrec *r = (struct athregrec *) ale->ae_data; + r->op = OP_WRITE; + r->reg = reg; + r->val = val; + alq_post(ath_hal_alq, ale); + } + } +#if _BYTE_ORDER == _BIG_ENDIAN + if (reg >= 0x4000 && reg < 0x5000) + bus_space_write_4(ah->ah_st, ah->ah_sh, reg, htole32(val)); + else +#endif + bus_space_write_4(ah->ah_st, ah->ah_sh, reg, val); +} + +u_int32_t +ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg) +{ + u_int32_t val; + + val = bus_space_read_4(ah->ah_st, ah->ah_sh, reg); +#if _BYTE_ORDER == _BIG_ENDIAN + if (reg >= 0x4000 && reg < 0x5000) + val = le32toh(val); +#endif + if (ath_hal_alq) { + struct ale *ale = ath_hal_alq_get(ah); + if (ale) { + struct athregrec *r = (struct athregrec *) ale->ae_data; + r->op = OP_READ; + r->reg = reg; + r->val = val; + alq_post(ath_hal_alq, ale); + } + } + return val; +} + +void +OS_MARK(struct ath_hal *ah, u_int id, u_int32_t v) +{ + if (ath_hal_alq) { + struct ale *ale = ath_hal_alq_get(ah); + if (ale) { + struct athregrec *r = (struct athregrec *) ale->ae_data; + r->op = OP_MARK; + r->reg = id; + r->val = v; + alq_post(ath_hal_alq, ale); + } + } +} +#elif defined(AH_DEBUG) || defined(AH_REGOPS_FUNC) +/* + * Memory-mapped device register read/write. These are here + * as routines when debugging support is enabled and/or when + * explicitly configured to use function calls. The latter is + * for architectures that might need to do something before + * referencing memory (e.g. remap an i/o window). + * + * NB: see the comments in ah_osdep.h about byte-swapping register + * reads and writes to understand what's going on below. + */ + +void +ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val) +{ +#if _BYTE_ORDER == _BIG_ENDIAN + if (reg >= 0x4000 && reg < 0x5000) + bus_space_write_4(ah->ah_st, ah->ah_sh, reg, htole32(val)); + else +#endif + bus_space_write_4(ah->ah_st, ah->ah_sh, reg, val); +} + +u_int32_t +ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg) +{ + u_int32_t val; + + val = bus_space_read_4(ah->ah_st, ah->ah_sh, reg); +#if _BYTE_ORDER == _BIG_ENDIAN + if (reg >= 0x4000 && reg < 0x5000) + val = le32toh(val); +#endif + return val; +} +#endif /* AH_DEBUG || AH_REGOPS_FUNC */ + +#ifdef AH_ASSERT +void +ath_hal_assert_failed(const char* filename, int lineno, const char *msg) +{ + printf("Atheros HAL assertion failure: %s: line %u: %s\n", + filename, lineno, msg); + panic("ath_hal_assert"); +} +#endif /* AH_ASSERT */ + +/* + * Delay n microseconds. + */ +void +ath_hal_delay(int n) +{ + DELAY(n); +} + +u_int32_t +ath_hal_getuptime(struct ath_hal *ah) +{ + struct bintime bt; + getbinuptime(&bt); + return (bt.sec * 1000) + + (((uint64_t)1000 * (uint32_t)(bt.frac >> 32)) >> 32); +} + +void +ath_hal_memzero(void *dst, size_t n) +{ + bzero(dst, n); +} + +void * +ath_hal_memcpy(void *dst, const void *src, size_t n) +{ + return memcpy(dst, src, n); +} + +/* + * Module glue. + */ + +static int +ath_hal_modevent(module_t mod, int type, void *unused) +{ + const char *sep; + int i; + + switch (type) { + case MOD_LOAD: + printf("ath_hal: %s (", ath_hal_version); + sep = ""; + for (i = 0; ath_hal_buildopts[i] != NULL; i++) { + printf("%s%s", sep, ath_hal_buildopts[i]); + sep = ", "; + } + printf(")\n"); + return 0; + case MOD_UNLOAD: + return 0; + } + return EINVAL; +} + +static moduledata_t ath_hal_mod = { + "ath_hal", + ath_hal_modevent, + 0 +}; +DECLARE_MODULE(ath_hal, ath_hal_mod, SI_SUB_DRIVERS, SI_ORDER_ANY); +MODULE_VERSION(ath_hal, 1); diff --git a/sys/contrib/dev/ath/dragonfly/ah_osdep.h b/sys/contrib/dev/ath/dragonfly/ah_osdep.h new file mode 100644 index 0000000000..3759d8432a --- /dev/null +++ b/sys/contrib/dev/ath/dragonfly/ah_osdep.h @@ -0,0 +1,127 @@ +/*- + * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting, Atheros + * Communications, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the following conditions are met: + * 1. The materials contained herein are unmodified and are used + * unmodified. + * 2. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following NO + * ''WARRANTY'' disclaimer below (''Disclaimer''), without + * modification. + * 3. Redistributions in binary form must reproduce at minimum a + * disclaimer similar to the Disclaimer below and any redistribution + * must be conditioned upon including a substantially similar + * Disclaimer requirement for further binary redistribution. + * 4. Neither the names of the above-listed copyright holders nor the + * names of any contributors may be used to endorse or promote + * product derived from this software without specific prior written + * permission. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, + * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE + * FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGES. + * + * $Id: //depot/sw/linuxsrc/src/802_11/madwifi/hal/main/freebsd/ah_osdep.h#17 $ + */ +#ifndef _ATH_AH_OSDEP_H_ +#define _ATH_AH_OSDEP_H_ +/* + * Atheros Hardware Access Layer (HAL) OS Dependent Definitions. + */ +#include +#include +#include + +#include + +typedef void* HAL_SOFTC; +typedef bus_space_tag_t HAL_BUS_TAG; +typedef bus_space_handle_t HAL_BUS_HANDLE; +typedef bus_addr_t HAL_BUS_ADDR; + +/* + * Delay n microseconds. + */ +extern void ath_hal_delay(int); +#define OS_DELAY(_n) ath_hal_delay(_n) + +#define OS_INLINE __inline +#define OS_MEMZERO(_a, _n) ath_hal_memzero((_a), (_n)) +extern void ath_hal_memzero(void *, size_t); +#define OS_MEMCPY(_d, _s, _n) ath_hal_memcpy(_d,_s,_n) +extern void *ath_hal_memcpy(void *, const void *, size_t); + +#define abs(_a) __builtin_abs(_a) + +struct ath_hal; +extern u_int32_t ath_hal_getuptime(struct ath_hal *); +#define OS_GETUPTIME(_ah) ath_hal_getuptime(_ah) + +/* + * Register read/write; we assume the registers will always + * be memory-mapped. Note that register accesses are done + * using target-specific functions when debugging is enabled + * (AH_DEBUG) or we are explicitly configured this way. The + * latter is used on some platforms where the full i/o space + * cannot be directly mapped. + */ +#if defined(AH_DEBUG) || defined(AH_REGOPS_FUNC) || defined(AH_DEBUG_ALQ) +#define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val) +#define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg) + +extern void ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val); +extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg); +#else +/* + * The hardware registers are native little-endian byte order. + * Big-endian hosts are handled by enabling hardware byte-swap + * of register reads and writes at reset. But the PCI clock + * domain registers are not byte swapped! Thus, on big-endian + * platforms we have to byte-swap thoese registers specifically. + * Most of this code is collapsed at compile time because the + * register values are constants. + */ +#define AH_LITTLE_ENDIAN 1234 +#define AH_BIG_ENDIAN 4321 + +#if _BYTE_ORDER == _BIG_ENDIAN +#define OS_REG_WRITE(_ah, _reg, _val) do { \ + if ( (_reg) >= 0x4000 && (_reg) < 0x5000) \ + bus_space_write_4((_ah)->ah_st, (_ah)->ah_sh, \ + (_reg), htole32(_val)); \ + else \ + bus_space_write_4((_ah)->ah_st, (_ah)->ah_sh, \ + (_reg), (_val)); \ +} while (0) +#define OS_REG_READ(_ah, _reg) \ + (((_reg) >= 0x4000 && (_reg) < 0x5000) ? \ + le32toh(bus_space_read_4((_ah)->ah_st, (_ah)->ah_sh, \ + (_reg))) : \ + bus_space_read_4((_ah)->ah_st, (_ah)->ah_sh, (_reg))) +#else /* _BYTE_ORDER == _LITTLE_ENDIAN */ +#define OS_REG_WRITE(_ah, _reg, _val) \ + bus_space_write_4((_ah)->ah_st, (_ah)->ah_sh, (_reg), (_val)) +#define OS_REG_READ(_ah, _reg) \ + ((u_int32_t) bus_space_read_4((_ah)->ah_st, (_ah)->ah_sh, (_reg))) +#endif /* _BYTE_ORDER */ +#endif /* AH_DEBUG || AH_REGFUNC || AH_DEBUG_ALQ */ + +#ifdef AH_DEBUG_ALQ +extern void OS_MARK(struct ath_hal *, u_int id, u_int32_t value); +#else +#define OS_MARK(_ah, _id, _v) +#endif + +#endif /* _ATH_AH_OSDEP_H_ */ diff --git a/sys/contrib/dev/ath/public/amd64-elf.hal.o.uu b/sys/contrib/dev/ath/public/amd64-elf.hal.o.uu new file mode 100644 index 0000000000..813a7f4d7b --- /dev/null +++ b/sys/contrib/dev/ath/public/amd64-elf.hal.o.uu @@ -0,0 +1,5791 @@ +/*- + * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting, Atheros + * Communications, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the following conditions are met: + * 1. The materials contained herein are unmodified and are used + * unmodified. + * 2. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following NO + * ''WARRANTY'' disclaimer below (''Disclaimer''), without + * modification. + * 3. Redistributions in binary form must reproduce at minimum a + * disclaimer similar to the Disclaimer below and any redistribution + * must be conditioned upon including a substantially similar + * Disclaimer requirement for further binary redistribution. + * 4. Neither the names of the above-listed copyright holders nor the + * names of any contributors may be used to endorse or promote + * product derived from this software without specific prior written + * permission. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, + * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE + * FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGES. + * + * $Id: //depot/sw/linuxsrc/src/802_11/madwifi/hal/main/COPYRIGHT#4 $ + */ +#define ATH_HAL_VERSION "0.9.16.16" +begin 644 hal.o +M?T5,1@(!`0````````````$`/@`!`````````````````````````#CQ`@`` +M`````````$```````$``$``-``^WQTC'P@````"#^%@/A/\```"#^%A_5X/X +M&W\J@_@:#XW>````@_@2?Q>#^!$/C;4```"#^`M+2,?"`````#T3\``` +M=$)(Q\(`````/1OQ``!T-.LM2,?"`````.LI2,?"`````.L@2,?"`````.L7 +M2,?"`````.L.2,?"`````.L%N@````!(B=##2(/L"(GQ9H'_C!9T$V:!_R>G +M=`RX`````&:!_[<0=0@/M_GHPO[__TB#Q`C#2(/L"`^WQST'`@``#X2*```` +M/0<"``!_((/X$G\,@_@1?6^#^`=T=.M_@_@3=%F#Z!J#^`)W""`0``&:)0@@/ +MMX(*!```9HE""HN"#`0``(E"+`^W@A`$``!FB4(P#[>"$@0``&:)0C(/MX(4 +M!```9HE"-`^W@A8$``!FB4(V2(G02(/$",.)MQ@$``"X`0```,-!5D%50515 +M4TF)_D&)U4&)S+L`````B?5)BT8@BT0%`$0AZ+H!````1#G@=!F_"@```.@` +M````_\.!^^<#``!^U[H`````B=!;74%<05U!7L.Y`````+@`````.?!S$HT4 +M`(GX@^`!"=#1[__!.?%R[L-!B=(/M\%(C01`1`^W3(8FN`````!%A`$BH&0HU$TA6)T;H````` +M]_'!X`0%D````.GR````2(._@@B<+!Z@9"C432%8G1N@````#W\8T$A20` +M``#K=D*-!,T`````BH&0HU$TA6)T;H`````]_&- +M!(46````ZT5"C02-`````(G`2&G`TTUB$$C!Z"")PL'J!D*-1-(5B=&Z```` +M`/?QP>`"C9"]````@\!<08'YYP,```]&PNL%N``````/M\##]D8"('0'N@(` +M``#K1`^W1@(ET````+H#````/<````!T+P^W1@(ET````+H$````/=````!T +M&O9&`A!T![H!````ZPWV1@,(#Y7`#[;0C122B=##2(/L&$B)7"0(2(EL)!") +M]8G3A-)Y'K@.````@?ZT"0``#X0.`0``@?ZS"0``=E3IT````/;&`70QZ``` +M``"%P'0+C86S[/__@_@P=G+WPT`!```/A,8```"!_8@3```/AI<```#IM0`` +M`+@.````@?ZT"0``#X2Z````@?ZS"0``=R"-E9GV__](8\)(:BYS@@P>@"C02`*<6-@@@___^#_0)U/8V"#3___T@/ +MK\'K.H'])!,``'8(C85@\/__ZR&-A3#V__^ZS@@P>@$@\`/ +MZQ:-A7CL__^ZS@@P>@"2(M<)`A(BVPD$$B#Q!C#4XGS2(NW +MFZ#@```$B)[DR)]^@` +M````9HE##$&X`0```$2)Z;H.````2(GN3(GWZ`````!FB4,.0?_$1#ME`'R2 +M6UU!7$%=05[#3(V'(`0``(/^'`^'`P$``(GP_R3%``````^WAT`$``#K!4$/ +MMT`*B0&X`````,-!#[=`".OQ0?9``@'K%T&`>`$`N@````"X#0````])PL-! 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+# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer, +# without modification. +# 2. Redistributions in binary form must reproduce at minimum a disclaimer +# similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any +# redistribution must be conditioned upon including a substantially +# similar Disclaimer requirement for further binary redistribution. +# 3. Neither the names of the above-listed copyright holders nor the names +# of any contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# Alternatively, this software may be distributed under the terms of the +# GNU General Public License ("GPL") version 2 as published by the Free +# Software Foundation. +# +# NO WARRANTY +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY +# AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +# THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, +# OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER +# IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +# THE POSSIBILITY OF SUCH DAMAGES. +# +# $Id: //depot/sw/linuxsrc/src/802_11/madwifi/hal/main/public/x86_64-elf.inc#20 $ +# + +# +# Compilation configuration for building x86-64-elf. +# + +# +ifndef TOOLPREFIX +TOOLPREFIX= /pub/gnu/bin/x86_64-linux- +endif +# +CC= ${TOOLPREFIX}gcc +LD= ${TOOLPREFIX}ld +STRIP= ${TOOLPREFIX}strip +OBJCOPY=${TOOLPREFIX}objcopy +NM= ${TOOLPREFIX}nm + +COPTS+= -DAH_BYTE_ORDER=AH_LITTLE_ENDIAN +# +# NB: this should come from inttypes.h but can't until we cleanp +# the definition of va_list on linux +# +COPTS+= -DAH_WORDSIZE=64 +COPTS+= -mcmodel=kernel -mno-red-zone +ifndef CONFIG_FRAME_POINTER +COPTS+= -fomit-frame-pointer +endif diff --git a/sys/contrib/dev/ath/public/amd64-elf.opt_ah.h b/sys/contrib/dev/ath/public/amd64-elf.opt_ah.h new file mode 100644 index 0000000000..de94323995 --- /dev/null +++ b/sys/contrib/dev/ath/public/amd64-elf.opt_ah.h @@ -0,0 +1,7 @@ +#define AH_SUPPORT_AR5210 1 +#define AH_SUPPORT_AR5211 1 +#define AH_SUPPORT_AR5212 1 +#define AH_SUPPORT_5111 1 +#define AH_SUPPORT_5112 1 +#define AH_SUPPORT_2413 1 +#define AH_SUPPORT_5413 1 diff --git a/sys/contrib/dev/ath/public/i386-elf.hal.o.uu b/sys/contrib/dev/ath/public/i386-elf.hal.o.uu new file mode 100644 index 0000000000..6116840fbc --- /dev/null +++ b/sys/contrib/dev/ath/public/i386-elf.hal.o.uu @@ -0,0 +1,4420 @@ +/*- + * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting, Atheros + * Communications, Inc. All rights reserved. + * + * Redistribution and use in source and binary forms are permitted + * provided that the following conditions are met: + * 1. The materials contained herein are unmodified and are used + * unmodified. + * 2. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following NO + * ''WARRANTY'' disclaimer below (''Disclaimer''), without + * modification. + * 3. Redistributions in binary form must reproduce at minimum a + * disclaimer similar to the Disclaimer below and any redistribution + * must be conditioned upon including a substantially similar + * Disclaimer requirement for further binary redistribution. + * 4. Neither the names of the above-listed copyright holders nor the + * names of any contributors may be used to endorse or promote + * product derived from this software without specific prior written + * permission. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, + * MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE + * FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGES. + * + * $Id: //depot/sw/linuxsrc/src/802_11/madwifi/hal/main/COPYRIGHT#4 $ + */ +#define ATH_HAL_VERSION "0.9.16.16" +begin 644 hal.o +M?T5,1@$!`0D```````````$``P`!```````````````DH0(``````#0````` +M`"@`#0`*``^W1"0$NC$```"#^%@/A`4!``"#^%A_:(/X&W\S@_@:#XWB```` +M@_@2?Q>#^!$/C;\```"#^`M4 +M/100``!T5.M:B?8]$Q$``'1)/1,1``!_"3T2$0``=";K0;ID````/1/P``!T +M/;IX````/1OQ``!T,>LGC78`NHP```#K);J9````ZQZZI@```.L7NKD```#K +M$+K,````ZPF0N@````"-=@")T,.0BU0D!(M$)`AF@?J,%G039H'Z)Z=T#+D` +M````9H'ZMQ!U#@^WP%#HN?[__X/$!(G!B#^!$/C8X```"#^`?````ZU&0/1,1``!T3CT3$0``?R(] +M!Q$``'1O/0<1``!_"3T4$```="WK=ST2$0``=$#K;HGV/1OQ``!T-3T;\0`` +M?PD]$_```'00ZU4]&?\``'5.B?:Z$P```(/L#%%35E +M`@``9HE")HG06UY?PXUV`(M4)`B+1"0$B9!@`@``N`$```##55=64X/L#(ML +M)"2+?"0HBW0D++L`````BU0D((M"%(L$*"'X.?!U"+@!````ZQR0@^P,:@KH +M_/___X/$$$.!^^<#``!^TK@`````@\0,6UY?7<.05E.+3"0,BW0D$+L````` +MN``````Y\',1C10`BXN&M!```&:#>`(`>2N)VL'B!+C336(0 +M]^+!Z@:-3/H5BH&C4SZ%8G(B=.Z`````/?SC02% +M)````.MLC13=`````+C336(0]^+!Z@:-3/H5B@"Z?\```"-DWCL__^XS@$@\`/ZQ60C9-X[/__N,W,S,SWXHG0 +MP>@"B?:#Q`Q;7E]=PU.+5"0(BUPD#(N"M!```(7`=!E04NC\____@\0(#[:` +M``````^OP^L'C78`:\,6D%O#B?93BU0D"(N"M!```(7`="504NC\____@\0( +M#[:0`````(M$)`R)T[H`````]_.)P>L3C78`N*.++KKW9"0,B='!Z02)]HG( +M6\-55U93@^P$BWPD'(!_!`!U<;L`````B?;&1!\$_T.#^Q]^];L`````@S\` +M?E6-=@"-!%N-=(<@BD8(BDX+#[;0B%P7!`I&"0^VP(A,```"+@80"``")!K@`````Z=$```"X#0```.G'```` +MC78`BD`"T.B#X`&#^`$9P(/@#>FO````BD`"P.@"@^`!@_@!&<"#X`WIF0`` +M`+@-````Z8\````/MD`!@^`!@_@!&<"#X`WK?HI``L#H!(/@`8/X`1G`@^`- +MZVN*0`+`Z`6#X`&#^`$9P(/@#>M8@_L!=!^#^P%R!X/[`G0CZS&*0`+`Z`:# +MX`&#^`$9P(/@#>LT@[G,$````1G`@^`-ZR8/MX'($```B0:X`````.L6N`T` +M``#K#XUV`+@-````ZP6X#````%M>PY!64XMT)`R+1"00BU0D%(M,)!B+7"0< +M@_@/=`F#^!ET'.M*B?:#^@-U0X/Y!'<^B8Z$`@``N`$```#K0)"#^@%T!X/Z +M`G07ZR2%R0^5P`^VP(F&S!```+@!````ZQYFB8[($```N`$```#K$)"%VW0& +MQP,,````N`````!;7L.)]E575E.+;"04BUPD((M,)!R_`````(/[!W8^B?:+ +M1"08#[<4N`^W=+@"B=#!X!`)\(D!@\$$@^L$BT44BP00B0&#P02#P@2#ZP0Y +M\G<%@_L#=^9'@_L'=\2)R"M$)!Q;7E]=PY!3BT0D"(M4)`R+3"08BUPD'(/Z +M#70J@_H-?PF%TG0-ZT^-=@"#^AMT,^M%D`50`@``B0''`Q````"X`0```.LU +M_S/_,?]T)!A0Z$[___^)`[@!````@\00ZQN)]@70$```B0''`Q@```"X`0`` +M`.L%N`````!;PY!3BUPD#(M,)!"X`````(-[!``/A"T!``"+`8D#BT$$B4,( +MBT$(B4,,BT$,B4,0@WD0_W04BT$0/?\```!V!;C_````B4,4ZPC'0Q0"```` +MD(-Y%/]T,(M1%('Z``0``'8%N@`$``#'0Q@!````.5,8)0QCK!HM!%(E#&(-Y&/]T,(M1&('Z``0``'8%N@`$``#'0QP!```` +M.5,<)0QSK"L=#'/\#``"-=@!F@WD<`'059HM! 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Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer, +# without modification. +# 2. Redistributions in binary form must reproduce at minimum a disclaimer +# similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any +# redistribution must be conditioned upon including a substantially +# similar Disclaimer requirement for further binary redistribution. +# 3. Neither the names of the above-listed copyright holders nor the names +# of any contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# Alternatively, this software may be distributed under the terms of the +# GNU General Public License ("GPL") version 2 as published by the Free +# Software Foundation. +# +# NO WARRANTY +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY +# AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +# THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, +# OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER +# IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF +# THE POSSIBILITY OF SUCH DAMAGES. +# +# $Id: //depot/sw/linuxsrc/src/802_11/madwifi/hal/main/public/i386-elf.inc#21 $ +# + +# +# Compilation configuration for building i386-elf. +# This assumes the build platform is also i386-elf. +# + +# +ifndef TOOLPREFIX +TOOLPREFIX= +endif +# +CC= ${TOOLPREFIX}gcc +LD= ${TOOLPREFIX}ld +STRIP= ${TOOLPREFIX}strip +OBJCOPY=${TOOLPREFIX}objcopy +NM= ${TOOLPREFIX}nm + +COPTS+= -DAH_BYTE_ORDER=AH_LITTLE_ENDIAN +ifndef CONFIG_FRAME_POINTER +COPTS+= -fomit-frame-pointer +endif diff --git a/sys/contrib/dev/ath/public/i386-elf.opt_ah.h b/sys/contrib/dev/ath/public/i386-elf.opt_ah.h new file mode 100644 index 0000000000..de94323995 --- /dev/null +++ b/sys/contrib/dev/ath/public/i386-elf.opt_ah.h @@ -0,0 +1,7 @@ +#define AH_SUPPORT_AR5210 1 +#define AH_SUPPORT_AR5211 1 +#define AH_SUPPORT_AR5212 1 +#define AH_SUPPORT_5111 1 +#define AH_SUPPORT_5112 1 +#define AH_SUPPORT_2413 1 +#define AH_SUPPORT_5413 1 diff --git a/sys/contrib/dev/ath/version.h b/sys/contrib/dev/ath/version.h new file mode 100644 index 0000000000..fe72823d8a --- /dev/null +++ b/sys/contrib/dev/ath/version.h @@ -0,0 +1,38 @@ +/*- + * Copyright (c) 2002-2006 Sam Leffler, Errno Consulting + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * 3. Neither the names of the above-listed copyright holders nor the names + * of any contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + * $Id: //depot/sw/linuxsrc/src/802_11/madwifi/hal/main/version.h#135 $ + */ +#define ATH_HAL_VERSION "0.9.16.16" -- 2.41.0