From aedf66eebba59f24875ae68f180138d1030dad88 Mon Sep 17 00:00:00 2001 From: Hasso Tepper Date: Mon, 22 Jun 2009 21:50:04 +0300 Subject: [PATCH] Radeon microcode handling cleanup. A little more cleanup from AMD, if we don't have the right microcode there is no reason to mess with the chip. Obtained-from: FreeBSD --- sys/dev/drm/r600_cp.c | 68 ++++++++++++++++++++--------------------- sys/dev/drm/radeon_cp.c | 7 +++-- 2 files changed, 37 insertions(+), 38 deletions(-) diff --git a/sys/dev/drm/r600_cp.c b/sys/dev/drm/r600_cp.c index 7c29b3d7fc..f53a5fa6ed 100644 --- a/sys/dev/drm/r600_cp.c +++ b/sys/dev/drm/r600_cp.c @@ -283,20 +283,6 @@ static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv) const u32 *pfp; int i; - r600_do_cp_stop(dev_priv); - - RADEON_WRITE(R600_CP_RB_CNTL, - R600_RB_NO_UPDATE | - R600_RB_BLKSZ(15) | - R600_RB_BUFSZ(3)); - - RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); - RADEON_READ(R600_GRBM_SOFT_RESET); - DRM_UDELAY(15000); - RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); - - RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); - switch (dev_priv->flags & RADEON_FAMILY_MASK) { case CHIP_R600: DRM_INFO("Loading R600 Microcode\n"); @@ -334,19 +320,32 @@ static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv) pfp = RS780_pfp_microcode; break; default: - goto no_microcode; + return; } - for (i = 0; i != PM4_UCODE_SIZE; i++) { + r600_do_cp_stop(dev_priv); + + RADEON_WRITE(R600_CP_RB_CNTL, + R600_RB_NO_UPDATE | + R600_RB_BLKSZ(15) | + R600_RB_BUFSZ(3)); + + RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); + RADEON_READ(R600_GRBM_SOFT_RESET); + DRM_UDELAY(15000); + RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); + + RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); + + for (i = 0; i < PM4_UCODE_SIZE; i++) { RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][0]); RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][1]); RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][2]); } RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); - for (i = 0; i != PFP_UCODE_SIZE; i++) + for (i = 0; i < PFP_UCODE_SIZE; i++) RADEON_WRITE(R600_CP_PFP_UCODE_DATA, pfp[i]); -no_microcode:; RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); @@ -412,21 +411,9 @@ static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv) const u32 *cp; int i; - r600_do_cp_stop(dev_priv); - - RADEON_WRITE(R600_CP_RB_CNTL, - R600_RB_NO_UPDATE | - (15 << 8) | - (3 << 0)); - - RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); - RADEON_READ(R600_GRBM_SOFT_RESET); - DRM_UDELAY(15000); - RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); - switch (dev_priv->flags & RADEON_FAMILY_MASK) { case CHIP_RV770: - DRM_INFO("Loading RV770 Microcode\n"); + DRM_INFO("Loading RV770/RV790 Microcode\n"); pfp = RV770_pfp_microcode; cp = RV770_cp_microcode; break; @@ -441,19 +428,30 @@ static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv) cp = RV710_cp_microcode; break; default: - goto no_microcode; + return; } + r600_do_cp_stop(dev_priv); + + RADEON_WRITE(R600_CP_RB_CNTL, + R600_RB_NO_UPDATE | + (15 << 8) | + (3 << 0)); + + RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); + RADEON_READ(R600_GRBM_SOFT_RESET); + DRM_UDELAY(15000); + RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); + RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); - for (i = 0; i != R700_PFP_UCODE_SIZE; i++) + for (i = 0; i < R700_PFP_UCODE_SIZE; i++) RADEON_WRITE(R600_CP_PFP_UCODE_DATA, pfp[i]); RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); - for (i = 0; i != R700_PM4_UCODE_SIZE; i++) + for (i = 0; i < R700_PM4_UCODE_SIZE; i++) RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i]); RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); -no_microcode:; RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); diff --git a/sys/dev/drm/radeon_cp.c b/sys/dev/drm/radeon_cp.c index 8d08417187..924e97851c 100644 --- a/sys/dev/drm/radeon_cp.c +++ b/sys/dev/drm/radeon_cp.c @@ -457,9 +457,6 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) DRM_DEBUG("\n"); - radeon_do_wait_for_idle(dev_priv); - - RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); switch (dev_priv->flags & RADEON_FAMILY_MASK) { case CHIP_R100: case CHIP_RV100: @@ -513,6 +510,10 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) return; } + radeon_do_wait_for_idle(dev_priv); + + RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0); + for (i = 0; i != 256; i++) { RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, cp[i][1]); RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, cp[i][0]); -- 2.41.0