sys/dev/netif/igb/if_igb.c

   1 /*
   2  * Copyright (c) 2001-2011, Intel Corporation
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  *  1. Redistributions of source code must retain the above copyright notice,
   9  *     this list of conditions and the following disclaimer.
  10  *
  11  *  2. Redistributions in binary form must reproduce the above copyright
  12  *     notice, this list of conditions and the following disclaimer in the
  13  *     documentation and/or other materials provided with the distribution.
  14  *
  15  *  3. Neither the name of the Intel Corporation nor the names of its
  16  *     contributors may be used to endorse or promote products derived from
  17  *     this software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #include "opt_polling.h"
  33
  34 #include <sys/param.h>
  35 #include <sys/bus.h>
  36 #include <sys/endian.h>
  37 #include <sys/interrupt.h>
  38 #include <sys/kernel.h>
  39 #include <sys/malloc.h>
  40 #include <sys/mbuf.h>
  41 #include <sys/proc.h>
  42 #include <sys/rman.h>
  43 #include <sys/serialize.h>
  44 #include <sys/serialize2.h>
  45 #include <sys/socket.h>
  46 #include <sys/sockio.h>
  47 #include <sys/sysctl.h>
  48 #include <sys/systm.h>
  49
  50 #include <net/bpf.h>
  51 #include <net/ethernet.h>
  52 #include <net/if.h>
  53 #include <net/if_arp.h>
  54 #include <net/if_dl.h>
  55 #include <net/if_media.h>
  56 #include <net/ifq_var.h>
  57 #include <net/toeplitz.h>
  58 #include <net/toeplitz2.h>
  59 #include <net/vlan/if_vlan_var.h>
  60 #include <net/vlan/if_vlan_ether.h>
  61 #include <net/if_poll.h>
  62
  63 #include <netinet/in_systm.h>
  64 #include <netinet/in.h>
  65 #include <netinet/ip.h>
  66 #include <netinet/tcp.h>
  67 #include <netinet/udp.h>
  68
  69 #include <bus/pci/pcivar.h>
  70 #include <bus/pci/pcireg.h>
  71
  72 #include <dev/netif/ig_hal/e1000_api.h>
  73 #include <dev/netif/ig_hal/e1000_82575.h>
  74 #include <dev/netif/igb/if_igb.h>
  75
  76 #define IGB_NAME        "Intel(R) PRO/1000 "
  77 #define IGB_DEVICE(id)  \
  78         { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
  79 #define IGB_DEVICE_NULL { 0, 0, NULL }
  80
  81 static struct igb_device {
  82         uint16_t        vid;
  83         uint16_t        did;
  84         const char      *desc;
  85 } igb_devices[] = {
  86         IGB_DEVICE(82575EB_COPPER),
  87         IGB_DEVICE(82575EB_FIBER_SERDES),
  88         IGB_DEVICE(82575GB_QUAD_COPPER),
  89         IGB_DEVICE(82576),
  90         IGB_DEVICE(82576_NS),
  91         IGB_DEVICE(82576_NS_SERDES),
  92         IGB_DEVICE(82576_FIBER),
  93         IGB_DEVICE(82576_SERDES),
  94         IGB_DEVICE(82576_SERDES_QUAD),
  95         IGB_DEVICE(82576_QUAD_COPPER),
  96         IGB_DEVICE(82576_QUAD_COPPER_ET2),
  97         IGB_DEVICE(82576_VF),
  98         IGB_DEVICE(82580_COPPER),
  99         IGB_DEVICE(82580_FIBER),
 100         IGB_DEVICE(82580_SERDES),
 101         IGB_DEVICE(82580_SGMII),
 102         IGB_DEVICE(82580_COPPER_DUAL),
 103         IGB_DEVICE(82580_QUAD_FIBER),
 104         IGB_DEVICE(DH89XXCC_SERDES),
 105         IGB_DEVICE(DH89XXCC_SGMII),
 106         IGB_DEVICE(DH89XXCC_SFP),
 107         IGB_DEVICE(DH89XXCC_BACKPLANE),
 108         IGB_DEVICE(I350_COPPER),
 109         IGB_DEVICE(I350_FIBER),
 110         IGB_DEVICE(I350_SERDES),
 111         IGB_DEVICE(I350_SGMII),
 112         IGB_DEVICE(I350_VF),
 113
 114         /* required last entry */
 115         IGB_DEVICE_NULL
 116 };
 117
 118 static int      igb_probe(device_t);
 119 static int      igb_attach(device_t);
 120 static int      igb_detach(device_t);
 121 static int      igb_shutdown(device_t);
 122 static int      igb_suspend(device_t);
 123 static int      igb_resume(device_t);
 124
 125 static boolean_t igb_is_valid_ether_addr(const uint8_t *);
 126 static void     igb_setup_ifp(struct igb_softc *);
 127 static int      igb_txctx_pullup(struct igb_tx_ring *, struct mbuf **);
 128 static boolean_t igb_txctx(struct igb_tx_ring *, struct mbuf *);
 129 static void     igb_add_sysctl(struct igb_softc *);
 130 static int      igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
 131 static int      igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
 132
 133 static void     igb_vf_init_stats(struct igb_softc *);
 134 static void     igb_reset(struct igb_softc *);
 135 static void     igb_update_stats_counters(struct igb_softc *);
 136 static void     igb_update_vf_stats_counters(struct igb_softc *);
 137 static void     igb_update_link_status(struct igb_softc *);
 138 static void     igb_init_tx_unit(struct igb_softc *);
 139 static void     igb_init_rx_unit(struct igb_softc *);
 140
 141 static void     igb_set_vlan(struct igb_softc *);
 142 static void     igb_set_multi(struct igb_softc *);
 143 static void     igb_set_promisc(struct igb_softc *);
 144 static void     igb_disable_promisc(struct igb_softc *);
 145
 146 static int      igb_dma_alloc(struct igb_softc *);
 147 static void     igb_dma_free(struct igb_softc *);
 148 static int      igb_create_tx_ring(struct igb_tx_ring *);
 149 static int      igb_create_rx_ring(struct igb_rx_ring *);
 150 static void     igb_free_tx_ring(struct igb_tx_ring *);
 151 static void     igb_free_rx_ring(struct igb_rx_ring *);
 152 static void     igb_destroy_tx_ring(struct igb_tx_ring *, int);
 153 static void     igb_destroy_rx_ring(struct igb_rx_ring *, int);
 154 static void     igb_init_tx_ring(struct igb_tx_ring *);
 155 static int      igb_init_rx_ring(struct igb_rx_ring *);
 156 static int      igb_newbuf(struct igb_rx_ring *, int, boolean_t);
 157 static int      igb_encap(struct igb_tx_ring *, struct mbuf **);
 158
 159 static void     igb_stop(struct igb_softc *);
 160 static void     igb_init(void *);
 161 static int      igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 162 static void     igb_media_status(struct ifnet *, struct ifmediareq *);
 163 static int      igb_media_change(struct ifnet *);
 164 static void     igb_timer(void *);
 165 static void     igb_watchdog(struct ifnet *);
 166 static void     igb_start(struct ifnet *);
 167 #ifdef DEVICE_POLLING
 168 static void     igb_poll(struct ifnet *, enum poll_cmd, int);
 169 #endif
 170
 171 static void     igb_intr(void *);
 172 static void     igb_shared_intr(void *);
 173 static void     igb_rxeof(struct igb_rx_ring *, int);
 174 static void     igb_txeof(struct igb_tx_ring *);
 175 static void     igb_set_eitr(struct igb_softc *);
 176 static void     igb_enable_intr(struct igb_softc *);
 177 static void     igb_disable_intr(struct igb_softc *);
 178 static void     igb_init_unshared_intr(struct igb_softc *);
 179 static void     igb_init_intr(struct igb_softc *);
 180 static int      igb_setup_intr(struct igb_softc *);
 181 static void     igb_setup_tx_intr(struct igb_tx_ring *);
 182 static void     igb_setup_rx_intr(struct igb_rx_ring *);
 183
 184 /* Management and WOL Support */
 185 static void     igb_get_mgmt(struct igb_softc *);
 186 static void     igb_rel_mgmt(struct igb_softc *);
 187 static void     igb_get_hw_control(struct igb_softc *);
 188 static void     igb_rel_hw_control(struct igb_softc *);
 189 static void     igb_enable_wol(device_t);
 190
 191 static device_method_t igb_methods[] = {
 192         /* Device interface */
 193         DEVMETHOD(device_probe,         igb_probe),
 194         DEVMETHOD(device_attach,        igb_attach),
 195         DEVMETHOD(device_detach,        igb_detach),
 196         DEVMETHOD(device_shutdown,      igb_shutdown),
 197         DEVMETHOD(device_suspend,       igb_suspend),
 198         DEVMETHOD(device_resume,        igb_resume),
 199         { 0, 0 }
 200 };
 201
 202 static driver_t igb_driver = {
 203         "igb",
 204         igb_methods,
 205         sizeof(struct igb_softc),
 206 };
 207
 208 static devclass_t igb_devclass;
 209
 210 DECLARE_DUMMY_MODULE(if_igb);
 211 MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
 212 DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
 213
 214 static int      igb_rxd = IGB_DEFAULT_RXD;
 215 static int      igb_txd = IGB_DEFAULT_TXD;
 216 static int      igb_msi_enable = 1;
 217 static int      igb_msix_enable = 1;
 218 static int      igb_eee_disabled = 1;   /* Energy Efficient Ethernet */
 219 static int      igb_fc_setting = e1000_fc_full;
 220
 221 /*
 222  * DMA Coalescing, only for i350 - default to off,
 223  * this feature is for power savings
 224  */
 225 static int      igb_dma_coalesce = 0;
 226
 227 TUNABLE_INT("hw.igb.rxd", &igb_rxd);
 228 TUNABLE_INT("hw.igb.txd", &igb_txd);
 229 TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
 230 TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
 231 TUNABLE_INT("hw.igb.fc_setting", &igb_fc_setting);
 232
 233 /* i350 specific */
 234 TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
 235 TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
 236
 237 static __inline void
 238 igb_rxcsum(uint32_t staterr, struct mbuf *mp)
 239 {
 240         /* Ignore Checksum bit is set */
 241         if (staterr & E1000_RXD_STAT_IXSM)
 242                 return;
 243
 244         if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
 245             E1000_RXD_STAT_IPCS)
 246                 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
 247
 248         if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
 249                 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
 250                         mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
 251                             CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
 252                         mp->m_pkthdr.csum_data = htons(0xffff);
 253                 }
 254         }
 255 }
 256
 257 static int
 258 igb_probe(device_t dev)
 259 {
 260         const struct igb_device *d;
 261         uint16_t vid, did;
 262
 263         vid = pci_get_vendor(dev);
 264         did = pci_get_device(dev);
 265
 266         for (d = igb_devices; d->desc != NULL; ++d) {
 267                 if (vid == d->vid && did == d->did) {
 268                         device_set_desc(dev, d->desc);
 269                         return 0;
 270                 }
 271         }
 272         return ENXIO;
 273 }
 274
 275 static int
 276 igb_attach(device_t dev)
 277 {
 278         struct igb_softc *sc = device_get_softc(dev);
 279         uint16_t eeprom_data;
 280         u_int intr_flags;
 281         int error = 0;
 282
 283 #ifdef notyet
 284         /* SYSCTL stuff */
 285         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 286             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 287             OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 288             igb_sysctl_nvm_info, "I", "NVM Information");
 289
 290         SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
 291             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 292             OID_AUTO, "enable_aim", CTLTYPE_INT|CTLFLAG_RW,
 293             &igb_enable_aim, 1, "Interrupt Moderation");
 294
 295         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 296             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 297             OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
 298             adapter, 0, igb_set_flowcntl, "I", "Flow Control");
 299 #endif
 300
 301         callout_init_mp(&sc->timer);
 302
 303         sc->dev = sc->osdep.dev = dev;
 304
 305         /*
 306          * Determine hardware and mac type
 307          */
 308         sc->hw.vendor_id = pci_get_vendor(dev);
 309         sc->hw.device_id = pci_get_device(dev);
 310         sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
 311         sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
 312         sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
 313
 314         if (e1000_set_mac_type(&sc->hw))
 315                 return ENXIO;
 316
 317         /* Are we a VF device? */
 318         if (sc->hw.mac.type == e1000_vfadapt ||
 319             sc->hw.mac.type == e1000_vfadapt_i350)
 320                 sc->vf_ifp = 1;
 321         else
 322                 sc->vf_ifp = 0;
 323
 324         /* Enable bus mastering */
 325         pci_enable_busmaster(dev);
 326
 327         /*
 328          * Allocate IO memory
 329          */
 330         sc->mem_rid = PCIR_BAR(0);
 331         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
 332             RF_ACTIVE);
 333         if (sc->mem_res == NULL) {
 334                 device_printf(dev, "Unable to allocate bus resource: memory\n");
 335                 error = ENXIO;
 336                 goto failed;
 337         }
 338         sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
 339         sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
 340
 341         sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
 342
 343         /*
 344          * Allocate interrupt
 345          */
 346         sc->intr_type = pci_alloc_1intr(dev, igb_msi_enable,
 347             &sc->intr_rid, &intr_flags);
 348
 349         sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
 350             intr_flags);
 351         if (sc->intr_res == NULL) {
 352                 device_printf(dev, "Unable to allocate bus resource: "
 353                     "interrupt\n");
 354                 error = ENXIO;
 355                 goto failed;
 356         }
 357
 358         /* Save PCI command register for Shared Code */
 359         sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
 360         sc->hw.back = &sc->osdep;
 361
 362         sc->tx_ring_cnt = 1; /* XXX */
 363         sc->rx_ring_cnt = 1; /* XXX */
 364         sc->intr_rate = IGB_INTR_RATE;
 365
 366         /* Do Shared Code initialization */
 367         if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
 368                 device_printf(dev, "Setup of Shared code failed\n");
 369                 error = ENXIO;
 370                 goto failed;
 371         }
 372
 373         e1000_get_bus_info(&sc->hw);
 374
 375         sc->hw.mac.autoneg = DO_AUTO_NEG;
 376         sc->hw.phy.autoneg_wait_to_complete = FALSE;
 377         sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
 378
 379         /* Copper options */
 380         if (sc->hw.phy.media_type == e1000_media_type_copper) {
 381                 sc->hw.phy.mdix = AUTO_ALL_MODES;
 382                 sc->hw.phy.disable_polarity_correction = FALSE;
 383                 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
 384         }
 385
 386         /* Set the frame limits assuming  standard ethernet sized frames. */
 387         sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
 388
 389         /* Allocate RX/TX rings' busdma(9) stuffs */
 390         error = igb_dma_alloc(sc);
 391         if (error)
 392                 goto failed;
 393
 394         /* Allocate the appropriate stats memory */
 395         if (sc->vf_ifp) {
 396                 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
 397                     M_WAITOK | M_ZERO);
 398                 igb_vf_init_stats(sc);
 399         } else {
 400                 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
 401                     M_WAITOK | M_ZERO);
 402         }
 403
 404         /* Allocate multicast array memory. */
 405         sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
 406             M_DEVBUF, M_WAITOK);
 407
 408         /* Some adapter-specific advanced features */
 409         if (sc->hw.mac.type >= e1000_i350) {
 410 #ifdef notyet
 411                 igb_set_sysctl_value(adapter, "dma_coalesce",
 412                     "configure dma coalesce",
 413                     &adapter->dma_coalesce, igb_dma_coalesce);
 414                 igb_set_sysctl_value(adapter, "eee_disabled",
 415                     "enable Energy Efficient Ethernet",
 416                     &adapter->hw.dev_spec._82575.eee_disable,
 417                     igb_eee_disabled);
 418 #else
 419                 sc->dma_coalesce = igb_dma_coalesce;
 420                 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
 421 #endif
 422                 e1000_set_eee_i350(&sc->hw);
 423         }
 424
 425         /*
 426          * Start from a known state, this is important in reading the nvm and
 427          * mac from that.
 428          */
 429         e1000_reset_hw(&sc->hw);
 430
 431         /* Make sure we have a good EEPROM before we read from it */
 432         if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
 433                 /*
 434                  * Some PCI-E parts fail the first check due to
 435                  * the link being in sleep state, call it again,
 436                  * if it fails a second time its a real issue.
 437                  */
 438                 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
 439                         device_printf(dev,
 440                             "The EEPROM Checksum Is Not Valid\n");
 441                         error = EIO;
 442                         goto failed;
 443                 }
 444         }
 445
 446         /* Copy the permanent MAC address out of the EEPROM */
 447         if (e1000_read_mac_addr(&sc->hw) < 0) {
 448                 device_printf(dev, "EEPROM read error while reading MAC"
 449                     " address\n");
 450                 error = EIO;
 451                 goto failed;
 452         }
 453         if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
 454                 device_printf(dev, "Invalid MAC address\n");
 455                 error = EIO;
 456                 goto failed;
 457         }
 458
 459 #ifdef notyet
 460         /*
 461         ** Configure Interrupts
 462         */
 463         if ((adapter->msix > 1) && (igb_enable_msix))
 464                 error = igb_allocate_msix(adapter);
 465         else /* MSI or Legacy */
 466                 error = igb_allocate_legacy(adapter);
 467         if (error)
 468                 goto err_late;
 469 #endif
 470
 471         /* Setup OS specific network interface */
 472         igb_setup_ifp(sc);
 473
 474         /* Add sysctl tree, must after igb_setup_ifp() */
 475         igb_add_sysctl(sc);
 476
 477         /* Now get a good starting state */
 478         igb_reset(sc);
 479
 480         /* Initialize statistics */
 481         igb_update_stats_counters(sc);
 482
 483         sc->hw.mac.get_link_status = 1;
 484         igb_update_link_status(sc);
 485
 486         /* Indicate SOL/IDER usage */
 487         if (e1000_check_reset_block(&sc->hw)) {
 488                 device_printf(dev,
 489                     "PHY reset is blocked due to SOL/IDER session.\n");
 490         }
 491
 492         /* Determine if we have to control management hardware */
 493         if (e1000_enable_mng_pass_thru(&sc->hw))
 494                 sc->flags |= IGB_FLAG_HAS_MGMT;
 495
 496         /*
 497          * Setup Wake-on-Lan
 498          */
 499         /* APME bit in EEPROM is mapped to WUC.APME */
 500         eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
 501         if (eeprom_data)
 502                 sc->wol = E1000_WUFC_MAG;
 503         /* XXX disable WOL */
 504         sc->wol = 0;
 505
 506 #ifdef notyet
 507         /* Register for VLAN events */
 508         adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
 509              igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
 510         adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
 511              igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
 512 #endif
 513
 514 #ifdef notyet
 515         igb_add_hw_stats(adapter);
 516 #endif
 517
 518         error = igb_setup_intr(sc);
 519         if (error) {
 520                 ether_ifdetach(&sc->arpcom.ac_if);
 521                 goto failed;
 522         }
 523         return 0;
 524
 525 failed:
 526         igb_detach(dev);
 527         return error;
 528 }
 529
 530 static int
 531 igb_detach(device_t dev)
 532 {
 533         struct igb_softc *sc = device_get_softc(dev);
 534
 535         if (device_is_attached(dev)) {
 536                 struct ifnet *ifp = &sc->arpcom.ac_if;
 537
 538                 ifnet_serialize_all(ifp);
 539
 540                 igb_stop(sc);
 541
 542                 e1000_phy_hw_reset(&sc->hw);
 543
 544                 /* Give control back to firmware */
 545                 igb_rel_mgmt(sc);
 546                 igb_rel_hw_control(sc);
 547
 548                 if (sc->wol) {
 549                         E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
 550                         E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
 551                         igb_enable_wol(dev);
 552                 }
 553
 554                 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
 555
 556                 ifnet_deserialize_all(ifp);
 557
 558                 ether_ifdetach(ifp);
 559         } else if (sc->mem_res != NULL) {
 560                 igb_rel_hw_control(sc);
 561         }
 562         bus_generic_detach(dev);
 563
 564         if (sc->intr_res != NULL) {
 565                 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
 566                     sc->intr_res);
 567         }
 568         if (sc->intr_type == PCI_INTR_TYPE_MSI)
 569                 pci_release_msi(dev);
 570
 571         if (sc->mem_res != NULL) {
 572                 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
 573                     sc->mem_res);
 574         }
 575
 576         igb_dma_free(sc);
 577
 578         if (sc->mta != NULL)
 579                 kfree(sc->mta, M_DEVBUF);
 580         if (sc->stats != NULL)
 581                 kfree(sc->stats, M_DEVBUF);
 582
 583         if (sc->sysctl_tree != NULL)
 584                 sysctl_ctx_free(&sc->sysctl_ctx);
 585
 586         return 0;
 587 }
 588
 589 static int
 590 igb_shutdown(device_t dev)
 591 {
 592         return igb_suspend(dev);
 593 }
 594
 595 static int
 596 igb_suspend(device_t dev)
 597 {
 598         struct igb_softc *sc = device_get_softc(dev);
 599         struct ifnet *ifp = &sc->arpcom.ac_if;
 600
 601         ifnet_serialize_all(ifp);
 602
 603         igb_stop(sc);
 604
 605         igb_rel_mgmt(sc);
 606         igb_rel_hw_control(sc);
 607
 608         if (sc->wol) {
 609                 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
 610                 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
 611                 igb_enable_wol(dev);
 612         }
 613
 614         ifnet_deserialize_all(ifp);
 615
 616         return bus_generic_suspend(dev);
 617 }
 618
 619 static int
 620 igb_resume(device_t dev)
 621 {
 622         struct igb_softc *sc = device_get_softc(dev);
 623         struct ifnet *ifp = &sc->arpcom.ac_if;
 624
 625         ifnet_serialize_all(ifp);
 626
 627         igb_init(sc);
 628         igb_get_mgmt(sc);
 629
 630         if_devstart(ifp);
 631
 632         ifnet_deserialize_all(ifp);
 633
 634         return bus_generic_resume(dev);
 635 }
 636
 637 static int
 638 igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
 639 {
 640         struct igb_softc *sc = ifp->if_softc;
 641         struct ifreq *ifr = (struct ifreq *)data;
 642         int max_frame_size, mask, reinit;
 643         int error = 0;
 644
 645         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 646
 647         switch (command) {
 648         case SIOCSIFMTU:
 649                 max_frame_size = 9234;
 650                 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
 651                     ETHER_CRC_LEN) {
 652                         error = EINVAL;
 653                         break;
 654                 }
 655
 656                 ifp->if_mtu = ifr->ifr_mtu;
 657                 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
 658                     ETHER_CRC_LEN;
 659
 660                 if (ifp->if_flags & IFF_RUNNING)
 661                         igb_init(sc);
 662                 break;
 663
 664         case SIOCSIFFLAGS:
 665                 if (ifp->if_flags & IFF_UP) {
 666                         if (ifp->if_flags & IFF_RUNNING) {
 667                                 if ((ifp->if_flags ^ sc->if_flags) &
 668                                     (IFF_PROMISC | IFF_ALLMULTI)) {
 669                                         igb_disable_promisc(sc);
 670                                         igb_set_promisc(sc);
 671                                 }
 672                         } else {
 673                                 igb_init(sc);
 674                         }
 675                 } else if (ifp->if_flags & IFF_RUNNING) {
 676                         igb_stop(sc);
 677                 }
 678                 sc->if_flags = ifp->if_flags;
 679                 break;
 680
 681         case SIOCADDMULTI:
 682         case SIOCDELMULTI:
 683                 if (ifp->if_flags & IFF_RUNNING) {
 684                         igb_disable_intr(sc);
 685                         igb_set_multi(sc);
 686 #ifdef DEVICE_POLLING
 687                         if (!(ifp->if_flags & IFF_POLLING))
 688 #endif
 689                                 igb_enable_intr(sc);
 690                 }
 691                 break;
 692
 693         case SIOCSIFMEDIA:
 694                 /*
 695                  * As the speed/duplex settings are being
 696                  * changed, we need toreset the PHY.
 697                  */
 698                 sc->hw.phy.reset_disable = FALSE;
 699
 700                 /* Check SOL/IDER usage */
 701                 if (e1000_check_reset_block(&sc->hw)) {
 702                         if_printf(ifp, "Media change is "
 703                             "blocked due to SOL/IDER session.\n");
 704                         break;
 705                 }
 706                 /* FALL THROUGH */
 707
 708         case SIOCGIFMEDIA:
 709                 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
 710                 break;
 711
 712         case SIOCSIFCAP:
 713                 reinit = 0;
 714                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
 715                 if (mask & IFCAP_HWCSUM) {
 716                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
 717                         reinit = 1;
 718                 }
 719                 if (mask & IFCAP_VLAN_HWTAGGING) {
 720                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
 721                         reinit = 1;
 722                 }
 723                 if (reinit && (ifp->if_flags & IFF_RUNNING))
 724                         igb_init(sc);
 725                 break;
 726
 727         default:
 728                 error = ether_ioctl(ifp, command, data);
 729                 break;
 730         }
 731         return error;
 732 }
 733
 734 static void
 735 igb_init(void *xsc)
 736 {
 737         struct igb_softc *sc = xsc;
 738         struct ifnet *ifp = &sc->arpcom.ac_if;
 739         int i;
 740
 741         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 742
 743         igb_stop(sc);
 744
 745         /* Get the latest mac address, User can use a LAA */
 746         bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
 747
 748         /* Put the address into the Receive Address Array */
 749         e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
 750
 751         igb_reset(sc);
 752         igb_update_link_status(sc);
 753
 754         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
 755
 756         /* Set hardware offload abilities */
 757         if (ifp->if_capenable & IFCAP_TXCSUM)
 758                 ifp->if_hwassist = IGB_CSUM_FEATURES;
 759         else
 760                 ifp->if_hwassist = 0;
 761
 762         /* Configure for OS presence */
 763         igb_get_mgmt(sc);
 764
 765         /* Prepare transmit descriptors and buffers */
 766         for (i = 0; i < sc->tx_ring_cnt; ++i)
 767                 igb_init_tx_ring(&sc->tx_rings[i]);
 768         igb_init_tx_unit(sc);
 769
 770         /* Setup Multicast table */
 771         igb_set_multi(sc);
 772
 773 #if 0
 774         /*
 775          * Figure out the desired mbuf pool
 776          * for doing jumbo/packetsplit
 777          */
 778         if (adapter->max_frame_size <= 2048)
 779                 adapter->rx_mbuf_sz = MCLBYTES;
 780         else if (adapter->max_frame_size <= 4096)
 781                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
 782         else
 783                 adapter->rx_mbuf_sz = MJUM9BYTES;
 784 #endif
 785
 786         /* Initialize interrupt */
 787         igb_init_intr(sc);
 788
 789         /* Prepare receive descriptors and buffers */
 790         for (i = 0; i < sc->rx_ring_cnt; ++i) {
 791                 int error;
 792
 793                 error = igb_init_rx_ring(&sc->rx_rings[i]);
 794                 if (error) {
 795                         if_printf(ifp, "Could not setup receive structures\n");
 796                         igb_stop(sc);
 797                         return;
 798                 }
 799         }
 800         igb_init_rx_unit(sc);
 801
 802         /* Enable VLAN support */
 803         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
 804                 igb_set_vlan(sc);
 805
 806         /* Don't lose promiscuous settings */
 807         igb_set_promisc(sc);
 808
 809         ifp->if_flags |= IFF_RUNNING;
 810         ifp->if_flags &= ~IFF_OACTIVE;
 811
 812         callout_reset(&sc->timer, hz, igb_timer, sc);
 813         e1000_clear_hw_cntrs_base_generic(&sc->hw);
 814
 815 #if 0
 816         if (adapter->msix > 1) /* Set up queue routing */
 817                 igb_configure_queues(adapter);
 818 #endif
 819
 820         /* this clears any pending interrupts */
 821         E1000_READ_REG(&sc->hw, E1000_ICR);
 822 #ifdef DEVICE_POLLING
 823         /*
 824          * Only enable interrupts if we are not polling, make sure
 825          * they are off otherwise.
 826          */
 827         if (ifp->if_flags & IFF_POLLING)
 828                 igb_disable_intr(sc);
 829         else
 830 #endif /* DEVICE_POLLING */
 831         {
 832                 igb_enable_intr(sc);
 833                 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
 834         }
 835
 836         /* Set Energy Efficient Ethernet */
 837         e1000_set_eee_i350(&sc->hw);
 838
 839         /* Don't reset the phy next time init gets called */
 840         sc->hw.phy.reset_disable = TRUE;
 841 }
 842
 843 static void
 844 igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
 845 {
 846         struct igb_softc *sc = ifp->if_softc;
 847         u_char fiber_type = IFM_1000_SX;
 848
 849         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 850
 851         igb_update_link_status(sc);
 852
 853         ifmr->ifm_status = IFM_AVALID;
 854         ifmr->ifm_active = IFM_ETHER;
 855
 856         if (!sc->link_active)
 857                 return;
 858
 859         ifmr->ifm_status |= IFM_ACTIVE;
 860
 861         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
 862             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
 863                 ifmr->ifm_active |= fiber_type | IFM_FDX;
 864         } else {
 865                 switch (sc->link_speed) {
 866                 case 10:
 867                         ifmr->ifm_active |= IFM_10_T;
 868                         break;
 869
 870                 case 100:
 871                         ifmr->ifm_active |= IFM_100_TX;
 872                         break;
 873
 874                 case 1000:
 875                         ifmr->ifm_active |= IFM_1000_T;
 876                         break;
 877                 }
 878                 if (sc->link_duplex == FULL_DUPLEX)
 879                         ifmr->ifm_active |= IFM_FDX;
 880                 else
 881                         ifmr->ifm_active |= IFM_HDX;
 882         }
 883 }
 884
 885 static int
 886 igb_media_change(struct ifnet *ifp)
 887 {
 888         struct igb_softc *sc = ifp->if_softc;
 889         struct ifmedia *ifm = &sc->media;
 890
 891         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 892
 893         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
 894                 return EINVAL;
 895
 896         switch (IFM_SUBTYPE(ifm->ifm_media)) {
 897         case IFM_AUTO:
 898                 sc->hw.mac.autoneg = DO_AUTO_NEG;
 899                 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
 900                 break;
 901
 902         case IFM_1000_LX:
 903         case IFM_1000_SX:
 904         case IFM_1000_T:
 905                 sc->hw.mac.autoneg = DO_AUTO_NEG;
 906                 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
 907                 break;
 908
 909         case IFM_100_TX:
 910                 sc->hw.mac.autoneg = FALSE;
 911                 sc->hw.phy.autoneg_advertised = 0;
 912                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
 913                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
 914                 else
 915                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
 916                 break;
 917
 918         case IFM_10_T:
 919                 sc->hw.mac.autoneg = FALSE;
 920                 sc->hw.phy.autoneg_advertised = 0;
 921                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
 922                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
 923                 else
 924                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
 925                 break;
 926
 927         default:
 928                 if_printf(ifp, "Unsupported media type\n");
 929                 break;
 930         }
 931
 932         igb_init(sc);
 933
 934         return 0;
 935 }
 936
 937 static void
 938 igb_set_promisc(struct igb_softc *sc)
 939 {
 940         struct ifnet *ifp = &sc->arpcom.ac_if;
 941         struct e1000_hw *hw = &sc->hw;
 942         uint32_t reg;
 943
 944         if (sc->vf_ifp) {
 945                 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
 946                 return;
 947         }
 948
 949         reg = E1000_READ_REG(hw, E1000_RCTL);
 950         if (ifp->if_flags & IFF_PROMISC) {
 951                 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
 952                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
 953         } else if (ifp->if_flags & IFF_ALLMULTI) {
 954                 reg |= E1000_RCTL_MPE;
 955                 reg &= ~E1000_RCTL_UPE;
 956                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
 957         }
 958 }
 959
 960 static void
 961 igb_disable_promisc(struct igb_softc *sc)
 962 {
 963         struct e1000_hw *hw = &sc->hw;
 964         uint32_t reg;
 965
 966         if (sc->vf_ifp) {
 967                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
 968                 return;
 969         }
 970         reg = E1000_READ_REG(hw, E1000_RCTL);
 971         reg &= ~E1000_RCTL_UPE;
 972         reg &= ~E1000_RCTL_MPE;
 973         E1000_WRITE_REG(hw, E1000_RCTL, reg);
 974 }
 975
 976 static void
 977 igb_set_multi(struct igb_softc *sc)
 978 {
 979         struct ifnet *ifp = &sc->arpcom.ac_if;
 980         struct ifmultiaddr *ifma;
 981         uint32_t reg_rctl = 0;
 982         uint8_t *mta;
 983         int mcnt = 0;
 984
 985         mta = sc->mta;
 986         bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
 987
 988         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 989                 if (ifma->ifma_addr->sa_family != AF_LINK)
 990                         continue;
 991
 992                 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
 993                         break;
 994
 995                 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
 996                     &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
 997                 mcnt++;
 998         }
 999
1000         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1001                 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1002                 reg_rctl |= E1000_RCTL_MPE;
1003                 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1004         } else {
1005                 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1006         }
1007 }
1008
1009 static void
1010 igb_timer(void *xsc)
1011 {
1012         struct igb_softc *sc = xsc;
1013         struct ifnet *ifp = &sc->arpcom.ac_if;
1014
1015         ifnet_serialize_all(ifp);
1016
1017         igb_update_link_status(sc);
1018         igb_update_stats_counters(sc);
1019
1020         callout_reset(&sc->timer, hz, igb_timer, sc);
1021
1022         ifnet_deserialize_all(ifp);
1023 }
1024
1025 static void
1026 igb_update_link_status(struct igb_softc *sc)
1027 {
1028         struct ifnet *ifp = &sc->arpcom.ac_if;
1029         struct e1000_hw *hw = &sc->hw;
1030         uint32_t link_check, thstat, ctrl;
1031
1032         link_check = thstat = ctrl = 0;
1033
1034         /* Get the cached link value or read for real */
1035         switch (hw->phy.media_type) {
1036         case e1000_media_type_copper:
1037                 if (hw->mac.get_link_status) {
1038                         /* Do the work to read phy */
1039                         e1000_check_for_link(hw);
1040                         link_check = !hw->mac.get_link_status;
1041                 } else {
1042                         link_check = TRUE;
1043                 }
1044                 break;
1045
1046         case e1000_media_type_fiber:
1047                 e1000_check_for_link(hw);
1048                 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1049                 break;
1050
1051         case e1000_media_type_internal_serdes:
1052                 e1000_check_for_link(hw);
1053                 link_check = hw->mac.serdes_has_link;
1054                 break;
1055
1056         /* VF device is type_unknown */
1057         case e1000_media_type_unknown:
1058                 e1000_check_for_link(hw);
1059                 link_check = !hw->mac.get_link_status;
1060                 /* Fall thru */
1061         default:
1062                 break;
1063         }
1064
1065         /* Check for thermal downshift or shutdown */
1066         if (hw->mac.type == e1000_i350) {
1067                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1068                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1069         }
1070
1071         /* Now we check if a transition has happened */
1072         if (link_check && sc->link_active == 0) {
1073                 e1000_get_speed_and_duplex(hw,
1074                     &sc->link_speed, &sc->link_duplex);
1075                 if (bootverbose) {
1076                         if_printf(ifp, "Link is up %d Mbps %s\n",
1077                             sc->link_speed,
1078                             sc->link_duplex == FULL_DUPLEX ?
1079                             "Full Duplex" : "Half Duplex");
1080                 }
1081                 sc->link_active = 1;
1082
1083                 ifp->if_baudrate = sc->link_speed * 1000000;
1084                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1085                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1086                         if_printf(ifp, "Link: thermal downshift\n");
1087                 /* This can sleep */
1088                 ifp->if_link_state = LINK_STATE_UP;
1089                 if_link_state_change(ifp);
1090         } else if (!link_check && sc->link_active == 1) {
1091                 ifp->if_baudrate = sc->link_speed = 0;
1092                 sc->link_duplex = 0;
1093                 if (bootverbose)
1094                         if_printf(ifp, "Link is Down\n");
1095                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1096                     (thstat & E1000_THSTAT_PWR_DOWN))
1097                         if_printf(ifp, "Link: thermal shutdown\n");
1098                 sc->link_active = 0;
1099                 /* This can sleep */
1100                 ifp->if_link_state = LINK_STATE_DOWN;
1101                 if_link_state_change(ifp);
1102         }
1103 }
1104
1105 static void
1106 igb_stop(struct igb_softc *sc)
1107 {
1108         struct ifnet *ifp = &sc->arpcom.ac_if;
1109         int i;
1110
1111         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1112
1113         igb_disable_intr(sc);
1114
1115         callout_stop(&sc->timer);
1116
1117         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1118         ifp->if_timer = 0;
1119
1120         e1000_reset_hw(&sc->hw);
1121         E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1122
1123         e1000_led_off(&sc->hw);
1124         e1000_cleanup_led(&sc->hw);
1125
1126         for (i = 0; i < sc->tx_ring_cnt; ++i)
1127                 igb_free_tx_ring(&sc->tx_rings[i]);
1128         for (i = 0; i < sc->rx_ring_cnt; ++i)
1129                 igb_free_rx_ring(&sc->rx_rings[i]);
1130 }
1131
1132 static void
1133 igb_reset(struct igb_softc *sc)
1134 {
1135         struct ifnet *ifp = &sc->arpcom.ac_if;
1136         struct e1000_hw *hw = &sc->hw;
1137         struct e1000_fc_info *fc = &hw->fc;
1138         uint32_t pba = 0;
1139         uint16_t hwm;
1140
1141         /* Let the firmware know the OS is in control */
1142         igb_get_hw_control(sc);
1143
1144         /*
1145          * Packet Buffer Allocation (PBA)
1146          * Writing PBA sets the receive portion of the buffer
1147          * the remainder is used for the transmit buffer.
1148          */
1149         switch (hw->mac.type) {
1150         case e1000_82575:
1151                 pba = E1000_PBA_32K;
1152                 break;
1153
1154         case e1000_82576:
1155         case e1000_vfadapt:
1156                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1157                 pba &= E1000_RXPBS_SIZE_MASK_82576;
1158                 break;
1159
1160         case e1000_82580:
1161         case e1000_i350:
1162         case e1000_vfadapt_i350:
1163                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1164                 pba = e1000_rxpbs_adjust_82580(pba);
1165                 break;
1166                 /* XXX pba = E1000_PBA_35K; */
1167
1168         default:
1169                 break;
1170         }
1171
1172         /* Special needs in case of Jumbo frames */
1173         if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1174                 uint32_t tx_space, min_tx, min_rx;
1175
1176                 pba = E1000_READ_REG(hw, E1000_PBA);
1177                 tx_space = pba >> 16;
1178                 pba &= 0xffff;
1179
1180                 min_tx = (sc->max_frame_size +
1181                     sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1182                 min_tx = roundup2(min_tx, 1024);
1183                 min_tx >>= 10;
1184                 min_rx = sc->max_frame_size;
1185                 min_rx = roundup2(min_rx, 1024);
1186                 min_rx >>= 10;
1187                 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1188                         pba = pba - (min_tx - tx_space);
1189                         /*
1190                          * if short on rx space, rx wins
1191                          * and must trump tx adjustment
1192                          */
1193                         if (pba < min_rx)
1194                                 pba = min_rx;
1195                 }
1196                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1197         }
1198
1199         /*
1200          * These parameters control the automatic generation (Tx) and
1201          * response (Rx) to Ethernet PAUSE frames.
1202          * - High water mark should allow for at least two frames to be
1203          *   received after sending an XOFF.
1204          * - Low water mark works best when it is very near the high water mark.
1205          *   This allows the receiver to restart by sending XON when it has
1206          *   drained a bit.
1207          */
1208         hwm = min(((pba << 10) * 9 / 10),
1209             ((pba << 10) - 2 * sc->max_frame_size));
1210
1211         if (hw->mac.type < e1000_82576) {
1212                 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1213                 fc->low_water = fc->high_water - 8;
1214         } else {
1215                 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1216                 fc->low_water = fc->high_water - 16;
1217         }
1218         fc->pause_time = IGB_FC_PAUSE_TIME;
1219         fc->send_xon = TRUE;
1220
1221         /* Issue a global reset */
1222         e1000_reset_hw(hw);
1223         E1000_WRITE_REG(hw, E1000_WUC, 0);
1224
1225         if (e1000_init_hw(hw) < 0)
1226                 if_printf(ifp, "Hardware Initialization Failed\n");
1227
1228         /* Setup DMA Coalescing */
1229         if (hw->mac.type == e1000_i350 && sc->dma_coalesce) {
1230                 uint32_t reg;
1231
1232                 hwm = (pba - 4) << 10;
1233                 reg = ((pba - 6) << E1000_DMACR_DMACTHR_SHIFT)
1234                     & E1000_DMACR_DMACTHR_MASK;
1235
1236                 /* transition to L0x or L1 if available..*/
1237                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1238
1239                 /* timer = +-1000 usec in 32usec intervals */
1240                 reg |= (1000 >> 5);
1241                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1242
1243                 /* No lower threshold */
1244                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1245
1246                 /* set hwm to PBA -  2 * max frame size */
1247                 E1000_WRITE_REG(hw, E1000_FCRTC, hwm);
1248
1249                 /* Set the interval before transition */
1250                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1251                 reg |= 0x800000FF; /* 255 usec */
1252                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1253
1254                 /* free space in tx packet buffer to wake from DMA coal */
1255                 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1256                     (20480 - (2 * sc->max_frame_size)) >> 6);
1257
1258                 /* make low power state decision controlled by DMA coal */
1259                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1260                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1261                     reg | E1000_PCIEMISC_LX_DECISION);
1262                 if_printf(ifp, "DMA Coalescing enabled\n");
1263         }
1264
1265         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1266         e1000_get_phy_info(hw);
1267         e1000_check_for_link(hw);
1268 }
1269
1270 static void
1271 igb_setup_ifp(struct igb_softc *sc)
1272 {
1273         struct ifnet *ifp = &sc->arpcom.ac_if;
1274
1275         if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
1276         ifp->if_softc = sc;
1277         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1278         ifp->if_init =  igb_init;
1279         ifp->if_ioctl = igb_ioctl;
1280         ifp->if_start = igb_start;
1281 #ifdef DEVICE_POLLING
1282         ifp->if_poll = igb_poll;
1283 #endif
1284         ifp->if_watchdog = igb_watchdog;
1285
1286         ifq_set_maxlen(&ifp->if_snd, sc->num_tx_desc - 1);
1287         ifq_set_ready(&ifp->if_snd);
1288
1289         ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1290
1291         ifp->if_capabilities =
1292             IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1293         ifp->if_capenable = ifp->if_capabilities;
1294         ifp->if_hwassist = IGB_CSUM_FEATURES;
1295
1296         /*
1297          * Tell the upper layer(s) we support long frames
1298          */
1299         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1300
1301         /*
1302          * Specify the media types supported by this adapter and register
1303          * callbacks to update media and link information
1304          */
1305         ifmedia_init(&sc->media, IFM_IMASK, igb_media_change, igb_media_status);
1306         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1307             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1308                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1309                     0, NULL);
1310                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1311         } else {
1312                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1313                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1314                     0, NULL);
1315                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1316                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1317                     0, NULL);
1318                 if (sc->hw.phy.type != e1000_phy_ife) {
1319                         ifmedia_add(&sc->media,
1320                             IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1321                         ifmedia_add(&sc->media,
1322                             IFM_ETHER | IFM_1000_T, 0, NULL);
1323                 }
1324         }
1325         ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1326         ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1327 }
1328
1329 static void
1330 igb_add_sysctl(struct igb_softc *sc)
1331 {
1332         sysctl_ctx_init(&sc->sysctl_ctx);
1333         sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1334             SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1335             device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "");
1336         if (sc->sysctl_tree == NULL) {
1337                 device_printf(sc->dev, "can't add sysctl node\n");
1338                 return;
1339         }
1340
1341         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1342             OID_AUTO, "rxd", CTLFLAG_RD, &sc->num_rx_desc, 0, NULL);
1343         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1344             OID_AUTO, "txd", CTLFLAG_RD, &sc->num_tx_desc, 0, NULL);
1345
1346         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1347             OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1348             sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1349
1350         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1351             OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1352             sc, 0, igb_sysctl_tx_intr_nsegs, "I",
1353             "# segments per TX interrupt");
1354 }
1355
1356 static int
1357 igb_dma_alloc(struct igb_softc *sc)
1358 {
1359         int error, i;
1360
1361         /*
1362          * Create top level busdma tag
1363          */
1364         error = bus_dma_tag_create(NULL, 1, 0,
1365             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1366             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1367             &sc->parent_tag);
1368         if (error) {
1369                 device_printf(sc->dev, "could not create top level DMA tag\n");
1370                 return error;
1371         }
1372
1373         /*
1374          * Allocate TX descriptor rings and buffers
1375          */
1376         sc->tx_rings = kmalloc(sizeof(struct igb_tx_ring) * sc->tx_ring_cnt,
1377             M_DEVBUF, M_WAITOK | M_ZERO);
1378         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1379                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1380
1381                 /* Set up some basics */
1382                 txr->sc = sc;
1383                 txr->me = i;
1384
1385                 error = igb_create_tx_ring(txr);
1386                 if (error)
1387                         return error;
1388         }
1389
1390         /*
1391          * Allocate RX descriptor rings and buffers
1392          */
1393         sc->rx_rings = kmalloc(sizeof(struct igb_rx_ring) * sc->rx_ring_cnt,
1394             M_DEVBUF, M_WAITOK | M_ZERO);
1395         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1396                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1397
1398                 /* Set up some basics */
1399                 rxr->sc = sc;
1400                 rxr->me = i;
1401
1402                 error = igb_create_rx_ring(rxr);
1403                 if (error)
1404                         return error;
1405         }
1406
1407         return 0;
1408 }
1409
1410 static void
1411 igb_dma_free(struct igb_softc *sc)
1412 {
1413         int i;
1414
1415         if (sc->tx_rings != NULL) {
1416                 for (i = 0; i < sc->tx_ring_cnt; ++i)
1417                         igb_destroy_tx_ring(&sc->tx_rings[i], sc->num_tx_desc);
1418                 kfree(sc->tx_rings, M_DEVBUF);
1419         }
1420
1421         if (sc->rx_rings != NULL) {
1422                 for (i = 0; i < sc->rx_ring_cnt; ++i)
1423                         igb_destroy_rx_ring(&sc->rx_rings[i], sc->num_rx_desc);
1424                 kfree(sc->rx_rings, M_DEVBUF);
1425         }
1426 }
1427
1428 static int
1429 igb_create_tx_ring(struct igb_tx_ring *txr)
1430 {
1431         int tsize, error, i;
1432
1433         /*
1434          * Validate number of transmit descriptors. It must not exceed
1435          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1436          */
1437         if (((igb_txd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN) != 0 ||
1438             (igb_txd > IGB_MAX_TXD) || (igb_txd < IGB_MIN_TXD)) {
1439                 device_printf(txr->sc->dev,
1440                     "Using %d TX descriptors instead of %d!\n",
1441                     IGB_DEFAULT_TXD, igb_txd);
1442                 txr->sc->num_tx_desc = IGB_DEFAULT_TXD;
1443         } else {
1444                 txr->sc->num_tx_desc = igb_txd;
1445         }
1446
1447         /*
1448          * Allocate TX descriptor ring
1449          */
1450         tsize = roundup2(txr->sc->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1451             IGB_DBA_ALIGN);
1452         txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1453             IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1454             &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1455         if (txr->txdma.dma_vaddr == NULL) {
1456                 device_printf(txr->sc->dev,
1457                     "Unable to allocate TX Descriptor memory\n");
1458                 return ENOMEM;
1459         }
1460         txr->tx_base = txr->txdma.dma_vaddr;
1461         bzero(txr->tx_base, tsize);
1462
1463         txr->tx_buf = kmalloc(sizeof(struct igb_tx_buf) * txr->sc->num_tx_desc,
1464             M_DEVBUF, M_WAITOK | M_ZERO);
1465
1466         /*
1467          * Allocate TX head write-back buffer
1468          */
1469         txr->tx_hdr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1470             __VM_CACHELINE_SIZE, __VM_CACHELINE_SIZE, BUS_DMA_WAITOK,
1471             &txr->tx_hdr_dtag, &txr->tx_hdr_dmap, &txr->tx_hdr_paddr);
1472         if (txr->tx_hdr == NULL) {
1473                 device_printf(txr->sc->dev,
1474                     "Unable to allocate TX head write-back buffer\n");
1475                 return ENOMEM;
1476         }
1477
1478         /*
1479          * Create DMA tag for TX buffers
1480          */
1481         error = bus_dma_tag_create(txr->sc->parent_tag,
1482             1, 0,               /* alignment, bounds */
1483             BUS_SPACE_MAXADDR,  /* lowaddr */
1484             BUS_SPACE_MAXADDR,  /* highaddr */
1485             NULL, NULL,         /* filter, filterarg */
1486             IGB_TSO_SIZE,       /* maxsize */
1487             IGB_MAX_SCATTER,    /* nsegments */
1488             PAGE_SIZE,          /* maxsegsize */
1489             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1490             BUS_DMA_ONEBPAGE,   /* flags */
1491             &txr->tx_tag);
1492         if (error) {
1493                 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1494                 kfree(txr->tx_buf, M_DEVBUF);
1495                 txr->tx_buf = NULL;
1496                 return error;
1497         }
1498
1499         /*
1500          * Create DMA maps for TX buffers
1501          */
1502         for (i = 0; i < txr->sc->num_tx_desc; ++i) {
1503                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1504
1505                 error = bus_dmamap_create(txr->tx_tag,
1506                     BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1507                 if (error) {
1508                         device_printf(txr->sc->dev,
1509                             "Unable to create TX DMA map\n");
1510                         igb_destroy_tx_ring(txr, i);
1511                         return error;
1512                 }
1513         }
1514
1515         /*
1516          * Initialize various watermark
1517          */
1518         txr->spare_desc = IGB_TX_SPARE;
1519         txr->intr_nsegs = txr->sc->num_tx_desc / 16;
1520         txr->oact_hi_desc = txr->sc->num_tx_desc / 2;
1521         txr->oact_lo_desc = txr->sc->num_tx_desc / 8;
1522         if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
1523                 txr->oact_lo_desc = IGB_TX_OACTIVE_MAX;
1524         if (txr->oact_lo_desc < txr->spare_desc + IGB_TX_RESERVED)
1525                 txr->oact_lo_desc = txr->spare_desc + IGB_TX_RESERVED;
1526
1527         return 0;
1528 }
1529
1530 static void
1531 igb_free_tx_ring(struct igb_tx_ring *txr)
1532 {
1533         int i;
1534
1535         for (i = 0; i < txr->sc->num_tx_desc; ++i) {
1536                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1537
1538                 if (txbuf->m_head != NULL) {
1539                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1540                         m_freem(txbuf->m_head);
1541                         txbuf->m_head = NULL;
1542                 }
1543         }
1544 }
1545
1546 static void
1547 igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1548 {
1549         int i;
1550
1551         if (txr->txdma.dma_vaddr != NULL) {
1552                 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1553                 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1554                     txr->txdma.dma_map);
1555                 bus_dma_tag_destroy(txr->txdma.dma_tag);
1556                 txr->txdma.dma_vaddr = NULL;
1557         }
1558
1559         if (txr->tx_hdr != NULL) {
1560                 bus_dmamap_unload(txr->tx_hdr_dtag, txr->tx_hdr_dmap);
1561                 bus_dmamem_free(txr->tx_hdr_dtag, txr->tx_hdr,
1562                     txr->tx_hdr_dmap);
1563                 bus_dma_tag_destroy(txr->tx_hdr_dtag);
1564                 txr->tx_hdr = NULL;
1565         }
1566
1567         if (txr->tx_buf == NULL)
1568                 return;
1569
1570         for (i = 0; i < ndesc; ++i) {
1571                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1572
1573                 KKASSERT(txbuf->m_head == NULL);
1574                 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1575         }
1576         bus_dma_tag_destroy(txr->tx_tag);
1577
1578         kfree(txr->tx_buf, M_DEVBUF);
1579         txr->tx_buf = NULL;
1580 }
1581
1582 static void
1583 igb_init_tx_ring(struct igb_tx_ring *txr)
1584 {
1585         /* Clear the old descriptor contents */
1586         bzero(txr->tx_base,
1587             sizeof(union e1000_adv_tx_desc) * txr->sc->num_tx_desc);
1588
1589         /* Clear TX head write-back buffer */
1590         *(txr->tx_hdr) = 0;
1591
1592         /* Reset indices */
1593         txr->next_avail_desc = 0;
1594         txr->next_to_clean = 0;
1595         txr->tx_nsegs = 0;
1596
1597         /* Set number of descriptors available */
1598         txr->tx_avail = txr->sc->num_tx_desc;
1599 }
1600
1601 static void
1602 igb_init_tx_unit(struct igb_softc *sc)
1603 {
1604         struct e1000_hw *hw = &sc->hw;
1605         uint32_t tctl;
1606         int i;
1607
1608         /* Setup the Tx Descriptor Rings */
1609         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1610                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1611                 uint64_t bus_addr = txr->txdma.dma_paddr;
1612                 uint64_t hdr_paddr = txr->tx_hdr_paddr;
1613                 uint32_t txdctl = 0;
1614                 uint32_t dca_txctrl;
1615
1616                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1617                     sc->num_tx_desc * sizeof(struct e1000_tx_desc));
1618                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1619                     (uint32_t)(bus_addr >> 32));
1620                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
1621                     (uint32_t)bus_addr);
1622
1623                 /* Setup the HW Tx Head and Tail descriptor pointers */
1624                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1625                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1626
1627                 txdctl |= IGB_TX_PTHRESH;
1628                 txdctl |= IGB_TX_HTHRESH << 8;
1629                 txdctl |= IGB_TX_WTHRESH << 16;
1630                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1631                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1632
1633                 dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));
1634                 dca_txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1635                 E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(i), dca_txctrl);
1636
1637                 E1000_WRITE_REG(hw, E1000_TDWBAH(i),
1638                     (uint32_t)(hdr_paddr >> 32));
1639                 E1000_WRITE_REG(hw, E1000_TDWBAL(i),
1640                     ((uint32_t)hdr_paddr) | E1000_TX_HEAD_WB_ENABLE);
1641         }
1642
1643         if (sc->vf_ifp)
1644                 return;
1645
1646         e1000_config_collision_dist(hw);
1647
1648         /* Program the Transmit Control Register */
1649         tctl = E1000_READ_REG(hw, E1000_TCTL);
1650         tctl &= ~E1000_TCTL_CT;
1651         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1652             (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1653
1654         /* This write will effectively turn on the transmit unit. */
1655         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1656 }
1657
1658 static boolean_t
1659 igb_txctx(struct igb_tx_ring *txr, struct mbuf *mp)
1660 {
1661         struct e1000_adv_tx_context_desc *TXD;
1662         struct igb_tx_buf *txbuf;
1663         uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
1664         struct ether_vlan_header *eh;
1665         struct ip *ip = NULL;
1666         int ehdrlen, ctxd, ip_hlen = 0;
1667         uint16_t etype, vlantag = 0;
1668         boolean_t offload = TRUE;
1669
1670         if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
1671                 offload = FALSE;
1672
1673         vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
1674         ctxd = txr->next_avail_desc;
1675         txbuf = &txr->tx_buf[ctxd];
1676         TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
1677
1678         /*
1679          * In advanced descriptors the vlan tag must
1680          * be placed into the context descriptor, thus
1681          * we need to be here just for that setup.
1682          */
1683         if (mp->m_flags & M_VLANTAG) {
1684                 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
1685                 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
1686         } else if (!offload) {
1687                 return FALSE;
1688         }
1689
1690         /*
1691          * Determine where frame payload starts.
1692          * Jump over vlan headers if already present,
1693          * helpful for QinQ too.
1694          */
1695         KASSERT(mp->m_len >= ETHER_HDR_LEN,
1696             ("igb_txctx_pullup is not called (eh)?\n"));
1697         eh = mtod(mp, struct ether_vlan_header *);
1698         if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
1699                 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN,
1700                     ("igb_txctx_pullup is not called (evh)?\n"));
1701                 etype = ntohs(eh->evl_proto);
1702                 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN;
1703         } else {
1704                 etype = ntohs(eh->evl_encap_proto);
1705                 ehdrlen = ETHER_HDR_LEN;
1706         }
1707
1708         /* Set the ether header length */
1709         vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
1710
1711         switch (etype) {
1712         case ETHERTYPE_IP:
1713                 KASSERT(mp->m_len >= ehdrlen + IGB_IPVHL_SIZE,
1714                     ("igb_txctx_pullup is not called (eh+ip_vhl)?\n"));
1715
1716                 /* NOTE: We could only safely access ip.ip_vhl part */
1717                 ip = (struct ip *)(mp->m_data + ehdrlen);
1718                 ip_hlen = ip->ip_hl << 2;
1719
1720                 if (mp->m_pkthdr.csum_flags & CSUM_IP)
1721                         type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
1722                 break;
1723
1724 #ifdef notyet
1725         case ETHERTYPE_IPV6:
1726                 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen);
1727                 ip_hlen = sizeof(struct ip6_hdr);
1728                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV6;
1729                 break;
1730 #endif
1731
1732         default:
1733                 offload = FALSE;
1734                 break;
1735         }
1736
1737         vlan_macip_lens |= ip_hlen;
1738         type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
1739
1740         if (mp->m_pkthdr.csum_flags & CSUM_TCP)
1741                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
1742         else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
1743                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
1744
1745         /* 82575 needs the queue index added */
1746         if (txr->sc->hw.mac.type == e1000_82575)
1747                 mss_l4len_idx = txr->me << 4;
1748
1749         /* Now copy bits into descriptor */
1750         TXD->vlan_macip_lens = htole32(vlan_macip_lens);
1751         TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
1752         TXD->seqnum_seed = htole32(0);
1753         TXD->mss_l4len_idx = htole32(mss_l4len_idx);
1754
1755         txbuf->m_head = NULL;
1756
1757         /* We've consumed the first desc, adjust counters */
1758         if (++ctxd == txr->sc->num_tx_desc)
1759                 ctxd = 0;
1760         txr->next_avail_desc = ctxd;
1761         --txr->tx_avail;
1762
1763         return offload;
1764 }
1765
1766 static void
1767 igb_txeof(struct igb_tx_ring *txr)
1768 {
1769         struct ifnet *ifp = &txr->sc->arpcom.ac_if;
1770         int first, hdr, avail;
1771
1772         if (txr->tx_avail == txr->sc->num_tx_desc)
1773                 return;
1774
1775         first = txr->next_to_clean;
1776         hdr = *(txr->tx_hdr);
1777
1778         if (first == hdr)
1779                 return;
1780
1781         avail = txr->tx_avail;
1782         while (first != hdr) {
1783                 struct igb_tx_buf *txbuf = &txr->tx_buf[first];
1784
1785                 ++avail;
1786                 if (txbuf->m_head) {
1787                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1788                         m_freem(txbuf->m_head);
1789                         txbuf->m_head = NULL;
1790                         ++ifp->if_opackets;
1791                 }
1792                 if (++first == txr->sc->num_tx_desc)
1793                         first = 0;
1794         }
1795         txr->next_to_clean = first;
1796         txr->tx_avail = avail;
1797
1798         /*
1799          * If we have a minimum free, clear IFF_OACTIVE
1800          * to tell the stack that it is OK to send packets.
1801          */
1802         if (IGB_IS_NOT_OACTIVE(txr)) {
1803                 ifp->if_flags &= ~IFF_OACTIVE;
1804
1805                 /*
1806                  * We have enough TX descriptors, turn off
1807                  * the watchdog.  We allow small amount of
1808                  * packets (roughly intr_nsegs) pending on
1809                  * the transmit ring.
1810                  */
1811                 ifp->if_timer = 0;
1812         }
1813 }
1814
1815 static int
1816 igb_create_rx_ring(struct igb_rx_ring *rxr)
1817 {
1818         int rsize, i, error;
1819
1820         /*
1821          * Validate number of receive descriptors. It must not exceed
1822          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1823          */
1824         if (((igb_rxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN) != 0 ||
1825             (igb_rxd > IGB_MAX_RXD) || (igb_rxd < IGB_MIN_RXD)) {
1826                 device_printf(rxr->sc->dev,
1827                     "Using %d RX descriptors instead of %d!\n",
1828                     IGB_DEFAULT_RXD, igb_rxd);
1829                 rxr->sc->num_rx_desc = IGB_DEFAULT_RXD;
1830         } else {
1831                 rxr->sc->num_rx_desc = igb_rxd;
1832         }
1833
1834         /*
1835          * Allocate RX descriptor ring
1836          */
1837         rsize = roundup2(rxr->sc->num_rx_desc * sizeof(union e1000_adv_rx_desc),
1838             IGB_DBA_ALIGN);
1839         rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
1840             IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
1841             &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
1842             &rxr->rxdma.dma_paddr);
1843         if (rxr->rxdma.dma_vaddr == NULL) {
1844                 device_printf(rxr->sc->dev,
1845                     "Unable to allocate RxDescriptor memory\n");
1846                 return ENOMEM;
1847         }
1848         rxr->rx_base = rxr->rxdma.dma_vaddr;
1849         bzero(rxr->rx_base, rsize);
1850
1851         rxr->rx_buf = kmalloc(sizeof(struct igb_rx_buf) * rxr->sc->num_rx_desc,
1852             M_DEVBUF, M_WAITOK | M_ZERO);
1853
1854         /*
1855          * Create DMA tag for RX buffers
1856          */
1857         error = bus_dma_tag_create(rxr->sc->parent_tag,
1858             1, 0,               /* alignment, bounds */
1859             BUS_SPACE_MAXADDR,  /* lowaddr */
1860             BUS_SPACE_MAXADDR,  /* highaddr */
1861             NULL, NULL,         /* filter, filterarg */
1862             MCLBYTES,           /* maxsize */
1863             1,                  /* nsegments */
1864             MCLBYTES,           /* maxsegsize */
1865             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
1866             &rxr->rx_tag);
1867         if (error) {
1868                 device_printf(rxr->sc->dev,
1869                     "Unable to create RX payload DMA tag\n");
1870                 kfree(rxr->rx_buf, M_DEVBUF);
1871                 rxr->rx_buf = NULL;
1872                 return error;
1873         }
1874
1875         /*
1876          * Create spare DMA map for RX buffers
1877          */
1878         error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
1879             &rxr->rx_sparemap);
1880         if (error) {
1881                 device_printf(rxr->sc->dev,
1882                     "Unable to create spare RX DMA maps\n");
1883                 bus_dma_tag_destroy(rxr->rx_tag);
1884                 kfree(rxr->rx_buf, M_DEVBUF);
1885                 rxr->rx_buf = NULL;
1886                 return error;
1887         }
1888
1889         /*
1890          * Create DMA maps for RX buffers
1891          */
1892         for (i = 0; i < rxr->sc->num_rx_desc; i++) {
1893                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
1894
1895                 error = bus_dmamap_create(rxr->rx_tag,
1896                     BUS_DMA_WAITOK, &rxbuf->map);
1897                 if (error) {
1898                         device_printf(rxr->sc->dev,
1899                             "Unable to create RX DMA maps\n");
1900                         igb_destroy_rx_ring(rxr, i);
1901                         return error;
1902                 }
1903         }
1904         return 0;
1905 }
1906
1907 static void
1908 igb_free_rx_ring(struct igb_rx_ring *rxr)
1909 {
1910         int i;
1911
1912         for (i = 0; i < rxr->sc->num_rx_desc; ++i) {
1913                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
1914
1915                 if (rxbuf->m_head != NULL) {
1916                         bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
1917                         m_freem(rxbuf->m_head);
1918                         rxbuf->m_head = NULL;
1919                 }
1920         }
1921
1922         if (rxr->fmp != NULL)
1923                 m_freem(rxr->fmp);
1924         rxr->fmp = NULL;
1925         rxr->lmp = NULL;
1926 }
1927
1928 static void
1929 igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
1930 {
1931         int i;
1932
1933         if (rxr->rxdma.dma_vaddr != NULL) {
1934                 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
1935                 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
1936                     rxr->rxdma.dma_map);
1937                 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
1938                 rxr->rxdma.dma_vaddr = NULL;
1939         }
1940
1941         if (rxr->rx_buf == NULL)
1942                 return;
1943
1944         for (i = 0; i < ndesc; ++i) {
1945                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
1946
1947                 KKASSERT(rxbuf->m_head == NULL);
1948                 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
1949         }
1950         bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
1951         bus_dma_tag_destroy(rxr->rx_tag);
1952
1953         kfree(rxr->rx_buf, M_DEVBUF);
1954         rxr->rx_buf = NULL;
1955 }
1956
1957 static void
1958 igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
1959 {
1960         rxd->read.pkt_addr = htole64(rxbuf->paddr);
1961         rxd->wb.upper.status_error = 0;
1962 }
1963
1964 static int
1965 igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
1966 {
1967         struct mbuf *m;
1968         bus_dma_segment_t seg;
1969         bus_dmamap_t map;
1970         struct igb_rx_buf *rxbuf;
1971         int error, nseg;
1972
1973         m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
1974         if (m == NULL) {
1975                 if (wait) {
1976                         if_printf(&rxr->sc->arpcom.ac_if,
1977                             "Unable to allocate RX mbuf\n");
1978                 }
1979                 return ENOBUFS;
1980         }
1981         m->m_len = m->m_pkthdr.len = MCLBYTES;
1982
1983         if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
1984                 m_adj(m, ETHER_ALIGN);
1985
1986         error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
1987             rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
1988         if (error) {
1989                 m_freem(m);
1990                 if (wait) {
1991                         if_printf(&rxr->sc->arpcom.ac_if,
1992                             "Unable to load RX mbuf\n");
1993                 }
1994                 return error;
1995         }
1996
1997         rxbuf = &rxr->rx_buf[i];
1998         if (rxbuf->m_head != NULL)
1999                 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2000
2001         map = rxbuf->map;
2002         rxbuf->map = rxr->rx_sparemap;
2003         rxr->rx_sparemap = map;
2004
2005         rxbuf->m_head = m;
2006         rxbuf->paddr = seg.ds_addr;
2007
2008         igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2009         return 0;
2010 }
2011
2012 static int
2013 igb_init_rx_ring(struct igb_rx_ring *rxr)
2014 {
2015         int i;
2016
2017         /* Clear the ring contents */
2018         bzero(rxr->rx_base,
2019             rxr->sc->num_rx_desc * sizeof(union e1000_adv_rx_desc));
2020
2021         /* Now replenish the ring mbufs */
2022         for (i = 0; i < rxr->sc->num_rx_desc; ++i) {
2023                 int error;
2024
2025                 error = igb_newbuf(rxr, i, TRUE);
2026                 if (error)
2027                         return error;
2028         }
2029
2030         /* Setup our descriptor indices */
2031         rxr->next_to_check = 0;
2032
2033         rxr->fmp = NULL;
2034         rxr->lmp = NULL;
2035         rxr->discard = FALSE;
2036
2037         return 0;
2038 }
2039
2040 static void
2041 igb_init_rx_unit(struct igb_softc *sc)
2042 {
2043         struct ifnet *ifp = &sc->arpcom.ac_if;
2044         struct e1000_hw *hw = &sc->hw;
2045         uint32_t rctl, rxcsum, srrctl = 0;
2046         int i;
2047
2048         /*
2049          * Make sure receives are disabled while setting
2050          * up the descriptor ring
2051          */
2052         rctl = E1000_READ_REG(hw, E1000_RCTL);
2053         E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2054
2055 #if 0
2056         /*
2057         ** Set up for header split
2058         */
2059         if (igb_header_split) {
2060                 /* Use a standard mbuf for the header */
2061                 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2062                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2063         } else
2064 #endif
2065                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2066
2067         /*
2068         ** Set up for jumbo frames
2069         */
2070         if (ifp->if_mtu > ETHERMTU) {
2071                 rctl |= E1000_RCTL_LPE;
2072 #if 0
2073                 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2074                         srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2075                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2076                 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2077                         srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2078                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2079                 }
2080                 /* Set maximum packet len */
2081                 psize = adapter->max_frame_size;
2082                 /* are we on a vlan? */
2083                 if (adapter->ifp->if_vlantrunk != NULL)
2084                         psize += VLAN_TAG_SIZE;
2085                 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2086 #else
2087                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2088                 rctl |= E1000_RCTL_SZ_2048;
2089 #endif
2090         } else {
2091                 rctl &= ~E1000_RCTL_LPE;
2092                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2093                 rctl |= E1000_RCTL_SZ_2048;
2094         }
2095
2096         /* Setup the Base and Length of the Rx Descriptor Rings */
2097         for (i = 0; i < sc->rx_ring_cnt; ++i) {
2098                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2099                 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2100                 uint32_t rxdctl;
2101
2102                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2103                     sc->num_rx_desc * sizeof(struct e1000_rx_desc));
2104                 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2105                     (uint32_t)(bus_addr >> 32));
2106                 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2107                     (uint32_t)bus_addr);
2108                 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2109                 /* Enable this Queue */
2110                 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2111                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2112                 rxdctl &= 0xFFF00000;
2113                 rxdctl |= IGB_RX_PTHRESH;
2114                 rxdctl |= IGB_RX_HTHRESH << 8;
2115                 rxdctl |= IGB_RX_WTHRESH << 16;
2116                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2117         }
2118
2119         /*
2120          * Setup for RX MultiQueue
2121          */
2122         rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
2123 #if 0
2124         if (sc->rx_ring_cnt >1) {
2125                 u32 random[10], mrqc, shift = 0;
2126                 union igb_reta {
2127                         u32 dword;
2128                         u8  bytes[4];
2129                 } reta;
2130
2131                 arc4rand(&random, sizeof(random), 0);
2132                 if (adapter->hw.mac.type == e1000_82575)
2133                         shift = 6;
2134                 /* Warning FM follows */
2135                 for (int i = 0; i < 128; i++) {
2136                         reta.bytes[i & 3] =
2137                             (i % sc->rx_ring_cnt) << shift;
2138                         if ((i & 3) == 3)
2139                                 E1000_WRITE_REG(hw,
2140                                     E1000_RETA(i >> 2), reta.dword);
2141                 }
2142                 /* Now fill in hash table */
2143                 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2144                 for (int i = 0; i < 10; i++)
2145                         E1000_WRITE_REG_ARRAY(hw,
2146                             E1000_RSSRK(0), i, random[i]);
2147
2148                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2149                     E1000_MRQC_RSS_FIELD_IPV4_TCP);
2150                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2151                     E1000_MRQC_RSS_FIELD_IPV6_TCP);
2152                 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP |
2153                     E1000_MRQC_RSS_FIELD_IPV6_UDP);
2154                 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2155                     E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2156
2157                 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2158
2159                 /*
2160                 ** NOTE: Receive Full-Packet Checksum Offload
2161                 ** is mutually exclusive with Multiqueue. However
2162                 ** this is not the same as TCP/IP checksums which
2163                 ** still work.
2164                 */
2165                 rxcsum |= E1000_RXCSUM_PCSD;
2166         } else
2167 #endif
2168         {
2169                 /* Non RSS setup */
2170                 if (ifp->if_capenable & IFCAP_RXCSUM)
2171                         rxcsum |= E1000_RXCSUM_IPPCSE;
2172                 else
2173                         rxcsum &= ~E1000_RXCSUM_TUOFL;
2174         }
2175         E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
2176
2177         /* Setup the Receive Control Register */
2178         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2179         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2180             E1000_RCTL_RDMTS_HALF |
2181             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2182         /* Strip CRC bytes. */
2183         rctl |= E1000_RCTL_SECRC;
2184         /* Make sure VLAN Filters are off */
2185         rctl &= ~E1000_RCTL_VFE;
2186         /* Don't store bad packets */
2187         rctl &= ~E1000_RCTL_SBP;
2188
2189         /* Enable Receives */
2190         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2191
2192         /*
2193          * Setup the HW Rx Head and Tail Descriptor Pointers
2194          *   - needs to be after enable
2195          */
2196         for (i = 0; i < sc->rx_ring_cnt; ++i) {
2197                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2198
2199                 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
2200                 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->sc->num_rx_desc - 1);
2201         }
2202 }
2203
2204 static void
2205 igb_rxeof(struct igb_rx_ring *rxr, int count)
2206 {
2207         struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2208         union e1000_adv_rx_desc *cur;
2209         uint32_t staterr;
2210         int i;
2211
2212         i = rxr->next_to_check;
2213         cur = &rxr->rx_base[i];
2214         staterr = le32toh(cur->wb.upper.status_error);
2215
2216         if ((staterr & E1000_RXD_STAT_DD) == 0)
2217                 return;
2218
2219         while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2220                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2221                 struct mbuf *m = NULL;
2222                 boolean_t eop;
2223
2224                 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2225                 if (eop)
2226                         --count;
2227
2228                 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2229                     !rxr->discard) {
2230                         struct mbuf *mp = rxbuf->m_head;
2231                         uint16_t vlan;
2232                         int len;
2233
2234                         len = le16toh(cur->wb.upper.length);
2235                         if (rxr->sc->hw.mac.type == e1000_i350 &&
2236                             (staterr & E1000_RXDEXT_STATERR_LB))
2237                                 vlan = be16toh(cur->wb.upper.vlan);
2238                         else
2239                                 vlan = le16toh(cur->wb.upper.vlan);
2240
2241                         bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2242                             BUS_DMASYNC_POSTREAD);
2243
2244                         if (igb_newbuf(rxr, i, FALSE) != 0) {
2245                                 ifp->if_iqdrops++;
2246                                 goto discard;
2247                         }
2248
2249                         mp->m_len = len;
2250                         if (rxr->fmp == NULL) {
2251                                 mp->m_pkthdr.len = len;
2252                                 rxr->fmp = mp;
2253                                 rxr->lmp = mp;
2254                         } else {
2255                                 rxr->lmp->m_next = mp;
2256                                 rxr->lmp = rxr->lmp->m_next;
2257                                 rxr->fmp->m_pkthdr.len += len;
2258                         }
2259
2260                         if (eop) {
2261                                 m = rxr->fmp;
2262                                 rxr->fmp = NULL;
2263                                 rxr->lmp = NULL;
2264
2265                                 m->m_pkthdr.rcvif = ifp;
2266                                 ifp->if_ipackets++;
2267
2268                                 if (ifp->if_capenable & IFCAP_RXCSUM)
2269                                         igb_rxcsum(staterr, m);
2270
2271                                 if (staterr & E1000_RXD_STAT_VP) {
2272                                         m->m_pkthdr.ether_vlantag = vlan;
2273                                         m->m_flags |= M_VLANTAG;
2274                                 }
2275
2276 #if 0
2277                                 if (ifp->if_capenable & IFCAP_RSS) {
2278                                         pi = emx_rssinfo(m, &pi0, mrq,
2279                                                          rss_hash, staterr);
2280                                 }
2281 #endif
2282                         }
2283                 } else {
2284                         ifp->if_ierrors++;
2285 discard:
2286                         igb_setup_rxdesc(cur, rxbuf);
2287                         if (!eop)
2288                                 rxr->discard = TRUE;
2289                         else
2290                                 rxr->discard = FALSE;
2291                         if (rxr->fmp != NULL) {
2292                                 m_freem(rxr->fmp);
2293                                 rxr->fmp = NULL;
2294                                 rxr->lmp = NULL;
2295                         }
2296                         m = NULL;
2297                 }
2298
2299                 if (m != NULL)
2300                         ether_input_pkt(ifp, m, NULL);
2301
2302                 /* Advance our pointers to the next descriptor. */
2303                 if (++i == rxr->sc->num_rx_desc)
2304                         i = 0;
2305
2306                 cur = &rxr->rx_base[i];
2307                 staterr = le32toh(cur->wb.upper.status_error);
2308         }
2309         rxr->next_to_check = i;
2310
2311         if (--i < 0)
2312                 i = rxr->sc->num_rx_desc - 1;
2313         E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2314 }
2315
2316
2317 static void
2318 igb_set_vlan(struct igb_softc *sc)
2319 {
2320         struct e1000_hw *hw = &sc->hw;
2321         uint32_t reg;
2322 #if 0
2323         struct ifnet *ifp = sc->arpcom.ac_if;
2324 #endif
2325
2326         if (sc->vf_ifp) {
2327                 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2328                 return;
2329         }
2330
2331         reg = E1000_READ_REG(hw, E1000_CTRL);
2332         reg |= E1000_CTRL_VME;
2333         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2334
2335 #if 0
2336         /* Enable the Filter Table */
2337         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2338                 reg = E1000_READ_REG(hw, E1000_RCTL);
2339                 reg &= ~E1000_RCTL_CFIEN;
2340                 reg |= E1000_RCTL_VFE;
2341                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2342         }
2343 #endif
2344
2345         /* Update the frame size */
2346         E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2347             sc->max_frame_size + VLAN_TAG_SIZE);
2348
2349 #if 0
2350         /* Don't bother with table if no vlans */
2351         if ((adapter->num_vlans == 0) ||
2352             ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2353                 return;
2354         /*
2355         ** A soft reset zero's out the VFTA, so
2356         ** we need to repopulate it now.
2357         */
2358         for (int i = 0; i < IGB_VFTA_SIZE; i++)
2359                 if (adapter->shadow_vfta[i] != 0) {
2360                         if (adapter->vf_ifp)
2361                                 e1000_vfta_set_vf(hw,
2362                                     adapter->shadow_vfta[i], TRUE);
2363                         else
2364                                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2365                                  i, adapter->shadow_vfta[i]);
2366                 }
2367 #endif
2368 }
2369
2370 static void
2371 igb_enable_intr(struct igb_softc *sc)
2372 {
2373         lwkt_serialize_handler_enable(sc->arpcom.ac_if.if_serializer);
2374
2375         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2376                 /* XXX MSI-X should use sc->intr_mask */
2377                 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2378                 E1000_WRITE_REG(&sc->hw, E1000_EIAM, sc->intr_mask);
2379                 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2380                 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2381         } else {
2382                 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2383         }
2384         E1000_WRITE_FLUSH(&sc->hw);
2385 }
2386
2387 static void
2388 igb_disable_intr(struct igb_softc *sc)
2389 {
2390         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2391                 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2392                 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2393         }
2394         E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2395         E1000_WRITE_FLUSH(&sc->hw);
2396
2397         lwkt_serialize_handler_disable(sc->arpcom.ac_if.if_serializer);
2398 }
2399
2400 /*
2401  * Bit of a misnomer, what this really means is
2402  * to enable OS management of the system... aka
2403  * to disable special hardware management features
2404  */
2405 static void
2406 igb_get_mgmt(struct igb_softc *sc)
2407 {
2408         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2409                 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2410                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2411
2412                 /* disable hardware interception of ARP */
2413                 manc &= ~E1000_MANC_ARP_EN;
2414
2415                 /* enable receiving management packets to the host */
2416                 manc |= E1000_MANC_EN_MNG2HOST;
2417                 manc2h |= 1 << 5; /* Mng Port 623 */
2418                 manc2h |= 1 << 6; /* Mng Port 664 */
2419                 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2420                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2421         }
2422 }
2423
2424 /*
2425  * Give control back to hardware management controller
2426  * if there is one.
2427  */
2428 static void
2429 igb_rel_mgmt(struct igb_softc *sc)
2430 {
2431         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2432                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2433
2434                 /* Re-enable hardware interception of ARP */
2435                 manc |= E1000_MANC_ARP_EN;
2436                 manc &= ~E1000_MANC_EN_MNG2HOST;
2437
2438                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2439         }
2440 }
2441
2442 /*
2443  * Sets CTRL_EXT:DRV_LOAD bit.
2444  *
2445  * For ASF and Pass Through versions of f/w this means that
2446  * the driver is loaded.
2447  */
2448 static void
2449 igb_get_hw_control(struct igb_softc *sc)
2450 {
2451         uint32_t ctrl_ext;
2452
2453         if (sc->vf_ifp)
2454                 return;
2455
2456         /* Let firmware know the driver has taken over */
2457         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2458         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2459             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2460 }
2461
2462 /*
2463  * Resets CTRL_EXT:DRV_LOAD bit.
2464  *
2465  * For ASF and Pass Through versions of f/w this means that the
2466  * driver is no longer loaded.
2467  */
2468 static void
2469 igb_rel_hw_control(struct igb_softc *sc)
2470 {
2471         uint32_t ctrl_ext;
2472
2473         if (sc->vf_ifp)
2474                 return;
2475
2476         /* Let firmware taken over control of h/w */
2477         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2478         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2479             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2480 }
2481
2482 static int
2483 igb_is_valid_ether_addr(const uint8_t *addr)
2484 {
2485         uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2486
2487         if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2488                 return FALSE;
2489         return TRUE;
2490 }
2491
2492 /*
2493  * Enable PCI Wake On Lan capability
2494  */
2495 static void
2496 igb_enable_wol(device_t dev)
2497 {
2498         uint16_t cap, status;
2499         uint8_t id;
2500
2501         /* First find the capabilities pointer*/
2502         cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2503
2504         /* Read the PM Capabilities */
2505         id = pci_read_config(dev, cap, 1);
2506         if (id != PCIY_PMG)     /* Something wrong */
2507                 return;
2508
2509         /*
2510          * OK, we have the power capabilities,
2511          * so now get the status register
2512          */
2513         cap += PCIR_POWER_STATUS;
2514         status = pci_read_config(dev, cap, 2);
2515         status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2516         pci_write_config(dev, cap, status, 2);
2517 }
2518
2519 static void
2520 igb_update_stats_counters(struct igb_softc *sc)
2521 {
2522         struct e1000_hw *hw = &sc->hw;
2523         struct e1000_hw_stats *stats;
2524         struct ifnet *ifp = &sc->arpcom.ac_if;
2525
2526         /*
2527          * The virtual function adapter has only a
2528          * small controlled set of stats, do only
2529          * those and return.
2530          */
2531         if (sc->vf_ifp) {
2532                 igb_update_vf_stats_counters(sc);
2533                 return;
2534         }
2535         stats = sc->stats;
2536
2537         if (sc->hw.phy.media_type == e1000_media_type_copper ||
2538             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2539                 stats->symerrs +=
2540                     E1000_READ_REG(hw,E1000_SYMERRS);
2541                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
2542         }
2543
2544         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
2545         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
2546         stats->scc += E1000_READ_REG(hw, E1000_SCC);
2547         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
2548
2549         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
2550         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
2551         stats->colc += E1000_READ_REG(hw, E1000_COLC);
2552         stats->dc += E1000_READ_REG(hw, E1000_DC);
2553         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
2554         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
2555         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
2556
2557         /*
2558          * For watchdog management we need to know if we have been
2559          * paused during the last interval, so capture that here.
2560          */
2561         sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
2562         stats->xoffrxc += sc->pause_frames;
2563         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
2564         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
2565         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
2566         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
2567         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
2568         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
2569         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
2570         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
2571         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
2572         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
2573         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
2574         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
2575
2576         /* For the 64-bit byte counters the low dword must be read first. */
2577         /* Both registers clear on the read of the high dword */
2578
2579         stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
2580             ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
2581         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
2582             ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
2583
2584         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
2585         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
2586         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
2587         stats->roc += E1000_READ_REG(hw, E1000_ROC);
2588         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
2589
2590         stats->tor += E1000_READ_REG(hw, E1000_TORH);
2591         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
2592
2593         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
2594         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
2595         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
2596         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
2597         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
2598         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
2599         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
2600         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
2601         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
2602         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
2603
2604         /* Interrupt Counts */
2605
2606         stats->iac += E1000_READ_REG(hw, E1000_IAC);
2607         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
2608         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
2609         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
2610         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
2611         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
2612         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
2613         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
2614         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
2615
2616         /* Host to Card Statistics */
2617
2618         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
2619         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
2620         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
2621         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
2622         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
2623         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
2624         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
2625         stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
2626             ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
2627         stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
2628             ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
2629         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
2630         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
2631         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
2632
2633         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
2634         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
2635         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
2636         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
2637         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
2638         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
2639
2640         ifp->if_collisions = stats->colc;
2641
2642         /* Rx Errors */
2643         ifp->if_ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
2644             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
2645
2646         /* Tx Errors */
2647         ifp->if_oerrors = stats->ecol + stats->latecol + sc->watchdog_events;
2648
2649         /* Driver specific counters */
2650         sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
2651         sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
2652         sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
2653         sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
2654         sc->packet_buf_alloc_tx =
2655             ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
2656         sc->packet_buf_alloc_rx =
2657             (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
2658 }
2659
2660 static void
2661 igb_vf_init_stats(struct igb_softc *sc)
2662 {
2663         struct e1000_hw *hw = &sc->hw;
2664         struct e1000_vf_stats *stats;
2665
2666         stats = sc->stats;
2667         stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
2668         stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
2669         stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
2670         stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
2671         stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
2672 }
2673
2674 static void
2675 igb_update_vf_stats_counters(struct igb_softc *sc)
2676 {
2677         struct e1000_hw *hw = &sc->hw;
2678         struct e1000_vf_stats *stats;
2679
2680         if (sc->link_speed == 0)
2681                 return;
2682
2683         stats = sc->stats;
2684         UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
2685         UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
2686         UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
2687         UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
2688         UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
2689 }
2690
2691 #ifdef DEVICE_POLLING
2692
2693 static void
2694 igb_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2695 {
2696         struct igb_softc *sc = ifp->if_softc;
2697         uint32_t reg_icr;
2698
2699         ASSERT_SERIALIZED(ifp->if_serializer);
2700
2701         switch (cmd) {
2702         case POLL_REGISTER:
2703                 igb_disable_intr(sc);
2704                 break;
2705
2706         case POLL_DEREGISTER:
2707                 igb_enable_intr(sc);
2708                 break;
2709
2710         case POLL_AND_CHECK_STATUS:
2711                 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2712                 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
2713                         sc->hw.mac.get_link_status = 1;
2714                         igb_update_link_status(sc);
2715                 }
2716                 /* FALL THROUGH */
2717         case POLL_ONLY:
2718                 if (ifp->if_flags & IFF_RUNNING) {
2719                         igb_rxeof(&sc->rx_rings[0], count);
2720
2721                         igb_txeof(&sc->tx_rings[0]);
2722                         if (!ifq_is_empty(&ifp->if_snd))
2723                                 if_devstart(ifp);
2724                 }
2725                 break;
2726         }
2727 }
2728
2729 #endif /* DEVICE_POLLING */
2730
2731 static void
2732 igb_intr(void *xsc)
2733 {
2734         struct igb_softc *sc = xsc;
2735         struct ifnet *ifp = &sc->arpcom.ac_if;
2736         uint32_t eicr;
2737
2738         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2739
2740         eicr = E1000_READ_REG(&sc->hw, E1000_EICR);
2741
2742         if (eicr == 0)
2743                 return;
2744
2745         if (ifp->if_flags & IFF_RUNNING) {
2746                 if (eicr & sc->rx_rings[0].rx_intr_mask)
2747                         igb_rxeof(&sc->rx_rings[0], -1);
2748
2749                 if (eicr & sc->tx_rings[0].tx_intr_mask) {
2750                         igb_txeof(&sc->tx_rings[0]);
2751                         if (!ifq_is_empty(&ifp->if_snd))
2752                                 if_devstart(ifp);
2753                 }
2754         }
2755
2756         if (eicr & E1000_EICR_OTHER) {
2757                 uint32_t icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2758
2759                 /* Link status change */
2760                 if (icr & E1000_ICR_LSC) {
2761                         sc->hw.mac.get_link_status = 1;
2762                         igb_update_link_status(sc);
2763                 }
2764         }
2765
2766         /*
2767          * Reading EICR has the side effect to clear interrupt mask,
2768          * so all interrupts need to be enabled here.
2769          */
2770         E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2771 }
2772
2773 static void
2774 igb_shared_intr(void *xsc)
2775 {
2776         struct igb_softc *sc = xsc;
2777         struct ifnet *ifp = &sc->arpcom.ac_if;
2778         uint32_t reg_icr;
2779
2780         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2781
2782         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2783
2784         /* Hot eject?  */
2785         if (reg_icr == 0xffffffff)
2786                 return;
2787
2788         /* Definitely not our interrupt.  */
2789         if (reg_icr == 0x0)
2790                 return;
2791
2792         if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
2793                 return;
2794
2795         if (ifp->if_flags & IFF_RUNNING) {
2796                 igb_rxeof(&sc->rx_rings[0], -1);
2797
2798                 igb_txeof(&sc->tx_rings[0]);
2799                 if (!ifq_is_empty(&ifp->if_snd))
2800                         if_devstart(ifp);
2801         }
2802
2803         /* Link status change */
2804         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
2805                 sc->hw.mac.get_link_status = 1;
2806                 igb_update_link_status(sc);
2807         }
2808
2809         if (reg_icr & E1000_ICR_RXO)
2810                 sc->rx_overruns++;
2811 }
2812
2813 static int
2814 igb_txctx_pullup(struct igb_tx_ring *txr, struct mbuf **m0)
2815 {
2816         struct mbuf *m = *m0;
2817         struct ether_header *eh;
2818         int len;
2819
2820         txr->ctx_try_pullup++;
2821
2822         len = ETHER_HDR_LEN + IGB_IPVHL_SIZE;
2823
2824         if (__predict_false(!M_WRITABLE(m))) {
2825                 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2826                         txr->ctx_drop1++;
2827                         m_freem(m);
2828                         *m0 = NULL;
2829                         return ENOBUFS;
2830                 }
2831                 eh = mtod(m, struct ether_header *);
2832
2833                 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2834                         len += EVL_ENCAPLEN;
2835
2836                 if (m->m_len < len) {
2837                         txr->ctx_drop2++;
2838                         m_freem(m);
2839                         *m0 = NULL;
2840                         return ENOBUFS;
2841                 }
2842                 return 0;
2843         }
2844
2845         if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2846                 txr->ctx_pullup1++;
2847                 m = m_pullup(m, ETHER_HDR_LEN);
2848                 if (m == NULL) {
2849                         txr->ctx_pullup1_failed++;
2850                         *m0 = NULL;
2851                         return ENOBUFS;
2852                 }
2853                 *m0 = m;
2854         }
2855         eh = mtod(m, struct ether_header *);
2856
2857         if (eh->ether_type == htons(ETHERTYPE_VLAN))
2858                 len += EVL_ENCAPLEN;
2859
2860         if (m->m_len < len) {
2861                 txr->ctx_pullup2++;
2862                 m = m_pullup(m, len);
2863                 if (m == NULL) {
2864                         txr->ctx_pullup2_failed++;
2865                         *m0 = NULL;
2866                         return ENOBUFS;
2867                 }
2868                 *m0 = m;
2869         }
2870         return 0;
2871 }
2872
2873 static int
2874 igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp)
2875 {
2876         bus_dma_segment_t segs[IGB_MAX_SCATTER];
2877         bus_dmamap_t map;
2878         struct igb_tx_buf *tx_buf, *tx_buf_mapped;
2879         union e1000_adv_tx_desc *txd = NULL;
2880         struct mbuf *m_head = *m_headp;
2881         uint32_t olinfo_status = 0, cmd_type_len = 0, cmd_rs = 0;
2882         int maxsegs, nsegs, i, j, error, last = 0;
2883         uint32_t hdrlen = 0;
2884
2885         if (m_head->m_len < IGB_TXCSUM_MINHL &&
2886             ((m_head->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) ||
2887              (m_head->m_flags & M_VLANTAG))) {
2888                 /*
2889                  * Make sure that ethernet header and ip.ip_hl are in
2890                  * contiguous memory, since if TXCSUM or VLANTAG is
2891                  * enabled, later TX context descriptor's setup need
2892                  * to access ip.ip_hl.
2893                  */
2894                 error = igb_txctx_pullup(txr, m_headp);
2895                 if (error) {
2896                         KKASSERT(*m_headp == NULL);
2897                         return error;
2898                 }
2899                 m_head = *m_headp;
2900         }
2901
2902         /* Set basic descriptor constants */
2903         cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
2904         cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
2905         if (m_head->m_flags & M_VLANTAG)
2906                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2907
2908         /*
2909          * Map the packet for DMA.
2910          */
2911         tx_buf = &txr->tx_buf[txr->next_avail_desc];
2912         tx_buf_mapped = tx_buf;
2913         map = tx_buf->map;
2914
2915         maxsegs = txr->tx_avail - IGB_TX_RESERVED;
2916         KASSERT(maxsegs >= txr->spare_desc, ("not enough spare TX desc\n"));
2917         if (maxsegs > IGB_MAX_SCATTER)
2918                 maxsegs = IGB_MAX_SCATTER;
2919
2920         error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
2921             segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2922         if (error) {
2923                 if (error == ENOBUFS)
2924                         txr->sc->mbuf_defrag_failed++;
2925                 else
2926                         txr->sc->no_tx_dma_setup++;
2927
2928                 m_freem(*m_headp);
2929                 *m_headp = NULL;
2930                 return error;
2931         }
2932         bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
2933
2934         m_head = *m_headp;
2935
2936 #if 0
2937         /*
2938          * Set up the context descriptor:
2939          * used when any hardware offload is done.
2940          * This includes CSUM, VLAN, and TSO. It
2941          * will use the first descriptor.
2942          */
2943         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
2944                 if (igb_tso_setup(txr, m_head, &hdrlen)) {
2945                         cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2946                         olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2947                         olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2948                 } else
2949                         return (ENXIO);
2950         } else if (igb_tx_ctx_setup(txr, m_head))
2951                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2952 #else
2953         if (igb_txctx(txr, m_head)) {
2954                 olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
2955                 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
2956                         olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
2957                 txr->tx_nsegs++;
2958         }
2959 #endif
2960
2961         txr->tx_nsegs += nsegs;
2962         if (txr->tx_nsegs >= txr->intr_nsegs) {
2963                 /*
2964                  * Report Status (RS) is turned on every intr_nsegs
2965                  * descriptors (roughly).
2966                  */
2967                 txr->tx_nsegs = 0;
2968                 cmd_rs = E1000_ADVTXD_DCMD_RS;
2969         }
2970
2971         /* Calculate payload length */
2972         olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
2973             << E1000_ADVTXD_PAYLEN_SHIFT);
2974
2975         /* 82575 needs the queue index added */
2976         if (txr->sc->hw.mac.type == e1000_82575)
2977                 olinfo_status |= txr->me << 4;
2978
2979         /* Set up our transmit descriptors */
2980         i = txr->next_avail_desc;
2981         for (j = 0; j < nsegs; j++) {
2982                 bus_size_t seg_len;
2983                 bus_addr_t seg_addr;
2984
2985                 tx_buf = &txr->tx_buf[i];
2986                 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
2987                 seg_addr = segs[j].ds_addr;
2988                 seg_len = segs[j].ds_len;
2989
2990                 txd->read.buffer_addr = htole64(seg_addr);
2991                 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
2992                 txd->read.olinfo_status = htole32(olinfo_status);
2993                 last = i;
2994                 if (++i == txr->sc->num_tx_desc)
2995                         i = 0;
2996                 tx_buf->m_head = NULL;
2997         }
2998
2999         KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
3000         txr->next_avail_desc = i;
3001         txr->tx_avail -= nsegs;
3002
3003         tx_buf->m_head = m_head;
3004         tx_buf_mapped->map = tx_buf->map;
3005         tx_buf->map = map;
3006
3007         /*
3008          * Last Descriptor of Packet needs End Of Packet (EOP)
3009          */
3010         txd->read.cmd_type_len |= htole32(E1000_ADVTXD_DCMD_EOP | cmd_rs);
3011
3012         /*
3013          * Advance the Transmit Descriptor Tail (TDT), this tells the E1000
3014          * that this frame is available to transmit.
3015          */
3016         E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), i);
3017         ++txr->tx_packets;
3018
3019         return 0;
3020 }
3021
3022 static void
3023 igb_start(struct ifnet *ifp)
3024 {
3025         struct igb_softc *sc = ifp->if_softc;
3026         struct igb_tx_ring *txr = &sc->tx_rings[0];
3027         struct mbuf *m_head;
3028
3029         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3030
3031         if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
3032                 return;
3033
3034         if (!sc->link_active) {
3035                 ifq_purge(&ifp->if_snd);
3036                 return;
3037         }
3038
3039         if (!IGB_IS_NOT_OACTIVE(txr))
3040                 igb_txeof(txr);
3041
3042         while (!ifq_is_empty(&ifp->if_snd)) {
3043                 if (IGB_IS_OACTIVE(txr)) {
3044                         ifp->if_flags |= IFF_OACTIVE;
3045                         /* Set watchdog on */
3046                         ifp->if_timer = 5;
3047                         break;
3048                 }
3049
3050                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3051                 if (m_head == NULL)
3052                         break;
3053
3054                 if (igb_encap(txr, &m_head)) {
3055                         ifp->if_oerrors++;
3056                         continue;
3057                 }
3058
3059                 /* Send a copy of the frame to the BPF listener */
3060                 ETHER_BPF_MTAP(ifp, m_head);
3061         }
3062 }
3063
3064 static void
3065 igb_watchdog(struct ifnet *ifp)
3066 {
3067         struct igb_softc *sc = ifp->if_softc;
3068         struct igb_tx_ring *txr = &sc->tx_rings[0];
3069
3070         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3071
3072         /*
3073          * If flow control has paused us since last checking
3074          * it invalidates the watchdog timing, so dont run it.
3075          */
3076         if (sc->pause_frames) {
3077                 sc->pause_frames = 0;
3078                 ifp->if_timer = 5;
3079                 return;
3080         }
3081
3082         if_printf(ifp, "Watchdog timeout -- resetting\n");
3083         if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3084             E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3085             E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3086         if_printf(ifp, "TX(%d) desc avail = %d, "
3087             "Next TX to Clean = %d\n",
3088             txr->me, txr->tx_avail, txr->next_to_clean);
3089
3090         ifp->if_oerrors++;
3091         sc->watchdog_events++;
3092
3093         igb_init(sc);
3094         if (!ifq_is_empty(&ifp->if_snd))
3095                 if_devstart(ifp);
3096 }
3097
3098 static void
3099 igb_set_eitr(struct igb_softc *sc)
3100 {
3101         uint32_t itr = 0;
3102
3103         if (sc->intr_rate > 0) {
3104                 if (sc->hw.mac.type == e1000_82575) {
3105                         itr = 1000000000 / 256 / sc->intr_rate;
3106                         /*
3107                          * NOTE:
3108                          * Document is wrong on the 2 bits left shift
3109                          */
3110                 } else {
3111                         itr = 1000000 / sc->intr_rate;
3112                         itr <<= 2;
3113                 }
3114                 itr &= 0x7FFC;
3115         }
3116         if (sc->hw.mac.type == e1000_82575)
3117                 itr |= itr << 16;
3118         else
3119                 itr |= E1000_EITR_CNT_IGNR;
3120         E1000_WRITE_REG(&sc->hw, E1000_EITR(0), itr);
3121 }
3122
3123 static int
3124 igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3125 {
3126         struct igb_softc *sc = (void *)arg1;
3127         struct ifnet *ifp = &sc->arpcom.ac_if;
3128         int error, intr_rate;
3129
3130         intr_rate = sc->intr_rate;
3131         error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3132         if (error || req->newptr == NULL)
3133                 return error;
3134         if (intr_rate < 0)
3135                 return EINVAL;
3136
3137         ifnet_serialize_all(ifp);
3138
3139         sc->intr_rate = intr_rate;
3140         if (ifp->if_flags & IFF_RUNNING)
3141                 igb_set_eitr(sc);
3142
3143         ifnet_deserialize_all(ifp);
3144
3145         if (bootverbose)
3146                 if_printf(ifp, "Interrupt rate set to %d/sec\n", sc->intr_rate);
3147         return 0;
3148 }
3149
3150 static int
3151 igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3152 {
3153         struct igb_softc *sc = (void *)arg1;
3154         struct ifnet *ifp = &sc->arpcom.ac_if;
3155         struct igb_tx_ring *txr = &sc->tx_rings[0];
3156         int error, nsegs;
3157
3158         nsegs = txr->intr_nsegs;
3159         error = sysctl_handle_int(oidp, &nsegs, 0, req);
3160         if (error || req->newptr == NULL)
3161                 return error;
3162         if (nsegs <= 0)
3163                 return EINVAL;
3164
3165         ifnet_serialize_all(ifp);
3166
3167         if (nsegs >= sc->num_tx_desc - txr->oact_lo_desc ||
3168             nsegs >= txr->oact_hi_desc - IGB_MAX_SCATTER) {
3169                 error = EINVAL;
3170         } else {
3171                 error = 0;
3172                 txr->intr_nsegs = nsegs;
3173         }
3174
3175         ifnet_deserialize_all(ifp);
3176
3177         return error;
3178 }
3179
3180 static void
3181 igb_init_intr(struct igb_softc *sc)
3182 {
3183         if (sc->flags & IGB_FLAG_SHARED_INTR)
3184                 igb_set_eitr(sc);
3185         else
3186                 igb_init_unshared_intr(sc);
3187 }
3188
3189 static void
3190 igb_init_unshared_intr(struct igb_softc *sc)
3191 {
3192         struct e1000_hw *hw = &sc->hw;
3193         const struct igb_rx_ring *rxr;
3194         const struct igb_tx_ring *txr;
3195         uint32_t ivar, index;
3196         int i;
3197
3198         /*
3199          * Enable extended mode
3200          */
3201         if (sc->hw.mac.type != e1000_82575) {
3202                 E1000_WRITE_REG(hw, E1000_GPIE, E1000_GPIE_NSICR);
3203         } else {
3204                 uint32_t tmp;
3205
3206                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
3207                 tmp |= E1000_CTRL_EXT_IRCA;
3208                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
3209         }
3210
3211         /*
3212          * Map TX/RX interrupts to EICR
3213          */
3214         switch (sc->hw.mac.type) {
3215         case e1000_82580:
3216         case e1000_i350:
3217         case e1000_vfadapt:
3218         case e1000_vfadapt_i350:
3219                 /* RX entries */
3220                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3221                         rxr = &sc->rx_rings[i];
3222
3223                         index = i >> 1;
3224                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3225
3226                         if (i & 1) {
3227                                 ivar &= 0xff00ffff;
3228                                 ivar |=
3229                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3230                         } else {
3231                                 ivar &= 0xffffff00;
3232                                 ivar |=
3233                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3234                         }
3235                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3236                 }
3237                 /* TX entries */
3238                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3239                         txr = &sc->tx_rings[i];
3240
3241                         index = i >> 1;
3242                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3243
3244                         if (i & 1) {
3245                                 ivar &= 0x00ffffff;
3246                                 ivar |=
3247                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3248                         } else {
3249                                 ivar &= 0xffff00ff;
3250                                 ivar |=
3251                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3252                         }
3253                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3254                 }
3255                 /* Clear unused IVAR_MISC */
3256                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
3257                 break;
3258
3259         case e1000_82576:
3260                 /* RX entries */
3261                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3262                         rxr = &sc->rx_rings[i];
3263
3264                         index = i & 0x7; /* Each IVAR has two entries */
3265                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3266
3267                         if (i < 8) {
3268                                 ivar &= 0xffffff00;
3269                                 ivar |=
3270                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3271                         } else {
3272                                 ivar &= 0xff00ffff;
3273                                 ivar |=
3274                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3275                         }
3276                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3277                 }
3278                 /* TX entries */
3279                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3280                         txr = &sc->tx_rings[i];
3281
3282                         index = i & 0x7; /* Each IVAR has two entries */
3283                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3284
3285                         if (i < 8) {
3286                                 ivar &= 0xffff00ff;
3287                                 ivar |=
3288                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3289                         } else {
3290                                 ivar &= 0x00ffffff;
3291                                 ivar |=
3292                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3293                         }
3294                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3295                 }
3296                 /* Clear unused IVAR_MISC */
3297                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
3298                 break;
3299
3300         case e1000_82575:
3301                 /*
3302                  * Enable necessary interrupt bits.
3303                  *
3304                  * The name of the register is confusing; in addition to
3305                  * configuring the first vector of MSI-X, it also configures
3306                  * which bits of EICR could be set by the hardware even when
3307                  * MSI or line interrupt is used; it thus controls interrupt
3308                  * generation.  It MUST be configured explicitly; the default
3309                  * value mentioned in the datasheet is wrong: RX queue0 and
3310                  * TX queue0 are NOT enabled by default.
3311                  */
3312                 E1000_WRITE_REG(&sc->hw, E1000_MSIXBM(0), sc->intr_mask);
3313                 break;
3314
3315         default:
3316                 break;
3317         }
3318
3319         /*
3320          * Configure interrupt moderation
3321          */
3322         igb_set_eitr(sc);
3323 }
3324
3325 static int
3326 igb_setup_intr(struct igb_softc *sc)
3327 {
3328         struct ifnet *ifp = &sc->arpcom.ac_if;
3329         int error, i;
3330
3331         /*
3332          * Setup interrupt mask
3333          */
3334         for (i = 0; i < sc->tx_ring_cnt; ++i)
3335                 igb_setup_tx_intr(&sc->tx_rings[i]);
3336         for (i = 0; i < sc->rx_ring_cnt; ++i)
3337                 igb_setup_rx_intr(&sc->rx_rings[i]);
3338
3339         sc->intr_mask = E1000_EICR_OTHER;
3340         for (i = 0; i < sc->rx_ring_cnt; ++i)
3341                 sc->intr_mask |= sc->rx_rings[i].rx_intr_mask;
3342         for (i = 0; i < sc->tx_ring_cnt; ++i)
3343                 sc->intr_mask |= sc->tx_rings[i].tx_intr_mask;
3344
3345         if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
3346                 int unshared;
3347
3348                 unshared = device_getenv_int(sc->dev, "irq.unshared", 0);
3349                 if (!unshared) {
3350                         sc->flags |= IGB_FLAG_SHARED_INTR;
3351                         if (bootverbose)
3352                                 device_printf(sc->dev, "IRQ shared\n");
3353                 } else if (bootverbose) {
3354                         device_printf(sc->dev, "IRQ unshared\n");
3355                 }
3356         }
3357
3358         error = bus_setup_intr(sc->dev, sc->intr_res, INTR_MPSAFE,
3359             (sc->flags & IGB_FLAG_SHARED_INTR) ? igb_shared_intr : igb_intr,
3360             sc, &sc->intr_tag, ifp->if_serializer);
3361         if (error) {
3362                 device_printf(sc->dev, "Failed to register interrupt handler");
3363                 return error;
3364         }
3365
3366         ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
3367         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3368
3369         return 0;
3370 }
3371
3372 static void
3373 igb_setup_tx_intr(struct igb_tx_ring *txr)
3374 {
3375         if (txr->sc->hw.mac.type == e1000_82575) {
3376                 txr->tx_intr_bit = 0;   /* unused */
3377                 switch (txr->me) {
3378                 case 0:
3379                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE0;
3380                         break;
3381                 case 1:
3382                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE1;
3383                         break;
3384                 case 2:
3385                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE2;
3386                         break;
3387                 case 3:
3388                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE3;
3389                         break;
3390                 default:
3391                         panic("unsupported # of TX ring, %d\n", txr->me);
3392                 }
3393         } else {
3394                 txr->tx_intr_bit = 0;   /* XXX */
3395                 txr->tx_intr_mask = 1 << txr->tx_intr_bit;
3396         }
3397 }
3398
3399 static void
3400 igb_setup_rx_intr(struct igb_rx_ring *rxr)
3401 {
3402         if (rxr->sc->hw.mac.type == e1000_82575) {
3403                 rxr->rx_intr_bit = 0;   /* unused */
3404                 switch (rxr->me) {
3405                 case 0:
3406                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE0;
3407                         break;
3408                 case 1:
3409                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE1;
3410                         break;
3411                 case 2:
3412                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE2;
3413                         break;
3414                 case 3:
3415                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE3;
3416                         break;
3417                 default:
3418                         panic("unsupported # of RX ring, %d\n", rxr->me);
3419                 }
3420         } else {
3421                 rxr->rx_intr_bit = 1;   /* XXX */
3422                 rxr->rx_intr_mask = 1 << rxr->rx_intr_bit;
3423         }
3424 }