2 * Copyright 1996 Massachusetts Institute of Technology
4 * Permission to use, copy, modify, and distribute this software and
5 * its documentation for any purpose and without fee is hereby
6 * granted, provided that both the above copyright notice and this
7 * permission notice appear in all copies, that both the above
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9 * supporting documentation, and that the name of M.I.T. not be used
10 * in advertising or publicity pertaining to distribution of the
11 * software without specific, written prior permission. M.I.T. makes
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13 * purpose. It is provided "as is" without express or implied
16 * THIS SOFTWARE IS PROVIDED BY M.I.T. ``AS IS''. M.I.T. DISCLAIMS
17 * ALL EXPRESS OR IMPLIED WARRANTIES WITH REGARD TO THIS SOFTWARE,
18 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT
20 * SHALL M.I.T. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
24 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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26 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * $FreeBSD: src/sys/pci/ide_pci.c,v 1.42 2000/01/29 16:59:53 peter Exp $
32 #include <sys/param.h>
33 #include <sys/systm.h>
35 #include <sys/malloc.h>
36 #include <sys/kernel.h>
40 #include <i386/isa/wdreg.h>
42 #include <pc98/pc98/pc98.h>
44 #include <i386/isa/isa.h>
46 #include <i386/isa/isa_device.h>
48 #include <pci/pcivar.h>
49 #include <pci/pcireg.h>
50 #include <pci/ide_pcireg.h>
53 #define MIN(a,b) (((a)<(b))?(a):(b))
56 #define PROMISE_ULTRA33 0x4d33105a
57 #define CMD640B_PCI_ID 0x06401095
59 struct ide_pci_cookie; /* structs vendor_fns, ide_pci_cookie are recursive */
62 int (*vendor_dmainit) /* initialize DMA controller and drive */
63 (struct ide_pci_cookie *cookie,
65 int (*wdcmd)(int, void *),
68 void (*vendor_status) /* prints off DMA timing info */
69 (struct ide_pci_cookie *cookie);
73 * XXX the fact that this list keeps all kinds of info on PCI controllers
74 * is pretty grotty-- much of this should be replaced by a proper integration
75 * of PCI probes into the wd driver.
76 * XXX if we're going to support native-PCI controllers, we also need to
77 * keep the address of the IDE control block register, which is something wd.c
78 * needs to know, which is why this info is in the wrong place.
81 struct ide_pci_cookie {
82 LIST_ENTRY(ide_pci_cookie) le;
84 int ctlr; /* controller 0/1 on PCI IDE interface */
86 int iobase_bm; /* SFF-8038 control registers */
90 struct ide_pci_prd *prd;
94 struct ide_pci_softc {
95 LIST_HEAD(, ide_pci_cookie) cookies;
99 generic_dmainit(struct ide_pci_cookie *cookie,
101 int (*wdcmd)(int, void *),
105 generic_status(struct ide_pci_cookie *cookie);
108 sis_5591_dmainit(struct ide_pci_cookie *cookie,
110 int (*wdcmd)(int, void *),
114 sis_5591_status(struct ide_pci_cookie *cookie);
117 via_571_status(struct ide_pci_cookie *cookie);
120 via_571_dmainit(struct ide_pci_cookie *cookie,
122 int (*wdcmd)(int, void *),
126 acer_status(struct ide_pci_cookie *cookie);
129 acer_dmainit(struct ide_pci_cookie *cookie,
131 int (*wdcmd)(int, void *),
135 intel_piix_dump_drive(char *ctlr,
145 intel_piix_status(struct ide_pci_cookie *cookie);
147 intel_piix_dmainit(struct ide_pci_cookie *cookie,
149 int (*wdcmd)(int, void *),
152 static struct ide_pci_cookie *
153 mkcookie(int iobase_wd,
159 struct vendor_fns *vp,
164 static void ide_pci_attach(pcici_t tag, int unit);
165 static void *ide_pci_candma(int, int, int);
166 static int ide_pci_dmainit(void *,
168 int (*)(int, void *),
171 static int ide_pci_dmaverify(void *, char *, u_long, int);
172 static int ide_pci_dmasetup(void *, char *, u_long, int);
173 static void ide_pci_dmastart(void *);
174 static int ide_pci_dmadone(void *);
175 static int ide_pci_status(void *);
176 static int ide_pci_iobase(void *xcp);
177 static int ide_pci_altiobase(void *xcp);
179 static struct ide_pci_softc softc;
181 static int ide_pci_softc_cookies_initted = 0;
183 extern struct isa_driver wdcdriver;
186 * PRD_ALLOC_SIZE should be something that will not be allocated across a 64k
188 * PRD_MAX_SEGS is defined to be the maximum number of segments required for
189 * a transfer on an IDE drive, for an xfer that is linear in virtual memory.
190 * PRD_BUF_SIZE is the size of the buffer needed for a PRD table.
192 #define PRD_ALLOC_SIZE PAGE_SIZE
193 #define PRD_MAX_SEGS ((256 * 512 / PAGE_SIZE) + 1)
194 #define PRD_BUF_SIZE PRD_MAX_SEGS * 8
196 static void *prdbuf = 0;
197 static void *prdbuf_next = 0;
200 * Hardware specific IDE controller code. All vendor-specific code
201 * for handling IDE timing and other chipset peculiarities should be
208 * nnn_mode() return the highest valid mode, or -1 if the mode class is
213 pio_mode(struct wdparams *wp)
215 if ((wp->wdp_atavalid & 2) == 2) {
216 if ((wp->wdp_eidepiomodes & 2) == 2) return 4;
217 if ((wp->wdp_eidepiomodes & 1) == 1) return 3;
224 dma_mode(struct wdparams *wp)
226 /* XXX not quite sure how to verify validity on this field */
231 mwdma_mode(struct wdparams *wp)
234 * XXX technically, using wdp_atavalid to test for validity of
235 * this field is not quite correct
237 if ((wp->wdp_atavalid & 2) == 2) {
238 if ((wp->wdp_dmamword & 4) == 4) return 2;
239 if ((wp->wdp_dmamword & 2) == 2) return 1;
240 if ((wp->wdp_dmamword & 1) == 1) return 0;
246 udma_mode(struct wdparams *wp)
248 if ((wp->wdp_atavalid & 4) == 4) {
249 if ((wp->wdp_udmamode & 4) == 4) return 2;
250 if ((wp->wdp_udmamode & 2) == 2) return 1;
251 if ((wp->wdp_udmamode & 1) == 1) return 0;
257 /* Generic busmastering PCI-IDE */
260 generic_dmainit(struct ide_pci_cookie *cookie,
262 int(*wdcmd)(int, void *),
266 * punt on the whole timing issue by looking for either a
267 * drive programmed for both PIO4 and mDMA2 (which use similar
268 * timing) or a drive in an UltraDMA mode (hopefully all
269 * controllers have separate timing for UDMA). one hopes that if
270 * the drive's DMA mode has been configured by the BIOS, the
271 * controller's has also.
273 * XXX there are examples where this approach is now known to be
274 * broken, at least on systems based on Intel chipsets.
277 if ((pio_mode(wp) >= 4 && mwdma_mode(wp) >= 2) ||
278 (udma_mode(wp) >= 2)) {
279 printf("ide_pci: generic_dmainit %04x:%d: warning, IDE controller timing not set\n",
282 /* If we're here, then this controller is most likely not set
283 for UDMA, even if the drive may be. Make the drive wise
286 if(!wdcmd(WDDMA_MDMA2, wdinfo))
287 printf("generic_dmainit: could not set multiword DMA mode!\n");
291 printf("pio_mode: %d, mwdma_mode(wp): %d, udma_mode(wp): %d\n",
292 pio_mode(wp), mwdma_mode(wp), udma_mode(wp));
298 generic_status(struct ide_pci_cookie *cookie)
300 printf("generic_status: no PCI IDE timing info available\n");
303 static struct vendor_fns vs_generic =
309 /* VIA Technologies "82C571" PCI-IDE controller core */
312 via_571_status(struct ide_pci_cookie *cookie)
322 iobase_wd = cookie->iobase_wd;
325 iobase_bm = cookie->iobase_bm;
329 unitno = ctlr * 2 + unit;
331 for (i=0; i<5; i++) {
332 word40[i] = pci_conf_read(tag, i * 4 + 0x40);
336 printf("via_571_status: Primary IDE prefetch/postwrite %s/%s\n",
337 word40[0] & 0x8000 ? "enabled" : "disabled",
338 word40[0] & 0x4000 ? "enabled" : "disabled");
340 printf("via_571_status: Secondary IDE prefetch/postwrite %s/%s\n",
341 word40[0] & 0x2000 ? "enabled" : "disabled",
342 word40[0] & 0x1000 ? "enabled" : "disabled");
344 printf("via_571_status: busmaster status read retry %s\n",
345 (word40[1] & 0x08) ? "enabled" : "disabled");
348 printf("via_571_status: %s drive %d data setup=%d active=%d recovery=%d\n",
349 unitno < 2 ? "primary" : "secondary",
351 ((u_int)(word40[3] >> ((3 - unitno) * 2)) & 3) + 1,
352 ((u_int)(word40[2] >> (((3 - unitno) * 8) + 4)) & 0x0f) + 1,
353 ((u_int)(word40[2] >> ((3 - unitno) * 8)) & 0x0f) + 1);
356 printf("via_571_status: primary ctrl active=%d recovery=%d\n",
357 ((u_int)(word40[3] >> 28) & 0x0f) + 1,
358 ((u_int)(word40[2] >> 24) & 0x0f) + 1);
360 printf("via_571_status: secondary ctrl active=%d recovery=%d\n",
361 ((u_int)(word40[3] >> 20) & 0x0f) + 1,
362 ((u_int)(word40[2] >> 16) & 0x0f) + 1);
368 foo = word40[4] >> ((3 - unitno) * 8);
369 printf("via_571_status: %s drive %d udma method=%d enable=%d PIOmode=%d cycle=%d\n",
370 i < 2 ? "primary" : "secondary",
380 * XXX timing values set here are only good for 30/33MHz buses; should deal
381 * with slower ones too (BTW: you overclock-- you lose)
385 via_571_dmainit(struct ide_pci_cookie *cookie,
387 int(*wdcmd)(int, void *),
393 pci_revision = pci_conf_read(cookie->tag, PCI_CLASS_REG) &
396 unitno = cookie->ctlr * 2 + cookie->unit;
398 /* If it's a UDMA drive on a '590, set it up */
400 * XXX the revision number we check for is of dubious validity.
401 * it's extracted from the AMD 645 datasheet.
403 if (pci_revision >= 1 && udma_mode(wp) >= 2) {
404 unsigned int word50, mask, new;
405 word50 = pci_conf_read(cookie->tag, 0x50);
407 /* UDMA enable by SET FEATURES, DMA cycles, cycle time 2T */
408 mask = 0xe3000000 >> (unitno * 8);
409 new = 0x40000000 >> (unitno * 8);
414 pci_conf_write(cookie->tag, 0x50, word50);
417 * With the '590, drive configuration should come *after* the
418 * controller configuration, to make sure the controller sees
419 * the SET FEATURES command and does the right thing.
421 /* Set UDMA mode 2 on drive */
423 printf("via_571_dmainit: setting ultra DMA mode 2\n");
424 if (!wdcmd(WDDMA_UDMA2, wdinfo)) {
425 printf("via_571_dmainit: setting DMA mode failed\n");
430 via_571_status(cookie);
435 /* otherwise, try and program it for MW DMA mode 2 */
436 else if (mwdma_mode(wp) >= 2 && pio_mode(wp) >= 4) {
439 /* Set multiword DMA mode 2 on drive */
441 printf("via_571_dmainit: setting multiword DMA mode 2\n");
442 if (!wdcmd(WDDMA_MDMA2, wdinfo)) {
443 printf("via_571_dmainit: setting DMA mode failed\n");
447 /* Configure the controller appropriately for MWDMA mode 2 */
449 workword = pci_conf_read(cookie->tag, 0x40);
452 * enable prefetch/postwrite-- XXX may cause problems
455 workword |= 0xc000 >> (cookie->ctlr * 2);
457 /* FIFO configurations-- equal split, threshold 1/2 */
458 workword &= 0x90ffffff;
459 workword |= 0x2a000000;
461 pci_conf_write(cookie->tag, 0x40, workword);
463 workword = pci_conf_read(cookie->tag, 0x44);
465 /* enable status read retry */
468 /* enable FIFO flush on interrupt and end of sector */
469 workword &= 0xff0cffff;
470 workword |= 0x00f00000;
471 pci_conf_write(cookie->tag, 0x44, workword);
473 workword = pci_conf_read(cookie->tag, 0x48);
474 /* set Mode2 timing */
475 workword &= ~(0xff000000 >> (unitno * 8));
476 workword |= 0x31000000 >> (unitno * 8);
477 pci_conf_write(cookie->tag, 0x48, workword);
479 /* set sector size */
480 pci_conf_write(cookie->tag, cookie->ctlr ? 0x68 : 0x60, 0x200);
483 via_571_status(cookie);
492 static struct vendor_fns vs_via_571 =
498 /* Cyrix Cx5530 Courtesy of Whistle Communications */
501 * Verify that controller can handle a dma request for cp. Should
502 * not affect any hardware or driver state.
503 * Special version for 5530 that allows only transfers on 16 byte boundaries.(!)
504 * (Yes the Cyrix 5530 can only UDMA to cache-line boundaries.(bleh!))
505 * Luckily nearly all disk IO is to kernel bufers which are page alligned.
506 * They may fix this in some other version of the chip, but it's in the latest
507 * at this time (Jan 1999).
510 cyrix_5530_dmaverify(void *xcp, char *vaddr, u_long count, int dir)
515 * check for nonaligned or odd-length Stuff
517 badfu = ((unsigned int)vaddr & 0xf) || (count & 0xf);
520 printf("ide_pci: dmaverify odd vaddr or length, ");
521 printf("vaddr = %p length = %08lx\n", (void *)vaddr, count);
528 * XXX Unit number handling may be broken in the Cx5530 modules.
529 * It has only been checked with a single drive.
530 * 12MByte/Sec transfer rates were seen with Quantum Fireball drives
531 * with negligable CPU usage.
534 cyrix_5530_status(struct ide_pci_cookie *cookie)
545 iobase_wd = cookie->iobase_wd;
548 iobase_bm = cookie->iobase_bm;
552 unitno = ctlr * 2 + unit;
554 PIO_config = inl(iobase_bm + (unit * 0x10) + 0x20);
555 DMA_config = inl(iobase_bm + (unit * 0x10) + 0x24);
558 printf("cyrix_5530_status: %s:%u IDE PIO cfg: 0x%08lx\n",
559 (ctlr ? "Secondary" : "Primary"), unit, PIO_config);
560 printf("cyrix_5530_status: %s:%u IDE DMA cfg: 0x%08lx\n",
561 (ctlr ? "Secondary" : "Primary"), unit, DMA_config);
565 * XXX timing values set here are only good for 30/33MHz buses; should deal
566 * with slower ones too (BTW: you overclock-- you lose)
570 cyrix_5530_dmainit(struct ide_pci_cookie *cookie,
572 int(*wdcmd)(int, void *),
583 /*cookie->unit = 0; */ /* XXX */
585 pci_revision = pci_conf_read(cookie->tag, PCI_CLASS_REG) &
588 unitno = cookie->ctlr * 2 + unit;
589 iobase_bm = cookie->iobase_bm;
591 printf("Setting using 0x%x\n", iobase_bm);
592 if ((cookie->ctlr == 0) && (unit == 0)) /* XXX */
593 outb(iobase_bm + (unit * 0x10) + BMISTA_PORT, 0xe6);
594 /* If it's a UDMA drive on a '5530, set it up */
596 * depending on what the drive can do,
597 * set the correct modes,
599 printf("wd%d: mw=0x%x, pio=0x%x, pcirev=0x%lx, udma=0x%x\n",
601 mwdma_mode(wp), pio_mode(wp),
602 pci_revision, udma_mode(wp));
603 if (/* pci_revision >= 1 && */ udma_mode(wp) >= 0) {
604 switch(udma_mode(wp)) {
607 drivemode = WDDMA_UDMA0;
610 default: /* newer modes not supported */
614 * XXX The 5530 can do mode 2 but if you do use it, it will block all
615 * access to the PCI bus (and thus the ISA bus, PICs, PIT, etc. etc.) until the
616 * transfer is complete. Mode 2 swamps the 5530 so much it can't really cope
617 * with any other operations. Therefore, use mode 1 for drives that can
618 * do mode 2 (or more). (FALL THROUGH)
623 drivemode = WDDMA_UDMA2;
629 drivemode = WDDMA_UDMA1;
634 * With the Cx5530, drive configuration
635 * should come *after* the controller configuration,
636 * to make sure the controller sees
637 * the command and does the right thing.
639 /* Set UDMA mode on drive */
641 printf("cyrix_5530_dmainit: set UDMA mode %d\n", mode);
642 outl(iobase_bm+0x24 + (unit * 16), regval);
643 if (!wdcmd(drivemode, wdinfo)) {
644 printf("cyrix_5530_dmainit: setting DMA mode failed\n");
649 cyrix_5530_status(cookie);
654 /* otherwise, try and program it for MW DMA mode 2 */
655 else if (mwdma_mode(wp) >= 0 && pio_mode(wp) >= 4) {
657 switch(mwdma_mode(wp)) {
660 drivemode = WDDMA_MDMA0;
665 drivemode = WDDMA_MDMA1;
668 default: /* newer modes not supported */
671 drivemode = WDDMA_MDMA2;
676 /* Set multiword DMA mode 2 on drive */
678 printf("cyrix_5530_dmainit: multiword DMA mode %d\n",
680 if (!wdcmd(drivemode, wdinfo)) {
681 printf("cyrix_5530_dmainit: setting DMA mode failed\n");
685 /* Configure the controller appropriately for MWDMA mode */
687 outl(iobase_bm + 0x24 + (unit * 16), regval);
690 cyrix_5530_status(cookie);
696 * Always set the PIO mode values.
698 switch(pio_mode(wp)) {
701 drivemode = WDDMA_MDMA0;
706 drivemode = WDDMA_MDMA1;
711 drivemode = WDDMA_MDMA1;
716 drivemode = WDDMA_MDMA1;
719 default: /* newer modes not supported */
722 drivemode = WDDMA_MDMA2;
727 outl(iobase_bm + 0x20 + (unit * 16), regval);
728 printf("cyrix_5530_dmainit: setting PIO mode %d\n", mode);
733 static struct vendor_fns vs_cyrix_5530 =
741 promise_status(struct ide_pci_cookie *cookie)
745 u_int32_t port0_command, port0_altstatus;
746 u_int32_t port1_command, port1_altstatus;
749 u_int32_t lat_and_interrupt;
750 u_int32_t drivetiming;
754 port0_command = pci_conf_read(tag, 0x10);
755 port0_altstatus = pci_conf_read(tag, 0x14);
756 port1_command = pci_conf_read(tag, 0x18);
757 port1_altstatus = pci_conf_read(tag, 0x1c);
759 dma_block = pci_conf_read(tag, 0x20);
760 lat_and_interrupt = pci_conf_read(tag, 0x3c);
762 printf("promise_status: port0: 0x%lx, port0_alt: 0x%lx, port1: 0x%lx, port1_alt: 0x%lx\n",
763 (u_long)port0_command, (u_long)port0_altstatus, (u_long)port1_command,
764 (u_long)port1_altstatus);
766 "promise_status: dma control blk address: 0x%lx, int: %d, irq: %d\n",
767 (u_long)dma_block, (u_int)(lat_and_interrupt >> 8) & 0xff,
768 (u_int)lat_and_interrupt & 0xff);
771 drivetiming = pci_conf_read(tag, 0x60 + i * 4);
772 printf("drivebits%d-%d: %b\n", i, i+1, drivetiming,
773 "\020\05Prefetch\06Iordy\07Errdy\010Sync\025DmaW\026DmaR");
774 pa = drivetiming & 0xf;
775 pb = (drivetiming >> 8) & 0x1f;
776 mb = (drivetiming >> 13) & 0x7;
777 mc = (drivetiming >> 16) & 0xf;
778 printf("drivetiming%d: pa: 0x%x, pb: 0x%x, mb: 0x%x, mc: 0x%x\n",
781 drivetiming = pci_conf_read(tag, 0x60 + (i + 1) * 4);
782 pa = drivetiming & 0xf;
783 pb = (drivetiming >> 8) & 0x1f;
784 mb = (drivetiming >> 13) & 0x7;
785 mc = (drivetiming >> 16) & 0xf;
786 printf("drivetiming%d: pa: 0x%x, pb: 0x%x, mb: 0x%x, mc: 0x%x\n",
787 i + 1, pa, pb, mb, mc);
791 static struct vendor_fns vs_promise =
797 /* Intel PIIX, PIIX3, and PIIX4 IDE controller subfunctions */
799 intel_piix_dump_drive(char *ctlr,
817 printf("intel_piix_status: %s %s sample = %d, %s recovery = %d\n",
820 5 - ((sitre && drive) ?
821 ((word44 >> 2) & 3) :
822 ((word40 >> 12) & 3)),
824 4 - ((sitre && drive) ?
825 ((word44 >> 0) & 3) :
826 ((word40 >> 8) & 3)));
828 word40 >>= (drive * 4);
829 printf("intel_piix_status: %s %s fastDMAonly %s, pre/post %s,\n\
830 intel_piix_status: IORDY sampling %s,\n\
831 intel_piix_status: fast PIO %s%s\n",
833 (drive == 0) ? "master" : "slave",
834 (word40 & 8) ? "enabled" : "disabled",
835 (word40 & 4) ? "enabled" : "disabled",
836 (word40 & 2) ? "enabled" : "disabled",
837 (word40 & 1) ? "enabled" : "disabled",
838 ((word40 & 9) == 9) ? " (overridden by fastDMAonly)" : "" );
841 printf("intel_piix_status: UltraDMA %s, CT/RP = %d/%d\n",
842 word48 ? "enabled": "disabled",
848 intel_piix_status(struct ide_pci_cookie *cookie)
856 u_long word40, word44, word48;
859 iobase_wd = cookie->iobase_wd;
861 iobase_bm = cookie->iobase_bm;
866 word40 = pci_conf_read(tag, 0x40);
867 word44 = pci_conf_read(tag, 0x44);
868 word48 = pci_conf_read(tag, 0x48);
871 * XXX will not be right for the *next* generation of upward-compatible
872 * intel IDE controllers...
874 is_piix4 = pci_conf_read(tag, PCI_CLASS_REG) == 0x71118086;
876 sitre = word40 & 0x4000;
878 switch (ctlr * 2 + unit) {
880 intel_piix_dump_drive("primary",
890 intel_piix_dump_drive("primary",
900 intel_piix_dump_drive("secondary",
903 (word40 >> 16) & 0xffff,
904 (word44 >> 4) & 0x0f,
910 intel_piix_dump_drive("secondary",
913 (word40 >> 16) & 0xffff,
914 (word44 >> 4) & 0x0f,
920 printf("intel_piix_status: bad drive or controller number\n");
925 * XXX timing values set hereare only good for 30/33MHz buses; should deal
926 * with slower ones too (BTW: you overclock-- you lose)
930 intel_piix_dmainit(struct ide_pci_cookie *cookie,
932 int(*wdcmd)(int, void *),
936 /* If it's a UDMA drive and a PIIX4, set it up */
937 if (cookie->type == 0x71118086 && udma_mode(wp) >= 2) {
938 /* Set UDMA mode 2 on controller */
939 int unitno, mask, new;
942 printf("intel_piix_dmainit: setting ultra DMA mode 2\n");
944 if (!wdcmd(WDDMA_UDMA2, wdinfo)) {
945 printf("intel_piix_dmainit: setting DMA mode failed\n");
949 unitno = cookie->ctlr * 2 + cookie->unit;
951 mask = (1 << unitno) + (3 << (16 + unitno * 4));
952 new = (1 << unitno) + (2 << (16 + unitno * 4));
954 pci_conf_write(cookie->tag, 0x48,
955 (pci_conf_read(cookie->tag, 0x48) & ~mask) | new);
958 intel_piix_status(cookie);
962 * if it's an 82371FB, which can't do independent programming of
963 * drive timing, we punt; we're not going to fuss with trying to
964 * coordinate timing modes between drives. if this is you, get a
965 * new motherboard. or contribute patches :)
967 * we do now at least see if the modes set are OK to use. this should
968 * satisfy the majority of people, with mwdma mode2 drives.
970 else if (cookie->type == 0x12308086)
974 /* can drive do PIO 4 and MW DMA 2? */
975 if (!(mwdma_mode(wp) >= 2 && pio_mode(wp) >= 4))
978 word40 = pci_conf_read(cookie->tag, 0x40);
979 word40 >>= cookie->ctlr * 16;
981 /* Check for timing config usable for DMA on controller */
982 if (!((word40 & 0x3300) == 0x2300 &&
983 ((word40 >> (cookie->unit * 4)) & 1) == 1))
986 /* Set multiword DMA mode 2 on drive */
988 printf("intel_piix_dmainit: setting multiword DMA mode 2\n");
989 if (!wdcmd(WDDMA_MDMA2, wdinfo)) {
990 printf("intel_piix_dmainit: setting DMA mode failed\n");
996 /* otherwise, treat it as a PIIX3 and program it for MW DMA mode 2 */
997 else if (mwdma_mode(wp) >= 2 && pio_mode(wp) >= 4) {
998 u_long mask40, mask44, new40, new44;
1001 * If SITRE is not set, set it and copy the
1002 * appropriate bits into the secondary registers. Do
1003 * both controllers at once.
1005 if (((pci_conf_read(cookie->tag, 0x40) >> (16 * cookie->ctlr))
1007 unsigned int word40, word44;
1009 word40 = pci_conf_read(cookie->tag, 0x40);
1011 /* copy bits to secondary register */
1012 word44 = pci_conf_read(cookie->tag, 0x44);
1014 * I've got a Biostar motherboard with Award
1015 * BIOS that sets SITRE and secondary timing
1016 * on one controller but not the other.
1019 if ((word40 & 0x4000) == 0) {
1021 word44 |= ((word40 & 0x3000) >> 10) |
1022 ((word40 & 0x0300) >> 8);
1024 if ((word40 & 0x40000000) == 0) {
1026 word44 |= ((word40 & 0x30000000) >> 22) |
1027 ((word40 & 0x03000000) >> 20);
1030 word40 |= 0x40004000;
1032 pci_conf_write(cookie->tag, 0x40, word40);
1033 pci_conf_write(cookie->tag, 0x44, word44);
1036 /* Set multiword DMA mode 2 on drive */
1038 printf("intel_piix_dmainit: setting multiword DMA mode 2\n");
1040 if (!wdcmd(WDDMA_MDMA2, wdinfo)) {
1041 printf("intel_piix_dmainit: setting DMA mode failed\n");
1046 * backward compatible hardware leaves us with such
1047 * twisted masses of software (aka twiddle the
1048 * extremely weird register layout on a PIIX3, setting
1049 * PIO mode 4 and MWDMA mode 2)
1051 if (cookie->unit == 0) {
1070 pci_conf_write(cookie->tag, 0x40,
1071 (pci_conf_read(cookie->tag, 0x40) & ~mask40) | new40);
1072 pci_conf_write(cookie->tag, 0x44,
1073 (pci_conf_read(cookie->tag, 0x44) & ~mask44) | new44);
1076 intel_piix_status(cookie);
1082 static struct vendor_fns vs_intel_piix =
1090 acer_status(struct ide_pci_cookie *cookie) {
1091 /* XXX does not do anything right now */
1095 acer_dmainit(struct ide_pci_cookie *cookie,
1096 struct wdparams *wp,
1097 int(*wdcmd)(int, void *),
1100 /* Acer Aladdin DMA setup code. UDMA looks to be sinfully easy to set
1101 on this thing - just one register. */
1103 u_long word54 = pci_conf_read(cookie->tag, 0x54);
1105 /* Set the default Acer FIFO settings (0x55 = 13-word depth and
1106 slave operation mode 1) */
1110 /* Is this drive UDMA? Set it up if so... */
1111 if(udma_mode(wp) >= 2) {
1112 /* This is really easy to do. Just write 0xa (enable
1113 UDMA mode with 2T timing) into the word at the right
1115 word54 |= (0xA << (16 + (cookie->ctlr * 8) + (cookie->unit * 4)));
1117 /* Now set the drive for UDMA2. */
1118 if(!wdcmd(WDDMA_UDMA2, wdinfo)) {
1119 printf("acer_dmainit: could not set UDMA2 mode on wdc%d:%d!\n", cookie->ctlr, cookie->unit);
1123 /* Write the new config into the registers. I'm not
1124 sure if I'm doing this in the right order. */
1126 pci_conf_write(cookie->tag, 0x54, word54);
1128 } else if(mwdma_mode(wp) >= 2 && pio_mode(wp) >=4) {
1131 /* Otherwise, we're already set for regular DMA. */
1133 if(!wdcmd(WDDMA_MDMA2, wdinfo)) {
1134 printf("acer_dmainit: could not set MWDMA2 mode on wdc%d:%d!\n",
1135 cookie->ctlr, cookie->unit);
1144 static struct vendor_fns vs_acer =
1153 sis_5591_status(struct ide_pci_cookie *cookie)
1165 iobase_wd = cookie->iobase_wd;
1166 unit = cookie->unit;
1167 ctlr = cookie->ctlr;
1168 iobase_bm = cookie->iobase_bm;
1170 type = cookie->type;
1172 unitno = ctlr * 2 + unit;
1174 for (i=0; i<5; i++) {
1175 word40[i] = pci_conf_read(tag, i * 4 + 0x40);
1178 DRTC = word40[ctlr] >> (16 * unit);
1179 DATC = word40[ctlr] >> (8 + 16*unit);
1182 if ((word40[4] & 0x80000) == 0) {
1183 val = word40[2] & 0xf;
1188 printf ("SiS 5591 status: CRTC %d PCICLK, ", val);
1189 val = (word40[2] >> 8) & 0x7;
1194 printf ("CATC %d PCICLK, applies to all IDE devices\n", val);
1196 printf ("SiS 5591 status: CRTC and CATC timings are per device, taken from DRTC and DATC\n");
1198 printf ("SiS 5591 status: burst cycles %s, fast post write control %s\n",
1199 ((word40[2] >> 16) & 0x80) ? "enabled" : "disabled",
1200 ((word40[2] >> 16) & 0x20) ? "enabled" : "disabled");
1208 printf ("SiS 5591 status: %s drive %d DRTC %d PCICLK,",
1209 unitno < 2 ? "primary" : "secondary",
1217 printf (" DATC %d PCICLK\n", val);
1218 printf ("SiS 5591 status: %s drive %d Ultra DMA %s",
1219 unitno < 2 ? "primary" : "secondary",
1221 (DATC & 0x80) ? "disabled\n" : "enabled");
1222 if ((DATC & 0x80) == 0)
1223 printf (", %d PCICLK data out\n", ((DATC >> 5) & 0x3) + 1);
1224 printf ("SiS 5591 status: %s drive %d postwrite %s, prefetch %s prefetch count is %d\n",
1225 unitno < 2 ? "primary" : "secondary",
1227 ((word40[2] >> (28 + unitno)) & 1) ? "enabled" : "disabled",
1228 ((word40[2] >> (24 + unitno)) & 1) ? "enabled" : "disabled",
1229 (word40[3] >> (16 * ctlr)) & 0xffff);
1230 printf ("SiS 5591 status: %s drive %d has%s been configured for DMA\n",
1231 unitno < 2 ? "primary" : "secondary",
1233 (inb(iobase_bm + BMISTA_PORT) & ((unit == 0) ? BMISTA_DMA0CAP : BMISTA_DMA1CAP)) ?
1238 sis_5591_dmainit(struct ide_pci_cookie *cookie,
1239 struct wdparams *wp,
1240 int(*wdcmd)(int, void *),
1244 unsigned int workword, new, mask;
1250 unit = cookie->unit;
1251 ctlr = cookie->ctlr;
1252 iobase_bm = cookie->iobase_bm;
1255 unitno = ctlr * 2 + unit;
1257 if (udma_mode(wp) >= 2) {
1258 workword = pci_conf_read(tag, ctlr * 4 + 0x40);
1260 /* These settings are a little arbitrary. They're taken from my
1261 * system, where the BIOS has already set the values, but where
1262 * we don't detect that we're initialized because the
1263 * BMISTA_DMA?CAP values aren't set by the BIOS.
1264 * 0x8000 turns on UDMA
1265 * 0x2000 sets UDMA cycle time to 2 PCI clocks for data out
1266 * 0x0300 sets DATC to 3 PCI clocks
1267 * 0x0001 sets DRTC to 1 PCI clock
1280 pci_conf_write(tag, ctlr * 4 + 0x40, workword);
1282 outb(iobase_bm + BMISTA_PORT,
1283 (inb(iobase_bm + BMISTA_PORT) | ((unit == 0) ? BMISTA_DMA0CAP : BMISTA_DMA1CAP)));
1286 printf("SiS 5591 dmainit: %s drive %d setting ultra DMA mode 2\n",
1287 unitno < 2 ? "primary" : "secondary",
1289 r = wdcmd(WDDMA_UDMA2, wdinfo);
1291 printf("SiS 5591 dmainit: %s drive %d setting DMA mode failed\n",
1292 unitno < 2 ? "primary" : "secondary",
1298 sis_5591_status(cookie);
1304 /* otherwise, try and program it for MW DMA mode 2 */
1305 else if (mwdma_mode(wp) >= 2 && pio_mode(wp) >= 4) {
1306 workword = pci_conf_read(tag, ctlr * 4 + 0x40);
1308 /* These settings are a little arbitrary. They're taken from my
1309 * system, where the BIOS has already set the values, but where
1310 * we don't detect that we're initialized because the
1311 * BMISTA_DMA?CAP values aren't set by the BIOS.
1312 * 0x0300 sets DATC to 3 PCI clocks
1313 * 0x0001 sets DRTC to 1 PCI clock
1326 pci_conf_write(tag, ctlr * 4 + 0x40, workword);
1328 outb(iobase_bm + BMISTA_PORT,
1329 (inb(iobase_bm + BMISTA_PORT) | ((unit == 0) ? BMISTA_DMA0CAP : BMISTA_DMA1CAP)));
1331 /* Set multiword DMA mode 2 on drive */
1333 printf("SiS 5591 dmainit: %s drive %d setting multiword DMA mode 2\n",
1334 unitno < 2 ? "primary" : "secondary",
1336 r = wdcmd(WDDMA_MDMA2, wdinfo);
1338 printf("SiS 5591 dmainit: %s drive %d setting DMA mode failed\n",
1339 unitno < 2 ? "primary" : "secondary",
1345 sis_5591_status(cookie);
1353 static struct vendor_fns vs_sis_5591 =
1359 /* Generic SFF-8038i code-- all code below here, except for PCI probes,
1360 * more or less conforms to the SFF-8038i spec as extended for PCI.
1361 * There should be no code that goes beyond that feature set below.
1364 /* XXX mkcookie is overloaded with too many parameters */
1366 static struct ide_pci_cookie *
1367 mkcookie(int iobase_wd,
1373 struct vendor_fns *vp,
1376 struct ide_pci_cookie *cp;
1378 cp = malloc(sizeof *cp, M_DEVBUF, M_NOWAIT);
1381 cp->iobase_wd = iobase_wd;
1386 cp->iobase_bm = iobase_bm;
1387 cp->altiobase_wd = altiobase_wd;
1388 bcopy(vp, &cp->vs, sizeof(struct vendor_fns));
1391 prdbuf = malloc(PRD_ALLOC_SIZE, M_DEVBUF, M_NOWAIT);
1396 if (((int)prdbuf >> PAGE_SHIFT) ^
1397 (((int)prdbuf + PRD_ALLOC_SIZE - 1) >> PAGE_SHIFT)) {
1398 printf("ide_pci: prdbuf straddles page boundary, no DMA\n");
1400 FREE(prdbuf, M_DEVBUF);
1404 prdbuf_next = prdbuf;
1406 if (((char *)prdbuf_next + PRD_BUF_SIZE) >
1407 ((char *)prdbuf + PRD_ALLOC_SIZE)) {
1408 printf("ide_pci: mkcookie %04x:%d: no more space for PRDs, no DMA\n",
1414 cp->prd = prdbuf_next;
1415 (char *)prdbuf_next += PRD_BUF_SIZE;
1417 LIST_INSERT_HEAD(&softc.cookies, cp, le);
1422 ide_pci_probe(pcici_t tag, pcidi_t type)
1426 data = pci_conf_read(tag, PCI_CLASS_REG);
1428 if ((data & PCI_CLASS_MASK) == PCI_CLASS_MASS_STORAGE &&
1429 ((data & PCI_SUBCLASS_MASK) == 0x00010000 ||
1430 ((data & PCI_SUBCLASS_MASK) == 0x00040000))) {
1431 if (type == 0x71118086)
1432 return ("Intel PIIX4 Bus-master IDE controller");
1433 if (type == 0x70108086)
1434 return ("Intel PIIX3 Bus-master IDE controller");
1435 if (type == 0x12308086)
1436 return ("Intel PIIX Bus-master IDE controller");
1437 if (type == PROMISE_ULTRA33)
1438 return ("Promise Ultra/33 IDE controller");
1439 if (type == 0x05711106)
1440 return ("VIA 82C586x (Apollo) Bus-master IDE controller");
1441 if (type == 0x01021078)
1442 return ("Cyrix 5530 Bus-master IDE controller");
1443 if (type == 0x522910b9)
1444 return ("Acer Aladdin IV/V (M5229) Bus-master IDE controller");
1445 if (type == 0x55131039)
1446 return ("SiS 5591 Bus-master IDE Controller");
1447 if (type == CMD640B_PCI_ID)
1448 return "CMD 640B IDE controller";
1450 return ("PCI IDE controller (busmaster capable)");
1452 return ("PCI IDE controller (not busmaster capable)");
1458 ide_pci_attach(pcici_t tag, int unit)
1460 u_long class = 0, cmd;
1461 int bmista_1, bmista_2;
1462 int iobase_wd_1, iobase_wd_2, iobase_bm_1, iobase_bm_2;
1463 int altiobase_wd_1, altiobase_wd_2;
1464 struct vendor_fns *vp;
1466 struct ide_pci_cookie *cookie;
1471 /* set up vendor-specific stuff */
1472 type = pci_conf_read(tag, PCI_ID_REG);
1474 if (type == CMD640B_PCI_ID) {
1479 if (type != PROMISE_ULTRA33) {
1480 /* is it busmaster capable? bail if not */
1481 class = pci_conf_read(tag, PCI_CLASS_REG);
1482 if (!(class & 0x8000)) {
1486 /* is it enabled and is busmastering turned on? */
1487 cmd = pci_conf_read(tag, PCI_COMMAND_STATUS_REG);
1488 if ((cmd & 5) != 5) {
1497 /* Intel PIIX, PIIX3, PIIX4 */
1498 vp = &vs_intel_piix;
1502 /* VIA Apollo chipset family */
1506 case PROMISE_ULTRA33:
1507 /* Promise controllers */
1511 case 0x01021078: /* cyrix 5530 */
1512 printf("cyrix 5530\n");
1513 vp = &vs_cyrix_5530;
1515 case 0x522910B9: /* Acer Aladdin IV/V (M5229) */
1518 case 0x55131039: /* SiS 5591 */
1522 /* everybody else */
1527 if (type != PROMISE_ULTRA33) {
1528 if ((class & 0x100) == 0) {
1529 iobase_wd_1 = IO_WD1;
1530 altiobase_wd_1 = iobase_wd_1 + wd_altsts;
1532 iobase_wd_1 = pci_conf_read(tag, 0x10) & 0xfffc;
1533 altiobase_wd_1 = pci_conf_read(tag, 0x14) & 0xfffc;
1536 if ((class & 0x400) == 0) {
1537 iobase_wd_2 = IO_WD2;
1538 altiobase_wd_2 = iobase_wd_2 + wd_altsts;
1540 iobase_wd_2 = pci_conf_read(tag, 0x18) & 0xfffc;
1541 altiobase_wd_2 = pci_conf_read(tag, 0x1c) & 0xfffc;
1544 iobase_wd_1 = pci_conf_read(tag, 0x10) & 0xfffc;
1545 altiobase_wd_1 = pci_conf_read(tag, 0x14) & 0xfffc;
1546 iobase_wd_2 = pci_conf_read(tag, 0x18) & 0xfffc;
1547 altiobase_wd_2 = pci_conf_read(tag, 0x1c) & 0xfffc;
1550 iobase_bm_1 = pci_conf_read(tag, 0x20) & 0xfffc;
1551 if (iobase_bm_1 == 0) {
1552 printf("ide_pci: BIOS has not configured busmaster"
1553 "I/O address,\n ide_pci: giving up\n");
1556 iobase_bm_2 = iobase_bm_1 + SFF8038_CTLR_1;
1558 wddma[unit].wdd_candma = ide_pci_candma;
1559 wddma[unit].wdd_dmainit = ide_pci_dmainit;
1560 if (type == 0x01021078 /*CYRIX_5530*/)
1561 wddma[unit].wdd_dmaverify = cyrix_5530_dmaverify;
1563 wddma[unit].wdd_dmaverify = ide_pci_dmaverify;
1564 wddma[unit].wdd_dmaprep = ide_pci_dmasetup;
1565 wddma[unit].wdd_dmastart = ide_pci_dmastart;
1566 wddma[unit].wdd_dmadone = ide_pci_dmadone;
1567 wddma[unit].wdd_dmastatus = ide_pci_status;
1568 wddma[unit].wdd_iobase = ide_pci_iobase;
1569 wddma[unit].wdd_altiobase = ide_pci_altiobase;
1571 bmista_1 = inb(iobase_bm_1 + BMISTA_PORT);
1572 bmista_2 = inb(iobase_bm_2 + BMISTA_PORT);
1574 if (!ide_pci_softc_cookies_initted) {
1575 LIST_INIT(&softc.cookies);
1576 ide_pci_softc_cookies_initted = 1;
1579 if (iobase_wd_1 != 0) {
1580 cookie = mkcookie(iobase_wd_1,
1589 vp->vendor_status(cookie);
1590 cookie = mkcookie(iobase_wd_1,
1599 vp->vendor_status(cookie);
1601 bmista_1 = inb(iobase_bm_1 + BMISTA_PORT);
1602 bmista_2 = inb(iobase_bm_2 + BMISTA_PORT);
1603 printf("ide_pci: busmaster 0 status: %02x from port: %08x\n",
1604 bmista_1, iobase_bm_1+BMISTA_PORT);
1606 if (bmista_1 & BMISTA_DMA0CAP)
1607 printf("ide_pci: ide0:0 has been configured for DMA by BIOS\n");
1608 if (bmista_1 & BMISTA_DMA1CAP)
1609 printf("ide_pci: ide0:1 has been configured for DMA by BIOS\n");
1613 if (iobase_wd_2 != 0) {
1614 cookie = mkcookie(iobase_wd_2,
1623 vp->vendor_status(cookie);
1624 cookie = mkcookie(iobase_wd_2,
1633 vp->vendor_status(cookie);
1635 bmista_1 = inb(iobase_bm_1 + BMISTA_PORT);
1636 bmista_2 = inb(iobase_bm_2 + BMISTA_PORT);
1637 printf("ide_pci: busmaster 1 status: %02x from port: %08x\n",
1638 bmista_2, iobase_bm_2+BMISTA_PORT);
1640 if (bmista_2 & BMISTA_DMA0CAP)
1641 printf("ide_pci: ide1:0 has been configured for DMA by BIOS\n");
1642 if (bmista_2 & BMISTA_DMA1CAP)
1643 printf("ide_pci: ide1:1 has been configured for DMA by BIOS\n");
1648 static u_long ide_pci_count;
1650 static struct pci_device ide_pci_device = {
1658 COMPAT_PCI_DRIVER(ide_pci, ide_pci_device);
1661 * Return a cookie if we may be able to do DMA on the specified
1662 * (iobase_wd, ctlr, unit).
1665 ide_pci_candma(int iobase_wd, int ctlr, int unit)
1667 struct ide_pci_cookie *cp;
1669 cp = softc.cookies.lh_first;
1671 if (cp->ctlr == ctlr && cp->unit == unit &&
1672 ((iobase_wd == 0) || (cp->iobase_wd == iobase_wd)))
1674 cp = cp->le.le_next;
1681 * Initialize controller and drive for DMA operation, including timing modes.
1682 * Uses data passed from the wd driver and a callback function to initialize
1683 * timing modes on the drive.
1686 ide_pci_dmainit(void *cookie,
1687 struct wdparams *wp,
1688 int(*wdcmd)(int, void *),
1691 struct ide_pci_cookie *cp = cookie;
1693 * If the controller status indicates that DMA is configured already,
1694 * we flounce happily away
1696 if (inb(cp->iobase_bm + BMISTA_PORT) &
1697 ((cp->unit == 0) ? BMISTA_DMA0CAP : BMISTA_DMA1CAP))
1700 /* We take a stab at it with device-dependent code */
1701 return(cp->vs.vendor_dmainit(cp, wp, wdcmd, wdinfo));
1705 * Verify that controller can handle a dma request for cp. Should
1706 * not affect any hardware or driver state.
1709 ide_pci_dmaverify(void *xcp, char *vaddr, u_long count, int dir)
1714 * check for nonaligned or odd-length Stuff
1716 badfu = ((unsigned int)vaddr & 1) || (count & 1);
1719 printf("ide_pci: dmaverify odd vaddr or length, ");
1720 printf("vaddr = %p length = %08lx\n", (void *)vaddr, count);
1727 * Set up DMA for cp. It is the responsibility of the caller
1728 * to ensure that the controller is idle before this routine
1732 ide_pci_dmasetup(void *xcp, char *vaddr, u_long vcount, int dir)
1734 struct ide_pci_cookie *cp = xcp;
1735 struct ide_pci_prd *prd;
1738 u_long prd_base, prd_count;
1739 u_long nbase, ncount, nend;
1749 iobase_bm = cp->iobase_bm;
1752 printf("ide_pci: dmasetup 0-length transfer, ");
1753 printf("vaddr = %p length = %08lx\n", (void *)vaddr, count);
1757 /* Generate first PRD entry, which may be non-aligned. */
1759 firstpage = PAGE_SIZE - ((uintptr_t)vaddr & PAGE_MASK);
1761 prd_base = vtophys(vaddr);
1762 prd_count = MIN(count, firstpage);
1768 * Step through virtual pages.
1769 * Note that it is not worth trying to coalesce pages that are
1770 * next to each other physically, and some DMA engines (e.g.
1771 * Cyrix Cx5530) actually blow up if you do.
1774 nbase = vtophys(vaddr);
1775 ncount = MIN(count, PAGE_SIZE);
1776 nend = nbase + ncount;
1778 prd[i].prd_base = prd_base;
1779 prd[i].prd_count = (prd_count & 0xffff);
1781 if (i >= PRD_MAX_SEGS) {
1782 printf("wd82371: too many segments in PRD table\n");
1791 /* Write last PRD entry. */
1792 prd[i].prd_base = prd_base;
1793 prd[i].prd_count = (prd_count & 0xffff) | PRD_EOT_BIT;
1795 /* Set up PRD base register */
1796 outl(iobase_bm + BMIDTP_PORT, vtophys(prd));
1798 /* Set direction of transfer */
1799 outb(iobase_bm + BMICOM_PORT, (dir == B_READ) ? BMICOM_READ_WRITE : 0);
1801 /* Clear interrupt and error bits */
1802 outb(iobase_bm + BMISTA_PORT,
1803 (inb(iobase_bm + BMISTA_PORT)
1804 | (BMISTA_INTERRUPT | BMISTA_DMA_ERROR)));
1810 ide_pci_dmastart(void *xcp)
1812 struct ide_pci_cookie *cp = xcp;
1815 iobase_bm = cp->iobase_bm;
1817 outb(iobase_bm + BMICOM_PORT,
1818 inb(iobase_bm + BMICOM_PORT) | BMICOM_STOP_START);
1823 ide_pci_dmadone(void *xcp)
1825 struct ide_pci_cookie *cp = xcp;
1826 int iobase_bm, status;
1828 status = ide_pci_status(xcp);
1829 iobase_bm = cp->iobase_bm;
1831 outb(iobase_bm + BMICOM_PORT,
1832 inb(iobase_bm + BMICOM_PORT) & ~BMICOM_STOP_START);
1838 ide_pci_status(void *xcp)
1840 int iobase_bm, status, bmista;
1843 iobase_bm = ((struct ide_pci_cookie *)xcp)->iobase_bm;
1845 bmista = inb(iobase_bm + BMISTA_PORT);
1847 if (bmista & BMISTA_INTERRUPT)
1848 status |= WDDS_INTERRUPT;
1849 if (bmista & BMISTA_DMA_ERROR)
1850 status |= WDDS_ERROR;
1851 if (bmista & BMISTA_DMA_ACTIVE)
1852 status |= WDDS_ACTIVE;
1857 ide_pci_altiobase(void *xcp)
1859 struct ide_pci_cookie *cp = xcp;
1863 return cp->altiobase_wd;
1868 ide_pci_iobase(void *xcp)
1870 struct ide_pci_cookie *cp = xcp;
1874 return cp->iobase_wd;